1 #ifndef _INTEL_DRIVER_H_
2 #define _INTEL_DRIVER_H_
11 #include <intel_bufmgr.h>
13 #include <va/va_backend.h>
14 #include "va_backend_compat.h"
16 #include "intel_compiler.h"
18 #define BATCH_SIZE 0x80000
19 #define BATCH_RESERVED 0x10
21 #define CMD_MI (0x0 << 29)
22 #define CMD_2D (0x2 << 29)
23 #define CMD_3D (0x3 << 29)
25 #define MI_NOOP (CMD_MI | 0)
27 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
28 #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
30 #define MI_FLUSH (CMD_MI | (0x4 << 23))
31 #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
33 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
34 #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
36 #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
37 #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
38 #define XY_COLOR_BLT_WRITE_RGB (1 << 20)
39 #define XY_COLOR_BLT_DST_TILED (1 << 11)
41 #define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05)
44 #define BR13_8 (0x0 << 24)
45 #define BR13_565 (0x1 << 24)
46 #define BR13_1555 (0x2 << 24)
47 #define BR13_8888 (0x3 << 24)
49 #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
50 #define CMD_PIPE_CONTROL_CS_STALL (1 << 20)
51 #define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
52 #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
53 #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
54 #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
55 #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
56 #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
57 #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
58 #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
59 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
60 #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
61 #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
62 #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
63 #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
64 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
67 struct intel_batchbuffer;
69 #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
70 #define MIN(a, b) ((a) < (b) ? (a) : (b))
71 #define MAX(a, b) ((a) > (b) ? (a) : (b))
72 #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
78 #define SET_BLOCKED_SIGSET() do { \
80 sigfillset(&bl_mask); \
81 sigdelset(&bl_mask, SIGFPE); \
82 sigdelset(&bl_mask, SIGILL); \
83 sigdelset(&bl_mask, SIGSEGV); \
84 sigdelset(&bl_mask, SIGBUS); \
85 sigdelset(&bl_mask, SIGKILL); \
86 pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
89 #define RESTORE_BLOCKED_SIGSET() do { \
90 pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
93 #define PPTHREAD_MUTEX_LOCK() do { \
94 SET_BLOCKED_SIGSET(); \
95 pthread_mutex_lock(&intel->ctxmutex); \
98 #define PPTHREAD_MUTEX_UNLOCK() do { \
99 pthread_mutex_unlock(&intel->ctxmutex); \
100 RESTORE_BLOCKED_SIGSET(); \
103 #define WARN_ONCE(...) do { \
104 static int g_once = 1; \
107 printf("WARNING: " __VA_ARGS__); \
111 struct intel_driver_data
120 pthread_mutex_t ctxmutex;
125 unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
126 unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
127 unsigned int has_blt : 1; /* Flag: has BLT unit? */
128 unsigned int has_vebox : 1; /* Flag: has VEBOX unit */
131 bool intel_driver_init(VADriverContextP ctx);
132 void intel_driver_terminate(VADriverContextP ctx);
134 static INLINE struct intel_driver_data *
135 intel_driver_data(VADriverContextP ctx)
137 return (struct intel_driver_data *)ctx->pDriverData;
149 unsigned int swizzle;
153 #define PCI_CHIP_GM45_GM 0x2A42
154 #define PCI_CHIP_IGD_E_G 0x2E02
155 #define PCI_CHIP_Q45_G 0x2E12
156 #define PCI_CHIP_G45_G 0x2E22
157 #define PCI_CHIP_G41_G 0x2E32
158 #define PCI_CHIP_B43_G 0x2E42
159 #define PCI_CHIP_B43_G1 0x2E92
161 #define PCI_CHIP_IRONLAKE_D_G 0x0042
162 #define PCI_CHIP_IRONLAKE_M_G 0x0046
164 #ifndef PCI_CHIP_SANDYBRIDGE_GT1
165 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
166 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
167 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
168 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
169 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
170 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
171 #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */
174 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */
175 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
176 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
177 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
178 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
179 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
181 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
182 #define PCI_CHIP_HASWELL_GT2 0x0412
183 #define PCI_CHIP_HASWELL_GT3 0x0422
184 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
185 #define PCI_CHIP_HASWELL_M_GT2 0x0416
186 #define PCI_CHIP_HASWELL_M_GT3 0x0426
187 #define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */
188 #define PCI_CHIP_HASWELL_S_GT2 0x041a
189 #define PCI_CHIP_HASWELL_S_GT3 0x042a
190 #define PCI_CHIP_HASWELL_B_GT1 0x040b /* Reserved */
191 #define PCI_CHIP_HASWELL_B_GT2 0x041b
192 #define PCI_CHIP_HASWELL_B_GT3 0x042b
193 #define PCI_CHIP_HASWELL_E_GT1 0x040e /* Reserved */
194 #define PCI_CHIP_HASWELL_E_GT2 0x041e
195 #define PCI_CHIP_HASWELL_E_GT3 0x042e
197 #define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */
198 #define PCI_CHIP_HASWELL_SDV_GT2 0x0c12
199 #define PCI_CHIP_HASWELL_SDV_GT3 0x0c22
200 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */
201 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16
202 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0c26
203 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */
204 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a
205 #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0c2a
206 #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0c0b /* Reserved */
207 #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0c1b
208 #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0c2b
209 #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0c0e /* Reserved */
210 #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0c1e
211 #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0c2e
213 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
214 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
215 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
216 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
217 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
218 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
219 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
220 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
221 #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
222 #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
223 #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
224 #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
225 #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
226 #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
227 #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
229 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
230 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
231 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
232 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
233 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
234 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
235 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
236 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
237 #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
238 #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
239 #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
240 #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
241 #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
242 #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
243 #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
245 #define PCI_CHIP_BAYTRAIL_M_1 0x0F31
246 #define PCI_CHIP_BAYTRAIL_M_2 0x0F32
247 #define PCI_CHIP_BAYTRAIL_M_3 0x0F33
248 #define PCI_CHIP_BAYTRAIL_M_4 0x0157
249 #define PCI_CHIP_BAYTRAIL_D 0x0155
251 #define PCI_CHIP_BROADWELL_MS_GT1 0x1602
252 #define PCI_CHIP_BROADWELL_MS_GT2 0x1612
253 #define PCI_CHIP_BROADWELL_MS_GT2PLUS 0x1622
255 #define PCI_CHIP_BROADWELL_M_GT1_1 0x1606
256 #define PCI_CHIP_BROADWELL_M_GT2_1 0x1616
257 #define PCI_CHIP_BROADWELL_M_GT2PLUS_1 0x1626
259 #define PCI_CHIP_BROADWELL_M_GT1_2 0x160B
260 #define PCI_CHIP_BROADWELL_M_GT2_2 0x161B
261 #define PCI_CHIP_BROADWELL_M_GT2PLUS_2 0x162B
263 #define PCI_CHIP_BROADWELL_M_GT1_3 0x160E
264 #define PCI_CHIP_BROADWELL_M_GT2_3 0x161E
265 #define PCI_CHIP_BROADWELL_M_GT2PLUS_3 0x162E
267 #define PCI_CHIP_BROADWELL_D_GT1_1 0x160A
268 #define PCI_CHIP_BROADWELL_D_GT2_1 0x161A
269 #define PCI_CHIP_BROADWELL_D_GT2PLUS_1 0x162A
271 #define PCI_CHIP_BROADWELL_D_GT1_2 0x160D
272 #define PCI_CHIP_BROADWELL_D_GT2_2 0x161D
273 #define PCI_CHIP_BROADWELL_D_GT2PLUS_2 0x162D
275 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
276 devid == PCI_CHIP_Q45_G || \
277 devid == PCI_CHIP_G45_G || \
278 devid == PCI_CHIP_G41_G || \
279 devid == PCI_CHIP_B43_G || \
280 devid == PCI_CHIP_B43_G1)
282 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
283 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
285 #define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G)
286 #define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G)
287 #define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
289 #define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
290 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
291 devid == PCI_CHIP_SANDYBRIDGE_S_GT)
293 #define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
294 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
295 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
296 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
298 #define IS_GEN6(devid) (IS_SNB_GT1(devid) || \
301 #define IS_BAYTRAIL_M1(devid) (devid == PCI_CHIP_BAYTRAIL_M_1)
302 #define IS_BAYTRAIL_M2(devid) (devid == PCI_CHIP_BAYTRAIL_M_2)
303 #define IS_BAYTRAIL_M3(devid) (devid == PCI_CHIP_BAYTRAIL_M_3)
304 #define IS_BAYTRAIL_D(devid) (devid == PCI_CHIP_BAYTRAIL_D)
305 #define IS_BAYTRAIL(devid) (IS_BAYTRAIL_M1(devid) || \
306 IS_BAYTRAIL_M2(devid) || \
307 IS_BAYTRAIL_M3(devid) || \
308 IS_BAYTRAIL_D(devid) )
310 #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
311 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
312 devid == PCI_CHIP_IVYBRIDGE_S_GT1)
314 #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
315 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
316 devid == PCI_CHIP_IVYBRIDGE_S_GT2)
318 #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \
319 IS_IVB_GT2(devid) || \
322 #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
323 devid == PCI_CHIP_HASWELL_M_GT1 || \
324 devid == PCI_CHIP_HASWELL_S_GT1 || \
325 devid == PCI_CHIP_HASWELL_B_GT1 || \
326 devid == PCI_CHIP_HASWELL_E_GT1 || \
327 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
328 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
329 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
330 devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
331 devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
332 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
333 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
334 devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
335 devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
336 devid == PCI_CHIP_HASWELL_CRW_E_GT1 || \
337 devid == PCI_CHIP_HASWELL_ULT_GT1 || \
338 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
339 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
340 devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
341 devid == PCI_CHIP_HASWELL_ULT_E_GT1)
344 #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \
345 devid == PCI_CHIP_HASWELL_M_GT2|| \
346 devid == PCI_CHIP_HASWELL_S_GT2|| \
347 devid == PCI_CHIP_HASWELL_B_GT2 || \
348 devid == PCI_CHIP_HASWELL_E_GT2 || \
349 devid == PCI_CHIP_HASWELL_SDV_GT2|| \
350 devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \
351 devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \
352 devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
353 devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
354 devid == PCI_CHIP_HASWELL_CRW_GT2|| \
355 devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \
356 devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \
357 devid == PCI_CHIP_HASWELL_CRW_B_GT2|| \
358 devid == PCI_CHIP_HASWELL_CRW_E_GT2|| \
359 devid == PCI_CHIP_HASWELL_ULT_GT2|| \
360 devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \
361 devid == PCI_CHIP_HASWELL_ULT_S_GT2|| \
362 devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
363 devid == PCI_CHIP_HASWELL_ULT_E_GT2)
366 #define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \
367 devid == PCI_CHIP_HASWELL_M_GT3 || \
368 devid == PCI_CHIP_HASWELL_S_GT3 || \
369 devid == PCI_CHIP_HASWELL_B_GT3 || \
370 devid == PCI_CHIP_HASWELL_E_GT3 || \
371 devid == PCI_CHIP_HASWELL_SDV_GT3 || \
372 devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
373 devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
374 devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
375 devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
376 devid == PCI_CHIP_HASWELL_CRW_GT3 || \
377 devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
378 devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
379 devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
380 devid == PCI_CHIP_HASWELL_CRW_E_GT3 || \
381 devid == PCI_CHIP_HASWELL_ULT_GT3 || \
382 devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
383 devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
384 devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
385 devid == PCI_CHIP_HASWELL_ULT_E_GT3)
387 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
388 IS_HSW_GT2(devid) || \
391 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
395 #define IS_BDW_GT1(devid) (devid == PCI_CHIP_BROADWELL_M_GT1_1 || \
396 devid == PCI_CHIP_BROADWELL_M_GT1_2 || \
397 devid == PCI_CHIP_BROADWELL_M_GT1_3 || \
398 devid == PCI_CHIP_BROADWELL_D_GT1_1 || \
399 devid == PCI_CHIP_BROADWELL_D_GT1_2 || \
400 devid == PCI_CHIP_BROADWELL_MS_GT1)
402 #define IS_BDW_GT2(devid) (devid == PCI_CHIP_BROADWELL_M_GT2_1 || \
403 devid == PCI_CHIP_BROADWELL_M_GT2_2 || \
404 devid == PCI_CHIP_BROADWELL_M_GT2_3 || \
405 devid == PCI_CHIP_BROADWELL_D_GT2_1 || \
406 devid == PCI_CHIP_BROADWELL_D_GT2_2 || \
407 devid == PCI_CHIP_BROADWELL_MS_GT2)
409 #define IS_BDW_GT2PLUS(devid) (devid == PCI_CHIP_BROADWELL_M_GT2PLUS_1 || \
410 devid == PCI_CHIP_BROADWELL_M_GT2PLUS_2 || \
411 devid == PCI_CHIP_BROADWELL_M_GT2PLUS_3 || \
412 devid == PCI_CHIP_BROADWELL_D_GT2PLUS_1 || \
413 devid == PCI_CHIP_BROADWELL_D_GT2PLUS_2 || \
414 devid == PCI_CHIP_BROADWELL_MS_GT2PLUS)
416 #define IS_GEN8(devid) (IS_BDW_GT1(devid) || \
417 IS_BDW_GT2(devid) || \
418 IS_BDW_GT2PLUS(devid))
420 #endif /* _INTEL_DRIVER_H_ */