1 #ifndef _INTEL_DRIVER_H_
2 #define _INTEL_DRIVER_H_
10 #include <intel_bufmgr.h>
12 #include <va/va_backend.h>
14 #include "intel_compiler.h"
16 #define BATCH_SIZE 0x80000
17 #define BATCH_RESERVED 0x10
19 #define CMD_MI (0x0 << 29)
20 #define CMD_2D (0x2 << 29)
21 #define CMD_3D (0x3 << 29)
23 #define MI_NOOP (CMD_MI | 0)
25 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
26 #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
28 #define MI_FLUSH (CMD_MI | (0x4 << 23))
29 #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
31 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
32 #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
34 #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
35 #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
36 #define XY_COLOR_BLT_WRITE_RGB (1 << 20)
37 #define XY_COLOR_BLT_DST_TILED (1 << 11)
40 #define BR13_8 (0x0 << 24)
41 #define BR13_565 (0x1 << 24)
42 #define BR13_1555 (0x2 << 24)
43 #define BR13_8888 (0x3 << 24)
45 #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
46 #define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
47 #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
48 #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
49 #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
50 #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
51 #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
52 #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
53 #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
54 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
55 #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
56 #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
57 #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
58 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
61 struct intel_batchbuffer;
63 #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
64 #define MIN(a, b) ((a) < (b) ? (a) : (b))
65 #define MAX(a, b) ((a) > (b) ? (a) : (b))
66 #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
72 #define SET_BLOCKED_SIGSET() do { \
74 sigfillset(&bl_mask); \
75 sigdelset(&bl_mask, SIGFPE); \
76 sigdelset(&bl_mask, SIGILL); \
77 sigdelset(&bl_mask, SIGSEGV); \
78 sigdelset(&bl_mask, SIGBUS); \
79 sigdelset(&bl_mask, SIGKILL); \
80 pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
83 #define RESTORE_BLOCKED_SIGSET() do { \
84 pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
87 #define PPTHREAD_MUTEX_LOCK() do { \
88 SET_BLOCKED_SIGSET(); \
89 pthread_mutex_lock(&intel->ctxmutex); \
92 #define PPTHREAD_MUTEX_UNLOCK() do { \
93 pthread_mutex_unlock(&intel->ctxmutex); \
94 RESTORE_BLOCKED_SIGSET(); \
97 #define WARN_ONCE(...) do { \
98 static int g_once = 1; \
101 printf("WARNING: " __VA_ARGS__); \
105 struct intel_driver_data
114 pthread_mutex_t ctxmutex;
119 unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
120 unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
121 unsigned int has_blt : 1; /* Flag: has BLT unit? */
124 Bool intel_driver_init(VADriverContextP ctx);
125 Bool intel_driver_terminate(VADriverContextP ctx);
127 static INLINE struct intel_driver_data *
128 intel_driver_data(VADriverContextP ctx)
130 return (struct intel_driver_data *)ctx->pDriverData;
142 unsigned int swizzle;
146 #define PCI_CHIP_GM45_GM 0x2A42
147 #define PCI_CHIP_IGD_E_G 0x2E02
148 #define PCI_CHIP_Q45_G 0x2E12
149 #define PCI_CHIP_G45_G 0x2E22
150 #define PCI_CHIP_G41_G 0x2E32
151 #define PCI_CHIP_B43_G 0x2E42
152 #define PCI_CHIP_B43_G1 0x2E92
154 #define PCI_CHIP_IRONLAKE_D_G 0x0042
155 #define PCI_CHIP_IRONLAKE_M_G 0x0046
157 #ifndef PCI_CHIP_SANDYBRIDGE_GT1
158 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
159 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
160 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
161 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
162 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
163 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
164 #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */
167 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */
168 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
169 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
170 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
171 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
172 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
174 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
175 #define PCI_CHIP_HASWELL_GT2 0x0412
176 #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
177 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
178 #define PCI_CHIP_HASWELL_M_GT2 0x0416
179 #define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
180 #define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */
181 #define PCI_CHIP_HASWELL_S_GT2 0x041a
182 #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042a
184 #define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */
185 #define PCI_CHIP_HASWELL_SDV_GT2 0x0c12
186 #define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0c22
187 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */
188 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16
189 #define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0c26
190 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */
191 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a
192 #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0c2a
194 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
195 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
196 #define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
197 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
198 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
199 #define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
200 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
201 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
202 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
204 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
205 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
206 #define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
207 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
208 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
209 #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
210 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
211 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
212 #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
214 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
215 devid == PCI_CHIP_Q45_G || \
216 devid == PCI_CHIP_G45_G || \
217 devid == PCI_CHIP_G41_G || \
218 devid == PCI_CHIP_B43_G || \
219 devid == PCI_CHIP_B43_G1)
221 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
222 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
224 #define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G)
225 #define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G)
226 #define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
228 #define IS_HASWELL_ULT(devid) (devid == PCI_CHIP_HASWELL_ULT_GT1 || \
229 devid == PCI_CHIP_HASWELL_ULT_GT2 || \
230 devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
231 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
232 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
233 devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
234 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
235 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
236 devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS)
238 #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
239 devid == PCI_CHIP_HASWELL_M_GT1 || \
240 devid == PCI_CHIP_HASWELL_S_GT1 || \
241 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
242 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
243 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
244 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
245 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
246 devid == PCI_CHIP_HASWELL_CRW_S_GT1)
248 #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
249 devid == PCI_CHIP_HASWELL_M_GT2 || \
250 devid == PCI_CHIP_HASWELL_S_GT2 || \
251 devid == PCI_CHIP_HASWELL_SDV_GT2 || \
252 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
253 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
254 devid == PCI_CHIP_HASWELL_CRW_GT2 || \
255 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
256 devid == PCI_CHIP_HASWELL_CRW_S_GT2)
258 #define IS_HSW_GT2_PLUS(devid) (devid == PCI_CHIP_HASWELL_GT2_PLUS || \
259 devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
260 devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
261 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
262 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
263 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
264 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
265 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
266 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
268 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
269 IS_HSW_GT2(devid) || \
270 IS_HSW_GT2_PLUS(devid) || \
271 IS_HASWELL_ULT(devid))
273 #define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
274 devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
275 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS ||\
276 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
277 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
278 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
279 devid == PCI_CHIP_SANDYBRIDGE_S_GT)
281 #define IS_GEN7(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
282 devid == PCI_CHIP_IVYBRIDGE_GT2 || \
283 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
284 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
285 devid == PCI_CHIP_IVYBRIDGE_S_GT1 || \
286 devid == PCI_CHIP_IVYBRIDGE_S_GT2 || \
289 #ifndef I915_EXEC_VEBOX
290 #define I915_EXEC_VEBOX 4
293 #endif /* _INTEL_DRIVER_H_ */