1 #ifndef _INTEL_DRIVER_H_
2 #define _INTEL_DRIVER_H_
11 #include <intel_bufmgr.h>
13 #include <va/va_backend.h>
14 #include "va_backend_compat.h"
16 #include "intel_compiler.h"
18 #define BATCH_SIZE 0x80000
19 #define BATCH_RESERVED 0x10
21 #define CMD_MI (0x0 << 29)
22 #define CMD_2D (0x2 << 29)
23 #define CMD_3D (0x3 << 29)
25 #define MI_NOOP (CMD_MI | 0)
27 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
28 #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
30 #define MI_FLUSH (CMD_MI | (0x4 << 23))
31 #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
33 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
34 #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
36 #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
37 #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
38 #define XY_COLOR_BLT_WRITE_RGB (1 << 20)
39 #define XY_COLOR_BLT_DST_TILED (1 << 11)
41 #define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05)
44 #define BR13_8 (0x0 << 24)
45 #define BR13_565 (0x1 << 24)
46 #define BR13_1555 (0x2 << 24)
47 #define BR13_8888 (0x3 << 24)
49 #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
50 #define CMD_PIPE_CONTROL_CS_STALL (1 << 20)
51 #define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
52 #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
53 #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
54 #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
55 #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
56 #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
57 #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
58 #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
59 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
60 #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
61 #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
62 #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
63 #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
64 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
67 struct intel_batchbuffer;
69 #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
70 #define IS_ALIGNED(i, n) (((i) & ((n)-1)) == 0)
71 #define MIN(a, b) ((a) < (b) ? (a) : (b))
72 #define MAX(a, b) ((a) > (b) ? (a) : (b))
73 #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
79 extern uint32_t g_intel_debug_option_flags;
80 #define VA_INTEL_DEBUG_OPTION_ASSERT (1 << 0)
81 #define VA_INTEL_DEBUG_OPTION_BENCH (1 << 1)
83 #define ASSERT_RET(value, fail_ret) do { \
85 if (g_intel_debug_option_flags & VA_INTEL_DEBUG_OPTION_ASSERT) \
91 #define SET_BLOCKED_SIGSET() do { \
93 sigfillset(&bl_mask); \
94 sigdelset(&bl_mask, SIGFPE); \
95 sigdelset(&bl_mask, SIGILL); \
96 sigdelset(&bl_mask, SIGSEGV); \
97 sigdelset(&bl_mask, SIGBUS); \
98 sigdelset(&bl_mask, SIGKILL); \
99 pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
102 #define RESTORE_BLOCKED_SIGSET() do { \
103 pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
106 #define PPTHREAD_MUTEX_LOCK() do { \
107 SET_BLOCKED_SIGSET(); \
108 pthread_mutex_lock(&intel->ctxmutex); \
111 #define PPTHREAD_MUTEX_UNLOCK() do { \
112 pthread_mutex_unlock(&intel->ctxmutex); \
113 RESTORE_BLOCKED_SIGSET(); \
116 #define WARN_ONCE(...) do { \
117 static int g_once = 1; \
120 printf("WARNING: " __VA_ARGS__); \
124 struct intel_device_info
129 unsigned int urb_size;
130 unsigned int max_wm_threads;
132 unsigned int is_g4x : 1; /* gen4 */
133 unsigned int is_ivybridge : 1; /* gen7 */
134 unsigned int is_baytrail : 1; /* gen7 */
135 unsigned int is_haswell : 1; /* gen7 */
138 struct intel_driver_data
147 pthread_mutex_t ctxmutex;
152 unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
153 unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
154 unsigned int has_blt : 1; /* Flag: has BLT unit? */
155 unsigned int has_vebox : 1; /* Flag: has VEBOX unit */
157 const struct intel_device_info *device_info;
160 bool intel_driver_init(VADriverContextP ctx);
161 void intel_driver_terminate(VADriverContextP ctx);
163 static INLINE struct intel_driver_data *
164 intel_driver_data(VADriverContextP ctx)
166 return (struct intel_driver_data *)ctx->pDriverData;
178 unsigned int swizzle;
182 #define IS_G4X(device_info) (device_info->is_g4x)
184 #define IS_IRONLAKE(device_info) (device_info->gen == 5)
186 #define IS_GEN6(device_info) (device_info->gen == 6)
188 #define IS_HASWELL(device_info) (device_info->is_haswell)
189 #define IS_GEN7(device_info) (device_info->gen == 7)
191 #define IS_GEN8(device_info) (device_info->gen == 8)
193 #endif /* _INTEL_DRIVER_H_ */