1 #ifndef _INTEL_DRIVER_H_
2 #define _INTEL_DRIVER_H_
11 #include <intel_bufmgr.h>
13 #include <va/va_backend.h>
14 #include "va_backend_compat.h"
16 #include "intel_compiler.h"
18 #define BATCH_SIZE 0x80000
19 #define BATCH_RESERVED 0x10
21 #define CMD_MI (0x0 << 29)
22 #define CMD_2D (0x2 << 29)
23 #define CMD_3D (0x3 << 29)
25 #define MI_NOOP (CMD_MI | 0)
27 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
28 #define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
30 #define MI_FLUSH (CMD_MI | (0x4 << 23))
31 #define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
33 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
34 #define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
36 #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
37 #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
38 #define XY_COLOR_BLT_WRITE_RGB (1 << 20)
39 #define XY_COLOR_BLT_DST_TILED (1 << 11)
41 #define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05)
44 #define BR13_8 (0x0 << 24)
45 #define BR13_565 (0x1 << 24)
46 #define BR13_1555 (0x2 << 24)
47 #define BR13_8888 (0x3 << 24)
49 #define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
50 #define CMD_PIPE_CONTROL_CS_STALL (1 << 20)
51 #define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
52 #define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
53 #define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
54 #define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
55 #define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
56 #define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
57 #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
58 #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
59 #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
60 #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
61 #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
62 #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
63 #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
64 #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
67 struct intel_batchbuffer;
69 #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
70 #define IS_ALIGNED(i, n) (((i) & ((n)-1)) == 0)
71 #define MIN(a, b) ((a) < (b) ? (a) : (b))
72 #define MAX(a, b) ((a) > (b) ? (a) : (b))
73 #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
79 #define ASSERT_RET(value, fail_ret) do { \
86 #define SET_BLOCKED_SIGSET() do { \
88 sigfillset(&bl_mask); \
89 sigdelset(&bl_mask, SIGFPE); \
90 sigdelset(&bl_mask, SIGILL); \
91 sigdelset(&bl_mask, SIGSEGV); \
92 sigdelset(&bl_mask, SIGBUS); \
93 sigdelset(&bl_mask, SIGKILL); \
94 pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
97 #define RESTORE_BLOCKED_SIGSET() do { \
98 pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
101 #define PPTHREAD_MUTEX_LOCK() do { \
102 SET_BLOCKED_SIGSET(); \
103 pthread_mutex_lock(&intel->ctxmutex); \
106 #define PPTHREAD_MUTEX_UNLOCK() do { \
107 pthread_mutex_unlock(&intel->ctxmutex); \
108 RESTORE_BLOCKED_SIGSET(); \
111 #define WARN_ONCE(...) do { \
112 static int g_once = 1; \
115 printf("WARNING: " __VA_ARGS__); \
119 struct intel_driver_data
128 pthread_mutex_t ctxmutex;
133 unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
134 unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
135 unsigned int has_blt : 1; /* Flag: has BLT unit? */
136 unsigned int has_vebox : 1; /* Flag: has VEBOX unit */
139 bool intel_driver_init(VADriverContextP ctx);
140 void intel_driver_terminate(VADriverContextP ctx);
142 static INLINE struct intel_driver_data *
143 intel_driver_data(VADriverContextP ctx)
145 return (struct intel_driver_data *)ctx->pDriverData;
157 unsigned int swizzle;
161 #define PCI_CHIP_GM45_GM 0x2A42
162 #define PCI_CHIP_IGD_E_G 0x2E02
163 #define PCI_CHIP_Q45_G 0x2E12
164 #define PCI_CHIP_G45_G 0x2E22
165 #define PCI_CHIP_G41_G 0x2E32
166 #define PCI_CHIP_B43_G 0x2E42
167 #define PCI_CHIP_B43_G1 0x2E92
169 #define PCI_CHIP_IRONLAKE_D_G 0x0042
170 #define PCI_CHIP_IRONLAKE_M_G 0x0046
172 #ifndef PCI_CHIP_SANDYBRIDGE_GT1
173 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
174 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
175 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
176 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
177 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
178 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
179 #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */
182 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */
183 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
184 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
185 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
186 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
187 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
189 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
190 #define PCI_CHIP_HASWELL_GT2 0x0412
191 #define PCI_CHIP_HASWELL_GT3 0x0422
192 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
193 #define PCI_CHIP_HASWELL_M_GT2 0x0416
194 #define PCI_CHIP_HASWELL_M_GT3 0x0426
195 #define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */
196 #define PCI_CHIP_HASWELL_S_GT2 0x041a
197 #define PCI_CHIP_HASWELL_S_GT3 0x042a
198 #define PCI_CHIP_HASWELL_B_GT1 0x040b /* Reserved */
199 #define PCI_CHIP_HASWELL_B_GT2 0x041b
200 #define PCI_CHIP_HASWELL_B_GT3 0x042b
201 #define PCI_CHIP_HASWELL_E_GT1 0x040e /* Reserved */
202 #define PCI_CHIP_HASWELL_E_GT2 0x041e
203 #define PCI_CHIP_HASWELL_E_GT3 0x042e
205 #define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */
206 #define PCI_CHIP_HASWELL_SDV_GT2 0x0c12
207 #define PCI_CHIP_HASWELL_SDV_GT3 0x0c22
208 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */
209 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16
210 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0c26
211 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */
212 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a
213 #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0c2a
214 #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0c0b /* Reserved */
215 #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0c1b
216 #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0c2b
217 #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0c0e /* Reserved */
218 #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0c1e
219 #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0c2e
221 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
222 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
223 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
224 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
225 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
226 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
227 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
228 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
229 #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
230 #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
231 #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
232 #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
233 #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
234 #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
235 #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
237 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
238 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
239 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
240 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
241 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
242 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
243 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
244 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
245 #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
246 #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
247 #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
248 #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
249 #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
250 #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
251 #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
253 #define PCI_CHIP_BAYTRAIL_M_1 0x0F31
254 #define PCI_CHIP_BAYTRAIL_M_2 0x0F32
255 #define PCI_CHIP_BAYTRAIL_M_3 0x0F33
256 #define PCI_CHIP_BAYTRAIL_M_4 0x0157
257 #define PCI_CHIP_BAYTRAIL_D 0x0155
259 #define PCI_CHIP_BROADWELL_MS_GT1 0x1602
260 #define PCI_CHIP_BROADWELL_MS_GT2 0x1612
261 #define PCI_CHIP_BROADWELL_MS_GT2PLUS 0x1622
263 #define PCI_CHIP_BROADWELL_M_GT1_1 0x1606
264 #define PCI_CHIP_BROADWELL_M_GT2_1 0x1616
265 #define PCI_CHIP_BROADWELL_M_GT2PLUS_1 0x1626
267 #define PCI_CHIP_BROADWELL_M_GT1_2 0x160B
268 #define PCI_CHIP_BROADWELL_M_GT2_2 0x161B
269 #define PCI_CHIP_BROADWELL_M_GT2PLUS_2 0x162B
271 #define PCI_CHIP_BROADWELL_M_GT1_3 0x160E
272 #define PCI_CHIP_BROADWELL_M_GT2_3 0x161E
273 #define PCI_CHIP_BROADWELL_M_GT2PLUS_3 0x162E
275 #define PCI_CHIP_BROADWELL_D_GT1_1 0x160A
276 #define PCI_CHIP_BROADWELL_D_GT2_1 0x161A
277 #define PCI_CHIP_BROADWELL_D_GT2PLUS_1 0x162A
279 #define PCI_CHIP_BROADWELL_D_GT1_2 0x160D
280 #define PCI_CHIP_BROADWELL_D_GT2_2 0x161D
281 #define PCI_CHIP_BROADWELL_D_GT2PLUS_2 0x162D
283 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
284 devid == PCI_CHIP_Q45_G || \
285 devid == PCI_CHIP_G45_G || \
286 devid == PCI_CHIP_G41_G || \
287 devid == PCI_CHIP_B43_G || \
288 devid == PCI_CHIP_B43_G1)
290 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
291 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
293 #define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G)
294 #define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G)
295 #define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
297 #define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
298 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
299 devid == PCI_CHIP_SANDYBRIDGE_S_GT)
301 #define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
302 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
303 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
304 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
306 #define IS_GEN6(devid) (IS_SNB_GT1(devid) || \
309 #define IS_BAYTRAIL_M1(devid) (devid == PCI_CHIP_BAYTRAIL_M_1)
310 #define IS_BAYTRAIL_M2(devid) (devid == PCI_CHIP_BAYTRAIL_M_2)
311 #define IS_BAYTRAIL_M3(devid) (devid == PCI_CHIP_BAYTRAIL_M_3)
312 #define IS_BAYTRAIL_D(devid) (devid == PCI_CHIP_BAYTRAIL_D)
313 #define IS_BAYTRAIL(devid) (IS_BAYTRAIL_M1(devid) || \
314 IS_BAYTRAIL_M2(devid) || \
315 IS_BAYTRAIL_M3(devid) || \
316 IS_BAYTRAIL_D(devid) )
318 #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
319 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
320 devid == PCI_CHIP_IVYBRIDGE_S_GT1)
322 #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
323 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
324 devid == PCI_CHIP_IVYBRIDGE_S_GT2)
326 #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \
327 IS_IVB_GT2(devid) || \
330 #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
331 devid == PCI_CHIP_HASWELL_M_GT1 || \
332 devid == PCI_CHIP_HASWELL_S_GT1 || \
333 devid == PCI_CHIP_HASWELL_B_GT1 || \
334 devid == PCI_CHIP_HASWELL_E_GT1 || \
335 devid == PCI_CHIP_HASWELL_SDV_GT1 || \
336 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
337 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
338 devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
339 devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
340 devid == PCI_CHIP_HASWELL_CRW_GT1 || \
341 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
342 devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
343 devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
344 devid == PCI_CHIP_HASWELL_CRW_E_GT1 || \
345 devid == PCI_CHIP_HASWELL_ULT_GT1 || \
346 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
347 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
348 devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
349 devid == PCI_CHIP_HASWELL_ULT_E_GT1)
352 #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \
353 devid == PCI_CHIP_HASWELL_M_GT2|| \
354 devid == PCI_CHIP_HASWELL_S_GT2|| \
355 devid == PCI_CHIP_HASWELL_B_GT2 || \
356 devid == PCI_CHIP_HASWELL_E_GT2 || \
357 devid == PCI_CHIP_HASWELL_SDV_GT2|| \
358 devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \
359 devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \
360 devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
361 devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
362 devid == PCI_CHIP_HASWELL_CRW_GT2|| \
363 devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \
364 devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \
365 devid == PCI_CHIP_HASWELL_CRW_B_GT2|| \
366 devid == PCI_CHIP_HASWELL_CRW_E_GT2|| \
367 devid == PCI_CHIP_HASWELL_ULT_GT2|| \
368 devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \
369 devid == PCI_CHIP_HASWELL_ULT_S_GT2|| \
370 devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
371 devid == PCI_CHIP_HASWELL_ULT_E_GT2)
374 #define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \
375 devid == PCI_CHIP_HASWELL_M_GT3 || \
376 devid == PCI_CHIP_HASWELL_S_GT3 || \
377 devid == PCI_CHIP_HASWELL_B_GT3 || \
378 devid == PCI_CHIP_HASWELL_E_GT3 || \
379 devid == PCI_CHIP_HASWELL_SDV_GT3 || \
380 devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
381 devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
382 devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
383 devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
384 devid == PCI_CHIP_HASWELL_CRW_GT3 || \
385 devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
386 devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
387 devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
388 devid == PCI_CHIP_HASWELL_CRW_E_GT3 || \
389 devid == PCI_CHIP_HASWELL_ULT_GT3 || \
390 devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
391 devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
392 devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
393 devid == PCI_CHIP_HASWELL_ULT_E_GT3)
395 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
396 IS_HSW_GT2(devid) || \
399 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
403 #define IS_BDW_GT1(devid) (devid == PCI_CHIP_BROADWELL_M_GT1_1 || \
404 devid == PCI_CHIP_BROADWELL_M_GT1_2 || \
405 devid == PCI_CHIP_BROADWELL_M_GT1_3 || \
406 devid == PCI_CHIP_BROADWELL_D_GT1_1 || \
407 devid == PCI_CHIP_BROADWELL_D_GT1_2 || \
408 devid == PCI_CHIP_BROADWELL_MS_GT1)
410 #define IS_BDW_GT2(devid) (devid == PCI_CHIP_BROADWELL_M_GT2_1 || \
411 devid == PCI_CHIP_BROADWELL_M_GT2_2 || \
412 devid == PCI_CHIP_BROADWELL_M_GT2_3 || \
413 devid == PCI_CHIP_BROADWELL_D_GT2_1 || \
414 devid == PCI_CHIP_BROADWELL_D_GT2_2 || \
415 devid == PCI_CHIP_BROADWELL_MS_GT2)
417 #define IS_BDW_GT2PLUS(devid) (devid == PCI_CHIP_BROADWELL_M_GT2PLUS_1 || \
418 devid == PCI_CHIP_BROADWELL_M_GT2PLUS_2 || \
419 devid == PCI_CHIP_BROADWELL_M_GT2PLUS_3 || \
420 devid == PCI_CHIP_BROADWELL_D_GT2PLUS_1 || \
421 devid == PCI_CHIP_BROADWELL_D_GT2PLUS_2 || \
422 devid == PCI_CHIP_BROADWELL_MS_GT2PLUS)
424 #define IS_GEN8(devid) (IS_BDW_GT1(devid) || \
425 IS_BDW_GT2(devid) || \
426 IS_BDW_GT2PLUS(devid))
428 #endif /* _INTEL_DRIVER_H_ */