src/intel_batchbuffer.c

   1 /**************************************************************************
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   3  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
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  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30 #include <assert.h>
  31
  32 #include "intel_batchbuffer.h"
  33
  34 #define MAX_BATCH_SIZE          0x400000
  35
  36 static void
  37 intel_batchbuffer_reset(struct intel_batchbuffer *batch, int buffer_size)
  38 {
  39     struct intel_driver_data *intel = batch->intel;
  40     int batch_size = buffer_size;
  41
  42     assert(batch->flag == I915_EXEC_RENDER ||
  43            batch->flag == I915_EXEC_BLT ||
  44            batch->flag == I915_EXEC_BSD ||
  45            batch->flag == I915_EXEC_VEBOX);
  46
  47     dri_bo_unreference(batch->buffer);
  48     batch->buffer = dri_bo_alloc(intel->bufmgr,
  49                                  "batch buffer",
  50                                  batch_size,
  51                                  0x1000);
  52     assert(batch->buffer);
  53     dri_bo_map(batch->buffer, 1);
  54     assert(batch->buffer->virtual);
  55     batch->map = batch->buffer->virtual;
  56     batch->size = batch_size;
  57     batch->ptr = batch->map;
  58     batch->atomic = 0;
  59 }
  60
  61 static unsigned int
  62 intel_batchbuffer_space(struct intel_batchbuffer *batch)
  63 {
  64     return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map);
  65 }
  66
  67
  68 struct intel_batchbuffer *
  69 intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int buffer_size)
  70 {
  71     struct intel_batchbuffer *batch = calloc(1, sizeof(*batch));
  72     assert(flag == I915_EXEC_RENDER ||
  73            flag == I915_EXEC_BSD ||
  74            flag == I915_EXEC_BLT ||
  75            flag == I915_EXEC_VEBOX);
  76
  77    if (!buffer_size || buffer_size < BATCH_SIZE) {
  78         buffer_size = BATCH_SIZE;
  79    }
  80
  81    /* the buffer size can't exceed 4M */
  82    if (buffer_size > MAX_BATCH_SIZE) {
  83         buffer_size = MAX_BATCH_SIZE;
  84    }
  85
  86     batch->intel = intel;
  87     batch->flag = flag;
  88     batch->run = drm_intel_bo_mrb_exec;
  89
  90     if (IS_GEN6(intel->device_id) &&
  91         flag == I915_EXEC_RENDER)
  92         batch->wa_render_bo = dri_bo_alloc(intel->bufmgr,
  93                                            "wa scratch",
  94                                            4096,
  95                                            4096);
  96     else
  97         batch->wa_render_bo = NULL;
  98
  99     intel_batchbuffer_reset(batch, buffer_size);
 100
 101     return batch;
 102 }
 103
 104 void intel_batchbuffer_free(struct intel_batchbuffer *batch)
 105 {
 106     if (batch->map) {
 107         dri_bo_unmap(batch->buffer);
 108         batch->map = NULL;
 109     }
 110
 111     dri_bo_unreference(batch->buffer);
 112     dri_bo_unreference(batch->wa_render_bo);
 113     free(batch);
 114 }
 115
 116 void
 117 intel_batchbuffer_flush(struct intel_batchbuffer *batch)
 118 {
 119     unsigned int used = batch->ptr - batch->map;
 120
 121     if (used == 0) {
 122         return;
 123     }
 124
 125     if ((used & 4) == 0) {
 126         *(unsigned int*)batch->ptr = 0;
 127         batch->ptr += 4;
 128     }
 129
 130     *(unsigned int*)batch->ptr = MI_BATCH_BUFFER_END;
 131     batch->ptr += 4;
 132     dri_bo_unmap(batch->buffer);
 133     used = batch->ptr - batch->map;
 134     batch->run(batch->buffer, used, 0, 0, 0, batch->flag);
 135     intel_batchbuffer_reset(batch, batch->size);
 136 }
 137
 138 void
 139 intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, unsigned int x)
 140 {
 141     assert(intel_batchbuffer_space(batch) >= 4);
 142     *(unsigned int *)batch->ptr = x;
 143     batch->ptr += 4;
 144 }
 145
 146 void
 147 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, dri_bo *bo,
 148                                 uint32_t read_domains, uint32_t write_domains,
 149                                 uint32_t delta)
 150 {
 151     assert(batch->ptr - batch->map < batch->size);
 152     dri_bo_emit_reloc(batch->buffer, read_domains, write_domains,
 153                       delta, batch->ptr - batch->map, bo);
 154     intel_batchbuffer_emit_dword(batch, bo->offset + delta);
 155 }
 156
 157 void
 158 intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
 159                                    unsigned int size)
 160 {
 161     assert(size < batch->size - 8);
 162
 163     if (intel_batchbuffer_space(batch) < size) {
 164         intel_batchbuffer_flush(batch);
 165     }
 166 }
 167
 168 void
 169 intel_batchbuffer_data(struct intel_batchbuffer *batch,
 170                           void *data,
 171                           unsigned int size)
 172 {
 173     assert((size & 3) == 0);
 174     intel_batchbuffer_require_space(batch, size);
 175
 176     assert(batch->ptr);
 177     memcpy(batch->ptr, data, size);
 178     batch->ptr += size;
 179 }
 180
 181 void
 182 intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
 183 {
 184     struct intel_driver_data *intel = batch->intel;
 185
 186     if (IS_GEN6(intel->device_id) ||
 187         IS_GEN7(intel->device_id) ||
 188         IS_GEN8(intel->device_id)) {
 189         if (batch->flag == I915_EXEC_RENDER) {
 190             if (IS_GEN8(intel->device_id)) {
 191                 BEGIN_BATCH(batch, 6);
 192                 OUT_BATCH(batch, CMD_PIPE_CONTROL | (6 - 2));
 193
 194                 OUT_BATCH(batch,
 195                           CMD_PIPE_CONTROL_WC_FLUSH |
 196                           CMD_PIPE_CONTROL_TC_FLUSH |
 197                           CMD_PIPE_CONTROL_DC_FLUSH |
 198                           CMD_PIPE_CONTROL_NOWRITE);
 199                 OUT_BATCH(batch, 0); /* write address */
 200                 OUT_BATCH(batch, 0);
 201                 OUT_BATCH(batch, 0); /* write data */
 202                 OUT_BATCH(batch, 0);
 203                 ADVANCE_BATCH(batch);
 204             } else if (IS_GEN6(intel->device_id)) {
 205                 assert(batch->wa_render_bo);
 206
 207                 BEGIN_BATCH(batch, 4 * 3);
 208
 209                 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
 210                 OUT_BATCH(batch,
 211                           CMD_PIPE_CONTROL_CS_STALL |
 212                           CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD);
 213                 OUT_BATCH(batch, 0); /* address */
 214                 OUT_BATCH(batch, 0); /* write data */
 215
 216                 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
 217                 OUT_BATCH(batch, CMD_PIPE_CONTROL_WRITE_QWORD);
 218                 OUT_RELOC(batch,
 219                           batch->wa_render_bo,
 220                           I915_GEM_DOMAIN_INSTRUCTION,
 221                           I915_GEM_DOMAIN_INSTRUCTION,
 222                           0);
 223                 OUT_BATCH(batch, 0); /* write data */
 224
 225                 /* now finally the _real flush */
 226                 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
 227                 OUT_BATCH(batch,
 228                           CMD_PIPE_CONTROL_WC_FLUSH |
 229                           CMD_PIPE_CONTROL_TC_FLUSH |
 230                           CMD_PIPE_CONTROL_NOWRITE);
 231                 OUT_BATCH(batch, 0); /* write address */
 232                 OUT_BATCH(batch, 0); /* write data */
 233                 ADVANCE_BATCH(batch);
 234             } else {
 235                 BEGIN_BATCH(batch, 4);
 236                 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
 237
 238                 OUT_BATCH(batch,
 239                           CMD_PIPE_CONTROL_WC_FLUSH |
 240                           CMD_PIPE_CONTROL_TC_FLUSH |
 241                           CMD_PIPE_CONTROL_DC_FLUSH |
 242                           CMD_PIPE_CONTROL_NOWRITE);
 243                 OUT_BATCH(batch, 0); /* write address */
 244                 OUT_BATCH(batch, 0); /* write data */
 245                 ADVANCE_BATCH(batch);
 246             }
 247
 248         } else {
 249             if (batch->flag == I915_EXEC_BLT) {
 250                 BEGIN_BLT_BATCH(batch, 4);
 251                 OUT_BLT_BATCH(batch, MI_FLUSH_DW);
 252                 OUT_BLT_BATCH(batch, 0);
 253                 OUT_BLT_BATCH(batch, 0);
 254                 OUT_BLT_BATCH(batch, 0);
 255                 ADVANCE_BLT_BATCH(batch);
 256             }else if (batch->flag == I915_EXEC_VEBOX) {
 257                 BEGIN_VEB_BATCH(batch, 4);
 258                 OUT_VEB_BATCH(batch, MI_FLUSH_DW);
 259                 OUT_VEB_BATCH(batch, 0);
 260                 OUT_VEB_BATCH(batch, 0);
 261                 OUT_VEB_BATCH(batch, 0);
 262                 ADVANCE_VEB_BATCH(batch);
 263             } else {
 264                 assert(batch->flag == I915_EXEC_BSD);
 265                 BEGIN_BCS_BATCH(batch, 4);
 266                 OUT_BCS_BATCH(batch, MI_FLUSH_DW | MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE);
 267                 OUT_BCS_BATCH(batch, 0);
 268                 OUT_BCS_BATCH(batch, 0);
 269                 OUT_BCS_BATCH(batch, 0);
 270                 ADVANCE_BCS_BATCH(batch);
 271             }
 272         }
 273     } else {
 274         if (batch->flag == I915_EXEC_RENDER) {
 275             BEGIN_BATCH(batch, 1);
 276             OUT_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
 277             ADVANCE_BATCH(batch);
 278          } else {
 279             assert(batch->flag == I915_EXEC_BSD);
 280             BEGIN_BCS_BATCH(batch, 1);
 281             OUT_BCS_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
 282             ADVANCE_BCS_BATCH(batch);
 283         }
 284     }
 285 }
 286
 287 void
 288 intel_batchbuffer_begin_batch(struct intel_batchbuffer *batch, int total)
 289 {
 290     batch->emit_total = total * 4;
 291     batch->emit_start = batch->ptr;
 292 }
 293
 294 void
 295 intel_batchbuffer_advance_batch(struct intel_batchbuffer *batch)
 296 {
 297     assert(batch->emit_total == (batch->ptr - batch->emit_start));
 298 }
 299
 300 void
 301 intel_batchbuffer_check_batchbuffer_flag(struct intel_batchbuffer *batch, int flag)
 302 {
 303     if (flag != I915_EXEC_RENDER &&
 304         flag != I915_EXEC_BLT &&
 305         flag != I915_EXEC_BSD &&
 306         flag != I915_EXEC_VEBOX)
 307         return;
 308
 309     if (batch->flag == flag)
 310         return;
 311
 312     intel_batchbuffer_flush(batch);
 313     batch->flag = flag;
 314 }
 315
 316 int
 317 intel_batchbuffer_check_free_space(struct intel_batchbuffer *batch, int size)
 318 {
 319     return intel_batchbuffer_space(batch) >= size;
 320 }
 321
 322 static void
 323 intel_batchbuffer_start_atomic_helper(struct intel_batchbuffer *batch,
 324                                       int flag,
 325                                       unsigned int size)
 326 {
 327     assert(!batch->atomic);
 328     intel_batchbuffer_check_batchbuffer_flag(batch, flag);
 329     intel_batchbuffer_require_space(batch, size);
 330     batch->atomic = 1;
 331 }
 332
 333 void
 334 intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size)
 335 {
 336     intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_RENDER, size);
 337 }
 338
 339 void
 340 intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch, unsigned int size)
 341 {
 342     intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BLT, size);
 343 }
 344
 345 void
 346 intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int size)
 347 {
 348     intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BSD, size);
 349 }
 350
 351 void
 352 intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch, unsigned int size)
 353 {
 354     intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_VEBOX, size);
 355 }
 356
 357
 358 void
 359 intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch)
 360 {
 361     assert(batch->atomic);
 362     batch->atomic = 0;
 363 }
 364
 365 int
 366 intel_batchbuffer_used_size(struct intel_batchbuffer *batch)
 367 {
 368     return batch->ptr - batch->map;
 369 }
 370
 371 void
 372 intel_batchbuffer_align(struct intel_batchbuffer *batch, unsigned int alignedment)
 373 {
 374     int used = batch->ptr - batch->map;
 375     int pad_size;
 376
 377     assert((alignedment & 3) == 0);
 378     pad_size = ALIGN(used, alignedment) - used;
 379     assert((pad_size & 3) == 0);
 380     assert(intel_batchbuffer_space(batch) >= pad_size);
 381
 382     while (pad_size >= 4) {
 383         intel_batchbuffer_emit_dword(batch, 0);
 384         pad_size -= 4;
 385     }
 386 }
 387