1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
32 #include "intel_batchbuffer.h"
34 #define MAX_BATCH_SIZE 0x400000
37 intel_batchbuffer_reset(struct intel_batchbuffer *batch, int buffer_size)
39 struct intel_driver_data *intel = batch->intel;
40 int batch_size = buffer_size;
42 assert(batch->flag == I915_EXEC_RENDER ||
43 batch->flag == I915_EXEC_BLT ||
44 batch->flag == I915_EXEC_BSD ||
45 batch->flag == I915_EXEC_VEBOX);
47 dri_bo_unreference(batch->buffer);
48 batch->buffer = dri_bo_alloc(intel->bufmgr,
52 assert(batch->buffer);
53 dri_bo_map(batch->buffer, 1);
54 assert(batch->buffer->virtual);
55 batch->map = batch->buffer->virtual;
56 batch->size = batch_size;
57 batch->ptr = batch->map;
62 intel_batchbuffer_space(struct intel_batchbuffer *batch)
64 return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map);
68 struct intel_batchbuffer *
69 intel_batchbuffer_new(struct intel_driver_data *intel, int flag, int buffer_size)
71 struct intel_batchbuffer *batch = calloc(1, sizeof(*batch));
72 assert(flag == I915_EXEC_RENDER ||
73 flag == I915_EXEC_BSD ||
74 flag == I915_EXEC_BLT ||
75 flag == I915_EXEC_VEBOX);
77 if (!buffer_size || buffer_size < BATCH_SIZE) {
78 buffer_size = BATCH_SIZE;
81 /* the buffer size can't exceed 4M */
82 if (buffer_size > MAX_BATCH_SIZE) {
83 buffer_size = MAX_BATCH_SIZE;
88 batch->run = drm_intel_bo_mrb_exec;
90 if (IS_GEN6(intel->device_id) &&
91 flag == I915_EXEC_RENDER)
92 batch->wa_render_bo = dri_bo_alloc(intel->bufmgr,
97 batch->wa_render_bo = NULL;
99 intel_batchbuffer_reset(batch, buffer_size);
104 void intel_batchbuffer_free(struct intel_batchbuffer *batch)
107 dri_bo_unmap(batch->buffer);
111 dri_bo_unreference(batch->buffer);
112 dri_bo_unreference(batch->wa_render_bo);
117 intel_batchbuffer_flush(struct intel_batchbuffer *batch)
119 unsigned int used = batch->ptr - batch->map;
125 if ((used & 4) == 0) {
126 *(unsigned int*)batch->ptr = 0;
130 *(unsigned int*)batch->ptr = MI_BATCH_BUFFER_END;
132 dri_bo_unmap(batch->buffer);
133 used = batch->ptr - batch->map;
134 batch->run(batch->buffer, used, 0, 0, 0, batch->flag);
135 intel_batchbuffer_reset(batch, batch->size);
139 intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, unsigned int x)
141 assert(intel_batchbuffer_space(batch) >= 4);
142 *(unsigned int *)batch->ptr = x;
147 intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, dri_bo *bo,
148 uint32_t read_domains, uint32_t write_domains,
151 assert(batch->ptr - batch->map < batch->size);
152 dri_bo_emit_reloc(batch->buffer, read_domains, write_domains,
153 delta, batch->ptr - batch->map, bo);
154 intel_batchbuffer_emit_dword(batch, bo->offset + delta);
158 intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
161 assert(size < batch->size - 8);
163 if (intel_batchbuffer_space(batch) < size) {
164 intel_batchbuffer_flush(batch);
169 intel_batchbuffer_data(struct intel_batchbuffer *batch,
173 assert((size & 3) == 0);
174 intel_batchbuffer_require_space(batch, size);
177 memcpy(batch->ptr, data, size);
182 intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
184 struct intel_driver_data *intel = batch->intel;
186 if (IS_GEN6(intel->device_id) ||
187 IS_GEN7(intel->device_id) ||
188 IS_GEN8(intel->device_id)) {
189 if (batch->flag == I915_EXEC_RENDER) {
190 if (IS_GEN8(intel->device_id)) {
191 BEGIN_BATCH(batch, 6);
192 OUT_BATCH(batch, CMD_PIPE_CONTROL | (6 - 2));
195 CMD_PIPE_CONTROL_WC_FLUSH |
196 CMD_PIPE_CONTROL_TC_FLUSH |
197 CMD_PIPE_CONTROL_DC_FLUSH |
198 CMD_PIPE_CONTROL_NOWRITE);
199 OUT_BATCH(batch, 0); /* write address */
201 OUT_BATCH(batch, 0); /* write data */
203 ADVANCE_BATCH(batch);
204 } else if (IS_GEN6(intel->device_id)) {
205 assert(batch->wa_render_bo);
207 BEGIN_BATCH(batch, 4 * 3);
209 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
211 CMD_PIPE_CONTROL_CS_STALL |
212 CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD);
213 OUT_BATCH(batch, 0); /* address */
214 OUT_BATCH(batch, 0); /* write data */
216 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
217 OUT_BATCH(batch, CMD_PIPE_CONTROL_WRITE_QWORD);
220 I915_GEM_DOMAIN_INSTRUCTION,
221 I915_GEM_DOMAIN_INSTRUCTION,
223 OUT_BATCH(batch, 0); /* write data */
225 /* now finally the _real flush */
226 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
228 CMD_PIPE_CONTROL_WC_FLUSH |
229 CMD_PIPE_CONTROL_TC_FLUSH |
230 CMD_PIPE_CONTROL_NOWRITE);
231 OUT_BATCH(batch, 0); /* write address */
232 OUT_BATCH(batch, 0); /* write data */
233 ADVANCE_BATCH(batch);
235 BEGIN_BATCH(batch, 4);
236 OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
239 CMD_PIPE_CONTROL_WC_FLUSH |
240 CMD_PIPE_CONTROL_TC_FLUSH |
241 CMD_PIPE_CONTROL_DC_FLUSH |
242 CMD_PIPE_CONTROL_NOWRITE);
243 OUT_BATCH(batch, 0); /* write address */
244 OUT_BATCH(batch, 0); /* write data */
245 ADVANCE_BATCH(batch);
249 if (batch->flag == I915_EXEC_BLT) {
250 BEGIN_BLT_BATCH(batch, 4);
251 OUT_BLT_BATCH(batch, MI_FLUSH_DW);
252 OUT_BLT_BATCH(batch, 0);
253 OUT_BLT_BATCH(batch, 0);
254 OUT_BLT_BATCH(batch, 0);
255 ADVANCE_BLT_BATCH(batch);
256 }else if (batch->flag == I915_EXEC_VEBOX) {
257 BEGIN_VEB_BATCH(batch, 4);
258 OUT_VEB_BATCH(batch, MI_FLUSH_DW);
259 OUT_VEB_BATCH(batch, 0);
260 OUT_VEB_BATCH(batch, 0);
261 OUT_VEB_BATCH(batch, 0);
262 ADVANCE_VEB_BATCH(batch);
264 assert(batch->flag == I915_EXEC_BSD);
265 BEGIN_BCS_BATCH(batch, 4);
266 OUT_BCS_BATCH(batch, MI_FLUSH_DW | MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE);
267 OUT_BCS_BATCH(batch, 0);
268 OUT_BCS_BATCH(batch, 0);
269 OUT_BCS_BATCH(batch, 0);
270 ADVANCE_BCS_BATCH(batch);
274 if (batch->flag == I915_EXEC_RENDER) {
275 BEGIN_BATCH(batch, 1);
276 OUT_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
277 ADVANCE_BATCH(batch);
279 assert(batch->flag == I915_EXEC_BSD);
280 BEGIN_BCS_BATCH(batch, 1);
281 OUT_BCS_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
282 ADVANCE_BCS_BATCH(batch);
288 intel_batchbuffer_begin_batch(struct intel_batchbuffer *batch, int total)
290 batch->emit_total = total * 4;
291 batch->emit_start = batch->ptr;
295 intel_batchbuffer_advance_batch(struct intel_batchbuffer *batch)
297 assert(batch->emit_total == (batch->ptr - batch->emit_start));
301 intel_batchbuffer_check_batchbuffer_flag(struct intel_batchbuffer *batch, int flag)
303 if (flag != I915_EXEC_RENDER &&
304 flag != I915_EXEC_BLT &&
305 flag != I915_EXEC_BSD &&
306 flag != I915_EXEC_VEBOX)
309 if (batch->flag == flag)
312 intel_batchbuffer_flush(batch);
317 intel_batchbuffer_check_free_space(struct intel_batchbuffer *batch, int size)
319 return intel_batchbuffer_space(batch) >= size;
323 intel_batchbuffer_start_atomic_helper(struct intel_batchbuffer *batch,
327 assert(!batch->atomic);
328 intel_batchbuffer_check_batchbuffer_flag(batch, flag);
329 intel_batchbuffer_require_space(batch, size);
334 intel_batchbuffer_start_atomic(struct intel_batchbuffer *batch, unsigned int size)
336 intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_RENDER, size);
340 intel_batchbuffer_start_atomic_blt(struct intel_batchbuffer *batch, unsigned int size)
342 intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BLT, size);
346 intel_batchbuffer_start_atomic_bcs(struct intel_batchbuffer *batch, unsigned int size)
348 intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_BSD, size);
352 intel_batchbuffer_start_atomic_veb(struct intel_batchbuffer *batch, unsigned int size)
354 intel_batchbuffer_start_atomic_helper(batch, I915_EXEC_VEBOX, size);
359 intel_batchbuffer_end_atomic(struct intel_batchbuffer *batch)
361 assert(batch->atomic);
366 intel_batchbuffer_used_size(struct intel_batchbuffer *batch)
368 return batch->ptr - batch->map;
372 intel_batchbuffer_align(struct intel_batchbuffer *batch, unsigned int alignedment)
374 int used = batch->ptr - batch->map;
377 assert((alignedment & 3) == 0);
378 pad_size = ALIGN(used, alignedment) - used;
379 assert((pad_size & 3) == 0);
380 assert(intel_batchbuffer_space(batch) >= pad_size);
382 while (pad_size >= 4) {
383 intel_batchbuffer_emit_dword(batch, 0);