1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
37 #include "src/ia32/assembler-ia32.h"
41 #if V8_TARGET_ARCH_IA32
44 #include <intrin.h> // _xgetbv()
47 #include <sys/sysctl.h>
50 #include "src/base/bits.h"
51 #include "src/base/cpu.h"
52 #include "src/disassembler.h"
53 #include "src/macro-assembler.h"
59 // -----------------------------------------------------------------------------
60 // Implementation of CpuFeatures
66 V8_INLINE uint64_t _xgetbv(unsigned int xcr) {
68 // Check xgetbv; this uses a .byte sequence instead of the instruction
69 // directly because older assemblers do not include support for xgetbv and
70 // there is no easy way to conditionally compile based on the assembler
72 __asm__ volatile(".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
73 return static_cast<uint64_t>(eax) | (static_cast<uint64_t>(edx) << 32);
76 #define _XCR_XFEATURE_ENABLED_MASK 0
78 #endif // !V8_LIBC_MSVCRT
81 bool OSHasAVXSupport() {
83 // Mac OS X up to 10.9 has a bug where AVX transitions were indeed being
84 // caused by ISRs, so we detect that here and disable AVX in that case.
86 size_t buffer_size = arraysize(buffer);
87 int ctl_name[] = {CTL_KERN, KERN_OSRELEASE};
88 if (sysctl(ctl_name, 2, buffer, &buffer_size, nullptr, 0) != 0) {
89 V8_Fatal(__FILE__, __LINE__, "V8 failed to get kernel version");
91 // The buffer now contains a string of the form XX.YY.ZZ, where
92 // XX is the major kernel version component.
93 char* period_pos = strchr(buffer, '.');
94 DCHECK_NOT_NULL(period_pos);
96 long kernel_version_major = strtol(buffer, nullptr, 10); // NOLINT
97 if (kernel_version_major <= 13) return false;
98 #endif // V8_OS_MACOSX
99 // Check whether OS claims to support AVX.
100 uint64_t feature_mask = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
101 return (feature_mask & 0x6) == 0x6;
107 void CpuFeatures::ProbeImpl(bool cross_compile) {
109 CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
110 CHECK(cpu.has_cmov()); // CMOV support is mandatory.
112 // Only use statically determined features for cross compile (snapshot).
113 if (cross_compile) return;
115 if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
116 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
117 if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
119 supported_ |= 1u << AVX;
121 if (cpu.has_fma3() && FLAG_enable_fma3 && cpu.has_osxsave() &&
123 supported_ |= 1u << FMA3;
125 if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
126 if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
127 if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;
128 if (cpu.has_popcnt() && FLAG_enable_popcnt) supported_ |= 1u << POPCNT;
129 if (strcmp(FLAG_mcpu, "auto") == 0) {
130 if (cpu.is_atom()) supported_ |= 1u << ATOM;
131 } else if (strcmp(FLAG_mcpu, "atom") == 0) {
132 supported_ |= 1u << ATOM;
137 void CpuFeatures::PrintTarget() { }
138 void CpuFeatures::PrintFeatures() {
140 "SSE3=%d SSE4_1=%d AVX=%d FMA3=%d BMI1=%d BMI2=%d LZCNT=%d POPCNT=%d "
142 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
143 CpuFeatures::IsSupported(AVX), CpuFeatures::IsSupported(FMA3),
144 CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2),
145 CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT),
146 CpuFeatures::IsSupported(ATOM));
150 // -----------------------------------------------------------------------------
151 // Implementation of Displacement
153 void Displacement::init(Label* L, Type type) {
154 DCHECK(!L->is_bound());
156 if (L->is_linked()) {
158 DCHECK(next > 0); // Displacements must be at positions > 0
160 // Ensure that we _never_ overflow the next field.
161 DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
162 data_ = NextField::encode(next) | TypeField::encode(type);
166 // -----------------------------------------------------------------------------
167 // Implementation of RelocInfo
170 const int RelocInfo::kApplyMask =
171 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
172 1 << RelocInfo::INTERNAL_REFERENCE | 1 << RelocInfo::CODE_AGE_SEQUENCE |
173 RelocInfo::kDebugBreakSlotMask;
176 bool RelocInfo::IsCodedSpecially() {
177 // The deserializer needs to know whether a pointer is specially coded. Being
178 // specially coded on IA32 means that it is a relative address, as used by
179 // branch instructions. These are also the ones that need changing when a
180 // code object moves.
181 return (1 << rmode_) & kApplyMask;
185 bool RelocInfo::IsInConstantPool() {
190 // Patch the code at the current PC with a call to the target address.
191 // Additional guard int3 instructions can be added if required.
192 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
193 // Call instruction takes up 5 bytes and int3 takes up one byte.
194 static const int kCallCodeSize = 5;
195 int code_size = kCallCodeSize + guard_bytes;
197 // Create a code patcher.
198 CodePatcher patcher(pc_, code_size);
200 // Add a label for checking the size of the code used for returning.
202 Label check_codesize;
203 patcher.masm()->bind(&check_codesize);
207 patcher.masm()->call(target, RelocInfo::NONE32);
209 // Check that the size of the code generated is as expected.
210 DCHECK_EQ(kCallCodeSize,
211 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
213 // Add the requested number of int3 instructions after the call.
214 DCHECK_GE(guard_bytes, 0);
215 for (int i = 0; i < guard_bytes; i++) {
216 patcher.masm()->int3();
221 // -----------------------------------------------------------------------------
222 // Implementation of Operand
224 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
226 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
229 if (base.is(esp)) set_sib(times_1, esp, base);
230 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
233 if (base.is(esp)) set_sib(times_1, esp, base);
238 if (base.is(esp)) set_sib(times_1, esp, base);
239 set_dispr(disp, rmode);
244 Operand::Operand(Register base,
248 RelocInfo::Mode rmode) {
249 DCHECK(!index.is(esp)); // illegal addressing mode
250 // [base + index*scale + disp/r]
251 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
252 // [base + index*scale]
254 set_sib(scale, index, base);
255 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
256 // [base + index*scale + disp8]
258 set_sib(scale, index, base);
261 // [base + index*scale + disp/r]
263 set_sib(scale, index, base);
264 set_dispr(disp, rmode);
269 Operand::Operand(Register index,
272 RelocInfo::Mode rmode) {
273 DCHECK(!index.is(esp)); // illegal addressing mode
274 // [index*scale + disp/r]
276 set_sib(scale, index, ebp);
277 set_dispr(disp, rmode);
281 bool Operand::is_reg(Register reg) const {
282 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
283 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
287 bool Operand::is_reg_only() const {
288 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
292 Register Operand::reg() const {
293 DCHECK(is_reg_only());
294 return Register::from_code(buf_[0] & 0x07);
298 // -----------------------------------------------------------------------------
299 // Implementation of Assembler.
301 // Emit a single byte. Must always be inlined.
306 #ifdef GENERATED_CODE_COVERAGE
307 static void InitCoverageLog();
310 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
311 : AssemblerBase(isolate, buffer, buffer_size),
312 positions_recorder_(this) {
313 // Clear the buffer in debug mode unless it was provided by the
314 // caller in which case we can't be sure it's okay to overwrite
315 // existing code in it; see CodePatcher::CodePatcher(...).
318 memset(buffer_, 0xCC, buffer_size_); // int3
322 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
324 #ifdef GENERATED_CODE_COVERAGE
330 void Assembler::GetCode(CodeDesc* desc) {
331 // Finalize code (at this point overflow() may be true, but the gap ensures
332 // that we are still not overlapping instructions and relocation info).
333 reloc_info_writer.Finish();
334 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
335 // Set up code descriptor.
336 desc->buffer = buffer_;
337 desc->buffer_size = buffer_size_;
338 desc->instr_size = pc_offset();
339 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
344 void Assembler::Align(int m) {
345 DCHECK(base::bits::IsPowerOfTwo32(m));
347 int addr = pc_offset();
348 Nop((m - (addr & mask)) & mask);
352 bool Assembler::IsNop(Address addr) {
354 while (*a == 0x66) a++;
355 if (*a == 0x90) return true;
356 if (a[0] == 0xf && a[1] == 0x1f) return true;
361 void Assembler::Nop(int bytes) {
362 EnsureSpace ensure_space(this);
364 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
426 void Assembler::CodeTargetAlign() {
427 Align(16); // Preferred alignment of jump targets on ia32.
431 void Assembler::cpuid() {
432 EnsureSpace ensure_space(this);
438 void Assembler::pushad() {
439 EnsureSpace ensure_space(this);
444 void Assembler::popad() {
445 EnsureSpace ensure_space(this);
450 void Assembler::pushfd() {
451 EnsureSpace ensure_space(this);
456 void Assembler::popfd() {
457 EnsureSpace ensure_space(this);
462 void Assembler::push(const Immediate& x) {
463 EnsureSpace ensure_space(this);
474 void Assembler::push_imm32(int32_t imm32) {
475 EnsureSpace ensure_space(this);
481 void Assembler::push(Register src) {
482 EnsureSpace ensure_space(this);
483 EMIT(0x50 | src.code());
487 void Assembler::push(const Operand& src) {
488 EnsureSpace ensure_space(this);
490 emit_operand(esi, src);
494 void Assembler::pop(Register dst) {
495 DCHECK(reloc_info_writer.last_pc() != NULL);
496 EnsureSpace ensure_space(this);
497 EMIT(0x58 | dst.code());
501 void Assembler::pop(const Operand& dst) {
502 EnsureSpace ensure_space(this);
504 emit_operand(eax, dst);
508 void Assembler::enter(const Immediate& size) {
509 EnsureSpace ensure_space(this);
516 void Assembler::leave() {
517 EnsureSpace ensure_space(this);
522 void Assembler::mov_b(Register dst, const Operand& src) {
523 CHECK(dst.is_byte_register());
524 EnsureSpace ensure_space(this);
526 emit_operand(dst, src);
530 void Assembler::mov_b(const Operand& dst, const Immediate& src) {
531 EnsureSpace ensure_space(this);
533 emit_operand(eax, dst);
534 EMIT(static_cast<int8_t>(src.x_));
538 void Assembler::mov_b(const Operand& dst, Register src) {
539 CHECK(src.is_byte_register());
540 EnsureSpace ensure_space(this);
542 emit_operand(src, dst);
546 void Assembler::mov_w(Register dst, const Operand& src) {
547 EnsureSpace ensure_space(this);
550 emit_operand(dst, src);
554 void Assembler::mov_w(const Operand& dst, Register src) {
555 EnsureSpace ensure_space(this);
558 emit_operand(src, dst);
562 void Assembler::mov_w(const Operand& dst, const Immediate& src) {
563 EnsureSpace ensure_space(this);
566 emit_operand(eax, dst);
567 EMIT(static_cast<int8_t>(src.x_ & 0xff));
568 EMIT(static_cast<int8_t>(src.x_ >> 8));
572 void Assembler::mov(Register dst, int32_t imm32) {
573 EnsureSpace ensure_space(this);
574 EMIT(0xB8 | dst.code());
579 void Assembler::mov(Register dst, const Immediate& x) {
580 EnsureSpace ensure_space(this);
581 EMIT(0xB8 | dst.code());
586 void Assembler::mov(Register dst, Handle<Object> handle) {
587 EnsureSpace ensure_space(this);
588 EMIT(0xB8 | dst.code());
593 void Assembler::mov(Register dst, const Operand& src) {
594 EnsureSpace ensure_space(this);
596 emit_operand(dst, src);
600 void Assembler::mov(Register dst, Register src) {
601 EnsureSpace ensure_space(this);
603 EMIT(0xC0 | src.code() << 3 | dst.code());
607 void Assembler::mov(const Operand& dst, const Immediate& x) {
608 EnsureSpace ensure_space(this);
610 emit_operand(eax, dst);
615 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
616 EnsureSpace ensure_space(this);
618 emit_operand(eax, dst);
623 void Assembler::mov(const Operand& dst, Register src) {
624 EnsureSpace ensure_space(this);
626 emit_operand(src, dst);
630 void Assembler::movsx_b(Register dst, const Operand& src) {
631 EnsureSpace ensure_space(this);
634 emit_operand(dst, src);
638 void Assembler::movsx_w(Register dst, const Operand& src) {
639 EnsureSpace ensure_space(this);
642 emit_operand(dst, src);
646 void Assembler::movzx_b(Register dst, const Operand& src) {
647 EnsureSpace ensure_space(this);
650 emit_operand(dst, src);
654 void Assembler::movzx_w(Register dst, const Operand& src) {
655 EnsureSpace ensure_space(this);
658 emit_operand(dst, src);
662 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
663 EnsureSpace ensure_space(this);
664 // Opcode: 0f 40 + cc /r.
667 emit_operand(dst, src);
671 void Assembler::cld() {
672 EnsureSpace ensure_space(this);
677 void Assembler::rep_movs() {
678 EnsureSpace ensure_space(this);
684 void Assembler::rep_stos() {
685 EnsureSpace ensure_space(this);
691 void Assembler::stos() {
692 EnsureSpace ensure_space(this);
697 void Assembler::xchg(Register dst, Register src) {
698 EnsureSpace ensure_space(this);
699 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
700 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
703 EMIT(0xC0 | src.code() << 3 | dst.code());
708 void Assembler::xchg(Register dst, const Operand& src) {
709 EnsureSpace ensure_space(this);
711 emit_operand(dst, src);
715 void Assembler::adc(Register dst, int32_t imm32) {
716 EnsureSpace ensure_space(this);
717 emit_arith(2, Operand(dst), Immediate(imm32));
721 void Assembler::adc(Register dst, const Operand& src) {
722 EnsureSpace ensure_space(this);
724 emit_operand(dst, src);
728 void Assembler::add(Register dst, const Operand& src) {
729 EnsureSpace ensure_space(this);
731 emit_operand(dst, src);
735 void Assembler::add(const Operand& dst, Register src) {
736 EnsureSpace ensure_space(this);
738 emit_operand(src, dst);
742 void Assembler::add(const Operand& dst, const Immediate& x) {
743 DCHECK(reloc_info_writer.last_pc() != NULL);
744 EnsureSpace ensure_space(this);
745 emit_arith(0, dst, x);
749 void Assembler::and_(Register dst, int32_t imm32) {
750 and_(dst, Immediate(imm32));
754 void Assembler::and_(Register dst, const Immediate& x) {
755 EnsureSpace ensure_space(this);
756 emit_arith(4, Operand(dst), x);
760 void Assembler::and_(Register dst, const Operand& src) {
761 EnsureSpace ensure_space(this);
763 emit_operand(dst, src);
767 void Assembler::and_(const Operand& dst, const Immediate& x) {
768 EnsureSpace ensure_space(this);
769 emit_arith(4, dst, x);
773 void Assembler::and_(const Operand& dst, Register src) {
774 EnsureSpace ensure_space(this);
776 emit_operand(src, dst);
780 void Assembler::cmpb(const Operand& op, int8_t imm8) {
781 EnsureSpace ensure_space(this);
782 if (op.is_reg(eax)) {
786 emit_operand(edi, op); // edi == 7
792 void Assembler::cmpb(const Operand& op, Register reg) {
793 CHECK(reg.is_byte_register());
794 EnsureSpace ensure_space(this);
796 emit_operand(reg, op);
800 void Assembler::cmpb(Register reg, const Operand& op) {
801 CHECK(reg.is_byte_register());
802 EnsureSpace ensure_space(this);
804 emit_operand(reg, op);
808 void Assembler::cmpw(const Operand& op, Immediate imm16) {
809 DCHECK(imm16.is_int16());
810 EnsureSpace ensure_space(this);
813 emit_operand(edi, op);
818 void Assembler::cmp(Register reg, int32_t imm32) {
819 EnsureSpace ensure_space(this);
820 emit_arith(7, Operand(reg), Immediate(imm32));
824 void Assembler::cmp(Register reg, Handle<Object> handle) {
825 EnsureSpace ensure_space(this);
826 emit_arith(7, Operand(reg), Immediate(handle));
830 void Assembler::cmp(Register reg, const Operand& op) {
831 EnsureSpace ensure_space(this);
833 emit_operand(reg, op);
837 void Assembler::cmp(const Operand& op, const Immediate& imm) {
838 EnsureSpace ensure_space(this);
839 emit_arith(7, op, imm);
843 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
844 EnsureSpace ensure_space(this);
845 emit_arith(7, op, Immediate(handle));
849 void Assembler::cmpb_al(const Operand& op) {
850 EnsureSpace ensure_space(this);
851 EMIT(0x38); // CMP r/m8, r8
852 emit_operand(eax, op); // eax has same code as register al.
856 void Assembler::cmpw_ax(const Operand& op) {
857 EnsureSpace ensure_space(this);
859 EMIT(0x39); // CMP r/m16, r16
860 emit_operand(eax, op); // eax has same code as register ax.
864 void Assembler::dec_b(Register dst) {
865 CHECK(dst.is_byte_register());
866 EnsureSpace ensure_space(this);
868 EMIT(0xC8 | dst.code());
872 void Assembler::dec_b(const Operand& dst) {
873 EnsureSpace ensure_space(this);
875 emit_operand(ecx, dst);
879 void Assembler::dec(Register dst) {
880 EnsureSpace ensure_space(this);
881 EMIT(0x48 | dst.code());
885 void Assembler::dec(const Operand& dst) {
886 EnsureSpace ensure_space(this);
888 emit_operand(ecx, dst);
892 void Assembler::cdq() {
893 EnsureSpace ensure_space(this);
898 void Assembler::idiv(const Operand& src) {
899 EnsureSpace ensure_space(this);
901 emit_operand(edi, src);
905 void Assembler::div(const Operand& src) {
906 EnsureSpace ensure_space(this);
908 emit_operand(esi, src);
912 void Assembler::imul(Register reg) {
913 EnsureSpace ensure_space(this);
915 EMIT(0xE8 | reg.code());
919 void Assembler::imul(Register dst, const Operand& src) {
920 EnsureSpace ensure_space(this);
923 emit_operand(dst, src);
927 void Assembler::imul(Register dst, Register src, int32_t imm32) {
928 imul(dst, Operand(src), imm32);
932 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
933 EnsureSpace ensure_space(this);
934 if (is_int8(imm32)) {
936 emit_operand(dst, src);
940 emit_operand(dst, src);
946 void Assembler::inc(Register dst) {
947 EnsureSpace ensure_space(this);
948 EMIT(0x40 | dst.code());
952 void Assembler::inc(const Operand& dst) {
953 EnsureSpace ensure_space(this);
955 emit_operand(eax, dst);
959 void Assembler::lea(Register dst, const Operand& src) {
960 EnsureSpace ensure_space(this);
962 emit_operand(dst, src);
966 void Assembler::mul(Register src) {
967 EnsureSpace ensure_space(this);
969 EMIT(0xE0 | src.code());
973 void Assembler::neg(Register dst) {
974 EnsureSpace ensure_space(this);
976 EMIT(0xD8 | dst.code());
980 void Assembler::neg(const Operand& dst) {
981 EnsureSpace ensure_space(this);
983 emit_operand(ebx, dst);
987 void Assembler::not_(Register dst) {
988 EnsureSpace ensure_space(this);
990 EMIT(0xD0 | dst.code());
994 void Assembler::not_(const Operand& dst) {
995 EnsureSpace ensure_space(this);
997 emit_operand(edx, dst);
1001 void Assembler::or_(Register dst, int32_t imm32) {
1002 EnsureSpace ensure_space(this);
1003 emit_arith(1, Operand(dst), Immediate(imm32));
1007 void Assembler::or_(Register dst, const Operand& src) {
1008 EnsureSpace ensure_space(this);
1010 emit_operand(dst, src);
1014 void Assembler::or_(const Operand& dst, const Immediate& x) {
1015 EnsureSpace ensure_space(this);
1016 emit_arith(1, dst, x);
1020 void Assembler::or_(const Operand& dst, Register src) {
1021 EnsureSpace ensure_space(this);
1023 emit_operand(src, dst);
1027 void Assembler::rcl(Register dst, uint8_t imm8) {
1028 EnsureSpace ensure_space(this);
1029 DCHECK(is_uint5(imm8)); // illegal shift count
1032 EMIT(0xD0 | dst.code());
1035 EMIT(0xD0 | dst.code());
1041 void Assembler::rcr(Register dst, uint8_t imm8) {
1042 EnsureSpace ensure_space(this);
1043 DCHECK(is_uint5(imm8)); // illegal shift count
1046 EMIT(0xD8 | dst.code());
1049 EMIT(0xD8 | dst.code());
1055 void Assembler::ror(const Operand& dst, uint8_t imm8) {
1056 EnsureSpace ensure_space(this);
1057 DCHECK(is_uint5(imm8)); // illegal shift count
1060 emit_operand(ecx, dst);
1063 emit_operand(ecx, dst);
1069 void Assembler::ror_cl(const Operand& dst) {
1070 EnsureSpace ensure_space(this);
1072 emit_operand(ecx, dst);
1076 void Assembler::sar(const Operand& dst, uint8_t imm8) {
1077 EnsureSpace ensure_space(this);
1078 DCHECK(is_uint5(imm8)); // illegal shift count
1081 emit_operand(edi, dst);
1084 emit_operand(edi, dst);
1090 void Assembler::sar_cl(const Operand& dst) {
1091 EnsureSpace ensure_space(this);
1093 emit_operand(edi, dst);
1097 void Assembler::sbb(Register dst, const Operand& src) {
1098 EnsureSpace ensure_space(this);
1100 emit_operand(dst, src);
1104 void Assembler::shld(Register dst, const Operand& src) {
1105 EnsureSpace ensure_space(this);
1108 emit_operand(dst, src);
1112 void Assembler::shl(const Operand& dst, uint8_t imm8) {
1113 EnsureSpace ensure_space(this);
1114 DCHECK(is_uint5(imm8)); // illegal shift count
1117 emit_operand(esp, dst);
1120 emit_operand(esp, dst);
1126 void Assembler::shl_cl(const Operand& dst) {
1127 EnsureSpace ensure_space(this);
1129 emit_operand(esp, dst);
1133 void Assembler::shrd(Register dst, const Operand& src) {
1134 EnsureSpace ensure_space(this);
1137 emit_operand(dst, src);
1141 void Assembler::shr(const Operand& dst, uint8_t imm8) {
1142 EnsureSpace ensure_space(this);
1143 DCHECK(is_uint5(imm8)); // illegal shift count
1146 emit_operand(ebp, dst);
1149 emit_operand(ebp, dst);
1155 void Assembler::shr_cl(const Operand& dst) {
1156 EnsureSpace ensure_space(this);
1158 emit_operand(ebp, dst);
1162 void Assembler::sub(const Operand& dst, const Immediate& x) {
1163 EnsureSpace ensure_space(this);
1164 emit_arith(5, dst, x);
1168 void Assembler::sub(Register dst, const Operand& src) {
1169 EnsureSpace ensure_space(this);
1171 emit_operand(dst, src);
1175 void Assembler::sub(const Operand& dst, Register src) {
1176 EnsureSpace ensure_space(this);
1178 emit_operand(src, dst);
1182 void Assembler::test(Register reg, const Immediate& imm) {
1183 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1184 test_b(reg, imm.x_);
1188 EnsureSpace ensure_space(this);
1189 // This is not using emit_arith because test doesn't support
1190 // sign-extension of 8-bit operands.
1195 EMIT(0xC0 | reg.code());
1201 void Assembler::test(Register reg, const Operand& op) {
1202 EnsureSpace ensure_space(this);
1204 emit_operand(reg, op);
1208 void Assembler::test_b(Register reg, const Operand& op) {
1209 CHECK(reg.is_byte_register());
1210 EnsureSpace ensure_space(this);
1212 emit_operand(reg, op);
1216 void Assembler::test(const Operand& op, const Immediate& imm) {
1217 if (op.is_reg_only()) {
1218 test(op.reg(), imm);
1221 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1222 return test_b(op, imm.x_);
1224 EnsureSpace ensure_space(this);
1226 emit_operand(eax, op);
1231 void Assembler::test_b(Register reg, uint8_t imm8) {
1232 EnsureSpace ensure_space(this);
1233 // Only use test against byte for registers that have a byte
1234 // variant: eax, ebx, ecx, and edx.
1238 } else if (reg.is_byte_register()) {
1239 emit_arith_b(0xF6, 0xC0, reg, imm8);
1242 EMIT(0xC0 | reg.code());
1248 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1249 if (op.is_reg_only()) {
1250 test_b(op.reg(), imm8);
1253 EnsureSpace ensure_space(this);
1255 emit_operand(eax, op);
1260 void Assembler::xor_(Register dst, int32_t imm32) {
1261 EnsureSpace ensure_space(this);
1262 emit_arith(6, Operand(dst), Immediate(imm32));
1266 void Assembler::xor_(Register dst, const Operand& src) {
1267 EnsureSpace ensure_space(this);
1269 emit_operand(dst, src);
1273 void Assembler::xor_(const Operand& dst, Register src) {
1274 EnsureSpace ensure_space(this);
1276 emit_operand(src, dst);
1280 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1281 EnsureSpace ensure_space(this);
1282 emit_arith(6, dst, x);
1286 void Assembler::bt(const Operand& dst, Register src) {
1287 EnsureSpace ensure_space(this);
1290 emit_operand(src, dst);
1294 void Assembler::bts(const Operand& dst, Register src) {
1295 EnsureSpace ensure_space(this);
1298 emit_operand(src, dst);
1302 void Assembler::bsr(Register dst, const Operand& src) {
1303 EnsureSpace ensure_space(this);
1306 emit_operand(dst, src);
1310 void Assembler::hlt() {
1311 EnsureSpace ensure_space(this);
1316 void Assembler::int3() {
1317 EnsureSpace ensure_space(this);
1322 void Assembler::nop() {
1323 EnsureSpace ensure_space(this);
1328 void Assembler::ret(int imm16) {
1329 EnsureSpace ensure_space(this);
1330 DCHECK(is_uint16(imm16));
1336 EMIT((imm16 >> 8) & 0xFF);
1341 void Assembler::ud2() {
1342 EnsureSpace ensure_space(this);
1348 // Labels refer to positions in the (to be) generated code.
1349 // There are bound, linked, and unused labels.
1351 // Bound labels refer to known positions in the already
1352 // generated code. pos() is the position the label refers to.
1354 // Linked labels refer to unknown positions in the code
1355 // to be generated; pos() is the position of the 32bit
1356 // Displacement of the last instruction using the label.
1359 void Assembler::print(Label* L) {
1360 if (L->is_unused()) {
1361 PrintF("unused label\n");
1362 } else if (L->is_bound()) {
1363 PrintF("bound label to %d\n", L->pos());
1364 } else if (L->is_linked()) {
1366 PrintF("unbound label");
1367 while (l.is_linked()) {
1368 Displacement disp = disp_at(&l);
1369 PrintF("@ %d ", l.pos());
1375 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1380 void Assembler::bind_to(Label* L, int pos) {
1381 EnsureSpace ensure_space(this);
1382 DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1383 while (L->is_linked()) {
1384 Displacement disp = disp_at(L);
1385 int fixup_pos = L->pos();
1386 if (disp.type() == Displacement::CODE_ABSOLUTE) {
1387 long_at_put(fixup_pos, reinterpret_cast<int>(buffer_ + pos));
1388 internal_reference_positions_.push_back(fixup_pos);
1389 } else if (disp.type() == Displacement::CODE_RELATIVE) {
1390 // Relative to Code* heap object pointer.
1391 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1393 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1394 DCHECK(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1396 // Relative address, relative to point after address.
1397 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1398 long_at_put(fixup_pos, imm32);
1402 while (L->is_near_linked()) {
1403 int fixup_pos = L->near_link_pos();
1404 int offset_to_next =
1405 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1406 DCHECK(offset_to_next <= 0);
1407 // Relative address, relative to point after address.
1408 int disp = pos - fixup_pos - sizeof(int8_t);
1409 CHECK(0 <= disp && disp <= 127);
1410 set_byte_at(fixup_pos, disp);
1411 if (offset_to_next < 0) {
1412 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1421 void Assembler::bind(Label* L) {
1422 EnsureSpace ensure_space(this);
1423 DCHECK(!L->is_bound()); // label can only be bound once
1424 bind_to(L, pc_offset());
1428 void Assembler::call(Label* L) {
1429 positions_recorder()->WriteRecordedPositions();
1430 EnsureSpace ensure_space(this);
1431 if (L->is_bound()) {
1432 const int long_size = 5;
1433 int offs = L->pos() - pc_offset();
1435 // 1110 1000 #32-bit disp.
1437 emit(offs - long_size);
1439 // 1110 1000 #32-bit disp.
1441 emit_disp(L, Displacement::OTHER);
1446 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1447 positions_recorder()->WriteRecordedPositions();
1448 EnsureSpace ensure_space(this);
1449 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1451 if (RelocInfo::IsRuntimeEntry(rmode)) {
1452 emit(reinterpret_cast<uint32_t>(entry), rmode);
1454 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1459 int Assembler::CallSize(const Operand& adr) {
1460 // Call size is 1 (opcode) + adr.len_ (operand).
1461 return 1 + adr.len_;
1465 void Assembler::call(const Operand& adr) {
1466 positions_recorder()->WriteRecordedPositions();
1467 EnsureSpace ensure_space(this);
1469 emit_operand(edx, adr);
1473 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1474 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1478 void Assembler::call(Handle<Code> code,
1479 RelocInfo::Mode rmode,
1480 TypeFeedbackId ast_id) {
1481 positions_recorder()->WriteRecordedPositions();
1482 EnsureSpace ensure_space(this);
1483 DCHECK(RelocInfo::IsCodeTarget(rmode)
1484 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1486 emit(code, rmode, ast_id);
1490 void Assembler::jmp(Label* L, Label::Distance distance) {
1491 EnsureSpace ensure_space(this);
1492 if (L->is_bound()) {
1493 const int short_size = 2;
1494 const int long_size = 5;
1495 int offs = L->pos() - pc_offset();
1497 if (is_int8(offs - short_size)) {
1498 // 1110 1011 #8-bit disp.
1500 EMIT((offs - short_size) & 0xFF);
1502 // 1110 1001 #32-bit disp.
1504 emit(offs - long_size);
1506 } else if (distance == Label::kNear) {
1510 // 1110 1001 #32-bit disp.
1512 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1517 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1518 EnsureSpace ensure_space(this);
1519 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1521 if (RelocInfo::IsRuntimeEntry(rmode)) {
1522 emit(reinterpret_cast<uint32_t>(entry), rmode);
1524 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1529 void Assembler::jmp(const Operand& adr) {
1530 EnsureSpace ensure_space(this);
1532 emit_operand(esp, adr);
1536 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1537 EnsureSpace ensure_space(this);
1538 DCHECK(RelocInfo::IsCodeTarget(rmode));
1544 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1545 EnsureSpace ensure_space(this);
1546 DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1547 if (L->is_bound()) {
1548 const int short_size = 2;
1549 const int long_size = 6;
1550 int offs = L->pos() - pc_offset();
1552 if (is_int8(offs - short_size)) {
1553 // 0111 tttn #8-bit disp
1555 EMIT((offs - short_size) & 0xFF);
1557 // 0000 1111 1000 tttn #32-bit disp
1560 emit(offs - long_size);
1562 } else if (distance == Label::kNear) {
1566 // 0000 1111 1000 tttn #32-bit disp
1567 // Note: could eliminate cond. jumps to this jump if condition
1568 // is the same however, seems to be rather unlikely case.
1571 emit_disp(L, Displacement::OTHER);
1576 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1577 EnsureSpace ensure_space(this);
1578 DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1579 // 0000 1111 1000 tttn #32-bit disp.
1582 if (RelocInfo::IsRuntimeEntry(rmode)) {
1583 emit(reinterpret_cast<uint32_t>(entry), rmode);
1585 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1590 void Assembler::j(Condition cc, Handle<Code> code, RelocInfo::Mode rmode) {
1591 EnsureSpace ensure_space(this);
1592 // 0000 1111 1000 tttn #32-bit disp
1599 // FPU instructions.
1601 void Assembler::fld(int i) {
1602 EnsureSpace ensure_space(this);
1603 emit_farith(0xD9, 0xC0, i);
1607 void Assembler::fstp(int i) {
1608 EnsureSpace ensure_space(this);
1609 emit_farith(0xDD, 0xD8, i);
1613 void Assembler::fld1() {
1614 EnsureSpace ensure_space(this);
1620 void Assembler::fldpi() {
1621 EnsureSpace ensure_space(this);
1627 void Assembler::fldz() {
1628 EnsureSpace ensure_space(this);
1634 void Assembler::fldln2() {
1635 EnsureSpace ensure_space(this);
1641 void Assembler::fld_s(const Operand& adr) {
1642 EnsureSpace ensure_space(this);
1644 emit_operand(eax, adr);
1648 void Assembler::fld_d(const Operand& adr) {
1649 EnsureSpace ensure_space(this);
1651 emit_operand(eax, adr);
1655 void Assembler::fstp_s(const Operand& adr) {
1656 EnsureSpace ensure_space(this);
1658 emit_operand(ebx, adr);
1662 void Assembler::fst_s(const Operand& adr) {
1663 EnsureSpace ensure_space(this);
1665 emit_operand(edx, adr);
1669 void Assembler::fstp_d(const Operand& adr) {
1670 EnsureSpace ensure_space(this);
1672 emit_operand(ebx, adr);
1676 void Assembler::fst_d(const Operand& adr) {
1677 EnsureSpace ensure_space(this);
1679 emit_operand(edx, adr);
1683 void Assembler::fild_s(const Operand& adr) {
1684 EnsureSpace ensure_space(this);
1686 emit_operand(eax, adr);
1690 void Assembler::fild_d(const Operand& adr) {
1691 EnsureSpace ensure_space(this);
1693 emit_operand(ebp, adr);
1697 void Assembler::fistp_s(const Operand& adr) {
1698 EnsureSpace ensure_space(this);
1700 emit_operand(ebx, adr);
1704 void Assembler::fisttp_s(const Operand& adr) {
1705 DCHECK(IsEnabled(SSE3));
1706 EnsureSpace ensure_space(this);
1708 emit_operand(ecx, adr);
1712 void Assembler::fisttp_d(const Operand& adr) {
1713 DCHECK(IsEnabled(SSE3));
1714 EnsureSpace ensure_space(this);
1716 emit_operand(ecx, adr);
1720 void Assembler::fist_s(const Operand& adr) {
1721 EnsureSpace ensure_space(this);
1723 emit_operand(edx, adr);
1727 void Assembler::fistp_d(const Operand& adr) {
1728 EnsureSpace ensure_space(this);
1730 emit_operand(edi, adr);
1734 void Assembler::fabs() {
1735 EnsureSpace ensure_space(this);
1741 void Assembler::fchs() {
1742 EnsureSpace ensure_space(this);
1748 void Assembler::fcos() {
1749 EnsureSpace ensure_space(this);
1755 void Assembler::fsin() {
1756 EnsureSpace ensure_space(this);
1762 void Assembler::fptan() {
1763 EnsureSpace ensure_space(this);
1769 void Assembler::fyl2x() {
1770 EnsureSpace ensure_space(this);
1776 void Assembler::f2xm1() {
1777 EnsureSpace ensure_space(this);
1783 void Assembler::fscale() {
1784 EnsureSpace ensure_space(this);
1790 void Assembler::fninit() {
1791 EnsureSpace ensure_space(this);
1797 void Assembler::fadd(int i) {
1798 EnsureSpace ensure_space(this);
1799 emit_farith(0xDC, 0xC0, i);
1803 void Assembler::fadd_i(int i) {
1804 EnsureSpace ensure_space(this);
1805 emit_farith(0xD8, 0xC0, i);
1809 void Assembler::fsub(int i) {
1810 EnsureSpace ensure_space(this);
1811 emit_farith(0xDC, 0xE8, i);
1815 void Assembler::fsub_i(int i) {
1816 EnsureSpace ensure_space(this);
1817 emit_farith(0xD8, 0xE0, i);
1821 void Assembler::fisub_s(const Operand& adr) {
1822 EnsureSpace ensure_space(this);
1824 emit_operand(esp, adr);
1828 void Assembler::fmul_i(int i) {
1829 EnsureSpace ensure_space(this);
1830 emit_farith(0xD8, 0xC8, i);
1834 void Assembler::fmul(int i) {
1835 EnsureSpace ensure_space(this);
1836 emit_farith(0xDC, 0xC8, i);
1840 void Assembler::fdiv(int i) {
1841 EnsureSpace ensure_space(this);
1842 emit_farith(0xDC, 0xF8, i);
1846 void Assembler::fdiv_i(int i) {
1847 EnsureSpace ensure_space(this);
1848 emit_farith(0xD8, 0xF0, i);
1852 void Assembler::faddp(int i) {
1853 EnsureSpace ensure_space(this);
1854 emit_farith(0xDE, 0xC0, i);
1858 void Assembler::fsubp(int i) {
1859 EnsureSpace ensure_space(this);
1860 emit_farith(0xDE, 0xE8, i);
1864 void Assembler::fsubrp(int i) {
1865 EnsureSpace ensure_space(this);
1866 emit_farith(0xDE, 0xE0, i);
1870 void Assembler::fmulp(int i) {
1871 EnsureSpace ensure_space(this);
1872 emit_farith(0xDE, 0xC8, i);
1876 void Assembler::fdivp(int i) {
1877 EnsureSpace ensure_space(this);
1878 emit_farith(0xDE, 0xF8, i);
1882 void Assembler::fprem() {
1883 EnsureSpace ensure_space(this);
1889 void Assembler::fprem1() {
1890 EnsureSpace ensure_space(this);
1896 void Assembler::fxch(int i) {
1897 EnsureSpace ensure_space(this);
1898 emit_farith(0xD9, 0xC8, i);
1902 void Assembler::fincstp() {
1903 EnsureSpace ensure_space(this);
1909 void Assembler::ffree(int i) {
1910 EnsureSpace ensure_space(this);
1911 emit_farith(0xDD, 0xC0, i);
1915 void Assembler::ftst() {
1916 EnsureSpace ensure_space(this);
1922 void Assembler::fucomp(int i) {
1923 EnsureSpace ensure_space(this);
1924 emit_farith(0xDD, 0xE8, i);
1928 void Assembler::fucompp() {
1929 EnsureSpace ensure_space(this);
1935 void Assembler::fucomi(int i) {
1936 EnsureSpace ensure_space(this);
1942 void Assembler::fucomip() {
1943 EnsureSpace ensure_space(this);
1949 void Assembler::fcompp() {
1950 EnsureSpace ensure_space(this);
1956 void Assembler::fnstsw_ax() {
1957 EnsureSpace ensure_space(this);
1963 void Assembler::fwait() {
1964 EnsureSpace ensure_space(this);
1969 void Assembler::frndint() {
1970 EnsureSpace ensure_space(this);
1976 void Assembler::fnclex() {
1977 EnsureSpace ensure_space(this);
1983 void Assembler::sahf() {
1984 EnsureSpace ensure_space(this);
1989 void Assembler::setcc(Condition cc, Register reg) {
1990 DCHECK(reg.is_byte_register());
1991 EnsureSpace ensure_space(this);
1994 EMIT(0xC0 | reg.code());
1998 void Assembler::cvttss2si(Register dst, const Operand& src) {
1999 EnsureSpace ensure_space(this);
2003 emit_operand(dst, src);
2007 void Assembler::cvttsd2si(Register dst, const Operand& src) {
2008 EnsureSpace ensure_space(this);
2012 emit_operand(dst, src);
2016 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
2017 EnsureSpace ensure_space(this);
2021 emit_sse_operand(dst, src);
2025 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
2026 EnsureSpace ensure_space(this);
2030 emit_sse_operand(dst, src);
2034 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
2035 EnsureSpace ensure_space(this);
2039 emit_sse_operand(dst, src);
2043 void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
2044 EnsureSpace ensure_space(this);
2048 emit_sse_operand(dst, src);
2052 void Assembler::addsd(XMMRegister dst, const Operand& src) {
2053 EnsureSpace ensure_space(this);
2057 emit_sse_operand(dst, src);
2061 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2062 EnsureSpace ensure_space(this);
2066 emit_sse_operand(dst, src);
2070 void Assembler::subsd(XMMRegister dst, const Operand& src) {
2071 EnsureSpace ensure_space(this);
2075 emit_sse_operand(dst, src);
2079 void Assembler::divsd(XMMRegister dst, const Operand& src) {
2080 EnsureSpace ensure_space(this);
2084 emit_sse_operand(dst, src);
2088 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2089 EnsureSpace ensure_space(this);
2093 emit_sse_operand(dst, src);
2097 void Assembler::andps(XMMRegister dst, const Operand& src) {
2098 EnsureSpace ensure_space(this);
2101 emit_sse_operand(dst, src);
2105 void Assembler::orps(XMMRegister dst, const Operand& src) {
2106 EnsureSpace ensure_space(this);
2109 emit_sse_operand(dst, src);
2113 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2114 EnsureSpace ensure_space(this);
2117 emit_sse_operand(dst, src);
2121 void Assembler::addps(XMMRegister dst, const Operand& src) {
2122 EnsureSpace ensure_space(this);
2125 emit_sse_operand(dst, src);
2129 void Assembler::subps(XMMRegister dst, const Operand& src) {
2130 EnsureSpace ensure_space(this);
2133 emit_sse_operand(dst, src);
2137 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2138 EnsureSpace ensure_space(this);
2141 emit_sse_operand(dst, src);
2145 void Assembler::divps(XMMRegister dst, const Operand& src) {
2146 EnsureSpace ensure_space(this);
2149 emit_sse_operand(dst, src);
2153 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2154 EnsureSpace ensure_space(this);
2158 emit_sse_operand(dst, src);
2162 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2163 EnsureSpace ensure_space(this);
2167 emit_sse_operand(dst, src);
2171 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2172 EnsureSpace ensure_space(this);
2176 emit_sse_operand(dst, src);
2180 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2181 EnsureSpace ensure_space(this);
2185 emit_sse_operand(dst, src);
2189 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2190 DCHECK(IsEnabled(SSE4_1));
2191 EnsureSpace ensure_space(this);
2196 emit_sse_operand(dst, src);
2197 // Mask precision exeption.
2198 EMIT(static_cast<byte>(mode) | 0x8);
2202 void Assembler::movmskpd(Register dst, XMMRegister src) {
2203 EnsureSpace ensure_space(this);
2207 emit_sse_operand(dst, src);
2211 void Assembler::movmskps(Register dst, XMMRegister src) {
2212 EnsureSpace ensure_space(this);
2215 emit_sse_operand(dst, src);
2219 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2220 EnsureSpace ensure_space(this);
2224 emit_sse_operand(dst, src);
2228 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2229 EnsureSpace ensure_space(this);
2233 emit_sse_operand(dst, src);
2237 void Assembler::punpckhdq(XMMRegister dst, XMMRegister src) {
2238 EnsureSpace ensure_space(this);
2242 emit_sse_operand(dst, src);
2246 void Assembler::maxsd(XMMRegister dst, const Operand& src) {
2247 EnsureSpace ensure_space(this);
2251 emit_sse_operand(dst, src);
2255 void Assembler::minsd(XMMRegister dst, const Operand& src) {
2256 EnsureSpace ensure_space(this);
2260 emit_sse_operand(dst, src);
2264 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2265 EnsureSpace ensure_space(this);
2269 emit_sse_operand(dst, src);
2274 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2275 EnsureSpace ensure_space(this);
2278 emit_sse_operand(dst, src);
2282 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2283 DCHECK(is_uint8(imm8));
2284 EnsureSpace ensure_space(this);
2287 emit_sse_operand(dst, src);
2292 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2293 EnsureSpace ensure_space(this);
2297 emit_sse_operand(src, dst);
2301 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2302 EnsureSpace ensure_space(this);
2306 emit_sse_operand(dst, src);
2310 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2311 EnsureSpace ensure_space(this);
2315 emit_sse_operand(src, dst);
2319 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2320 EnsureSpace ensure_space(this);
2324 emit_sse_operand(dst, src);
2328 void Assembler::prefetch(const Operand& src, int level) {
2329 DCHECK(is_uint2(level));
2330 EnsureSpace ensure_space(this);
2333 // Emit hint number in Reg position of RegR/M.
2334 XMMRegister code = XMMRegister::from_code(level);
2335 emit_sse_operand(code, src);
2339 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2340 EnsureSpace ensure_space(this);
2341 EMIT(0xF2); // double
2343 EMIT(0x11); // store
2344 emit_sse_operand(src, dst);
2348 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2349 EnsureSpace ensure_space(this);
2350 EMIT(0xF2); // double
2353 emit_sse_operand(dst, src);
2357 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2358 EnsureSpace ensure_space(this);
2359 EMIT(0xF3); // float
2361 EMIT(0x11); // store
2362 emit_sse_operand(src, dst);
2366 void Assembler::movss(XMMRegister dst, const Operand& src) {
2367 EnsureSpace ensure_space(this);
2368 EMIT(0xF3); // float
2371 emit_sse_operand(dst, src);
2375 void Assembler::movd(XMMRegister dst, const Operand& src) {
2376 EnsureSpace ensure_space(this);
2380 emit_sse_operand(dst, src);
2384 void Assembler::movd(const Operand& dst, XMMRegister src) {
2385 EnsureSpace ensure_space(this);
2389 emit_sse_operand(src, dst);
2393 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2394 DCHECK(IsEnabled(SSE4_1));
2395 DCHECK(is_uint8(imm8));
2396 EnsureSpace ensure_space(this);
2401 emit_sse_operand(src, dst);
2406 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2407 EnsureSpace ensure_space(this);
2411 emit_sse_operand(dst, src);
2415 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2416 EnsureSpace ensure_space(this);
2420 emit_sse_operand(dst, src);
2424 void Assembler::por(XMMRegister dst, XMMRegister src) {
2425 EnsureSpace ensure_space(this);
2429 emit_sse_operand(dst, src);
2433 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2434 DCHECK(IsEnabled(SSE4_1));
2435 EnsureSpace ensure_space(this);
2440 emit_sse_operand(dst, src);
2444 void Assembler::pslld(XMMRegister reg, int8_t shift) {
2445 EnsureSpace ensure_space(this);
2449 emit_sse_operand(esi, reg); // esi == 6
2454 void Assembler::psrld(XMMRegister reg, int8_t shift) {
2455 EnsureSpace ensure_space(this);
2459 emit_sse_operand(edx, reg); // edx == 2
2464 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2465 EnsureSpace ensure_space(this);
2469 emit_sse_operand(esi, reg); // esi == 6
2474 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2475 EnsureSpace ensure_space(this);
2479 emit_sse_operand(dst, src);
2483 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2484 EnsureSpace ensure_space(this);
2488 emit_sse_operand(edx, reg); // edx == 2
2493 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2494 EnsureSpace ensure_space(this);
2498 emit_sse_operand(dst, src);
2502 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2503 EnsureSpace ensure_space(this);
2507 emit_sse_operand(dst, src);
2512 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2513 DCHECK(IsEnabled(SSE4_1));
2514 EnsureSpace ensure_space(this);
2519 emit_sse_operand(src, dst);
2524 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2525 DCHECK(IsEnabled(SSE4_1));
2526 EnsureSpace ensure_space(this);
2531 emit_sse_operand(dst, src);
2536 void Assembler::addss(XMMRegister dst, const Operand& src) {
2537 EnsureSpace ensure_space(this);
2541 emit_sse_operand(dst, src);
2545 void Assembler::subss(XMMRegister dst, const Operand& src) {
2546 EnsureSpace ensure_space(this);
2550 emit_sse_operand(dst, src);
2554 void Assembler::mulss(XMMRegister dst, const Operand& src) {
2555 EnsureSpace ensure_space(this);
2559 emit_sse_operand(dst, src);
2563 void Assembler::divss(XMMRegister dst, const Operand& src) {
2564 EnsureSpace ensure_space(this);
2568 emit_sse_operand(dst, src);
2572 void Assembler::sqrtss(XMMRegister dst, const Operand& src) {
2573 EnsureSpace ensure_space(this);
2577 emit_sse_operand(dst, src);
2581 void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
2582 EnsureSpace ensure_space(this);
2585 emit_sse_operand(dst, src);
2589 void Assembler::maxss(XMMRegister dst, const Operand& src) {
2590 EnsureSpace ensure_space(this);
2594 emit_sse_operand(dst, src);
2598 void Assembler::minss(XMMRegister dst, const Operand& src) {
2599 EnsureSpace ensure_space(this);
2603 emit_sse_operand(dst, src);
2608 void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
2609 const Operand& src2) {
2610 DCHECK(IsEnabled(FMA3));
2611 EnsureSpace ensure_space(this);
2612 emit_vex_prefix(src1, kLIG, k66, k0F38, kW1);
2614 emit_sse_operand(dst, src2);
2618 void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
2619 const Operand& src2) {
2620 DCHECK(IsEnabled(FMA3));
2621 EnsureSpace ensure_space(this);
2622 emit_vex_prefix(src1, kLIG, k66, k0F38, kW0);
2624 emit_sse_operand(dst, src2);
2628 void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1,
2629 const Operand& src2) {
2630 DCHECK(IsEnabled(AVX));
2631 EnsureSpace ensure_space(this);
2632 emit_vex_prefix(src1, kLIG, kF2, k0F, kWIG);
2634 emit_sse_operand(dst, src2);
2638 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
2639 const Operand& src2) {
2640 DCHECK(IsEnabled(AVX));
2641 EnsureSpace ensure_space(this);
2642 emit_vex_prefix(src1, kLIG, kF3, k0F, kWIG);
2644 emit_sse_operand(dst, src2);
2648 void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
2649 const Operand& src2) {
2650 DCHECK(IsEnabled(AVX));
2651 EnsureSpace ensure_space(this);
2652 emit_vex_prefix(src1, kL128, kNone, k0F, kWIG);
2654 emit_sse_operand(dst, src2);
2658 void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
2659 const Operand& src2) {
2660 DCHECK(IsEnabled(AVX));
2661 EnsureSpace ensure_space(this);
2662 emit_vex_prefix(src1, kL128, k66, k0F, kWIG);
2664 emit_sse_operand(dst, src2);
2668 void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) {
2669 DCHECK(IsEnabled(BMI1));
2670 EnsureSpace ensure_space(this);
2671 emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0);
2673 emit_operand(reg, rm);
2677 void Assembler::tzcnt(Register dst, const Operand& src) {
2678 DCHECK(IsEnabled(BMI1));
2679 EnsureSpace ensure_space(this);
2683 emit_operand(dst, src);
2687 void Assembler::lzcnt(Register dst, const Operand& src) {
2688 DCHECK(IsEnabled(LZCNT));
2689 EnsureSpace ensure_space(this);
2693 emit_operand(dst, src);
2697 void Assembler::popcnt(Register dst, const Operand& src) {
2698 DCHECK(IsEnabled(POPCNT));
2699 EnsureSpace ensure_space(this);
2703 emit_operand(dst, src);
2707 void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg,
2708 const Operand& rm) {
2709 DCHECK(IsEnabled(BMI2));
2710 EnsureSpace ensure_space(this);
2711 emit_vex_prefix(vreg, kLZ, pp, k0F38, kW0);
2713 emit_operand(reg, rm);
2717 void Assembler::rorx(Register dst, const Operand& src, byte imm8) {
2718 DCHECK(IsEnabled(BMI2));
2719 DCHECK(is_uint8(imm8));
2720 Register vreg = {0}; // VEX.vvvv unused
2721 EnsureSpace ensure_space(this);
2722 emit_vex_prefix(vreg, kLZ, kF2, k0F3A, kW0);
2724 emit_operand(dst, src);
2729 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2730 Register ireg = { reg.code() };
2731 emit_operand(ireg, adr);
2735 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2736 EMIT(0xC0 | dst.code() << 3 | src.code());
2740 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2741 EMIT(0xC0 | dst.code() << 3 | src.code());
2745 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2746 EMIT(0xC0 | (dst.code() << 3) | src.code());
2750 void Assembler::emit_vex_prefix(XMMRegister vreg, VectorLength l, SIMDPrefix pp,
2751 LeadingOpcode mm, VexW w) {
2752 if (mm != k0F || w != kW0) {
2754 // Change RXB from "110" to "111" to align with gdb disassembler.
2756 EMIT(w | ((~vreg.code() & 0xf) << 3) | l | pp);
2759 EMIT(((~vreg.code()) << 3) | l | pp);
2764 void Assembler::emit_vex_prefix(Register vreg, VectorLength l, SIMDPrefix pp,
2765 LeadingOpcode mm, VexW w) {
2766 XMMRegister ivreg = {vreg.code()};
2767 emit_vex_prefix(ivreg, l, pp, mm, w);
2771 void Assembler::GrowBuffer() {
2772 DCHECK(buffer_overflow());
2773 if (!own_buffer_) FATAL("external code buffer is too small");
2775 // Compute new buffer size.
2776 CodeDesc desc; // the new buffer
2777 desc.buffer_size = 2 * buffer_size_;
2779 // Some internal data structures overflow for very large buffers,
2780 // they must ensure that kMaximalBufferSize is not too large.
2781 if ((desc.buffer_size > kMaximalBufferSize) ||
2782 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2783 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2786 // Set up new buffer.
2787 desc.buffer = NewArray<byte>(desc.buffer_size);
2788 desc.instr_size = pc_offset();
2789 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2791 // Clear the buffer in debug mode. Use 'int3' instructions to make
2792 // sure to get into problems if we ever run uninitialized code.
2794 memset(desc.buffer, 0xCC, desc.buffer_size);
2798 int pc_delta = desc.buffer - buffer_;
2799 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2800 MemMove(desc.buffer, buffer_, desc.instr_size);
2801 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
2805 DeleteArray(buffer_);
2806 buffer_ = desc.buffer;
2807 buffer_size_ = desc.buffer_size;
2809 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2810 reloc_info_writer.last_pc() + pc_delta);
2812 // Relocate internal references.
2813 for (auto pos : internal_reference_positions_) {
2814 int32_t* p = reinterpret_cast<int32_t*>(buffer_ + pos);
2818 DCHECK(!buffer_overflow());
2822 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2823 DCHECK(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2824 DCHECK(is_uint8(imm8));
2825 DCHECK((op1 & 0x01) == 0); // should be 8bit operation
2827 EMIT(op2 | dst.code());
2832 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2833 DCHECK((0 <= sel) && (sel <= 7));
2834 Register ireg = { sel };
2836 EMIT(0x83); // using a sign-extended 8-bit immediate.
2837 emit_operand(ireg, dst);
2839 } else if (dst.is_reg(eax)) {
2840 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2843 EMIT(0x81); // using a literal 32-bit immediate.
2844 emit_operand(ireg, dst);
2850 void Assembler::emit_operand(Register reg, const Operand& adr) {
2851 const unsigned length = adr.len_;
2854 // Emit updated ModRM byte containing the given register.
2855 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2857 // Emit the rest of the encoded operand.
2858 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2861 // Emit relocation information if necessary.
2862 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2863 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2864 RecordRelocInfo(adr.rmode_);
2865 if (adr.rmode_ == RelocInfo::INTERNAL_REFERENCE) { // Fixup for labels
2866 emit_label(*reinterpret_cast<Label**>(pc_));
2868 pc_ += sizeof(int32_t);
2874 void Assembler::emit_label(Label* label) {
2875 if (label->is_bound()) {
2876 internal_reference_positions_.push_back(pc_offset());
2877 emit(reinterpret_cast<uint32_t>(buffer_ + label->pos()));
2879 emit_disp(label, Displacement::CODE_ABSOLUTE);
2884 void Assembler::emit_farith(int b1, int b2, int i) {
2885 DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2886 DCHECK(0 <= i && i < 8); // illegal stack offset
2892 void Assembler::db(uint8_t data) {
2893 EnsureSpace ensure_space(this);
2898 void Assembler::dd(uint32_t data) {
2899 EnsureSpace ensure_space(this);
2904 void Assembler::dq(uint64_t data) {
2905 EnsureSpace ensure_space(this);
2910 void Assembler::dd(Label* label) {
2911 EnsureSpace ensure_space(this);
2912 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
2917 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2918 DCHECK(!RelocInfo::IsNone(rmode));
2919 // Don't record external references unless the heap will be serialized.
2920 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2921 !serializer_enabled() && !emit_debug_code()) {
2924 RelocInfo rinfo(pc_, rmode, data, NULL);
2925 reloc_info_writer.Write(&rinfo);
2929 #ifdef GENERATED_CODE_COVERAGE
2930 static FILE* coverage_log = NULL;
2933 static void InitCoverageLog() {
2934 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
2935 if (file_name != NULL) {
2936 coverage_log = fopen(file_name, "aw+");
2941 void LogGeneratedCodeCoverage(const char* file_line) {
2942 const char* return_address = (&file_line)[-1];
2943 char* push_insn = const_cast<char*>(return_address - 12);
2944 push_insn[0] = 0xeb; // Relative branch insn.
2945 push_insn[1] = 13; // Skip over coverage insns.
2946 if (coverage_log != NULL) {
2947 fprintf(coverage_log, "%s\n", file_line);
2948 fflush(coverage_log);
2954 } // namespace internal
2957 #endif // V8_TARGET_ARCH_IA32