src/i965_render.c

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Xiang Haihao <haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 /*
  31  * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <assert.h>
  38
  39 #include <va/va_drmcommon.h>
  40
  41 #include "intel_batchbuffer.h"
  42 #include "intel_driver.h"
  43 #include "i965_defines.h"
  44 #include "i965_drv_video.h"
  45 #include "i965_structs.h"
  46
  47 #include "i965_render.h"
  48
  49 #define SF_KERNEL_NUM_GRF       16
  50 #define SF_MAX_THREADS          1
  51
  52 static const uint32_t sf_kernel_static[][4] =
  53 {
  54 #include "shaders/render/exa_sf.g4b"
  55 };
  56
  57 #define PS_KERNEL_NUM_GRF       32
  58 #define PS_MAX_THREADS          32
  59
  60 #define I965_GRF_BLOCKS(nreg)   ((nreg + 15) / 16 - 1)
  61
  62 static const uint32_t ps_kernel_static[][4] =
  63 {
  64 #include "shaders/render/exa_wm_xy.g4b"
  65 #include "shaders/render/exa_wm_src_affine.g4b"
  66 #include "shaders/render/exa_wm_src_sample_planar.g4b"
  67 #include "shaders/render/exa_wm_yuv_rgb.g4b"
  68 #include "shaders/render/exa_wm_write.g4b"
  69 };
  70 static const uint32_t ps_subpic_kernel_static[][4] =
  71 {
  72 #include "shaders/render/exa_wm_xy.g4b"
  73 #include "shaders/render/exa_wm_src_affine.g4b"
  74 #include "shaders/render/exa_wm_src_sample_argb.g4b"
  75 #include "shaders/render/exa_wm_write.g4b"
  76 };
  77
  78 /* On IRONLAKE */
  79 static const uint32_t sf_kernel_static_gen5[][4] =
  80 {
  81 #include "shaders/render/exa_sf.g4b.gen5"
  82 };
  83
  84 static const uint32_t ps_kernel_static_gen5[][4] =
  85 {
  86 #include "shaders/render/exa_wm_xy.g4b.gen5"
  87 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
  88 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
  89 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
  90 #include "shaders/render/exa_wm_write.g4b.gen5"
  91 };
  92 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
  93 {
  94 #include "shaders/render/exa_wm_xy.g4b.gen5"
  95 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
  96 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
  97 #include "shaders/render/exa_wm_write.g4b.gen5"
  98 };
  99
 100 /* programs for Sandybridge */
 101 static const uint32_t sf_kernel_static_gen6[][4] =
 102 {
 103 };
 104
 105 static const uint32_t ps_kernel_static_gen6[][4] = {
 106 #include "shaders/render/exa_wm_src_affine.g6b"
 107 #include "shaders/render/exa_wm_src_sample_planar.g6b"
 108 #include "shaders/render/exa_wm_yuv_rgb.g6b"
 109 #include "shaders/render/exa_wm_write.g6b"
 110 };
 111
 112 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
 113 #include "shaders/render/exa_wm_src_affine.g6b"
 114 #include "shaders/render/exa_wm_src_sample_argb.g6b"
 115 #include "shaders/render/exa_wm_write.g6b"
 116 };
 117
 118 /* programs for Ivybridge */
 119 static const uint32_t sf_kernel_static_gen7[][4] =
 120 {
 121 };
 122
 123 static const uint32_t ps_kernel_static_gen7[][4] = {
 124 #include "shaders/render/exa_wm_src_affine.g7b"
 125 #include "shaders/render/exa_wm_src_sample_planar.g7b"
 126 #include "shaders/render/exa_wm_yuv_rgb.g7b"
 127 #include "shaders/render/exa_wm_write.g7b"
 128 };
 129
 130 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
 131 #include "shaders/render/exa_wm_src_affine.g7b"
 132 #include "shaders/render/exa_wm_src_sample_argb.g7b"
 133 #include "shaders/render/exa_wm_write.g7b"
 134 };
 135
 136 /* Programs for Haswell */
 137 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
 138 #include "shaders/render/exa_wm_src_affine.g7b"
 139 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
 140 #include "shaders/render/exa_wm_yuv_rgb.g7b"
 141 #include "shaders/render/exa_wm_write.g7b"
 142 };
 143
 144 #define SURFACE_STATE_PADDED_SIZE_I965  ALIGN(sizeof(struct i965_surface_state), 32)
 145 #define SURFACE_STATE_PADDED_SIZE_GEN7  ALIGN(sizeof(struct gen7_surface_state), 32)
 146 #define SURFACE_STATE_PADDED_SIZE       MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
 147 #define SURFACE_STATE_OFFSET(index)     (SURFACE_STATE_PADDED_SIZE * index)
 148 #define BINDING_TABLE_OFFSET            SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
 149
 150 static uint32_t float_to_uint (float f)
 151 {
 152     union {
 153         uint32_t i;
 154         float f;
 155     } x;
 156
 157     x.f = f;
 158     return x.i;
 159 }
 160
 161 enum
 162 {
 163     SF_KERNEL = 0,
 164     PS_KERNEL,
 165     PS_SUBPIC_KERNEL
 166 };
 167
 168 static struct i965_kernel render_kernels_gen4[] = {
 169     {
 170         "SF",
 171         SF_KERNEL,
 172         sf_kernel_static,
 173         sizeof(sf_kernel_static),
 174         NULL
 175     },
 176     {
 177         "PS",
 178         PS_KERNEL,
 179         ps_kernel_static,
 180         sizeof(ps_kernel_static),
 181         NULL
 182     },
 183
 184     {
 185         "PS_SUBPIC",
 186         PS_SUBPIC_KERNEL,
 187         ps_subpic_kernel_static,
 188         sizeof(ps_subpic_kernel_static),
 189         NULL
 190     }
 191 };
 192
 193 static struct i965_kernel render_kernels_gen5[] = {
 194     {
 195         "SF",
 196         SF_KERNEL,
 197         sf_kernel_static_gen5,
 198         sizeof(sf_kernel_static_gen5),
 199         NULL
 200     },
 201     {
 202         "PS",
 203         PS_KERNEL,
 204         ps_kernel_static_gen5,
 205         sizeof(ps_kernel_static_gen5),
 206         NULL
 207     },
 208
 209     {
 210         "PS_SUBPIC",
 211         PS_SUBPIC_KERNEL,
 212         ps_subpic_kernel_static_gen5,
 213         sizeof(ps_subpic_kernel_static_gen5),
 214         NULL
 215     }
 216 };
 217
 218 static struct i965_kernel render_kernels_gen6[] = {
 219     {
 220         "SF",
 221         SF_KERNEL,
 222         sf_kernel_static_gen6,
 223         sizeof(sf_kernel_static_gen6),
 224         NULL
 225     },
 226     {
 227         "PS",
 228         PS_KERNEL,
 229         ps_kernel_static_gen6,
 230         sizeof(ps_kernel_static_gen6),
 231         NULL
 232     },
 233
 234     {
 235         "PS_SUBPIC",
 236         PS_SUBPIC_KERNEL,
 237         ps_subpic_kernel_static_gen6,
 238         sizeof(ps_subpic_kernel_static_gen6),
 239         NULL
 240     }
 241 };
 242
 243 static struct i965_kernel render_kernels_gen7[] = {
 244     {
 245         "SF",
 246         SF_KERNEL,
 247         sf_kernel_static_gen7,
 248         sizeof(sf_kernel_static_gen7),
 249         NULL
 250     },
 251     {
 252         "PS",
 253         PS_KERNEL,
 254         ps_kernel_static_gen7,
 255         sizeof(ps_kernel_static_gen7),
 256         NULL
 257     },
 258
 259     {
 260         "PS_SUBPIC",
 261         PS_SUBPIC_KERNEL,
 262         ps_subpic_kernel_static_gen7,
 263         sizeof(ps_subpic_kernel_static_gen7),
 264         NULL
 265     }
 266 };
 267
 268 static struct i965_kernel render_kernels_gen7_haswell[] = {
 269     {
 270         "SF",
 271         SF_KERNEL,
 272         sf_kernel_static_gen7,
 273         sizeof(sf_kernel_static_gen7),
 274         NULL
 275     },
 276     {
 277         "PS",
 278         PS_KERNEL,
 279         ps_kernel_static_gen7_haswell,
 280         sizeof(ps_kernel_static_gen7_haswell),
 281         NULL
 282     },
 283
 284     {
 285         "PS_SUBPIC",
 286         PS_SUBPIC_KERNEL,
 287         ps_subpic_kernel_static_gen7,
 288         sizeof(ps_subpic_kernel_static_gen7),
 289         NULL
 290     }
 291 };
 292
 293 #define URB_VS_ENTRIES        8
 294 #define URB_VS_ENTRY_SIZE     1
 295
 296 #define URB_GS_ENTRIES        0
 297 #define URB_GS_ENTRY_SIZE     0
 298
 299 #define URB_CLIP_ENTRIES      0
 300 #define URB_CLIP_ENTRY_SIZE   0
 301
 302 #define URB_SF_ENTRIES        1
 303 #define URB_SF_ENTRY_SIZE     2
 304
 305 #define URB_CS_ENTRIES        1
 306 #define URB_CS_ENTRY_SIZE     1
 307
 308 static void
 309 i965_render_vs_unit(VADriverContextP ctx)
 310 {
 311     struct i965_driver_data *i965 = i965_driver_data(ctx);
 312     struct i965_render_state *render_state = &i965->render_state;
 313     struct i965_vs_unit_state *vs_state;
 314
 315     dri_bo_map(render_state->vs.state, 1);
 316     assert(render_state->vs.state->virtual);
 317     vs_state = render_state->vs.state->virtual;
 318     memset(vs_state, 0, sizeof(*vs_state));
 319
 320     if (IS_IRONLAKE(i965->intel.device_id))
 321         vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
 322     else
 323         vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
 324
 325     vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
 326     vs_state->vs6.vs_enable = 0;
 327     vs_state->vs6.vert_cache_disable = 1;
 328
 329     dri_bo_unmap(render_state->vs.state);
 330 }
 331
 332 static void
 333 i965_render_sf_unit(VADriverContextP ctx)
 334 {
 335     struct i965_driver_data *i965 = i965_driver_data(ctx);
 336     struct i965_render_state *render_state = &i965->render_state;
 337     struct i965_sf_unit_state *sf_state;
 338
 339     dri_bo_map(render_state->sf.state, 1);
 340     assert(render_state->sf.state->virtual);
 341     sf_state = render_state->sf.state->virtual;
 342     memset(sf_state, 0, sizeof(*sf_state));
 343
 344     sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
 345     sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
 346
 347     sf_state->sf1.single_program_flow = 1; /* XXX */
 348     sf_state->sf1.binding_table_entry_count = 0;
 349     sf_state->sf1.thread_priority = 0;
 350     sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
 351     sf_state->sf1.illegal_op_exception_enable = 1;
 352     sf_state->sf1.mask_stack_exception_enable = 1;
 353     sf_state->sf1.sw_exception_enable = 1;
 354
 355     /* scratch space is not used in our kernel */
 356     sf_state->thread2.per_thread_scratch_space = 0;
 357     sf_state->thread2.scratch_space_base_pointer = 0;
 358
 359     sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
 360     sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
 361     sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
 362     sf_state->thread3.urb_entry_read_offset = 0;
 363     sf_state->thread3.dispatch_grf_start_reg = 3;
 364
 365     sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
 366     sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
 367     sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
 368     sf_state->thread4.stats_enable = 1;
 369
 370     sf_state->sf5.viewport_transform = 0; /* skip viewport */
 371
 372     sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
 373     sf_state->sf6.scissor = 0;
 374
 375     sf_state->sf7.trifan_pv = 2;
 376
 377     sf_state->sf6.dest_org_vbias = 0x8;
 378     sf_state->sf6.dest_org_hbias = 0x8;
 379
 380     dri_bo_emit_reloc(render_state->sf.state,
 381                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 382                       sf_state->thread0.grf_reg_count << 1,
 383                       offsetof(struct i965_sf_unit_state, thread0),
 384                       render_state->render_kernels[SF_KERNEL].bo);
 385
 386     dri_bo_unmap(render_state->sf.state);
 387 }
 388
 389 static void
 390 i965_render_sampler(VADriverContextP ctx)
 391 {
 392     struct i965_driver_data *i965 = i965_driver_data(ctx);
 393     struct i965_render_state *render_state = &i965->render_state;
 394     struct i965_sampler_state *sampler_state;
 395     int i;
 396
 397     assert(render_state->wm.sampler_count > 0);
 398     assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
 399
 400     dri_bo_map(render_state->wm.sampler, 1);
 401     assert(render_state->wm.sampler->virtual);
 402     sampler_state = render_state->wm.sampler->virtual;
 403     for (i = 0; i < render_state->wm.sampler_count; i++) {
 404         memset(sampler_state, 0, sizeof(*sampler_state));
 405         sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
 406         sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
 407         sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 408         sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 409         sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 410         sampler_state++;
 411     }
 412
 413     dri_bo_unmap(render_state->wm.sampler);
 414 }
 415 static void
 416 i965_subpic_render_wm_unit(VADriverContextP ctx)
 417 {
 418     struct i965_driver_data *i965 = i965_driver_data(ctx);
 419     struct i965_render_state *render_state = &i965->render_state;
 420     struct i965_wm_unit_state *wm_state;
 421
 422     assert(render_state->wm.sampler);
 423
 424     dri_bo_map(render_state->wm.state, 1);
 425     assert(render_state->wm.state->virtual);
 426     wm_state = render_state->wm.state->virtual;
 427     memset(wm_state, 0, sizeof(*wm_state));
 428
 429     wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
 430     wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
 431
 432     wm_state->thread1.single_program_flow = 1; /* XXX */
 433
 434     if (IS_IRONLAKE(i965->intel.device_id))
 435         wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
 436     else
 437         wm_state->thread1.binding_table_entry_count = 7;
 438
 439     wm_state->thread2.scratch_space_base_pointer = 0;
 440     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 441
 442     wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
 443     wm_state->thread3.const_urb_entry_read_length = 0;
 444     wm_state->thread3.const_urb_entry_read_offset = 0;
 445     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
 446     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
 447
 448     wm_state->wm4.stats_enable = 0;
 449     wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
 450
 451     if (IS_IRONLAKE(i965->intel.device_id)) {
 452         wm_state->wm4.sampler_count = 0;        /* hardware requirement */
 453     } else {
 454         wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
 455     }
 456
 457     wm_state->wm5.max_threads = render_state->max_wm_threads - 1;
 458     wm_state->wm5.thread_dispatch_enable = 1;
 459     wm_state->wm5.enable_16_pix = 1;
 460     wm_state->wm5.enable_8_pix = 0;
 461     wm_state->wm5.early_depth_test = 1;
 462
 463     dri_bo_emit_reloc(render_state->wm.state,
 464                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 465                       wm_state->thread0.grf_reg_count << 1,
 466                       offsetof(struct i965_wm_unit_state, thread0),
 467                       render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
 468
 469     dri_bo_emit_reloc(render_state->wm.state,
 470                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 471                       wm_state->wm4.sampler_count << 2,
 472                       offsetof(struct i965_wm_unit_state, wm4),
 473                       render_state->wm.sampler);
 474
 475     dri_bo_unmap(render_state->wm.state);
 476 }
 477
 478
 479 static void
 480 i965_render_wm_unit(VADriverContextP ctx)
 481 {
 482     struct i965_driver_data *i965 = i965_driver_data(ctx);
 483     struct i965_render_state *render_state = &i965->render_state;
 484     struct i965_wm_unit_state *wm_state;
 485
 486     assert(render_state->wm.sampler);
 487
 488     dri_bo_map(render_state->wm.state, 1);
 489     assert(render_state->wm.state->virtual);
 490     wm_state = render_state->wm.state->virtual;
 491     memset(wm_state, 0, sizeof(*wm_state));
 492
 493     wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
 494     wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
 495
 496     wm_state->thread1.single_program_flow = 1; /* XXX */
 497
 498     if (IS_IRONLAKE(i965->intel.device_id))
 499         wm_state->thread1.binding_table_entry_count = 0;        /* hardware requirement */
 500     else
 501         wm_state->thread1.binding_table_entry_count = 7;
 502
 503     wm_state->thread2.scratch_space_base_pointer = 0;
 504     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 505
 506     wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
 507     wm_state->thread3.const_urb_entry_read_length = 1;
 508     wm_state->thread3.const_urb_entry_read_offset = 0;
 509     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
 510     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
 511
 512     wm_state->wm4.stats_enable = 0;
 513     wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
 514
 515     if (IS_IRONLAKE(i965->intel.device_id)) {
 516         wm_state->wm4.sampler_count = 0;        /* hardware requirement */
 517     } else {
 518         wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
 519     }
 520
 521     wm_state->wm5.max_threads = render_state->max_wm_threads - 1;
 522     wm_state->wm5.thread_dispatch_enable = 1;
 523     wm_state->wm5.enable_16_pix = 1;
 524     wm_state->wm5.enable_8_pix = 0;
 525     wm_state->wm5.early_depth_test = 1;
 526
 527     dri_bo_emit_reloc(render_state->wm.state,
 528                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 529                       wm_state->thread0.grf_reg_count << 1,
 530                       offsetof(struct i965_wm_unit_state, thread0),
 531                       render_state->render_kernels[PS_KERNEL].bo);
 532
 533     dri_bo_emit_reloc(render_state->wm.state,
 534                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 535                       wm_state->wm4.sampler_count << 2,
 536                       offsetof(struct i965_wm_unit_state, wm4),
 537                       render_state->wm.sampler);
 538
 539     dri_bo_unmap(render_state->wm.state);
 540 }
 541
 542 static void
 543 i965_render_cc_viewport(VADriverContextP ctx)
 544 {
 545     struct i965_driver_data *i965 = i965_driver_data(ctx);
 546     struct i965_render_state *render_state = &i965->render_state;
 547     struct i965_cc_viewport *cc_viewport;
 548
 549     dri_bo_map(render_state->cc.viewport, 1);
 550     assert(render_state->cc.viewport->virtual);
 551     cc_viewport = render_state->cc.viewport->virtual;
 552     memset(cc_viewport, 0, sizeof(*cc_viewport));
 553
 554     cc_viewport->min_depth = -1.e35;
 555     cc_viewport->max_depth = 1.e35;
 556
 557     dri_bo_unmap(render_state->cc.viewport);
 558 }
 559
 560 static void
 561 i965_subpic_render_cc_unit(VADriverContextP ctx)
 562 {
 563     struct i965_driver_data *i965 = i965_driver_data(ctx);
 564     struct i965_render_state *render_state = &i965->render_state;
 565     struct i965_cc_unit_state *cc_state;
 566
 567     assert(render_state->cc.viewport);
 568
 569     dri_bo_map(render_state->cc.state, 1);
 570     assert(render_state->cc.state->virtual);
 571     cc_state = render_state->cc.state->virtual;
 572     memset(cc_state, 0, sizeof(*cc_state));
 573
 574     cc_state->cc0.stencil_enable = 0;   /* disable stencil */
 575     cc_state->cc2.depth_test = 0;       /* disable depth test */
 576     cc_state->cc2.logicop_enable = 0;   /* disable logic op */
 577     cc_state->cc3.ia_blend_enable = 0 ;  /* blend alpha just like colors */
 578     cc_state->cc3.blend_enable = 1;     /* enable color blend */
 579     cc_state->cc3.alpha_test = 0;       /* disable alpha test */
 580     cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8;       /*store alpha value with UNORM8 */
 581     cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS;       /*pass if less than the reference */
 582     cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
 583
 584     cc_state->cc5.dither_enable = 0;    /* disable dither */
 585     cc_state->cc5.logicop_func = 0xc;   /* WHITE */
 586     cc_state->cc5.statistics_enable = 1;
 587     cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
 588     cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
 589     cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
 590
 591     cc_state->cc6.clamp_post_alpha_blend = 0;
 592     cc_state->cc6.clamp_pre_alpha_blend  =0;
 593
 594     /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
 595     cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
 596     cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
 597     cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
 598
 599     /*alpha test reference*/
 600     cc_state->cc7.alpha_ref.f =0.0 ;
 601
 602
 603     dri_bo_emit_reloc(render_state->cc.state,
 604                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 605                       0,
 606                       offsetof(struct i965_cc_unit_state, cc4),
 607                       render_state->cc.viewport);
 608
 609     dri_bo_unmap(render_state->cc.state);
 610 }
 611
 612
 613 static void
 614 i965_render_cc_unit(VADriverContextP ctx)
 615 {
 616     struct i965_driver_data *i965 = i965_driver_data(ctx);
 617     struct i965_render_state *render_state = &i965->render_state;
 618     struct i965_cc_unit_state *cc_state;
 619
 620     assert(render_state->cc.viewport);
 621
 622     dri_bo_map(render_state->cc.state, 1);
 623     assert(render_state->cc.state->virtual);
 624     cc_state = render_state->cc.state->virtual;
 625     memset(cc_state, 0, sizeof(*cc_state));
 626
 627     cc_state->cc0.stencil_enable = 0;   /* disable stencil */
 628     cc_state->cc2.depth_test = 0;       /* disable depth test */
 629     cc_state->cc2.logicop_enable = 1;   /* enable logic op */
 630     cc_state->cc3.ia_blend_enable = 0;  /* blend alpha just like colors */
 631     cc_state->cc3.blend_enable = 0;     /* disable color blend */
 632     cc_state->cc3.alpha_test = 0;       /* disable alpha test */
 633     cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
 634
 635     cc_state->cc5.dither_enable = 0;    /* disable dither */
 636     cc_state->cc5.logicop_func = 0xc;   /* WHITE */
 637     cc_state->cc5.statistics_enable = 1;
 638     cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
 639     cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
 640     cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
 641
 642     dri_bo_emit_reloc(render_state->cc.state,
 643                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 644                       0,
 645                       offsetof(struct i965_cc_unit_state, cc4),
 646                       render_state->cc.viewport);
 647
 648     dri_bo_unmap(render_state->cc.state);
 649 }
 650
 651 static void
 652 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 653 {
 654     switch (tiling) {
 655     case I915_TILING_NONE:
 656         ss->ss3.tiled_surface = 0;
 657         ss->ss3.tile_walk = 0;
 658         break;
 659     case I915_TILING_X:
 660         ss->ss3.tiled_surface = 1;
 661         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 662         break;
 663     case I915_TILING_Y:
 664         ss->ss3.tiled_surface = 1;
 665         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 666         break;
 667     }
 668 }
 669
 670 static void
 671 i965_render_set_surface_state(
 672     struct i965_surface_state *ss,
 673     dri_bo                    *bo,
 674     unsigned long              offset,
 675     unsigned int               width,
 676     unsigned int               height,
 677     unsigned int               pitch,
 678     unsigned int               format,
 679     unsigned int               flags
 680 )
 681 {
 682     unsigned int tiling;
 683     unsigned int swizzle;
 684
 685     memset(ss, 0, sizeof(*ss));
 686
 687     switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
 688     case I965_PP_FLAG_BOTTOM_FIELD:
 689         ss->ss0.vert_line_stride_ofs = 1;
 690         /* fall-through */
 691     case I965_PP_FLAG_TOP_FIELD:
 692         ss->ss0.vert_line_stride = 1;
 693         height /= 2;
 694         break;
 695     }
 696
 697     ss->ss0.surface_type = I965_SURFACE_2D;
 698     ss->ss0.surface_format = format;
 699     ss->ss0.color_blend = 1;
 700
 701     ss->ss1.base_addr = bo->offset + offset;
 702
 703     ss->ss2.width = width - 1;
 704     ss->ss2.height = height - 1;
 705
 706     ss->ss3.pitch = pitch - 1;
 707
 708     dri_bo_get_tiling(bo, &tiling, &swizzle);
 709     i965_render_set_surface_tiling(ss, tiling);
 710 }
 711
 712 static void
 713 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
 714 {
 715    switch (tiling) {
 716    case I915_TILING_NONE:
 717       ss->ss0.tiled_surface = 0;
 718       ss->ss0.tile_walk = 0;
 719       break;
 720    case I915_TILING_X:
 721       ss->ss0.tiled_surface = 1;
 722       ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 723       break;
 724    case I915_TILING_Y:
 725       ss->ss0.tiled_surface = 1;
 726       ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 727       break;
 728    }
 729 }
 730
 731 /* Set "Shader Channel Select" */
 732 void
 733 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
 734 {
 735     ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
 736     ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 737     ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 738     ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 739 }
 740
 741 static void
 742 gen7_render_set_surface_state(
 743     struct gen7_surface_state *ss,
 744     dri_bo                    *bo,
 745     unsigned long              offset,
 746     int                        width,
 747     int                        height,
 748     int                        pitch,
 749     int                        format,
 750     unsigned int               flags
 751 )
 752 {
 753     unsigned int tiling;
 754     unsigned int swizzle;
 755
 756     memset(ss, 0, sizeof(*ss));
 757
 758     switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
 759     case I965_PP_FLAG_BOTTOM_FIELD:
 760         ss->ss0.vert_line_stride_ofs = 1;
 761         /* fall-through */
 762     case I965_PP_FLAG_TOP_FIELD:
 763         ss->ss0.vert_line_stride = 1;
 764         height /= 2;
 765         break;
 766     }
 767
 768     ss->ss0.surface_type = I965_SURFACE_2D;
 769     ss->ss0.surface_format = format;
 770
 771     ss->ss1.base_addr = bo->offset + offset;
 772
 773     ss->ss2.width = width - 1;
 774     ss->ss2.height = height - 1;
 775
 776     ss->ss3.pitch = pitch - 1;
 777
 778     dri_bo_get_tiling(bo, &tiling, &swizzle);
 779     gen7_render_set_surface_tiling(ss, tiling);
 780 }
 781
 782 static void
 783 i965_render_src_surface_state(
 784     VADriverContextP ctx,
 785     int              index,
 786     dri_bo          *region,
 787     unsigned long    offset,
 788     int              w,
 789     int              h,
 790     int              pitch,
 791     int              format,
 792     unsigned int     flags
 793 )
 794 {
 795     struct i965_driver_data *i965 = i965_driver_data(ctx);
 796     struct i965_render_state *render_state = &i965->render_state;
 797     void *ss;
 798     dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
 799
 800     assert(index < MAX_RENDER_SURFACES);
 801
 802     dri_bo_map(ss_bo, 1);
 803     assert(ss_bo->virtual);
 804     ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
 805
 806     if (IS_GEN7(i965->intel.device_id)) {
 807         gen7_render_set_surface_state(ss,
 808                                       region, offset,
 809                                       w, h,
 810                                       pitch, format, flags);
 811         if (IS_HASWELL(i965->intel.device_id))
 812             gen7_render_set_surface_scs(ss);
 813         dri_bo_emit_reloc(ss_bo,
 814                           I915_GEM_DOMAIN_SAMPLER, 0,
 815                           offset,
 816                           SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 817                           region);
 818     } else {
 819         i965_render_set_surface_state(ss,
 820                                       region, offset,
 821                                       w, h,
 822                                       pitch, format, flags);
 823         dri_bo_emit_reloc(ss_bo,
 824                           I915_GEM_DOMAIN_SAMPLER, 0,
 825                           offset,
 826                           SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 827                           region);
 828     }
 829
 830     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 831     dri_bo_unmap(ss_bo);
 832     render_state->wm.sampler_count++;
 833 }
 834
 835 static void
 836 i965_render_src_surfaces_state(
 837     VADriverContextP ctx,
 838     struct object_surface *obj_surface,
 839     unsigned int     flags
 840 )
 841 {
 842     int region_pitch;
 843     int rw, rh;
 844     dri_bo *region;
 845
 846     region_pitch = obj_surface->width;
 847     rw = obj_surface->orig_width;
 848     rh = obj_surface->orig_height;
 849     region = obj_surface->bo;
 850
 851     i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);     /* Y */
 852     i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
 853
 854     if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2')) {
 855         i965_render_src_surface_state(ctx, 3, region,
 856                                       region_pitch * obj_surface->y_cb_offset,
 857                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
 858                                       I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
 859         i965_render_src_surface_state(ctx, 4, region,
 860                                       region_pitch * obj_surface->y_cb_offset,
 861                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
 862                                       I965_SURFACEFORMAT_R8G8_UNORM, flags);
 863     } else {
 864         i965_render_src_surface_state(ctx, 3, region,
 865                                       region_pitch * obj_surface->y_cb_offset,
 866                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
 867                                       I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
 868         i965_render_src_surface_state(ctx, 4, region,
 869                                       region_pitch * obj_surface->y_cb_offset,
 870                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
 871                                       I965_SURFACEFORMAT_R8_UNORM, flags);
 872         i965_render_src_surface_state(ctx, 5, region,
 873                                       region_pitch * obj_surface->y_cr_offset,
 874                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
 875                                       I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
 876         i965_render_src_surface_state(ctx, 6, region,
 877                                       region_pitch * obj_surface->y_cr_offset,
 878                                       obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
 879                                       I965_SURFACEFORMAT_R8_UNORM, flags);
 880     }
 881 }
 882
 883 static void
 884 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
 885                                       struct object_surface *obj_surface)
 886 {
 887     dri_bo *subpic_region;
 888     unsigned int index = obj_surface->subpic_render_idx;
 889     struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
 890     struct object_image *obj_image = obj_subpic->obj_image;
 891
 892     assert(obj_surface);
 893     assert(obj_surface->bo);
 894     subpic_region = obj_image->bo;
 895     /*subpicture surface*/
 896     i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
 897     i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
 898 }
 899
 900 static void
 901 i965_render_dest_surface_state(VADriverContextP ctx, int index)
 902 {
 903     struct i965_driver_data *i965 = i965_driver_data(ctx);
 904     struct i965_render_state *render_state = &i965->render_state;
 905     struct intel_region *dest_region = render_state->draw_region;
 906     void *ss;
 907     dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
 908     int format;
 909     assert(index < MAX_RENDER_SURFACES);
 910
 911     if (dest_region->cpp == 2) {
 912         format = I965_SURFACEFORMAT_B5G6R5_UNORM;
 913     } else {
 914         format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
 915     }
 916
 917     dri_bo_map(ss_bo, 1);
 918     assert(ss_bo->virtual);
 919     ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
 920
 921     if (IS_GEN7(i965->intel.device_id)) {
 922         gen7_render_set_surface_state(ss,
 923                                       dest_region->bo, 0,
 924                                       dest_region->width, dest_region->height,
 925                                       dest_region->pitch, format, 0);
 926         if (IS_HASWELL(i965->intel.device_id))
 927             gen7_render_set_surface_scs(ss);
 928         dri_bo_emit_reloc(ss_bo,
 929                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 930                           0,
 931                           SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 932                           dest_region->bo);
 933     } else {
 934         i965_render_set_surface_state(ss,
 935                                       dest_region->bo, 0,
 936                                       dest_region->width, dest_region->height,
 937                                       dest_region->pitch, format, 0);
 938         dri_bo_emit_reloc(ss_bo,
 939                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 940                           0,
 941                           SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 942                           dest_region->bo);
 943     }
 944
 945     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 946     dri_bo_unmap(ss_bo);
 947 }
 948
 949 static void
 950 i965_fill_vertex_buffer(
 951     VADriverContextP ctx,
 952     float tex_coords[4], /* [(u1,v1);(u2,v2)] */
 953     float vid_coords[4]  /* [(x1,y1);(x2,y2)] */
 954 )
 955 {
 956     struct i965_driver_data * const i965 = i965_driver_data(ctx);
 957     float vb[12];
 958
 959     enum { X1, Y1, X2, Y2 };
 960
 961     static const unsigned int g_rotation_indices[][6] = {
 962         [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
 963         [VA_ROTATION_90]   = { X2, Y1, X2, Y2, X1, Y2 },
 964         [VA_ROTATION_180]  = { X1, Y1, X2, Y1, X2, Y2 },
 965         [VA_ROTATION_270]  = { X1, Y2, X1, Y1, X2, Y1 },
 966     };
 967
 968     const unsigned int * const rotation_indices =
 969         g_rotation_indices[i965->rotation_attrib->value];
 970
 971     vb[0]  = tex_coords[rotation_indices[0]]; /* bottom-right corner */
 972     vb[1]  = tex_coords[rotation_indices[1]];
 973     vb[2]  = vid_coords[X2];
 974     vb[3]  = vid_coords[Y2];
 975
 976     vb[4]  = tex_coords[rotation_indices[2]]; /* bottom-left corner */
 977     vb[5]  = tex_coords[rotation_indices[3]];
 978     vb[6]  = vid_coords[X1];
 979     vb[7]  = vid_coords[Y2];
 980
 981     vb[8]  = tex_coords[rotation_indices[4]]; /* top-left corner */
 982     vb[9]  = tex_coords[rotation_indices[5]];
 983     vb[10] = vid_coords[X1];
 984     vb[11] = vid_coords[Y1];
 985
 986     dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
 987 }
 988
 989 static void
 990 i965_subpic_render_upload_vertex(VADriverContextP ctx,
 991                                  struct object_surface *obj_surface,
 992                                  const VARectangle *output_rect)
 993 {
 994     unsigned int index = obj_surface->subpic_render_idx;
 995     struct object_subpic     *obj_subpic   = obj_surface->obj_subpic[index];
 996     float tex_coords[4], vid_coords[4];
 997     VARectangle dst_rect;
 998
 999     if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1000         dst_rect = obj_subpic->dst_rect;
1001     else {
1002         const float sx  = (float)output_rect->width  / obj_surface->orig_width;
1003         const float sy  = (float)output_rect->height / obj_surface->orig_height;
1004         dst_rect.x      = output_rect->x + sx * obj_subpic->dst_rect.x;
1005         dst_rect.y      = output_rect->y + sy * obj_subpic->dst_rect.y;
1006         dst_rect.width  = sx * obj_subpic->dst_rect.width;
1007         dst_rect.height = sy * obj_subpic->dst_rect.height;
1008     }
1009
1010     tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1011     tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1012     tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1013     tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1014
1015     vid_coords[0] = dst_rect.x;
1016     vid_coords[1] = dst_rect.y;
1017     vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1018     vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1019
1020     i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1021 }
1022
1023 static void
1024 i965_render_upload_vertex(
1025     VADriverContextP   ctx,
1026     struct object_surface *obj_surface,
1027     const VARectangle *src_rect,
1028     const VARectangle *dst_rect
1029 )
1030 {
1031     struct i965_driver_data *i965 = i965_driver_data(ctx);
1032     struct i965_render_state *render_state = &i965->render_state;
1033     struct intel_region *dest_region = render_state->draw_region;
1034     float tex_coords[4], vid_coords[4];
1035     int width, height;
1036
1037     width  = obj_surface->orig_width;
1038     height = obj_surface->orig_height;
1039
1040     tex_coords[0] = (float)src_rect->x / width;
1041     tex_coords[1] = (float)src_rect->y / height;
1042     tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1043     tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1044
1045     vid_coords[0] = dest_region->x + dst_rect->x;
1046     vid_coords[1] = dest_region->y + dst_rect->y;
1047     vid_coords[2] = vid_coords[0] + dst_rect->width;
1048     vid_coords[3] = vid_coords[1] + dst_rect->height;
1049
1050     i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1051 }
1052
1053 static void
1054 i965_render_upload_constants(VADriverContextP ctx,
1055                              struct object_surface *obj_surface)
1056 {
1057     struct i965_driver_data *i965 = i965_driver_data(ctx);
1058     struct i965_render_state *render_state = &i965->render_state;
1059     unsigned short *constant_buffer;
1060
1061     dri_bo_map(render_state->curbe.bo, 1);
1062     assert(render_state->curbe.bo->virtual);
1063     constant_buffer = render_state->curbe.bo->virtual;
1064
1065     if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1066         assert(obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
1067                obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '3'));
1068         *constant_buffer = 2;
1069     } else {
1070         if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
1071             *constant_buffer = 1;
1072         else
1073             *constant_buffer = 0;
1074     }
1075
1076     dri_bo_unmap(render_state->curbe.bo);
1077 }
1078
1079 static void
1080 i965_subpic_render_upload_constants(VADriverContextP ctx,
1081                                     struct object_surface *obj_surface)
1082 {
1083     struct i965_driver_data *i965 = i965_driver_data(ctx);
1084     struct i965_render_state *render_state = &i965->render_state;
1085     float *constant_buffer;
1086     float global_alpha = 1.0;
1087     unsigned int index = obj_surface->subpic_render_idx;
1088     struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1089
1090     if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) {
1091         global_alpha = obj_subpic->global_alpha;
1092     }
1093
1094     dri_bo_map(render_state->curbe.bo, 1);
1095
1096     assert(render_state->curbe.bo->virtual);
1097     constant_buffer = render_state->curbe.bo->virtual;
1098     *constant_buffer = global_alpha;
1099
1100     dri_bo_unmap(render_state->curbe.bo);
1101 }
1102
1103 static void
1104 i965_surface_render_state_setup(
1105     VADriverContextP   ctx,
1106     struct object_surface *obj_surface,
1107     const VARectangle *src_rect,
1108     const VARectangle *dst_rect,
1109     unsigned int       flags
1110 )
1111 {
1112     i965_render_vs_unit(ctx);
1113     i965_render_sf_unit(ctx);
1114     i965_render_dest_surface_state(ctx, 0);
1115     i965_render_src_surfaces_state(ctx, obj_surface, flags);
1116     i965_render_sampler(ctx);
1117     i965_render_wm_unit(ctx);
1118     i965_render_cc_viewport(ctx);
1119     i965_render_cc_unit(ctx);
1120     i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1121     i965_render_upload_constants(ctx, obj_surface);
1122 }
1123
1124 static void
1125 i965_subpic_render_state_setup(
1126     VADriverContextP   ctx,
1127     struct object_surface *obj_surface,
1128     const VARectangle *src_rect,
1129     const VARectangle *dst_rect
1130 )
1131 {
1132     i965_render_vs_unit(ctx);
1133     i965_render_sf_unit(ctx);
1134     i965_render_dest_surface_state(ctx, 0);
1135     i965_subpic_render_src_surfaces_state(ctx, obj_surface);
1136     i965_render_sampler(ctx);
1137     i965_subpic_render_wm_unit(ctx);
1138     i965_render_cc_viewport(ctx);
1139     i965_subpic_render_cc_unit(ctx);
1140     i965_subpic_render_upload_constants(ctx, obj_surface);
1141     i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
1142 }
1143
1144
1145 static void
1146 i965_render_pipeline_select(VADriverContextP ctx)
1147 {
1148     struct i965_driver_data *i965 = i965_driver_data(ctx);
1149     struct intel_batchbuffer *batch = i965->batch;
1150
1151     BEGIN_BATCH(batch, 1);
1152     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1153     ADVANCE_BATCH(batch);
1154 }
1155
1156 static void
1157 i965_render_state_sip(VADriverContextP ctx)
1158 {
1159     struct i965_driver_data *i965 = i965_driver_data(ctx);
1160     struct intel_batchbuffer *batch = i965->batch;
1161
1162     BEGIN_BATCH(batch, 2);
1163     OUT_BATCH(batch, CMD_STATE_SIP | 0);
1164     OUT_BATCH(batch, 0);
1165     ADVANCE_BATCH(batch);
1166 }
1167
1168 static void
1169 i965_render_state_base_address(VADriverContextP ctx)
1170 {
1171     struct i965_driver_data *i965 = i965_driver_data(ctx);
1172     struct intel_batchbuffer *batch = i965->batch;
1173     struct i965_render_state *render_state = &i965->render_state;
1174
1175     if (IS_IRONLAKE(i965->intel.device_id)) {
1176         BEGIN_BATCH(batch, 8);
1177         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1178         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1179         OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1180         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1181         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1182         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1183         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1184         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1185         ADVANCE_BATCH(batch);
1186     } else {
1187         BEGIN_BATCH(batch, 6);
1188         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1189         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1190         OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1191         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1192         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1193         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1194         ADVANCE_BATCH(batch);
1195     }
1196 }
1197
1198 static void
1199 i965_render_binding_table_pointers(VADriverContextP ctx)
1200 {
1201     struct i965_driver_data *i965 = i965_driver_data(ctx);
1202     struct intel_batchbuffer *batch = i965->batch;
1203
1204     BEGIN_BATCH(batch, 6);
1205     OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1206     OUT_BATCH(batch, 0); /* vs */
1207     OUT_BATCH(batch, 0); /* gs */
1208     OUT_BATCH(batch, 0); /* clip */
1209     OUT_BATCH(batch, 0); /* sf */
1210     OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1211     ADVANCE_BATCH(batch);
1212 }
1213
1214 static void
1215 i965_render_constant_color(VADriverContextP ctx)
1216 {
1217     struct i965_driver_data *i965 = i965_driver_data(ctx);
1218     struct intel_batchbuffer *batch = i965->batch;
1219
1220     BEGIN_BATCH(batch, 5);
1221     OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1222     OUT_BATCH(batch, float_to_uint(1.0));
1223     OUT_BATCH(batch, float_to_uint(0.0));
1224     OUT_BATCH(batch, float_to_uint(1.0));
1225     OUT_BATCH(batch, float_to_uint(1.0));
1226     ADVANCE_BATCH(batch);
1227 }
1228
1229 static void
1230 i965_render_pipelined_pointers(VADriverContextP ctx)
1231 {
1232     struct i965_driver_data *i965 = i965_driver_data(ctx);
1233     struct intel_batchbuffer *batch = i965->batch;
1234     struct i965_render_state *render_state = &i965->render_state;
1235
1236     BEGIN_BATCH(batch, 7);
1237     OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1238     OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1239     OUT_BATCH(batch, 0);  /* disable GS */
1240     OUT_BATCH(batch, 0);  /* disable CLIP */
1241     OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1242     OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1243     OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1244     ADVANCE_BATCH(batch);
1245 }
1246
1247 static void
1248 i965_render_urb_layout(VADriverContextP ctx)
1249 {
1250     struct i965_driver_data *i965 = i965_driver_data(ctx);
1251     struct intel_batchbuffer *batch = i965->batch;
1252     int urb_vs_start, urb_vs_size;
1253     int urb_gs_start, urb_gs_size;
1254     int urb_clip_start, urb_clip_size;
1255     int urb_sf_start, urb_sf_size;
1256     int urb_cs_start, urb_cs_size;
1257
1258     urb_vs_start = 0;
1259     urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1260     urb_gs_start = urb_vs_start + urb_vs_size;
1261     urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1262     urb_clip_start = urb_gs_start + urb_gs_size;
1263     urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1264     urb_sf_start = urb_clip_start + urb_clip_size;
1265     urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1266     urb_cs_start = urb_sf_start + urb_sf_size;
1267     urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1268
1269     BEGIN_BATCH(batch, 3);
1270     OUT_BATCH(batch,
1271               CMD_URB_FENCE |
1272               UF0_CS_REALLOC |
1273               UF0_SF_REALLOC |
1274               UF0_CLIP_REALLOC |
1275               UF0_GS_REALLOC |
1276               UF0_VS_REALLOC |
1277               1);
1278     OUT_BATCH(batch,
1279               ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1280               ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1281               ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1282     OUT_BATCH(batch,
1283               ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1284               ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1285     ADVANCE_BATCH(batch);
1286 }
1287
1288 static void
1289 i965_render_cs_urb_layout(VADriverContextP ctx)
1290 {
1291     struct i965_driver_data *i965 = i965_driver_data(ctx);
1292     struct intel_batchbuffer *batch = i965->batch;
1293
1294     BEGIN_BATCH(batch, 2);
1295     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1296     OUT_BATCH(batch,
1297               ((URB_CS_ENTRY_SIZE - 1) << 4) |          /* URB Entry Allocation Size */
1298               (URB_CS_ENTRIES << 0));                /* Number of URB Entries */
1299     ADVANCE_BATCH(batch);
1300 }
1301
1302 static void
1303 i965_render_constant_buffer(VADriverContextP ctx)
1304 {
1305     struct i965_driver_data *i965 = i965_driver_data(ctx);
1306     struct intel_batchbuffer *batch = i965->batch;
1307     struct i965_render_state *render_state = &i965->render_state;
1308
1309     BEGIN_BATCH(batch, 2);
1310     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1311     OUT_RELOC(batch, render_state->curbe.bo,
1312               I915_GEM_DOMAIN_INSTRUCTION, 0,
1313               URB_CS_ENTRY_SIZE - 1);
1314     ADVANCE_BATCH(batch);
1315 }
1316
1317 static void
1318 i965_render_drawing_rectangle(VADriverContextP ctx)
1319 {
1320     struct i965_driver_data *i965 = i965_driver_data(ctx);
1321     struct intel_batchbuffer *batch = i965->batch;
1322     struct i965_render_state *render_state = &i965->render_state;
1323     struct intel_region *dest_region = render_state->draw_region;
1324
1325     BEGIN_BATCH(batch, 4);
1326     OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1327     OUT_BATCH(batch, 0x00000000);
1328     OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1329     OUT_BATCH(batch, 0x00000000);
1330     ADVANCE_BATCH(batch);
1331 }
1332
1333 static void
1334 i965_render_vertex_elements(VADriverContextP ctx)
1335 {
1336     struct i965_driver_data *i965 = i965_driver_data(ctx);
1337     struct intel_batchbuffer *batch = i965->batch;
1338
1339     if (IS_IRONLAKE(i965->intel.device_id)) {
1340         BEGIN_BATCH(batch, 5);
1341         OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1342         /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1343         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1344                   VE0_VALID |
1345                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1346                   (0 << VE0_OFFSET_SHIFT));
1347         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1348                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1349                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1350                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1351         /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1352         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1353                   VE0_VALID |
1354                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1355                   (8 << VE0_OFFSET_SHIFT));
1356         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1357                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1358                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1359                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1360         ADVANCE_BATCH(batch);
1361     } else {
1362         BEGIN_BATCH(batch, 5);
1363         OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1364         /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1365         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1366                   VE0_VALID |
1367                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1368                   (0 << VE0_OFFSET_SHIFT));
1369         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1370                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1371                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1372                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1373                   (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1374         /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1375         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1376                   VE0_VALID |
1377                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1378                   (8 << VE0_OFFSET_SHIFT));
1379         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1380                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1381                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1382                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1383                   (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1384         ADVANCE_BATCH(batch);
1385     }
1386 }
1387
1388 static void
1389 i965_render_upload_image_palette(
1390     VADriverContextP ctx,
1391     struct object_image *obj_image,
1392     unsigned int     alpha
1393 )
1394 {
1395     struct i965_driver_data *i965 = i965_driver_data(ctx);
1396     struct intel_batchbuffer *batch = i965->batch;
1397     unsigned int i;
1398
1399     assert(obj_image);
1400
1401     if (!obj_image)
1402         return;
1403
1404     if (obj_image->image.num_palette_entries == 0)
1405         return;
1406
1407     BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1408     OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1409     /*fill palette*/
1410     //int32_t out[16]; //0-23:color 23-31:alpha
1411     for (i = 0; i < obj_image->image.num_palette_entries; i++)
1412         OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1413     ADVANCE_BATCH(batch);
1414 }
1415
1416 static void
1417 i965_render_startup(VADriverContextP ctx)
1418 {
1419     struct i965_driver_data *i965 = i965_driver_data(ctx);
1420     struct intel_batchbuffer *batch = i965->batch;
1421     struct i965_render_state *render_state = &i965->render_state;
1422
1423     BEGIN_BATCH(batch, 11);
1424     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1425     OUT_BATCH(batch,
1426               (0 << VB0_BUFFER_INDEX_SHIFT) |
1427               VB0_VERTEXDATA |
1428               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1429     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1430
1431     if (IS_IRONLAKE(i965->intel.device_id))
1432         OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1433     else
1434         OUT_BATCH(batch, 3);
1435
1436     OUT_BATCH(batch, 0);
1437
1438     OUT_BATCH(batch,
1439               CMD_3DPRIMITIVE |
1440               _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1441               (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1442               (0 << 9) |
1443               4);
1444     OUT_BATCH(batch, 3); /* vertex count per instance */
1445     OUT_BATCH(batch, 0); /* start vertex offset */
1446     OUT_BATCH(batch, 1); /* single instance */
1447     OUT_BATCH(batch, 0); /* start instance location */
1448     OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1449     ADVANCE_BATCH(batch);
1450 }
1451
1452 static void
1453 i965_clear_dest_region(VADriverContextP ctx)
1454 {
1455     struct i965_driver_data *i965 = i965_driver_data(ctx);
1456     struct intel_batchbuffer *batch = i965->batch;
1457     struct i965_render_state *render_state = &i965->render_state;
1458     struct intel_region *dest_region = render_state->draw_region;
1459     unsigned int blt_cmd, br13;
1460     int pitch;
1461
1462     blt_cmd = XY_COLOR_BLT_CMD;
1463     br13 = 0xf0 << 16;
1464     pitch = dest_region->pitch;
1465
1466     if (dest_region->cpp == 4) {
1467         br13 |= BR13_8888;
1468         blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1469     } else {
1470         assert(dest_region->cpp == 2);
1471         br13 |= BR13_565;
1472     }
1473
1474     if (dest_region->tiling != I915_TILING_NONE) {
1475         blt_cmd |= XY_COLOR_BLT_DST_TILED;
1476         pitch /= 4;
1477     }
1478
1479     br13 |= pitch;
1480
1481     if (IS_GEN6(i965->intel.device_id) ||
1482         IS_GEN7(i965->intel.device_id)) {
1483         intel_batchbuffer_start_atomic_blt(batch, 24);
1484         BEGIN_BLT_BATCH(batch, 6);
1485     } else {
1486         intel_batchbuffer_start_atomic(batch, 24);
1487         BEGIN_BATCH(batch, 6);
1488     }
1489
1490     OUT_BATCH(batch, blt_cmd);
1491     OUT_BATCH(batch, br13);
1492     OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1493     OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1494               (dest_region->x + dest_region->width));
1495     OUT_RELOC(batch, dest_region->bo,
1496               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1497               0);
1498     OUT_BATCH(batch, 0x0);
1499     ADVANCE_BATCH(batch);
1500     intel_batchbuffer_end_atomic(batch);
1501 }
1502
1503 static void
1504 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1505 {
1506     struct i965_driver_data *i965 = i965_driver_data(ctx);
1507     struct intel_batchbuffer *batch = i965->batch;
1508
1509     i965_clear_dest_region(ctx);
1510     intel_batchbuffer_start_atomic(batch, 0x1000);
1511     intel_batchbuffer_emit_mi_flush(batch);
1512     i965_render_pipeline_select(ctx);
1513     i965_render_state_sip(ctx);
1514     i965_render_state_base_address(ctx);
1515     i965_render_binding_table_pointers(ctx);
1516     i965_render_constant_color(ctx);
1517     i965_render_pipelined_pointers(ctx);
1518     i965_render_urb_layout(ctx);
1519     i965_render_cs_urb_layout(ctx);
1520     i965_render_constant_buffer(ctx);
1521     i965_render_drawing_rectangle(ctx);
1522     i965_render_vertex_elements(ctx);
1523     i965_render_startup(ctx);
1524     intel_batchbuffer_end_atomic(batch);
1525 }
1526
1527 static void
1528 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1529 {
1530     struct i965_driver_data *i965 = i965_driver_data(ctx);
1531     struct intel_batchbuffer *batch = i965->batch;
1532
1533     intel_batchbuffer_start_atomic(batch, 0x1000);
1534     intel_batchbuffer_emit_mi_flush(batch);
1535     i965_render_pipeline_select(ctx);
1536     i965_render_state_sip(ctx);
1537     i965_render_state_base_address(ctx);
1538     i965_render_binding_table_pointers(ctx);
1539     i965_render_constant_color(ctx);
1540     i965_render_pipelined_pointers(ctx);
1541     i965_render_urb_layout(ctx);
1542     i965_render_cs_urb_layout(ctx);
1543     i965_render_drawing_rectangle(ctx);
1544     i965_render_vertex_elements(ctx);
1545     i965_render_startup(ctx);
1546     intel_batchbuffer_end_atomic(batch);
1547 }
1548
1549
1550 static void
1551 i965_render_initialize(VADriverContextP ctx)
1552 {
1553     struct i965_driver_data *i965 = i965_driver_data(ctx);
1554     struct i965_render_state *render_state = &i965->render_state;
1555     dri_bo *bo;
1556
1557     /* VERTEX BUFFER */
1558     dri_bo_unreference(render_state->vb.vertex_buffer);
1559     bo = dri_bo_alloc(i965->intel.bufmgr,
1560                       "vertex buffer",
1561                       4096,
1562                       4096);
1563     assert(bo);
1564     render_state->vb.vertex_buffer = bo;
1565
1566     /* VS */
1567     dri_bo_unreference(render_state->vs.state);
1568     bo = dri_bo_alloc(i965->intel.bufmgr,
1569                       "vs state",
1570                       sizeof(struct i965_vs_unit_state),
1571                       64);
1572     assert(bo);
1573     render_state->vs.state = bo;
1574
1575     /* GS */
1576     /* CLIP */
1577     /* SF */
1578     dri_bo_unreference(render_state->sf.state);
1579     bo = dri_bo_alloc(i965->intel.bufmgr,
1580                       "sf state",
1581                       sizeof(struct i965_sf_unit_state),
1582                       64);
1583     assert(bo);
1584     render_state->sf.state = bo;
1585
1586     /* WM */
1587     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1588     bo = dri_bo_alloc(i965->intel.bufmgr,
1589                       "surface state & binding table",
1590                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1591                       4096);
1592     assert(bo);
1593     render_state->wm.surface_state_binding_table_bo = bo;
1594
1595     dri_bo_unreference(render_state->wm.sampler);
1596     bo = dri_bo_alloc(i965->intel.bufmgr,
1597                       "sampler state",
1598                       MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1599                       64);
1600     assert(bo);
1601     render_state->wm.sampler = bo;
1602     render_state->wm.sampler_count = 0;
1603
1604     dri_bo_unreference(render_state->wm.state);
1605     bo = dri_bo_alloc(i965->intel.bufmgr,
1606                       "wm state",
1607                       sizeof(struct i965_wm_unit_state),
1608                       64);
1609     assert(bo);
1610     render_state->wm.state = bo;
1611
1612     /* COLOR CALCULATOR */
1613     dri_bo_unreference(render_state->cc.state);
1614     bo = dri_bo_alloc(i965->intel.bufmgr,
1615                       "color calc state",
1616                       sizeof(struct i965_cc_unit_state),
1617                       64);
1618     assert(bo);
1619     render_state->cc.state = bo;
1620
1621     dri_bo_unreference(render_state->cc.viewport);
1622     bo = dri_bo_alloc(i965->intel.bufmgr,
1623                       "cc viewport",
1624                       sizeof(struct i965_cc_viewport),
1625                       64);
1626     assert(bo);
1627     render_state->cc.viewport = bo;
1628 }
1629
1630 static void
1631 i965_render_put_surface(
1632     VADriverContextP   ctx,
1633     struct object_surface *obj_surface,
1634     const VARectangle *src_rect,
1635     const VARectangle *dst_rect,
1636     unsigned int       flags
1637 )
1638 {
1639     struct i965_driver_data *i965 = i965_driver_data(ctx);
1640     struct intel_batchbuffer *batch = i965->batch;
1641
1642     i965_render_initialize(ctx);
1643     i965_surface_render_state_setup(ctx, obj_surface, src_rect, dst_rect, flags);
1644     i965_surface_render_pipeline_setup(ctx);
1645     intel_batchbuffer_flush(batch);
1646 }
1647
1648 static void
1649 i965_render_put_subpicture(
1650     VADriverContextP   ctx,
1651     struct object_surface *obj_surface,
1652     const VARectangle *src_rect,
1653     const VARectangle *dst_rect
1654 )
1655 {
1656     struct i965_driver_data *i965 = i965_driver_data(ctx);
1657     struct intel_batchbuffer *batch = i965->batch;
1658     unsigned int index = obj_surface->subpic_render_idx;
1659     struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1660
1661     assert(obj_subpic);
1662
1663     i965_render_initialize(ctx);
1664     i965_subpic_render_state_setup(ctx, obj_surface, src_rect, dst_rect);
1665     i965_subpic_render_pipeline_setup(ctx);
1666     i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
1667     intel_batchbuffer_flush(batch);
1668 }
1669
1670 /*
1671  * for GEN6+
1672  */
1673 static void
1674 gen6_render_initialize(VADriverContextP ctx)
1675 {
1676     struct i965_driver_data *i965 = i965_driver_data(ctx);
1677     struct i965_render_state *render_state = &i965->render_state;
1678     dri_bo *bo;
1679
1680     /* VERTEX BUFFER */
1681     dri_bo_unreference(render_state->vb.vertex_buffer);
1682     bo = dri_bo_alloc(i965->intel.bufmgr,
1683                       "vertex buffer",
1684                       4096,
1685                       4096);
1686     assert(bo);
1687     render_state->vb.vertex_buffer = bo;
1688
1689     /* WM */
1690     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1691     bo = dri_bo_alloc(i965->intel.bufmgr,
1692                       "surface state & binding table",
1693                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1694                       4096);
1695     assert(bo);
1696     render_state->wm.surface_state_binding_table_bo = bo;
1697
1698     dri_bo_unreference(render_state->wm.sampler);
1699     bo = dri_bo_alloc(i965->intel.bufmgr,
1700                       "sampler state",
1701                       MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1702                       4096);
1703     assert(bo);
1704     render_state->wm.sampler = bo;
1705     render_state->wm.sampler_count = 0;
1706
1707     /* COLOR CALCULATOR */
1708     dri_bo_unreference(render_state->cc.state);
1709     bo = dri_bo_alloc(i965->intel.bufmgr,
1710                       "color calc state",
1711                       sizeof(struct gen6_color_calc_state),
1712                       4096);
1713     assert(bo);
1714     render_state->cc.state = bo;
1715
1716     /* CC VIEWPORT */
1717     dri_bo_unreference(render_state->cc.viewport);
1718     bo = dri_bo_alloc(i965->intel.bufmgr,
1719                       "cc viewport",
1720                       sizeof(struct i965_cc_viewport),
1721                       4096);
1722     assert(bo);
1723     render_state->cc.viewport = bo;
1724
1725     /* BLEND STATE */
1726     dri_bo_unreference(render_state->cc.blend);
1727     bo = dri_bo_alloc(i965->intel.bufmgr,
1728                       "blend state",
1729                       sizeof(struct gen6_blend_state),
1730                       4096);
1731     assert(bo);
1732     render_state->cc.blend = bo;
1733
1734     /* DEPTH & STENCIL STATE */
1735     dri_bo_unreference(render_state->cc.depth_stencil);
1736     bo = dri_bo_alloc(i965->intel.bufmgr,
1737                       "depth & stencil state",
1738                       sizeof(struct gen6_depth_stencil_state),
1739                       4096);
1740     assert(bo);
1741     render_state->cc.depth_stencil = bo;
1742 }
1743
1744 static void
1745 gen6_render_color_calc_state(VADriverContextP ctx)
1746 {
1747     struct i965_driver_data *i965 = i965_driver_data(ctx);
1748     struct i965_render_state *render_state = &i965->render_state;
1749     struct gen6_color_calc_state *color_calc_state;
1750
1751     dri_bo_map(render_state->cc.state, 1);
1752     assert(render_state->cc.state->virtual);
1753     color_calc_state = render_state->cc.state->virtual;
1754     memset(color_calc_state, 0, sizeof(*color_calc_state));
1755     color_calc_state->constant_r = 1.0;
1756     color_calc_state->constant_g = 0.0;
1757     color_calc_state->constant_b = 1.0;
1758     color_calc_state->constant_a = 1.0;
1759     dri_bo_unmap(render_state->cc.state);
1760 }
1761
1762 static void
1763 gen6_render_blend_state(VADriverContextP ctx)
1764 {
1765     struct i965_driver_data *i965 = i965_driver_data(ctx);
1766     struct i965_render_state *render_state = &i965->render_state;
1767     struct gen6_blend_state *blend_state;
1768
1769     dri_bo_map(render_state->cc.blend, 1);
1770     assert(render_state->cc.blend->virtual);
1771     blend_state = render_state->cc.blend->virtual;
1772     memset(blend_state, 0, sizeof(*blend_state));
1773     blend_state->blend1.logic_op_enable = 1;
1774     blend_state->blend1.logic_op_func = 0xc;
1775     dri_bo_unmap(render_state->cc.blend);
1776 }
1777
1778 static void
1779 gen6_render_depth_stencil_state(VADriverContextP ctx)
1780 {
1781     struct i965_driver_data *i965 = i965_driver_data(ctx);
1782     struct i965_render_state *render_state = &i965->render_state;
1783     struct gen6_depth_stencil_state *depth_stencil_state;
1784
1785     dri_bo_map(render_state->cc.depth_stencil, 1);
1786     assert(render_state->cc.depth_stencil->virtual);
1787     depth_stencil_state = render_state->cc.depth_stencil->virtual;
1788     memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1789     dri_bo_unmap(render_state->cc.depth_stencil);
1790 }
1791
1792 static void
1793 gen6_render_setup_states(
1794     VADriverContextP   ctx,
1795     struct object_surface *obj_surface,
1796     const VARectangle *src_rect,
1797     const VARectangle *dst_rect,
1798     unsigned int       flags
1799 )
1800 {
1801     i965_render_dest_surface_state(ctx, 0);
1802     i965_render_src_surfaces_state(ctx, obj_surface, flags);
1803     i965_render_sampler(ctx);
1804     i965_render_cc_viewport(ctx);
1805     gen6_render_color_calc_state(ctx);
1806     gen6_render_blend_state(ctx);
1807     gen6_render_depth_stencil_state(ctx);
1808     i965_render_upload_constants(ctx, obj_surface);
1809     i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1810 }
1811
1812 static void
1813 gen6_emit_invarient_states(VADriverContextP ctx)
1814 {
1815     struct i965_driver_data *i965 = i965_driver_data(ctx);
1816     struct intel_batchbuffer *batch = i965->batch;
1817
1818     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1819
1820     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1821     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1822               GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1823     OUT_BATCH(batch, 0);
1824
1825     OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1826     OUT_BATCH(batch, 1);
1827
1828     /* Set system instruction pointer */
1829     OUT_BATCH(batch, CMD_STATE_SIP | 0);
1830     OUT_BATCH(batch, 0);
1831 }
1832
1833 static void
1834 gen6_emit_state_base_address(VADriverContextP ctx)
1835 {
1836     struct i965_driver_data *i965 = i965_driver_data(ctx);
1837     struct intel_batchbuffer *batch = i965->batch;
1838     struct i965_render_state *render_state = &i965->render_state;
1839
1840     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1841     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1842     OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1843     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1844     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1845     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1846     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1847     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1848     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1849     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1850 }
1851
1852 static void
1853 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1854 {
1855     struct i965_driver_data *i965 = i965_driver_data(ctx);
1856     struct intel_batchbuffer *batch = i965->batch;
1857     struct i965_render_state *render_state = &i965->render_state;
1858
1859     OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1860               GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1861               (4 - 2));
1862     OUT_BATCH(batch, 0);
1863     OUT_BATCH(batch, 0);
1864     OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1865 }
1866
1867 static void
1868 gen6_emit_urb(VADriverContextP ctx)
1869 {
1870     struct i965_driver_data *i965 = i965_driver_data(ctx);
1871     struct intel_batchbuffer *batch = i965->batch;
1872
1873     OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1874     OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1875               (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1876     OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1877               (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1878 }
1879
1880 static void
1881 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1882 {
1883     struct i965_driver_data *i965 = i965_driver_data(ctx);
1884     struct intel_batchbuffer *batch = i965->batch;
1885     struct i965_render_state *render_state = &i965->render_state;
1886
1887     OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1888     OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1889     OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1890     OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1891 }
1892
1893 static void
1894 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1895 {
1896     struct i965_driver_data *i965 = i965_driver_data(ctx);
1897     struct intel_batchbuffer *batch = i965->batch;
1898     struct i965_render_state *render_state = &i965->render_state;
1899
1900     OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1901               GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1902               (4 - 2));
1903     OUT_BATCH(batch, 0); /* VS */
1904     OUT_BATCH(batch, 0); /* GS */
1905     OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1906 }
1907
1908 static void
1909 gen6_emit_binding_table(VADriverContextP ctx)
1910 {
1911     struct i965_driver_data *i965 = i965_driver_data(ctx);
1912     struct intel_batchbuffer *batch = i965->batch;
1913
1914     /* Binding table pointers */
1915     OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1916               GEN6_BINDING_TABLE_MODIFY_PS |
1917               (4 - 2));
1918     OUT_BATCH(batch, 0);                /* vs */
1919     OUT_BATCH(batch, 0);                /* gs */
1920     /* Only the PS uses the binding table */
1921     OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1922 }
1923
1924 static void
1925 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1926 {
1927     struct i965_driver_data *i965 = i965_driver_data(ctx);
1928     struct intel_batchbuffer *batch = i965->batch;
1929
1930     OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1931     OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1932               (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1933     OUT_BATCH(batch, 0);
1934     OUT_BATCH(batch, 0);
1935     OUT_BATCH(batch, 0);
1936     OUT_BATCH(batch, 0);
1937     OUT_BATCH(batch, 0);
1938
1939     OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
1940     OUT_BATCH(batch, 0);
1941 }
1942
1943 static void
1944 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1945 {
1946     i965_render_drawing_rectangle(ctx);
1947 }
1948
1949 static void
1950 gen6_emit_vs_state(VADriverContextP ctx)
1951 {
1952     struct i965_driver_data *i965 = i965_driver_data(ctx);
1953     struct intel_batchbuffer *batch = i965->batch;
1954
1955     /* disable VS constant buffer */
1956     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1957     OUT_BATCH(batch, 0);
1958     OUT_BATCH(batch, 0);
1959     OUT_BATCH(batch, 0);
1960     OUT_BATCH(batch, 0);
1961
1962     OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
1963     OUT_BATCH(batch, 0); /* without VS kernel */
1964     OUT_BATCH(batch, 0);
1965     OUT_BATCH(batch, 0);
1966     OUT_BATCH(batch, 0);
1967     OUT_BATCH(batch, 0); /* pass-through */
1968 }
1969
1970 static void
1971 gen6_emit_gs_state(VADriverContextP ctx)
1972 {
1973     struct i965_driver_data *i965 = i965_driver_data(ctx);
1974     struct intel_batchbuffer *batch = i965->batch;
1975
1976     /* disable GS constant buffer */
1977     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
1978     OUT_BATCH(batch, 0);
1979     OUT_BATCH(batch, 0);
1980     OUT_BATCH(batch, 0);
1981     OUT_BATCH(batch, 0);
1982
1983     OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
1984     OUT_BATCH(batch, 0); /* without GS kernel */
1985     OUT_BATCH(batch, 0);
1986     OUT_BATCH(batch, 0);
1987     OUT_BATCH(batch, 0);
1988     OUT_BATCH(batch, 0);
1989     OUT_BATCH(batch, 0); /* pass-through */
1990 }
1991
1992 static void
1993 gen6_emit_clip_state(VADriverContextP ctx)
1994 {
1995     struct i965_driver_data *i965 = i965_driver_data(ctx);
1996     struct intel_batchbuffer *batch = i965->batch;
1997
1998     OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
1999     OUT_BATCH(batch, 0);
2000     OUT_BATCH(batch, 0); /* pass-through */
2001     OUT_BATCH(batch, 0);
2002 }
2003
2004 static void
2005 gen6_emit_sf_state(VADriverContextP ctx)
2006 {
2007     struct i965_driver_data *i965 = i965_driver_data(ctx);
2008     struct intel_batchbuffer *batch = i965->batch;
2009
2010     OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2011     OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2012               (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2013               (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2014     OUT_BATCH(batch, 0);
2015     OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2016     OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2017     OUT_BATCH(batch, 0);
2018     OUT_BATCH(batch, 0);
2019     OUT_BATCH(batch, 0);
2020     OUT_BATCH(batch, 0);
2021     OUT_BATCH(batch, 0); /* DW9 */
2022     OUT_BATCH(batch, 0);
2023     OUT_BATCH(batch, 0);
2024     OUT_BATCH(batch, 0);
2025     OUT_BATCH(batch, 0);
2026     OUT_BATCH(batch, 0); /* DW14 */
2027     OUT_BATCH(batch, 0);
2028     OUT_BATCH(batch, 0);
2029     OUT_BATCH(batch, 0);
2030     OUT_BATCH(batch, 0);
2031     OUT_BATCH(batch, 0); /* DW19 */
2032 }
2033
2034 static void
2035 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2036 {
2037     struct i965_driver_data *i965 = i965_driver_data(ctx);
2038     struct intel_batchbuffer *batch = i965->batch;
2039     struct i965_render_state *render_state = &i965->render_state;
2040
2041     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2042               GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2043               (5 - 2));
2044     OUT_RELOC(batch,
2045               render_state->curbe.bo,
2046               I915_GEM_DOMAIN_INSTRUCTION, 0,
2047               0);
2048     OUT_BATCH(batch, 0);
2049     OUT_BATCH(batch, 0);
2050     OUT_BATCH(batch, 0);
2051
2052     OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2053     OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2054               I915_GEM_DOMAIN_INSTRUCTION, 0,
2055               0);
2056     OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2057               (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2058     OUT_BATCH(batch, 0);
2059     OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2060     OUT_BATCH(batch, ((render_state->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2061               GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2062               GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2063     OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2064               GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2065     OUT_BATCH(batch, 0);
2066     OUT_BATCH(batch, 0);
2067 }
2068
2069 static void
2070 gen6_emit_vertex_element_state(VADriverContextP ctx)
2071 {
2072     struct i965_driver_data *i965 = i965_driver_data(ctx);
2073     struct intel_batchbuffer *batch = i965->batch;
2074
2075     /* Set up our vertex elements, sourced from the single vertex buffer. */
2076     OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2077     /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2078     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2079               GEN6_VE0_VALID |
2080               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2081               (0 << VE0_OFFSET_SHIFT));
2082     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2083               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2084               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2085               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2086     /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2087     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2088               GEN6_VE0_VALID |
2089               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2090               (8 << VE0_OFFSET_SHIFT));
2091     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2092               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2093               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2094               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2095 }
2096
2097 static void
2098 gen6_emit_vertices(VADriverContextP ctx)
2099 {
2100     struct i965_driver_data *i965 = i965_driver_data(ctx);
2101     struct intel_batchbuffer *batch = i965->batch;
2102     struct i965_render_state *render_state = &i965->render_state;
2103
2104     BEGIN_BATCH(batch, 11);
2105     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2106     OUT_BATCH(batch,
2107               (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2108               GEN6_VB0_VERTEXDATA |
2109               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2110     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2111     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2112     OUT_BATCH(batch, 0);
2113
2114     OUT_BATCH(batch,
2115               CMD_3DPRIMITIVE |
2116               _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2117               (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2118               (0 << 9) |
2119               4);
2120     OUT_BATCH(batch, 3); /* vertex count per instance */
2121     OUT_BATCH(batch, 0); /* start vertex offset */
2122     OUT_BATCH(batch, 1); /* single instance */
2123     OUT_BATCH(batch, 0); /* start instance location */
2124     OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2125     ADVANCE_BATCH(batch);
2126 }
2127
2128 static void
2129 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2130 {
2131     struct i965_driver_data *i965 = i965_driver_data(ctx);
2132     struct intel_batchbuffer *batch = i965->batch;
2133
2134     intel_batchbuffer_start_atomic(batch, 0x1000);
2135     intel_batchbuffer_emit_mi_flush(batch);
2136     gen6_emit_invarient_states(ctx);
2137     gen6_emit_state_base_address(ctx);
2138     gen6_emit_viewport_state_pointers(ctx);
2139     gen6_emit_urb(ctx);
2140     gen6_emit_cc_state_pointers(ctx);
2141     gen6_emit_sampler_state_pointers(ctx);
2142     gen6_emit_vs_state(ctx);
2143     gen6_emit_gs_state(ctx);
2144     gen6_emit_clip_state(ctx);
2145     gen6_emit_sf_state(ctx);
2146     gen6_emit_wm_state(ctx, kernel);
2147     gen6_emit_binding_table(ctx);
2148     gen6_emit_depth_buffer_state(ctx);
2149     gen6_emit_drawing_rectangle(ctx);
2150     gen6_emit_vertex_element_state(ctx);
2151     gen6_emit_vertices(ctx);
2152     intel_batchbuffer_end_atomic(batch);
2153 }
2154
2155 static void
2156 gen6_render_put_surface(
2157     VADriverContextP   ctx,
2158     struct object_surface *obj_surface,
2159     const VARectangle *src_rect,
2160     const VARectangle *dst_rect,
2161     unsigned int       flags
2162 )
2163 {
2164     struct i965_driver_data *i965 = i965_driver_data(ctx);
2165     struct intel_batchbuffer *batch = i965->batch;
2166
2167     gen6_render_initialize(ctx);
2168     gen6_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2169     i965_clear_dest_region(ctx);
2170     gen6_render_emit_states(ctx, PS_KERNEL);
2171     intel_batchbuffer_flush(batch);
2172 }
2173
2174 static void
2175 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2176 {
2177     struct i965_driver_data *i965 = i965_driver_data(ctx);
2178     struct i965_render_state *render_state = &i965->render_state;
2179     struct gen6_blend_state *blend_state;
2180
2181     dri_bo_unmap(render_state->cc.state);
2182     dri_bo_map(render_state->cc.blend, 1);
2183     assert(render_state->cc.blend->virtual);
2184     blend_state = render_state->cc.blend->virtual;
2185     memset(blend_state, 0, sizeof(*blend_state));
2186     blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2187     blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2188     blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2189     blend_state->blend0.blend_enable = 1;
2190     blend_state->blend1.post_blend_clamp_enable = 1;
2191     blend_state->blend1.pre_blend_clamp_enable = 1;
2192     blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2193     dri_bo_unmap(render_state->cc.blend);
2194 }
2195
2196 static void
2197 gen6_subpicture_render_setup_states(
2198     VADriverContextP   ctx,
2199     struct object_surface *obj_surface,
2200     const VARectangle *src_rect,
2201     const VARectangle *dst_rect
2202 )
2203 {
2204     i965_render_dest_surface_state(ctx, 0);
2205     i965_subpic_render_src_surfaces_state(ctx, obj_surface);
2206     i965_render_sampler(ctx);
2207     i965_render_cc_viewport(ctx);
2208     gen6_render_color_calc_state(ctx);
2209     gen6_subpicture_render_blend_state(ctx);
2210     gen6_render_depth_stencil_state(ctx);
2211     i965_subpic_render_upload_constants(ctx, obj_surface);
2212     i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
2213 }
2214
2215 static void
2216 gen6_render_put_subpicture(
2217     VADriverContextP   ctx,
2218     struct object_surface *obj_surface,
2219     const VARectangle *src_rect,
2220     const VARectangle *dst_rect
2221 )
2222 {
2223     struct i965_driver_data *i965 = i965_driver_data(ctx);
2224     struct intel_batchbuffer *batch = i965->batch;
2225     unsigned int index = obj_surface->subpic_render_idx;
2226     struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
2227
2228     assert(obj_subpic);
2229     gen6_render_initialize(ctx);
2230     gen6_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
2231     gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2232     i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
2233     intel_batchbuffer_flush(batch);
2234 }
2235
2236 /*
2237  * for GEN7
2238  */
2239 static void
2240 gen7_render_initialize(VADriverContextP ctx)
2241 {
2242     struct i965_driver_data *i965 = i965_driver_data(ctx);
2243     struct i965_render_state *render_state = &i965->render_state;
2244     dri_bo *bo;
2245
2246     /* VERTEX BUFFER */
2247     dri_bo_unreference(render_state->vb.vertex_buffer);
2248     bo = dri_bo_alloc(i965->intel.bufmgr,
2249                       "vertex buffer",
2250                       4096,
2251                       4096);
2252     assert(bo);
2253     render_state->vb.vertex_buffer = bo;
2254
2255     /* WM */
2256     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2257     bo = dri_bo_alloc(i965->intel.bufmgr,
2258                       "surface state & binding table",
2259                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2260                       4096);
2261     assert(bo);
2262     render_state->wm.surface_state_binding_table_bo = bo;
2263
2264     dri_bo_unreference(render_state->wm.sampler);
2265     bo = dri_bo_alloc(i965->intel.bufmgr,
2266                       "sampler state",
2267                       MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2268                       4096);
2269     assert(bo);
2270     render_state->wm.sampler = bo;
2271     render_state->wm.sampler_count = 0;
2272
2273     /* COLOR CALCULATOR */
2274     dri_bo_unreference(render_state->cc.state);
2275     bo = dri_bo_alloc(i965->intel.bufmgr,
2276                       "color calc state",
2277                       sizeof(struct gen6_color_calc_state),
2278                       4096);
2279     assert(bo);
2280     render_state->cc.state = bo;
2281
2282     /* CC VIEWPORT */
2283     dri_bo_unreference(render_state->cc.viewport);
2284     bo = dri_bo_alloc(i965->intel.bufmgr,
2285                       "cc viewport",
2286                       sizeof(struct i965_cc_viewport),
2287                       4096);
2288     assert(bo);
2289     render_state->cc.viewport = bo;
2290
2291     /* BLEND STATE */
2292     dri_bo_unreference(render_state->cc.blend);
2293     bo = dri_bo_alloc(i965->intel.bufmgr,
2294                       "blend state",
2295                       sizeof(struct gen6_blend_state),
2296                       4096);
2297     assert(bo);
2298     render_state->cc.blend = bo;
2299
2300     /* DEPTH & STENCIL STATE */
2301     dri_bo_unreference(render_state->cc.depth_stencil);
2302     bo = dri_bo_alloc(i965->intel.bufmgr,
2303                       "depth & stencil state",
2304                       sizeof(struct gen6_depth_stencil_state),
2305                       4096);
2306     assert(bo);
2307     render_state->cc.depth_stencil = bo;
2308 }
2309
2310 static void
2311 gen7_render_color_calc_state(VADriverContextP ctx)
2312 {
2313     struct i965_driver_data *i965 = i965_driver_data(ctx);
2314     struct i965_render_state *render_state = &i965->render_state;
2315     struct gen6_color_calc_state *color_calc_state;
2316
2317     dri_bo_map(render_state->cc.state, 1);
2318     assert(render_state->cc.state->virtual);
2319     color_calc_state = render_state->cc.state->virtual;
2320     memset(color_calc_state, 0, sizeof(*color_calc_state));
2321     color_calc_state->constant_r = 1.0;
2322     color_calc_state->constant_g = 0.0;
2323     color_calc_state->constant_b = 1.0;
2324     color_calc_state->constant_a = 1.0;
2325     dri_bo_unmap(render_state->cc.state);
2326 }
2327
2328 static void
2329 gen7_render_blend_state(VADriverContextP ctx)
2330 {
2331     struct i965_driver_data *i965 = i965_driver_data(ctx);
2332     struct i965_render_state *render_state = &i965->render_state;
2333     struct gen6_blend_state *blend_state;
2334
2335     dri_bo_map(render_state->cc.blend, 1);
2336     assert(render_state->cc.blend->virtual);
2337     blend_state = render_state->cc.blend->virtual;
2338     memset(blend_state, 0, sizeof(*blend_state));
2339     blend_state->blend1.logic_op_enable = 1;
2340     blend_state->blend1.logic_op_func = 0xc;
2341     blend_state->blend1.pre_blend_clamp_enable = 1;
2342     dri_bo_unmap(render_state->cc.blend);
2343 }
2344
2345 static void
2346 gen7_render_depth_stencil_state(VADriverContextP ctx)
2347 {
2348     struct i965_driver_data *i965 = i965_driver_data(ctx);
2349     struct i965_render_state *render_state = &i965->render_state;
2350     struct gen6_depth_stencil_state *depth_stencil_state;
2351
2352     dri_bo_map(render_state->cc.depth_stencil, 1);
2353     assert(render_state->cc.depth_stencil->virtual);
2354     depth_stencil_state = render_state->cc.depth_stencil->virtual;
2355     memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2356     dri_bo_unmap(render_state->cc.depth_stencil);
2357 }
2358
2359 static void
2360 gen7_render_sampler(VADriverContextP ctx)
2361 {
2362     struct i965_driver_data *i965 = i965_driver_data(ctx);
2363     struct i965_render_state *render_state = &i965->render_state;
2364     struct gen7_sampler_state *sampler_state;
2365     int i;
2366
2367     assert(render_state->wm.sampler_count > 0);
2368     assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2369
2370     dri_bo_map(render_state->wm.sampler, 1);
2371     assert(render_state->wm.sampler->virtual);
2372     sampler_state = render_state->wm.sampler->virtual;
2373     for (i = 0; i < render_state->wm.sampler_count; i++) {
2374         memset(sampler_state, 0, sizeof(*sampler_state));
2375         sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2376         sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2377         sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2378         sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2379         sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2380         sampler_state++;
2381     }
2382
2383     dri_bo_unmap(render_state->wm.sampler);
2384 }
2385
2386 static void
2387 gen7_render_setup_states(
2388     VADriverContextP   ctx,
2389     struct object_surface *obj_surface,
2390     const VARectangle *src_rect,
2391     const VARectangle *dst_rect,
2392     unsigned int       flags
2393 )
2394 {
2395     i965_render_dest_surface_state(ctx, 0);
2396     i965_render_src_surfaces_state(ctx, obj_surface, flags);
2397     gen7_render_sampler(ctx);
2398     i965_render_cc_viewport(ctx);
2399     gen7_render_color_calc_state(ctx);
2400     gen7_render_blend_state(ctx);
2401     gen7_render_depth_stencil_state(ctx);
2402     i965_render_upload_constants(ctx, obj_surface);
2403     i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2404 }
2405
2406 static void
2407 gen7_emit_invarient_states(VADriverContextP ctx)
2408 {
2409     struct i965_driver_data *i965 = i965_driver_data(ctx);
2410     struct intel_batchbuffer *batch = i965->batch;
2411
2412     BEGIN_BATCH(batch, 1);
2413     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2414     ADVANCE_BATCH(batch);
2415
2416     BEGIN_BATCH(batch, 4);
2417     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2418     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2419               GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2420     OUT_BATCH(batch, 0);
2421     OUT_BATCH(batch, 0);
2422     ADVANCE_BATCH(batch);
2423
2424     BEGIN_BATCH(batch, 2);
2425     OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2426     OUT_BATCH(batch, 1);
2427     ADVANCE_BATCH(batch);
2428
2429     /* Set system instruction pointer */
2430     BEGIN_BATCH(batch, 2);
2431     OUT_BATCH(batch, CMD_STATE_SIP | 0);
2432     OUT_BATCH(batch, 0);
2433     ADVANCE_BATCH(batch);
2434 }
2435
2436 static void
2437 gen7_emit_state_base_address(VADriverContextP ctx)
2438 {
2439     struct i965_driver_data *i965 = i965_driver_data(ctx);
2440     struct intel_batchbuffer *batch = i965->batch;
2441     struct i965_render_state *render_state = &i965->render_state;
2442
2443     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2444     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2445     OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2446     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2447     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2448     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2449     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2450     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2451     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2452     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2453 }
2454
2455 static void
2456 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2457 {
2458     struct i965_driver_data *i965 = i965_driver_data(ctx);
2459     struct intel_batchbuffer *batch = i965->batch;
2460     struct i965_render_state *render_state = &i965->render_state;
2461
2462     BEGIN_BATCH(batch, 2);
2463     OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2464     OUT_RELOC(batch,
2465               render_state->cc.viewport,
2466               I915_GEM_DOMAIN_INSTRUCTION, 0,
2467               0);
2468     ADVANCE_BATCH(batch);
2469
2470     BEGIN_BATCH(batch, 2);
2471     OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2472     OUT_BATCH(batch, 0);
2473     ADVANCE_BATCH(batch);
2474 }
2475
2476 /*
2477  * URB layout on GEN7
2478  * ----------------------------------------
2479  * | PS Push Constants (8KB) | VS entries |
2480  * ----------------------------------------
2481  */
2482 static void
2483 gen7_emit_urb(VADriverContextP ctx)
2484 {
2485     struct i965_driver_data *i965 = i965_driver_data(ctx);
2486     struct intel_batchbuffer *batch = i965->batch;
2487     unsigned int num_urb_entries = 32;
2488
2489     if (IS_HASWELL(i965->intel.device_id))
2490         num_urb_entries = 64;
2491
2492     BEGIN_BATCH(batch, 2);
2493     OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2494     OUT_BATCH(batch, 8); /* in 1KBs */
2495     ADVANCE_BATCH(batch);
2496
2497     BEGIN_BATCH(batch, 2);
2498     OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2499     OUT_BATCH(batch,
2500               (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
2501               (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2502               (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2503    ADVANCE_BATCH(batch);
2504
2505    BEGIN_BATCH(batch, 2);
2506    OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2507    OUT_BATCH(batch,
2508              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2509              (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2510    ADVANCE_BATCH(batch);
2511
2512    BEGIN_BATCH(batch, 2);
2513    OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2514    OUT_BATCH(batch,
2515              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2516              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2517    ADVANCE_BATCH(batch);
2518
2519    BEGIN_BATCH(batch, 2);
2520    OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2521    OUT_BATCH(batch,
2522              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2523              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2524    ADVANCE_BATCH(batch);
2525 }
2526
2527 static void
2528 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2529 {
2530     struct i965_driver_data *i965 = i965_driver_data(ctx);
2531     struct intel_batchbuffer *batch = i965->batch;
2532     struct i965_render_state *render_state = &i965->render_state;
2533
2534     BEGIN_BATCH(batch, 2);
2535     OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2536     OUT_RELOC(batch,
2537               render_state->cc.state,
2538               I915_GEM_DOMAIN_INSTRUCTION, 0,
2539               1);
2540     ADVANCE_BATCH(batch);
2541
2542     BEGIN_BATCH(batch, 2);
2543     OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2544     OUT_RELOC(batch,
2545               render_state->cc.blend,
2546               I915_GEM_DOMAIN_INSTRUCTION, 0,
2547               1);
2548     ADVANCE_BATCH(batch);
2549
2550     BEGIN_BATCH(batch, 2);
2551     OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2552     OUT_RELOC(batch,
2553               render_state->cc.depth_stencil,
2554               I915_GEM_DOMAIN_INSTRUCTION, 0,
2555               1);
2556     ADVANCE_BATCH(batch);
2557 }
2558
2559 static void
2560 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2561 {
2562     struct i965_driver_data *i965 = i965_driver_data(ctx);
2563     struct intel_batchbuffer *batch = i965->batch;
2564     struct i965_render_state *render_state = &i965->render_state;
2565
2566     BEGIN_BATCH(batch, 2);
2567     OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2568     OUT_RELOC(batch,
2569               render_state->wm.sampler,
2570               I915_GEM_DOMAIN_INSTRUCTION, 0,
2571               0);
2572     ADVANCE_BATCH(batch);
2573 }
2574
2575 static void
2576 gen7_emit_binding_table(VADriverContextP ctx)
2577 {
2578     struct i965_driver_data *i965 = i965_driver_data(ctx);
2579     struct intel_batchbuffer *batch = i965->batch;
2580
2581     BEGIN_BATCH(batch, 2);
2582     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2583     OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2584     ADVANCE_BATCH(batch);
2585 }
2586
2587 static void
2588 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2589 {
2590     struct i965_driver_data *i965 = i965_driver_data(ctx);
2591     struct intel_batchbuffer *batch = i965->batch;
2592
2593     BEGIN_BATCH(batch, 7);
2594     OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2595     OUT_BATCH(batch,
2596               (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2597               (I965_SURFACE_NULL << 29));
2598     OUT_BATCH(batch, 0);
2599     OUT_BATCH(batch, 0);
2600     OUT_BATCH(batch, 0);
2601     OUT_BATCH(batch, 0);
2602     OUT_BATCH(batch, 0);
2603     ADVANCE_BATCH(batch);
2604
2605     BEGIN_BATCH(batch, 3);
2606     OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2607     OUT_BATCH(batch, 0);
2608     OUT_BATCH(batch, 0);
2609     ADVANCE_BATCH(batch);
2610 }
2611
2612 static void
2613 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2614 {
2615     i965_render_drawing_rectangle(ctx);
2616 }
2617
2618 static void
2619 gen7_emit_vs_state(VADriverContextP ctx)
2620 {
2621     struct i965_driver_data *i965 = i965_driver_data(ctx);
2622     struct intel_batchbuffer *batch = i965->batch;
2623
2624     /* disable VS constant buffer */
2625     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2626     OUT_BATCH(batch, 0);
2627     OUT_BATCH(batch, 0);
2628     OUT_BATCH(batch, 0);
2629     OUT_BATCH(batch, 0);
2630     OUT_BATCH(batch, 0);
2631     OUT_BATCH(batch, 0);
2632
2633     OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2634     OUT_BATCH(batch, 0); /* without VS kernel */
2635     OUT_BATCH(batch, 0);
2636     OUT_BATCH(batch, 0);
2637     OUT_BATCH(batch, 0);
2638     OUT_BATCH(batch, 0); /* pass-through */
2639 }
2640
2641 static void
2642 gen7_emit_bypass_state(VADriverContextP ctx)
2643 {
2644     struct i965_driver_data *i965 = i965_driver_data(ctx);
2645     struct intel_batchbuffer *batch = i965->batch;
2646
2647     /* bypass GS */
2648     BEGIN_BATCH(batch, 7);
2649     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2650     OUT_BATCH(batch, 0);
2651     OUT_BATCH(batch, 0);
2652     OUT_BATCH(batch, 0);
2653     OUT_BATCH(batch, 0);
2654     OUT_BATCH(batch, 0);
2655     OUT_BATCH(batch, 0);
2656     ADVANCE_BATCH(batch);
2657
2658     BEGIN_BATCH(batch, 7);
2659     OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2660     OUT_BATCH(batch, 0); /* without GS kernel */
2661     OUT_BATCH(batch, 0);
2662     OUT_BATCH(batch, 0);
2663     OUT_BATCH(batch, 0);
2664     OUT_BATCH(batch, 0);
2665     OUT_BATCH(batch, 0); /* pass-through */
2666     ADVANCE_BATCH(batch);
2667
2668     BEGIN_BATCH(batch, 2);
2669     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2670     OUT_BATCH(batch, 0);
2671     ADVANCE_BATCH(batch);
2672
2673     /* disable HS */
2674     BEGIN_BATCH(batch, 7);
2675     OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2676     OUT_BATCH(batch, 0);
2677     OUT_BATCH(batch, 0);
2678     OUT_BATCH(batch, 0);
2679     OUT_BATCH(batch, 0);
2680     OUT_BATCH(batch, 0);
2681     OUT_BATCH(batch, 0);
2682     ADVANCE_BATCH(batch);
2683
2684     BEGIN_BATCH(batch, 7);
2685     OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2686     OUT_BATCH(batch, 0);
2687     OUT_BATCH(batch, 0);
2688     OUT_BATCH(batch, 0);
2689     OUT_BATCH(batch, 0);
2690     OUT_BATCH(batch, 0);
2691     OUT_BATCH(batch, 0);
2692     ADVANCE_BATCH(batch);
2693
2694     BEGIN_BATCH(batch, 2);
2695     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2696     OUT_BATCH(batch, 0);
2697     ADVANCE_BATCH(batch);
2698
2699     /* Disable TE */
2700     BEGIN_BATCH(batch, 4);
2701     OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2702     OUT_BATCH(batch, 0);
2703     OUT_BATCH(batch, 0);
2704     OUT_BATCH(batch, 0);
2705     ADVANCE_BATCH(batch);
2706
2707     /* Disable DS */
2708     BEGIN_BATCH(batch, 7);
2709     OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2710     OUT_BATCH(batch, 0);
2711     OUT_BATCH(batch, 0);
2712     OUT_BATCH(batch, 0);
2713     OUT_BATCH(batch, 0);
2714     OUT_BATCH(batch, 0);
2715     OUT_BATCH(batch, 0);
2716     ADVANCE_BATCH(batch);
2717
2718     BEGIN_BATCH(batch, 6);
2719     OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2720     OUT_BATCH(batch, 0);
2721     OUT_BATCH(batch, 0);
2722     OUT_BATCH(batch, 0);
2723     OUT_BATCH(batch, 0);
2724     OUT_BATCH(batch, 0);
2725     ADVANCE_BATCH(batch);
2726
2727     BEGIN_BATCH(batch, 2);
2728     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2729     OUT_BATCH(batch, 0);
2730     ADVANCE_BATCH(batch);
2731
2732     /* Disable STREAMOUT */
2733     BEGIN_BATCH(batch, 3);
2734     OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2735     OUT_BATCH(batch, 0);
2736     OUT_BATCH(batch, 0);
2737     ADVANCE_BATCH(batch);
2738 }
2739
2740 static void
2741 gen7_emit_clip_state(VADriverContextP ctx)
2742 {
2743     struct i965_driver_data *i965 = i965_driver_data(ctx);
2744     struct intel_batchbuffer *batch = i965->batch;
2745
2746     OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2747     OUT_BATCH(batch, 0);
2748     OUT_BATCH(batch, 0); /* pass-through */
2749     OUT_BATCH(batch, 0);
2750 }
2751
2752 static void
2753 gen7_emit_sf_state(VADriverContextP ctx)
2754 {
2755     struct i965_driver_data *i965 = i965_driver_data(ctx);
2756     struct intel_batchbuffer *batch = i965->batch;
2757
2758     BEGIN_BATCH(batch, 14);
2759     OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2760     OUT_BATCH(batch,
2761               (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2762               (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2763               (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2764     OUT_BATCH(batch, 0);
2765     OUT_BATCH(batch, 0);
2766     OUT_BATCH(batch, 0); /* DW4 */
2767     OUT_BATCH(batch, 0);
2768     OUT_BATCH(batch, 0);
2769     OUT_BATCH(batch, 0);
2770     OUT_BATCH(batch, 0);
2771     OUT_BATCH(batch, 0); /* DW9 */
2772     OUT_BATCH(batch, 0);
2773     OUT_BATCH(batch, 0);
2774     OUT_BATCH(batch, 0);
2775     OUT_BATCH(batch, 0);
2776     ADVANCE_BATCH(batch);
2777
2778     BEGIN_BATCH(batch, 7);
2779     OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2780     OUT_BATCH(batch, 0);
2781     OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2782     OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2783     OUT_BATCH(batch, 0);
2784     OUT_BATCH(batch, 0);
2785     OUT_BATCH(batch, 0);
2786     ADVANCE_BATCH(batch);
2787 }
2788
2789 static void
2790 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2791 {
2792     struct i965_driver_data *i965 = i965_driver_data(ctx);
2793     struct intel_batchbuffer *batch = i965->batch;
2794     struct i965_render_state *render_state = &i965->render_state;
2795     unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
2796     unsigned int num_samples = 0;
2797
2798     if (IS_HASWELL(i965->intel.device_id)) {
2799         max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
2800         num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
2801     }
2802
2803     BEGIN_BATCH(batch, 3);
2804     OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2805     OUT_BATCH(batch,
2806               GEN7_WM_DISPATCH_ENABLE |
2807               GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2808     OUT_BATCH(batch, 0);
2809     ADVANCE_BATCH(batch);
2810
2811     BEGIN_BATCH(batch, 7);
2812     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2813     OUT_BATCH(batch, 1);
2814     OUT_BATCH(batch, 0);
2815     OUT_RELOC(batch,
2816               render_state->curbe.bo,
2817               I915_GEM_DOMAIN_INSTRUCTION, 0,
2818               0);
2819     OUT_BATCH(batch, 0);
2820     OUT_BATCH(batch, 0);
2821     OUT_BATCH(batch, 0);
2822     ADVANCE_BATCH(batch);
2823
2824     BEGIN_BATCH(batch, 8);
2825     OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2826     OUT_RELOC(batch,
2827               render_state->render_kernels[kernel].bo,
2828               I915_GEM_DOMAIN_INSTRUCTION, 0,
2829               0);
2830     OUT_BATCH(batch,
2831               (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2832               (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2833     OUT_BATCH(batch, 0); /* scratch space base offset */
2834     OUT_BATCH(batch,
2835               ((render_state->max_wm_threads - 1) << max_threads_shift) | num_samples |
2836               GEN7_PS_PUSH_CONSTANT_ENABLE |
2837               GEN7_PS_ATTRIBUTE_ENABLE |
2838               GEN7_PS_16_DISPATCH_ENABLE);
2839     OUT_BATCH(batch,
2840               (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2841     OUT_BATCH(batch, 0); /* kernel 1 pointer */
2842     OUT_BATCH(batch, 0); /* kernel 2 pointer */
2843     ADVANCE_BATCH(batch);
2844 }
2845
2846 static void
2847 gen7_emit_vertex_element_state(VADriverContextP ctx)
2848 {
2849     struct i965_driver_data *i965 = i965_driver_data(ctx);
2850     struct intel_batchbuffer *batch = i965->batch;
2851
2852     /* Set up our vertex elements, sourced from the single vertex buffer. */
2853     OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2854     /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2855     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2856               GEN6_VE0_VALID |
2857               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2858               (0 << VE0_OFFSET_SHIFT));
2859     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2860               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2861               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2862               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2863     /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2864     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2865               GEN6_VE0_VALID |
2866               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2867               (8 << VE0_OFFSET_SHIFT));
2868     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2869               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2870               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2871               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2872 }
2873
2874 static void
2875 gen7_emit_vertices(VADriverContextP ctx)
2876 {
2877     struct i965_driver_data *i965 = i965_driver_data(ctx);
2878     struct intel_batchbuffer *batch = i965->batch;
2879     struct i965_render_state *render_state = &i965->render_state;
2880
2881     BEGIN_BATCH(batch, 5);
2882     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2883     OUT_BATCH(batch,
2884               (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2885               GEN6_VB0_VERTEXDATA |
2886               GEN7_VB0_ADDRESS_MODIFYENABLE |
2887               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2888     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2889     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2890     OUT_BATCH(batch, 0);
2891     ADVANCE_BATCH(batch);
2892
2893     BEGIN_BATCH(batch, 7);
2894     OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2895     OUT_BATCH(batch,
2896               _3DPRIM_RECTLIST |
2897               GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2898     OUT_BATCH(batch, 3); /* vertex count per instance */
2899     OUT_BATCH(batch, 0); /* start vertex offset */
2900     OUT_BATCH(batch, 1); /* single instance */
2901     OUT_BATCH(batch, 0); /* start instance location */
2902     OUT_BATCH(batch, 0);
2903     ADVANCE_BATCH(batch);
2904 }
2905
2906 static void
2907 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2908 {
2909     struct i965_driver_data *i965 = i965_driver_data(ctx);
2910     struct intel_batchbuffer *batch = i965->batch;
2911
2912     intel_batchbuffer_start_atomic(batch, 0x1000);
2913     intel_batchbuffer_emit_mi_flush(batch);
2914     gen7_emit_invarient_states(ctx);
2915     gen7_emit_state_base_address(ctx);
2916     gen7_emit_viewport_state_pointers(ctx);
2917     gen7_emit_urb(ctx);
2918     gen7_emit_cc_state_pointers(ctx);
2919     gen7_emit_sampler_state_pointers(ctx);
2920     gen7_emit_bypass_state(ctx);
2921     gen7_emit_vs_state(ctx);
2922     gen7_emit_clip_state(ctx);
2923     gen7_emit_sf_state(ctx);
2924     gen7_emit_wm_state(ctx, kernel);
2925     gen7_emit_binding_table(ctx);
2926     gen7_emit_depth_buffer_state(ctx);
2927     gen7_emit_drawing_rectangle(ctx);
2928     gen7_emit_vertex_element_state(ctx);
2929     gen7_emit_vertices(ctx);
2930     intel_batchbuffer_end_atomic(batch);
2931 }
2932
2933 static void
2934 gen7_render_put_surface(
2935     VADriverContextP   ctx,
2936     struct object_surface *obj_surface,
2937     const VARectangle *src_rect,
2938     const VARectangle *dst_rect,
2939     unsigned int       flags
2940 )
2941 {
2942     struct i965_driver_data *i965 = i965_driver_data(ctx);
2943     struct intel_batchbuffer *batch = i965->batch;
2944
2945     gen7_render_initialize(ctx);
2946     gen7_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2947     i965_clear_dest_region(ctx);
2948     gen7_render_emit_states(ctx, PS_KERNEL);
2949     intel_batchbuffer_flush(batch);
2950 }
2951
2952 static void
2953 gen7_subpicture_render_blend_state(VADriverContextP ctx)
2954 {
2955     struct i965_driver_data *i965 = i965_driver_data(ctx);
2956     struct i965_render_state *render_state = &i965->render_state;
2957     struct gen6_blend_state *blend_state;
2958
2959     dri_bo_unmap(render_state->cc.state);
2960     dri_bo_map(render_state->cc.blend, 1);
2961     assert(render_state->cc.blend->virtual);
2962     blend_state = render_state->cc.blend->virtual;
2963     memset(blend_state, 0, sizeof(*blend_state));
2964     blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2965     blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2966     blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2967     blend_state->blend0.blend_enable = 1;
2968     blend_state->blend1.post_blend_clamp_enable = 1;
2969     blend_state->blend1.pre_blend_clamp_enable = 1;
2970     blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2971     dri_bo_unmap(render_state->cc.blend);
2972 }
2973
2974 static void
2975 gen7_subpicture_render_setup_states(
2976     VADriverContextP   ctx,
2977     struct object_surface *obj_surface,
2978     const VARectangle *src_rect,
2979     const VARectangle *dst_rect
2980 )
2981 {
2982     i965_render_dest_surface_state(ctx, 0);
2983     i965_subpic_render_src_surfaces_state(ctx, obj_surface);
2984     i965_render_sampler(ctx);
2985     i965_render_cc_viewport(ctx);
2986     gen7_render_color_calc_state(ctx);
2987     gen7_subpicture_render_blend_state(ctx);
2988     gen7_render_depth_stencil_state(ctx);
2989     i965_subpic_render_upload_constants(ctx, obj_surface);
2990     i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
2991 }
2992
2993 static void
2994 gen7_render_put_subpicture(
2995     VADriverContextP   ctx,
2996     struct object_surface *obj_surface,
2997     const VARectangle *src_rect,
2998     const VARectangle *dst_rect
2999 )
3000 {
3001     struct i965_driver_data *i965 = i965_driver_data(ctx);
3002     struct intel_batchbuffer *batch = i965->batch;
3003     unsigned int index = obj_surface->subpic_render_idx;
3004     struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
3005
3006     assert(obj_subpic);
3007     gen7_render_initialize(ctx);
3008     gen7_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
3009     gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
3010     i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
3011     intel_batchbuffer_flush(batch);
3012 }
3013
3014
3015 /*
3016  * global functions
3017  */
3018 VAStatus
3019 i965_DestroySurfaces(VADriverContextP ctx,
3020                      VASurfaceID *surface_list,
3021                      int num_surfaces);
3022 void
3023 intel_render_put_surface(
3024     VADriverContextP   ctx,
3025     struct object_surface *obj_surface,
3026     const VARectangle *src_rect,
3027     const VARectangle *dst_rect,
3028     unsigned int       flags
3029 )
3030 {
3031     struct i965_driver_data *i965 = i965_driver_data(ctx);
3032     int has_done_scaling = 0;
3033     VASurfaceID out_surface_id = i965_post_processing(ctx,
3034                                                       obj_surface,
3035                                                       src_rect,
3036                                                       dst_rect,
3037                                                       flags,
3038                                                       &has_done_scaling);
3039
3040     assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
3041
3042     if (out_surface_id != VA_INVALID_ID) {
3043         struct object_surface *new_obj_surface = SURFACE(out_surface_id);
3044
3045         if (new_obj_surface && new_obj_surface->bo)
3046             obj_surface = new_obj_surface;
3047
3048         if (has_done_scaling)
3049             src_rect = dst_rect;
3050     }
3051
3052     if (IS_GEN7(i965->intel.device_id))
3053         gen7_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3054     else if (IS_GEN6(i965->intel.device_id))
3055         gen6_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3056     else
3057         i965_render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3058
3059     if (out_surface_id != VA_INVALID_ID)
3060         i965_DestroySurfaces(ctx, &out_surface_id, 1);
3061 }
3062
3063 void
3064 intel_render_put_subpicture(
3065     VADriverContextP   ctx,
3066     struct object_surface *obj_surface,
3067     const VARectangle *src_rect,
3068     const VARectangle *dst_rect
3069 )
3070 {
3071     struct i965_driver_data *i965 = i965_driver_data(ctx);
3072
3073     if (IS_GEN7(i965->intel.device_id))
3074         gen7_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3075     else if (IS_GEN6(i965->intel.device_id))
3076         gen6_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3077     else
3078         i965_render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3079 }
3080
3081 bool
3082 i965_render_init(VADriverContextP ctx)
3083 {
3084     struct i965_driver_data *i965 = i965_driver_data(ctx);
3085     struct i965_render_state *render_state = &i965->render_state;
3086     int i;
3087
3088     /* kernel */
3089     assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
3090                                  sizeof(render_kernels_gen5[0])));
3091     assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
3092                                  sizeof(render_kernels_gen6[0])));
3093
3094     if (IS_GEN7(i965->intel.device_id))
3095         memcpy(render_state->render_kernels,
3096                (IS_HASWELL(i965->intel.device_id) ? render_kernels_gen7_haswell : render_kernels_gen7),
3097                sizeof(render_state->render_kernels));
3098     else if (IS_GEN6(i965->intel.device_id))
3099         memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
3100     else if (IS_IRONLAKE(i965->intel.device_id))
3101         memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
3102     else
3103         memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
3104
3105     for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3106         struct i965_kernel *kernel = &render_state->render_kernels[i];
3107
3108         if (!kernel->size)
3109             continue;
3110
3111         kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
3112                                   kernel->name,
3113                                   kernel->size, 0x1000);
3114         assert(kernel->bo);
3115         dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
3116     }
3117
3118     /* constant buffer */
3119     render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
3120                       "constant buffer",
3121                       4096, 64);
3122     assert(render_state->curbe.bo);
3123
3124     if (IS_IVB_GT1(i965->intel.device_id) ||
3125         IS_HSW_GT1(i965->intel.device_id)) {
3126         render_state->max_wm_threads = 48;
3127     } else if (IS_IVB_GT2(i965->intel.device_id) ||
3128                IS_HSW_GT2(i965->intel.device_id)) {
3129         render_state->max_wm_threads = 172;
3130     } else if (IS_HSW_GT3(i965->intel.device_id)) {
3131         render_state->max_wm_threads = 172;
3132     } else if (IS_SNB_GT1(i965->intel.device_id)) {
3133         render_state->max_wm_threads = 40;
3134     } else if (IS_SNB_GT2(i965->intel.device_id)) {
3135         render_state->max_wm_threads = 80;
3136     } else if (IS_IRONLAKE(i965->intel.device_id)) {
3137         render_state->max_wm_threads = 72; /* 12 * 6 */
3138     } else if (IS_G4X(i965->intel.device_id)) {
3139         render_state->max_wm_threads = 50; /* 12 * 5 */
3140     } else {
3141         /* should never get here !!! */
3142         assert(0);
3143     }
3144
3145     return true;
3146 }
3147
3148 void
3149 i965_render_terminate(VADriverContextP ctx)
3150 {
3151     int i;
3152     struct i965_driver_data *i965 = i965_driver_data(ctx);
3153     struct i965_render_state *render_state = &i965->render_state;
3154
3155     dri_bo_unreference(render_state->curbe.bo);
3156     render_state->curbe.bo = NULL;
3157
3158     for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3159         struct i965_kernel *kernel = &render_state->render_kernels[i];
3160
3161         dri_bo_unreference(kernel->bo);
3162         kernel->bo = NULL;
3163     }
3164
3165     dri_bo_unreference(render_state->vb.vertex_buffer);
3166     render_state->vb.vertex_buffer = NULL;
3167     dri_bo_unreference(render_state->vs.state);
3168     render_state->vs.state = NULL;
3169     dri_bo_unreference(render_state->sf.state);
3170     render_state->sf.state = NULL;
3171     dri_bo_unreference(render_state->wm.sampler);
3172     render_state->wm.sampler = NULL;
3173     dri_bo_unreference(render_state->wm.state);
3174     render_state->wm.state = NULL;
3175     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3176     dri_bo_unreference(render_state->cc.viewport);
3177     render_state->cc.viewport = NULL;
3178     dri_bo_unreference(render_state->cc.state);
3179     render_state->cc.state = NULL;
3180     dri_bo_unreference(render_state->cc.blend);
3181     render_state->cc.blend = NULL;
3182     dri_bo_unreference(render_state->cc.depth_stencil);
3183     render_state->cc.depth_stencil = NULL;
3184
3185     if (render_state->draw_region) {
3186         dri_bo_unreference(render_state->draw_region->bo);
3187         free(render_state->draw_region);
3188         render_state->draw_region = NULL;
3189     }
3190 }
3191