2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
31 * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
40 #include <va/va_drmcommon.h>
42 #include "intel_batchbuffer.h"
43 #include "intel_driver.h"
44 #include "i965_defines.h"
45 #include "i965_drv_video.h"
46 #include "i965_structs.h"
48 #include "i965_render.h"
50 #define SF_KERNEL_NUM_GRF 16
51 #define SF_MAX_THREADS 1
53 static const uint32_t sf_kernel_static[][4] =
55 #include "shaders/render/exa_sf.g4b"
58 #define PS_KERNEL_NUM_GRF 48
59 #define PS_MAX_THREADS 32
61 #define I965_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
63 static const uint32_t ps_kernel_static[][4] =
65 #include "shaders/render/exa_wm_xy.g4b"
66 #include "shaders/render/exa_wm_src_affine.g4b"
67 #include "shaders/render/exa_wm_src_sample_planar.g4b"
68 #include "shaders/render/exa_wm_yuv_color_balance.g4b"
69 #include "shaders/render/exa_wm_yuv_rgb.g4b"
70 #include "shaders/render/exa_wm_write.g4b"
72 static const uint32_t ps_subpic_kernel_static[][4] =
74 #include "shaders/render/exa_wm_xy.g4b"
75 #include "shaders/render/exa_wm_src_affine.g4b"
76 #include "shaders/render/exa_wm_src_sample_argb.g4b"
77 #include "shaders/render/exa_wm_write.g4b"
81 static const uint32_t sf_kernel_static_gen5[][4] =
83 #include "shaders/render/exa_sf.g4b.gen5"
86 static const uint32_t ps_kernel_static_gen5[][4] =
88 #include "shaders/render/exa_wm_xy.g4b.gen5"
89 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
90 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
91 #include "shaders/render/exa_wm_yuv_color_balance.g4b.gen5"
92 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
93 #include "shaders/render/exa_wm_write.g4b.gen5"
95 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
97 #include "shaders/render/exa_wm_xy.g4b.gen5"
98 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
99 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
100 #include "shaders/render/exa_wm_write.g4b.gen5"
103 /* programs for Sandybridge */
104 static const uint32_t sf_kernel_static_gen6[][4] =
108 static const uint32_t ps_kernel_static_gen6[][4] = {
109 #include "shaders/render/exa_wm_src_affine.g6b"
110 #include "shaders/render/exa_wm_src_sample_planar.g6b"
111 #include "shaders/render/exa_wm_yuv_color_balance.g6b"
112 #include "shaders/render/exa_wm_yuv_rgb.g6b"
113 #include "shaders/render/exa_wm_write.g6b"
116 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
117 #include "shaders/render/exa_wm_src_affine.g6b"
118 #include "shaders/render/exa_wm_src_sample_argb.g6b"
119 #include "shaders/render/exa_wm_write.g6b"
122 /* programs for Ivybridge */
123 static const uint32_t sf_kernel_static_gen7[][4] =
127 static const uint32_t ps_kernel_static_gen7[][4] = {
128 #include "shaders/render/exa_wm_src_affine.g7b"
129 #include "shaders/render/exa_wm_src_sample_planar.g7b"
130 #include "shaders/render/exa_wm_yuv_color_balance.g7b"
131 #include "shaders/render/exa_wm_yuv_rgb.g7b"
132 #include "shaders/render/exa_wm_write.g7b"
135 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
136 #include "shaders/render/exa_wm_src_affine.g7b"
137 #include "shaders/render/exa_wm_src_sample_argb.g7b"
138 #include "shaders/render/exa_wm_write.g7b"
141 /* Programs for Haswell */
142 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
143 #include "shaders/render/exa_wm_src_affine.g7b"
144 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
145 #include "shaders/render/exa_wm_yuv_color_balance.g7b.haswell"
146 #include "shaders/render/exa_wm_yuv_rgb.g7b"
147 #include "shaders/render/exa_wm_write.g7b"
151 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
153 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
154 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
156 static uint32_t float_to_uint (float f)
174 static struct i965_kernel render_kernels_gen4[] = {
179 sizeof(sf_kernel_static),
186 sizeof(ps_kernel_static),
193 ps_subpic_kernel_static,
194 sizeof(ps_subpic_kernel_static),
199 static struct i965_kernel render_kernels_gen5[] = {
203 sf_kernel_static_gen5,
204 sizeof(sf_kernel_static_gen5),
210 ps_kernel_static_gen5,
211 sizeof(ps_kernel_static_gen5),
218 ps_subpic_kernel_static_gen5,
219 sizeof(ps_subpic_kernel_static_gen5),
224 static struct i965_kernel render_kernels_gen6[] = {
228 sf_kernel_static_gen6,
229 sizeof(sf_kernel_static_gen6),
235 ps_kernel_static_gen6,
236 sizeof(ps_kernel_static_gen6),
243 ps_subpic_kernel_static_gen6,
244 sizeof(ps_subpic_kernel_static_gen6),
249 static struct i965_kernel render_kernels_gen7[] = {
253 sf_kernel_static_gen7,
254 sizeof(sf_kernel_static_gen7),
260 ps_kernel_static_gen7,
261 sizeof(ps_kernel_static_gen7),
268 ps_subpic_kernel_static_gen7,
269 sizeof(ps_subpic_kernel_static_gen7),
274 static struct i965_kernel render_kernels_gen7_haswell[] = {
278 sf_kernel_static_gen7,
279 sizeof(sf_kernel_static_gen7),
285 ps_kernel_static_gen7_haswell,
286 sizeof(ps_kernel_static_gen7_haswell),
293 ps_subpic_kernel_static_gen7,
294 sizeof(ps_subpic_kernel_static_gen7),
299 #define URB_VS_ENTRIES 8
300 #define URB_VS_ENTRY_SIZE 1
302 #define URB_GS_ENTRIES 0
303 #define URB_GS_ENTRY_SIZE 0
305 #define URB_CLIP_ENTRIES 0
306 #define URB_CLIP_ENTRY_SIZE 0
308 #define URB_SF_ENTRIES 1
309 #define URB_SF_ENTRY_SIZE 2
311 #define URB_CS_ENTRIES 4
312 #define URB_CS_ENTRY_SIZE 4
314 static float yuv_to_rgb_bt601[3][4] = {
315 {1.164, 0, 1.596, -0.06275,},
316 {1.164, -0.392, -0.813, -0.50196,},
317 {1.164, 2.017, 0, -0.50196,},
320 static float yuv_to_rgb_bt709[3][4] = {
321 {1.164, 0, 1.793, -0.06275,},
322 {1.164, -0.213, -0.533, -0.50196,},
323 {1.164, 2.112, 0, -0.50196,},
326 static float yuv_to_rgb_smpte_240[3][4] = {
327 {1.164, 0, 1.794, -0.06275,},
328 {1.164, -0.258, -0.5425, -0.50196,},
329 {1.164, 2.078, 0, -0.50196,},
333 i965_render_vs_unit(VADriverContextP ctx)
335 struct i965_driver_data *i965 = i965_driver_data(ctx);
336 struct i965_render_state *render_state = &i965->render_state;
337 struct i965_vs_unit_state *vs_state;
339 dri_bo_map(render_state->vs.state, 1);
340 assert(render_state->vs.state->virtual);
341 vs_state = render_state->vs.state->virtual;
342 memset(vs_state, 0, sizeof(*vs_state));
344 if (IS_IRONLAKE(i965->intel.device_info))
345 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
347 vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
349 vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
350 vs_state->vs6.vs_enable = 0;
351 vs_state->vs6.vert_cache_disable = 1;
353 dri_bo_unmap(render_state->vs.state);
357 i965_render_sf_unit(VADriverContextP ctx)
359 struct i965_driver_data *i965 = i965_driver_data(ctx);
360 struct i965_render_state *render_state = &i965->render_state;
361 struct i965_sf_unit_state *sf_state;
363 dri_bo_map(render_state->sf.state, 1);
364 assert(render_state->sf.state->virtual);
365 sf_state = render_state->sf.state->virtual;
366 memset(sf_state, 0, sizeof(*sf_state));
368 sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
369 sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
371 sf_state->sf1.single_program_flow = 1; /* XXX */
372 sf_state->sf1.binding_table_entry_count = 0;
373 sf_state->sf1.thread_priority = 0;
374 sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
375 sf_state->sf1.illegal_op_exception_enable = 1;
376 sf_state->sf1.mask_stack_exception_enable = 1;
377 sf_state->sf1.sw_exception_enable = 1;
379 /* scratch space is not used in our kernel */
380 sf_state->thread2.per_thread_scratch_space = 0;
381 sf_state->thread2.scratch_space_base_pointer = 0;
383 sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
384 sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
385 sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
386 sf_state->thread3.urb_entry_read_offset = 0;
387 sf_state->thread3.dispatch_grf_start_reg = 3;
389 sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
390 sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
391 sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
392 sf_state->thread4.stats_enable = 1;
394 sf_state->sf5.viewport_transform = 0; /* skip viewport */
396 sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
397 sf_state->sf6.scissor = 0;
399 sf_state->sf7.trifan_pv = 2;
401 sf_state->sf6.dest_org_vbias = 0x8;
402 sf_state->sf6.dest_org_hbias = 0x8;
404 dri_bo_emit_reloc(render_state->sf.state,
405 I915_GEM_DOMAIN_INSTRUCTION, 0,
406 sf_state->thread0.grf_reg_count << 1,
407 offsetof(struct i965_sf_unit_state, thread0),
408 render_state->render_kernels[SF_KERNEL].bo);
410 dri_bo_unmap(render_state->sf.state);
414 i965_render_sampler(VADriverContextP ctx)
416 struct i965_driver_data *i965 = i965_driver_data(ctx);
417 struct i965_render_state *render_state = &i965->render_state;
418 struct i965_sampler_state *sampler_state;
421 assert(render_state->wm.sampler_count > 0);
422 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
424 dri_bo_map(render_state->wm.sampler, 1);
425 assert(render_state->wm.sampler->virtual);
426 sampler_state = render_state->wm.sampler->virtual;
427 for (i = 0; i < render_state->wm.sampler_count; i++) {
428 memset(sampler_state, 0, sizeof(*sampler_state));
429 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
430 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
431 sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
432 sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
433 sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
437 dri_bo_unmap(render_state->wm.sampler);
440 i965_subpic_render_wm_unit(VADriverContextP ctx)
442 struct i965_driver_data *i965 = i965_driver_data(ctx);
443 struct i965_render_state *render_state = &i965->render_state;
444 struct i965_wm_unit_state *wm_state;
446 assert(render_state->wm.sampler);
448 dri_bo_map(render_state->wm.state, 1);
449 assert(render_state->wm.state->virtual);
450 wm_state = render_state->wm.state->virtual;
451 memset(wm_state, 0, sizeof(*wm_state));
453 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
454 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
456 wm_state->thread1.single_program_flow = 1; /* XXX */
458 if (IS_IRONLAKE(i965->intel.device_info))
459 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
461 wm_state->thread1.binding_table_entry_count = 7;
463 wm_state->thread2.scratch_space_base_pointer = 0;
464 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
466 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
467 wm_state->thread3.const_urb_entry_read_length = 4;
468 wm_state->thread3.const_urb_entry_read_offset = 0;
469 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
470 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
472 wm_state->wm4.stats_enable = 0;
473 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
475 if (IS_IRONLAKE(i965->intel.device_info)) {
476 wm_state->wm4.sampler_count = 0; /* hardware requirement */
478 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
481 wm_state->wm5.max_threads = i965->intel.device_info->max_wm_threads - 1;
482 wm_state->wm5.thread_dispatch_enable = 1;
483 wm_state->wm5.enable_16_pix = 1;
484 wm_state->wm5.enable_8_pix = 0;
485 wm_state->wm5.early_depth_test = 1;
487 dri_bo_emit_reloc(render_state->wm.state,
488 I915_GEM_DOMAIN_INSTRUCTION, 0,
489 wm_state->thread0.grf_reg_count << 1,
490 offsetof(struct i965_wm_unit_state, thread0),
491 render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
493 dri_bo_emit_reloc(render_state->wm.state,
494 I915_GEM_DOMAIN_INSTRUCTION, 0,
495 wm_state->wm4.sampler_count << 2,
496 offsetof(struct i965_wm_unit_state, wm4),
497 render_state->wm.sampler);
499 dri_bo_unmap(render_state->wm.state);
504 i965_render_wm_unit(VADriverContextP ctx)
506 struct i965_driver_data *i965 = i965_driver_data(ctx);
507 struct i965_render_state *render_state = &i965->render_state;
508 struct i965_wm_unit_state *wm_state;
510 assert(render_state->wm.sampler);
512 dri_bo_map(render_state->wm.state, 1);
513 assert(render_state->wm.state->virtual);
514 wm_state = render_state->wm.state->virtual;
515 memset(wm_state, 0, sizeof(*wm_state));
517 wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
518 wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
520 wm_state->thread1.single_program_flow = 1; /* XXX */
522 if (IS_IRONLAKE(i965->intel.device_info))
523 wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
525 wm_state->thread1.binding_table_entry_count = 7;
527 wm_state->thread2.scratch_space_base_pointer = 0;
528 wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
530 wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
531 wm_state->thread3.const_urb_entry_read_length = 4;
532 wm_state->thread3.const_urb_entry_read_offset = 0;
533 wm_state->thread3.urb_entry_read_length = 1; /* XXX */
534 wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
536 wm_state->wm4.stats_enable = 0;
537 wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
539 if (IS_IRONLAKE(i965->intel.device_info)) {
540 wm_state->wm4.sampler_count = 0; /* hardware requirement */
542 wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
545 wm_state->wm5.max_threads = i965->intel.device_info->max_wm_threads - 1;
546 wm_state->wm5.thread_dispatch_enable = 1;
547 wm_state->wm5.enable_16_pix = 1;
548 wm_state->wm5.enable_8_pix = 0;
549 wm_state->wm5.early_depth_test = 1;
551 dri_bo_emit_reloc(render_state->wm.state,
552 I915_GEM_DOMAIN_INSTRUCTION, 0,
553 wm_state->thread0.grf_reg_count << 1,
554 offsetof(struct i965_wm_unit_state, thread0),
555 render_state->render_kernels[PS_KERNEL].bo);
557 dri_bo_emit_reloc(render_state->wm.state,
558 I915_GEM_DOMAIN_INSTRUCTION, 0,
559 wm_state->wm4.sampler_count << 2,
560 offsetof(struct i965_wm_unit_state, wm4),
561 render_state->wm.sampler);
563 dri_bo_unmap(render_state->wm.state);
567 i965_render_cc_viewport(VADriverContextP ctx)
569 struct i965_driver_data *i965 = i965_driver_data(ctx);
570 struct i965_render_state *render_state = &i965->render_state;
571 struct i965_cc_viewport *cc_viewport;
573 dri_bo_map(render_state->cc.viewport, 1);
574 assert(render_state->cc.viewport->virtual);
575 cc_viewport = render_state->cc.viewport->virtual;
576 memset(cc_viewport, 0, sizeof(*cc_viewport));
578 cc_viewport->min_depth = -1.e35;
579 cc_viewport->max_depth = 1.e35;
581 dri_bo_unmap(render_state->cc.viewport);
585 i965_subpic_render_cc_unit(VADriverContextP ctx)
587 struct i965_driver_data *i965 = i965_driver_data(ctx);
588 struct i965_render_state *render_state = &i965->render_state;
589 struct i965_cc_unit_state *cc_state;
591 assert(render_state->cc.viewport);
593 dri_bo_map(render_state->cc.state, 1);
594 assert(render_state->cc.state->virtual);
595 cc_state = render_state->cc.state->virtual;
596 memset(cc_state, 0, sizeof(*cc_state));
598 cc_state->cc0.stencil_enable = 0; /* disable stencil */
599 cc_state->cc2.depth_test = 0; /* disable depth test */
600 cc_state->cc2.logicop_enable = 0; /* disable logic op */
601 cc_state->cc3.ia_blend_enable = 0 ; /* blend alpha just like colors */
602 cc_state->cc3.blend_enable = 1; /* enable color blend */
603 cc_state->cc3.alpha_test = 0; /* disable alpha test */
604 cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8; /*store alpha value with UNORM8 */
605 cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS; /*pass if less than the reference */
606 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
608 cc_state->cc5.dither_enable = 0; /* disable dither */
609 cc_state->cc5.logicop_func = 0xc; /* WHITE */
610 cc_state->cc5.statistics_enable = 1;
611 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
612 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
613 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
615 cc_state->cc6.clamp_post_alpha_blend = 0;
616 cc_state->cc6.clamp_pre_alpha_blend =0;
618 /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
619 cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
620 cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
621 cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
623 /*alpha test reference*/
624 cc_state->cc7.alpha_ref.f =0.0 ;
627 dri_bo_emit_reloc(render_state->cc.state,
628 I915_GEM_DOMAIN_INSTRUCTION, 0,
630 offsetof(struct i965_cc_unit_state, cc4),
631 render_state->cc.viewport);
633 dri_bo_unmap(render_state->cc.state);
638 i965_render_cc_unit(VADriverContextP ctx)
640 struct i965_driver_data *i965 = i965_driver_data(ctx);
641 struct i965_render_state *render_state = &i965->render_state;
642 struct i965_cc_unit_state *cc_state;
644 assert(render_state->cc.viewport);
646 dri_bo_map(render_state->cc.state, 1);
647 assert(render_state->cc.state->virtual);
648 cc_state = render_state->cc.state->virtual;
649 memset(cc_state, 0, sizeof(*cc_state));
651 cc_state->cc0.stencil_enable = 0; /* disable stencil */
652 cc_state->cc2.depth_test = 0; /* disable depth test */
653 cc_state->cc2.logicop_enable = 1; /* enable logic op */
654 cc_state->cc3.ia_blend_enable = 0; /* blend alpha just like colors */
655 cc_state->cc3.blend_enable = 0; /* disable color blend */
656 cc_state->cc3.alpha_test = 0; /* disable alpha test */
657 cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
659 cc_state->cc5.dither_enable = 0; /* disable dither */
660 cc_state->cc5.logicop_func = 0xc; /* WHITE */
661 cc_state->cc5.statistics_enable = 1;
662 cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
663 cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
664 cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
666 dri_bo_emit_reloc(render_state->cc.state,
667 I915_GEM_DOMAIN_INSTRUCTION, 0,
669 offsetof(struct i965_cc_unit_state, cc4),
670 render_state->cc.viewport);
672 dri_bo_unmap(render_state->cc.state);
676 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
679 case I915_TILING_NONE:
680 ss->ss3.tiled_surface = 0;
681 ss->ss3.tile_walk = 0;
684 ss->ss3.tiled_surface = 1;
685 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
688 ss->ss3.tiled_surface = 1;
689 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
695 i965_render_set_surface_state(
696 struct i965_surface_state *ss,
698 unsigned long offset,
707 unsigned int swizzle;
709 memset(ss, 0, sizeof(*ss));
711 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
712 case I965_PP_FLAG_BOTTOM_FIELD:
713 ss->ss0.vert_line_stride_ofs = 1;
715 case I965_PP_FLAG_TOP_FIELD:
716 ss->ss0.vert_line_stride = 1;
721 ss->ss0.surface_type = I965_SURFACE_2D;
722 ss->ss0.surface_format = format;
723 ss->ss0.color_blend = 1;
725 ss->ss1.base_addr = bo->offset + offset;
727 ss->ss2.width = width - 1;
728 ss->ss2.height = height - 1;
730 ss->ss3.pitch = pitch - 1;
732 dri_bo_get_tiling(bo, &tiling, &swizzle);
733 i965_render_set_surface_tiling(ss, tiling);
737 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
740 case I915_TILING_NONE:
741 ss->ss0.tiled_surface = 0;
742 ss->ss0.tile_walk = 0;
745 ss->ss0.tiled_surface = 1;
746 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
749 ss->ss0.tiled_surface = 1;
750 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
755 /* Set "Shader Channel Select" */
757 gen7_render_set_surface_scs(struct gen7_surface_state *ss)
759 ss->ss7.shader_chanel_select_r = HSW_SCS_RED;
760 ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
761 ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
762 ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
766 gen7_render_set_surface_state(
767 struct gen7_surface_state *ss,
769 unsigned long offset,
778 unsigned int swizzle;
780 memset(ss, 0, sizeof(*ss));
782 switch (flags & (I965_PP_FLAG_TOP_FIELD|I965_PP_FLAG_BOTTOM_FIELD)) {
783 case I965_PP_FLAG_BOTTOM_FIELD:
784 ss->ss0.vert_line_stride_ofs = 1;
786 case I965_PP_FLAG_TOP_FIELD:
787 ss->ss0.vert_line_stride = 1;
792 ss->ss0.surface_type = I965_SURFACE_2D;
793 ss->ss0.surface_format = format;
795 ss->ss1.base_addr = bo->offset + offset;
797 ss->ss2.width = width - 1;
798 ss->ss2.height = height - 1;
800 ss->ss3.pitch = pitch - 1;
802 dri_bo_get_tiling(bo, &tiling, &swizzle);
803 gen7_render_set_surface_tiling(ss, tiling);
808 i965_render_src_surface_state(
809 VADriverContextP ctx,
812 unsigned long offset,
820 struct i965_driver_data *i965 = i965_driver_data(ctx);
821 struct i965_render_state *render_state = &i965->render_state;
823 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
825 assert(index < MAX_RENDER_SURFACES);
827 dri_bo_map(ss_bo, 1);
828 assert(ss_bo->virtual);
829 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
831 if (IS_GEN7(i965->intel.device_info)) {
832 gen7_render_set_surface_state(ss,
835 pitch, format, flags);
836 if (IS_HASWELL(i965->intel.device_info))
837 gen7_render_set_surface_scs(ss);
838 dri_bo_emit_reloc(ss_bo,
839 I915_GEM_DOMAIN_SAMPLER, 0,
841 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
844 i965_render_set_surface_state(ss,
847 pitch, format, flags);
848 dri_bo_emit_reloc(ss_bo,
849 I915_GEM_DOMAIN_SAMPLER, 0,
851 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
855 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
857 render_state->wm.sampler_count++;
861 i965_render_src_surfaces_state(
862 VADriverContextP ctx,
863 struct object_surface *obj_surface,
871 region_pitch = obj_surface->width;
872 rw = obj_surface->orig_width;
873 rh = obj_surface->orig_height;
874 region = obj_surface->bo;
876 i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags); /* Y */
877 i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, region_pitch, I965_SURFACEFORMAT_R8_UNORM, flags);
879 if (obj_surface->fourcc == VA_FOURCC_Y800) /* single plane for grayscale */
882 if (obj_surface->fourcc == VA_FOURCC_NV12) {
883 i965_render_src_surface_state(ctx, 3, region,
884 region_pitch * obj_surface->y_cb_offset,
885 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
886 I965_SURFACEFORMAT_R8G8_UNORM, flags); /* UV */
887 i965_render_src_surface_state(ctx, 4, region,
888 region_pitch * obj_surface->y_cb_offset,
889 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
890 I965_SURFACEFORMAT_R8G8_UNORM, flags);
892 i965_render_src_surface_state(ctx, 3, region,
893 region_pitch * obj_surface->y_cb_offset,
894 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
895 I965_SURFACEFORMAT_R8_UNORM, flags); /* U */
896 i965_render_src_surface_state(ctx, 4, region,
897 region_pitch * obj_surface->y_cb_offset,
898 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
899 I965_SURFACEFORMAT_R8_UNORM, flags);
900 i965_render_src_surface_state(ctx, 5, region,
901 region_pitch * obj_surface->y_cr_offset,
902 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
903 I965_SURFACEFORMAT_R8_UNORM, flags); /* V */
904 i965_render_src_surface_state(ctx, 6, region,
905 region_pitch * obj_surface->y_cr_offset,
906 obj_surface->cb_cr_width, obj_surface->cb_cr_height, obj_surface->cb_cr_pitch,
907 I965_SURFACEFORMAT_R8_UNORM, flags);
912 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
913 struct object_surface *obj_surface)
915 dri_bo *subpic_region;
916 unsigned int index = obj_surface->subpic_render_idx;
917 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
918 struct object_image *obj_image = obj_subpic->obj_image;
921 assert(obj_surface->bo);
922 subpic_region = obj_image->bo;
923 /*subpicture surface*/
924 i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
925 i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format, 0);
929 i965_render_dest_surface_state(VADriverContextP ctx, int index)
931 struct i965_driver_data *i965 = i965_driver_data(ctx);
932 struct i965_render_state *render_state = &i965->render_state;
933 struct intel_region *dest_region = render_state->draw_region;
935 dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
937 assert(index < MAX_RENDER_SURFACES);
939 if (dest_region->cpp == 2) {
940 format = I965_SURFACEFORMAT_B5G6R5_UNORM;
942 format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
945 dri_bo_map(ss_bo, 1);
946 assert(ss_bo->virtual);
947 ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
949 if (IS_GEN7(i965->intel.device_info)) {
950 gen7_render_set_surface_state(ss,
952 dest_region->width, dest_region->height,
953 dest_region->pitch, format, 0);
954 if (IS_HASWELL(i965->intel.device_info))
955 gen7_render_set_surface_scs(ss);
956 dri_bo_emit_reloc(ss_bo,
957 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
959 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
962 i965_render_set_surface_state(ss,
964 dest_region->width, dest_region->height,
965 dest_region->pitch, format, 0);
966 dri_bo_emit_reloc(ss_bo,
967 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
969 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
973 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
978 i965_fill_vertex_buffer(
979 VADriverContextP ctx,
980 float tex_coords[4], /* [(u1,v1);(u2,v2)] */
981 float vid_coords[4] /* [(x1,y1);(x2,y2)] */
984 struct i965_driver_data * const i965 = i965_driver_data(ctx);
987 enum { X1, Y1, X2, Y2 };
989 static const unsigned int g_rotation_indices[][6] = {
990 [VA_ROTATION_NONE] = { X2, Y2, X1, Y2, X1, Y1 },
991 [VA_ROTATION_90] = { X2, Y1, X2, Y2, X1, Y2 },
992 [VA_ROTATION_180] = { X1, Y1, X2, Y1, X2, Y2 },
993 [VA_ROTATION_270] = { X1, Y2, X1, Y1, X2, Y1 },
996 const unsigned int * const rotation_indices =
997 g_rotation_indices[i965->rotation_attrib->value];
999 vb[0] = tex_coords[rotation_indices[0]]; /* bottom-right corner */
1000 vb[1] = tex_coords[rotation_indices[1]];
1001 vb[2] = vid_coords[X2];
1002 vb[3] = vid_coords[Y2];
1004 vb[4] = tex_coords[rotation_indices[2]]; /* bottom-left corner */
1005 vb[5] = tex_coords[rotation_indices[3]];
1006 vb[6] = vid_coords[X1];
1007 vb[7] = vid_coords[Y2];
1009 vb[8] = tex_coords[rotation_indices[4]]; /* top-left corner */
1010 vb[9] = tex_coords[rotation_indices[5]];
1011 vb[10] = vid_coords[X1];
1012 vb[11] = vid_coords[Y1];
1014 dri_bo_subdata(i965->render_state.vb.vertex_buffer, 0, sizeof(vb), vb);
1018 i965_subpic_render_upload_vertex(VADriverContextP ctx,
1019 struct object_surface *obj_surface,
1020 const VARectangle *output_rect)
1022 unsigned int index = obj_surface->subpic_render_idx;
1023 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1024 float tex_coords[4], vid_coords[4];
1025 VARectangle dst_rect;
1027 if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
1028 dst_rect = obj_subpic->dst_rect;
1030 const float sx = (float)output_rect->width / obj_surface->orig_width;
1031 const float sy = (float)output_rect->height / obj_surface->orig_height;
1032 dst_rect.x = output_rect->x + sx * obj_subpic->dst_rect.x;
1033 dst_rect.y = output_rect->y + sy * obj_subpic->dst_rect.y;
1034 dst_rect.width = sx * obj_subpic->dst_rect.width;
1035 dst_rect.height = sy * obj_subpic->dst_rect.height;
1038 tex_coords[0] = (float)obj_subpic->src_rect.x / obj_subpic->width;
1039 tex_coords[1] = (float)obj_subpic->src_rect.y / obj_subpic->height;
1040 tex_coords[2] = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
1041 tex_coords[3] = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
1043 vid_coords[0] = dst_rect.x;
1044 vid_coords[1] = dst_rect.y;
1045 vid_coords[2] = (float)(dst_rect.x + dst_rect.width);
1046 vid_coords[3] = (float)(dst_rect.y + dst_rect.height);
1048 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1052 i965_render_upload_vertex(
1053 VADriverContextP ctx,
1054 struct object_surface *obj_surface,
1055 const VARectangle *src_rect,
1056 const VARectangle *dst_rect
1059 struct i965_driver_data *i965 = i965_driver_data(ctx);
1060 struct i965_render_state *render_state = &i965->render_state;
1061 struct intel_region *dest_region = render_state->draw_region;
1062 float tex_coords[4], vid_coords[4];
1065 width = obj_surface->orig_width;
1066 height = obj_surface->orig_height;
1068 tex_coords[0] = (float)src_rect->x / width;
1069 tex_coords[1] = (float)src_rect->y / height;
1070 tex_coords[2] = (float)(src_rect->x + src_rect->width) / width;
1071 tex_coords[3] = (float)(src_rect->y + src_rect->height) / height;
1073 vid_coords[0] = dest_region->x + dst_rect->x;
1074 vid_coords[1] = dest_region->y + dst_rect->y;
1075 vid_coords[2] = vid_coords[0] + dst_rect->width;
1076 vid_coords[3] = vid_coords[1] + dst_rect->height;
1078 i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
1081 #define PI 3.1415926
1084 i965_render_upload_constants(VADriverContextP ctx,
1085 struct object_surface *obj_surface,
1088 struct i965_driver_data *i965 = i965_driver_data(ctx);
1089 struct i965_render_state *render_state = &i965->render_state;
1090 unsigned short *constant_buffer;
1091 float *color_balance_base;
1092 float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST;
1093 float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
1094 float hue = (float)i965->hue_attrib->value / 180 * PI;
1095 float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
1097 unsigned int color_flag;
1099 dri_bo_map(render_state->curbe.bo, 1);
1100 assert(render_state->curbe.bo->virtual);
1101 constant_buffer = render_state->curbe.bo->virtual;
1103 if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
1104 assert(obj_surface->fourcc == VA_FOURCC_Y800);
1106 constant_buffer[0] = 2;
1108 if (obj_surface->fourcc == VA_FOURCC_NV12)
1109 constant_buffer[0] = 1;
1111 constant_buffer[0] = 0;
1114 if (i965->contrast_attrib->value == DEFAULT_CONTRAST &&
1115 i965->brightness_attrib->value == DEFAULT_BRIGHTNESS &&
1116 i965->hue_attrib->value == DEFAULT_HUE &&
1117 i965->saturation_attrib->value == DEFAULT_SATURATION)
1118 constant_buffer[1] = 1; /* skip color balance transformation */
1120 constant_buffer[1] = 0;
1122 color_balance_base = (float *)constant_buffer + 4;
1123 *color_balance_base++ = contrast;
1124 *color_balance_base++ = brightness;
1125 *color_balance_base++ = cos(hue) * contrast * saturation;
1126 *color_balance_base++ = sin(hue) * contrast * saturation;
1128 color_flag = flags & VA_SRC_COLOR_MASK;
1129 yuv_to_rgb = (float *)constant_buffer + 8;
1130 if (color_flag == VA_SRC_BT709)
1131 memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
1132 else if (color_flag == VA_SRC_SMPTE_240)
1133 memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240));
1135 memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
1137 dri_bo_unmap(render_state->curbe.bo);
1141 i965_subpic_render_upload_constants(VADriverContextP ctx,
1142 struct object_surface *obj_surface)
1144 struct i965_driver_data *i965 = i965_driver_data(ctx);
1145 struct i965_render_state *render_state = &i965->render_state;
1146 float *constant_buffer;
1147 float global_alpha = 1.0;
1148 unsigned int index = obj_surface->subpic_render_idx;
1149 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1151 if (obj_subpic->flags & VA_SUBPICTURE_GLOBAL_ALPHA) {
1152 global_alpha = obj_subpic->global_alpha;
1155 dri_bo_map(render_state->curbe.bo, 1);
1157 assert(render_state->curbe.bo->virtual);
1158 constant_buffer = render_state->curbe.bo->virtual;
1159 *constant_buffer = global_alpha;
1161 dri_bo_unmap(render_state->curbe.bo);
1165 i965_surface_render_state_setup(
1166 VADriverContextP ctx,
1167 struct object_surface *obj_surface,
1168 const VARectangle *src_rect,
1169 const VARectangle *dst_rect,
1173 i965_render_vs_unit(ctx);
1174 i965_render_sf_unit(ctx);
1175 i965_render_dest_surface_state(ctx, 0);
1176 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1177 i965_render_sampler(ctx);
1178 i965_render_wm_unit(ctx);
1179 i965_render_cc_viewport(ctx);
1180 i965_render_cc_unit(ctx);
1181 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1182 i965_render_upload_constants(ctx, obj_surface, flags);
1186 i965_subpic_render_state_setup(
1187 VADriverContextP ctx,
1188 struct object_surface *obj_surface,
1189 const VARectangle *src_rect,
1190 const VARectangle *dst_rect
1193 i965_render_vs_unit(ctx);
1194 i965_render_sf_unit(ctx);
1195 i965_render_dest_surface_state(ctx, 0);
1196 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
1197 i965_render_sampler(ctx);
1198 i965_subpic_render_wm_unit(ctx);
1199 i965_render_cc_viewport(ctx);
1200 i965_subpic_render_cc_unit(ctx);
1201 i965_subpic_render_upload_constants(ctx, obj_surface);
1202 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
1207 i965_render_pipeline_select(VADriverContextP ctx)
1209 struct i965_driver_data *i965 = i965_driver_data(ctx);
1210 struct intel_batchbuffer *batch = i965->batch;
1212 BEGIN_BATCH(batch, 1);
1213 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1214 ADVANCE_BATCH(batch);
1218 i965_render_state_sip(VADriverContextP ctx)
1220 struct i965_driver_data *i965 = i965_driver_data(ctx);
1221 struct intel_batchbuffer *batch = i965->batch;
1223 BEGIN_BATCH(batch, 2);
1224 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1225 OUT_BATCH(batch, 0);
1226 ADVANCE_BATCH(batch);
1230 i965_render_state_base_address(VADriverContextP ctx)
1232 struct i965_driver_data *i965 = i965_driver_data(ctx);
1233 struct intel_batchbuffer *batch = i965->batch;
1234 struct i965_render_state *render_state = &i965->render_state;
1236 if (IS_IRONLAKE(i965->intel.device_info)) {
1237 BEGIN_BATCH(batch, 8);
1238 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1239 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1240 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1241 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1242 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1243 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1244 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1245 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1246 ADVANCE_BATCH(batch);
1248 BEGIN_BATCH(batch, 6);
1249 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1250 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1251 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1252 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1253 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1254 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1255 ADVANCE_BATCH(batch);
1260 i965_render_binding_table_pointers(VADriverContextP ctx)
1262 struct i965_driver_data *i965 = i965_driver_data(ctx);
1263 struct intel_batchbuffer *batch = i965->batch;
1265 BEGIN_BATCH(batch, 6);
1266 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1267 OUT_BATCH(batch, 0); /* vs */
1268 OUT_BATCH(batch, 0); /* gs */
1269 OUT_BATCH(batch, 0); /* clip */
1270 OUT_BATCH(batch, 0); /* sf */
1271 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1272 ADVANCE_BATCH(batch);
1276 i965_render_constant_color(VADriverContextP ctx)
1278 struct i965_driver_data *i965 = i965_driver_data(ctx);
1279 struct intel_batchbuffer *batch = i965->batch;
1281 BEGIN_BATCH(batch, 5);
1282 OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1283 OUT_BATCH(batch, float_to_uint(1.0));
1284 OUT_BATCH(batch, float_to_uint(0.0));
1285 OUT_BATCH(batch, float_to_uint(1.0));
1286 OUT_BATCH(batch, float_to_uint(1.0));
1287 ADVANCE_BATCH(batch);
1291 i965_render_pipelined_pointers(VADriverContextP ctx)
1293 struct i965_driver_data *i965 = i965_driver_data(ctx);
1294 struct intel_batchbuffer *batch = i965->batch;
1295 struct i965_render_state *render_state = &i965->render_state;
1297 BEGIN_BATCH(batch, 7);
1298 OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1299 OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1300 OUT_BATCH(batch, 0); /* disable GS */
1301 OUT_BATCH(batch, 0); /* disable CLIP */
1302 OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1303 OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1304 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1305 ADVANCE_BATCH(batch);
1309 i965_render_urb_layout(VADriverContextP ctx)
1311 struct i965_driver_data *i965 = i965_driver_data(ctx);
1312 struct intel_batchbuffer *batch = i965->batch;
1313 int urb_vs_start, urb_vs_size;
1314 int urb_gs_start, urb_gs_size;
1315 int urb_clip_start, urb_clip_size;
1316 int urb_sf_start, urb_sf_size;
1317 int urb_cs_start, urb_cs_size;
1320 urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1321 urb_gs_start = urb_vs_start + urb_vs_size;
1322 urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1323 urb_clip_start = urb_gs_start + urb_gs_size;
1324 urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1325 urb_sf_start = urb_clip_start + urb_clip_size;
1326 urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1327 urb_cs_start = urb_sf_start + urb_sf_size;
1328 urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1330 BEGIN_BATCH(batch, 3);
1340 ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1341 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1342 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1344 ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1345 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1346 ADVANCE_BATCH(batch);
1350 i965_render_cs_urb_layout(VADriverContextP ctx)
1352 struct i965_driver_data *i965 = i965_driver_data(ctx);
1353 struct intel_batchbuffer *batch = i965->batch;
1355 BEGIN_BATCH(batch, 2);
1356 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1358 ((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
1359 (URB_CS_ENTRIES << 0)); /* Number of URB Entries */
1360 ADVANCE_BATCH(batch);
1364 i965_render_constant_buffer(VADriverContextP ctx)
1366 struct i965_driver_data *i965 = i965_driver_data(ctx);
1367 struct intel_batchbuffer *batch = i965->batch;
1368 struct i965_render_state *render_state = &i965->render_state;
1370 BEGIN_BATCH(batch, 2);
1371 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1372 OUT_RELOC(batch, render_state->curbe.bo,
1373 I915_GEM_DOMAIN_INSTRUCTION, 0,
1374 URB_CS_ENTRY_SIZE - 1);
1375 ADVANCE_BATCH(batch);
1379 i965_render_drawing_rectangle(VADriverContextP ctx)
1381 struct i965_driver_data *i965 = i965_driver_data(ctx);
1382 struct intel_batchbuffer *batch = i965->batch;
1383 struct i965_render_state *render_state = &i965->render_state;
1384 struct intel_region *dest_region = render_state->draw_region;
1386 BEGIN_BATCH(batch, 4);
1387 OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1388 OUT_BATCH(batch, 0x00000000);
1389 OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1390 OUT_BATCH(batch, 0x00000000);
1391 ADVANCE_BATCH(batch);
1395 i965_render_vertex_elements(VADriverContextP ctx)
1397 struct i965_driver_data *i965 = i965_driver_data(ctx);
1398 struct intel_batchbuffer *batch = i965->batch;
1400 if (IS_IRONLAKE(i965->intel.device_info)) {
1401 BEGIN_BATCH(batch, 5);
1402 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1403 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1404 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1406 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1407 (0 << VE0_OFFSET_SHIFT));
1408 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1409 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1410 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1411 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1412 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1413 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1415 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1416 (8 << VE0_OFFSET_SHIFT));
1417 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1418 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1419 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1420 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1421 ADVANCE_BATCH(batch);
1423 BEGIN_BATCH(batch, 5);
1424 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1425 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1426 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1428 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1429 (0 << VE0_OFFSET_SHIFT));
1430 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1431 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1432 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1433 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1434 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1435 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1436 OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1438 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1439 (8 << VE0_OFFSET_SHIFT));
1440 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1441 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1442 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1443 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1444 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1445 ADVANCE_BATCH(batch);
1450 i965_render_upload_image_palette(
1451 VADriverContextP ctx,
1452 struct object_image *obj_image,
1456 struct i965_driver_data *i965 = i965_driver_data(ctx);
1457 struct intel_batchbuffer *batch = i965->batch;
1465 if (obj_image->image.num_palette_entries == 0)
1468 BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1469 OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1471 //int32_t out[16]; //0-23:color 23-31:alpha
1472 for (i = 0; i < obj_image->image.num_palette_entries; i++)
1473 OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1474 ADVANCE_BATCH(batch);
1478 i965_render_startup(VADriverContextP ctx)
1480 struct i965_driver_data *i965 = i965_driver_data(ctx);
1481 struct intel_batchbuffer *batch = i965->batch;
1482 struct i965_render_state *render_state = &i965->render_state;
1484 BEGIN_BATCH(batch, 11);
1485 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1487 (0 << VB0_BUFFER_INDEX_SHIFT) |
1489 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1490 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1492 if (IS_IRONLAKE(i965->intel.device_info))
1493 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1495 OUT_BATCH(batch, 3);
1497 OUT_BATCH(batch, 0);
1501 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1502 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1505 OUT_BATCH(batch, 3); /* vertex count per instance */
1506 OUT_BATCH(batch, 0); /* start vertex offset */
1507 OUT_BATCH(batch, 1); /* single instance */
1508 OUT_BATCH(batch, 0); /* start instance location */
1509 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1510 ADVANCE_BATCH(batch);
1514 i965_clear_dest_region(VADriverContextP ctx)
1516 struct i965_driver_data *i965 = i965_driver_data(ctx);
1517 struct intel_batchbuffer *batch = i965->batch;
1518 struct i965_render_state *render_state = &i965->render_state;
1519 struct intel_region *dest_region = render_state->draw_region;
1520 unsigned int blt_cmd, br13;
1523 blt_cmd = XY_COLOR_BLT_CMD;
1525 pitch = dest_region->pitch;
1527 if (dest_region->cpp == 4) {
1529 blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1531 assert(dest_region->cpp == 2);
1535 if (dest_region->tiling != I915_TILING_NONE) {
1536 blt_cmd |= XY_COLOR_BLT_DST_TILED;
1542 if (IS_GEN6(i965->intel.device_info) ||
1543 IS_GEN7(i965->intel.device_info) ||
1544 IS_GEN8(i965->intel.device_info)) {
1545 intel_batchbuffer_start_atomic_blt(batch, 24);
1546 BEGIN_BLT_BATCH(batch, 6);
1548 intel_batchbuffer_start_atomic(batch, 24);
1549 BEGIN_BATCH(batch, 6);
1552 OUT_BATCH(batch, blt_cmd);
1553 OUT_BATCH(batch, br13);
1554 OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1555 OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1556 (dest_region->x + dest_region->width));
1557 OUT_RELOC(batch, dest_region->bo,
1558 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1560 OUT_BATCH(batch, 0x0);
1561 ADVANCE_BATCH(batch);
1562 intel_batchbuffer_end_atomic(batch);
1566 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1568 struct i965_driver_data *i965 = i965_driver_data(ctx);
1569 struct intel_batchbuffer *batch = i965->batch;
1571 i965_clear_dest_region(ctx);
1572 intel_batchbuffer_start_atomic(batch, 0x1000);
1573 intel_batchbuffer_emit_mi_flush(batch);
1574 i965_render_pipeline_select(ctx);
1575 i965_render_state_sip(ctx);
1576 i965_render_state_base_address(ctx);
1577 i965_render_binding_table_pointers(ctx);
1578 i965_render_constant_color(ctx);
1579 i965_render_pipelined_pointers(ctx);
1580 i965_render_urb_layout(ctx);
1581 i965_render_cs_urb_layout(ctx);
1582 i965_render_constant_buffer(ctx);
1583 i965_render_drawing_rectangle(ctx);
1584 i965_render_vertex_elements(ctx);
1585 i965_render_startup(ctx);
1586 intel_batchbuffer_end_atomic(batch);
1590 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1592 struct i965_driver_data *i965 = i965_driver_data(ctx);
1593 struct intel_batchbuffer *batch = i965->batch;
1595 intel_batchbuffer_start_atomic(batch, 0x1000);
1596 intel_batchbuffer_emit_mi_flush(batch);
1597 i965_render_pipeline_select(ctx);
1598 i965_render_state_sip(ctx);
1599 i965_render_state_base_address(ctx);
1600 i965_render_binding_table_pointers(ctx);
1601 i965_render_constant_color(ctx);
1602 i965_render_pipelined_pointers(ctx);
1603 i965_render_urb_layout(ctx);
1604 i965_render_cs_urb_layout(ctx);
1605 i965_render_constant_buffer(ctx);
1606 i965_render_drawing_rectangle(ctx);
1607 i965_render_vertex_elements(ctx);
1608 i965_render_startup(ctx);
1609 intel_batchbuffer_end_atomic(batch);
1614 i965_render_initialize(VADriverContextP ctx)
1616 struct i965_driver_data *i965 = i965_driver_data(ctx);
1617 struct i965_render_state *render_state = &i965->render_state;
1621 dri_bo_unreference(render_state->vb.vertex_buffer);
1622 bo = dri_bo_alloc(i965->intel.bufmgr,
1627 render_state->vb.vertex_buffer = bo;
1630 dri_bo_unreference(render_state->vs.state);
1631 bo = dri_bo_alloc(i965->intel.bufmgr,
1633 sizeof(struct i965_vs_unit_state),
1636 render_state->vs.state = bo;
1641 dri_bo_unreference(render_state->sf.state);
1642 bo = dri_bo_alloc(i965->intel.bufmgr,
1644 sizeof(struct i965_sf_unit_state),
1647 render_state->sf.state = bo;
1650 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1651 bo = dri_bo_alloc(i965->intel.bufmgr,
1652 "surface state & binding table",
1653 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1656 render_state->wm.surface_state_binding_table_bo = bo;
1658 dri_bo_unreference(render_state->wm.sampler);
1659 bo = dri_bo_alloc(i965->intel.bufmgr,
1661 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1664 render_state->wm.sampler = bo;
1665 render_state->wm.sampler_count = 0;
1667 dri_bo_unreference(render_state->wm.state);
1668 bo = dri_bo_alloc(i965->intel.bufmgr,
1670 sizeof(struct i965_wm_unit_state),
1673 render_state->wm.state = bo;
1675 /* COLOR CALCULATOR */
1676 dri_bo_unreference(render_state->cc.state);
1677 bo = dri_bo_alloc(i965->intel.bufmgr,
1679 sizeof(struct i965_cc_unit_state),
1682 render_state->cc.state = bo;
1684 dri_bo_unreference(render_state->cc.viewport);
1685 bo = dri_bo_alloc(i965->intel.bufmgr,
1687 sizeof(struct i965_cc_viewport),
1690 render_state->cc.viewport = bo;
1694 i965_render_put_surface(
1695 VADriverContextP ctx,
1696 struct object_surface *obj_surface,
1697 const VARectangle *src_rect,
1698 const VARectangle *dst_rect,
1702 struct i965_driver_data *i965 = i965_driver_data(ctx);
1703 struct intel_batchbuffer *batch = i965->batch;
1705 i965_render_initialize(ctx);
1706 i965_surface_render_state_setup(ctx, obj_surface, src_rect, dst_rect, flags);
1707 i965_surface_render_pipeline_setup(ctx);
1708 intel_batchbuffer_flush(batch);
1712 i965_render_put_subpicture(
1713 VADriverContextP ctx,
1714 struct object_surface *obj_surface,
1715 const VARectangle *src_rect,
1716 const VARectangle *dst_rect
1719 struct i965_driver_data *i965 = i965_driver_data(ctx);
1720 struct intel_batchbuffer *batch = i965->batch;
1721 unsigned int index = obj_surface->subpic_render_idx;
1722 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
1726 i965_render_initialize(ctx);
1727 i965_subpic_render_state_setup(ctx, obj_surface, src_rect, dst_rect);
1728 i965_subpic_render_pipeline_setup(ctx);
1729 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
1730 intel_batchbuffer_flush(batch);
1737 gen6_render_initialize(VADriverContextP ctx)
1739 struct i965_driver_data *i965 = i965_driver_data(ctx);
1740 struct i965_render_state *render_state = &i965->render_state;
1744 dri_bo_unreference(render_state->vb.vertex_buffer);
1745 bo = dri_bo_alloc(i965->intel.bufmgr,
1750 render_state->vb.vertex_buffer = bo;
1753 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1754 bo = dri_bo_alloc(i965->intel.bufmgr,
1755 "surface state & binding table",
1756 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1759 render_state->wm.surface_state_binding_table_bo = bo;
1761 dri_bo_unreference(render_state->wm.sampler);
1762 bo = dri_bo_alloc(i965->intel.bufmgr,
1764 MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1767 render_state->wm.sampler = bo;
1768 render_state->wm.sampler_count = 0;
1770 /* COLOR CALCULATOR */
1771 dri_bo_unreference(render_state->cc.state);
1772 bo = dri_bo_alloc(i965->intel.bufmgr,
1774 sizeof(struct gen6_color_calc_state),
1777 render_state->cc.state = bo;
1780 dri_bo_unreference(render_state->cc.viewport);
1781 bo = dri_bo_alloc(i965->intel.bufmgr,
1783 sizeof(struct i965_cc_viewport),
1786 render_state->cc.viewport = bo;
1789 dri_bo_unreference(render_state->cc.blend);
1790 bo = dri_bo_alloc(i965->intel.bufmgr,
1792 sizeof(struct gen6_blend_state),
1795 render_state->cc.blend = bo;
1797 /* DEPTH & STENCIL STATE */
1798 dri_bo_unreference(render_state->cc.depth_stencil);
1799 bo = dri_bo_alloc(i965->intel.bufmgr,
1800 "depth & stencil state",
1801 sizeof(struct gen6_depth_stencil_state),
1804 render_state->cc.depth_stencil = bo;
1808 gen6_render_color_calc_state(VADriverContextP ctx)
1810 struct i965_driver_data *i965 = i965_driver_data(ctx);
1811 struct i965_render_state *render_state = &i965->render_state;
1812 struct gen6_color_calc_state *color_calc_state;
1814 dri_bo_map(render_state->cc.state, 1);
1815 assert(render_state->cc.state->virtual);
1816 color_calc_state = render_state->cc.state->virtual;
1817 memset(color_calc_state, 0, sizeof(*color_calc_state));
1818 color_calc_state->constant_r = 1.0;
1819 color_calc_state->constant_g = 0.0;
1820 color_calc_state->constant_b = 1.0;
1821 color_calc_state->constant_a = 1.0;
1822 dri_bo_unmap(render_state->cc.state);
1826 gen6_render_blend_state(VADriverContextP ctx)
1828 struct i965_driver_data *i965 = i965_driver_data(ctx);
1829 struct i965_render_state *render_state = &i965->render_state;
1830 struct gen6_blend_state *blend_state;
1832 dri_bo_map(render_state->cc.blend, 1);
1833 assert(render_state->cc.blend->virtual);
1834 blend_state = render_state->cc.blend->virtual;
1835 memset(blend_state, 0, sizeof(*blend_state));
1836 blend_state->blend1.logic_op_enable = 1;
1837 blend_state->blend1.logic_op_func = 0xc;
1838 dri_bo_unmap(render_state->cc.blend);
1842 gen6_render_depth_stencil_state(VADriverContextP ctx)
1844 struct i965_driver_data *i965 = i965_driver_data(ctx);
1845 struct i965_render_state *render_state = &i965->render_state;
1846 struct gen6_depth_stencil_state *depth_stencil_state;
1848 dri_bo_map(render_state->cc.depth_stencil, 1);
1849 assert(render_state->cc.depth_stencil->virtual);
1850 depth_stencil_state = render_state->cc.depth_stencil->virtual;
1851 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1852 dri_bo_unmap(render_state->cc.depth_stencil);
1856 gen6_render_setup_states(
1857 VADriverContextP ctx,
1858 struct object_surface *obj_surface,
1859 const VARectangle *src_rect,
1860 const VARectangle *dst_rect,
1864 i965_render_dest_surface_state(ctx, 0);
1865 i965_render_src_surfaces_state(ctx, obj_surface, flags);
1866 i965_render_sampler(ctx);
1867 i965_render_cc_viewport(ctx);
1868 gen6_render_color_calc_state(ctx);
1869 gen6_render_blend_state(ctx);
1870 gen6_render_depth_stencil_state(ctx);
1871 i965_render_upload_constants(ctx, obj_surface, flags);
1872 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
1876 gen6_emit_invarient_states(VADriverContextP ctx)
1878 struct i965_driver_data *i965 = i965_driver_data(ctx);
1879 struct intel_batchbuffer *batch = i965->batch;
1881 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1883 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1884 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1885 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1886 OUT_BATCH(batch, 0);
1888 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1889 OUT_BATCH(batch, 1);
1891 /* Set system instruction pointer */
1892 OUT_BATCH(batch, CMD_STATE_SIP | 0);
1893 OUT_BATCH(batch, 0);
1897 gen6_emit_state_base_address(VADriverContextP ctx)
1899 struct i965_driver_data *i965 = i965_driver_data(ctx);
1900 struct intel_batchbuffer *batch = i965->batch;
1901 struct i965_render_state *render_state = &i965->render_state;
1903 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1904 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1905 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1906 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1907 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1908 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1909 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1910 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1911 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1912 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1916 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1918 struct i965_driver_data *i965 = i965_driver_data(ctx);
1919 struct intel_batchbuffer *batch = i965->batch;
1920 struct i965_render_state *render_state = &i965->render_state;
1922 OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1923 GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1925 OUT_BATCH(batch, 0);
1926 OUT_BATCH(batch, 0);
1927 OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1931 gen6_emit_urb(VADriverContextP ctx)
1933 struct i965_driver_data *i965 = i965_driver_data(ctx);
1934 struct intel_batchbuffer *batch = i965->batch;
1936 OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1937 OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1938 (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1939 OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1940 (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1944 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1946 struct i965_driver_data *i965 = i965_driver_data(ctx);
1947 struct intel_batchbuffer *batch = i965->batch;
1948 struct i965_render_state *render_state = &i965->render_state;
1950 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1951 OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1952 OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1953 OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1957 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1959 struct i965_driver_data *i965 = i965_driver_data(ctx);
1960 struct intel_batchbuffer *batch = i965->batch;
1961 struct i965_render_state *render_state = &i965->render_state;
1963 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1964 GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1966 OUT_BATCH(batch, 0); /* VS */
1967 OUT_BATCH(batch, 0); /* GS */
1968 OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1972 gen6_emit_binding_table(VADriverContextP ctx)
1974 struct i965_driver_data *i965 = i965_driver_data(ctx);
1975 struct intel_batchbuffer *batch = i965->batch;
1977 /* Binding table pointers */
1978 OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1979 GEN6_BINDING_TABLE_MODIFY_PS |
1981 OUT_BATCH(batch, 0); /* vs */
1982 OUT_BATCH(batch, 0); /* gs */
1983 /* Only the PS uses the binding table */
1984 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1988 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1990 struct i965_driver_data *i965 = i965_driver_data(ctx);
1991 struct intel_batchbuffer *batch = i965->batch;
1993 OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1994 OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1995 (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1996 OUT_BATCH(batch, 0);
1997 OUT_BATCH(batch, 0);
1998 OUT_BATCH(batch, 0);
1999 OUT_BATCH(batch, 0);
2000 OUT_BATCH(batch, 0);
2002 OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
2003 OUT_BATCH(batch, 0);
2007 gen6_emit_drawing_rectangle(VADriverContextP ctx)
2009 i965_render_drawing_rectangle(ctx);
2013 gen6_emit_vs_state(VADriverContextP ctx)
2015 struct i965_driver_data *i965 = i965_driver_data(ctx);
2016 struct intel_batchbuffer *batch = i965->batch;
2018 /* disable VS constant buffer */
2019 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
2020 OUT_BATCH(batch, 0);
2021 OUT_BATCH(batch, 0);
2022 OUT_BATCH(batch, 0);
2023 OUT_BATCH(batch, 0);
2025 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2026 OUT_BATCH(batch, 0); /* without VS kernel */
2027 OUT_BATCH(batch, 0);
2028 OUT_BATCH(batch, 0);
2029 OUT_BATCH(batch, 0);
2030 OUT_BATCH(batch, 0); /* pass-through */
2034 gen6_emit_gs_state(VADriverContextP ctx)
2036 struct i965_driver_data *i965 = i965_driver_data(ctx);
2037 struct intel_batchbuffer *batch = i965->batch;
2039 /* disable GS constant buffer */
2040 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
2041 OUT_BATCH(batch, 0);
2042 OUT_BATCH(batch, 0);
2043 OUT_BATCH(batch, 0);
2044 OUT_BATCH(batch, 0);
2046 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2047 OUT_BATCH(batch, 0); /* without GS kernel */
2048 OUT_BATCH(batch, 0);
2049 OUT_BATCH(batch, 0);
2050 OUT_BATCH(batch, 0);
2051 OUT_BATCH(batch, 0);
2052 OUT_BATCH(batch, 0); /* pass-through */
2056 gen6_emit_clip_state(VADriverContextP ctx)
2058 struct i965_driver_data *i965 = i965_driver_data(ctx);
2059 struct intel_batchbuffer *batch = i965->batch;
2061 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2062 OUT_BATCH(batch, 0);
2063 OUT_BATCH(batch, 0); /* pass-through */
2064 OUT_BATCH(batch, 0);
2068 gen6_emit_sf_state(VADriverContextP ctx)
2070 struct i965_driver_data *i965 = i965_driver_data(ctx);
2071 struct intel_batchbuffer *batch = i965->batch;
2073 OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
2074 OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
2075 (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
2076 (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
2077 OUT_BATCH(batch, 0);
2078 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2079 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
2080 OUT_BATCH(batch, 0);
2081 OUT_BATCH(batch, 0);
2082 OUT_BATCH(batch, 0);
2083 OUT_BATCH(batch, 0);
2084 OUT_BATCH(batch, 0); /* DW9 */
2085 OUT_BATCH(batch, 0);
2086 OUT_BATCH(batch, 0);
2087 OUT_BATCH(batch, 0);
2088 OUT_BATCH(batch, 0);
2089 OUT_BATCH(batch, 0); /* DW14 */
2090 OUT_BATCH(batch, 0);
2091 OUT_BATCH(batch, 0);
2092 OUT_BATCH(batch, 0);
2093 OUT_BATCH(batch, 0);
2094 OUT_BATCH(batch, 0); /* DW19 */
2098 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
2100 struct i965_driver_data *i965 = i965_driver_data(ctx);
2101 struct intel_batchbuffer *batch = i965->batch;
2102 struct i965_render_state *render_state = &i965->render_state;
2104 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
2105 GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
2108 render_state->curbe.bo,
2109 I915_GEM_DOMAIN_INSTRUCTION, 0,
2110 (URB_CS_ENTRY_SIZE-1));
2111 OUT_BATCH(batch, 0);
2112 OUT_BATCH(batch, 0);
2113 OUT_BATCH(batch, 0);
2115 OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
2116 OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
2117 I915_GEM_DOMAIN_INSTRUCTION, 0,
2119 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
2120 (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2121 OUT_BATCH(batch, 0);
2122 OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
2123 OUT_BATCH(batch, ((i965->intel.device_info->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
2124 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
2125 GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
2126 OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
2127 GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2128 OUT_BATCH(batch, 0);
2129 OUT_BATCH(batch, 0);
2133 gen6_emit_vertex_element_state(VADriverContextP ctx)
2135 struct i965_driver_data *i965 = i965_driver_data(ctx);
2136 struct intel_batchbuffer *batch = i965->batch;
2138 /* Set up our vertex elements, sourced from the single vertex buffer. */
2139 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2140 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2141 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2143 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2144 (0 << VE0_OFFSET_SHIFT));
2145 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2146 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2147 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2148 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2149 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2150 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2152 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2153 (8 << VE0_OFFSET_SHIFT));
2154 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2155 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2156 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2157 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2161 gen6_emit_vertices(VADriverContextP ctx)
2163 struct i965_driver_data *i965 = i965_driver_data(ctx);
2164 struct intel_batchbuffer *batch = i965->batch;
2165 struct i965_render_state *render_state = &i965->render_state;
2167 BEGIN_BATCH(batch, 11);
2168 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2170 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2171 GEN6_VB0_VERTEXDATA |
2172 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2173 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2174 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2175 OUT_BATCH(batch, 0);
2179 _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2180 (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2183 OUT_BATCH(batch, 3); /* vertex count per instance */
2184 OUT_BATCH(batch, 0); /* start vertex offset */
2185 OUT_BATCH(batch, 1); /* single instance */
2186 OUT_BATCH(batch, 0); /* start instance location */
2187 OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2188 ADVANCE_BATCH(batch);
2192 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2194 struct i965_driver_data *i965 = i965_driver_data(ctx);
2195 struct intel_batchbuffer *batch = i965->batch;
2197 intel_batchbuffer_start_atomic(batch, 0x1000);
2198 intel_batchbuffer_emit_mi_flush(batch);
2199 gen6_emit_invarient_states(ctx);
2200 gen6_emit_state_base_address(ctx);
2201 gen6_emit_viewport_state_pointers(ctx);
2203 gen6_emit_cc_state_pointers(ctx);
2204 gen6_emit_sampler_state_pointers(ctx);
2205 gen6_emit_vs_state(ctx);
2206 gen6_emit_gs_state(ctx);
2207 gen6_emit_clip_state(ctx);
2208 gen6_emit_sf_state(ctx);
2209 gen6_emit_wm_state(ctx, kernel);
2210 gen6_emit_binding_table(ctx);
2211 gen6_emit_depth_buffer_state(ctx);
2212 gen6_emit_drawing_rectangle(ctx);
2213 gen6_emit_vertex_element_state(ctx);
2214 gen6_emit_vertices(ctx);
2215 intel_batchbuffer_end_atomic(batch);
2219 gen6_render_put_surface(
2220 VADriverContextP ctx,
2221 struct object_surface *obj_surface,
2222 const VARectangle *src_rect,
2223 const VARectangle *dst_rect,
2227 struct i965_driver_data *i965 = i965_driver_data(ctx);
2228 struct intel_batchbuffer *batch = i965->batch;
2230 gen6_render_initialize(ctx);
2231 gen6_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
2232 i965_clear_dest_region(ctx);
2233 gen6_render_emit_states(ctx, PS_KERNEL);
2234 intel_batchbuffer_flush(batch);
2238 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2240 struct i965_driver_data *i965 = i965_driver_data(ctx);
2241 struct i965_render_state *render_state = &i965->render_state;
2242 struct gen6_blend_state *blend_state;
2244 dri_bo_unmap(render_state->cc.state);
2245 dri_bo_map(render_state->cc.blend, 1);
2246 assert(render_state->cc.blend->virtual);
2247 blend_state = render_state->cc.blend->virtual;
2248 memset(blend_state, 0, sizeof(*blend_state));
2249 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2250 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2251 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2252 blend_state->blend0.blend_enable = 1;
2253 blend_state->blend1.post_blend_clamp_enable = 1;
2254 blend_state->blend1.pre_blend_clamp_enable = 1;
2255 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2256 dri_bo_unmap(render_state->cc.blend);
2260 gen6_subpicture_render_setup_states(
2261 VADriverContextP ctx,
2262 struct object_surface *obj_surface,
2263 const VARectangle *src_rect,
2264 const VARectangle *dst_rect
2267 i965_render_dest_surface_state(ctx, 0);
2268 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
2269 i965_render_sampler(ctx);
2270 i965_render_cc_viewport(ctx);
2271 gen6_render_color_calc_state(ctx);
2272 gen6_subpicture_render_blend_state(ctx);
2273 gen6_render_depth_stencil_state(ctx);
2274 i965_subpic_render_upload_constants(ctx, obj_surface);
2275 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
2279 gen6_render_put_subpicture(
2280 VADriverContextP ctx,
2281 struct object_surface *obj_surface,
2282 const VARectangle *src_rect,
2283 const VARectangle *dst_rect
2286 struct i965_driver_data *i965 = i965_driver_data(ctx);
2287 struct intel_batchbuffer *batch = i965->batch;
2288 unsigned int index = obj_surface->subpic_render_idx;
2289 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
2292 gen6_render_initialize(ctx);
2293 gen6_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
2294 gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2295 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
2296 intel_batchbuffer_flush(batch);
2303 gen7_render_initialize(VADriverContextP ctx)
2305 struct i965_driver_data *i965 = i965_driver_data(ctx);
2306 struct i965_render_state *render_state = &i965->render_state;
2310 dri_bo_unreference(render_state->vb.vertex_buffer);
2311 bo = dri_bo_alloc(i965->intel.bufmgr,
2316 render_state->vb.vertex_buffer = bo;
2319 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2320 bo = dri_bo_alloc(i965->intel.bufmgr,
2321 "surface state & binding table",
2322 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2325 render_state->wm.surface_state_binding_table_bo = bo;
2327 dri_bo_unreference(render_state->wm.sampler);
2328 bo = dri_bo_alloc(i965->intel.bufmgr,
2330 MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2333 render_state->wm.sampler = bo;
2334 render_state->wm.sampler_count = 0;
2336 /* COLOR CALCULATOR */
2337 dri_bo_unreference(render_state->cc.state);
2338 bo = dri_bo_alloc(i965->intel.bufmgr,
2340 sizeof(struct gen6_color_calc_state),
2343 render_state->cc.state = bo;
2346 dri_bo_unreference(render_state->cc.viewport);
2347 bo = dri_bo_alloc(i965->intel.bufmgr,
2349 sizeof(struct i965_cc_viewport),
2352 render_state->cc.viewport = bo;
2355 dri_bo_unreference(render_state->cc.blend);
2356 bo = dri_bo_alloc(i965->intel.bufmgr,
2358 sizeof(struct gen6_blend_state),
2361 render_state->cc.blend = bo;
2363 /* DEPTH & STENCIL STATE */
2364 dri_bo_unreference(render_state->cc.depth_stencil);
2365 bo = dri_bo_alloc(i965->intel.bufmgr,
2366 "depth & stencil state",
2367 sizeof(struct gen6_depth_stencil_state),
2370 render_state->cc.depth_stencil = bo;
2376 #define ALIGNMENT 64
2379 gen7_render_color_calc_state(VADriverContextP ctx)
2381 struct i965_driver_data *i965 = i965_driver_data(ctx);
2382 struct i965_render_state *render_state = &i965->render_state;
2383 struct gen6_color_calc_state *color_calc_state;
2385 dri_bo_map(render_state->cc.state, 1);
2386 assert(render_state->cc.state->virtual);
2387 color_calc_state = render_state->cc.state->virtual;
2388 memset(color_calc_state, 0, sizeof(*color_calc_state));
2389 color_calc_state->constant_r = 1.0;
2390 color_calc_state->constant_g = 0.0;
2391 color_calc_state->constant_b = 1.0;
2392 color_calc_state->constant_a = 1.0;
2393 dri_bo_unmap(render_state->cc.state);
2397 gen7_render_blend_state(VADriverContextP ctx)
2399 struct i965_driver_data *i965 = i965_driver_data(ctx);
2400 struct i965_render_state *render_state = &i965->render_state;
2401 struct gen6_blend_state *blend_state;
2403 dri_bo_map(render_state->cc.blend, 1);
2404 assert(render_state->cc.blend->virtual);
2405 blend_state = render_state->cc.blend->virtual;
2406 memset(blend_state, 0, sizeof(*blend_state));
2407 blend_state->blend1.logic_op_enable = 1;
2408 blend_state->blend1.logic_op_func = 0xc;
2409 blend_state->blend1.pre_blend_clamp_enable = 1;
2410 dri_bo_unmap(render_state->cc.blend);
2414 gen7_render_depth_stencil_state(VADriverContextP ctx)
2416 struct i965_driver_data *i965 = i965_driver_data(ctx);
2417 struct i965_render_state *render_state = &i965->render_state;
2418 struct gen6_depth_stencil_state *depth_stencil_state;
2420 dri_bo_map(render_state->cc.depth_stencil, 1);
2421 assert(render_state->cc.depth_stencil->virtual);
2422 depth_stencil_state = render_state->cc.depth_stencil->virtual;
2423 memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2424 dri_bo_unmap(render_state->cc.depth_stencil);
2428 gen7_render_sampler(VADriverContextP ctx)
2430 struct i965_driver_data *i965 = i965_driver_data(ctx);
2431 struct i965_render_state *render_state = &i965->render_state;
2432 struct gen7_sampler_state *sampler_state;
2435 assert(render_state->wm.sampler_count > 0);
2436 assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2438 dri_bo_map(render_state->wm.sampler, 1);
2439 assert(render_state->wm.sampler->virtual);
2440 sampler_state = render_state->wm.sampler->virtual;
2441 for (i = 0; i < render_state->wm.sampler_count; i++) {
2442 memset(sampler_state, 0, sizeof(*sampler_state));
2443 sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2444 sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2445 sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2446 sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2447 sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2451 dri_bo_unmap(render_state->wm.sampler);
2456 gen7_render_setup_states(
2457 VADriverContextP ctx,
2458 struct object_surface *obj_surface,
2459 const VARectangle *src_rect,
2460 const VARectangle *dst_rect,
2464 i965_render_dest_surface_state(ctx, 0);
2465 i965_render_src_surfaces_state(ctx, obj_surface, flags);
2466 gen7_render_sampler(ctx);
2467 i965_render_cc_viewport(ctx);
2468 gen7_render_color_calc_state(ctx);
2469 gen7_render_blend_state(ctx);
2470 gen7_render_depth_stencil_state(ctx);
2471 i965_render_upload_constants(ctx, obj_surface, flags);
2472 i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
2477 gen7_emit_invarient_states(VADriverContextP ctx)
2479 struct i965_driver_data *i965 = i965_driver_data(ctx);
2480 struct intel_batchbuffer *batch = i965->batch;
2482 BEGIN_BATCH(batch, 1);
2483 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2484 ADVANCE_BATCH(batch);
2486 BEGIN_BATCH(batch, 4);
2487 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2488 OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2489 GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2490 OUT_BATCH(batch, 0);
2491 OUT_BATCH(batch, 0);
2492 ADVANCE_BATCH(batch);
2494 BEGIN_BATCH(batch, 2);
2495 OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2496 OUT_BATCH(batch, 1);
2497 ADVANCE_BATCH(batch);
2499 /* Set system instruction pointer */
2500 BEGIN_BATCH(batch, 2);
2501 OUT_BATCH(batch, CMD_STATE_SIP | 0);
2502 OUT_BATCH(batch, 0);
2503 ADVANCE_BATCH(batch);
2507 gen7_emit_state_base_address(VADriverContextP ctx)
2509 struct i965_driver_data *i965 = i965_driver_data(ctx);
2510 struct intel_batchbuffer *batch = i965->batch;
2511 struct i965_render_state *render_state = &i965->render_state;
2513 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2514 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2515 OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2516 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2517 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2518 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2519 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2520 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2521 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2522 OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2526 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2528 struct i965_driver_data *i965 = i965_driver_data(ctx);
2529 struct intel_batchbuffer *batch = i965->batch;
2530 struct i965_render_state *render_state = &i965->render_state;
2532 BEGIN_BATCH(batch, 2);
2533 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2535 render_state->cc.viewport,
2536 I915_GEM_DOMAIN_INSTRUCTION, 0,
2538 ADVANCE_BATCH(batch);
2540 BEGIN_BATCH(batch, 2);
2541 OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2542 OUT_BATCH(batch, 0);
2543 ADVANCE_BATCH(batch);
2547 * URB layout on GEN7
2548 * ----------------------------------------
2549 * | PS Push Constants (8KB) | VS entries |
2550 * ----------------------------------------
2553 gen7_emit_urb(VADriverContextP ctx)
2555 struct i965_driver_data *i965 = i965_driver_data(ctx);
2556 struct intel_batchbuffer *batch = i965->batch;
2557 unsigned int num_urb_entries = 32;
2559 if (IS_HASWELL(i965->intel.device_info))
2560 num_urb_entries = 64;
2562 BEGIN_BATCH(batch, 2);
2563 OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2564 OUT_BATCH(batch, 8); /* in 1KBs */
2565 ADVANCE_BATCH(batch);
2567 BEGIN_BATCH(batch, 2);
2568 OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2570 (num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
2571 (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2572 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2573 ADVANCE_BATCH(batch);
2575 BEGIN_BATCH(batch, 2);
2576 OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2578 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2579 (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2580 ADVANCE_BATCH(batch);
2582 BEGIN_BATCH(batch, 2);
2583 OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2585 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2586 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2587 ADVANCE_BATCH(batch);
2589 BEGIN_BATCH(batch, 2);
2590 OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2592 (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2593 (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2594 ADVANCE_BATCH(batch);
2598 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2600 struct i965_driver_data *i965 = i965_driver_data(ctx);
2601 struct intel_batchbuffer *batch = i965->batch;
2602 struct i965_render_state *render_state = &i965->render_state;
2604 BEGIN_BATCH(batch, 2);
2605 OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2607 render_state->cc.state,
2608 I915_GEM_DOMAIN_INSTRUCTION, 0,
2610 ADVANCE_BATCH(batch);
2612 BEGIN_BATCH(batch, 2);
2613 OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2615 render_state->cc.blend,
2616 I915_GEM_DOMAIN_INSTRUCTION, 0,
2618 ADVANCE_BATCH(batch);
2620 BEGIN_BATCH(batch, 2);
2621 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2623 render_state->cc.depth_stencil,
2624 I915_GEM_DOMAIN_INSTRUCTION, 0,
2626 ADVANCE_BATCH(batch);
2630 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2632 struct i965_driver_data *i965 = i965_driver_data(ctx);
2633 struct intel_batchbuffer *batch = i965->batch;
2634 struct i965_render_state *render_state = &i965->render_state;
2636 BEGIN_BATCH(batch, 2);
2637 OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2639 render_state->wm.sampler,
2640 I915_GEM_DOMAIN_INSTRUCTION, 0,
2642 ADVANCE_BATCH(batch);
2646 gen7_emit_binding_table(VADriverContextP ctx)
2648 struct i965_driver_data *i965 = i965_driver_data(ctx);
2649 struct intel_batchbuffer *batch = i965->batch;
2651 BEGIN_BATCH(batch, 2);
2652 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2653 OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2654 ADVANCE_BATCH(batch);
2658 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2660 struct i965_driver_data *i965 = i965_driver_data(ctx);
2661 struct intel_batchbuffer *batch = i965->batch;
2663 BEGIN_BATCH(batch, 7);
2664 OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2666 (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2667 (I965_SURFACE_NULL << 29));
2668 OUT_BATCH(batch, 0);
2669 OUT_BATCH(batch, 0);
2670 OUT_BATCH(batch, 0);
2671 OUT_BATCH(batch, 0);
2672 OUT_BATCH(batch, 0);
2673 ADVANCE_BATCH(batch);
2675 BEGIN_BATCH(batch, 3);
2676 OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2677 OUT_BATCH(batch, 0);
2678 OUT_BATCH(batch, 0);
2679 ADVANCE_BATCH(batch);
2683 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2685 i965_render_drawing_rectangle(ctx);
2689 gen7_emit_vs_state(VADriverContextP ctx)
2691 struct i965_driver_data *i965 = i965_driver_data(ctx);
2692 struct intel_batchbuffer *batch = i965->batch;
2694 /* disable VS constant buffer */
2695 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2696 OUT_BATCH(batch, 0);
2697 OUT_BATCH(batch, 0);
2698 OUT_BATCH(batch, 0);
2699 OUT_BATCH(batch, 0);
2700 OUT_BATCH(batch, 0);
2701 OUT_BATCH(batch, 0);
2703 OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2704 OUT_BATCH(batch, 0); /* without VS kernel */
2705 OUT_BATCH(batch, 0);
2706 OUT_BATCH(batch, 0);
2707 OUT_BATCH(batch, 0);
2708 OUT_BATCH(batch, 0); /* pass-through */
2712 gen7_emit_bypass_state(VADriverContextP ctx)
2714 struct i965_driver_data *i965 = i965_driver_data(ctx);
2715 struct intel_batchbuffer *batch = i965->batch;
2718 BEGIN_BATCH(batch, 7);
2719 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2720 OUT_BATCH(batch, 0);
2721 OUT_BATCH(batch, 0);
2722 OUT_BATCH(batch, 0);
2723 OUT_BATCH(batch, 0);
2724 OUT_BATCH(batch, 0);
2725 OUT_BATCH(batch, 0);
2726 ADVANCE_BATCH(batch);
2728 BEGIN_BATCH(batch, 7);
2729 OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2730 OUT_BATCH(batch, 0); /* without GS kernel */
2731 OUT_BATCH(batch, 0);
2732 OUT_BATCH(batch, 0);
2733 OUT_BATCH(batch, 0);
2734 OUT_BATCH(batch, 0);
2735 OUT_BATCH(batch, 0); /* pass-through */
2736 ADVANCE_BATCH(batch);
2738 BEGIN_BATCH(batch, 2);
2739 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2740 OUT_BATCH(batch, 0);
2741 ADVANCE_BATCH(batch);
2744 BEGIN_BATCH(batch, 7);
2745 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2746 OUT_BATCH(batch, 0);
2747 OUT_BATCH(batch, 0);
2748 OUT_BATCH(batch, 0);
2749 OUT_BATCH(batch, 0);
2750 OUT_BATCH(batch, 0);
2751 OUT_BATCH(batch, 0);
2752 ADVANCE_BATCH(batch);
2754 BEGIN_BATCH(batch, 7);
2755 OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2756 OUT_BATCH(batch, 0);
2757 OUT_BATCH(batch, 0);
2758 OUT_BATCH(batch, 0);
2759 OUT_BATCH(batch, 0);
2760 OUT_BATCH(batch, 0);
2761 OUT_BATCH(batch, 0);
2762 ADVANCE_BATCH(batch);
2764 BEGIN_BATCH(batch, 2);
2765 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2766 OUT_BATCH(batch, 0);
2767 ADVANCE_BATCH(batch);
2770 BEGIN_BATCH(batch, 4);
2771 OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2772 OUT_BATCH(batch, 0);
2773 OUT_BATCH(batch, 0);
2774 OUT_BATCH(batch, 0);
2775 ADVANCE_BATCH(batch);
2778 BEGIN_BATCH(batch, 7);
2779 OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2780 OUT_BATCH(batch, 0);
2781 OUT_BATCH(batch, 0);
2782 OUT_BATCH(batch, 0);
2783 OUT_BATCH(batch, 0);
2784 OUT_BATCH(batch, 0);
2785 OUT_BATCH(batch, 0);
2786 ADVANCE_BATCH(batch);
2788 BEGIN_BATCH(batch, 6);
2789 OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2790 OUT_BATCH(batch, 0);
2791 OUT_BATCH(batch, 0);
2792 OUT_BATCH(batch, 0);
2793 OUT_BATCH(batch, 0);
2794 OUT_BATCH(batch, 0);
2795 ADVANCE_BATCH(batch);
2797 BEGIN_BATCH(batch, 2);
2798 OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2799 OUT_BATCH(batch, 0);
2800 ADVANCE_BATCH(batch);
2802 /* Disable STREAMOUT */
2803 BEGIN_BATCH(batch, 3);
2804 OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2805 OUT_BATCH(batch, 0);
2806 OUT_BATCH(batch, 0);
2807 ADVANCE_BATCH(batch);
2811 gen7_emit_clip_state(VADriverContextP ctx)
2813 struct i965_driver_data *i965 = i965_driver_data(ctx);
2814 struct intel_batchbuffer *batch = i965->batch;
2816 OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2817 OUT_BATCH(batch, 0);
2818 OUT_BATCH(batch, 0); /* pass-through */
2819 OUT_BATCH(batch, 0);
2823 gen7_emit_sf_state(VADriverContextP ctx)
2825 struct i965_driver_data *i965 = i965_driver_data(ctx);
2826 struct intel_batchbuffer *batch = i965->batch;
2828 BEGIN_BATCH(batch, 14);
2829 OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2831 (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2832 (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2833 (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2834 OUT_BATCH(batch, 0);
2835 OUT_BATCH(batch, 0);
2836 OUT_BATCH(batch, 0); /* DW4 */
2837 OUT_BATCH(batch, 0);
2838 OUT_BATCH(batch, 0);
2839 OUT_BATCH(batch, 0);
2840 OUT_BATCH(batch, 0);
2841 OUT_BATCH(batch, 0); /* DW9 */
2842 OUT_BATCH(batch, 0);
2843 OUT_BATCH(batch, 0);
2844 OUT_BATCH(batch, 0);
2845 OUT_BATCH(batch, 0);
2846 ADVANCE_BATCH(batch);
2848 BEGIN_BATCH(batch, 7);
2849 OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2850 OUT_BATCH(batch, 0);
2851 OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2852 OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2853 OUT_BATCH(batch, 0);
2854 OUT_BATCH(batch, 0);
2855 OUT_BATCH(batch, 0);
2856 ADVANCE_BATCH(batch);
2860 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2862 struct i965_driver_data *i965 = i965_driver_data(ctx);
2863 struct intel_batchbuffer *batch = i965->batch;
2864 struct i965_render_state *render_state = &i965->render_state;
2865 unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
2866 unsigned int num_samples = 0;
2868 if (IS_HASWELL(i965->intel.device_info)) {
2869 max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
2870 num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
2873 BEGIN_BATCH(batch, 3);
2874 OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2876 GEN7_WM_DISPATCH_ENABLE |
2877 GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2878 OUT_BATCH(batch, 0);
2879 ADVANCE_BATCH(batch);
2881 BEGIN_BATCH(batch, 7);
2882 OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2883 OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
2884 OUT_BATCH(batch, 0);
2886 render_state->curbe.bo,
2887 I915_GEM_DOMAIN_INSTRUCTION, 0,
2889 OUT_BATCH(batch, 0);
2890 OUT_BATCH(batch, 0);
2891 OUT_BATCH(batch, 0);
2892 ADVANCE_BATCH(batch);
2894 BEGIN_BATCH(batch, 8);
2895 OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2897 render_state->render_kernels[kernel].bo,
2898 I915_GEM_DOMAIN_INSTRUCTION, 0,
2901 (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2902 (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2903 OUT_BATCH(batch, 0); /* scratch space base offset */
2905 ((i965->intel.device_info->max_wm_threads - 1) << max_threads_shift) | num_samples |
2906 GEN7_PS_PUSH_CONSTANT_ENABLE |
2907 GEN7_PS_ATTRIBUTE_ENABLE |
2908 GEN7_PS_16_DISPATCH_ENABLE);
2910 (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2911 OUT_BATCH(batch, 0); /* kernel 1 pointer */
2912 OUT_BATCH(batch, 0); /* kernel 2 pointer */
2913 ADVANCE_BATCH(batch);
2917 gen7_emit_vertex_element_state(VADriverContextP ctx)
2919 struct i965_driver_data *i965 = i965_driver_data(ctx);
2920 struct intel_batchbuffer *batch = i965->batch;
2922 /* Set up our vertex elements, sourced from the single vertex buffer. */
2923 OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2924 /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2925 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2927 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2928 (0 << VE0_OFFSET_SHIFT));
2929 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2930 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2931 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2932 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2933 /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2934 OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2936 (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2937 (8 << VE0_OFFSET_SHIFT));
2938 OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2939 (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2940 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2941 (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2945 gen7_emit_vertices(VADriverContextP ctx)
2947 struct i965_driver_data *i965 = i965_driver_data(ctx);
2948 struct intel_batchbuffer *batch = i965->batch;
2949 struct i965_render_state *render_state = &i965->render_state;
2951 BEGIN_BATCH(batch, 5);
2952 OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2954 (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2955 GEN6_VB0_VERTEXDATA |
2956 GEN7_VB0_ADDRESS_MODIFYENABLE |
2957 ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2958 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2959 OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2960 OUT_BATCH(batch, 0);
2961 ADVANCE_BATCH(batch);
2963 BEGIN_BATCH(batch, 7);
2964 OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2967 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2968 OUT_BATCH(batch, 3); /* vertex count per instance */
2969 OUT_BATCH(batch, 0); /* start vertex offset */
2970 OUT_BATCH(batch, 1); /* single instance */
2971 OUT_BATCH(batch, 0); /* start instance location */
2972 OUT_BATCH(batch, 0);
2973 ADVANCE_BATCH(batch);
2977 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2979 struct i965_driver_data *i965 = i965_driver_data(ctx);
2980 struct intel_batchbuffer *batch = i965->batch;
2982 intel_batchbuffer_start_atomic(batch, 0x1000);
2983 intel_batchbuffer_emit_mi_flush(batch);
2984 gen7_emit_invarient_states(ctx);
2985 gen7_emit_state_base_address(ctx);
2986 gen7_emit_viewport_state_pointers(ctx);
2988 gen7_emit_cc_state_pointers(ctx);
2989 gen7_emit_sampler_state_pointers(ctx);
2990 gen7_emit_bypass_state(ctx);
2991 gen7_emit_vs_state(ctx);
2992 gen7_emit_clip_state(ctx);
2993 gen7_emit_sf_state(ctx);
2994 gen7_emit_wm_state(ctx, kernel);
2995 gen7_emit_binding_table(ctx);
2996 gen7_emit_depth_buffer_state(ctx);
2997 gen7_emit_drawing_rectangle(ctx);
2998 gen7_emit_vertex_element_state(ctx);
2999 gen7_emit_vertices(ctx);
3000 intel_batchbuffer_end_atomic(batch);
3005 gen7_render_put_surface(
3006 VADriverContextP ctx,
3007 struct object_surface *obj_surface,
3008 const VARectangle *src_rect,
3009 const VARectangle *dst_rect,
3013 struct i965_driver_data *i965 = i965_driver_data(ctx);
3014 struct intel_batchbuffer *batch = i965->batch;
3016 gen7_render_initialize(ctx);
3017 gen7_render_setup_states(ctx, obj_surface, src_rect, dst_rect, flags);
3018 i965_clear_dest_region(ctx);
3019 gen7_render_emit_states(ctx, PS_KERNEL);
3020 intel_batchbuffer_flush(batch);
3025 gen7_subpicture_render_blend_state(VADriverContextP ctx)
3027 struct i965_driver_data *i965 = i965_driver_data(ctx);
3028 struct i965_render_state *render_state = &i965->render_state;
3029 struct gen6_blend_state *blend_state;
3031 dri_bo_unmap(render_state->cc.state);
3032 dri_bo_map(render_state->cc.blend, 1);
3033 assert(render_state->cc.blend->virtual);
3034 blend_state = render_state->cc.blend->virtual;
3035 memset(blend_state, 0, sizeof(*blend_state));
3036 blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
3037 blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
3038 blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
3039 blend_state->blend0.blend_enable = 1;
3040 blend_state->blend1.post_blend_clamp_enable = 1;
3041 blend_state->blend1.pre_blend_clamp_enable = 1;
3042 blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
3043 dri_bo_unmap(render_state->cc.blend);
3047 gen7_subpicture_render_setup_states(
3048 VADriverContextP ctx,
3049 struct object_surface *obj_surface,
3050 const VARectangle *src_rect,
3051 const VARectangle *dst_rect
3054 i965_render_dest_surface_state(ctx, 0);
3055 i965_subpic_render_src_surfaces_state(ctx, obj_surface);
3056 i965_render_sampler(ctx);
3057 i965_render_cc_viewport(ctx);
3058 gen7_render_color_calc_state(ctx);
3059 gen7_subpicture_render_blend_state(ctx);
3060 gen7_render_depth_stencil_state(ctx);
3061 i965_subpic_render_upload_constants(ctx, obj_surface);
3062 i965_subpic_render_upload_vertex(ctx, obj_surface, dst_rect);
3066 gen7_render_put_subpicture(
3067 VADriverContextP ctx,
3068 struct object_surface *obj_surface,
3069 const VARectangle *src_rect,
3070 const VARectangle *dst_rect
3073 struct i965_driver_data *i965 = i965_driver_data(ctx);
3074 struct intel_batchbuffer *batch = i965->batch;
3075 unsigned int index = obj_surface->subpic_render_idx;
3076 struct object_subpic *obj_subpic = obj_surface->obj_subpic[index];
3079 gen7_render_initialize(ctx);
3080 gen7_subpicture_render_setup_states(ctx, obj_surface, src_rect, dst_rect);
3081 gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
3082 i965_render_upload_image_palette(ctx, obj_subpic->obj_image, 0xff);
3083 intel_batchbuffer_flush(batch);
3088 intel_render_put_surface(
3089 VADriverContextP ctx,
3090 struct object_surface *obj_surface,
3091 const VARectangle *src_rect,
3092 const VARectangle *dst_rect,
3096 struct i965_driver_data *i965 = i965_driver_data(ctx);
3097 struct i965_render_state *render_state = &i965->render_state;
3098 int has_done_scaling = 0;
3099 VASurfaceID out_surface_id = i965_post_processing(ctx,
3106 assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
3108 if (out_surface_id != VA_INVALID_ID) {
3109 struct object_surface *new_obj_surface = SURFACE(out_surface_id);
3111 if (new_obj_surface && new_obj_surface->bo)
3112 obj_surface = new_obj_surface;
3114 if (has_done_scaling)
3115 src_rect = dst_rect;
3118 render_state->render_put_surface(ctx, obj_surface, src_rect, dst_rect, flags);
3120 if (out_surface_id != VA_INVALID_ID)
3121 i965_DestroySurfaces(ctx, &out_surface_id, 1);
3125 intel_render_put_subpicture(
3126 VADriverContextP ctx,
3127 struct object_surface *obj_surface,
3128 const VARectangle *src_rect,
3129 const VARectangle *dst_rect
3132 struct i965_driver_data *i965 = i965_driver_data(ctx);
3133 struct i965_render_state *render_state = &i965->render_state;
3135 render_state->render_put_subpicture(ctx, obj_surface, src_rect, dst_rect);
3139 genx_render_terminate(VADriverContextP ctx)
3142 struct i965_driver_data *i965 = i965_driver_data(ctx);
3143 struct i965_render_state *render_state = &i965->render_state;
3145 dri_bo_unreference(render_state->curbe.bo);
3146 render_state->curbe.bo = NULL;
3148 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3149 struct i965_kernel *kernel = &render_state->render_kernels[i];
3151 dri_bo_unreference(kernel->bo);
3155 dri_bo_unreference(render_state->vb.vertex_buffer);
3156 render_state->vb.vertex_buffer = NULL;
3157 dri_bo_unreference(render_state->vs.state);
3158 render_state->vs.state = NULL;
3159 dri_bo_unreference(render_state->sf.state);
3160 render_state->sf.state = NULL;
3161 dri_bo_unreference(render_state->wm.sampler);
3162 render_state->wm.sampler = NULL;
3163 dri_bo_unreference(render_state->wm.state);
3164 render_state->wm.state = NULL;
3165 dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3166 dri_bo_unreference(render_state->cc.viewport);
3167 render_state->cc.viewport = NULL;
3168 dri_bo_unreference(render_state->cc.state);
3169 render_state->cc.state = NULL;
3170 dri_bo_unreference(render_state->cc.blend);
3171 render_state->cc.blend = NULL;
3172 dri_bo_unreference(render_state->cc.depth_stencil);
3173 render_state->cc.depth_stencil = NULL;
3175 if (render_state->draw_region) {
3176 dri_bo_unreference(render_state->draw_region->bo);
3177 free(render_state->draw_region);
3178 render_state->draw_region = NULL;
3183 genx_render_init(VADriverContextP ctx)
3185 struct i965_driver_data *i965 = i965_driver_data(ctx);
3186 struct i965_render_state *render_state = &i965->render_state;
3190 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
3191 sizeof(render_kernels_gen5[0])));
3192 assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
3193 sizeof(render_kernels_gen6[0])));
3195 if (IS_GEN7(i965->intel.device_info)) {
3196 memcpy(render_state->render_kernels,
3197 (IS_HASWELL(i965->intel.device_info) ? render_kernels_gen7_haswell : render_kernels_gen7),
3198 sizeof(render_state->render_kernels));
3199 render_state->render_put_surface = gen7_render_put_surface;
3200 render_state->render_put_subpicture = gen7_render_put_subpicture;
3201 } else if (IS_GEN6(i965->intel.device_info)) {
3202 memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
3203 render_state->render_put_surface = gen6_render_put_surface;
3204 render_state->render_put_subpicture = gen6_render_put_subpicture;
3205 } else if (IS_IRONLAKE(i965->intel.device_info)) {
3206 memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
3207 render_state->render_put_surface = i965_render_put_surface;
3208 render_state->render_put_subpicture = i965_render_put_subpicture;
3210 memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
3211 render_state->render_put_surface = i965_render_put_surface;
3212 render_state->render_put_subpicture = i965_render_put_subpicture;
3215 render_state->render_terminate = genx_render_terminate;
3217 for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3218 struct i965_kernel *kernel = &render_state->render_kernels[i];
3223 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
3225 kernel->size, 0x1000);
3227 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
3230 /* constant buffer */
3231 render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
3234 assert(render_state->curbe.bo);
3240 i965_render_init(VADriverContextP ctx)
3242 struct i965_driver_data *i965 = i965_driver_data(ctx);
3244 return i965->codec_info->render_init(ctx);
3248 i965_render_terminate(VADriverContextP ctx)
3250 struct i965_driver_data *i965 = i965_driver_data(ctx);
3251 struct i965_render_state *render_state = &i965->render_state;
3253 render_state->render_terminate(ctx);