src/i965_render.c

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Xiang Haihao <haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 /*
  31  * Most of rendering codes are ported from xf86-video-intel/src/i965_video.c
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <assert.h>
  38
  39 #include <va/va_backend.h>
  40 #include <va/va_dricommon.h>
  41
  42 #include "intel_batchbuffer.h"
  43 #include "intel_driver.h"
  44 #include "i965_defines.h"
  45 #include "i965_drv_video.h"
  46 #include "i965_structs.h"
  47
  48 #include "i965_render.h"
  49
  50 #define SF_KERNEL_NUM_GRF       16
  51 #define SF_MAX_THREADS          1
  52
  53 static const uint32_t sf_kernel_static[][4] =
  54 {
  55 #include "shaders/render/exa_sf.g4b"
  56 };
  57
  58 #define PS_KERNEL_NUM_GRF       32
  59 #define PS_MAX_THREADS          32
  60
  61 #define I965_GRF_BLOCKS(nreg)   ((nreg + 15) / 16 - 1)
  62
  63 static const uint32_t ps_kernel_static[][4] =
  64 {
  65 #include "shaders/render/exa_wm_xy.g4b"
  66 #include "shaders/render/exa_wm_src_affine.g4b"
  67 #include "shaders/render/exa_wm_src_sample_planar.g4b"
  68 #include "shaders/render/exa_wm_yuv_rgb.g4b"
  69 #include "shaders/render/exa_wm_write.g4b"
  70 };
  71 static const uint32_t ps_subpic_kernel_static[][4] =
  72 {
  73 #include "shaders/render/exa_wm_xy.g4b"
  74 #include "shaders/render/exa_wm_src_affine.g4b"
  75 #include "shaders/render/exa_wm_src_sample_argb.g4b"
  76 #include "shaders/render/exa_wm_write.g4b"
  77 };
  78
  79 /* On IRONLAKE */
  80 static const uint32_t sf_kernel_static_gen5[][4] =
  81 {
  82 #include "shaders/render/exa_sf.g4b.gen5"
  83 };
  84
  85 static const uint32_t ps_kernel_static_gen5[][4] =
  86 {
  87 #include "shaders/render/exa_wm_xy.g4b.gen5"
  88 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
  89 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
  90 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
  91 #include "shaders/render/exa_wm_write.g4b.gen5"
  92 };
  93 static const uint32_t ps_subpic_kernel_static_gen5[][4] =
  94 {
  95 #include "shaders/render/exa_wm_xy.g4b.gen5"
  96 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
  97 #include "shaders/render/exa_wm_src_sample_argb.g4b.gen5"
  98 #include "shaders/render/exa_wm_write.g4b.gen5"
  99 };
 100
 101 /* programs for Sandybridge */
 102 static const uint32_t sf_kernel_static_gen6[][4] =
 103 {
 104 };
 105
 106 static const uint32_t ps_kernel_static_gen6[][4] = {
 107 #include "shaders/render/exa_wm_src_affine.g6b"
 108 #include "shaders/render/exa_wm_src_sample_planar.g6b"
 109 #include "shaders/render/exa_wm_yuv_rgb.g6b"
 110 #include "shaders/render/exa_wm_write.g6b"
 111 };
 112
 113 static const uint32_t ps_subpic_kernel_static_gen6[][4] = {
 114 #include "shaders/render/exa_wm_src_affine.g6b"
 115 #include "shaders/render/exa_wm_src_sample_argb.g6b"
 116 #include "shaders/render/exa_wm_write.g6b"
 117 };
 118
 119 /* programs for Ivybridge */
 120 static const uint32_t sf_kernel_static_gen7[][4] =
 121 {
 122 };
 123
 124 static const uint32_t ps_kernel_static_gen7[][4] = {
 125 #include "shaders/render/exa_wm_src_affine.g7b"
 126 #include "shaders/render/exa_wm_src_sample_planar.g7b"
 127 #include "shaders/render/exa_wm_yuv_rgb.g7b"
 128 #include "shaders/render/exa_wm_write.g7b"
 129 };
 130
 131 static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
 132 #include "shaders/render/exa_wm_src_affine.g7b"
 133 #include "shaders/render/exa_wm_src_sample_argb.g7b"
 134 #include "shaders/render/exa_wm_write.g7b"
 135 };
 136
 137 #define SURFACE_STATE_PADDED_SIZE_I965  ALIGN(sizeof(struct i965_surface_state), 32)
 138 #define SURFACE_STATE_PADDED_SIZE_GEN7  ALIGN(sizeof(struct gen7_surface_state), 32)
 139 #define SURFACE_STATE_PADDED_SIZE       MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
 140 #define SURFACE_STATE_OFFSET(index)     (SURFACE_STATE_PADDED_SIZE * index)
 141 #define BINDING_TABLE_OFFSET            SURFACE_STATE_OFFSET(MAX_RENDER_SURFACES)
 142
 143 static uint32_t float_to_uint (float f)
 144 {
 145     union {
 146         uint32_t i;
 147         float f;
 148     } x;
 149
 150     x.f = f;
 151     return x.i;
 152 }
 153
 154 enum
 155 {
 156     SF_KERNEL = 0,
 157     PS_KERNEL,
 158     PS_SUBPIC_KERNEL
 159 };
 160
 161 static struct i965_kernel render_kernels_gen4[] = {
 162     {
 163         "SF",
 164         SF_KERNEL,
 165         sf_kernel_static,
 166         sizeof(sf_kernel_static),
 167         NULL
 168     },
 169     {
 170         "PS",
 171         PS_KERNEL,
 172         ps_kernel_static,
 173         sizeof(ps_kernel_static),
 174         NULL
 175     },
 176
 177     {
 178         "PS_SUBPIC",
 179         PS_SUBPIC_KERNEL,
 180         ps_subpic_kernel_static,
 181         sizeof(ps_subpic_kernel_static),
 182         NULL
 183     }
 184 };
 185
 186 static struct i965_kernel render_kernels_gen5[] = {
 187     {
 188         "SF",
 189         SF_KERNEL,
 190         sf_kernel_static_gen5,
 191         sizeof(sf_kernel_static_gen5),
 192         NULL
 193     },
 194     {
 195         "PS",
 196         PS_KERNEL,
 197         ps_kernel_static_gen5,
 198         sizeof(ps_kernel_static_gen5),
 199         NULL
 200     },
 201
 202     {
 203         "PS_SUBPIC",
 204         PS_SUBPIC_KERNEL,
 205         ps_subpic_kernel_static_gen5,
 206         sizeof(ps_subpic_kernel_static_gen5),
 207         NULL
 208     }
 209 };
 210
 211 static struct i965_kernel render_kernels_gen6[] = {
 212     {
 213         "SF",
 214         SF_KERNEL,
 215         sf_kernel_static_gen6,
 216         sizeof(sf_kernel_static_gen6),
 217         NULL
 218     },
 219     {
 220         "PS",
 221         PS_KERNEL,
 222         ps_kernel_static_gen6,
 223         sizeof(ps_kernel_static_gen6),
 224         NULL
 225     },
 226
 227     {
 228         "PS_SUBPIC",
 229         PS_SUBPIC_KERNEL,
 230         ps_subpic_kernel_static_gen6,
 231         sizeof(ps_subpic_kernel_static_gen6),
 232         NULL
 233     }
 234 };
 235
 236 static struct i965_kernel render_kernels_gen7[] = {
 237     {
 238         "SF",
 239         SF_KERNEL,
 240         sf_kernel_static_gen7,
 241         sizeof(sf_kernel_static_gen7),
 242         NULL
 243     },
 244     {
 245         "PS",
 246         PS_KERNEL,
 247         ps_kernel_static_gen7,
 248         sizeof(ps_kernel_static_gen7),
 249         NULL
 250     },
 251
 252     {
 253         "PS_SUBPIC",
 254         PS_SUBPIC_KERNEL,
 255         ps_subpic_kernel_static_gen7,
 256         sizeof(ps_subpic_kernel_static_gen7),
 257         NULL
 258     }
 259 };
 260
 261 #define URB_VS_ENTRIES        8
 262 #define URB_VS_ENTRY_SIZE     1
 263
 264 #define URB_GS_ENTRIES        0
 265 #define URB_GS_ENTRY_SIZE     0
 266
 267 #define URB_CLIP_ENTRIES      0
 268 #define URB_CLIP_ENTRY_SIZE   0
 269
 270 #define URB_SF_ENTRIES        1
 271 #define URB_SF_ENTRY_SIZE     2
 272
 273 #define URB_CS_ENTRIES        1
 274 #define URB_CS_ENTRY_SIZE     1
 275
 276 static void
 277 i965_render_vs_unit(VADriverContextP ctx)
 278 {
 279     struct i965_driver_data *i965 = i965_driver_data(ctx);
 280     struct i965_render_state *render_state = &i965->render_state;
 281     struct i965_vs_unit_state *vs_state;
 282
 283     dri_bo_map(render_state->vs.state, 1);
 284     assert(render_state->vs.state->virtual);
 285     vs_state = render_state->vs.state->virtual;
 286     memset(vs_state, 0, sizeof(*vs_state));
 287
 288     if (IS_IRONLAKE(i965->intel.device_id))
 289         vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
 290     else
 291         vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
 292
 293     vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
 294     vs_state->vs6.vs_enable = 0;
 295     vs_state->vs6.vert_cache_disable = 1;
 296
 297     dri_bo_unmap(render_state->vs.state);
 298 }
 299
 300 static void
 301 i965_render_sf_unit(VADriverContextP ctx)
 302 {
 303     struct i965_driver_data *i965 = i965_driver_data(ctx);
 304     struct i965_render_state *render_state = &i965->render_state;
 305     struct i965_sf_unit_state *sf_state;
 306
 307     dri_bo_map(render_state->sf.state, 1);
 308     assert(render_state->sf.state->virtual);
 309     sf_state = render_state->sf.state->virtual;
 310     memset(sf_state, 0, sizeof(*sf_state));
 311
 312     sf_state->thread0.grf_reg_count = I965_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
 313     sf_state->thread0.kernel_start_pointer = render_state->render_kernels[SF_KERNEL].bo->offset >> 6;
 314
 315     sf_state->sf1.single_program_flow = 1; /* XXX */
 316     sf_state->sf1.binding_table_entry_count = 0;
 317     sf_state->sf1.thread_priority = 0;
 318     sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
 319     sf_state->sf1.illegal_op_exception_enable = 1;
 320     sf_state->sf1.mask_stack_exception_enable = 1;
 321     sf_state->sf1.sw_exception_enable = 1;
 322
 323     /* scratch space is not used in our kernel */
 324     sf_state->thread2.per_thread_scratch_space = 0;
 325     sf_state->thread2.scratch_space_base_pointer = 0;
 326
 327     sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
 328     sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
 329     sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
 330     sf_state->thread3.urb_entry_read_offset = 0;
 331     sf_state->thread3.dispatch_grf_start_reg = 3;
 332
 333     sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
 334     sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
 335     sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
 336     sf_state->thread4.stats_enable = 1;
 337
 338     sf_state->sf5.viewport_transform = 0; /* skip viewport */
 339
 340     sf_state->sf6.cull_mode = I965_CULLMODE_NONE;
 341     sf_state->sf6.scissor = 0;
 342
 343     sf_state->sf7.trifan_pv = 2;
 344
 345     sf_state->sf6.dest_org_vbias = 0x8;
 346     sf_state->sf6.dest_org_hbias = 0x8;
 347
 348     dri_bo_emit_reloc(render_state->sf.state,
 349                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 350                       sf_state->thread0.grf_reg_count << 1,
 351                       offsetof(struct i965_sf_unit_state, thread0),
 352                       render_state->render_kernels[SF_KERNEL].bo);
 353
 354     dri_bo_unmap(render_state->sf.state);
 355 }
 356
 357 static void
 358 i965_render_sampler(VADriverContextP ctx)
 359 {
 360     struct i965_driver_data *i965 = i965_driver_data(ctx);
 361     struct i965_render_state *render_state = &i965->render_state;
 362     struct i965_sampler_state *sampler_state;
 363     int i;
 364
 365     assert(render_state->wm.sampler_count > 0);
 366     assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
 367
 368     dri_bo_map(render_state->wm.sampler, 1);
 369     assert(render_state->wm.sampler->virtual);
 370     sampler_state = render_state->wm.sampler->virtual;
 371     for (i = 0; i < render_state->wm.sampler_count; i++) {
 372         memset(sampler_state, 0, sizeof(*sampler_state));
 373         sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
 374         sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
 375         sampler_state->ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 376         sampler_state->ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 377         sampler_state->ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
 378         sampler_state++;
 379     }
 380
 381     dri_bo_unmap(render_state->wm.sampler);
 382 }
 383 static void
 384 i965_subpic_render_wm_unit(VADriverContextP ctx)
 385 {
 386     struct i965_driver_data *i965 = i965_driver_data(ctx);
 387     struct i965_render_state *render_state = &i965->render_state;
 388     struct i965_wm_unit_state *wm_state;
 389
 390     assert(render_state->wm.sampler);
 391
 392     dri_bo_map(render_state->wm.state, 1);
 393     assert(render_state->wm.state->virtual);
 394     wm_state = render_state->wm.state->virtual;
 395     memset(wm_state, 0, sizeof(*wm_state));
 396
 397     wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
 398     wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_SUBPIC_KERNEL].bo->offset >> 6;
 399
 400     wm_state->thread1.single_program_flow = 1; /* XXX */
 401
 402     if (IS_IRONLAKE(i965->intel.device_id))
 403         wm_state->thread1.binding_table_entry_count = 0; /* hardware requirement */
 404     else
 405         wm_state->thread1.binding_table_entry_count = 7;
 406
 407     wm_state->thread2.scratch_space_base_pointer = 0;
 408     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 409
 410     wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
 411     wm_state->thread3.const_urb_entry_read_length = 0;
 412     wm_state->thread3.const_urb_entry_read_offset = 0;
 413     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
 414     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
 415
 416     wm_state->wm4.stats_enable = 0;
 417     wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
 418
 419     if (IS_IRONLAKE(i965->intel.device_id)) {
 420         wm_state->wm4.sampler_count = 0;        /* hardware requirement */
 421         wm_state->wm5.max_threads = 12 * 6 - 1;
 422     } else {
 423         wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
 424         wm_state->wm5.max_threads = 10 * 5 - 1;
 425     }
 426
 427     wm_state->wm5.thread_dispatch_enable = 1;
 428     wm_state->wm5.enable_16_pix = 1;
 429     wm_state->wm5.enable_8_pix = 0;
 430     wm_state->wm5.early_depth_test = 1;
 431
 432     dri_bo_emit_reloc(render_state->wm.state,
 433                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 434                       wm_state->thread0.grf_reg_count << 1,
 435                       offsetof(struct i965_wm_unit_state, thread0),
 436                       render_state->render_kernels[PS_SUBPIC_KERNEL].bo);
 437
 438     dri_bo_emit_reloc(render_state->wm.state,
 439                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 440                       wm_state->wm4.sampler_count << 2,
 441                       offsetof(struct i965_wm_unit_state, wm4),
 442                       render_state->wm.sampler);
 443
 444     dri_bo_unmap(render_state->wm.state);
 445 }
 446
 447
 448 static void
 449 i965_render_wm_unit(VADriverContextP ctx)
 450 {
 451     struct i965_driver_data *i965 = i965_driver_data(ctx);
 452     struct i965_render_state *render_state = &i965->render_state;
 453     struct i965_wm_unit_state *wm_state;
 454
 455     assert(render_state->wm.sampler);
 456
 457     dri_bo_map(render_state->wm.state, 1);
 458     assert(render_state->wm.state->virtual);
 459     wm_state = render_state->wm.state->virtual;
 460     memset(wm_state, 0, sizeof(*wm_state));
 461
 462     wm_state->thread0.grf_reg_count = I965_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
 463     wm_state->thread0.kernel_start_pointer = render_state->render_kernels[PS_KERNEL].bo->offset >> 6;
 464
 465     wm_state->thread1.single_program_flow = 1; /* XXX */
 466
 467     if (IS_IRONLAKE(i965->intel.device_id))
 468         wm_state->thread1.binding_table_entry_count = 0;        /* hardware requirement */
 469     else
 470         wm_state->thread1.binding_table_entry_count = 7;
 471
 472     wm_state->thread2.scratch_space_base_pointer = 0;
 473     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 474
 475     wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
 476     wm_state->thread3.const_urb_entry_read_length = 1;
 477     wm_state->thread3.const_urb_entry_read_offset = 0;
 478     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
 479     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
 480
 481     wm_state->wm4.stats_enable = 0;
 482     wm_state->wm4.sampler_state_pointer = render_state->wm.sampler->offset >> 5;
 483
 484     if (IS_IRONLAKE(i965->intel.device_id)) {
 485         wm_state->wm4.sampler_count = 0;        /* hardware requirement */
 486         wm_state->wm5.max_threads = 12 * 6 - 1;
 487     } else {
 488         wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4;
 489         wm_state->wm5.max_threads = 10 * 5 - 1;
 490     }
 491
 492     wm_state->wm5.thread_dispatch_enable = 1;
 493     wm_state->wm5.enable_16_pix = 1;
 494     wm_state->wm5.enable_8_pix = 0;
 495     wm_state->wm5.early_depth_test = 1;
 496
 497     dri_bo_emit_reloc(render_state->wm.state,
 498                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 499                       wm_state->thread0.grf_reg_count << 1,
 500                       offsetof(struct i965_wm_unit_state, thread0),
 501                       render_state->render_kernels[PS_KERNEL].bo);
 502
 503     dri_bo_emit_reloc(render_state->wm.state,
 504                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 505                       wm_state->wm4.sampler_count << 2,
 506                       offsetof(struct i965_wm_unit_state, wm4),
 507                       render_state->wm.sampler);
 508
 509     dri_bo_unmap(render_state->wm.state);
 510 }
 511
 512 static void
 513 i965_render_cc_viewport(VADriverContextP ctx)
 514 {
 515     struct i965_driver_data *i965 = i965_driver_data(ctx);
 516     struct i965_render_state *render_state = &i965->render_state;
 517     struct i965_cc_viewport *cc_viewport;
 518
 519     dri_bo_map(render_state->cc.viewport, 1);
 520     assert(render_state->cc.viewport->virtual);
 521     cc_viewport = render_state->cc.viewport->virtual;
 522     memset(cc_viewport, 0, sizeof(*cc_viewport));
 523
 524     cc_viewport->min_depth = -1.e35;
 525     cc_viewport->max_depth = 1.e35;
 526
 527     dri_bo_unmap(render_state->cc.viewport);
 528 }
 529
 530 static void
 531 i965_subpic_render_cc_unit(VADriverContextP ctx)
 532 {
 533     struct i965_driver_data *i965 = i965_driver_data(ctx);
 534     struct i965_render_state *render_state = &i965->render_state;
 535     struct i965_cc_unit_state *cc_state;
 536
 537     assert(render_state->cc.viewport);
 538
 539     dri_bo_map(render_state->cc.state, 1);
 540     assert(render_state->cc.state->virtual);
 541     cc_state = render_state->cc.state->virtual;
 542     memset(cc_state, 0, sizeof(*cc_state));
 543
 544     cc_state->cc0.stencil_enable = 0;   /* disable stencil */
 545     cc_state->cc2.depth_test = 0;       /* disable depth test */
 546     cc_state->cc2.logicop_enable = 0;   /* disable logic op */
 547     cc_state->cc3.ia_blend_enable = 0 ;  /* blend alpha just like colors */
 548     cc_state->cc3.blend_enable = 1;     /* enable color blend */
 549     cc_state->cc3.alpha_test = 0;       /* disable alpha test */
 550     cc_state->cc3.alpha_test_format = 0;//0:ALPHATEST_UNORM8;       /*store alpha value with UNORM8 */
 551     cc_state->cc3.alpha_test_func = 5;//COMPAREFUNCTION_LESS;       /*pass if less than the reference */
 552     cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
 553
 554     cc_state->cc5.dither_enable = 0;    /* disable dither */
 555     cc_state->cc5.logicop_func = 0xc;   /* WHITE */
 556     cc_state->cc5.statistics_enable = 1;
 557     cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
 558     cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
 559     cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_DST_ALPHA;
 560
 561     cc_state->cc6.clamp_post_alpha_blend = 0;
 562     cc_state->cc6.clamp_pre_alpha_blend  =0;
 563
 564     /*final color = src_color*src_blend_factor +/- dst_color*dest_color_blend_factor*/
 565     cc_state->cc6.blend_function = I965_BLENDFUNCTION_ADD;
 566     cc_state->cc6.src_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
 567     cc_state->cc6.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
 568
 569     /*alpha test reference*/
 570     cc_state->cc7.alpha_ref.f =0.0 ;
 571
 572
 573     dri_bo_emit_reloc(render_state->cc.state,
 574                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 575                       0,
 576                       offsetof(struct i965_cc_unit_state, cc4),
 577                       render_state->cc.viewport);
 578
 579     dri_bo_unmap(render_state->cc.state);
 580 }
 581
 582
 583 static void
 584 i965_render_cc_unit(VADriverContextP ctx)
 585 {
 586     struct i965_driver_data *i965 = i965_driver_data(ctx);
 587     struct i965_render_state *render_state = &i965->render_state;
 588     struct i965_cc_unit_state *cc_state;
 589
 590     assert(render_state->cc.viewport);
 591
 592     dri_bo_map(render_state->cc.state, 1);
 593     assert(render_state->cc.state->virtual);
 594     cc_state = render_state->cc.state->virtual;
 595     memset(cc_state, 0, sizeof(*cc_state));
 596
 597     cc_state->cc0.stencil_enable = 0;   /* disable stencil */
 598     cc_state->cc2.depth_test = 0;       /* disable depth test */
 599     cc_state->cc2.logicop_enable = 1;   /* enable logic op */
 600     cc_state->cc3.ia_blend_enable = 0;  /* blend alpha just like colors */
 601     cc_state->cc3.blend_enable = 0;     /* disable color blend */
 602     cc_state->cc3.alpha_test = 0;       /* disable alpha test */
 603     cc_state->cc4.cc_viewport_state_offset = render_state->cc.viewport->offset >> 5;
 604
 605     cc_state->cc5.dither_enable = 0;    /* disable dither */
 606     cc_state->cc5.logicop_func = 0xc;   /* WHITE */
 607     cc_state->cc5.statistics_enable = 1;
 608     cc_state->cc5.ia_blend_function = I965_BLENDFUNCTION_ADD;
 609     cc_state->cc5.ia_src_blend_factor = I965_BLENDFACTOR_ONE;
 610     cc_state->cc5.ia_dest_blend_factor = I965_BLENDFACTOR_ONE;
 611
 612     dri_bo_emit_reloc(render_state->cc.state,
 613                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 614                       0,
 615                       offsetof(struct i965_cc_unit_state, cc4),
 616                       render_state->cc.viewport);
 617
 618     dri_bo_unmap(render_state->cc.state);
 619 }
 620
 621 static void
 622 i965_render_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 623 {
 624     switch (tiling) {
 625     case I915_TILING_NONE:
 626         ss->ss3.tiled_surface = 0;
 627         ss->ss3.tile_walk = 0;
 628         break;
 629     case I915_TILING_X:
 630         ss->ss3.tiled_surface = 1;
 631         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 632         break;
 633     case I915_TILING_Y:
 634         ss->ss3.tiled_surface = 1;
 635         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 636         break;
 637     }
 638 }
 639
 640 static void
 641 i965_render_set_surface_state(struct i965_surface_state *ss,
 642                               dri_bo *bo, unsigned long offset,
 643                               int width, int height,
 644                               int pitch, int format)
 645 {
 646     unsigned int tiling;
 647     unsigned int swizzle;
 648
 649     memset(ss, 0, sizeof(*ss));
 650     ss->ss0.surface_type = I965_SURFACE_2D;
 651     ss->ss0.surface_format = format;
 652     ss->ss0.color_blend = 1;
 653
 654     ss->ss1.base_addr = bo->offset + offset;
 655
 656     ss->ss2.width = width - 1;
 657     ss->ss2.height = height - 1;
 658
 659     ss->ss3.pitch = pitch - 1;
 660
 661     dri_bo_get_tiling(bo, &tiling, &swizzle);
 662     i965_render_set_surface_tiling(ss, tiling);
 663 }
 664
 665 static void
 666 gen7_render_set_surface_tiling(struct gen7_surface_state *ss, uint32_t tiling)
 667 {
 668    switch (tiling) {
 669    case I915_TILING_NONE:
 670       ss->ss0.tiled_surface = 0;
 671       ss->ss0.tile_walk = 0;
 672       break;
 673    case I915_TILING_X:
 674       ss->ss0.tiled_surface = 1;
 675       ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 676       break;
 677    case I915_TILING_Y:
 678       ss->ss0.tiled_surface = 1;
 679       ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 680       break;
 681    }
 682 }
 683
 684 static void
 685 gen7_render_set_surface_state(struct gen7_surface_state *ss,
 686                               dri_bo *bo, unsigned long offset,
 687                               int width, int height,
 688                               int pitch, int format)
 689 {
 690     unsigned int tiling;
 691     unsigned int swizzle;
 692
 693     memset(ss, 0, sizeof(*ss));
 694
 695     ss->ss0.surface_type = I965_SURFACE_2D;
 696     ss->ss0.surface_format = format;
 697
 698     ss->ss1.base_addr = bo->offset + offset;
 699
 700     ss->ss2.width = width - 1;
 701     ss->ss2.height = height - 1;
 702
 703     ss->ss3.pitch = pitch - 1;
 704
 705     dri_bo_get_tiling(bo, &tiling, &swizzle);
 706     gen7_render_set_surface_tiling(ss, tiling);
 707 }
 708
 709 static void
 710 i965_render_src_surface_state(VADriverContextP ctx,
 711                               int index,
 712                               dri_bo *region,
 713                               unsigned long offset,
 714                               int w, int h,
 715                               int pitch, int format)
 716 {
 717     struct i965_driver_data *i965 = i965_driver_data(ctx);
 718     struct i965_render_state *render_state = &i965->render_state;
 719     void *ss;
 720     dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
 721
 722     assert(index < MAX_RENDER_SURFACES);
 723
 724     dri_bo_map(ss_bo, 1);
 725     assert(ss_bo->virtual);
 726     ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
 727
 728     if (IS_GEN7(i965->intel.device_id)) {
 729         gen7_render_set_surface_state(ss,
 730                                       region, offset,
 731                                       w, h,
 732                                       pitch, format);
 733         dri_bo_emit_reloc(ss_bo,
 734                           I915_GEM_DOMAIN_SAMPLER, 0,
 735                           offset,
 736                           SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 737                           region);
 738     } else {
 739         i965_render_set_surface_state(ss,
 740                                       region, offset,
 741                                       w, h,
 742                                       pitch, format);
 743         dri_bo_emit_reloc(ss_bo,
 744                           I915_GEM_DOMAIN_SAMPLER, 0,
 745                           offset,
 746                           SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 747                           region);
 748     }
 749
 750     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 751     dri_bo_unmap(ss_bo);
 752     render_state->wm.sampler_count++;
 753 }
 754
 755 static void
 756 i965_render_src_surfaces_state(VADriverContextP ctx,
 757                               VASurfaceID surface)
 758 {
 759     struct i965_driver_data *i965 = i965_driver_data(ctx);
 760     struct object_surface *obj_surface;
 761     int w, h;
 762     int rw, rh;
 763     dri_bo *region;
 764
 765     obj_surface = SURFACE(surface);
 766     assert(obj_surface);
 767
 768     w = obj_surface->width;
 769     h = obj_surface->height;
 770     rw = obj_surface->orig_width;
 771     rh = obj_surface->orig_height;
 772     region = obj_surface->bo;
 773
 774     i965_render_src_surface_state(ctx, 1, region, 0, rw, rh, w, I965_SURFACEFORMAT_R8_UNORM);     /* Y */
 775     i965_render_src_surface_state(ctx, 2, region, 0, rw, rh, w, I965_SURFACEFORMAT_R8_UNORM);
 776
 777     if (obj_surface->fourcc == VA_FOURCC('Y','V','1','2')) {
 778         int u3 = 5, u4 = 6, v5 = 3, v6 = 4;
 779
 780         i965_render_src_surface_state(ctx, u3, region, w * h, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM); /* U */
 781         i965_render_src_surface_state(ctx, u4, region, w * h, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);
 782         i965_render_src_surface_state(ctx, v5, region, w * h + w * h / 4, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);     /* V */
 783         i965_render_src_surface_state(ctx, v6, region, w * h + w * h / 4, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);
 784     } else if (obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '1')) {
 785         int u3 = 5, u4 = 6, v5 = 3, v6 = 4;
 786
 787         i965_render_src_surface_state(ctx, u3, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM); /* U */
 788         i965_render_src_surface_state(ctx, u4, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM);
 789         i965_render_src_surface_state(ctx, v5, region, w * h + w * ALIGN(h / 2, 32), rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM);     /* V */
 790         i965_render_src_surface_state(ctx, v6, region, w * h + w * ALIGN(h / 2, 32), rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM);
 791     } else if (obj_surface->fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
 792         int u3 = 3, u4 = 4, v5 = 5, v6 = 6;
 793
 794         i965_render_src_surface_state(ctx, u3, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM); /* U */
 795         i965_render_src_surface_state(ctx, u4, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM);
 796         i965_render_src_surface_state(ctx, v5, region, w * h + w * ALIGN(h / 2, 32), rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM);     /* V */
 797         i965_render_src_surface_state(ctx, v6, region, w * h + w * ALIGN(h / 2, 32), rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8_UNORM);
 798     } else if (obj_surface->fourcc == VA_FOURCC('N','V','1','2')) {
 799         i965_render_src_surface_state(ctx, 3, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8G8_UNORM); /* UV */
 800         i965_render_src_surface_state(ctx, 4, region, w * h, rw / 2, rh / 2, w, I965_SURFACEFORMAT_R8G8_UNORM);
 801     } else {
 802         int u3 = 3, u4 = 4, v5 = 5, v6 = 6;
 803
 804         i965_render_src_surface_state(ctx, u3, region, w * h, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM); /* U */
 805         i965_render_src_surface_state(ctx, u4, region, w * h, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);
 806         i965_render_src_surface_state(ctx, v5, region, w * h + w * h / 4, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);     /* V */
 807         i965_render_src_surface_state(ctx, v6, region, w * h + w * h / 4, rw / 2, rh / 2, w / 2, I965_SURFACEFORMAT_R8_UNORM);
 808     }
 809 }
 810
 811 static void
 812 i965_subpic_render_src_surfaces_state(VADriverContextP ctx,
 813                               VASurfaceID surface)
 814 {
 815     struct i965_driver_data *i965 = i965_driver_data(ctx);
 816     struct object_surface *obj_surface = SURFACE(surface);
 817     int w, h;
 818     dri_bo *region;
 819     dri_bo *subpic_region;
 820     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
 821     struct object_image *obj_image = IMAGE(obj_subpic->image);
 822     assert(obj_surface);
 823     assert(obj_surface->bo);
 824     w = obj_surface->width;
 825     h = obj_surface->height;
 826     region = obj_surface->bo;
 827     subpic_region = obj_image->bo;
 828     /*subpicture surface*/
 829     i965_render_src_surface_state(ctx, 1, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format);
 830     i965_render_src_surface_state(ctx, 2, subpic_region, 0, obj_subpic->width, obj_subpic->height, obj_subpic->pitch, obj_subpic->format);
 831 }
 832
 833 static void
 834 i965_render_dest_surface_state(VADriverContextP ctx, int index)
 835 {
 836     struct i965_driver_data *i965 = i965_driver_data(ctx);
 837     struct i965_render_state *render_state = &i965->render_state;
 838     struct intel_region *dest_region = render_state->draw_region;
 839     void *ss;
 840     dri_bo *ss_bo = render_state->wm.surface_state_binding_table_bo;
 841     int format;
 842     assert(index < MAX_RENDER_SURFACES);
 843
 844     if (dest_region->cpp == 2) {
 845         format = I965_SURFACEFORMAT_B5G6R5_UNORM;
 846     } else {
 847         format = I965_SURFACEFORMAT_B8G8R8A8_UNORM;
 848     }
 849
 850     dri_bo_map(ss_bo, 1);
 851     assert(ss_bo->virtual);
 852     ss = (char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index);
 853
 854     if (IS_GEN7(i965->intel.device_id)) {
 855         gen7_render_set_surface_state(ss,
 856                                       dest_region->bo, 0,
 857                                       dest_region->width, dest_region->height,
 858                                       dest_region->pitch, format);
 859         dri_bo_emit_reloc(ss_bo,
 860                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 861                           0,
 862                           SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 863                           dest_region->bo);
 864     } else {
 865         i965_render_set_surface_state(ss,
 866                                       dest_region->bo, 0,
 867                                       dest_region->width, dest_region->height,
 868                                       dest_region->pitch, format);
 869         dri_bo_emit_reloc(ss_bo,
 870                           I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 871                           0,
 872                           SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 873                           dest_region->bo);
 874     }
 875
 876     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 877     dri_bo_unmap(ss_bo);
 878 }
 879
 880 static void
 881 i965_subpic_render_upload_vertex(VADriverContextP ctx,
 882                                  VASurfaceID surface,
 883                                  const VARectangle *output_rect)
 884 {
 885     struct i965_driver_data  *i965         = i965_driver_data(ctx);
 886     struct i965_render_state *render_state = &i965->render_state;
 887     struct object_surface    *obj_surface  = SURFACE(surface);
 888     struct object_subpic     *obj_subpic   = SUBPIC(obj_surface->subpic);
 889     VARectangle dst_rect;
 890     float *vb, tx1, tx2, ty1, ty2, x1, x2, y1, y2;
 891     int i = 0;
 892
 893     if (obj_subpic->flags & VA_SUBPICTURE_DESTINATION_IS_SCREEN_COORD)
 894         dst_rect = obj_subpic->dst_rect;
 895     else {
 896         const float sx  = (float)output_rect->width  / obj_surface->orig_width;
 897         const float sy  = (float)output_rect->height / obj_surface->orig_height;
 898         dst_rect.x      = output_rect->x + sx * obj_subpic->dst_rect.x;
 899         dst_rect.y      = output_rect->y + sy * obj_subpic->dst_rect.y;
 900         dst_rect.width  = sx * obj_subpic->dst_rect.width;
 901         dst_rect.height = sy * obj_subpic->dst_rect.height;
 902     }
 903
 904     dri_bo_map(render_state->vb.vertex_buffer, 1);
 905     assert(render_state->vb.vertex_buffer->virtual);
 906     vb = render_state->vb.vertex_buffer->virtual;
 907
 908     tx1 = (float)obj_subpic->src_rect.x / obj_subpic->width;
 909     ty1 = (float)obj_subpic->src_rect.y / obj_subpic->height;
 910     tx2 = (float)(obj_subpic->src_rect.x + obj_subpic->src_rect.width) / obj_subpic->width;
 911     ty2 = (float)(obj_subpic->src_rect.y + obj_subpic->src_rect.height) / obj_subpic->height;
 912
 913     x1 = (float)dst_rect.x;
 914     y1 = (float)dst_rect.y;
 915     x2 = (float)(dst_rect.x + dst_rect.width);
 916     y2 = (float)(dst_rect.y + dst_rect.height);
 917
 918     vb[i++] = tx2;
 919     vb[i++] = ty2;
 920     vb[i++] = x2;
 921     vb[i++] = y2;
 922
 923     vb[i++] = tx1;
 924     vb[i++] = ty2;
 925     vb[i++] = x1;
 926     vb[i++] = y2;
 927
 928     vb[i++] = tx1;
 929     vb[i++] = ty1;
 930     vb[i++] = x1;
 931     vb[i++] = y1;
 932     dri_bo_unmap(render_state->vb.vertex_buffer);
 933 }
 934
 935 static void
 936 i965_render_upload_vertex(
 937     VADriverContextP   ctx,
 938     VASurfaceID        surface,
 939     const VARectangle *src_rect,
 940     const VARectangle *dst_rect
 941 )
 942 {
 943     struct i965_driver_data *i965 = i965_driver_data(ctx);
 944     struct i965_render_state *render_state = &i965->render_state;
 945     struct intel_region *dest_region = render_state->draw_region;
 946     struct object_surface *obj_surface;
 947     float *vb;
 948
 949     float u1, v1, u2, v2;
 950     int i, width, height;
 951     int box_x1 = dest_region->x + dst_rect->x;
 952     int box_y1 = dest_region->y + dst_rect->y;
 953     int box_x2 = box_x1 + dst_rect->width;
 954     int box_y2 = box_y1 + dst_rect->height;
 955
 956     obj_surface = SURFACE(surface);
 957     assert(surface);
 958     width = obj_surface->orig_width;
 959     height = obj_surface->orig_height;
 960
 961     u1 = (float)src_rect->x / width;
 962     v1 = (float)src_rect->y / height;
 963     u2 = (float)(src_rect->x + src_rect->width) / width;
 964     v2 = (float)(src_rect->y + src_rect->height) / height;
 965
 966     dri_bo_map(render_state->vb.vertex_buffer, 1);
 967     assert(render_state->vb.vertex_buffer->virtual);
 968     vb = render_state->vb.vertex_buffer->virtual;
 969
 970     i = 0;
 971     vb[i++] = u2;
 972     vb[i++] = v2;
 973     vb[i++] = (float)box_x2;
 974     vb[i++] = (float)box_y2;
 975
 976     vb[i++] = u1;
 977     vb[i++] = v2;
 978     vb[i++] = (float)box_x1;
 979     vb[i++] = (float)box_y2;
 980
 981     vb[i++] = u1;
 982     vb[i++] = v1;
 983     vb[i++] = (float)box_x1;
 984     vb[i++] = (float)box_y1;
 985
 986     dri_bo_unmap(render_state->vb.vertex_buffer);
 987 }
 988
 989 static void
 990 i965_render_upload_constants(VADriverContextP ctx,
 991                              VASurfaceID surface)
 992 {
 993     struct i965_driver_data *i965 = i965_driver_data(ctx);
 994     struct i965_render_state *render_state = &i965->render_state;
 995     unsigned short *constant_buffer;
 996     struct object_surface *obj_surface = SURFACE(surface);
 997
 998     dri_bo_map(render_state->curbe.bo, 1);
 999     assert(render_state->curbe.bo->virtual);
1000     constant_buffer = render_state->curbe.bo->virtual;
1001
1002     if (obj_surface->fourcc == VA_FOURCC('N','V','1','2'))
1003         *constant_buffer = 1;
1004     else
1005         *constant_buffer = 0;
1006
1007     dri_bo_unmap(render_state->curbe.bo);
1008 }
1009
1010 static void
1011 i965_surface_render_state_setup(
1012     VADriverContextP   ctx,
1013     VASurfaceID        surface,
1014     const VARectangle *src_rect,
1015     const VARectangle *dst_rect
1016 )
1017 {
1018     i965_render_vs_unit(ctx);
1019     i965_render_sf_unit(ctx);
1020     i965_render_dest_surface_state(ctx, 0);
1021     i965_render_src_surfaces_state(ctx, surface);
1022     i965_render_sampler(ctx);
1023     i965_render_wm_unit(ctx);
1024     i965_render_cc_viewport(ctx);
1025     i965_render_cc_unit(ctx);
1026     i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
1027     i965_render_upload_constants(ctx, surface);
1028 }
1029 static void
1030 i965_subpic_render_state_setup(
1031     VADriverContextP   ctx,
1032     VASurfaceID        surface,
1033     const VARectangle *src_rect,
1034     const VARectangle *dst_rect
1035 )
1036 {
1037     i965_render_vs_unit(ctx);
1038     i965_render_sf_unit(ctx);
1039     i965_render_dest_surface_state(ctx, 0);
1040     i965_subpic_render_src_surfaces_state(ctx, surface);
1041     i965_render_sampler(ctx);
1042     i965_subpic_render_wm_unit(ctx);
1043     i965_render_cc_viewport(ctx);
1044     i965_subpic_render_cc_unit(ctx);
1045     i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
1046 }
1047
1048
1049 static void
1050 i965_render_pipeline_select(VADriverContextP ctx)
1051 {
1052     struct i965_driver_data *i965 = i965_driver_data(ctx);
1053     struct intel_batchbuffer *batch = i965->batch;
1054
1055     BEGIN_BATCH(batch, 1);
1056     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1057     ADVANCE_BATCH(batch);
1058 }
1059
1060 static void
1061 i965_render_state_sip(VADriverContextP ctx)
1062 {
1063     struct i965_driver_data *i965 = i965_driver_data(ctx);
1064     struct intel_batchbuffer *batch = i965->batch;
1065
1066     BEGIN_BATCH(batch, 2);
1067     OUT_BATCH(batch, CMD_STATE_SIP | 0);
1068     OUT_BATCH(batch, 0);
1069     ADVANCE_BATCH(batch);
1070 }
1071
1072 static void
1073 i965_render_state_base_address(VADriverContextP ctx)
1074 {
1075     struct i965_driver_data *i965 = i965_driver_data(ctx);
1076     struct intel_batchbuffer *batch = i965->batch;
1077     struct i965_render_state *render_state = &i965->render_state;
1078
1079     if (IS_IRONLAKE(i965->intel.device_id)) {
1080         BEGIN_BATCH(batch, 8);
1081         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1082         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1083         OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1084         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1085         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1086         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1087         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1088         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1089         ADVANCE_BATCH(batch);
1090     } else {
1091         BEGIN_BATCH(batch, 6);
1092         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
1093         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1094         OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1095         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1096         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1097         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1098         ADVANCE_BATCH(batch);
1099     }
1100 }
1101
1102 static void
1103 i965_render_binding_table_pointers(VADriverContextP ctx)
1104 {
1105     struct i965_driver_data *i965 = i965_driver_data(ctx);
1106     struct intel_batchbuffer *batch = i965->batch;
1107
1108     BEGIN_BATCH(batch, 6);
1109     OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS | 4);
1110     OUT_BATCH(batch, 0); /* vs */
1111     OUT_BATCH(batch, 0); /* gs */
1112     OUT_BATCH(batch, 0); /* clip */
1113     OUT_BATCH(batch, 0); /* sf */
1114     OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1115     ADVANCE_BATCH(batch);
1116 }
1117
1118 static void
1119 i965_render_constant_color(VADriverContextP ctx)
1120 {
1121     struct i965_driver_data *i965 = i965_driver_data(ctx);
1122     struct intel_batchbuffer *batch = i965->batch;
1123
1124     BEGIN_BATCH(batch, 5);
1125     OUT_BATCH(batch, CMD_CONSTANT_COLOR | 3);
1126     OUT_BATCH(batch, float_to_uint(1.0));
1127     OUT_BATCH(batch, float_to_uint(0.0));
1128     OUT_BATCH(batch, float_to_uint(1.0));
1129     OUT_BATCH(batch, float_to_uint(1.0));
1130     ADVANCE_BATCH(batch);
1131 }
1132
1133 static void
1134 i965_render_pipelined_pointers(VADriverContextP ctx)
1135 {
1136     struct i965_driver_data *i965 = i965_driver_data(ctx);
1137     struct intel_batchbuffer *batch = i965->batch;
1138     struct i965_render_state *render_state = &i965->render_state;
1139
1140     BEGIN_BATCH(batch, 7);
1141     OUT_BATCH(batch, CMD_PIPELINED_POINTERS | 5);
1142     OUT_RELOC(batch, render_state->vs.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1143     OUT_BATCH(batch, 0);  /* disable GS */
1144     OUT_BATCH(batch, 0);  /* disable CLIP */
1145     OUT_RELOC(batch, render_state->sf.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1146     OUT_RELOC(batch, render_state->wm.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1147     OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1148     ADVANCE_BATCH(batch);
1149 }
1150
1151 static void
1152 i965_render_urb_layout(VADriverContextP ctx)
1153 {
1154     struct i965_driver_data *i965 = i965_driver_data(ctx);
1155     struct intel_batchbuffer *batch = i965->batch;
1156     int urb_vs_start, urb_vs_size;
1157     int urb_gs_start, urb_gs_size;
1158     int urb_clip_start, urb_clip_size;
1159     int urb_sf_start, urb_sf_size;
1160     int urb_cs_start, urb_cs_size;
1161
1162     urb_vs_start = 0;
1163     urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
1164     urb_gs_start = urb_vs_start + urb_vs_size;
1165     urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
1166     urb_clip_start = urb_gs_start + urb_gs_size;
1167     urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
1168     urb_sf_start = urb_clip_start + urb_clip_size;
1169     urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
1170     urb_cs_start = urb_sf_start + urb_sf_size;
1171     urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
1172
1173     BEGIN_BATCH(batch, 3);
1174     OUT_BATCH(batch,
1175               CMD_URB_FENCE |
1176               UF0_CS_REALLOC |
1177               UF0_SF_REALLOC |
1178               UF0_CLIP_REALLOC |
1179               UF0_GS_REALLOC |
1180               UF0_VS_REALLOC |
1181               1);
1182     OUT_BATCH(batch,
1183               ((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1184               ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1185               ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1186     OUT_BATCH(batch,
1187               ((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1188               ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1189     ADVANCE_BATCH(batch);
1190 }
1191
1192 static void
1193 i965_render_cs_urb_layout(VADriverContextP ctx)
1194 {
1195     struct i965_driver_data *i965 = i965_driver_data(ctx);
1196     struct intel_batchbuffer *batch = i965->batch;
1197
1198     BEGIN_BATCH(batch, 2);
1199     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1200     OUT_BATCH(batch,
1201               ((URB_CS_ENTRY_SIZE - 1) << 4) |          /* URB Entry Allocation Size */
1202               (URB_CS_ENTRIES << 0));                /* Number of URB Entries */
1203     ADVANCE_BATCH(batch);
1204 }
1205
1206 static void
1207 i965_render_constant_buffer(VADriverContextP ctx)
1208 {
1209     struct i965_driver_data *i965 = i965_driver_data(ctx);
1210     struct intel_batchbuffer *batch = i965->batch;
1211     struct i965_render_state *render_state = &i965->render_state;
1212
1213     BEGIN_BATCH(batch, 2);
1214     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1215     OUT_RELOC(batch, render_state->curbe.bo,
1216               I915_GEM_DOMAIN_INSTRUCTION, 0,
1217               URB_CS_ENTRY_SIZE - 1);
1218     ADVANCE_BATCH(batch);
1219 }
1220
1221 static void
1222 i965_render_drawing_rectangle(VADriverContextP ctx)
1223 {
1224     struct i965_driver_data *i965 = i965_driver_data(ctx);
1225     struct intel_batchbuffer *batch = i965->batch;
1226     struct i965_render_state *render_state = &i965->render_state;
1227     struct intel_region *dest_region = render_state->draw_region;
1228
1229     BEGIN_BATCH(batch, 4);
1230     OUT_BATCH(batch, CMD_DRAWING_RECTANGLE | 2);
1231     OUT_BATCH(batch, 0x00000000);
1232     OUT_BATCH(batch, (dest_region->width - 1) | (dest_region->height - 1) << 16);
1233     OUT_BATCH(batch, 0x00000000);
1234     ADVANCE_BATCH(batch);
1235 }
1236
1237 static void
1238 i965_render_vertex_elements(VADriverContextP ctx)
1239 {
1240     struct i965_driver_data *i965 = i965_driver_data(ctx);
1241     struct intel_batchbuffer *batch = i965->batch;
1242
1243     if (IS_IRONLAKE(i965->intel.device_id)) {
1244         BEGIN_BATCH(batch, 5);
1245         OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1246         /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1247         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1248                   VE0_VALID |
1249                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1250                   (0 << VE0_OFFSET_SHIFT));
1251         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1252                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1253                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1254                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1255         /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1256         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1257                   VE0_VALID |
1258                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1259                   (8 << VE0_OFFSET_SHIFT));
1260         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1261                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1262                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1263                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1264         ADVANCE_BATCH(batch);
1265     } else {
1266         BEGIN_BATCH(batch, 5);
1267         OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | 3);
1268         /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1269         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1270                   VE0_VALID |
1271                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1272                   (0 << VE0_OFFSET_SHIFT));
1273         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1274                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1275                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1276                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1277                   (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1278         /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1279         OUT_BATCH(batch, (0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1280                   VE0_VALID |
1281                   (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1282                   (8 << VE0_OFFSET_SHIFT));
1283         OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1284                   (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1285                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1286                   (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1287                   (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1288         ADVANCE_BATCH(batch);
1289     }
1290 }
1291
1292 static void
1293 i965_render_upload_image_palette(
1294     VADriverContextP ctx,
1295     VAImageID        image_id,
1296     unsigned int     alpha
1297 )
1298 {
1299     struct i965_driver_data *i965 = i965_driver_data(ctx);
1300     struct intel_batchbuffer *batch = i965->batch;
1301     unsigned int i;
1302
1303     struct object_image *obj_image = IMAGE(image_id);
1304     assert(obj_image);
1305
1306     if (obj_image->image.num_palette_entries == 0)
1307         return;
1308
1309     BEGIN_BATCH(batch, 1 + obj_image->image.num_palette_entries);
1310     OUT_BATCH(batch, CMD_SAMPLER_PALETTE_LOAD | (obj_image->image.num_palette_entries - 1));
1311     /*fill palette*/
1312     //int32_t out[16]; //0-23:color 23-31:alpha
1313     for (i = 0; i < obj_image->image.num_palette_entries; i++)
1314         OUT_BATCH(batch, (alpha << 24) | obj_image->palette[i]);
1315     ADVANCE_BATCH(batch);
1316 }
1317
1318 static void
1319 i965_render_startup(VADriverContextP ctx)
1320 {
1321     struct i965_driver_data *i965 = i965_driver_data(ctx);
1322     struct intel_batchbuffer *batch = i965->batch;
1323     struct i965_render_state *render_state = &i965->render_state;
1324
1325     BEGIN_BATCH(batch, 11);
1326     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
1327     OUT_BATCH(batch,
1328               (0 << VB0_BUFFER_INDEX_SHIFT) |
1329               VB0_VERTEXDATA |
1330               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
1331     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
1332
1333     if (IS_IRONLAKE(i965->intel.device_id))
1334         OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
1335     else
1336         OUT_BATCH(batch, 3);
1337
1338     OUT_BATCH(batch, 0);
1339
1340     OUT_BATCH(batch,
1341               CMD_3DPRIMITIVE |
1342               _3DPRIMITIVE_VERTEX_SEQUENTIAL |
1343               (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
1344               (0 << 9) |
1345               4);
1346     OUT_BATCH(batch, 3); /* vertex count per instance */
1347     OUT_BATCH(batch, 0); /* start vertex offset */
1348     OUT_BATCH(batch, 1); /* single instance */
1349     OUT_BATCH(batch, 0); /* start instance location */
1350     OUT_BATCH(batch, 0); /* index buffer offset, ignored */
1351     ADVANCE_BATCH(batch);
1352 }
1353
1354 static void
1355 i965_clear_dest_region(VADriverContextP ctx)
1356 {
1357     struct i965_driver_data *i965 = i965_driver_data(ctx);
1358     struct intel_batchbuffer *batch = i965->batch;
1359     struct i965_render_state *render_state = &i965->render_state;
1360     struct intel_region *dest_region = render_state->draw_region;
1361     unsigned int blt_cmd, br13;
1362     int pitch;
1363
1364     blt_cmd = XY_COLOR_BLT_CMD;
1365     br13 = 0xf0 << 16;
1366     pitch = dest_region->pitch;
1367
1368     if (dest_region->cpp == 4) {
1369         br13 |= BR13_8888;
1370         blt_cmd |= (XY_COLOR_BLT_WRITE_RGB | XY_COLOR_BLT_WRITE_ALPHA);
1371     } else {
1372         assert(dest_region->cpp == 2);
1373         br13 |= BR13_565;
1374     }
1375
1376     if (dest_region->tiling != I915_TILING_NONE) {
1377         blt_cmd |= XY_COLOR_BLT_DST_TILED;
1378         pitch /= 4;
1379     }
1380
1381     br13 |= pitch;
1382
1383     if (IS_GEN6(i965->intel.device_id) ||
1384         IS_GEN7(i965->intel.device_id)) {
1385         intel_batchbuffer_start_atomic_blt(batch, 24);
1386         BEGIN_BLT_BATCH(batch, 6);
1387     } else {
1388         intel_batchbuffer_start_atomic(batch, 24);
1389         BEGIN_BATCH(batch, 6);
1390     }
1391
1392     OUT_BATCH(batch, blt_cmd);
1393     OUT_BATCH(batch, br13);
1394     OUT_BATCH(batch, (dest_region->y << 16) | (dest_region->x));
1395     OUT_BATCH(batch, ((dest_region->y + dest_region->height) << 16) |
1396               (dest_region->x + dest_region->width));
1397     OUT_RELOC(batch, dest_region->bo,
1398               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
1399               0);
1400     OUT_BATCH(batch, 0x0);
1401     ADVANCE_BATCH(batch);
1402     intel_batchbuffer_end_atomic(batch);
1403 }
1404
1405 static void
1406 i965_surface_render_pipeline_setup(VADriverContextP ctx)
1407 {
1408     struct i965_driver_data *i965 = i965_driver_data(ctx);
1409     struct intel_batchbuffer *batch = i965->batch;
1410
1411     i965_clear_dest_region(ctx);
1412     intel_batchbuffer_start_atomic(batch, 0x1000);
1413     intel_batchbuffer_emit_mi_flush(batch);
1414     i965_render_pipeline_select(ctx);
1415     i965_render_state_sip(ctx);
1416     i965_render_state_base_address(ctx);
1417     i965_render_binding_table_pointers(ctx);
1418     i965_render_constant_color(ctx);
1419     i965_render_pipelined_pointers(ctx);
1420     i965_render_urb_layout(ctx);
1421     i965_render_cs_urb_layout(ctx);
1422     i965_render_constant_buffer(ctx);
1423     i965_render_drawing_rectangle(ctx);
1424     i965_render_vertex_elements(ctx);
1425     i965_render_startup(ctx);
1426     intel_batchbuffer_end_atomic(batch);
1427 }
1428
1429 static void
1430 i965_subpic_render_pipeline_setup(VADriverContextP ctx)
1431 {
1432     struct i965_driver_data *i965 = i965_driver_data(ctx);
1433     struct intel_batchbuffer *batch = i965->batch;
1434
1435     intel_batchbuffer_start_atomic(batch, 0x1000);
1436     intel_batchbuffer_emit_mi_flush(batch);
1437     i965_render_pipeline_select(ctx);
1438     i965_render_state_sip(ctx);
1439     i965_render_state_base_address(ctx);
1440     i965_render_binding_table_pointers(ctx);
1441     i965_render_constant_color(ctx);
1442     i965_render_pipelined_pointers(ctx);
1443     i965_render_urb_layout(ctx);
1444     i965_render_cs_urb_layout(ctx);
1445     i965_render_drawing_rectangle(ctx);
1446     i965_render_vertex_elements(ctx);
1447     i965_render_startup(ctx);
1448     intel_batchbuffer_end_atomic(batch);
1449 }
1450
1451
1452 static void
1453 i965_render_initialize(VADriverContextP ctx)
1454 {
1455     struct i965_driver_data *i965 = i965_driver_data(ctx);
1456     struct i965_render_state *render_state = &i965->render_state;
1457     dri_bo *bo;
1458
1459     /* VERTEX BUFFER */
1460     dri_bo_unreference(render_state->vb.vertex_buffer);
1461     bo = dri_bo_alloc(i965->intel.bufmgr,
1462                       "vertex buffer",
1463                       4096,
1464                       4096);
1465     assert(bo);
1466     render_state->vb.vertex_buffer = bo;
1467
1468     /* VS */
1469     dri_bo_unreference(render_state->vs.state);
1470     bo = dri_bo_alloc(i965->intel.bufmgr,
1471                       "vs state",
1472                       sizeof(struct i965_vs_unit_state),
1473                       64);
1474     assert(bo);
1475     render_state->vs.state = bo;
1476
1477     /* GS */
1478     /* CLIP */
1479     /* SF */
1480     dri_bo_unreference(render_state->sf.state);
1481     bo = dri_bo_alloc(i965->intel.bufmgr,
1482                       "sf state",
1483                       sizeof(struct i965_sf_unit_state),
1484                       64);
1485     assert(bo);
1486     render_state->sf.state = bo;
1487
1488     /* WM */
1489     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1490     bo = dri_bo_alloc(i965->intel.bufmgr,
1491                       "surface state & binding table",
1492                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1493                       4096);
1494     assert(bo);
1495     render_state->wm.surface_state_binding_table_bo = bo;
1496
1497     dri_bo_unreference(render_state->wm.sampler);
1498     bo = dri_bo_alloc(i965->intel.bufmgr,
1499                       "sampler state",
1500                       MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1501                       64);
1502     assert(bo);
1503     render_state->wm.sampler = bo;
1504     render_state->wm.sampler_count = 0;
1505
1506     dri_bo_unreference(render_state->wm.state);
1507     bo = dri_bo_alloc(i965->intel.bufmgr,
1508                       "wm state",
1509                       sizeof(struct i965_wm_unit_state),
1510                       64);
1511     assert(bo);
1512     render_state->wm.state = bo;
1513
1514     /* COLOR CALCULATOR */
1515     dri_bo_unreference(render_state->cc.state);
1516     bo = dri_bo_alloc(i965->intel.bufmgr,
1517                       "color calc state",
1518                       sizeof(struct i965_cc_unit_state),
1519                       64);
1520     assert(bo);
1521     render_state->cc.state = bo;
1522
1523     dri_bo_unreference(render_state->cc.viewport);
1524     bo = dri_bo_alloc(i965->intel.bufmgr,
1525                       "cc viewport",
1526                       sizeof(struct i965_cc_viewport),
1527                       64);
1528     assert(bo);
1529     render_state->cc.viewport = bo;
1530 }
1531
1532 static void
1533 i965_render_put_surface(
1534     VADriverContextP   ctx,
1535     VASurfaceID        surface,
1536     const VARectangle *src_rect,
1537     const VARectangle *dst_rect,
1538     unsigned int       flags
1539 )
1540 {
1541     struct i965_driver_data *i965 = i965_driver_data(ctx);
1542     struct intel_batchbuffer *batch = i965->batch;
1543
1544     i965_render_initialize(ctx);
1545     i965_surface_render_state_setup(ctx, surface, src_rect, dst_rect);
1546     i965_surface_render_pipeline_setup(ctx);
1547     intel_batchbuffer_flush(batch);
1548 }
1549
1550 static void
1551 i965_render_put_subpicture(
1552     VADriverContextP   ctx,
1553     VASurfaceID        surface,
1554     const VARectangle *src_rect,
1555     const VARectangle *dst_rect
1556 )
1557 {
1558     struct i965_driver_data *i965 = i965_driver_data(ctx);
1559     struct intel_batchbuffer *batch = i965->batch;
1560     struct object_surface *obj_surface = SURFACE(surface);
1561     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
1562
1563     assert(obj_subpic);
1564
1565     i965_render_initialize(ctx);
1566     i965_subpic_render_state_setup(ctx, surface, src_rect, dst_rect);
1567     i965_subpic_render_pipeline_setup(ctx);
1568     i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
1569     intel_batchbuffer_flush(batch);
1570 }
1571
1572 /*
1573  * for GEN6+
1574  */
1575 static void
1576 gen6_render_initialize(VADriverContextP ctx)
1577 {
1578     struct i965_driver_data *i965 = i965_driver_data(ctx);
1579     struct i965_render_state *render_state = &i965->render_state;
1580     dri_bo *bo;
1581
1582     /* VERTEX BUFFER */
1583     dri_bo_unreference(render_state->vb.vertex_buffer);
1584     bo = dri_bo_alloc(i965->intel.bufmgr,
1585                       "vertex buffer",
1586                       4096,
1587                       4096);
1588     assert(bo);
1589     render_state->vb.vertex_buffer = bo;
1590
1591     /* WM */
1592     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
1593     bo = dri_bo_alloc(i965->intel.bufmgr,
1594                       "surface state & binding table",
1595                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
1596                       4096);
1597     assert(bo);
1598     render_state->wm.surface_state_binding_table_bo = bo;
1599
1600     dri_bo_unreference(render_state->wm.sampler);
1601     bo = dri_bo_alloc(i965->intel.bufmgr,
1602                       "sampler state",
1603                       MAX_SAMPLERS * sizeof(struct i965_sampler_state),
1604                       4096);
1605     assert(bo);
1606     render_state->wm.sampler = bo;
1607     render_state->wm.sampler_count = 0;
1608
1609     /* COLOR CALCULATOR */
1610     dri_bo_unreference(render_state->cc.state);
1611     bo = dri_bo_alloc(i965->intel.bufmgr,
1612                       "color calc state",
1613                       sizeof(struct gen6_color_calc_state),
1614                       4096);
1615     assert(bo);
1616     render_state->cc.state = bo;
1617
1618     /* CC VIEWPORT */
1619     dri_bo_unreference(render_state->cc.viewport);
1620     bo = dri_bo_alloc(i965->intel.bufmgr,
1621                       "cc viewport",
1622                       sizeof(struct i965_cc_viewport),
1623                       4096);
1624     assert(bo);
1625     render_state->cc.viewport = bo;
1626
1627     /* BLEND STATE */
1628     dri_bo_unreference(render_state->cc.blend);
1629     bo = dri_bo_alloc(i965->intel.bufmgr,
1630                       "blend state",
1631                       sizeof(struct gen6_blend_state),
1632                       4096);
1633     assert(bo);
1634     render_state->cc.blend = bo;
1635
1636     /* DEPTH & STENCIL STATE */
1637     dri_bo_unreference(render_state->cc.depth_stencil);
1638     bo = dri_bo_alloc(i965->intel.bufmgr,
1639                       "depth & stencil state",
1640                       sizeof(struct gen6_depth_stencil_state),
1641                       4096);
1642     assert(bo);
1643     render_state->cc.depth_stencil = bo;
1644 }
1645
1646 static void
1647 gen6_render_color_calc_state(VADriverContextP ctx)
1648 {
1649     struct i965_driver_data *i965 = i965_driver_data(ctx);
1650     struct i965_render_state *render_state = &i965->render_state;
1651     struct gen6_color_calc_state *color_calc_state;
1652
1653     dri_bo_map(render_state->cc.state, 1);
1654     assert(render_state->cc.state->virtual);
1655     color_calc_state = render_state->cc.state->virtual;
1656     memset(color_calc_state, 0, sizeof(*color_calc_state));
1657     color_calc_state->constant_r = 1.0;
1658     color_calc_state->constant_g = 0.0;
1659     color_calc_state->constant_b = 1.0;
1660     color_calc_state->constant_a = 1.0;
1661     dri_bo_unmap(render_state->cc.state);
1662 }
1663
1664 static void
1665 gen6_render_blend_state(VADriverContextP ctx)
1666 {
1667     struct i965_driver_data *i965 = i965_driver_data(ctx);
1668     struct i965_render_state *render_state = &i965->render_state;
1669     struct gen6_blend_state *blend_state;
1670
1671     dri_bo_map(render_state->cc.blend, 1);
1672     assert(render_state->cc.blend->virtual);
1673     blend_state = render_state->cc.blend->virtual;
1674     memset(blend_state, 0, sizeof(*blend_state));
1675     blend_state->blend1.logic_op_enable = 1;
1676     blend_state->blend1.logic_op_func = 0xc;
1677     dri_bo_unmap(render_state->cc.blend);
1678 }
1679
1680 static void
1681 gen6_render_depth_stencil_state(VADriverContextP ctx)
1682 {
1683     struct i965_driver_data *i965 = i965_driver_data(ctx);
1684     struct i965_render_state *render_state = &i965->render_state;
1685     struct gen6_depth_stencil_state *depth_stencil_state;
1686
1687     dri_bo_map(render_state->cc.depth_stencil, 1);
1688     assert(render_state->cc.depth_stencil->virtual);
1689     depth_stencil_state = render_state->cc.depth_stencil->virtual;
1690     memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
1691     dri_bo_unmap(render_state->cc.depth_stencil);
1692 }
1693
1694 static void
1695 gen6_render_setup_states(
1696     VADriverContextP   ctx,
1697     VASurfaceID        surface,
1698     const VARectangle *src_rect,
1699     const VARectangle *dst_rect
1700 )
1701 {
1702     i965_render_dest_surface_state(ctx, 0);
1703     i965_render_src_surfaces_state(ctx, surface);
1704     i965_render_sampler(ctx);
1705     i965_render_cc_viewport(ctx);
1706     gen6_render_color_calc_state(ctx);
1707     gen6_render_blend_state(ctx);
1708     gen6_render_depth_stencil_state(ctx);
1709     i965_render_upload_constants(ctx, surface);
1710     i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
1711 }
1712
1713 static void
1714 gen6_emit_invarient_states(VADriverContextP ctx)
1715 {
1716     struct i965_driver_data *i965 = i965_driver_data(ctx);
1717     struct intel_batchbuffer *batch = i965->batch;
1718
1719     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1720
1721     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
1722     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
1723               GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
1724     OUT_BATCH(batch, 0);
1725
1726     OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
1727     OUT_BATCH(batch, 1);
1728
1729     /* Set system instruction pointer */
1730     OUT_BATCH(batch, CMD_STATE_SIP | 0);
1731     OUT_BATCH(batch, 0);
1732 }
1733
1734 static void
1735 gen6_emit_state_base_address(VADriverContextP ctx)
1736 {
1737     struct i965_driver_data *i965 = i965_driver_data(ctx);
1738     struct intel_batchbuffer *batch = i965->batch;
1739     struct i965_render_state *render_state = &i965->render_state;
1740
1741     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
1742     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
1743     OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
1744     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
1745     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
1746     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
1747     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
1748     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
1749     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
1750     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
1751 }
1752
1753 static void
1754 gen6_emit_viewport_state_pointers(VADriverContextP ctx)
1755 {
1756     struct i965_driver_data *i965 = i965_driver_data(ctx);
1757     struct intel_batchbuffer *batch = i965->batch;
1758     struct i965_render_state *render_state = &i965->render_state;
1759
1760     OUT_BATCH(batch, GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
1761               GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
1762               (4 - 2));
1763     OUT_BATCH(batch, 0);
1764     OUT_BATCH(batch, 0);
1765     OUT_RELOC(batch, render_state->cc.viewport, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1766 }
1767
1768 static void
1769 gen6_emit_urb(VADriverContextP ctx)
1770 {
1771     struct i965_driver_data *i965 = i965_driver_data(ctx);
1772     struct intel_batchbuffer *batch = i965->batch;
1773
1774     OUT_BATCH(batch, GEN6_3DSTATE_URB | (3 - 2));
1775     OUT_BATCH(batch, ((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
1776               (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
1777     OUT_BATCH(batch, (0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
1778               (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
1779 }
1780
1781 static void
1782 gen6_emit_cc_state_pointers(VADriverContextP ctx)
1783 {
1784     struct i965_driver_data *i965 = i965_driver_data(ctx);
1785     struct intel_batchbuffer *batch = i965->batch;
1786     struct i965_render_state *render_state = &i965->render_state;
1787
1788     OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
1789     OUT_RELOC(batch, render_state->cc.blend, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1790     OUT_RELOC(batch, render_state->cc.depth_stencil, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1791     OUT_RELOC(batch, render_state->cc.state, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
1792 }
1793
1794 static void
1795 gen6_emit_sampler_state_pointers(VADriverContextP ctx)
1796 {
1797     struct i965_driver_data *i965 = i965_driver_data(ctx);
1798     struct intel_batchbuffer *batch = i965->batch;
1799     struct i965_render_state *render_state = &i965->render_state;
1800
1801     OUT_BATCH(batch, GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
1802               GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
1803               (4 - 2));
1804     OUT_BATCH(batch, 0); /* VS */
1805     OUT_BATCH(batch, 0); /* GS */
1806     OUT_RELOC(batch,render_state->wm.sampler, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1807 }
1808
1809 static void
1810 gen6_emit_binding_table(VADriverContextP ctx)
1811 {
1812     struct i965_driver_data *i965 = i965_driver_data(ctx);
1813     struct intel_batchbuffer *batch = i965->batch;
1814
1815     /* Binding table pointers */
1816     OUT_BATCH(batch, CMD_BINDING_TABLE_POINTERS |
1817               GEN6_BINDING_TABLE_MODIFY_PS |
1818               (4 - 2));
1819     OUT_BATCH(batch, 0);                /* vs */
1820     OUT_BATCH(batch, 0);                /* gs */
1821     /* Only the PS uses the binding table */
1822     OUT_BATCH(batch, BINDING_TABLE_OFFSET);
1823 }
1824
1825 static void
1826 gen6_emit_depth_buffer_state(VADriverContextP ctx)
1827 {
1828     struct i965_driver_data *i965 = i965_driver_data(ctx);
1829     struct intel_batchbuffer *batch = i965->batch;
1830
1831     OUT_BATCH(batch, CMD_DEPTH_BUFFER | (7 - 2));
1832     OUT_BATCH(batch, (I965_SURFACE_NULL << CMD_DEPTH_BUFFER_TYPE_SHIFT) |
1833               (I965_DEPTHFORMAT_D32_FLOAT << CMD_DEPTH_BUFFER_FORMAT_SHIFT));
1834     OUT_BATCH(batch, 0);
1835     OUT_BATCH(batch, 0);
1836     OUT_BATCH(batch, 0);
1837     OUT_BATCH(batch, 0);
1838     OUT_BATCH(batch, 0);
1839
1840     OUT_BATCH(batch, CMD_CLEAR_PARAMS | (2 - 2));
1841     OUT_BATCH(batch, 0);
1842 }
1843
1844 static void
1845 gen6_emit_drawing_rectangle(VADriverContextP ctx)
1846 {
1847     i965_render_drawing_rectangle(ctx);
1848 }
1849
1850 static void
1851 gen6_emit_vs_state(VADriverContextP ctx)
1852 {
1853     struct i965_driver_data *i965 = i965_driver_data(ctx);
1854     struct intel_batchbuffer *batch = i965->batch;
1855
1856     /* disable VS constant buffer */
1857     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
1858     OUT_BATCH(batch, 0);
1859     OUT_BATCH(batch, 0);
1860     OUT_BATCH(batch, 0);
1861     OUT_BATCH(batch, 0);
1862
1863     OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
1864     OUT_BATCH(batch, 0); /* without VS kernel */
1865     OUT_BATCH(batch, 0);
1866     OUT_BATCH(batch, 0);
1867     OUT_BATCH(batch, 0);
1868     OUT_BATCH(batch, 0); /* pass-through */
1869 }
1870
1871 static void
1872 gen6_emit_gs_state(VADriverContextP ctx)
1873 {
1874     struct i965_driver_data *i965 = i965_driver_data(ctx);
1875     struct intel_batchbuffer *batch = i965->batch;
1876
1877     /* disable GS constant buffer */
1878     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
1879     OUT_BATCH(batch, 0);
1880     OUT_BATCH(batch, 0);
1881     OUT_BATCH(batch, 0);
1882     OUT_BATCH(batch, 0);
1883
1884     OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
1885     OUT_BATCH(batch, 0); /* without GS kernel */
1886     OUT_BATCH(batch, 0);
1887     OUT_BATCH(batch, 0);
1888     OUT_BATCH(batch, 0);
1889     OUT_BATCH(batch, 0);
1890     OUT_BATCH(batch, 0); /* pass-through */
1891 }
1892
1893 static void
1894 gen6_emit_clip_state(VADriverContextP ctx)
1895 {
1896     struct i965_driver_data *i965 = i965_driver_data(ctx);
1897     struct intel_batchbuffer *batch = i965->batch;
1898
1899     OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
1900     OUT_BATCH(batch, 0);
1901     OUT_BATCH(batch, 0); /* pass-through */
1902     OUT_BATCH(batch, 0);
1903 }
1904
1905 static void
1906 gen6_emit_sf_state(VADriverContextP ctx)
1907 {
1908     struct i965_driver_data *i965 = i965_driver_data(ctx);
1909     struct intel_batchbuffer *batch = i965->batch;
1910
1911     OUT_BATCH(batch, GEN6_3DSTATE_SF | (20 - 2));
1912     OUT_BATCH(batch, (1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
1913               (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
1914               (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
1915     OUT_BATCH(batch, 0);
1916     OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
1917     OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
1918     OUT_BATCH(batch, 0);
1919     OUT_BATCH(batch, 0);
1920     OUT_BATCH(batch, 0);
1921     OUT_BATCH(batch, 0);
1922     OUT_BATCH(batch, 0); /* DW9 */
1923     OUT_BATCH(batch, 0);
1924     OUT_BATCH(batch, 0);
1925     OUT_BATCH(batch, 0);
1926     OUT_BATCH(batch, 0);
1927     OUT_BATCH(batch, 0); /* DW14 */
1928     OUT_BATCH(batch, 0);
1929     OUT_BATCH(batch, 0);
1930     OUT_BATCH(batch, 0);
1931     OUT_BATCH(batch, 0);
1932     OUT_BATCH(batch, 0); /* DW19 */
1933 }
1934
1935 static void
1936 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
1937 {
1938     struct i965_driver_data *i965 = i965_driver_data(ctx);
1939     struct intel_batchbuffer *batch = i965->batch;
1940     struct i965_render_state *render_state = &i965->render_state;
1941
1942     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS |
1943               GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
1944               (5 - 2));
1945     OUT_RELOC(batch,
1946               render_state->curbe.bo,
1947               I915_GEM_DOMAIN_INSTRUCTION, 0,
1948               0);
1949     OUT_BATCH(batch, 0);
1950     OUT_BATCH(batch, 0);
1951     OUT_BATCH(batch, 0);
1952
1953     OUT_BATCH(batch, GEN6_3DSTATE_WM | (9 - 2));
1954     OUT_RELOC(batch, render_state->render_kernels[kernel].bo,
1955               I915_GEM_DOMAIN_INSTRUCTION, 0,
1956               0);
1957     OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) |
1958               (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT));
1959     OUT_BATCH(batch, 0);
1960     OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
1961     OUT_BATCH(batch, ((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
1962               GEN6_3DSTATE_WM_DISPATCH_ENABLE |
1963               GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
1964     OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
1965               GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
1966     OUT_BATCH(batch, 0);
1967     OUT_BATCH(batch, 0);
1968 }
1969
1970 static void
1971 gen6_emit_vertex_element_state(VADriverContextP ctx)
1972 {
1973     struct i965_driver_data *i965 = i965_driver_data(ctx);
1974     struct intel_batchbuffer *batch = i965->batch;
1975
1976     /* Set up our vertex elements, sourced from the single vertex buffer. */
1977     OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
1978     /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
1979     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1980               GEN6_VE0_VALID |
1981               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1982               (0 << VE0_OFFSET_SHIFT));
1983     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1984               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1985               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1986               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1987     /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
1988     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1989               GEN6_VE0_VALID |
1990               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1991               (8 << VE0_OFFSET_SHIFT));
1992     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1993               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1994               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1995               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1996 }
1997
1998 static void
1999 gen6_emit_vertices(VADriverContextP ctx)
2000 {
2001     struct i965_driver_data *i965 = i965_driver_data(ctx);
2002     struct intel_batchbuffer *batch = i965->batch;
2003     struct i965_render_state *render_state = &i965->render_state;
2004
2005     BEGIN_BATCH(batch, 11);
2006     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | 3);
2007     OUT_BATCH(batch,
2008               (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2009               GEN6_VB0_VERTEXDATA |
2010               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2011     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2012     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2013     OUT_BATCH(batch, 0);
2014
2015     OUT_BATCH(batch,
2016               CMD_3DPRIMITIVE |
2017               _3DPRIMITIVE_VERTEX_SEQUENTIAL |
2018               (_3DPRIM_RECTLIST << _3DPRIMITIVE_TOPOLOGY_SHIFT) |
2019               (0 << 9) |
2020               4);
2021     OUT_BATCH(batch, 3); /* vertex count per instance */
2022     OUT_BATCH(batch, 0); /* start vertex offset */
2023     OUT_BATCH(batch, 1); /* single instance */
2024     OUT_BATCH(batch, 0); /* start instance location */
2025     OUT_BATCH(batch, 0); /* index buffer offset, ignored */
2026     ADVANCE_BATCH(batch);
2027 }
2028
2029 static void
2030 gen6_render_emit_states(VADriverContextP ctx, int kernel)
2031 {
2032     struct i965_driver_data *i965 = i965_driver_data(ctx);
2033     struct intel_batchbuffer *batch = i965->batch;
2034
2035     intel_batchbuffer_start_atomic(batch, 0x1000);
2036     intel_batchbuffer_emit_mi_flush(batch);
2037     gen6_emit_invarient_states(ctx);
2038     gen6_emit_state_base_address(ctx);
2039     gen6_emit_viewport_state_pointers(ctx);
2040     gen6_emit_urb(ctx);
2041     gen6_emit_cc_state_pointers(ctx);
2042     gen6_emit_sampler_state_pointers(ctx);
2043     gen6_emit_vs_state(ctx);
2044     gen6_emit_gs_state(ctx);
2045     gen6_emit_clip_state(ctx);
2046     gen6_emit_sf_state(ctx);
2047     gen6_emit_wm_state(ctx, kernel);
2048     gen6_emit_binding_table(ctx);
2049     gen6_emit_depth_buffer_state(ctx);
2050     gen6_emit_drawing_rectangle(ctx);
2051     gen6_emit_vertex_element_state(ctx);
2052     gen6_emit_vertices(ctx);
2053     intel_batchbuffer_end_atomic(batch);
2054 }
2055
2056 static void
2057 gen6_render_put_surface(
2058     VADriverContextP   ctx,
2059     VASurfaceID        surface,
2060     const VARectangle *src_rect,
2061     const VARectangle *dst_rect,
2062     unsigned int       flags
2063 )
2064 {
2065     struct i965_driver_data *i965 = i965_driver_data(ctx);
2066     struct intel_batchbuffer *batch = i965->batch;
2067
2068     gen6_render_initialize(ctx);
2069     gen6_render_setup_states(ctx, surface, src_rect, dst_rect);
2070     i965_clear_dest_region(ctx);
2071     gen6_render_emit_states(ctx, PS_KERNEL);
2072     intel_batchbuffer_flush(batch);
2073 }
2074
2075 static void
2076 gen6_subpicture_render_blend_state(VADriverContextP ctx)
2077 {
2078     struct i965_driver_data *i965 = i965_driver_data(ctx);
2079     struct i965_render_state *render_state = &i965->render_state;
2080     struct gen6_blend_state *blend_state;
2081
2082     dri_bo_unmap(render_state->cc.state);
2083     dri_bo_map(render_state->cc.blend, 1);
2084     assert(render_state->cc.blend->virtual);
2085     blend_state = render_state->cc.blend->virtual;
2086     memset(blend_state, 0, sizeof(*blend_state));
2087     blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2088     blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2089     blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2090     blend_state->blend0.blend_enable = 1;
2091     blend_state->blend1.post_blend_clamp_enable = 1;
2092     blend_state->blend1.pre_blend_clamp_enable = 1;
2093     blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2094     dri_bo_unmap(render_state->cc.blend);
2095 }
2096
2097 static void
2098 gen6_subpicture_render_setup_states(
2099     VADriverContextP   ctx,
2100     VASurfaceID        surface,
2101     const VARectangle *src_rect,
2102     const VARectangle *dst_rect
2103 )
2104 {
2105     i965_render_dest_surface_state(ctx, 0);
2106     i965_subpic_render_src_surfaces_state(ctx, surface);
2107     i965_render_sampler(ctx);
2108     i965_render_cc_viewport(ctx);
2109     gen6_render_color_calc_state(ctx);
2110     gen6_subpicture_render_blend_state(ctx);
2111     gen6_render_depth_stencil_state(ctx);
2112     i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
2113 }
2114
2115 static void
2116 gen6_render_put_subpicture(
2117     VADriverContextP   ctx,
2118     VASurfaceID        surface,
2119     const VARectangle *src_rect,
2120     const VARectangle *dst_rect
2121 )
2122 {
2123     struct i965_driver_data *i965 = i965_driver_data(ctx);
2124     struct intel_batchbuffer *batch = i965->batch;
2125     struct object_surface *obj_surface = SURFACE(surface);
2126     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
2127
2128     assert(obj_subpic);
2129     gen6_render_initialize(ctx);
2130     gen6_subpicture_render_setup_states(ctx, surface, src_rect, dst_rect);
2131     gen6_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2132     i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
2133     intel_batchbuffer_flush(batch);
2134 }
2135
2136 /*
2137  * for GEN7
2138  */
2139 static void
2140 gen7_render_initialize(VADriverContextP ctx)
2141 {
2142     struct i965_driver_data *i965 = i965_driver_data(ctx);
2143     struct i965_render_state *render_state = &i965->render_state;
2144     dri_bo *bo;
2145
2146     /* VERTEX BUFFER */
2147     dri_bo_unreference(render_state->vb.vertex_buffer);
2148     bo = dri_bo_alloc(i965->intel.bufmgr,
2149                       "vertex buffer",
2150                       4096,
2151                       4096);
2152     assert(bo);
2153     render_state->vb.vertex_buffer = bo;
2154
2155     /* WM */
2156     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
2157     bo = dri_bo_alloc(i965->intel.bufmgr,
2158                       "surface state & binding table",
2159                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_RENDER_SURFACES,
2160                       4096);
2161     assert(bo);
2162     render_state->wm.surface_state_binding_table_bo = bo;
2163
2164     dri_bo_unreference(render_state->wm.sampler);
2165     bo = dri_bo_alloc(i965->intel.bufmgr,
2166                       "sampler state",
2167                       MAX_SAMPLERS * sizeof(struct gen7_sampler_state),
2168                       4096);
2169     assert(bo);
2170     render_state->wm.sampler = bo;
2171     render_state->wm.sampler_count = 0;
2172
2173     /* COLOR CALCULATOR */
2174     dri_bo_unreference(render_state->cc.state);
2175     bo = dri_bo_alloc(i965->intel.bufmgr,
2176                       "color calc state",
2177                       sizeof(struct gen6_color_calc_state),
2178                       4096);
2179     assert(bo);
2180     render_state->cc.state = bo;
2181
2182     /* CC VIEWPORT */
2183     dri_bo_unreference(render_state->cc.viewport);
2184     bo = dri_bo_alloc(i965->intel.bufmgr,
2185                       "cc viewport",
2186                       sizeof(struct i965_cc_viewport),
2187                       4096);
2188     assert(bo);
2189     render_state->cc.viewport = bo;
2190
2191     /* BLEND STATE */
2192     dri_bo_unreference(render_state->cc.blend);
2193     bo = dri_bo_alloc(i965->intel.bufmgr,
2194                       "blend state",
2195                       sizeof(struct gen6_blend_state),
2196                       4096);
2197     assert(bo);
2198     render_state->cc.blend = bo;
2199
2200     /* DEPTH & STENCIL STATE */
2201     dri_bo_unreference(render_state->cc.depth_stencil);
2202     bo = dri_bo_alloc(i965->intel.bufmgr,
2203                       "depth & stencil state",
2204                       sizeof(struct gen6_depth_stencil_state),
2205                       4096);
2206     assert(bo);
2207     render_state->cc.depth_stencil = bo;
2208 }
2209
2210 static void
2211 gen7_render_color_calc_state(VADriverContextP ctx)
2212 {
2213     struct i965_driver_data *i965 = i965_driver_data(ctx);
2214     struct i965_render_state *render_state = &i965->render_state;
2215     struct gen6_color_calc_state *color_calc_state;
2216
2217     dri_bo_map(render_state->cc.state, 1);
2218     assert(render_state->cc.state->virtual);
2219     color_calc_state = render_state->cc.state->virtual;
2220     memset(color_calc_state, 0, sizeof(*color_calc_state));
2221     color_calc_state->constant_r = 1.0;
2222     color_calc_state->constant_g = 0.0;
2223     color_calc_state->constant_b = 1.0;
2224     color_calc_state->constant_a = 1.0;
2225     dri_bo_unmap(render_state->cc.state);
2226 }
2227
2228 static void
2229 gen7_render_blend_state(VADriverContextP ctx)
2230 {
2231     struct i965_driver_data *i965 = i965_driver_data(ctx);
2232     struct i965_render_state *render_state = &i965->render_state;
2233     struct gen6_blend_state *blend_state;
2234
2235     dri_bo_map(render_state->cc.blend, 1);
2236     assert(render_state->cc.blend->virtual);
2237     blend_state = render_state->cc.blend->virtual;
2238     memset(blend_state, 0, sizeof(*blend_state));
2239     blend_state->blend1.logic_op_enable = 1;
2240     blend_state->blend1.logic_op_func = 0xc;
2241     blend_state->blend1.pre_blend_clamp_enable = 1;
2242     dri_bo_unmap(render_state->cc.blend);
2243 }
2244
2245 static void
2246 gen7_render_depth_stencil_state(VADriverContextP ctx)
2247 {
2248     struct i965_driver_data *i965 = i965_driver_data(ctx);
2249     struct i965_render_state *render_state = &i965->render_state;
2250     struct gen6_depth_stencil_state *depth_stencil_state;
2251
2252     dri_bo_map(render_state->cc.depth_stencil, 1);
2253     assert(render_state->cc.depth_stencil->virtual);
2254     depth_stencil_state = render_state->cc.depth_stencil->virtual;
2255     memset(depth_stencil_state, 0, sizeof(*depth_stencil_state));
2256     dri_bo_unmap(render_state->cc.depth_stencil);
2257 }
2258
2259 static void
2260 gen7_render_sampler(VADriverContextP ctx)
2261 {
2262     struct i965_driver_data *i965 = i965_driver_data(ctx);
2263     struct i965_render_state *render_state = &i965->render_state;
2264     struct gen7_sampler_state *sampler_state;
2265     int i;
2266
2267     assert(render_state->wm.sampler_count > 0);
2268     assert(render_state->wm.sampler_count <= MAX_SAMPLERS);
2269
2270     dri_bo_map(render_state->wm.sampler, 1);
2271     assert(render_state->wm.sampler->virtual);
2272     sampler_state = render_state->wm.sampler->virtual;
2273     for (i = 0; i < render_state->wm.sampler_count; i++) {
2274         memset(sampler_state, 0, sizeof(*sampler_state));
2275         sampler_state->ss0.min_filter = I965_MAPFILTER_LINEAR;
2276         sampler_state->ss0.mag_filter = I965_MAPFILTER_LINEAR;
2277         sampler_state->ss3.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2278         sampler_state->ss3.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2279         sampler_state->ss3.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
2280         sampler_state++;
2281     }
2282
2283     dri_bo_unmap(render_state->wm.sampler);
2284 }
2285
2286 static void
2287 gen7_render_setup_states(
2288     VADriverContextP   ctx,
2289     VASurfaceID        surface,
2290     const VARectangle *src_rect,
2291     const VARectangle *dst_rect
2292 )
2293 {
2294     i965_render_dest_surface_state(ctx, 0);
2295     i965_render_src_surfaces_state(ctx, surface);
2296     gen7_render_sampler(ctx);
2297     i965_render_cc_viewport(ctx);
2298     gen7_render_color_calc_state(ctx);
2299     gen7_render_blend_state(ctx);
2300     gen7_render_depth_stencil_state(ctx);
2301     i965_render_upload_constants(ctx, surface);
2302     i965_render_upload_vertex(ctx, surface, src_rect, dst_rect);
2303 }
2304
2305 static void
2306 gen7_emit_invarient_states(VADriverContextP ctx)
2307 {
2308     struct i965_driver_data *i965 = i965_driver_data(ctx);
2309     struct intel_batchbuffer *batch = i965->batch;
2310
2311     BEGIN_BATCH(batch, 1);
2312     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_3D);
2313     ADVANCE_BATCH(batch);
2314
2315     BEGIN_BATCH(batch, 4);
2316     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
2317     OUT_BATCH(batch, GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
2318               GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
2319     OUT_BATCH(batch, 0);
2320     OUT_BATCH(batch, 0);
2321     ADVANCE_BATCH(batch);
2322
2323     BEGIN_BATCH(batch, 2);
2324     OUT_BATCH(batch, GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
2325     OUT_BATCH(batch, 1);
2326     ADVANCE_BATCH(batch);
2327
2328     /* Set system instruction pointer */
2329     BEGIN_BATCH(batch, 2);
2330     OUT_BATCH(batch, CMD_STATE_SIP | 0);
2331     OUT_BATCH(batch, 0);
2332     ADVANCE_BATCH(batch);
2333 }
2334
2335 static void
2336 gen7_emit_state_base_address(VADriverContextP ctx)
2337 {
2338     struct i965_driver_data *i965 = i965_driver_data(ctx);
2339     struct intel_batchbuffer *batch = i965->batch;
2340     struct i965_render_state *render_state = &i965->render_state;
2341
2342     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
2343     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state base address */
2344     OUT_RELOC(batch, render_state->wm.surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
2345     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state base address */
2346     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object base address */
2347     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction base address */
2348     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* General state upper bound */
2349     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */
2350     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Indirect object upper bound */
2351     OUT_BATCH(batch, BASE_ADDRESS_MODIFY); /* Instruction access upper bound */
2352 }
2353
2354 static void
2355 gen7_emit_viewport_state_pointers(VADriverContextP ctx)
2356 {
2357     struct i965_driver_data *i965 = i965_driver_data(ctx);
2358     struct intel_batchbuffer *batch = i965->batch;
2359     struct i965_render_state *render_state = &i965->render_state;
2360
2361     BEGIN_BATCH(batch, 2);
2362     OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
2363     OUT_RELOC(batch,
2364               render_state->cc.viewport,
2365               I915_GEM_DOMAIN_INSTRUCTION, 0,
2366               0);
2367     ADVANCE_BATCH(batch);
2368
2369     BEGIN_BATCH(batch, 2);
2370     OUT_BATCH(batch, GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
2371     OUT_BATCH(batch, 0);
2372     ADVANCE_BATCH(batch);
2373 }
2374
2375 /*
2376  * URB layout on GEN7
2377  * ----------------------------------------
2378  * | PS Push Constants (8KB) | VS entries |
2379  * ----------------------------------------
2380  */
2381 static void
2382 gen7_emit_urb(VADriverContextP ctx)
2383 {
2384     struct i965_driver_data *i965 = i965_driver_data(ctx);
2385     struct intel_batchbuffer *batch = i965->batch;
2386
2387     BEGIN_BATCH(batch, 2);
2388     OUT_BATCH(batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
2389     OUT_BATCH(batch, 8); /* in 1KBs */
2390     ADVANCE_BATCH(batch);
2391
2392     BEGIN_BATCH(batch, 2);
2393     OUT_BATCH(batch, GEN7_3DSTATE_URB_VS | (2 - 2));
2394     OUT_BATCH(batch,
2395               (32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */
2396               (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
2397               (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2398    ADVANCE_BATCH(batch);
2399
2400    BEGIN_BATCH(batch, 2);
2401    OUT_BATCH(batch, GEN7_3DSTATE_URB_GS | (2 - 2));
2402    OUT_BATCH(batch,
2403              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2404              (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2405    ADVANCE_BATCH(batch);
2406
2407    BEGIN_BATCH(batch, 2);
2408    OUT_BATCH(batch, GEN7_3DSTATE_URB_HS | (2 - 2));
2409    OUT_BATCH(batch,
2410              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2411              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2412    ADVANCE_BATCH(batch);
2413
2414    BEGIN_BATCH(batch, 2);
2415    OUT_BATCH(batch, GEN7_3DSTATE_URB_DS | (2 - 2));
2416    OUT_BATCH(batch,
2417              (0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
2418              (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
2419    ADVANCE_BATCH(batch);
2420 }
2421
2422 static void
2423 gen7_emit_cc_state_pointers(VADriverContextP ctx)
2424 {
2425     struct i965_driver_data *i965 = i965_driver_data(ctx);
2426     struct intel_batchbuffer *batch = i965->batch;
2427     struct i965_render_state *render_state = &i965->render_state;
2428
2429     BEGIN_BATCH(batch, 2);
2430     OUT_BATCH(batch, GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
2431     OUT_RELOC(batch,
2432               render_state->cc.state,
2433               I915_GEM_DOMAIN_INSTRUCTION, 0,
2434               1);
2435     ADVANCE_BATCH(batch);
2436
2437     BEGIN_BATCH(batch, 2);
2438     OUT_BATCH(batch, GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
2439     OUT_RELOC(batch,
2440               render_state->cc.blend,
2441               I915_GEM_DOMAIN_INSTRUCTION, 0,
2442               1);
2443     ADVANCE_BATCH(batch);
2444
2445     BEGIN_BATCH(batch, 2);
2446     OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
2447     OUT_RELOC(batch,
2448               render_state->cc.depth_stencil,
2449               I915_GEM_DOMAIN_INSTRUCTION, 0,
2450               1);
2451     ADVANCE_BATCH(batch);
2452 }
2453
2454 static void
2455 gen7_emit_sampler_state_pointers(VADriverContextP ctx)
2456 {
2457     struct i965_driver_data *i965 = i965_driver_data(ctx);
2458     struct intel_batchbuffer *batch = i965->batch;
2459     struct i965_render_state *render_state = &i965->render_state;
2460
2461     BEGIN_BATCH(batch, 2);
2462     OUT_BATCH(batch, GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
2463     OUT_RELOC(batch,
2464               render_state->wm.sampler,
2465               I915_GEM_DOMAIN_INSTRUCTION, 0,
2466               0);
2467     ADVANCE_BATCH(batch);
2468 }
2469
2470 static void
2471 gen7_emit_binding_table(VADriverContextP ctx)
2472 {
2473     struct i965_driver_data *i965 = i965_driver_data(ctx);
2474     struct intel_batchbuffer *batch = i965->batch;
2475
2476     BEGIN_BATCH(batch, 2);
2477     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
2478     OUT_BATCH(batch, BINDING_TABLE_OFFSET);
2479     ADVANCE_BATCH(batch);
2480 }
2481
2482 static void
2483 gen7_emit_depth_buffer_state(VADriverContextP ctx)
2484 {
2485     struct i965_driver_data *i965 = i965_driver_data(ctx);
2486     struct intel_batchbuffer *batch = i965->batch;
2487
2488     BEGIN_BATCH(batch, 7);
2489     OUT_BATCH(batch, GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
2490     OUT_BATCH(batch,
2491               (I965_DEPTHFORMAT_D32_FLOAT << 18) |
2492               (I965_SURFACE_NULL << 29));
2493     OUT_BATCH(batch, 0);
2494     OUT_BATCH(batch, 0);
2495     OUT_BATCH(batch, 0);
2496     OUT_BATCH(batch, 0);
2497     OUT_BATCH(batch, 0);
2498     ADVANCE_BATCH(batch);
2499
2500     BEGIN_BATCH(batch, 3);
2501     OUT_BATCH(batch, GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
2502     OUT_BATCH(batch, 0);
2503     OUT_BATCH(batch, 0);
2504     ADVANCE_BATCH(batch);
2505 }
2506
2507 static void
2508 gen7_emit_drawing_rectangle(VADriverContextP ctx)
2509 {
2510     i965_render_drawing_rectangle(ctx);
2511 }
2512
2513 static void
2514 gen7_emit_vs_state(VADriverContextP ctx)
2515 {
2516     struct i965_driver_data *i965 = i965_driver_data(ctx);
2517     struct intel_batchbuffer *batch = i965->batch;
2518
2519     /* disable VS constant buffer */
2520     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_VS | (7 - 2));
2521     OUT_BATCH(batch, 0);
2522     OUT_BATCH(batch, 0);
2523     OUT_BATCH(batch, 0);
2524     OUT_BATCH(batch, 0);
2525     OUT_BATCH(batch, 0);
2526     OUT_BATCH(batch, 0);
2527
2528     OUT_BATCH(batch, GEN6_3DSTATE_VS | (6 - 2));
2529     OUT_BATCH(batch, 0); /* without VS kernel */
2530     OUT_BATCH(batch, 0);
2531     OUT_BATCH(batch, 0);
2532     OUT_BATCH(batch, 0);
2533     OUT_BATCH(batch, 0); /* pass-through */
2534 }
2535
2536 static void
2537 gen7_emit_bypass_state(VADriverContextP ctx)
2538 {
2539     struct i965_driver_data *i965 = i965_driver_data(ctx);
2540     struct intel_batchbuffer *batch = i965->batch;
2541
2542     /* bypass GS */
2543     BEGIN_BATCH(batch, 7);
2544     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
2545     OUT_BATCH(batch, 0);
2546     OUT_BATCH(batch, 0);
2547     OUT_BATCH(batch, 0);
2548     OUT_BATCH(batch, 0);
2549     OUT_BATCH(batch, 0);
2550     OUT_BATCH(batch, 0);
2551     ADVANCE_BATCH(batch);
2552
2553     BEGIN_BATCH(batch, 7);
2554     OUT_BATCH(batch, GEN6_3DSTATE_GS | (7 - 2));
2555     OUT_BATCH(batch, 0); /* without GS kernel */
2556     OUT_BATCH(batch, 0);
2557     OUT_BATCH(batch, 0);
2558     OUT_BATCH(batch, 0);
2559     OUT_BATCH(batch, 0);
2560     OUT_BATCH(batch, 0); /* pass-through */
2561     ADVANCE_BATCH(batch);
2562
2563     BEGIN_BATCH(batch, 2);
2564     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
2565     OUT_BATCH(batch, 0);
2566     ADVANCE_BATCH(batch);
2567
2568     /* disable HS */
2569     BEGIN_BATCH(batch, 7);
2570     OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
2571     OUT_BATCH(batch, 0);
2572     OUT_BATCH(batch, 0);
2573     OUT_BATCH(batch, 0);
2574     OUT_BATCH(batch, 0);
2575     OUT_BATCH(batch, 0);
2576     OUT_BATCH(batch, 0);
2577     ADVANCE_BATCH(batch);
2578
2579     BEGIN_BATCH(batch, 7);
2580     OUT_BATCH(batch, GEN7_3DSTATE_HS | (7 - 2));
2581     OUT_BATCH(batch, 0);
2582     OUT_BATCH(batch, 0);
2583     OUT_BATCH(batch, 0);
2584     OUT_BATCH(batch, 0);
2585     OUT_BATCH(batch, 0);
2586     OUT_BATCH(batch, 0);
2587     ADVANCE_BATCH(batch);
2588
2589     BEGIN_BATCH(batch, 2);
2590     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
2591     OUT_BATCH(batch, 0);
2592     ADVANCE_BATCH(batch);
2593
2594     /* Disable TE */
2595     BEGIN_BATCH(batch, 4);
2596     OUT_BATCH(batch, GEN7_3DSTATE_TE | (4 - 2));
2597     OUT_BATCH(batch, 0);
2598     OUT_BATCH(batch, 0);
2599     OUT_BATCH(batch, 0);
2600     ADVANCE_BATCH(batch);
2601
2602     /* Disable DS */
2603     BEGIN_BATCH(batch, 7);
2604     OUT_BATCH(batch, GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
2605     OUT_BATCH(batch, 0);
2606     OUT_BATCH(batch, 0);
2607     OUT_BATCH(batch, 0);
2608     OUT_BATCH(batch, 0);
2609     OUT_BATCH(batch, 0);
2610     OUT_BATCH(batch, 0);
2611     ADVANCE_BATCH(batch);
2612
2613     BEGIN_BATCH(batch, 6);
2614     OUT_BATCH(batch, GEN7_3DSTATE_DS | (6 - 2));
2615     OUT_BATCH(batch, 0);
2616     OUT_BATCH(batch, 0);
2617     OUT_BATCH(batch, 0);
2618     OUT_BATCH(batch, 0);
2619     OUT_BATCH(batch, 0);
2620     ADVANCE_BATCH(batch);
2621
2622     BEGIN_BATCH(batch, 2);
2623     OUT_BATCH(batch, GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
2624     OUT_BATCH(batch, 0);
2625     ADVANCE_BATCH(batch);
2626
2627     /* Disable STREAMOUT */
2628     BEGIN_BATCH(batch, 3);
2629     OUT_BATCH(batch, GEN7_3DSTATE_STREAMOUT | (3 - 2));
2630     OUT_BATCH(batch, 0);
2631     OUT_BATCH(batch, 0);
2632     ADVANCE_BATCH(batch);
2633 }
2634
2635 static void
2636 gen7_emit_clip_state(VADriverContextP ctx)
2637 {
2638     struct i965_driver_data *i965 = i965_driver_data(ctx);
2639     struct intel_batchbuffer *batch = i965->batch;
2640
2641     OUT_BATCH(batch, GEN6_3DSTATE_CLIP | (4 - 2));
2642     OUT_BATCH(batch, 0);
2643     OUT_BATCH(batch, 0); /* pass-through */
2644     OUT_BATCH(batch, 0);
2645 }
2646
2647 static void
2648 gen7_emit_sf_state(VADriverContextP ctx)
2649 {
2650     struct i965_driver_data *i965 = i965_driver_data(ctx);
2651     struct intel_batchbuffer *batch = i965->batch;
2652
2653     BEGIN_BATCH(batch, 14);
2654     OUT_BATCH(batch, GEN7_3DSTATE_SBE | (14 - 2));
2655     OUT_BATCH(batch,
2656               (1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
2657               (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
2658               (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
2659     OUT_BATCH(batch, 0);
2660     OUT_BATCH(batch, 0);
2661     OUT_BATCH(batch, 0); /* DW4 */
2662     OUT_BATCH(batch, 0);
2663     OUT_BATCH(batch, 0);
2664     OUT_BATCH(batch, 0);
2665     OUT_BATCH(batch, 0);
2666     OUT_BATCH(batch, 0); /* DW9 */
2667     OUT_BATCH(batch, 0);
2668     OUT_BATCH(batch, 0);
2669     OUT_BATCH(batch, 0);
2670     OUT_BATCH(batch, 0);
2671     ADVANCE_BATCH(batch);
2672
2673     BEGIN_BATCH(batch, 7);
2674     OUT_BATCH(batch, GEN6_3DSTATE_SF | (7 - 2));
2675     OUT_BATCH(batch, 0);
2676     OUT_BATCH(batch, GEN6_3DSTATE_SF_CULL_NONE);
2677     OUT_BATCH(batch, 2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
2678     OUT_BATCH(batch, 0);
2679     OUT_BATCH(batch, 0);
2680     OUT_BATCH(batch, 0);
2681     ADVANCE_BATCH(batch);
2682 }
2683
2684 static void
2685 gen7_emit_wm_state(VADriverContextP ctx, int kernel)
2686 {
2687     struct i965_driver_data *i965 = i965_driver_data(ctx);
2688     struct intel_batchbuffer *batch = i965->batch;
2689     struct i965_render_state *render_state = &i965->render_state;
2690
2691     BEGIN_BATCH(batch, 3);
2692     OUT_BATCH(batch, GEN6_3DSTATE_WM | (3 - 2));
2693     OUT_BATCH(batch,
2694               GEN7_WM_DISPATCH_ENABLE |
2695               GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
2696     OUT_BATCH(batch, 0);
2697     ADVANCE_BATCH(batch);
2698
2699     BEGIN_BATCH(batch, 7);
2700     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
2701     OUT_BATCH(batch, 1);
2702     OUT_BATCH(batch, 0);
2703     OUT_RELOC(batch,
2704               render_state->curbe.bo,
2705               I915_GEM_DOMAIN_INSTRUCTION, 0,
2706               0);
2707     OUT_BATCH(batch, 0);
2708     OUT_BATCH(batch, 0);
2709     OUT_BATCH(batch, 0);
2710     ADVANCE_BATCH(batch);
2711
2712     BEGIN_BATCH(batch, 8);
2713     OUT_BATCH(batch, GEN7_3DSTATE_PS | (8 - 2));
2714     OUT_RELOC(batch,
2715               render_state->render_kernels[kernel].bo,
2716               I915_GEM_DOMAIN_INSTRUCTION, 0,
2717               0);
2718     OUT_BATCH(batch,
2719               (1 << GEN7_PS_SAMPLER_COUNT_SHIFT) |
2720               (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
2721     OUT_BATCH(batch, 0); /* scratch space base offset */
2722     OUT_BATCH(batch,
2723               ((86 - 1) << GEN7_PS_MAX_THREADS_SHIFT) |
2724               GEN7_PS_PUSH_CONSTANT_ENABLE |
2725               GEN7_PS_ATTRIBUTE_ENABLE |
2726               GEN7_PS_16_DISPATCH_ENABLE);
2727     OUT_BATCH(batch,
2728               (6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0));
2729     OUT_BATCH(batch, 0); /* kernel 1 pointer */
2730     OUT_BATCH(batch, 0); /* kernel 2 pointer */
2731     ADVANCE_BATCH(batch);
2732 }
2733
2734 static void
2735 gen7_emit_vertex_element_state(VADriverContextP ctx)
2736 {
2737     struct i965_driver_data *i965 = i965_driver_data(ctx);
2738     struct intel_batchbuffer *batch = i965->batch;
2739
2740     /* Set up our vertex elements, sourced from the single vertex buffer. */
2741     OUT_BATCH(batch, CMD_VERTEX_ELEMENTS | (5 - 2));
2742     /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
2743     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2744               GEN6_VE0_VALID |
2745               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2746               (0 << VE0_OFFSET_SHIFT));
2747     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2748               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2749               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2750               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2751     /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
2752     OUT_BATCH(batch, (0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) |
2753               GEN6_VE0_VALID |
2754               (I965_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2755               (8 << VE0_OFFSET_SHIFT));
2756     OUT_BATCH(batch, (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
2757               (I965_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
2758               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
2759               (I965_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2760 }
2761
2762 static void
2763 gen7_emit_vertices(VADriverContextP ctx)
2764 {
2765     struct i965_driver_data *i965 = i965_driver_data(ctx);
2766     struct intel_batchbuffer *batch = i965->batch;
2767     struct i965_render_state *render_state = &i965->render_state;
2768
2769     BEGIN_BATCH(batch, 5);
2770     OUT_BATCH(batch, CMD_VERTEX_BUFFERS | (5 - 2));
2771     OUT_BATCH(batch,
2772               (0 << GEN6_VB0_BUFFER_INDEX_SHIFT) |
2773               GEN6_VB0_VERTEXDATA |
2774               GEN7_VB0_ADDRESS_MODIFYENABLE |
2775               ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
2776     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 0);
2777     OUT_RELOC(batch, render_state->vb.vertex_buffer, I915_GEM_DOMAIN_VERTEX, 0, 12 * 4);
2778     OUT_BATCH(batch, 0);
2779     ADVANCE_BATCH(batch);
2780
2781     BEGIN_BATCH(batch, 7);
2782     OUT_BATCH(batch, CMD_3DPRIMITIVE | (7 - 2));
2783     OUT_BATCH(batch,
2784               _3DPRIM_RECTLIST |
2785               GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
2786     OUT_BATCH(batch, 3); /* vertex count per instance */
2787     OUT_BATCH(batch, 0); /* start vertex offset */
2788     OUT_BATCH(batch, 1); /* single instance */
2789     OUT_BATCH(batch, 0); /* start instance location */
2790     OUT_BATCH(batch, 0);
2791     ADVANCE_BATCH(batch);
2792 }
2793
2794 static void
2795 gen7_render_emit_states(VADriverContextP ctx, int kernel)
2796 {
2797     struct i965_driver_data *i965 = i965_driver_data(ctx);
2798     struct intel_batchbuffer *batch = i965->batch;
2799
2800     intel_batchbuffer_start_atomic(batch, 0x1000);
2801     intel_batchbuffer_emit_mi_flush(batch);
2802     gen7_emit_invarient_states(ctx);
2803     gen7_emit_state_base_address(ctx);
2804     gen7_emit_viewport_state_pointers(ctx);
2805     gen7_emit_urb(ctx);
2806     gen7_emit_cc_state_pointers(ctx);
2807     gen7_emit_sampler_state_pointers(ctx);
2808     gen7_emit_bypass_state(ctx);
2809     gen7_emit_vs_state(ctx);
2810     gen7_emit_clip_state(ctx);
2811     gen7_emit_sf_state(ctx);
2812     gen7_emit_wm_state(ctx, kernel);
2813     gen7_emit_binding_table(ctx);
2814     gen7_emit_depth_buffer_state(ctx);
2815     gen7_emit_drawing_rectangle(ctx);
2816     gen7_emit_vertex_element_state(ctx);
2817     gen7_emit_vertices(ctx);
2818     intel_batchbuffer_end_atomic(batch);
2819 }
2820
2821 static void
2822 gen7_render_put_surface(
2823     VADriverContextP   ctx,
2824     VASurfaceID        surface,
2825     const VARectangle *src_rect,
2826     const VARectangle *dst_rect,
2827     unsigned int       flags
2828 )
2829 {
2830     struct i965_driver_data *i965 = i965_driver_data(ctx);
2831     struct intel_batchbuffer *batch = i965->batch;
2832
2833     gen7_render_initialize(ctx);
2834     gen7_render_setup_states(ctx, surface, src_rect, dst_rect);
2835     i965_clear_dest_region(ctx);
2836     gen7_render_emit_states(ctx, PS_KERNEL);
2837     intel_batchbuffer_flush(batch);
2838 }
2839
2840 static void
2841 gen7_subpicture_render_blend_state(VADriverContextP ctx)
2842 {
2843     struct i965_driver_data *i965 = i965_driver_data(ctx);
2844     struct i965_render_state *render_state = &i965->render_state;
2845     struct gen6_blend_state *blend_state;
2846
2847     dri_bo_unmap(render_state->cc.state);
2848     dri_bo_map(render_state->cc.blend, 1);
2849     assert(render_state->cc.blend->virtual);
2850     blend_state = render_state->cc.blend->virtual;
2851     memset(blend_state, 0, sizeof(*blend_state));
2852     blend_state->blend0.dest_blend_factor = I965_BLENDFACTOR_INV_SRC_ALPHA;
2853     blend_state->blend0.source_blend_factor = I965_BLENDFACTOR_SRC_ALPHA;
2854     blend_state->blend0.blend_func = I965_BLENDFUNCTION_ADD;
2855     blend_state->blend0.blend_enable = 1;
2856     blend_state->blend1.post_blend_clamp_enable = 1;
2857     blend_state->blend1.pre_blend_clamp_enable = 1;
2858     blend_state->blend1.clamp_range = 0; /* clamp range [0, 1] */
2859     dri_bo_unmap(render_state->cc.blend);
2860 }
2861
2862 static void
2863 gen7_subpicture_render_setup_states(
2864     VADriverContextP   ctx,
2865     VASurfaceID        surface,
2866     const VARectangle *src_rect,
2867     const VARectangle *dst_rect
2868 )
2869 {
2870     i965_render_dest_surface_state(ctx, 0);
2871     i965_subpic_render_src_surfaces_state(ctx, surface);
2872     i965_render_sampler(ctx);
2873     i965_render_cc_viewport(ctx);
2874     gen7_render_color_calc_state(ctx);
2875     gen7_subpicture_render_blend_state(ctx);
2876     gen7_render_depth_stencil_state(ctx);
2877     i965_subpic_render_upload_vertex(ctx, surface, dst_rect);
2878 }
2879
2880 static void
2881 gen7_render_put_subpicture(
2882     VADriverContextP   ctx,
2883     VASurfaceID        surface,
2884     const VARectangle *src_rect,
2885     const VARectangle *dst_rect
2886 )
2887 {
2888     struct i965_driver_data *i965 = i965_driver_data(ctx);
2889     struct intel_batchbuffer *batch = i965->batch;
2890     struct object_surface *obj_surface = SURFACE(surface);
2891     struct object_subpic *obj_subpic = SUBPIC(obj_surface->subpic);
2892
2893     assert(obj_subpic);
2894     gen7_render_initialize(ctx);
2895     gen7_subpicture_render_setup_states(ctx, surface, src_rect, dst_rect);
2896     gen7_render_emit_states(ctx, PS_SUBPIC_KERNEL);
2897     i965_render_upload_image_palette(ctx, obj_subpic->image, 0xff);
2898     intel_batchbuffer_flush(batch);
2899 }
2900
2901
2902 /*
2903  * global functions
2904  */
2905 VAStatus
2906 i965_DestroySurfaces(VADriverContextP ctx,
2907                      VASurfaceID *surface_list,
2908                      int num_surfaces);
2909 void
2910 intel_render_put_surface(
2911     VADriverContextP   ctx,
2912     VASurfaceID        surface,
2913     const VARectangle *src_rect,
2914     const VARectangle *dst_rect,
2915     unsigned int       flags
2916 )
2917 {
2918     struct i965_driver_data *i965 = i965_driver_data(ctx);
2919     int has_done_scaling = 0;
2920     VASurfaceID in_surface_id = surface;
2921     VASurfaceID out_surface_id = i965_post_processing(ctx, surface, src_rect, dst_rect, flags, &has_done_scaling);
2922
2923     assert((!has_done_scaling) || (out_surface_id != VA_INVALID_ID));
2924
2925     if (out_surface_id != VA_INVALID_ID)
2926         in_surface_id = out_surface_id;
2927
2928     if (IS_GEN7(i965->intel.device_id))
2929         gen7_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
2930     else if (IS_GEN6(i965->intel.device_id))
2931         gen6_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
2932     else
2933         i965_render_put_surface(ctx, in_surface_id, has_done_scaling ? dst_rect : src_rect, dst_rect, flags);
2934
2935     if (in_surface_id != surface)
2936         i965_DestroySurfaces(ctx, &in_surface_id, 1);
2937 }
2938
2939 void
2940 intel_render_put_subpicture(
2941     VADriverContextP   ctx,
2942     VASurfaceID        surface,
2943     const VARectangle *src_rect,
2944     const VARectangle *dst_rect
2945 )
2946 {
2947     struct i965_driver_data *i965 = i965_driver_data(ctx);
2948
2949     if (IS_GEN7(i965->intel.device_id))
2950         gen7_render_put_subpicture(ctx, surface, src_rect, dst_rect);
2951     else if (IS_GEN6(i965->intel.device_id))
2952         gen6_render_put_subpicture(ctx, surface, src_rect, dst_rect);
2953     else
2954         i965_render_put_subpicture(ctx, surface, src_rect, dst_rect);
2955 }
2956
2957 Bool
2958 i965_render_init(VADriverContextP ctx)
2959 {
2960     struct i965_driver_data *i965 = i965_driver_data(ctx);
2961     struct i965_render_state *render_state = &i965->render_state;
2962     int i;
2963
2964     /* kernel */
2965     assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen5) /
2966                                  sizeof(render_kernels_gen5[0])));
2967     assert(NUM_RENDER_KERNEL == (sizeof(render_kernels_gen6) /
2968                                  sizeof(render_kernels_gen6[0])));
2969
2970     if (IS_GEN7(i965->intel.device_id))
2971         memcpy(render_state->render_kernels, render_kernels_gen7, sizeof(render_state->render_kernels));
2972     else if (IS_GEN6(i965->intel.device_id))
2973         memcpy(render_state->render_kernels, render_kernels_gen6, sizeof(render_state->render_kernels));
2974     else if (IS_IRONLAKE(i965->intel.device_id))
2975         memcpy(render_state->render_kernels, render_kernels_gen5, sizeof(render_state->render_kernels));
2976     else
2977         memcpy(render_state->render_kernels, render_kernels_gen4, sizeof(render_state->render_kernels));
2978
2979     for (i = 0; i < NUM_RENDER_KERNEL; i++) {
2980         struct i965_kernel *kernel = &render_state->render_kernels[i];
2981
2982         if (!kernel->size)
2983             continue;
2984
2985         kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
2986                                   kernel->name,
2987                                   kernel->size, 0x1000);
2988         assert(kernel->bo);
2989         dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
2990     }
2991
2992     /* constant buffer */
2993     render_state->curbe.bo = dri_bo_alloc(i965->intel.bufmgr,
2994                       "constant buffer",
2995                       4096, 64);
2996     assert(render_state->curbe.bo);
2997
2998     return True;
2999 }
3000
3001 Bool
3002 i965_render_terminate(VADriverContextP ctx)
3003 {
3004     int i;
3005     struct i965_driver_data *i965 = i965_driver_data(ctx);
3006     struct i965_render_state *render_state = &i965->render_state;
3007
3008     dri_bo_unreference(render_state->curbe.bo);
3009     render_state->curbe.bo = NULL;
3010
3011     for (i = 0; i < NUM_RENDER_KERNEL; i++) {
3012         struct i965_kernel *kernel = &render_state->render_kernels[i];
3013
3014         dri_bo_unreference(kernel->bo);
3015         kernel->bo = NULL;
3016     }
3017
3018     dri_bo_unreference(render_state->vb.vertex_buffer);
3019     render_state->vb.vertex_buffer = NULL;
3020     dri_bo_unreference(render_state->vs.state);
3021     render_state->vs.state = NULL;
3022     dri_bo_unreference(render_state->sf.state);
3023     render_state->sf.state = NULL;
3024     dri_bo_unreference(render_state->wm.sampler);
3025     render_state->wm.sampler = NULL;
3026     dri_bo_unreference(render_state->wm.state);
3027     render_state->wm.state = NULL;
3028     dri_bo_unreference(render_state->wm.surface_state_binding_table_bo);
3029     dri_bo_unreference(render_state->cc.viewport);
3030     render_state->cc.viewport = NULL;
3031     dri_bo_unreference(render_state->cc.state);
3032     render_state->cc.state = NULL;
3033     dri_bo_unreference(render_state->cc.blend);
3034     render_state->cc.blend = NULL;
3035     dri_bo_unreference(render_state->cc.depth_stencil);
3036     render_state->cc.depth_stencil = NULL;
3037
3038     if (render_state->draw_region) {
3039         dri_bo_unreference(render_state->draw_region->bo);
3040         free(render_state->draw_region);
3041         render_state->draw_region = NULL;
3042     }
3043
3044     return True;
3045 }
3046