2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #define MAX_PP_SURFACES 48
34 #define I965_PP_FLAG_TOP_FIELD 1
35 #define I965_PP_FLAG_BOTTOM_FIELD 2
36 #define I965_PP_FLAG_MCDI 4
37 #define I965_PP_FLAG_AVS 8
42 PP_NV12_LOAD_SAVE_N12,
43 PP_NV12_LOAD_SAVE_PL3,
55 PP_RGBX_LOAD_SAVE_NV12,
56 PP_NV12_LOAD_SAVE_RGBX,
60 struct i965_post_processing_context;
62 struct pp_load_save_context
70 struct pp_scaling_context
72 int dest_x; /* in pixel */
73 int dest_y; /* in pixel */
76 float src_normalized_x;
77 float src_normalized_y;
82 int dest_x; /* in pixel */
83 int dest_y; /* in pixel */
86 float src_normalized_x;
87 float src_normalized_y;
93 struct pp_dndi_context
98 int frame_order; /* -1 for the first frame */
99 VASurfaceID current_out_surface;
100 struct object_surface *current_out_obj_surface;
110 struct i965_post_processing_context;
114 struct i965_kernel kernel;
117 VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
118 const struct i965_surface *src_surface,
119 const VARectangle *src_rect,
120 struct i965_surface *dst_surface,
121 const VARectangle *dst_rect,
125 struct pp_static_parameter
129 float procamp_constant_c0;
131 /* Load and Same r1.1 */
132 unsigned int source_packed_y_offset:8;
133 unsigned int source_packed_u_offset:8;
134 unsigned int source_packed_v_offset:8;
135 unsigned int source_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
138 /* Load and Save r1.2 */
140 unsigned int destination_packed_y_offset:8;
141 unsigned int destination_packed_u_offset:8;
142 unsigned int destination_packed_v_offset:8;
148 unsigned int pad0:24;
149 unsigned int destination_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
154 float procamp_constant_c1;
157 float procamp_constant_c2;
160 unsigned int statistics_surface_picth:16; /* Devided by 2 */
161 unsigned int pad1:16;
166 unsigned int pad0:24;
167 unsigned int top_field_first:8;
170 /* AVS/Scaling r1.6 */
171 float normalized_video_y_scaling_step;
175 float procamp_constant_c5;
180 float procamp_constant_c3;
186 float wg_csc_constant_c4;
189 float wg_csc_constant_c8;
192 float procamp_constant_c4;
201 float wg_csc_constant_c9;
206 float wg_csc_constant_c0;
209 float scaling_step_ratio;
212 float normalized_alpha_y_scaling;
215 float wg_csc_constant_c4;
218 float wg_csc_constant_c1;
221 int horizontal_origin_offset:16;
222 int vertical_origin_offset:16;
227 unsigned int color_pixel;
230 float wg_csc_constant_c2;
234 float wg_csc_constant_c3;
239 float wg_csc_constant_c6;
241 /* ALL r4.1 MBZ ???*/
248 unsigned int pad1:15;
250 unsigned int pad2:16;
255 unsigned int motion_history_coefficient_m2:8;
256 unsigned int motion_history_coefficient_m1:8;
257 unsigned int pad0:16;
262 float wg_csc_constant_c7;
265 float wg_csc_constant_c10;
268 float source_video_frame_normalized_horizontal_origin;
274 float wg_csc_constant_c11;
278 struct pp_inline_parameter
282 int destination_block_horizontal_origin:16;
283 int destination_block_vertical_origin:16;
288 float source_surface_block_normalized_horizontal_origin;
292 unsigned int variance_surface_vertical_origin:16;
293 unsigned int pad0:16;
297 /* AVS/Scaling r5.2 */
298 float source_surface_block_normalized_vertical_origin;
301 float alpha_surface_block_normalized_horizontal_origin;
304 float alpha_surface_block_normalized_vertical_origin;
307 unsigned int alpha_mask_x:16;
308 unsigned int alpha_mask_y:8;
309 unsigned int block_count_x:8;
312 /* we only support M*1 or 1*N block partitation now.
313 * -- it means asm code only need update this mask from grf6 for the last block
315 unsigned int block_horizontal_mask:16;
316 unsigned int block_vertical_mask:8;
317 unsigned int number_blocks:8;
319 /* AVS/Scaling r5.7 */
320 float normalized_video_x_scaling_step;
325 float video_step_delta;
327 /* r6.1 */ // sizeof(int) == 4?
328 unsigned int block_horizontal_mask_right:16;
329 unsigned int block_vertical_mask_bottom:8;
333 unsigned int block_horizontal_mask_middle:16;
334 unsigned int pad2:16;
337 unsigned int padx[5];
341 struct gen7_pp_static_parameter
345 unsigned int padx[6];
347 unsigned int di_statistics_surface_pitch_div2:16;
348 unsigned int di_statistics_surface_height_div4:16;
350 unsigned int di_top_field_first:8;
351 unsigned int pad0:16;
352 unsigned int pointer_to_inline_parameter:8; /* value: 7 */
357 /* Indicates whether the rgb is swapped for the src surface
358 * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
360 unsigned int src_avs_rgb_swap:1;
361 unsigned int pad3:31;
364 unsigned int pad2:16;
365 unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
366 unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
367 unsigned int ief_enable:1;
368 unsigned int avs_wa_width:13;
371 float avs_wa_one_div_256_width;
374 float avs_wa_five_div_256_width;
377 unsigned int padx[3];
380 unsigned int di_destination_packed_y_component_offset:8;
381 unsigned int di_destination_packed_u_component_offset:8;
382 unsigned int di_destination_packed_v_component_offset:8;
383 unsigned int alpha:8;
387 float sampler_load_horizontal_scaling_step_ratio;
388 unsigned int padx[7];
392 float sampler_load_vertical_scaling_step;
394 unsigned int di_hoffset_svf_from_dvf:16;
395 unsigned int di_voffset_svf_from_dvf:16;
396 unsigned int padx[5];
400 float sampler_load_vertical_frame_origin;
401 unsigned int padx[7];
405 float sampler_load_horizontal_frame_origin;
406 unsigned int padx[7];
410 struct gen7_pp_inline_parameter
414 unsigned int destination_block_horizontal_origin:16;
415 unsigned int destination_block_vertical_origin:16;
416 /* r7.1: 0xffffffff */
417 unsigned int constant_0;
423 float sampler_load_main_video_x_scaling_step;
426 /* r7.6: must be zero */
427 unsigned int avs_vertical_block_number;
429 unsigned int group_id_number;
433 unsigned int padx[8];
437 struct i965_post_processing_context
440 struct pp_module pp_modules[NUM_PP_MODULES];
441 void *pp_static_parameter;
442 void *pp_inline_parameter;
446 } surface_state_binding_table;
454 int num_interface_descriptors;
465 } sampler_state_table;
470 unsigned int vfe_start;
471 unsigned int cs_start;
473 unsigned int num_vfe_entries;
474 unsigned int num_cs_entries;
476 unsigned int size_vfe_entry;
477 unsigned int size_cs_entry;
481 unsigned int gpgpu_mode : 1;
482 unsigned int pad0 : 7;
483 unsigned int max_num_threads : 16;
484 unsigned int num_urb_entries : 8;
485 unsigned int urb_entry_size : 16;
486 unsigned int curbe_allocation_size : 16;
489 struct pp_load_save_context pp_load_save_context;
490 struct pp_scaling_context pp_scaling_context;
491 struct pp_avs_context pp_avs_context;
492 struct pp_dndi_context pp_dndi_context;
493 struct pp_dn_context pp_dn_context;
494 void *private_context; /* pointer to the current private context */
495 void *pipeline_param; /* pointer to the pipeline parameter */
497 int (*pp_x_steps)(void *private_context);
498 int (*pp_y_steps)(void *private_context);
499 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
501 struct intel_batchbuffer *batch;
503 unsigned int block_horizontal_mask_left:16;
504 unsigned int block_horizontal_mask_right:16;
505 unsigned int block_vertical_mask_bottom:8;
510 unsigned int end_offset;
520 unsigned int end_offset;
523 unsigned int sampler_offset;
525 unsigned int idrt_offset;
527 unsigned int curbe_offset;
530 VAStatus (*intel_post_processing)(VADriverContextP ctx,
531 struct i965_post_processing_context *pp_context,
532 const struct i965_surface *src_surface,
533 const VARectangle *src_rect,
534 struct i965_surface *dst_surface,
535 const VARectangle *dst_rect,
537 void * filter_param);
538 void (*finalize)(struct i965_post_processing_context *pp_context);
541 struct i965_proc_context
543 struct hw_context base;
544 struct i965_post_processing_context pp_context;
548 i965_post_processing(
549 VADriverContextP ctx,
550 struct object_surface *obj_surface,
551 const VARectangle *src_rect,
552 const VARectangle *dst_rect,
554 int *has_done_scaling
558 i965_scaling_processing(
559 VADriverContextP ctx,
560 struct object_surface *src_surface_obj,
561 const VARectangle *src_rect,
562 struct object_surface *dst_surface_obj,
563 const VARectangle *dst_rect,
568 i965_image_processing(VADriverContextP ctx,
569 const struct i965_surface *src_surface,
570 const VARectangle *src_rect,
571 struct i965_surface *dst_surface,
572 const VARectangle *dst_rect);
575 i965_post_processing_terminate(VADriverContextP ctx);
577 i965_post_processing_init(VADriverContextP ctx);
581 i965_proc_picture(VADriverContextP ctx,
583 union codec_state *codec_state,
584 struct hw_context *hw_context);
586 #endif /* __I965_POST_PROCESSING_H__ */