src/i965_post_processing.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #ifndef __I965_POST_PROCESSING_H__
  30 #define __I965_POST_PROCESSING_H__
  31
  32 #define MAX_PP_SURFACES 48
  33
  34 #define I965_PP_FLAG_TOP_FIELD          1
  35 #define I965_PP_FLAG_BOTTOM_FIELD       2
  36 #define I965_PP_FLAG_MCDI               4
  37 #define I965_PP_FLAG_AVS                8
  38
  39 enum
  40 {
  41     PP_NULL = 0,
  42     PP_NV12_LOAD_SAVE_N12,
  43     PP_NV12_LOAD_SAVE_PL3,
  44     PP_PL3_LOAD_SAVE_N12,
  45     PP_PL3_LOAD_SAVE_PL3,
  46     PP_NV12_SCALING,
  47     PP_NV12_AVS,
  48     PP_NV12_DNDI,
  49     PP_NV12_DN,
  50     PP_NV12_LOAD_SAVE_PA,
  51 };
  52
  53 #define NUM_PP_MODULES                  10
  54
  55 struct i965_post_processing_context;
  56
  57 struct pp_load_save_context
  58 {
  59     int dest_w;
  60     int dest_h;
  61 };
  62
  63 struct pp_scaling_context
  64 {
  65     int dest_x; /* in pixel */
  66     int dest_y; /* in pixel */
  67     int dest_w;
  68     int dest_h;
  69     float src_normalized_x;
  70     float src_normalized_y;
  71 };
  72
  73 struct pp_avs_context
  74 {
  75     int dest_x; /* in pixel */
  76     int dest_y; /* in pixel */
  77     int dest_w;
  78     int dest_h;
  79     float src_normalized_x;
  80     float src_normalized_y;
  81     int src_w;
  82     int src_h;
  83 };
  84
  85 struct pp_dndi_context
  86 {
  87     int dest_w;
  88     int dest_h;
  89 };
  90
  91 struct pp_dn_context
  92 {
  93     int dest_w;
  94     int dest_h;
  95 };
  96
  97 struct pp_module
  98 {
  99     struct i965_kernel kernel;
 100
 101     /* others */
 102     VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 103                            const struct i965_surface *src_surface,
 104                            const VARectangle *src_rect,
 105                            struct i965_surface *dst_surface,
 106                            const VARectangle *dst_rect,
 107                            void *filter_param);
 108 };
 109
 110 struct pp_static_parameter
 111 {
 112     struct {
 113         /* Procamp r1.0 */
 114         float procamp_constant_c0;
 115
 116         /* Load and Same r1.1 */
 117         unsigned int source_packed_y_offset:8;
 118         unsigned int source_packed_u_offset:8;
 119         unsigned int source_packed_v_offset:8;
 120         unsigned int pad0:8;
 121
 122         union {
 123             /* Load and Save r1.2 */
 124             struct {
 125                 unsigned int destination_packed_y_offset:8;
 126                 unsigned int destination_packed_u_offset:8;
 127                 unsigned int destination_packed_v_offset:8;
 128                 unsigned int pad0:8;
 129             } load_and_save;
 130
 131             /* CSC r1.2 */
 132             struct {
 133                 unsigned int destination_rgb_format:8;
 134                 unsigned int pad0:24;
 135             } csc;
 136         } r1_2;
 137
 138         /* Procamp r1.3 */
 139         float procamp_constant_c1;
 140
 141         /* Procamp r1.4 */
 142         float procamp_constant_c2;
 143
 144         /* DI r1.5 */
 145         unsigned int statistics_surface_picth:16;  /* Devided by 2 */
 146         unsigned int pad1:16;
 147
 148         union {
 149             /* DI r1.6 */
 150             struct {
 151                 unsigned int pad0:24;
 152                 unsigned int top_field_first:8;
 153             } di;
 154
 155             /* AVS/Scaling r1.6 */
 156             float normalized_video_y_scaling_step;
 157         } r1_6;
 158
 159         /* Procamp r1.7 */
 160         float procamp_constant_c5;
 161     } grf1;
 162
 163     struct {
 164         /* Procamp r2.0 */
 165         float procamp_constant_c3;
 166
 167         /* MBZ r2.1*/
 168         unsigned int pad0;
 169
 170         /* WG+CSC r2.2 */
 171         float wg_csc_constant_c4;
 172
 173         /* WG+CSC r2.3 */
 174         float wg_csc_constant_c8;
 175
 176         /* Procamp r2.4 */
 177         float procamp_constant_c4;
 178
 179         /* MBZ r2.5 */
 180         unsigned int pad1;
 181
 182         /* MBZ r2.6 */
 183         unsigned int pad2;
 184
 185         /* WG+CSC r2.7 */
 186         float wg_csc_constant_c9;
 187     } grf2;
 188
 189     struct {
 190         /* WG+CSC r3.0 */
 191         float wg_csc_constant_c0;
 192
 193         /* Blending r3.1 */
 194         float scaling_step_ratio;
 195
 196         /* Blending r3.2 */
 197         float normalized_alpha_y_scaling;
 198
 199         /* WG+CSC r3.3 */
 200         float wg_csc_constant_c4;
 201
 202         /* WG+CSC r3.4 */
 203         float wg_csc_constant_c1;
 204
 205         /* ALL r3.5 */
 206         int horizontal_origin_offset:16;
 207         int vertical_origin_offset:16;
 208
 209         /* Shared r3.6*/
 210         union {
 211             /* Color filll */
 212             unsigned int color_pixel;
 213
 214             /* WG+CSC */
 215             float wg_csc_constant_c2;
 216         } r3_6;
 217
 218         /* WG+CSC r3.7 */
 219         float wg_csc_constant_c3;
 220     } grf3;
 221
 222     struct {
 223         /* WG+CSC r4.0 */
 224         float wg_csc_constant_c6;
 225
 226         /* ALL r4.1 MBZ ???*/
 227         unsigned int pad0;
 228
 229         /* Shared r4.2 */
 230         union {
 231             /* AVS */
 232             struct {
 233                 unsigned int pad1:15;
 234                 unsigned int nlas:1;
 235                 unsigned int pad2:16;
 236             } avs;
 237
 238             /* DI */
 239             struct {
 240                 unsigned int motion_history_coefficient_m2:8;
 241                 unsigned int motion_history_coefficient_m1:8;
 242                 unsigned int pad0:16;
 243             } di;
 244         } r4_2;
 245
 246         /* WG+CSC r4.3 */
 247         float wg_csc_constant_c7;
 248
 249         /* WG+CSC r4.4 */
 250         float wg_csc_constant_c10;
 251
 252         /* AVS r4.5 */
 253         float source_video_frame_normalized_horizontal_origin;
 254
 255         /* MBZ r4.6 */
 256         unsigned int pad1;
 257
 258         /* WG+CSC r4.7 */
 259         float wg_csc_constant_c11;
 260     } grf4;
 261 };
 262
 263 struct pp_inline_parameter
 264 {
 265     struct {
 266         /* ALL r5.0 */
 267         int destination_block_horizontal_origin:16;
 268         int destination_block_vertical_origin:16;
 269
 270         /* Shared r5.1 */
 271         union {
 272             /* AVS/Scaling */
 273             float source_surface_block_normalized_horizontal_origin;
 274
 275             /* FMD */
 276             struct {
 277                 unsigned int variance_surface_vertical_origin:16;
 278                 unsigned int pad0:16;
 279             } fmd;
 280         } r5_1;
 281
 282         /* AVS/Scaling r5.2 */
 283         float source_surface_block_normalized_vertical_origin;
 284
 285         /* Alpha r5.3 */
 286         float alpha_surface_block_normalized_horizontal_origin;
 287
 288         /* Alpha r5.4 */
 289         float alpha_surface_block_normalized_vertical_origin;
 290
 291         /* Alpha r5.5 */
 292         unsigned int alpha_mask_x:16;
 293         unsigned int alpha_mask_y:8;
 294         unsigned int block_count_x:8;
 295
 296         /* r5.6 */
 297         unsigned int block_horizontal_mask:16;
 298         unsigned int block_vertical_mask:8;
 299         unsigned int number_blocks:8;
 300
 301         /* AVS/Scaling r5.7 */
 302         float normalized_video_x_scaling_step;
 303     } grf5;
 304
 305     struct {
 306         /* AVS r6.0 */
 307         float video_step_delta;
 308
 309         /* r6.1-r6.7 */
 310         unsigned int padx[7];
 311     } grf6;
 312 };
 313
 314 struct gen7_pp_static_parameter
 315 {
 316     struct {
 317         /* r1.0-r1.5 */
 318         unsigned int padx[6];
 319         /* r1.6 */
 320         unsigned int di_statistics_surface_pitch_div2:16;
 321         unsigned int di_statistics_surface_height_div4:16;
 322         /* r1.7 */
 323         unsigned int di_top_field_first:8;
 324         unsigned int pad0:16;
 325         unsigned int pointer_to_inline_parameter:8; /* value: 7 */
 326     } grf1;
 327
 328     struct {
 329         /* r2.0-r2.6 */
 330         unsigned int padx[7];
 331         /* r2.7 */
 332         unsigned int di_destination_packed_y_component_offset:8;
 333         unsigned int di_destination_packed_u_component_offset:8;
 334         unsigned int di_destination_packed_v_component_offset:8;
 335         unsigned int pad0:8;
 336     } grf2;
 337
 338     struct {
 339         float sampler_load_horizontal_scaling_step_ratio;
 340         unsigned int padx[7];
 341     } grf3;
 342
 343     struct {
 344         float sampler_load_vertical_scaling_step;
 345         unsigned int pad0;
 346         unsigned int di_hoffset_svf_from_dvf:16;
 347         unsigned int di_voffset_svf_from_dvf:16;
 348         unsigned int padx[5];
 349     } grf4;
 350
 351     struct {
 352         float sampler_load_vertical_frame_origin;
 353         unsigned int padx[7];
 354     } grf5;
 355
 356     struct {
 357         float sampler_load_horizontal_frame_origin;
 358         unsigned int padx[7];
 359     } grf6;
 360 };
 361
 362 struct gen7_pp_inline_parameter
 363 {
 364     struct {
 365         /* r7.0 */
 366         unsigned int destination_block_horizontal_origin:16;
 367         unsigned int destination_block_vertical_origin:16;
 368         /* r7.1: 0xffffffff */
 369         unsigned int constant_0;
 370         /* r7.2 */
 371         unsigned int pad0;
 372         /* r7.3 */
 373         unsigned int pad1;
 374         /* r7.4 */
 375         float sampler_load_main_video_x_scaling_step;
 376         /* r7.5 */
 377         unsigned int pad2;
 378         /* r7.6: must be zero */
 379         unsigned int avs_vertical_block_number;
 380         /* r7.7: 0 */
 381         unsigned int group_id_number;
 382     } grf7;
 383
 384     struct {
 385         unsigned int padx[8];
 386     } grf8;
 387 };
 388
 389 struct i965_post_processing_context
 390 {
 391     int current_pp;
 392     struct pp_module pp_modules[NUM_PP_MODULES];
 393     void *pp_static_parameter;
 394     void *pp_inline_parameter;
 395
 396     struct {
 397         dri_bo *bo;
 398     } surface_state_binding_table;
 399
 400     struct {
 401         dri_bo *bo;
 402     } curbe;
 403
 404     struct {
 405         dri_bo *bo;
 406         int num_interface_descriptors;
 407     } idrt;
 408
 409     struct {
 410         dri_bo *bo;
 411     } vfe_state;
 412
 413     struct {
 414         dri_bo *bo;
 415         dri_bo *bo_8x8;
 416         dri_bo *bo_8x8_uv;
 417     } sampler_state_table;
 418
 419     struct {
 420         unsigned int size;
 421
 422         unsigned int vfe_start;
 423         unsigned int cs_start;
 424
 425         unsigned int num_vfe_entries;
 426         unsigned int num_cs_entries;
 427
 428         unsigned int size_vfe_entry;
 429         unsigned int size_cs_entry;
 430     } urb;
 431
 432     struct {
 433         dri_bo *bo;
 434     } stmm;
 435
 436     union {
 437         struct pp_load_save_context pp_load_save_context;
 438         struct pp_scaling_context pp_scaling_context;
 439         struct pp_avs_context pp_avs_context;
 440         struct pp_dndi_context pp_dndi_context;
 441         struct pp_dn_context pp_dn_context;
 442     } private_context;
 443
 444     int (*pp_x_steps)(void *private_context);
 445     int (*pp_y_steps)(void *private_context);
 446     int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
 447
 448     struct intel_batchbuffer *batch;
 449 };
 450
 451 struct i965_proc_context
 452 {
 453     struct hw_context base;
 454     struct i965_post_processing_context pp_context;
 455 };
 456
 457 VASurfaceID
 458 i965_post_processing(
 459     VADriverContextP   ctx,
 460     VASurfaceID        surface,
 461     const VARectangle *src_rect,
 462     const VARectangle *dst_rect,
 463     unsigned int       flags,
 464     int                *has_done_scaling
 465 );
 466
 467 VAStatus
 468 i965_image_processing(VADriverContextP ctx,
 469                       const struct i965_surface *src_surface,
 470                       const VARectangle *src_rect,
 471                       struct i965_surface *dst_surface,
 472                       const VARectangle *dst_rect);
 473
 474 Bool
 475 i965_post_processing_terminate(VADriverContextP ctx);
 476 Bool
 477 i965_post_processing_init(VADriverContextP ctx);
 478
 479 #endif /* __I965_POST_PROCESSING_H__ */