2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #define MAX_PP_SURFACES 48
34 #define I965_PP_FLAG_TOP_FIELD 1
35 #define I965_PP_FLAG_BOTTOM_FIELD 2
36 #define I965_PP_FLAG_MCDI 4
37 #define I965_PP_FLAG_AVS 8
42 PP_NV12_LOAD_SAVE_N12,
43 PP_NV12_LOAD_SAVE_PL3,
54 PP_RGBX_LOAD_SAVE_NV12,
55 PP_NV12_LOAD_SAVE_RGBX,
59 struct i965_post_processing_context;
61 struct pp_load_save_context
67 struct pp_scaling_context
69 int dest_x; /* in pixel */
70 int dest_y; /* in pixel */
73 float src_normalized_x;
74 float src_normalized_y;
79 int dest_x; /* in pixel */
80 int dest_y; /* in pixel */
83 float src_normalized_x;
84 float src_normalized_y;
89 struct pp_dndi_context
103 struct i965_kernel kernel;
106 VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
107 const struct i965_surface *src_surface,
108 const VARectangle *src_rect,
109 struct i965_surface *dst_surface,
110 const VARectangle *dst_rect,
114 struct pp_static_parameter
118 float procamp_constant_c0;
120 /* Load and Same r1.1 */
121 unsigned int source_packed_y_offset:8;
122 unsigned int source_packed_u_offset:8;
123 unsigned int source_packed_v_offset:8;
124 unsigned int source_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
127 /* Load and Save r1.2 */
129 unsigned int destination_packed_y_offset:8;
130 unsigned int destination_packed_u_offset:8;
131 unsigned int destination_packed_v_offset:8;
137 unsigned int pad0:24;
138 unsigned int destination_rgb_layout:8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
143 float procamp_constant_c1;
146 float procamp_constant_c2;
149 unsigned int statistics_surface_picth:16; /* Devided by 2 */
150 unsigned int pad1:16;
155 unsigned int pad0:24;
156 unsigned int top_field_first:8;
159 /* AVS/Scaling r1.6 */
160 float normalized_video_y_scaling_step;
164 float procamp_constant_c5;
169 float procamp_constant_c3;
175 float wg_csc_constant_c4;
178 float wg_csc_constant_c8;
181 float procamp_constant_c4;
190 float wg_csc_constant_c9;
195 float wg_csc_constant_c0;
198 float scaling_step_ratio;
201 float normalized_alpha_y_scaling;
204 float wg_csc_constant_c4;
207 float wg_csc_constant_c1;
210 int horizontal_origin_offset:16;
211 int vertical_origin_offset:16;
216 unsigned int color_pixel;
219 float wg_csc_constant_c2;
223 float wg_csc_constant_c3;
228 float wg_csc_constant_c6;
230 /* ALL r4.1 MBZ ???*/
237 unsigned int pad1:15;
239 unsigned int pad2:16;
244 unsigned int motion_history_coefficient_m2:8;
245 unsigned int motion_history_coefficient_m1:8;
246 unsigned int pad0:16;
251 float wg_csc_constant_c7;
254 float wg_csc_constant_c10;
257 float source_video_frame_normalized_horizontal_origin;
263 float wg_csc_constant_c11;
267 struct pp_inline_parameter
271 int destination_block_horizontal_origin:16;
272 int destination_block_vertical_origin:16;
277 float source_surface_block_normalized_horizontal_origin;
281 unsigned int variance_surface_vertical_origin:16;
282 unsigned int pad0:16;
286 /* AVS/Scaling r5.2 */
287 float source_surface_block_normalized_vertical_origin;
290 float alpha_surface_block_normalized_horizontal_origin;
293 float alpha_surface_block_normalized_vertical_origin;
296 unsigned int alpha_mask_x:16;
297 unsigned int alpha_mask_y:8;
298 unsigned int block_count_x:8;
301 /* we only support M*1 or 1*N block partitation now.
302 * -- it means asm code only need update this mask from grf6 for the last block
304 unsigned int block_horizontal_mask:16;
305 unsigned int block_vertical_mask:8;
306 unsigned int number_blocks:8;
308 /* AVS/Scaling r5.7 */
309 float normalized_video_x_scaling_step;
314 float video_step_delta;
317 unsigned int block_horizontal_mask:16;
318 unsigned int block_vertical_mask:8;
322 unsigned int padx[6];
326 struct gen7_pp_static_parameter
330 unsigned int padx[6];
332 unsigned int di_statistics_surface_pitch_div2:16;
333 unsigned int di_statistics_surface_height_div4:16;
335 unsigned int di_top_field_first:8;
336 unsigned int pad0:16;
337 unsigned int pointer_to_inline_parameter:8; /* value: 7 */
345 unsigned int pad2:16;
346 unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
347 unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
349 unsigned int avs_wa_width:13;
352 float avs_wa_one_div_256_width;
355 float avs_wa_five_div_256_width;
358 unsigned int padx[3];
361 unsigned int di_destination_packed_y_component_offset:8;
362 unsigned int di_destination_packed_u_component_offset:8;
363 unsigned int di_destination_packed_v_component_offset:8;
368 float sampler_load_horizontal_scaling_step_ratio;
369 unsigned int padx[7];
373 float sampler_load_vertical_scaling_step;
375 unsigned int di_hoffset_svf_from_dvf:16;
376 unsigned int di_voffset_svf_from_dvf:16;
377 unsigned int padx[5];
381 float sampler_load_vertical_frame_origin;
382 unsigned int padx[7];
386 float sampler_load_horizontal_frame_origin;
387 unsigned int padx[7];
391 struct gen7_pp_inline_parameter
395 unsigned int destination_block_horizontal_origin:16;
396 unsigned int destination_block_vertical_origin:16;
397 /* r7.1: 0xffffffff */
398 unsigned int constant_0;
404 float sampler_load_main_video_x_scaling_step;
407 /* r7.6: must be zero */
408 unsigned int avs_vertical_block_number;
410 unsigned int group_id_number;
414 unsigned int padx[8];
418 struct i965_post_processing_context
421 struct pp_module pp_modules[NUM_PP_MODULES];
422 void *pp_static_parameter;
423 void *pp_inline_parameter;
427 } surface_state_binding_table;
435 int num_interface_descriptors;
446 } sampler_state_table;
451 unsigned int vfe_start;
452 unsigned int cs_start;
454 unsigned int num_vfe_entries;
455 unsigned int num_cs_entries;
457 unsigned int size_vfe_entry;
458 unsigned int size_cs_entry;
466 struct pp_load_save_context pp_load_save_context;
467 struct pp_scaling_context pp_scaling_context;
468 struct pp_avs_context pp_avs_context;
469 struct pp_dndi_context pp_dndi_context;
470 struct pp_dn_context pp_dn_context;
473 int (*pp_x_steps)(void *private_context);
474 int (*pp_y_steps)(void *private_context);
475 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
477 struct intel_batchbuffer *batch;
479 unsigned int block_horizontal_mask:16;
480 unsigned int block_vertical_mask:8;
483 struct i965_proc_context
485 struct hw_context base;
486 struct i965_post_processing_context pp_context;
490 i965_post_processing(
491 VADriverContextP ctx,
493 const VARectangle *src_rect,
494 const VARectangle *dst_rect,
496 int *has_done_scaling
500 i965_image_processing(VADriverContextP ctx,
501 const struct i965_surface *src_surface,
502 const VARectangle *src_rect,
503 struct i965_surface *dst_surface,
504 const VARectangle *dst_rect);
507 i965_post_processing_terminate(VADriverContextP ctx);
509 i965_post_processing_init(VADriverContextP ctx);
511 #endif /* __I965_POST_PROCESSING_H__ */