2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_post_processing.h"
40 #include "i965_render.h"
42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \
43 IS_GEN6((ctx)->intel.device_id) || \
44 IS_GEN7((ctx)->intel.device_id))
46 #define SURFACE_STATE_PADDED_SIZE_0_I965 ALIGN(sizeof(struct i965_surface_state), 32)
47 #define SURFACE_STATE_PADDED_SIZE_1_I965 ALIGN(sizeof(struct i965_surface_state2), 32)
48 #define SURFACE_STATE_PADDED_SIZE_I965 MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
52 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
54 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
55 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
56 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
58 static const uint32_t pp_null_gen5[][4] = {
59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
82 static const uint32_t pp_nv12_avs_gen5[][4] = {
83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
90 static const uint32_t pp_nv12_dn_gen5[][4] = {
91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
111 const struct i965_surface *src_surface,
112 const VARectangle *src_rect,
113 struct i965_surface *dst_surface,
114 const VARectangle *dst_rect,
116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
117 const struct i965_surface *src_surface,
118 const VARectangle *src_rect,
119 struct i965_surface *dst_surface,
120 const VARectangle *dst_rect,
122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
123 const struct i965_surface *src_surface,
124 const VARectangle *src_rect,
125 struct i965_surface *dst_surface,
126 const VARectangle *dst_rect,
128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
129 const struct i965_surface *src_surface,
130 const VARectangle *src_rect,
131 struct i965_surface *dst_surface,
132 const VARectangle *dst_rect,
134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
135 const struct i965_surface *src_surface,
136 const VARectangle *src_rect,
137 struct i965_surface *dst_surface,
138 const VARectangle *dst_rect,
140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
141 const struct i965_surface *src_surface,
142 const VARectangle *src_rect,
143 struct i965_surface *dst_surface,
144 const VARectangle *dst_rect,
146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
147 const struct i965_surface *src_surface,
148 const VARectangle *src_rect,
149 struct i965_surface *dst_surface,
150 const VARectangle *dst_rect,
153 static struct pp_module pp_modules_gen5[] = {
156 "NULL module (for testing)",
159 sizeof(pp_null_gen5),
169 PP_NV12_LOAD_SAVE_N12,
170 pp_nv12_load_save_nv12_gen5,
171 sizeof(pp_nv12_load_save_nv12_gen5),
175 pp_plx_load_save_plx_initialize,
181 PP_NV12_LOAD_SAVE_PL3,
182 pp_nv12_load_save_pl3_gen5,
183 sizeof(pp_nv12_load_save_pl3_gen5),
187 pp_plx_load_save_plx_initialize,
193 PP_PL3_LOAD_SAVE_N12,
194 pp_pl3_load_save_nv12_gen5,
195 sizeof(pp_pl3_load_save_nv12_gen5),
199 pp_plx_load_save_plx_initialize,
205 PP_PL3_LOAD_SAVE_N12,
206 pp_pl3_load_save_pl3_gen5,
207 sizeof(pp_pl3_load_save_pl3_gen5),
211 pp_plx_load_save_plx_initialize
216 "NV12 Scaling module",
218 pp_nv12_scaling_gen5,
219 sizeof(pp_nv12_scaling_gen5),
223 pp_nv12_scaling_initialize,
231 sizeof(pp_nv12_avs_gen5),
235 pp_nv12_avs_initialize_nlas,
243 sizeof(pp_nv12_dndi_gen5),
247 pp_nv12_dndi_initialize,
255 sizeof(pp_nv12_dn_gen5),
259 pp_nv12_dn_initialize,
265 PP_NV12_LOAD_SAVE_PA,
266 pp_nv12_load_save_pa_gen5,
267 sizeof(pp_nv12_load_save_pa_gen5),
271 pp_plx_load_save_plx_initialize,
278 pp_pl3_load_save_pa_gen5,
279 sizeof(pp_pl3_load_save_pa_gen5),
283 pp_plx_load_save_plx_initialize,
289 PP_PA_LOAD_SAVE_NV12,
290 pp_pa_load_save_nv12_gen5,
291 sizeof(pp_pa_load_save_nv12_gen5),
295 pp_plx_load_save_plx_initialize,
302 pp_pa_load_save_pl3_gen5,
303 sizeof(pp_pa_load_save_pl3_gen5),
307 pp_plx_load_save_plx_initialize,
312 static const uint32_t pp_null_gen6[][4] = {
313 #include "shaders/post_processing/gen5_6/null.g6b"
316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
336 static const uint32_t pp_nv12_avs_gen6[][4] = {
337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
344 static const uint32_t pp_nv12_dn_gen6[][4] = {
345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
364 static struct pp_module pp_modules_gen6[] = {
367 "NULL module (for testing)",
370 sizeof(pp_null_gen6),
380 PP_NV12_LOAD_SAVE_N12,
381 pp_nv12_load_save_nv12_gen6,
382 sizeof(pp_nv12_load_save_nv12_gen6),
386 pp_plx_load_save_plx_initialize,
392 PP_NV12_LOAD_SAVE_PL3,
393 pp_nv12_load_save_pl3_gen6,
394 sizeof(pp_nv12_load_save_pl3_gen6),
398 pp_plx_load_save_plx_initialize,
404 PP_PL3_LOAD_SAVE_N12,
405 pp_pl3_load_save_nv12_gen6,
406 sizeof(pp_pl3_load_save_nv12_gen6),
410 pp_plx_load_save_plx_initialize,
416 PP_PL3_LOAD_SAVE_N12,
417 pp_pl3_load_save_pl3_gen6,
418 sizeof(pp_pl3_load_save_pl3_gen6),
422 pp_plx_load_save_plx_initialize,
427 "NV12 Scaling module",
429 pp_nv12_scaling_gen6,
430 sizeof(pp_nv12_scaling_gen6),
434 gen6_nv12_scaling_initialize,
442 sizeof(pp_nv12_avs_gen6),
446 pp_nv12_avs_initialize_nlas,
454 sizeof(pp_nv12_dndi_gen6),
458 pp_nv12_dndi_initialize,
466 sizeof(pp_nv12_dn_gen6),
470 pp_nv12_dn_initialize,
475 PP_NV12_LOAD_SAVE_PA,
476 pp_nv12_load_save_pa_gen6,
477 sizeof(pp_nv12_load_save_pa_gen6),
481 pp_plx_load_save_plx_initialize,
488 pp_pl3_load_save_pa_gen6,
489 sizeof(pp_pl3_load_save_pa_gen6),
493 pp_plx_load_save_plx_initialize,
499 PP_PA_LOAD_SAVE_NV12,
500 pp_pa_load_save_nv12_gen6,
501 sizeof(pp_pa_load_save_nv12_gen6),
505 pp_plx_load_save_plx_initialize,
512 pp_pa_load_save_pl3_gen6,
513 sizeof(pp_pa_load_save_pl3_gen6),
517 pp_plx_load_save_plx_initialize,
522 static const uint32_t pp_null_gen7[][4] = {
525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
542 #include "shaders/post_processing/gen7/avs.g7b"
545 static const uint32_t pp_nv12_avs_gen7[][4] = {
546 #include "shaders/post_processing/gen7/avs.g7b"
549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
550 // #include "shaders/post_processing/gen7/dndi.g7b"
553 static const uint32_t pp_nv12_dn_gen7[][4] = {
555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
556 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
558 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
559 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
561 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
562 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
564 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
565 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
568 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
569 const struct i965_surface *src_surface,
570 const VARectangle *src_rect,
571 struct i965_surface *dst_surface,
572 const VARectangle *dst_rect,
574 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
575 const struct i965_surface *src_surface,
576 const VARectangle *src_rect,
577 struct i965_surface *dst_surface,
578 const VARectangle *dst_rect,
580 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
581 const struct i965_surface *src_surface,
582 const VARectangle *src_rect,
583 struct i965_surface *dst_surface,
584 const VARectangle *dst_rect,
587 static struct pp_module pp_modules_gen7[] = {
590 "NULL module (for testing)",
593 sizeof(pp_null_gen7),
603 PP_NV12_LOAD_SAVE_N12,
604 pp_nv12_load_save_nv12_gen7,
605 sizeof(pp_nv12_load_save_nv12_gen7),
609 gen7_pp_plx_avs_initialize,
615 PP_NV12_LOAD_SAVE_PL3,
616 pp_nv12_load_save_pl3_gen7,
617 sizeof(pp_nv12_load_save_pl3_gen7),
621 gen7_pp_plx_avs_initialize,
627 PP_PL3_LOAD_SAVE_N12,
628 pp_pl3_load_save_nv12_gen7,
629 sizeof(pp_pl3_load_save_nv12_gen7),
633 gen7_pp_plx_avs_initialize,
639 PP_PL3_LOAD_SAVE_N12,
640 pp_pl3_load_save_pl3_gen7,
641 sizeof(pp_pl3_load_save_pl3_gen7),
645 gen7_pp_plx_avs_initialize,
650 "NV12 Scaling module",
652 pp_nv12_scaling_gen7,
653 sizeof(pp_nv12_scaling_gen7),
657 gen7_pp_plx_avs_initialize,
665 sizeof(pp_nv12_avs_gen7),
669 gen7_pp_plx_avs_initialize,
677 sizeof(pp_nv12_dndi_gen7),
681 gen7_pp_nv12_dndi_initialize,
689 sizeof(pp_nv12_dn_gen7),
693 gen7_pp_nv12_dn_initialize,
698 PP_NV12_LOAD_SAVE_PA,
699 pp_nv12_load_save_pa_gen7,
700 sizeof(pp_nv12_load_save_pa_gen7),
704 gen7_pp_plx_avs_initialize,
711 pp_pl3_load_save_pa_gen7,
712 sizeof(pp_pl3_load_save_pa_gen7),
716 gen7_pp_plx_avs_initialize,
722 PP_PA_LOAD_SAVE_NV12,
723 pp_pa_load_save_nv12_gen7,
724 sizeof(pp_pa_load_save_nv12_gen7),
728 gen7_pp_plx_avs_initialize,
735 pp_pa_load_save_pl3_gen7,
736 sizeof(pp_pa_load_save_pl3_gen7),
740 gen7_pp_plx_avs_initialize,
746 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
748 struct i965_driver_data *i965 = i965_driver_data(ctx);
751 if (surface->type == I965_SURFACE_TYPE_IMAGE) {
752 struct object_image *obj_image = IMAGE(surface->id);
753 fourcc = obj_image->image.format.fourcc;
755 struct object_surface *obj_surface = SURFACE(surface->id);
756 fourcc = obj_surface->fourcc;
763 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
766 case I915_TILING_NONE:
767 ss->ss3.tiled_surface = 0;
768 ss->ss3.tile_walk = 0;
771 ss->ss3.tiled_surface = 1;
772 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
775 ss->ss3.tiled_surface = 1;
776 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
782 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
785 case I915_TILING_NONE:
786 ss->ss2.tiled_surface = 0;
787 ss->ss2.tile_walk = 0;
790 ss->ss2.tiled_surface = 1;
791 ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
794 ss->ss2.tiled_surface = 1;
795 ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
801 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
804 case I915_TILING_NONE:
805 ss->ss0.tiled_surface = 0;
806 ss->ss0.tile_walk = 0;
809 ss->ss0.tiled_surface = 1;
810 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
813 ss->ss0.tiled_surface = 1;
814 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
820 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
823 case I915_TILING_NONE:
824 ss->ss2.tiled_surface = 0;
825 ss->ss2.tile_walk = 0;
828 ss->ss2.tiled_surface = 1;
829 ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
832 ss->ss2.tiled_surface = 1;
833 ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
839 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
841 struct i965_interface_descriptor *desc;
843 int pp_index = pp_context->current_pp;
845 bo = pp_context->idrt.bo;
849 memset(desc, 0, sizeof(*desc));
850 desc->desc0.grf_reg_blocks = 10;
851 desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
852 desc->desc1.const_urb_entry_read_offset = 0;
853 desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
854 desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
855 desc->desc2.sampler_count = 0;
856 desc->desc3.binding_table_entry_count = 0;
857 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
859 dri_bo_emit_reloc(bo,
860 I915_GEM_DOMAIN_INSTRUCTION, 0,
861 desc->desc0.grf_reg_blocks,
862 offsetof(struct i965_interface_descriptor, desc0),
863 pp_context->pp_modules[pp_index].kernel.bo);
865 dri_bo_emit_reloc(bo,
866 I915_GEM_DOMAIN_INSTRUCTION, 0,
867 desc->desc2.sampler_count << 2,
868 offsetof(struct i965_interface_descriptor, desc2),
869 pp_context->sampler_state_table.bo);
872 pp_context->idrt.num_interface_descriptors++;
876 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
878 struct i965_vfe_state *vfe_state;
881 bo = pp_context->vfe_state.bo;
884 vfe_state = bo->virtual;
885 memset(vfe_state, 0, sizeof(*vfe_state));
886 vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
887 vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
888 vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
889 vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
890 vfe_state->vfe1.children_present = 0;
891 vfe_state->vfe2.interface_descriptor_base =
892 pp_context->idrt.bo->offset >> 4; /* reloc */
893 dri_bo_emit_reloc(bo,
894 I915_GEM_DOMAIN_INSTRUCTION, 0,
896 offsetof(struct i965_vfe_state, vfe2),
897 pp_context->idrt.bo);
902 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
904 unsigned char *constant_buffer;
905 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
907 assert(sizeof(*pp_static_parameter) == 128);
908 dri_bo_map(pp_context->curbe.bo, 1);
909 assert(pp_context->curbe.bo->virtual);
910 constant_buffer = pp_context->curbe.bo->virtual;
911 memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
912 dri_bo_unmap(pp_context->curbe.bo);
916 ironlake_pp_states_setup(VADriverContextP ctx,
917 struct i965_post_processing_context *pp_context)
919 ironlake_pp_interface_descriptor_table(pp_context);
920 ironlake_pp_vfe_state(pp_context);
921 ironlake_pp_upload_constants(pp_context);
925 ironlake_pp_pipeline_select(VADriverContextP ctx,
926 struct i965_post_processing_context *pp_context)
928 struct intel_batchbuffer *batch = pp_context->batch;
930 BEGIN_BATCH(batch, 1);
931 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
932 ADVANCE_BATCH(batch);
936 ironlake_pp_urb_layout(VADriverContextP ctx,
937 struct i965_post_processing_context *pp_context)
939 struct intel_batchbuffer *batch = pp_context->batch;
940 unsigned int vfe_fence, cs_fence;
942 vfe_fence = pp_context->urb.cs_start;
943 cs_fence = pp_context->urb.size;
945 BEGIN_BATCH(batch, 3);
946 OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
949 (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */
950 (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */
951 ADVANCE_BATCH(batch);
955 ironlake_pp_state_base_address(VADriverContextP ctx,
956 struct i965_post_processing_context *pp_context)
958 struct intel_batchbuffer *batch = pp_context->batch;
960 BEGIN_BATCH(batch, 8);
961 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
962 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
963 OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
964 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
965 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
966 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
967 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
968 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
969 ADVANCE_BATCH(batch);
973 ironlake_pp_state_pointers(VADriverContextP ctx,
974 struct i965_post_processing_context *pp_context)
976 struct intel_batchbuffer *batch = pp_context->batch;
978 BEGIN_BATCH(batch, 3);
979 OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
981 OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
982 ADVANCE_BATCH(batch);
986 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
987 struct i965_post_processing_context *pp_context)
989 struct intel_batchbuffer *batch = pp_context->batch;
991 BEGIN_BATCH(batch, 2);
992 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
994 ((pp_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */
995 (pp_context->urb.num_cs_entries << 0)); /* Number of URB Entries */
996 ADVANCE_BATCH(batch);
1000 ironlake_pp_constant_buffer(VADriverContextP ctx,
1001 struct i965_post_processing_context *pp_context)
1003 struct intel_batchbuffer *batch = pp_context->batch;
1005 BEGIN_BATCH(batch, 2);
1006 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1007 OUT_RELOC(batch, pp_context->curbe.bo,
1008 I915_GEM_DOMAIN_INSTRUCTION, 0,
1009 pp_context->urb.size_cs_entry - 1);
1010 ADVANCE_BATCH(batch);
1014 ironlake_pp_object_walker(VADriverContextP ctx,
1015 struct i965_post_processing_context *pp_context)
1017 struct intel_batchbuffer *batch = pp_context->batch;
1018 int x, x_steps, y, y_steps;
1019 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1021 x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1022 y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1024 for (y = 0; y < y_steps; y++) {
1025 for (x = 0; x < x_steps; x++) {
1026 if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1027 BEGIN_BATCH(batch, 20);
1028 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1029 OUT_BATCH(batch, 0);
1030 OUT_BATCH(batch, 0); /* no indirect data */
1031 OUT_BATCH(batch, 0);
1033 /* inline data grf 5-6 */
1034 assert(sizeof(*pp_inline_parameter) == 64);
1035 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1037 ADVANCE_BATCH(batch);
1044 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1045 struct i965_post_processing_context *pp_context)
1047 struct intel_batchbuffer *batch = pp_context->batch;
1049 intel_batchbuffer_start_atomic(batch, 0x1000);
1050 intel_batchbuffer_emit_mi_flush(batch);
1051 ironlake_pp_pipeline_select(ctx, pp_context);
1052 ironlake_pp_state_base_address(ctx, pp_context);
1053 ironlake_pp_state_pointers(ctx, pp_context);
1054 ironlake_pp_urb_layout(ctx, pp_context);
1055 ironlake_pp_cs_urb_layout(ctx, pp_context);
1056 ironlake_pp_constant_buffer(ctx, pp_context);
1057 ironlake_pp_object_walker(ctx, pp_context);
1058 intel_batchbuffer_end_atomic(batch);
1061 // update u/v offset when the surface format are packed yuv
1062 static void i965_update_src_surface_uv_offset(
1063 VADriverContextP ctx,
1064 struct i965_post_processing_context *pp_context,
1065 const struct i965_surface *surface)
1067 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1068 int fourcc = pp_get_surface_fourcc(ctx, surface);
1070 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1071 pp_static_parameter->grf1.source_packed_u_offset = 1;
1072 pp_static_parameter->grf1.source_packed_v_offset = 3;
1074 else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1075 pp_static_parameter->grf1.source_packed_y_offset = 1;
1076 pp_static_parameter->grf1.source_packed_v_offset = 2;
1081 static void i965_update_dst_surface_uv_offset(
1082 VADriverContextP ctx,
1083 struct i965_post_processing_context *pp_context,
1084 const struct i965_surface *surface)
1086 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1087 int fourcc = pp_get_surface_fourcc(ctx, surface);
1089 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1090 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1091 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1093 else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1094 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1095 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1101 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1102 dri_bo *surf_bo, unsigned long surf_bo_offset,
1103 int width, int height, int pitch, int format,
1104 int index, int is_target)
1106 struct i965_surface_state *ss;
1108 unsigned int tiling;
1109 unsigned int swizzle;
1111 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1112 ss_bo = pp_context->surface_state_binding_table.bo;
1115 dri_bo_map(ss_bo, True);
1116 assert(ss_bo->virtual);
1117 ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1118 memset(ss, 0, sizeof(*ss));
1119 ss->ss0.surface_type = I965_SURFACE_2D;
1120 ss->ss0.surface_format = format;
1121 ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1122 ss->ss2.width = width - 1;
1123 ss->ss2.height = height - 1;
1124 ss->ss3.pitch = pitch - 1;
1125 pp_set_surface_tiling(ss, tiling);
1126 dri_bo_emit_reloc(ss_bo,
1127 I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1129 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1131 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1132 dri_bo_unmap(ss_bo);
1136 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1137 dri_bo *surf_bo, unsigned long surf_bo_offset,
1138 int width, int height, int wpitch,
1139 int xoffset, int yoffset,
1140 int format, int interleave_chroma,
1143 struct i965_surface_state2 *ss2;
1145 unsigned int tiling;
1146 unsigned int swizzle;
1148 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1149 ss2_bo = pp_context->surface_state_binding_table.bo;
1152 dri_bo_map(ss2_bo, True);
1153 assert(ss2_bo->virtual);
1154 ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1155 memset(ss2, 0, sizeof(*ss2));
1156 ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1157 ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1158 ss2->ss1.width = width - 1;
1159 ss2->ss1.height = height - 1;
1160 ss2->ss2.pitch = wpitch - 1;
1161 ss2->ss2.interleave_chroma = interleave_chroma;
1162 ss2->ss2.surface_format = format;
1163 ss2->ss3.x_offset_for_cb = xoffset;
1164 ss2->ss3.y_offset_for_cb = yoffset;
1165 pp_set_surface2_tiling(ss2, tiling);
1166 dri_bo_emit_reloc(ss2_bo,
1167 I915_GEM_DOMAIN_RENDER, 0,
1169 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1171 ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1172 dri_bo_unmap(ss2_bo);
1176 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1177 dri_bo *surf_bo, unsigned long surf_bo_offset,
1178 int width, int height, int pitch, int format,
1179 int index, int is_target)
1181 struct gen7_surface_state *ss;
1183 unsigned int tiling;
1184 unsigned int swizzle;
1186 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1187 ss_bo = pp_context->surface_state_binding_table.bo;
1190 dri_bo_map(ss_bo, True);
1191 assert(ss_bo->virtual);
1192 ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1193 memset(ss, 0, sizeof(*ss));
1194 ss->ss0.surface_type = I965_SURFACE_2D;
1195 ss->ss0.surface_format = format;
1196 ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1197 ss->ss2.width = width - 1;
1198 ss->ss2.height = height - 1;
1199 ss->ss3.pitch = pitch - 1;
1200 gen7_pp_set_surface_tiling(ss, tiling);
1201 dri_bo_emit_reloc(ss_bo,
1202 I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1204 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1206 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1207 dri_bo_unmap(ss_bo);
1211 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1212 dri_bo *surf_bo, unsigned long surf_bo_offset,
1213 int width, int height, int wpitch,
1214 int xoffset, int yoffset,
1215 int format, int interleave_chroma,
1218 struct gen7_surface_state2 *ss2;
1220 unsigned int tiling;
1221 unsigned int swizzle;
1223 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1224 ss2_bo = pp_context->surface_state_binding_table.bo;
1227 dri_bo_map(ss2_bo, True);
1228 assert(ss2_bo->virtual);
1229 ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1230 memset(ss2, 0, sizeof(*ss2));
1231 ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1232 ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1233 ss2->ss1.width = width - 1;
1234 ss2->ss1.height = height - 1;
1235 ss2->ss2.pitch = wpitch - 1;
1236 ss2->ss2.interleave_chroma = interleave_chroma;
1237 ss2->ss2.surface_format = format;
1238 ss2->ss3.x_offset_for_cb = xoffset;
1239 ss2->ss3.y_offset_for_cb = yoffset;
1240 gen7_pp_set_surface2_tiling(ss2, tiling);
1241 dri_bo_emit_reloc(ss2_bo,
1242 I915_GEM_DOMAIN_RENDER, 0,
1244 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1246 ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1247 dri_bo_unmap(ss2_bo);
1251 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1252 const struct i965_surface *surface,
1253 int base_index, int is_target,
1254 int *width, int *height, int *pitch, int *offset)
1256 struct i965_driver_data *i965 = i965_driver_data(ctx);
1257 struct object_surface *obj_surface;
1258 struct object_image *obj_image;
1260 int fourcc = pp_get_surface_fourcc(ctx, surface);
1262 const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1263 const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1265 int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1266 int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1268 if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1269 obj_surface = SURFACE(surface->id);
1270 bo = obj_surface->bo;
1271 width[0] = obj_surface->orig_width;
1272 height[0] = obj_surface->orig_height;
1273 pitch[0] = obj_surface->width;
1277 width[0] = obj_surface->orig_width * 2;
1278 pitch[0] = obj_surface->width * 2;
1280 else if (interleaved_uv) {
1281 width[1] = obj_surface->orig_width;
1282 height[1] = obj_surface->orig_height / 2;
1283 pitch[1] = obj_surface->width;
1284 offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1286 width[1] = obj_surface->orig_width / 2;
1287 height[1] = obj_surface->orig_height / 2;
1288 pitch[1] = obj_surface->width / 2;
1289 offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1290 width[2] = obj_surface->orig_width / 2;
1291 height[2] = obj_surface->orig_height / 2;
1292 pitch[2] = obj_surface->width / 2;
1293 offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1296 obj_image = IMAGE(surface->id);
1298 width[0] = obj_image->image.width;
1299 height[0] = obj_image->image.height;
1300 pitch[0] = obj_image->image.pitches[0];
1301 offset[0] = obj_image->image.offsets[0];
1304 width[0] = obj_image->image.width * 2;
1306 else if (interleaved_uv) {
1307 width[1] = obj_image->image.width;
1308 height[1] = obj_image->image.height / 2;
1309 pitch[1] = obj_image->image.pitches[1];
1310 offset[1] = obj_image->image.offsets[1];
1312 width[1] = obj_image->image.width / 2;
1313 height[1] = obj_image->image.height / 2;
1314 pitch[1] = obj_image->image.pitches[1];
1315 offset[1] = obj_image->image.offsets[1];
1316 width[2] = obj_image->image.width / 2;
1317 height[2] = obj_image->image.height / 2;
1318 pitch[2] = obj_image->image.pitches[2];
1319 offset[2] = obj_image->image.offsets[2];
1324 i965_pp_set_surface_state(ctx, pp_context,
1326 width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1327 base_index, is_target);
1330 if (interleaved_uv) {
1331 i965_pp_set_surface_state(ctx, pp_context,
1333 width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1334 base_index + 1, is_target);
1337 i965_pp_set_surface_state(ctx, pp_context,
1339 width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1340 base_index + 1, is_target);
1343 i965_pp_set_surface_state(ctx, pp_context,
1345 width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1346 base_index + 2, is_target);
1353 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1354 const struct i965_surface *surface,
1355 int base_index, int is_target,
1356 int *width, int *height, int *pitch, int *offset)
1358 struct i965_driver_data *i965 = i965_driver_data(ctx);
1359 struct object_surface *obj_surface;
1360 struct object_image *obj_image;
1362 int fourcc = pp_get_surface_fourcc(ctx, surface);
1363 const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1364 fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1365 const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1366 fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1367 int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1368 int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1370 if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1371 obj_surface = SURFACE(surface->id);
1372 bo = obj_surface->bo;
1373 width[0] = obj_surface->orig_width;
1374 height[0] = obj_surface->orig_height;
1375 pitch[0] = obj_surface->width;
1380 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1382 width[0] = obj_surface->orig_width; /* surface foramt is YCBCR, width is specified in units of pixels */
1384 pitch[0] = obj_surface->width * 2;
1387 width[1] = obj_surface->cb_cr_width;
1388 height[1] = obj_surface->cb_cr_height;
1389 pitch[1] = obj_surface->cb_cr_pitch;
1390 offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1392 width[2] = obj_surface->cb_cr_width;
1393 height[2] = obj_surface->cb_cr_height;
1394 pitch[2] = obj_surface->cb_cr_pitch;
1395 offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1397 obj_image = IMAGE(surface->id);
1399 width[0] = obj_image->image.width;
1400 height[0] = obj_image->image.height;
1401 pitch[0] = obj_image->image.pitches[0];
1402 offset[0] = obj_image->image.offsets[0];
1406 width[0] = obj_image->image.width * 2; /* surface format is R8, so double the width */
1408 width[0] = obj_image->image.width; /* surface foramt is YCBCR, width is specified in units of pixels */
1409 } else if (interleaved_uv) {
1410 width[1] = obj_image->image.width / 2;
1411 height[1] = obj_image->image.height / 2;
1412 pitch[1] = obj_image->image.pitches[1];
1413 offset[1] = obj_image->image.offsets[1];
1415 width[1] = obj_image->image.width / 2;
1416 height[1] = obj_image->image.height / 2;
1417 pitch[1] = obj_image->image.pitches[U];
1418 offset[1] = obj_image->image.offsets[U];
1419 width[2] = obj_image->image.width / 2;
1420 height[2] = obj_image->image.height / 2;
1421 pitch[2] = obj_image->image.pitches[V];
1422 offset[2] = obj_image->image.offsets[V];
1427 gen7_pp_set_surface_state(ctx, pp_context,
1429 width[0] / 4, height[0], pitch[0],
1430 I965_SURFACEFORMAT_R8_SINT,
1434 if (interleaved_uv) {
1435 gen7_pp_set_surface_state(ctx, pp_context,
1437 width[1] / 2, height[1], pitch[1],
1438 I965_SURFACEFORMAT_R8G8_SINT,
1441 gen7_pp_set_surface_state(ctx, pp_context,
1443 width[1] / 4, height[1], pitch[1],
1444 I965_SURFACEFORMAT_R8_SINT,
1446 gen7_pp_set_surface_state(ctx, pp_context,
1448 width[2] / 4, height[2], pitch[2],
1449 I965_SURFACEFORMAT_R8_SINT,
1454 int format0 = SURFACE_FORMAT_Y8_UNORM;
1457 case VA_FOURCC('Y', 'U', 'Y', '2'):
1458 format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1461 case VA_FOURCC('U', 'Y', 'V', 'Y'):
1462 format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1469 gen7_pp_set_surface2_state(ctx, pp_context,
1471 width[0], height[0], pitch[0],
1477 if (interleaved_uv) {
1478 gen7_pp_set_surface2_state(ctx, pp_context,
1480 width[1], height[1], pitch[1],
1482 SURFACE_FORMAT_R8B8_UNORM, 0,
1485 gen7_pp_set_surface2_state(ctx, pp_context,
1487 width[1], height[1], pitch[1],
1489 SURFACE_FORMAT_R8_UNORM, 0,
1491 gen7_pp_set_surface2_state(ctx, pp_context,
1493 width[2], height[2], pitch[2],
1495 SURFACE_FORMAT_R8_UNORM, 0,
1503 pp_null_x_steps(void *private_context)
1509 pp_null_y_steps(void *private_context)
1515 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1521 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1522 const struct i965_surface *src_surface,
1523 const VARectangle *src_rect,
1524 struct i965_surface *dst_surface,
1525 const VARectangle *dst_rect,
1528 /* private function & data */
1529 pp_context->pp_x_steps = pp_null_x_steps;
1530 pp_context->pp_y_steps = pp_null_y_steps;
1531 pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1533 dst_surface->flags = src_surface->flags;
1535 return VA_STATUS_SUCCESS;
1539 pp_load_save_x_steps(void *private_context)
1545 pp_load_save_y_steps(void *private_context)
1547 struct pp_load_save_context *pp_load_save_context = private_context;
1549 return pp_load_save_context->dest_h / 8;
1553 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1555 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1557 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1558 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1559 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1560 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1566 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1567 const struct i965_surface *src_surface,
1568 const VARectangle *src_rect,
1569 struct i965_surface *dst_surface,
1570 const VARectangle *dst_rect,
1573 struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1574 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1575 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1576 int width[3], height[3], pitch[3], offset[3];
1579 /* source surface */
1580 pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1581 width, height, pitch, offset);
1583 /* destination surface */
1584 pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1585 width, height, pitch, offset);
1587 /* private function & data */
1588 pp_context->pp_x_steps = pp_load_save_x_steps;
1589 pp_context->pp_y_steps = pp_load_save_y_steps;
1590 pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1591 pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1592 pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1594 pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16; /* 1 x N */
1595 pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1597 pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1598 pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1600 // update u/v offset for packed yuv
1601 i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
1602 i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
1604 dst_surface->flags = src_surface->flags;
1606 return VA_STATUS_SUCCESS;
1610 pp_scaling_x_steps(void *private_context)
1616 pp_scaling_y_steps(void *private_context)
1618 struct pp_scaling_context *pp_scaling_context = private_context;
1620 return pp_scaling_context->dest_h / 8;
1624 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1626 struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1627 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1628 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1629 float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1630 float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1632 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1633 pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1634 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1635 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1641 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1642 const struct i965_surface *src_surface,
1643 const VARectangle *src_rect,
1644 struct i965_surface *dst_surface,
1645 const VARectangle *dst_rect,
1648 struct i965_driver_data *i965 = i965_driver_data(ctx);
1649 struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1650 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1651 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1652 struct object_surface *obj_surface;
1653 struct i965_sampler_state *sampler_state;
1654 int in_w, in_h, in_wpitch, in_hpitch;
1655 int out_w, out_h, out_wpitch, out_hpitch;
1657 /* source surface */
1658 obj_surface = SURFACE(src_surface->id);
1659 in_w = obj_surface->orig_width;
1660 in_h = obj_surface->orig_height;
1661 in_wpitch = obj_surface->width;
1662 in_hpitch = obj_surface->height;
1664 /* source Y surface index 1 */
1665 i965_pp_set_surface_state(ctx, pp_context,
1667 in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1670 /* source UV surface index 2 */
1671 i965_pp_set_surface_state(ctx, pp_context,
1672 obj_surface->bo, in_wpitch * in_hpitch,
1673 in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1676 /* destination surface */
1677 obj_surface = SURFACE(dst_surface->id);
1678 out_w = obj_surface->orig_width;
1679 out_h = obj_surface->orig_height;
1680 out_wpitch = obj_surface->width;
1681 out_hpitch = obj_surface->height;
1683 /* destination Y surface index 7 */
1684 i965_pp_set_surface_state(ctx, pp_context,
1686 out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1689 /* destination UV surface index 8 */
1690 i965_pp_set_surface_state(ctx, pp_context,
1691 obj_surface->bo, out_wpitch * out_hpitch,
1692 out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1696 dri_bo_map(pp_context->sampler_state_table.bo, True);
1697 assert(pp_context->sampler_state_table.bo->virtual);
1698 sampler_state = pp_context->sampler_state_table.bo->virtual;
1700 /* SIMD16 Y index 1 */
1701 sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1702 sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1703 sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1704 sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1705 sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1707 /* SIMD16 UV index 2 */
1708 sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1709 sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1710 sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1711 sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1712 sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1714 dri_bo_unmap(pp_context->sampler_state_table.bo);
1716 /* private function & data */
1717 pp_context->pp_x_steps = pp_scaling_x_steps;
1718 pp_context->pp_y_steps = pp_scaling_y_steps;
1719 pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1721 pp_scaling_context->dest_x = dst_rect->x;
1722 pp_scaling_context->dest_y = dst_rect->y;
1723 pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1724 pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1725 pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1726 pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1728 pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1730 pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1731 pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16; /* 1 x N */
1732 pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1733 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1734 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1736 dst_surface->flags = src_surface->flags;
1738 return VA_STATUS_SUCCESS;
1742 pp_avs_x_steps(void *private_context)
1744 struct pp_avs_context *pp_avs_context = private_context;
1746 return pp_avs_context->dest_w / 16;
1750 pp_avs_y_steps(void *private_context)
1756 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1758 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1759 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1760 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1761 float src_x_steping, src_y_steping, video_step_delta;
1762 int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1764 if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1765 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1766 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1767 } else if (tmp_w >= pp_avs_context->dest_w) {
1768 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1769 pp_inline_parameter->grf6.video_step_delta = 0;
1772 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1773 pp_avs_context->src_normalized_x;
1775 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1776 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1777 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1778 16 * 15 * video_step_delta / 2;
1781 int n0, n1, n2, nls_left, nls_right;
1782 int factor_a = 5, factor_b = 4;
1785 n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1786 n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1787 n2 = tmp_w / (16 * factor_a);
1789 nls_right = n1 + n2;
1790 f = (float) n2 * 16 / tmp_w;
1793 pp_inline_parameter->grf6.video_step_delta = 0.0;
1796 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1797 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1799 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1800 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1801 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1802 16 * 15 * video_step_delta / 2;
1806 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1807 float a = f / (nls_left * 16 * factor_b);
1808 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1810 pp_inline_parameter->grf6.video_step_delta = b;
1813 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1814 pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1816 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1817 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1818 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1819 16 * 15 * video_step_delta / 2;
1820 pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1822 } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1823 /* scale the center linearly */
1824 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1825 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1826 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1827 16 * 15 * video_step_delta / 2;
1828 pp_inline_parameter->grf6.video_step_delta = 0.0;
1829 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1831 float a = f / (nls_right * 16 * factor_b);
1832 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1834 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1835 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1836 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1837 16 * 15 * video_step_delta / 2;
1838 pp_inline_parameter->grf6.video_step_delta = -b;
1840 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1841 pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16 - 1) * b;
1843 pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1848 src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1849 pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1850 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1851 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1857 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1858 const struct i965_surface *src_surface,
1859 const VARectangle *src_rect,
1860 struct i965_surface *dst_surface,
1861 const VARectangle *dst_rect,
1865 struct i965_driver_data *i965 = i965_driver_data(ctx);
1866 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1867 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1868 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1869 struct object_surface *obj_surface;
1870 struct i965_sampler_8x8 *sampler_8x8;
1871 struct i965_sampler_8x8_state *sampler_8x8_state;
1873 int in_w, in_h, in_wpitch, in_hpitch;
1874 int out_w, out_h, out_wpitch, out_hpitch;
1878 obj_surface = SURFACE(src_surface->id);
1879 in_w = obj_surface->orig_width;
1880 in_h = obj_surface->orig_height;
1881 in_wpitch = obj_surface->width;
1882 in_hpitch = obj_surface->height;
1884 /* source Y surface index 1 */
1885 i965_pp_set_surface2_state(ctx, pp_context,
1887 in_w, in_h, in_wpitch,
1889 SURFACE_FORMAT_Y8_UNORM, 0,
1892 /* source UV surface index 2 */
1893 i965_pp_set_surface2_state(ctx, pp_context,
1894 obj_surface->bo, in_wpitch * in_hpitch,
1895 in_w / 2, in_h / 2, in_wpitch,
1897 SURFACE_FORMAT_R8B8_UNORM, 0,
1900 /* destination surface */
1901 obj_surface = SURFACE(dst_surface->id);
1902 out_w = obj_surface->orig_width;
1903 out_h = obj_surface->orig_height;
1904 out_wpitch = obj_surface->width;
1905 out_hpitch = obj_surface->height;
1906 assert(out_w <= out_wpitch && out_h <= out_hpitch);
1908 /* destination Y surface index 7 */
1909 i965_pp_set_surface_state(ctx, pp_context,
1911 out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1914 /* destination UV surface index 8 */
1915 i965_pp_set_surface_state(ctx, pp_context,
1916 obj_surface->bo, out_wpitch * out_hpitch,
1917 out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1920 /* sampler 8x8 state */
1921 dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1922 assert(pp_context->sampler_state_table.bo_8x8->virtual);
1923 assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1924 sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1925 memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1927 for (i = 0; i < 17; i++) {
1928 /* for Y channel, currently ignore */
1929 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1930 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1931 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1932 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1933 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1934 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1935 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1936 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1937 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1938 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1939 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1940 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1941 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1942 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1943 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1944 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1945 /* for U/V channel, 0.25 */
1946 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1947 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1948 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1949 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1950 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1951 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1952 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1953 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1954 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1955 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1956 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1957 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1958 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1959 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1960 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1961 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1964 sampler_8x8_state->dw136.default_sharpness_level = 0;
1965 sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1966 sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1967 sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1968 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1971 dri_bo_map(pp_context->sampler_state_table.bo, True);
1972 assert(pp_context->sampler_state_table.bo->virtual);
1973 assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1974 sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1976 /* sample_8x8 Y index 1 */
1978 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1979 sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1980 sampler_8x8[index].dw0.ief_bypass = 1;
1981 sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1982 sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1983 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1984 sampler_8x8[index].dw2.global_noise_estimation = 22;
1985 sampler_8x8[index].dw2.strong_edge_threshold = 8;
1986 sampler_8x8[index].dw2.weak_edge_threshold = 1;
1987 sampler_8x8[index].dw3.strong_edge_weight = 7;
1988 sampler_8x8[index].dw3.regular_weight = 2;
1989 sampler_8x8[index].dw3.non_edge_weight = 0;
1990 sampler_8x8[index].dw3.gain_factor = 40;
1991 sampler_8x8[index].dw4.steepness_boost = 0;
1992 sampler_8x8[index].dw4.steepness_threshold = 0;
1993 sampler_8x8[index].dw4.mr_boost = 0;
1994 sampler_8x8[index].dw4.mr_threshold = 5;
1995 sampler_8x8[index].dw5.pwl1_point_1 = 4;
1996 sampler_8x8[index].dw5.pwl1_point_2 = 12;
1997 sampler_8x8[index].dw5.pwl1_point_3 = 16;
1998 sampler_8x8[index].dw5.pwl1_point_4 = 26;
1999 sampler_8x8[index].dw6.pwl1_point_5 = 40;
2000 sampler_8x8[index].dw6.pwl1_point_6 = 160;
2001 sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2002 sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2003 sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2004 sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2005 sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2006 sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2007 sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2008 sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2009 sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2010 sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2011 sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2012 sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2013 sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2014 sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2015 sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2016 sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2017 sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2018 sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2019 sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2020 sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2021 sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2022 sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2023 sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2024 sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2025 sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2026 sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2027 sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2028 sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2029 sampler_8x8[index].dw13.limiter_boost = 0;
2030 sampler_8x8[index].dw13.minimum_limiter = 10;
2031 sampler_8x8[index].dw13.maximum_limiter = 11;
2032 sampler_8x8[index].dw14.clip_limiter = 130;
2033 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2034 I915_GEM_DOMAIN_RENDER,
2037 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2038 pp_context->sampler_state_table.bo_8x8);
2040 /* sample_8x8 UV index 2 */
2042 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2043 sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2044 sampler_8x8[index].dw0.ief_bypass = 1;
2045 sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2046 sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2047 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2048 sampler_8x8[index].dw2.global_noise_estimation = 22;
2049 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2050 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2051 sampler_8x8[index].dw3.strong_edge_weight = 7;
2052 sampler_8x8[index].dw3.regular_weight = 2;
2053 sampler_8x8[index].dw3.non_edge_weight = 0;
2054 sampler_8x8[index].dw3.gain_factor = 40;
2055 sampler_8x8[index].dw4.steepness_boost = 0;
2056 sampler_8x8[index].dw4.steepness_threshold = 0;
2057 sampler_8x8[index].dw4.mr_boost = 0;
2058 sampler_8x8[index].dw4.mr_threshold = 5;
2059 sampler_8x8[index].dw5.pwl1_point_1 = 4;
2060 sampler_8x8[index].dw5.pwl1_point_2 = 12;
2061 sampler_8x8[index].dw5.pwl1_point_3 = 16;
2062 sampler_8x8[index].dw5.pwl1_point_4 = 26;
2063 sampler_8x8[index].dw6.pwl1_point_5 = 40;
2064 sampler_8x8[index].dw6.pwl1_point_6 = 160;
2065 sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2066 sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2067 sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2068 sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2069 sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2070 sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2071 sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2072 sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2073 sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2074 sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2075 sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2076 sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2077 sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2078 sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2079 sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2080 sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2081 sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2082 sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2083 sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2084 sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2085 sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2086 sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2087 sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2088 sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2089 sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2090 sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2091 sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2092 sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2093 sampler_8x8[index].dw13.limiter_boost = 0;
2094 sampler_8x8[index].dw13.minimum_limiter = 10;
2095 sampler_8x8[index].dw13.maximum_limiter = 11;
2096 sampler_8x8[index].dw14.clip_limiter = 130;
2097 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2098 I915_GEM_DOMAIN_RENDER,
2101 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2102 pp_context->sampler_state_table.bo_8x8);
2104 dri_bo_unmap(pp_context->sampler_state_table.bo);
2106 /* private function & data */
2107 pp_context->pp_x_steps = pp_avs_x_steps;
2108 pp_context->pp_y_steps = pp_avs_y_steps;
2109 pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2111 pp_avs_context->dest_x = dst_rect->x;
2112 pp_avs_context->dest_y = dst_rect->y;
2113 pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2114 pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2115 pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2116 pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2117 pp_avs_context->src_w = src_rect->width;
2118 pp_avs_context->src_h = src_rect->height;
2120 pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2121 pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2123 pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2124 pp_inline_parameter->grf5.block_count_x = 1; /* M x 1 */
2125 pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2126 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2127 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2128 pp_inline_parameter->grf6.video_step_delta = 0.0;
2130 dst_surface->flags = src_surface->flags;
2132 return VA_STATUS_SUCCESS;
2136 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2137 const struct i965_surface *src_surface,
2138 const VARectangle *src_rect,
2139 struct i965_surface *dst_surface,
2140 const VARectangle *dst_rect,
2143 return pp_nv12_avs_initialize(ctx, pp_context,
2153 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2154 const struct i965_surface *src_surface,
2155 const VARectangle *src_rect,
2156 struct i965_surface *dst_surface,
2157 const VARectangle *dst_rect,
2160 return pp_nv12_avs_initialize(ctx, pp_context,
2170 gen7_pp_avs_x_steps(void *private_context)
2172 struct pp_avs_context *pp_avs_context = private_context;
2174 return pp_avs_context->dest_w / 16;
2178 gen7_pp_avs_y_steps(void *private_context)
2180 struct pp_avs_context *pp_avs_context = private_context;
2182 return pp_avs_context->dest_h / 16;
2186 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2188 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2189 struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2191 pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2192 pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2193 pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2194 pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2199 static void gen7_update_src_surface_uv_offset(VADriverContextP ctx,
2200 struct i965_post_processing_context *pp_context,
2201 const struct i965_surface *surface)
2203 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2204 int fourcc = pp_get_surface_fourcc(ctx, surface);
2206 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2207 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2208 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2209 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2210 } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2211 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2212 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2213 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2218 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2219 const struct i965_surface *src_surface,
2220 const VARectangle *src_rect,
2221 struct i965_surface *dst_surface,
2222 const VARectangle *dst_rect,
2225 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2226 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2227 struct gen7_sampler_8x8 *sampler_8x8;
2228 struct i965_sampler_8x8_state *sampler_8x8_state;
2230 int width[3], height[3], pitch[3], offset[3];
2232 /* source surface */
2233 gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2234 width, height, pitch, offset);
2236 /* destination surface */
2237 gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2238 width, height, pitch, offset);
2240 /* sampler 8x8 state */
2241 dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2242 assert(pp_context->sampler_state_table.bo_8x8->virtual);
2243 assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2244 sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2245 memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2247 for (i = 0; i < 17; i++) {
2248 /* for Y channel, currently ignore */
2249 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2250 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2251 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2252 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2253 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2254 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2255 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2256 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2257 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2258 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2259 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2260 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2261 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2262 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2263 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2264 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2265 /* for U/V channel, 0.25 */
2266 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2267 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2268 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2269 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2270 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2271 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2272 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2273 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2274 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2275 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2276 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2277 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2278 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2279 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2280 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2281 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2284 sampler_8x8_state->dw136.default_sharpness_level = 0;
2285 sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2286 sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2287 sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2288 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2291 dri_bo_map(pp_context->sampler_state_table.bo, True);
2292 assert(pp_context->sampler_state_table.bo->virtual);
2293 assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2294 sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2296 /* sample_8x8 Y index 4 */
2298 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2299 sampler_8x8[index].dw0.global_noise_estimation = 255;
2300 sampler_8x8[index].dw0.ief_bypass = 1;
2302 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2304 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2305 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2306 sampler_8x8[index].dw2.r5x_coefficient = 9;
2307 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2308 sampler_8x8[index].dw2.r5c_coefficient = 3;
2310 sampler_8x8[index].dw3.r3x_coefficient = 27;
2311 sampler_8x8[index].dw3.r3c_coefficient = 5;
2312 sampler_8x8[index].dw3.gain_factor = 40;
2313 sampler_8x8[index].dw3.non_edge_weight = 1;
2314 sampler_8x8[index].dw3.regular_weight = 2;
2315 sampler_8x8[index].dw3.strong_edge_weight = 7;
2316 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2318 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2319 I915_GEM_DOMAIN_RENDER,
2322 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2323 pp_context->sampler_state_table.bo_8x8);
2325 /* sample_8x8 UV index 8 */
2327 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2328 sampler_8x8[index].dw0.disable_8x8_filter = 0;
2329 sampler_8x8[index].dw0.global_noise_estimation = 255;
2330 sampler_8x8[index].dw0.ief_bypass = 1;
2331 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2332 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2333 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2334 sampler_8x8[index].dw2.r5x_coefficient = 9;
2335 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2336 sampler_8x8[index].dw2.r5c_coefficient = 3;
2337 sampler_8x8[index].dw3.r3x_coefficient = 27;
2338 sampler_8x8[index].dw3.r3c_coefficient = 5;
2339 sampler_8x8[index].dw3.gain_factor = 40;
2340 sampler_8x8[index].dw3.non_edge_weight = 1;
2341 sampler_8x8[index].dw3.regular_weight = 2;
2342 sampler_8x8[index].dw3.strong_edge_weight = 7;
2343 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2345 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2346 I915_GEM_DOMAIN_RENDER,
2349 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2350 pp_context->sampler_state_table.bo_8x8);
2352 /* sampler_8x8 V, index 12 */
2354 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2355 sampler_8x8[index].dw0.disable_8x8_filter = 0;
2356 sampler_8x8[index].dw0.global_noise_estimation = 255;
2357 sampler_8x8[index].dw0.ief_bypass = 1;
2358 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2359 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2360 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2361 sampler_8x8[index].dw2.r5x_coefficient = 9;
2362 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2363 sampler_8x8[index].dw2.r5c_coefficient = 3;
2364 sampler_8x8[index].dw3.r3x_coefficient = 27;
2365 sampler_8x8[index].dw3.r3c_coefficient = 5;
2366 sampler_8x8[index].dw3.gain_factor = 40;
2367 sampler_8x8[index].dw3.non_edge_weight = 1;
2368 sampler_8x8[index].dw3.regular_weight = 2;
2369 sampler_8x8[index].dw3.strong_edge_weight = 7;
2370 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2372 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2373 I915_GEM_DOMAIN_RENDER,
2376 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2377 pp_context->sampler_state_table.bo_8x8);
2379 dri_bo_unmap(pp_context->sampler_state_table.bo);
2381 /* private function & data */
2382 pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2383 pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2384 pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2386 pp_avs_context->dest_x = dst_rect->x;
2387 pp_avs_context->dest_y = dst_rect->y;
2388 pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2389 pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2390 pp_avs_context->src_w = src_rect->width;
2391 pp_avs_context->src_h = src_rect->height;
2393 int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2394 dw = MAX(dw, pp_avs_context->dest_w);
2396 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2397 pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2398 pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2399 pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2400 pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2402 gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2404 dst_surface->flags = src_surface->flags;
2406 return VA_STATUS_SUCCESS;
2410 pp_dndi_x_steps(void *private_context)
2416 pp_dndi_y_steps(void *private_context)
2418 struct pp_dndi_context *pp_dndi_context = private_context;
2420 return pp_dndi_context->dest_h / 4;
2424 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2426 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2428 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2429 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2435 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2436 const struct i965_surface *src_surface,
2437 const VARectangle *src_rect,
2438 struct i965_surface *dst_surface,
2439 const VARectangle *dst_rect,
2442 struct i965_driver_data *i965 = i965_driver_data(ctx);
2443 struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2444 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2445 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2446 struct object_surface *obj_surface;
2447 struct i965_sampler_dndi *sampler_dndi;
2451 int dndi_top_first = 1;
2453 if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2454 return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2456 if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2462 obj_surface = SURFACE(src_surface->id);
2463 orig_w = obj_surface->orig_width;
2464 orig_h = obj_surface->orig_height;
2465 w = obj_surface->width;
2466 h = obj_surface->height;
2468 if (pp_context->stmm.bo == NULL) {
2469 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2473 assert(pp_context->stmm.bo);
2476 /* source UV surface index 2 */
2477 i965_pp_set_surface_state(ctx, pp_context,
2478 obj_surface->bo, w * h,
2479 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2482 /* source YUV surface index 4 */
2483 i965_pp_set_surface2_state(ctx, pp_context,
2487 SURFACE_FORMAT_PLANAR_420_8, 1,
2490 /* source STMM surface index 20 */
2491 i965_pp_set_surface_state(ctx, pp_context,
2492 pp_context->stmm.bo, 0,
2493 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2496 /* destination surface */
2497 obj_surface = SURFACE(dst_surface->id);
2498 orig_w = obj_surface->orig_width;
2499 orig_h = obj_surface->orig_height;
2500 w = obj_surface->width;
2501 h = obj_surface->height;
2503 /* destination Y surface index 7 */
2504 i965_pp_set_surface_state(ctx, pp_context,
2506 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2509 /* destination UV surface index 8 */
2510 i965_pp_set_surface_state(ctx, pp_context,
2511 obj_surface->bo, w * h,
2512 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2515 dri_bo_map(pp_context->sampler_state_table.bo, True);
2516 assert(pp_context->sampler_state_table.bo->virtual);
2517 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2518 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2520 /* sample dndi index 1 */
2522 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2523 sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8
2524 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2525 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2527 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2528 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2529 sampler_dndi[index].dw1.stmm_c2 = 1;
2530 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2531 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2533 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15; // 0-31
2534 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15
2535 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15
2536 sampler_dndi[index].dw2.good_neighbor_threshold = 4; // 0-63
2538 sampler_dndi[index].dw3.maximum_stmm = 128;
2539 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2540 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2541 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2542 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2544 sampler_dndi[index].dw4.sdi_delta = 8;
2545 sampler_dndi[index].dw4.sdi_threshold = 128;
2546 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2547 sampler_dndi[index].dw4.stmm_shift_up = 0;
2548 sampler_dndi[index].dw4.stmm_shift_down = 0;
2549 sampler_dndi[index].dw4.minimum_stmm = 0;
2551 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2552 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2553 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2554 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2556 sampler_dndi[index].dw6.dn_enable = 1;
2557 sampler_dndi[index].dw6.di_enable = 1;
2558 sampler_dndi[index].dw6.di_partial = 0;
2559 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2560 sampler_dndi[index].dw6.dndi_stream_id = 0;
2561 sampler_dndi[index].dw6.dndi_first_frame = 1;
2562 sampler_dndi[index].dw6.progressive_dn = 0;
2563 sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2564 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2565 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2567 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2568 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2569 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2570 sampler_dndi[index].dw7.column_width_minus1 = 0;
2572 dri_bo_unmap(pp_context->sampler_state_table.bo);
2574 /* private function & data */
2575 pp_context->pp_x_steps = pp_dndi_x_steps;
2576 pp_context->pp_y_steps = pp_dndi_y_steps;
2577 pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2579 pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2580 pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2581 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2582 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2584 pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */
2585 pp_inline_parameter->grf5.number_blocks = w / 16;
2586 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2587 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2589 pp_dndi_context->dest_w = w;
2590 pp_dndi_context->dest_h = h;
2592 dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2594 return VA_STATUS_SUCCESS;
2598 pp_dn_x_steps(void *private_context)
2604 pp_dn_y_steps(void *private_context)
2606 struct pp_dn_context *pp_dn_context = private_context;
2608 return pp_dn_context->dest_h / 8;
2612 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2614 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2616 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2617 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2623 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2624 const struct i965_surface *src_surface,
2625 const VARectangle *src_rect,
2626 struct i965_surface *dst_surface,
2627 const VARectangle *dst_rect,
2630 struct i965_driver_data *i965 = i965_driver_data(ctx);
2631 struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2632 struct object_surface *obj_surface;
2633 struct i965_sampler_dndi *sampler_dndi;
2634 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2635 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2636 VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2640 int dn_strength = 15;
2641 int dndi_top_first = 1;
2642 int dn_progressive = 0;
2644 if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2647 } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2655 if (dn_filter_param) {
2656 float value = dn_filter_param->value;
2664 dn_strength = (int)(value * 31.0F);
2668 obj_surface = SURFACE(src_surface->id);
2669 orig_w = obj_surface->orig_width;
2670 orig_h = obj_surface->orig_height;
2671 w = obj_surface->width;
2672 h = obj_surface->height;
2674 if (pp_context->stmm.bo == NULL) {
2675 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2679 assert(pp_context->stmm.bo);
2682 /* source UV surface index 2 */
2683 i965_pp_set_surface_state(ctx, pp_context,
2684 obj_surface->bo, w * h,
2685 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2688 /* source YUV surface index 4 */
2689 i965_pp_set_surface2_state(ctx, pp_context,
2693 SURFACE_FORMAT_PLANAR_420_8, 1,
2696 /* source STMM surface index 20 */
2697 i965_pp_set_surface_state(ctx, pp_context,
2698 pp_context->stmm.bo, 0,
2699 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2702 /* destination surface */
2703 obj_surface = SURFACE(dst_surface->id);
2704 orig_w = obj_surface->orig_width;
2705 orig_h = obj_surface->orig_height;
2706 w = obj_surface->width;
2707 h = obj_surface->height;
2709 /* destination Y surface index 7 */
2710 i965_pp_set_surface_state(ctx, pp_context,
2712 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2715 /* destination UV surface index 8 */
2716 i965_pp_set_surface_state(ctx, pp_context,
2717 obj_surface->bo, w * h,
2718 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2721 dri_bo_map(pp_context->sampler_state_table.bo, True);
2722 assert(pp_context->sampler_state_table.bo->virtual);
2723 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2724 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2726 /* sample dndi index 1 */
2728 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2729 sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8
2730 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2731 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2733 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2734 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2735 sampler_dndi[index].dw1.stmm_c2 = 0;
2736 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2737 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2739 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31
2740 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15
2741 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15
2742 sampler_dndi[index].dw2.good_neighbor_threshold = 7; // 0-63
2744 sampler_dndi[index].dw3.maximum_stmm = 128;
2745 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2746 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2747 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2748 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2750 sampler_dndi[index].dw4.sdi_delta = 8;
2751 sampler_dndi[index].dw4.sdi_threshold = 128;
2752 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2753 sampler_dndi[index].dw4.stmm_shift_up = 0;
2754 sampler_dndi[index].dw4.stmm_shift_down = 0;
2755 sampler_dndi[index].dw4.minimum_stmm = 0;
2757 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2758 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2759 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2760 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2762 sampler_dndi[index].dw6.dn_enable = 1;
2763 sampler_dndi[index].dw6.di_enable = 0;
2764 sampler_dndi[index].dw6.di_partial = 0;
2765 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2766 sampler_dndi[index].dw6.dndi_stream_id = 1;
2767 sampler_dndi[index].dw6.dndi_first_frame = 1;
2768 sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2769 sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2770 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2771 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2773 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2774 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2775 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2776 sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2778 dri_bo_unmap(pp_context->sampler_state_table.bo);
2780 /* private function & data */
2781 pp_context->pp_x_steps = pp_dn_x_steps;
2782 pp_context->pp_y_steps = pp_dn_y_steps;
2783 pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2785 pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2786 pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2787 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2788 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2790 pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */
2791 pp_inline_parameter->grf5.number_blocks = w / 16;
2792 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2793 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2795 pp_dn_context->dest_w = w;
2796 pp_dn_context->dest_h = h;
2798 dst_surface->flags = src_surface->flags;
2800 return VA_STATUS_SUCCESS;
2804 gen7_pp_dndi_x_steps(void *private_context)
2806 struct pp_dndi_context *pp_dndi_context = private_context;
2808 return pp_dndi_context->dest_w / 16;
2812 gen7_pp_dndi_y_steps(void *private_context)
2814 struct pp_dndi_context *pp_dndi_context = private_context;
2816 return pp_dndi_context->dest_h / 4;
2820 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2822 struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2824 pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2825 pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2831 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2832 const struct i965_surface *src_surface,
2833 const VARectangle *src_rect,
2834 struct i965_surface *dst_surface,
2835 const VARectangle *dst_rect,
2838 struct i965_driver_data *i965 = i965_driver_data(ctx);
2839 struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2840 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2841 struct object_surface *obj_surface;
2842 struct gen7_sampler_dndi *sampler_dndi;
2846 int dndi_top_first = 1;
2848 if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2849 return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2851 if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2857 obj_surface = SURFACE(src_surface->id);
2858 orig_w = obj_surface->orig_width;
2859 orig_h = obj_surface->orig_height;
2860 w = obj_surface->width;
2861 h = obj_surface->height;
2863 if (pp_context->stmm.bo == NULL) {
2864 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2868 assert(pp_context->stmm.bo);
2871 /* source UV surface index 1 */
2872 gen7_pp_set_surface_state(ctx, pp_context,
2873 obj_surface->bo, w * h,
2874 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2877 /* source YUV surface index 3 */
2878 gen7_pp_set_surface2_state(ctx, pp_context,
2882 SURFACE_FORMAT_PLANAR_420_8, 1,
2885 /* source (temporal reference) YUV surface index 4 */
2886 gen7_pp_set_surface2_state(ctx, pp_context,
2890 SURFACE_FORMAT_PLANAR_420_8, 1,
2893 /* STMM / History Statistics input surface, index 5 */
2894 gen7_pp_set_surface_state(ctx, pp_context,
2895 pp_context->stmm.bo, 0,
2896 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2899 /* destination surface */
2900 obj_surface = SURFACE(dst_surface->id);
2901 orig_w = obj_surface->orig_width;
2902 orig_h = obj_surface->orig_height;
2903 w = obj_surface->width;
2904 h = obj_surface->height;
2906 /* destination(Previous frame) Y surface index 27 */
2907 gen7_pp_set_surface_state(ctx, pp_context,
2909 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2912 /* destination(Previous frame) UV surface index 28 */
2913 gen7_pp_set_surface_state(ctx, pp_context,
2914 obj_surface->bo, w * h,
2915 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2918 /* destination(Current frame) Y surface index 30 */
2919 gen7_pp_set_surface_state(ctx, pp_context,
2921 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2924 /* destination(Current frame) UV surface index 31 */
2925 gen7_pp_set_surface_state(ctx, pp_context,
2926 obj_surface->bo, w * h,
2927 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2930 /* STMM output surface, index 33 */
2931 gen7_pp_set_surface_state(ctx, pp_context,
2932 pp_context->stmm.bo, 0,
2933 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2938 dri_bo_map(pp_context->sampler_state_table.bo, True);
2939 assert(pp_context->sampler_state_table.bo->virtual);
2940 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2941 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2943 /* sample dndi index 0 */
2945 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2946 sampler_dndi[index].dw0.dnmh_delt = 8;
2947 sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2948 sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2949 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2950 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2952 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2953 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2954 sampler_dndi[index].dw1.stmm_c2 = 0;
2955 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2956 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2958 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15; // 0-31
2959 sampler_dndi[index].dw2.bne_edge_th = 1;
2960 sampler_dndi[index].dw2.smooth_mv_th = 0;
2961 sampler_dndi[index].dw2.sad_tight_th = 5;
2962 sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2963 sampler_dndi[index].dw2.good_neighbor_th = 4;
2965 sampler_dndi[index].dw3.maximum_stmm = 128;
2966 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2967 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2968 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2969 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2971 sampler_dndi[index].dw4.sdi_delta = 8;
2972 sampler_dndi[index].dw4.sdi_threshold = 128;
2973 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2974 sampler_dndi[index].dw4.stmm_shift_up = 0;
2975 sampler_dndi[index].dw4.stmm_shift_down = 0;
2976 sampler_dndi[index].dw4.minimum_stmm = 0;
2978 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2979 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2980 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2981 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2983 sampler_dndi[index].dw6.dn_enable = 0;
2984 sampler_dndi[index].dw6.di_enable = 1;
2985 sampler_dndi[index].dw6.di_partial = 0;
2986 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2987 sampler_dndi[index].dw6.dndi_stream_id = 1;
2988 sampler_dndi[index].dw6.dndi_first_frame = 1;
2989 sampler_dndi[index].dw6.progressive_dn = 0;
2990 sampler_dndi[index].dw6.mcdi_enable = 0;
2991 sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2992 sampler_dndi[index].dw6.cat_th1 = 0;
2993 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2994 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2996 sampler_dndi[index].dw7.sad_tha = 5;
2997 sampler_dndi[index].dw7.sad_thb = 10;
2998 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2999 sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3000 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3001 sampler_dndi[index].dw7.vdi_walker_enable = 0;
3002 sampler_dndi[index].dw7.neighborpixel_th = 10;
3003 sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3005 dri_bo_unmap(pp_context->sampler_state_table.bo);
3007 /* private function & data */
3008 pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3009 pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3010 pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3012 pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3013 pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3014 pp_static_parameter->grf1.di_top_field_first = 0;
3015 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3017 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3018 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3019 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3021 pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3022 pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3024 pp_dndi_context->dest_w = w;
3025 pp_dndi_context->dest_h = h;
3027 dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3029 return VA_STATUS_SUCCESS;
3033 gen7_pp_dn_x_steps(void *private_context)
3039 gen7_pp_dn_y_steps(void *private_context)
3041 struct pp_dn_context *pp_dn_context = private_context;
3043 return pp_dn_context->dest_h / 4;
3047 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3049 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3051 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3052 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3058 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3059 const struct i965_surface *src_surface,
3060 const VARectangle *src_rect,
3061 struct i965_surface *dst_surface,
3062 const VARectangle *dst_rect,
3065 struct i965_driver_data *i965 = i965_driver_data(ctx);
3066 struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3067 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3068 struct object_surface *obj_surface;
3069 struct gen7_sampler_dndi *sampler_dn;
3070 VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3074 int dn_strength = 15;
3075 int dndi_top_first = 1;
3076 int dn_progressive = 0;
3078 if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3081 } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3089 if (dn_filter_param) {
3090 float value = dn_filter_param->value;
3098 dn_strength = (int)(value * 31.0F);
3102 obj_surface = SURFACE(src_surface->id);
3103 orig_w = obj_surface->orig_width;
3104 orig_h = obj_surface->orig_height;
3105 w = obj_surface->width;
3106 h = obj_surface->height;
3108 if (pp_context->stmm.bo == NULL) {
3109 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3113 assert(pp_context->stmm.bo);
3116 /* source UV surface index 1 */
3117 gen7_pp_set_surface_state(ctx, pp_context,
3118 obj_surface->bo, w * h,
3119 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3122 /* source YUV surface index 3 */
3123 gen7_pp_set_surface2_state(ctx, pp_context,
3127 SURFACE_FORMAT_PLANAR_420_8, 1,
3130 /* source STMM surface index 5 */
3131 gen7_pp_set_surface_state(ctx, pp_context,
3132 pp_context->stmm.bo, 0,
3133 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3136 /* destination surface */
3137 obj_surface = SURFACE(dst_surface->id);
3138 orig_w = obj_surface->orig_width;
3139 orig_h = obj_surface->orig_height;
3140 w = obj_surface->width;
3141 h = obj_surface->height;
3143 /* destination Y surface index 7 */
3144 gen7_pp_set_surface_state(ctx, pp_context,
3146 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3149 /* destination UV surface index 8 */
3150 gen7_pp_set_surface_state(ctx, pp_context,
3151 obj_surface->bo, w * h,
3152 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3155 dri_bo_map(pp_context->sampler_state_table.bo, True);
3156 assert(pp_context->sampler_state_table.bo->virtual);
3157 assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3158 sampler_dn = pp_context->sampler_state_table.bo->virtual;
3160 /* sample dn index 1 */
3162 sampler_dn[index].dw0.denoise_asd_threshold = 0;
3163 sampler_dn[index].dw0.dnmh_delt = 8;
3164 sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3165 sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3166 sampler_dn[index].dw0.denoise_maximum_history = 128; // 128-240
3167 sampler_dn[index].dw0.denoise_stad_threshold = 0;
3169 sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3170 sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3171 sampler_dn[index].dw1.stmm_c2 = 0;
3172 sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3173 sampler_dn[index].dw1.temporal_difference_threshold = 16;
3175 sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31
3176 sampler_dn[index].dw2.bne_edge_th = 1;
3177 sampler_dn[index].dw2.smooth_mv_th = 0;
3178 sampler_dn[index].dw2.sad_tight_th = 5;
3179 sampler_dn[index].dw2.cat_slope_minus1 = 9;
3180 sampler_dn[index].dw2.good_neighbor_th = 4;
3182 sampler_dn[index].dw3.maximum_stmm = 128;
3183 sampler_dn[index].dw3.multipler_for_vecm = 2;
3184 sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3185 sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3186 sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3188 sampler_dn[index].dw4.sdi_delta = 8;
3189 sampler_dn[index].dw4.sdi_threshold = 128;
3190 sampler_dn[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
3191 sampler_dn[index].dw4.stmm_shift_up = 0;
3192 sampler_dn[index].dw4.stmm_shift_down = 0;
3193 sampler_dn[index].dw4.minimum_stmm = 0;
3195 sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3196 sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3197 sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3198 sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3200 sampler_dn[index].dw6.dn_enable = 1;
3201 sampler_dn[index].dw6.di_enable = 0;
3202 sampler_dn[index].dw6.di_partial = 0;
3203 sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3204 sampler_dn[index].dw6.dndi_stream_id = 1;
3205 sampler_dn[index].dw6.dndi_first_frame = 1;
3206 sampler_dn[index].dw6.progressive_dn = dn_progressive;
3207 sampler_dn[index].dw6.mcdi_enable = 0;
3208 sampler_dn[index].dw6.fmd_tear_threshold = 32;
3209 sampler_dn[index].dw6.cat_th1 = 0;
3210 sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3211 sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3213 sampler_dn[index].dw7.sad_tha = 5;
3214 sampler_dn[index].dw7.sad_thb = 10;
3215 sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3216 sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3217 sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3218 sampler_dn[index].dw7.vdi_walker_enable = 0;
3219 sampler_dn[index].dw7.neighborpixel_th = 10;
3220 sampler_dn[index].dw7.column_width_minus1 = w / 16;
3222 dri_bo_unmap(pp_context->sampler_state_table.bo);
3224 /* private function & data */
3225 pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3226 pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3227 pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3229 pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3230 pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3231 pp_static_parameter->grf1.di_top_field_first = 0;
3232 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3234 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3235 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3236 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3238 pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3239 pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3241 pp_dn_context->dest_w = w;
3242 pp_dn_context->dest_h = h;
3244 dst_surface->flags = src_surface->flags;
3246 return VA_STATUS_SUCCESS;
3250 ironlake_pp_initialize(
3251 VADriverContextP ctx,
3252 struct i965_post_processing_context *pp_context,
3253 const struct i965_surface *src_surface,
3254 const VARectangle *src_rect,
3255 struct i965_surface *dst_surface,
3256 const VARectangle *dst_rect,
3262 struct i965_driver_data *i965 = i965_driver_data(ctx);
3263 struct pp_module *pp_module;
3265 int static_param_size, inline_param_size;
3267 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3268 bo = dri_bo_alloc(i965->intel.bufmgr,
3269 "surface state & binding table",
3270 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3273 pp_context->surface_state_binding_table.bo = bo;
3275 dri_bo_unreference(pp_context->curbe.bo);
3276 bo = dri_bo_alloc(i965->intel.bufmgr,
3281 pp_context->curbe.bo = bo;
3283 dri_bo_unreference(pp_context->idrt.bo);
3284 bo = dri_bo_alloc(i965->intel.bufmgr,
3285 "interface discriptor",
3286 sizeof(struct i965_interface_descriptor),
3289 pp_context->idrt.bo = bo;
3290 pp_context->idrt.num_interface_descriptors = 0;
3292 dri_bo_unreference(pp_context->sampler_state_table.bo);
3293 bo = dri_bo_alloc(i965->intel.bufmgr,
3294 "sampler state table",
3298 dri_bo_map(bo, True);
3299 memset(bo->virtual, 0, bo->size);
3301 pp_context->sampler_state_table.bo = bo;
3303 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3304 bo = dri_bo_alloc(i965->intel.bufmgr,
3305 "sampler 8x8 state ",
3309 pp_context->sampler_state_table.bo_8x8 = bo;
3311 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3312 bo = dri_bo_alloc(i965->intel.bufmgr,
3313 "sampler 8x8 state ",
3317 pp_context->sampler_state_table.bo_8x8_uv = bo;
3319 dri_bo_unreference(pp_context->vfe_state.bo);
3320 bo = dri_bo_alloc(i965->intel.bufmgr,
3322 sizeof(struct i965_vfe_state),
3325 pp_context->vfe_state.bo = bo;
3327 static_param_size = sizeof(struct pp_static_parameter);
3328 inline_param_size = sizeof(struct pp_inline_parameter);
3330 memset(pp_context->pp_static_parameter, 0, static_param_size);
3331 memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3333 assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3334 pp_context->current_pp = pp_index;
3335 pp_module = &pp_context->pp_modules[pp_index];
3337 if (pp_module->initialize)
3338 va_status = pp_module->initialize(ctx, pp_context,
3345 va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3351 ironlake_post_processing(
3352 VADriverContextP ctx,
3353 struct i965_post_processing_context *pp_context,
3354 const struct i965_surface *src_surface,
3355 const VARectangle *src_rect,
3356 struct i965_surface *dst_surface,
3357 const VARectangle *dst_rect,
3364 va_status = ironlake_pp_initialize(ctx, pp_context,
3372 if (va_status == VA_STATUS_SUCCESS) {
3373 ironlake_pp_states_setup(ctx, pp_context);
3374 ironlake_pp_pipeline_setup(ctx, pp_context);
3382 VADriverContextP ctx,
3383 struct i965_post_processing_context *pp_context,
3384 const struct i965_surface *src_surface,
3385 const VARectangle *src_rect,
3386 struct i965_surface *dst_surface,
3387 const VARectangle *dst_rect,
3393 struct i965_driver_data *i965 = i965_driver_data(ctx);
3394 struct pp_module *pp_module;
3396 int static_param_size, inline_param_size;
3398 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3399 bo = dri_bo_alloc(i965->intel.bufmgr,
3400 "surface state & binding table",
3401 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3404 pp_context->surface_state_binding_table.bo = bo;
3406 dri_bo_unreference(pp_context->curbe.bo);
3407 bo = dri_bo_alloc(i965->intel.bufmgr,
3412 pp_context->curbe.bo = bo;
3414 dri_bo_unreference(pp_context->idrt.bo);
3415 bo = dri_bo_alloc(i965->intel.bufmgr,
3416 "interface discriptor",
3417 sizeof(struct gen6_interface_descriptor_data),
3420 pp_context->idrt.bo = bo;
3421 pp_context->idrt.num_interface_descriptors = 0;
3423 dri_bo_unreference(pp_context->sampler_state_table.bo);
3424 bo = dri_bo_alloc(i965->intel.bufmgr,
3425 "sampler state table",
3429 dri_bo_map(bo, True);
3430 memset(bo->virtual, 0, bo->size);
3432 pp_context->sampler_state_table.bo = bo;
3434 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3435 bo = dri_bo_alloc(i965->intel.bufmgr,
3436 "sampler 8x8 state ",
3440 pp_context->sampler_state_table.bo_8x8 = bo;
3442 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3443 bo = dri_bo_alloc(i965->intel.bufmgr,
3444 "sampler 8x8 state ",
3448 pp_context->sampler_state_table.bo_8x8_uv = bo;
3450 dri_bo_unreference(pp_context->vfe_state.bo);
3451 bo = dri_bo_alloc(i965->intel.bufmgr,
3453 sizeof(struct i965_vfe_state),
3456 pp_context->vfe_state.bo = bo;
3458 if (IS_GEN7(i965->intel.device_id)) {
3459 static_param_size = sizeof(struct gen7_pp_static_parameter);
3460 inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3462 static_param_size = sizeof(struct pp_static_parameter);
3463 inline_param_size = sizeof(struct pp_inline_parameter);
3466 memset(pp_context->pp_static_parameter, 0, static_param_size);
3467 memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3469 assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3470 pp_context->current_pp = pp_index;
3471 pp_module = &pp_context->pp_modules[pp_index];
3473 if (pp_module->initialize)
3474 va_status = pp_module->initialize(ctx, pp_context,
3481 va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3487 gen6_pp_interface_descriptor_table(VADriverContextP ctx,
3488 struct i965_post_processing_context *pp_context)
3490 struct i965_driver_data *i965 = i965_driver_data(ctx);
3491 struct gen6_interface_descriptor_data *desc;
3493 int pp_index = pp_context->current_pp;
3495 bo = pp_context->idrt.bo;
3496 dri_bo_map(bo, True);
3497 assert(bo->virtual);
3499 memset(desc, 0, sizeof(*desc));
3500 desc->desc0.kernel_start_pointer =
3501 pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3502 desc->desc1.single_program_flow = 1;
3503 desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3504 desc->desc2.sampler_count = 1; /* 1 - 4 samplers used */
3505 desc->desc2.sampler_state_pointer =
3506 pp_context->sampler_state_table.bo->offset >> 5;
3507 desc->desc3.binding_table_entry_count = 0;
3508 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3509 desc->desc4.constant_urb_entry_read_offset = 0;
3511 if (IS_GEN7(i965->intel.device_id))
3512 desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3514 desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3516 dri_bo_emit_reloc(bo,
3517 I915_GEM_DOMAIN_INSTRUCTION, 0,
3519 offsetof(struct gen6_interface_descriptor_data, desc0),
3520 pp_context->pp_modules[pp_index].kernel.bo);
3522 dri_bo_emit_reloc(bo,
3523 I915_GEM_DOMAIN_INSTRUCTION, 0,
3524 desc->desc2.sampler_count << 2,
3525 offsetof(struct gen6_interface_descriptor_data, desc2),
3526 pp_context->sampler_state_table.bo);
3529 pp_context->idrt.num_interface_descriptors++;
3533 gen6_pp_upload_constants(VADriverContextP ctx,
3534 struct i965_post_processing_context *pp_context)
3536 struct i965_driver_data *i965 = i965_driver_data(ctx);
3537 unsigned char *constant_buffer;
3540 assert(sizeof(struct pp_static_parameter) == 128);
3541 assert(sizeof(struct gen7_pp_static_parameter) == 192);
3543 if (IS_GEN7(i965->intel.device_id))
3544 param_size = sizeof(struct gen7_pp_static_parameter);
3546 param_size = sizeof(struct pp_static_parameter);
3548 dri_bo_map(pp_context->curbe.bo, 1);
3549 assert(pp_context->curbe.bo->virtual);
3550 constant_buffer = pp_context->curbe.bo->virtual;
3551 memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3552 dri_bo_unmap(pp_context->curbe.bo);
3556 gen6_pp_states_setup(VADriverContextP ctx,
3557 struct i965_post_processing_context *pp_context)
3559 gen6_pp_interface_descriptor_table(ctx, pp_context);
3560 gen6_pp_upload_constants(ctx, pp_context);
3564 gen6_pp_pipeline_select(VADriverContextP ctx,
3565 struct i965_post_processing_context *pp_context)
3567 struct intel_batchbuffer *batch = pp_context->batch;
3569 BEGIN_BATCH(batch, 1);
3570 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3571 ADVANCE_BATCH(batch);
3575 gen6_pp_state_base_address(VADriverContextP ctx,
3576 struct i965_post_processing_context *pp_context)
3578 struct intel_batchbuffer *batch = pp_context->batch;
3580 BEGIN_BATCH(batch, 10);
3581 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3582 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3583 OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3584 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3585 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3586 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3587 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3588 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3589 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3590 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3591 ADVANCE_BATCH(batch);
3595 gen6_pp_vfe_state(VADriverContextP ctx,
3596 struct i965_post_processing_context *pp_context)
3598 struct intel_batchbuffer *batch = pp_context->batch;
3600 BEGIN_BATCH(batch, 8);
3601 OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3602 OUT_BATCH(batch, 0);
3604 (pp_context->urb.num_vfe_entries - 1) << 16 |
3605 pp_context->urb.num_vfe_entries << 8);
3606 OUT_BATCH(batch, 0);
3608 (pp_context->urb.size_vfe_entry * 2) << 16 | /* URB Entry Allocation Size, in 256 bits unit */
3609 (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3610 OUT_BATCH(batch, 0);
3611 OUT_BATCH(batch, 0);
3612 OUT_BATCH(batch, 0);
3613 ADVANCE_BATCH(batch);
3617 gen6_pp_curbe_load(VADriverContextP ctx,
3618 struct i965_post_processing_context *pp_context)
3620 struct intel_batchbuffer *batch = pp_context->batch;
3622 assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3624 BEGIN_BATCH(batch, 4);
3625 OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3626 OUT_BATCH(batch, 0);
3628 pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3630 pp_context->curbe.bo,
3631 I915_GEM_DOMAIN_INSTRUCTION, 0,
3633 ADVANCE_BATCH(batch);
3637 gen6_interface_descriptor_load(VADriverContextP ctx,
3638 struct i965_post_processing_context *pp_context)
3640 struct intel_batchbuffer *batch = pp_context->batch;
3642 BEGIN_BATCH(batch, 4);
3643 OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3644 OUT_BATCH(batch, 0);
3646 pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3648 pp_context->idrt.bo,
3649 I915_GEM_DOMAIN_INSTRUCTION, 0,
3651 ADVANCE_BATCH(batch);
3655 gen6_pp_object_walker(VADriverContextP ctx,
3656 struct i965_post_processing_context *pp_context)
3658 struct i965_driver_data *i965 = i965_driver_data(ctx);
3659 struct intel_batchbuffer *batch = pp_context->batch;
3660 int x, x_steps, y, y_steps;
3661 int param_size, command_length_in_dws;
3662 dri_bo *command_buffer;
3663 unsigned int *command_ptr;
3665 if (IS_GEN7(i965->intel.device_id))
3666 param_size = sizeof(struct gen7_pp_inline_parameter);
3668 param_size = sizeof(struct pp_inline_parameter);
3670 x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3671 y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3672 command_length_in_dws = 6 + (param_size >> 2);
3673 command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3674 "command objects buffer",
3675 command_length_in_dws * 4 * x_steps * y_steps + 8,
3678 dri_bo_map(command_buffer, 1);
3679 command_ptr = command_buffer->virtual;
3681 for (y = 0; y < y_steps; y++) {
3682 for (x = 0; x < x_steps; x++) {
3683 if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3684 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3690 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3691 command_ptr += (param_size >> 2);
3696 if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3699 *command_ptr = MI_BATCH_BUFFER_END;
3701 dri_bo_unmap(command_buffer);
3703 BEGIN_BATCH(batch, 2);
3704 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3705 OUT_RELOC(batch, command_buffer,
3706 I915_GEM_DOMAIN_COMMAND, 0,
3708 ADVANCE_BATCH(batch);
3710 dri_bo_unreference(command_buffer);
3712 /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3713 * will cause control to pass back to ring buffer
3715 intel_batchbuffer_end_atomic(batch);
3716 intel_batchbuffer_flush(batch);
3717 intel_batchbuffer_start_atomic(batch, 0x1000);
3721 gen6_pp_pipeline_setup(VADriverContextP ctx,
3722 struct i965_post_processing_context *pp_context)
3724 struct intel_batchbuffer *batch = pp_context->batch;
3726 intel_batchbuffer_start_atomic(batch, 0x1000);
3727 intel_batchbuffer_emit_mi_flush(batch);
3728 gen6_pp_pipeline_select(ctx, pp_context);
3729 gen6_pp_state_base_address(ctx, pp_context);
3730 gen6_pp_vfe_state(ctx, pp_context);
3731 gen6_pp_curbe_load(ctx, pp_context);
3732 gen6_interface_descriptor_load(ctx, pp_context);
3733 gen6_pp_object_walker(ctx, pp_context);
3734 intel_batchbuffer_end_atomic(batch);
3738 gen6_post_processing(
3739 VADriverContextP ctx,
3740 struct i965_post_processing_context *pp_context,
3741 const struct i965_surface *src_surface,
3742 const VARectangle *src_rect,
3743 struct i965_surface *dst_surface,
3744 const VARectangle *dst_rect,
3751 va_status = gen6_pp_initialize(ctx, pp_context,
3759 if (va_status == VA_STATUS_SUCCESS) {
3760 gen6_pp_states_setup(ctx, pp_context);
3761 gen6_pp_pipeline_setup(ctx, pp_context);
3768 i965_post_processing_internal(
3769 VADriverContextP ctx,
3770 struct i965_post_processing_context *pp_context,
3771 const struct i965_surface *src_surface,
3772 const VARectangle *src_rect,
3773 struct i965_surface *dst_surface,
3774 const VARectangle *dst_rect,
3779 struct i965_driver_data *i965 = i965_driver_data(ctx);
3782 if (IS_GEN6(i965->intel.device_id) ||
3783 IS_GEN7(i965->intel.device_id))
3784 va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3786 va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3792 i965_DestroySurfaces(VADriverContextP ctx,
3793 VASurfaceID *surface_list,
3796 i965_CreateSurfaces(VADriverContextP ctx,
3801 VASurfaceID *surfaces);
3804 rgb_to_yuv(unsigned int argb,
3810 int r = ((argb >> 16) & 0xff);
3811 int g = ((argb >> 8) & 0xff);
3812 int b = ((argb >> 0) & 0xff);
3814 *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3815 *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3816 *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3817 *a = ((argb >> 24) & 0xff);
3821 i965_vpp_clear_surface(VADriverContextP ctx,
3822 struct i965_post_processing_context *pp_context,
3823 VASurfaceID surface,
3826 struct i965_driver_data *i965 = i965_driver_data(ctx);
3827 struct intel_batchbuffer *batch = pp_context->batch;
3828 struct object_surface *obj_surface = SURFACE(surface);
3829 unsigned int blt_cmd, br13;
3830 unsigned int tiling = 0, swizzle = 0;
3832 unsigned char y, u, v, a = 0;
3834 /* Currently only support NV12 surface */
3835 if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3838 rgb_to_yuv(color, &y, &u, &v, &a);
3843 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3844 blt_cmd = XY_COLOR_BLT_CMD;
3845 pitch = obj_surface->width;
3847 if (tiling != I915_TILING_NONE) {
3848 blt_cmd |= XY_COLOR_BLT_DST_TILED;
3856 if (IS_GEN6(i965->intel.device_id) ||
3857 IS_GEN7(i965->intel.device_id)) {
3858 intel_batchbuffer_start_atomic_blt(batch, 48);
3859 BEGIN_BLT_BATCH(batch, 12);
3861 intel_batchbuffer_start_atomic(batch, 48);
3862 BEGIN_BATCH(batch, 12);
3865 OUT_BATCH(batch, blt_cmd);
3866 OUT_BATCH(batch, br13);
3871 obj_surface->height << 16 |
3872 obj_surface->width);
3873 OUT_RELOC(batch, obj_surface->bo,
3874 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3876 OUT_BATCH(batch, y);
3882 OUT_BATCH(batch, blt_cmd);
3883 OUT_BATCH(batch, br13);
3888 obj_surface->height / 2 << 16 |
3889 obj_surface->width / 2);
3890 OUT_RELOC(batch, obj_surface->bo,
3891 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3892 obj_surface->width * obj_surface->y_cb_offset);
3893 OUT_BATCH(batch, v << 8 | u);
3895 ADVANCE_BATCH(batch);
3896 intel_batchbuffer_end_atomic(batch);
3900 i965_post_processing(
3901 VADriverContextP ctx,
3902 VASurfaceID surface,
3903 const VARectangle *src_rect,
3904 const VARectangle *dst_rect,
3906 int *has_done_scaling
3909 struct i965_driver_data *i965 = i965_driver_data(ctx);
3910 VASurfaceID in_surface_id = surface;
3911 VASurfaceID out_surface_id = VA_INVALID_ID;
3913 *has_done_scaling = 0;
3916 struct object_surface *obj_surface;
3918 struct i965_surface src_surface;
3919 struct i965_surface dst_surface;
3921 obj_surface = SURFACE(in_surface_id);
3923 /* Currently only support post processing for NV12 surface */
3924 if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3925 return out_surface_id;
3927 _i965LockMutex(&i965->pp_mutex);
3929 if (flags & I965_PP_FLAG_MCDI) {
3930 status = i965_CreateSurfaces(ctx,
3931 obj_surface->orig_width,
3932 obj_surface->orig_height,
3933 VA_RT_FORMAT_YUV420,
3936 assert(status == VA_STATUS_SUCCESS);
3937 obj_surface = SURFACE(out_surface_id);
3938 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3939 i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3940 src_surface.id = in_surface_id;
3941 src_surface.type = I965_SURFACE_TYPE_SURFACE;
3942 src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3943 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3944 dst_surface.id = out_surface_id;
3945 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3946 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3948 i965_post_processing_internal(ctx, i965->pp_context,
3957 if (flags & I965_PP_FLAG_AVS) {
3958 struct i965_render_state *render_state = &i965->render_state;
3959 struct intel_region *dest_region = render_state->draw_region;
3961 if (out_surface_id != VA_INVALID_ID)
3962 in_surface_id = out_surface_id;
3964 status = i965_CreateSurfaces(ctx,
3966 dest_region->height,
3967 VA_RT_FORMAT_YUV420,
3970 assert(status == VA_STATUS_SUCCESS);
3971 obj_surface = SURFACE(out_surface_id);
3972 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3973 i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3974 src_surface.id = in_surface_id;
3975 src_surface.type = I965_SURFACE_TYPE_SURFACE;
3976 src_surface.flags = I965_SURFACE_FLAG_FRAME;
3977 dst_surface.id = out_surface_id;
3978 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3979 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3981 i965_post_processing_internal(ctx, i965->pp_context,
3989 if (in_surface_id != surface)
3990 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3992 *has_done_scaling = 1;
3995 _i965UnlockMutex(&i965->pp_mutex);
3998 return out_surface_id;
4002 i965_image_pl3_processing(VADriverContextP ctx,
4003 const struct i965_surface *src_surface,
4004 const VARectangle *src_rect,
4005 struct i965_surface *dst_surface,
4006 const VARectangle *dst_rect)
4008 struct i965_driver_data *i965 = i965_driver_data(ctx);
4009 struct i965_post_processing_context *pp_context = i965->pp_context;
4010 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4011 VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4013 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4014 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4019 PP_PL3_LOAD_SAVE_N12,
4021 } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4022 fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4023 fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4024 fourcc == VA_FOURCC('I', '4', '2', '0')) {
4025 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4030 PP_PL3_LOAD_SAVE_PL3,
4032 } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4033 fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4034 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4039 PP_PL3_LOAD_SAVE_PA,
4046 intel_batchbuffer_flush(pp_context->batch);
4052 i965_image_pl2_processing(VADriverContextP ctx,
4053 const struct i965_surface *src_surface,
4054 const VARectangle *src_rect,
4055 struct i965_surface *dst_surface,
4056 const VARectangle *dst_rect)
4058 struct i965_driver_data *i965 = i965_driver_data(ctx);
4059 struct i965_post_processing_context *pp_context = i965->pp_context;
4060 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4061 VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4063 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4064 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4069 PP_NV12_LOAD_SAVE_N12,
4071 } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4072 fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4073 fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4074 fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4075 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4080 PP_NV12_LOAD_SAVE_PL3,
4082 } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4083 fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4084 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4089 PP_NV12_LOAD_SAVE_PA,
4093 intel_batchbuffer_flush(pp_context->batch);
4099 i965_image_pl1_processing(VADriverContextP ctx,
4100 const struct i965_surface *src_surface,
4101 const VARectangle *src_rect,
4102 struct i965_surface *dst_surface,
4103 const VARectangle *dst_rect)
4105 struct i965_driver_data *i965 = i965_driver_data(ctx);
4106 struct i965_post_processing_context *pp_context = i965->pp_context;
4107 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4109 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4110 i965_post_processing_internal(ctx, i965->pp_context,
4115 PP_PA_LOAD_SAVE_NV12,
4118 else if (fourcc == VA_FOURCC_YV12) {
4119 i965_post_processing_internal(ctx, i965->pp_context,
4124 PP_PA_LOAD_SAVE_PL3,
4129 return VA_STATUS_ERROR_UNKNOWN;
4132 intel_batchbuffer_flush(pp_context->batch);
4134 return VA_STATUS_SUCCESS;
4138 i965_image_processing(VADriverContextP ctx,
4139 const struct i965_surface *src_surface,
4140 const VARectangle *src_rect,
4141 struct i965_surface *dst_surface,
4142 const VARectangle *dst_rect)
4144 struct i965_driver_data *i965 = i965_driver_data(ctx);
4145 VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4148 int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4150 _i965LockMutex(&i965->pp_mutex);
4153 case VA_FOURCC('Y', 'V', '1', '2'):
4154 case VA_FOURCC('I', '4', '2', '0'):
4155 case VA_FOURCC('I', 'M', 'C', '1'):
4156 case VA_FOURCC('I', 'M', 'C', '3'):
4157 status = i965_image_pl3_processing(ctx,
4164 case VA_FOURCC('N', 'V', '1', '2'):
4165 status = i965_image_pl2_processing(ctx,
4171 case VA_FOURCC('Y', 'U', 'Y', '2'):
4172 case VA_FOURCC('U', 'Y', 'V', 'Y'):
4173 status = i965_image_pl1_processing(ctx,
4181 status = VA_STATUS_ERROR_UNIMPLEMENTED;
4185 _i965UnlockMutex(&i965->pp_mutex);
4192 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4196 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4197 pp_context->surface_state_binding_table.bo = NULL;
4199 dri_bo_unreference(pp_context->curbe.bo);
4200 pp_context->curbe.bo = NULL;
4202 dri_bo_unreference(pp_context->sampler_state_table.bo);
4203 pp_context->sampler_state_table.bo = NULL;
4205 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4206 pp_context->sampler_state_table.bo_8x8 = NULL;
4208 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4209 pp_context->sampler_state_table.bo_8x8_uv = NULL;
4211 dri_bo_unreference(pp_context->idrt.bo);
4212 pp_context->idrt.bo = NULL;
4213 pp_context->idrt.num_interface_descriptors = 0;
4215 dri_bo_unreference(pp_context->vfe_state.bo);
4216 pp_context->vfe_state.bo = NULL;
4218 dri_bo_unreference(pp_context->stmm.bo);
4219 pp_context->stmm.bo = NULL;
4221 for (i = 0; i < NUM_PP_MODULES; i++) {
4222 struct pp_module *pp_module = &pp_context->pp_modules[i];
4224 dri_bo_unreference(pp_module->kernel.bo);
4225 pp_module->kernel.bo = NULL;
4228 free(pp_context->pp_static_parameter);
4229 free(pp_context->pp_inline_parameter);
4230 pp_context->pp_static_parameter = NULL;
4231 pp_context->pp_inline_parameter = NULL;
4235 i965_post_processing_terminate(VADriverContextP ctx)
4237 struct i965_driver_data *i965 = i965_driver_data(ctx);
4238 struct i965_post_processing_context *pp_context = i965->pp_context;
4241 i965_post_processing_context_finalize(pp_context);
4245 i965->pp_context = NULL;
4251 i965_post_processing_context_init(VADriverContextP ctx,
4252 struct i965_post_processing_context *pp_context,
4253 struct intel_batchbuffer *batch)
4255 struct i965_driver_data *i965 = i965_driver_data(ctx);
4258 pp_context->urb.size = URB_SIZE((&i965->intel));
4259 pp_context->urb.num_vfe_entries = 32;
4260 pp_context->urb.size_vfe_entry = 1; /* in 512 bits unit */
4261 pp_context->urb.num_cs_entries = 1;
4263 if (IS_GEN7(i965->intel.device_id))
4264 pp_context->urb.size_cs_entry = 4; /* in 512 bits unit */
4266 pp_context->urb.size_cs_entry = 2;
4268 pp_context->urb.vfe_start = 0;
4269 pp_context->urb.cs_start = pp_context->urb.vfe_start +
4270 pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4271 assert(pp_context->urb.cs_start +
4272 pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4274 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4275 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4276 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4278 if (IS_GEN7(i965->intel.device_id))
4279 memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4280 else if (IS_GEN6(i965->intel.device_id))
4281 memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4282 else if (IS_IRONLAKE(i965->intel.device_id))
4283 memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4285 for (i = 0; i < NUM_PP_MODULES; i++) {
4286 struct pp_module *pp_module = &pp_context->pp_modules[i];
4287 dri_bo_unreference(pp_module->kernel.bo);
4288 if (pp_module->kernel.bin && pp_module->kernel.size) {
4289 pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4290 pp_module->kernel.name,
4291 pp_module->kernel.size,
4293 assert(pp_module->kernel.bo);
4294 dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4296 pp_module->kernel.bo = NULL;
4300 /* static & inline parameters */
4301 if (IS_GEN7(i965->intel.device_id)) {
4302 pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4303 pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4305 pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4306 pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4309 pp_context->batch = batch;
4313 i965_post_processing_init(VADriverContextP ctx)
4315 struct i965_driver_data *i965 = i965_driver_data(ctx);
4316 struct i965_post_processing_context *pp_context = i965->pp_context;
4319 if (pp_context == NULL) {
4320 pp_context = calloc(1, sizeof(*pp_context));
4321 i965_post_processing_context_init(ctx, pp_context, i965->batch);
4322 i965->pp_context = pp_context;
4329 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4330 PP_NULL, /* VAProcFilterNone */
4331 PP_NV12_DN, /* VAProcFilterNoiseReduction */
4332 PP_NULL, /* VAProcFilterDeblocking */
4333 PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4334 PP_NULL, /* VAProcFilterSharpening */
4335 PP_NULL, /* VAProcFilterColorBalance */
4336 PP_NULL, /* VAProcFilterColorStandard */
4337 PP_NULL, /* VAProcFilterFrameRateConversion */
4340 static const int proc_frame_to_pp_frame[3] = {
4341 I965_SURFACE_FLAG_FRAME,
4342 I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4343 I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4347 i965_proc_picture(VADriverContextP ctx,
4349 union codec_state *codec_state,
4350 struct hw_context *hw_context)
4352 struct i965_driver_data *i965 = i965_driver_data(ctx);
4353 struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4354 struct proc_state *proc_state = &codec_state->proc;
4355 VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4356 struct object_surface *obj_surface;
4357 struct i965_surface src_surface, dst_surface;
4358 VARectangle src_rect, dst_rect;
4361 VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4362 int num_tmp_surfaces = 0;
4363 unsigned int tiling = 0, swizzle = 0;
4364 int in_width, in_height;
4366 assert(pipeline_param->surface != VA_INVALID_ID);
4367 assert(proc_state->current_render_target != VA_INVALID_ID);
4369 obj_surface = SURFACE(pipeline_param->surface);
4370 in_width = obj_surface->orig_width;
4371 in_height = obj_surface->orig_height;
4372 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4374 src_surface.id = pipeline_param->surface;
4375 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4376 src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4378 if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4379 VASurfaceID out_surface_id = VA_INVALID_ID;
4381 src_surface.id = pipeline_param->surface;
4382 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4383 src_surface.flags = I965_SURFACE_FLAG_FRAME;
4386 src_rect.width = in_width;
4387 src_rect.height = in_height;
4389 status = i965_CreateSurfaces(ctx,
4392 VA_RT_FORMAT_YUV420,
4395 assert(status == VA_STATUS_SUCCESS);
4396 tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4397 obj_surface = SURFACE(out_surface_id);
4398 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4400 dst_surface.id = out_surface_id;
4401 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4402 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4405 dst_rect.width = in_width;
4406 dst_rect.height = in_height;
4408 status = i965_image_processing(ctx,
4413 assert(status == VA_STATUS_SUCCESS);
4415 src_surface.id = out_surface_id;
4416 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4417 src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4420 if (pipeline_param->surface_region) {
4421 src_rect.x = pipeline_param->surface_region->x;
4422 src_rect.y = pipeline_param->surface_region->y;
4423 src_rect.width = pipeline_param->surface_region->width;
4424 src_rect.height = pipeline_param->surface_region->height;
4428 src_rect.width = in_width;
4429 src_rect.height = in_height;
4432 if (pipeline_param->output_region) {
4433 dst_rect.x = pipeline_param->output_region->x;
4434 dst_rect.y = pipeline_param->output_region->y;
4435 dst_rect.width = pipeline_param->output_region->width;
4436 dst_rect.height = pipeline_param->output_region->height;
4440 dst_rect.width = in_width;
4441 dst_rect.height = in_height;
4444 obj_surface = SURFACE(proc_state->current_render_target);
4445 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4446 i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4448 for (i = 0; i < pipeline_param->num_filters; i++) {
4449 struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4450 VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4451 VAProcFilterType filter_type = filter_param->type;
4452 VASurfaceID out_surface_id = VA_INVALID_ID;
4453 int kernel_index = procfilter_to_pp_flag[filter_type];
4455 if (kernel_index != PP_NULL &&
4456 proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4457 status = i965_CreateSurfaces(ctx,
4460 VA_RT_FORMAT_YUV420,
4463 assert(status == VA_STATUS_SUCCESS);
4464 tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4465 obj_surface = SURFACE(out_surface_id);
4466 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4467 dst_surface.id = out_surface_id;
4468 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4469 status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4477 if (status == VA_STATUS_SUCCESS) {
4478 src_surface.id = dst_surface.id;
4479 src_surface.type = dst_surface.type;
4480 src_surface.flags = dst_surface.flags;
4485 dst_surface.id = proc_state->current_render_target;
4486 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4488 if (src_rect.width == dst_rect.width &&
4489 src_rect.height == dst_rect.height) {
4490 i965_post_processing_internal(ctx, &proc_context->pp_context,
4495 PP_NV12_LOAD_SAVE_N12,
4499 i965_post_processing_internal(ctx, &proc_context->pp_context,
4504 (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4505 PP_NV12_AVS : PP_NV12_SCALING,
4509 if (num_tmp_surfaces)
4510 i965_DestroySurfaces(ctx,
4514 intel_batchbuffer_flush(hw_context->batch);
4518 i965_proc_context_destroy(void *hw_context)
4520 struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4522 i965_post_processing_context_finalize(&proc_context->pp_context);
4523 intel_batchbuffer_free(proc_context->base.batch);
4528 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4530 struct intel_driver_data *intel = intel_driver_data(ctx);
4531 struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4533 proc_context->base.destroy = i965_proc_context_destroy;
4534 proc_context->base.run = i965_proc_picture;
4535 proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4536 i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4538 return (struct hw_context *)proc_context;