src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 111                                    const struct i965_surface *src_surface,
 112                                    const VARectangle *src_rect,
 113                                    struct i965_surface *dst_surface,
 114                                    const VARectangle *dst_rect,
 115                                    void *filter_param);
 116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 117                                             const struct i965_surface *src_surface,
 118                                             const VARectangle *src_rect,
 119                                             struct i965_surface *dst_surface,
 120                                             const VARectangle *dst_rect,
 121                                             void *filter_param);
 122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 123                                            const struct i965_surface *src_surface,
 124                                            const VARectangle *src_rect,
 125                                            struct i965_surface *dst_surface,
 126                                            const VARectangle *dst_rect,
 127                                            void *filter_param);
 128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 129                                              const struct i965_surface *src_surface,
 130                                              const VARectangle *src_rect,
 131                                              struct i965_surface *dst_surface,
 132                                              const VARectangle *dst_rect,
 133                                              void *filter_param);
 134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 135                                                 const struct i965_surface *src_surface,
 136                                                 const VARectangle *src_rect,
 137                                                 struct i965_surface *dst_surface,
 138                                                 const VARectangle *dst_rect,
 139                                                 void *filter_param);
 140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 141                                         const struct i965_surface *src_surface,
 142                                         const VARectangle *src_rect,
 143                                         struct i965_surface *dst_surface,
 144                                         const VARectangle *dst_rect,
 145                                         void *filter_param);
 146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 147                                       const struct i965_surface *src_surface,
 148                                       const VARectangle *src_rect,
 149                                       struct i965_surface *dst_surface,
 150                                       const VARectangle *dst_rect,
 151                                       void *filter_param);
 152
 153 static struct pp_module pp_modules_gen5[] = {
 154     {
 155         {
 156             "NULL module (for testing)",
 157             PP_NULL,
 158             pp_null_gen5,
 159             sizeof(pp_null_gen5),
 160             NULL,
 161         },
 162
 163         pp_null_initialize,
 164     },
 165
 166     {
 167         {
 168             "NV12_NV12",
 169             PP_NV12_LOAD_SAVE_N12,
 170             pp_nv12_load_save_nv12_gen5,
 171             sizeof(pp_nv12_load_save_nv12_gen5),
 172             NULL,
 173         },
 174
 175         pp_plx_load_save_plx_initialize,
 176     },
 177
 178     {
 179         {
 180             "NV12_PL3",
 181             PP_NV12_LOAD_SAVE_PL3,
 182             pp_nv12_load_save_pl3_gen5,
 183             sizeof(pp_nv12_load_save_pl3_gen5),
 184             NULL,
 185         },
 186
 187         pp_plx_load_save_plx_initialize,
 188     },
 189
 190     {
 191         {
 192             "PL3_NV12",
 193             PP_PL3_LOAD_SAVE_N12,
 194             pp_pl3_load_save_nv12_gen5,
 195             sizeof(pp_pl3_load_save_nv12_gen5),
 196             NULL,
 197         },
 198
 199         pp_plx_load_save_plx_initialize,
 200     },
 201
 202     {
 203         {
 204             "PL3_PL3",
 205             PP_PL3_LOAD_SAVE_N12,
 206             pp_pl3_load_save_pl3_gen5,
 207             sizeof(pp_pl3_load_save_pl3_gen5),
 208             NULL,
 209         },
 210
 211         pp_plx_load_save_plx_initialize
 212     },
 213
 214     {
 215         {
 216             "NV12 Scaling module",
 217             PP_NV12_SCALING,
 218             pp_nv12_scaling_gen5,
 219             sizeof(pp_nv12_scaling_gen5),
 220             NULL,
 221         },
 222
 223         pp_nv12_scaling_initialize,
 224     },
 225
 226     {
 227         {
 228             "NV12 AVS module",
 229             PP_NV12_AVS,
 230             pp_nv12_avs_gen5,
 231             sizeof(pp_nv12_avs_gen5),
 232             NULL,
 233         },
 234
 235         pp_nv12_avs_initialize_nlas,
 236     },
 237
 238     {
 239         {
 240             "NV12 DNDI module",
 241             PP_NV12_DNDI,
 242             pp_nv12_dndi_gen5,
 243             sizeof(pp_nv12_dndi_gen5),
 244             NULL,
 245         },
 246
 247         pp_nv12_dndi_initialize,
 248     },
 249
 250     {
 251         {
 252             "NV12 DN module",
 253             PP_NV12_DN,
 254             pp_nv12_dn_gen5,
 255             sizeof(pp_nv12_dn_gen5),
 256             NULL,
 257         },
 258
 259         pp_nv12_dn_initialize,
 260     },
 261
 262     {
 263         {
 264             "NV12_PA module",
 265             PP_NV12_LOAD_SAVE_PA,
 266             pp_nv12_load_save_pa_gen5,
 267             sizeof(pp_nv12_load_save_pa_gen5),
 268             NULL,
 269         },
 270
 271         pp_plx_load_save_plx_initialize,
 272     },
 273
 274     {
 275         {
 276             "PL3_PA module",
 277             PP_PL3_LOAD_SAVE_PA,
 278             pp_pl3_load_save_pa_gen5,
 279             sizeof(pp_pl3_load_save_pa_gen5),
 280             NULL,
 281         },
 282
 283         pp_plx_load_save_plx_initialize,
 284     },
 285
 286     {
 287         {
 288             "PA_NV12 module",
 289             PP_PA_LOAD_SAVE_NV12,
 290             pp_pa_load_save_nv12_gen5,
 291             sizeof(pp_pa_load_save_nv12_gen5),
 292             NULL,
 293         },
 294
 295         pp_plx_load_save_plx_initialize,
 296     },
 297
 298     {
 299         {
 300             "PA_PL3 module",
 301             PP_PA_LOAD_SAVE_PL3,
 302             pp_pa_load_save_pl3_gen5,
 303             sizeof(pp_pa_load_save_pl3_gen5),
 304             NULL,
 305         },
 306
 307         pp_plx_load_save_plx_initialize,
 308     },
 309
 310 };
 311
 312 static const uint32_t pp_null_gen6[][4] = {
 313 #include "shaders/post_processing/gen5_6/null.g6b"
 314 };
 315
 316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 318 };
 319
 320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 322 };
 323
 324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 326 };
 327
 328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 330 };
 331
 332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 334 };
 335
 336 static const uint32_t pp_nv12_avs_gen6[][4] = {
 337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 338 };
 339
 340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 342 };
 343
 344 static const uint32_t pp_nv12_dn_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 350 };
 351
 352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 354 };
 355
 356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 362 };
 363
 364 static struct pp_module pp_modules_gen6[] = {
 365     {
 366         {
 367             "NULL module (for testing)",
 368             PP_NULL,
 369             pp_null_gen6,
 370             sizeof(pp_null_gen6),
 371             NULL,
 372         },
 373
 374         pp_null_initialize,
 375     },
 376
 377     {
 378         {
 379             "NV12_NV12",
 380             PP_NV12_LOAD_SAVE_N12,
 381             pp_nv12_load_save_nv12_gen6,
 382             sizeof(pp_nv12_load_save_nv12_gen6),
 383             NULL,
 384         },
 385
 386         pp_plx_load_save_plx_initialize,
 387     },
 388
 389     {
 390         {
 391             "NV12_PL3",
 392             PP_NV12_LOAD_SAVE_PL3,
 393             pp_nv12_load_save_pl3_gen6,
 394             sizeof(pp_nv12_load_save_pl3_gen6),
 395             NULL,
 396         },
 397
 398         pp_plx_load_save_plx_initialize,
 399     },
 400
 401     {
 402         {
 403             "PL3_NV12",
 404             PP_PL3_LOAD_SAVE_N12,
 405             pp_pl3_load_save_nv12_gen6,
 406             sizeof(pp_pl3_load_save_nv12_gen6),
 407             NULL,
 408         },
 409
 410         pp_plx_load_save_plx_initialize,
 411     },
 412
 413     {
 414         {
 415             "PL3_PL3",
 416             PP_PL3_LOAD_SAVE_N12,
 417             pp_pl3_load_save_pl3_gen6,
 418             sizeof(pp_pl3_load_save_pl3_gen6),
 419             NULL,
 420         },
 421
 422         pp_plx_load_save_plx_initialize,
 423     },
 424
 425     {
 426         {
 427             "NV12 Scaling module",
 428             PP_NV12_SCALING,
 429             pp_nv12_scaling_gen6,
 430             sizeof(pp_nv12_scaling_gen6),
 431             NULL,
 432         },
 433
 434         gen6_nv12_scaling_initialize,
 435     },
 436
 437     {
 438         {
 439             "NV12 AVS module",
 440             PP_NV12_AVS,
 441             pp_nv12_avs_gen6,
 442             sizeof(pp_nv12_avs_gen6),
 443             NULL,
 444         },
 445
 446         pp_nv12_avs_initialize_nlas,
 447     },
 448
 449     {
 450         {
 451             "NV12 DNDI module",
 452             PP_NV12_DNDI,
 453             pp_nv12_dndi_gen6,
 454             sizeof(pp_nv12_dndi_gen6),
 455             NULL,
 456         },
 457
 458         pp_nv12_dndi_initialize,
 459     },
 460
 461     {
 462         {
 463             "NV12 DN module",
 464             PP_NV12_DN,
 465             pp_nv12_dn_gen6,
 466             sizeof(pp_nv12_dn_gen6),
 467             NULL,
 468         },
 469
 470         pp_nv12_dn_initialize,
 471     },
 472     {
 473         {
 474             "NV12_PA module",
 475             PP_NV12_LOAD_SAVE_PA,
 476             pp_nv12_load_save_pa_gen6,
 477             sizeof(pp_nv12_load_save_pa_gen6),
 478             NULL,
 479         },
 480
 481         pp_plx_load_save_plx_initialize,
 482     },
 483
 484     {
 485         {
 486             "PL3_PA module",
 487             PP_PL3_LOAD_SAVE_PA,
 488             pp_pl3_load_save_pa_gen6,
 489             sizeof(pp_pl3_load_save_pa_gen6),
 490             NULL,
 491         },
 492
 493         pp_plx_load_save_plx_initialize,
 494     },
 495
 496     {
 497         {
 498             "PA_NV12 module",
 499             PP_PA_LOAD_SAVE_NV12,
 500             pp_pa_load_save_nv12_gen6,
 501             sizeof(pp_pa_load_save_nv12_gen6),
 502             NULL,
 503         },
 504
 505         pp_plx_load_save_plx_initialize,
 506     },
 507
 508     {
 509         {
 510             "PA_PL3 module",
 511             PP_PA_LOAD_SAVE_PL3,
 512             pp_pa_load_save_pl3_gen6,
 513             sizeof(pp_pa_load_save_pl3_gen6),
 514             NULL,
 515         },
 516
 517         pp_plx_load_save_plx_initialize,
 518     },
 519
 520 };
 521
 522 static const uint32_t pp_null_gen7[][4] = {
 523 };
 524
 525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 527 };
 528
 529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 531 };
 532
 533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 535 };
 536
 537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 539 };
 540
 541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 542 #include "shaders/post_processing/gen7/avs.g7b"
 543 };
 544
 545 static const uint32_t pp_nv12_avs_gen7[][4] = {
 546 #include "shaders/post_processing/gen7/avs.g7b"
 547 };
 548
 549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 550 // #include "shaders/post_processing/gen7/dndi.g7b"
 551 };
 552
 553 static const uint32_t pp_nv12_dn_gen7[][4] = {
 554 };
 555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 556 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 557 };
 558 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 559 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 560 };
 561 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 562 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 563 };
 564 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 565 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 566 };
 567
 568 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 569                                            const struct i965_surface *src_surface,
 570                                            const VARectangle *src_rect,
 571                                            struct i965_surface *dst_surface,
 572                                            const VARectangle *dst_rect,
 573                                            void *filter_param);
 574 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 575                                              const struct i965_surface *src_surface,
 576                                              const VARectangle *src_rect,
 577                                              struct i965_surface *dst_surface,
 578                                              const VARectangle *dst_rect,
 579                                              void *filter_param);
 580 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 581                                            const struct i965_surface *src_surface,
 582                                            const VARectangle *src_rect,
 583                                            struct i965_surface *dst_surface,
 584                                            const VARectangle *dst_rect,
 585                                            void *filter_param);
 586
 587 static struct pp_module pp_modules_gen7[] = {
 588     {
 589         {
 590             "NULL module (for testing)",
 591             PP_NULL,
 592             pp_null_gen7,
 593             sizeof(pp_null_gen7),
 594             NULL,
 595         },
 596
 597         pp_null_initialize,
 598     },
 599
 600     {
 601         {
 602             "NV12_NV12",
 603             PP_NV12_LOAD_SAVE_N12,
 604             pp_nv12_load_save_nv12_gen7,
 605             sizeof(pp_nv12_load_save_nv12_gen7),
 606             NULL,
 607         },
 608
 609         gen7_pp_plx_avs_initialize,
 610     },
 611
 612     {
 613         {
 614             "NV12_PL3",
 615             PP_NV12_LOAD_SAVE_PL3,
 616             pp_nv12_load_save_pl3_gen7,
 617             sizeof(pp_nv12_load_save_pl3_gen7),
 618             NULL,
 619         },
 620
 621         gen7_pp_plx_avs_initialize,
 622     },
 623
 624     {
 625         {
 626             "PL3_NV12",
 627             PP_PL3_LOAD_SAVE_N12,
 628             pp_pl3_load_save_nv12_gen7,
 629             sizeof(pp_pl3_load_save_nv12_gen7),
 630             NULL,
 631         },
 632
 633         gen7_pp_plx_avs_initialize,
 634     },
 635
 636     {
 637         {
 638             "PL3_PL3",
 639             PP_PL3_LOAD_SAVE_N12,
 640             pp_pl3_load_save_pl3_gen7,
 641             sizeof(pp_pl3_load_save_pl3_gen7),
 642             NULL,
 643         },
 644
 645         gen7_pp_plx_avs_initialize,
 646     },
 647
 648     {
 649         {
 650             "NV12 Scaling module",
 651             PP_NV12_SCALING,
 652             pp_nv12_scaling_gen7,
 653             sizeof(pp_nv12_scaling_gen7),
 654             NULL,
 655         },
 656
 657         gen7_pp_plx_avs_initialize,
 658     },
 659
 660     {
 661         {
 662             "NV12 AVS module",
 663             PP_NV12_AVS,
 664             pp_nv12_avs_gen7,
 665             sizeof(pp_nv12_avs_gen7),
 666             NULL,
 667         },
 668
 669         gen7_pp_plx_avs_initialize,
 670     },
 671
 672     {
 673         {
 674             "NV12 DNDI module",
 675             PP_NV12_DNDI,
 676             pp_nv12_dndi_gen7,
 677             sizeof(pp_nv12_dndi_gen7),
 678             NULL,
 679         },
 680
 681         gen7_pp_nv12_dndi_initialize,
 682     },
 683
 684     {
 685         {
 686             "NV12 DN module",
 687             PP_NV12_DN,
 688             pp_nv12_dn_gen7,
 689             sizeof(pp_nv12_dn_gen7),
 690             NULL,
 691         },
 692
 693         gen7_pp_nv12_dn_initialize,
 694     },
 695     {
 696         {
 697             "NV12_PA module",
 698             PP_NV12_LOAD_SAVE_PA,
 699             pp_nv12_load_save_pa_gen7,
 700             sizeof(pp_nv12_load_save_pa_gen7),
 701             NULL,
 702         },
 703
 704         gen7_pp_plx_avs_initialize,
 705     },
 706
 707     {
 708         {
 709             "PL3_PA module",
 710             PP_PL3_LOAD_SAVE_PA,
 711             pp_pl3_load_save_pa_gen7,
 712             sizeof(pp_pl3_load_save_pa_gen7),
 713             NULL,
 714         },
 715
 716         gen7_pp_plx_avs_initialize,
 717     },
 718
 719     {
 720         {
 721             "PA_NV12 module",
 722             PP_PA_LOAD_SAVE_NV12,
 723             pp_pa_load_save_nv12_gen7,
 724             sizeof(pp_pa_load_save_nv12_gen7),
 725             NULL,
 726         },
 727
 728         gen7_pp_plx_avs_initialize,
 729     },
 730
 731     {
 732         {
 733             "PA_PL3 module",
 734             PP_PA_LOAD_SAVE_PL3,
 735             pp_pa_load_save_pl3_gen7,
 736             sizeof(pp_pa_load_save_pl3_gen7),
 737             NULL,
 738         },
 739
 740         gen7_pp_plx_avs_initialize,
 741     },
 742
 743 };
 744
 745 static int
 746 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 747 {
 748     struct i965_driver_data *i965 = i965_driver_data(ctx);
 749     int fourcc;
 750
 751     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 752         struct object_image *obj_image = IMAGE(surface->id);
 753         fourcc = obj_image->image.format.fourcc;
 754     } else {
 755         struct object_surface *obj_surface = SURFACE(surface->id);
 756         fourcc = obj_surface->fourcc;
 757     }
 758
 759     return fourcc;
 760 }
 761
 762 static void
 763 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 764 {
 765     switch (tiling) {
 766     case I915_TILING_NONE:
 767         ss->ss3.tiled_surface = 0;
 768         ss->ss3.tile_walk = 0;
 769         break;
 770     case I915_TILING_X:
 771         ss->ss3.tiled_surface = 1;
 772         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 773         break;
 774     case I915_TILING_Y:
 775         ss->ss3.tiled_surface = 1;
 776         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 777         break;
 778     }
 779 }
 780
 781 static void
 782 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 783 {
 784     switch (tiling) {
 785     case I915_TILING_NONE:
 786         ss->ss2.tiled_surface = 0;
 787         ss->ss2.tile_walk = 0;
 788         break;
 789     case I915_TILING_X:
 790         ss->ss2.tiled_surface = 1;
 791         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 792         break;
 793     case I915_TILING_Y:
 794         ss->ss2.tiled_surface = 1;
 795         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 796         break;
 797     }
 798 }
 799
 800 static void
 801 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 802 {
 803     switch (tiling) {
 804     case I915_TILING_NONE:
 805         ss->ss0.tiled_surface = 0;
 806         ss->ss0.tile_walk = 0;
 807         break;
 808     case I915_TILING_X:
 809         ss->ss0.tiled_surface = 1;
 810         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 811         break;
 812     case I915_TILING_Y:
 813         ss->ss0.tiled_surface = 1;
 814         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 815         break;
 816     }
 817 }
 818
 819 static void
 820 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 821 {
 822     switch (tiling) {
 823     case I915_TILING_NONE:
 824         ss->ss2.tiled_surface = 0;
 825         ss->ss2.tile_walk = 0;
 826         break;
 827     case I915_TILING_X:
 828         ss->ss2.tiled_surface = 1;
 829         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 830         break;
 831     case I915_TILING_Y:
 832         ss->ss2.tiled_surface = 1;
 833         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 834         break;
 835     }
 836 }
 837
 838 static void
 839 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 840 {
 841     struct i965_interface_descriptor *desc;
 842     dri_bo *bo;
 843     int pp_index = pp_context->current_pp;
 844
 845     bo = pp_context->idrt.bo;
 846     dri_bo_map(bo, 1);
 847     assert(bo->virtual);
 848     desc = bo->virtual;
 849     memset(desc, 0, sizeof(*desc));
 850     desc->desc0.grf_reg_blocks = 10;
 851     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 852     desc->desc1.const_urb_entry_read_offset = 0;
 853     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 854     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 855     desc->desc2.sampler_count = 0;
 856     desc->desc3.binding_table_entry_count = 0;
 857     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 858
 859     dri_bo_emit_reloc(bo,
 860                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 861                       desc->desc0.grf_reg_blocks,
 862                       offsetof(struct i965_interface_descriptor, desc0),
 863                       pp_context->pp_modules[pp_index].kernel.bo);
 864
 865     dri_bo_emit_reloc(bo,
 866                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 867                       desc->desc2.sampler_count << 2,
 868                       offsetof(struct i965_interface_descriptor, desc2),
 869                       pp_context->sampler_state_table.bo);
 870
 871     dri_bo_unmap(bo);
 872     pp_context->idrt.num_interface_descriptors++;
 873 }
 874
 875 static void
 876 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 877 {
 878     struct i965_vfe_state *vfe_state;
 879     dri_bo *bo;
 880
 881     bo = pp_context->vfe_state.bo;
 882     dri_bo_map(bo, 1);
 883     assert(bo->virtual);
 884     vfe_state = bo->virtual;
 885     memset(vfe_state, 0, sizeof(*vfe_state));
 886     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 887     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 888     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 889     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 890     vfe_state->vfe1.children_present = 0;
 891     vfe_state->vfe2.interface_descriptor_base =
 892         pp_context->idrt.bo->offset >> 4; /* reloc */
 893     dri_bo_emit_reloc(bo,
 894                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 895                       0,
 896                       offsetof(struct i965_vfe_state, vfe2),
 897                       pp_context->idrt.bo);
 898     dri_bo_unmap(bo);
 899 }
 900
 901 static void
 902 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 903 {
 904     unsigned char *constant_buffer;
 905     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 906
 907     assert(sizeof(*pp_static_parameter) == 128);
 908     dri_bo_map(pp_context->curbe.bo, 1);
 909     assert(pp_context->curbe.bo->virtual);
 910     constant_buffer = pp_context->curbe.bo->virtual;
 911     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 912     dri_bo_unmap(pp_context->curbe.bo);
 913 }
 914
 915 static void
 916 ironlake_pp_states_setup(VADriverContextP ctx,
 917                          struct i965_post_processing_context *pp_context)
 918 {
 919     ironlake_pp_interface_descriptor_table(pp_context);
 920     ironlake_pp_vfe_state(pp_context);
 921     ironlake_pp_upload_constants(pp_context);
 922 }
 923
 924 static void
 925 ironlake_pp_pipeline_select(VADriverContextP ctx,
 926                             struct i965_post_processing_context *pp_context)
 927 {
 928     struct intel_batchbuffer *batch = pp_context->batch;
 929
 930     BEGIN_BATCH(batch, 1);
 931     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 932     ADVANCE_BATCH(batch);
 933 }
 934
 935 static void
 936 ironlake_pp_urb_layout(VADriverContextP ctx,
 937                        struct i965_post_processing_context *pp_context)
 938 {
 939     struct intel_batchbuffer *batch = pp_context->batch;
 940     unsigned int vfe_fence, cs_fence;
 941
 942     vfe_fence = pp_context->urb.cs_start;
 943     cs_fence = pp_context->urb.size;
 944
 945     BEGIN_BATCH(batch, 3);
 946     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 947     OUT_BATCH(batch, 0);
 948     OUT_BATCH(batch,
 949               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 950               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 951     ADVANCE_BATCH(batch);
 952 }
 953
 954 static void
 955 ironlake_pp_state_base_address(VADriverContextP ctx,
 956                                struct i965_post_processing_context *pp_context)
 957 {
 958     struct intel_batchbuffer *batch = pp_context->batch;
 959
 960     BEGIN_BATCH(batch, 8);
 961     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 962     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 963     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 964     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 965     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 966     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 967     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 968     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 969     ADVANCE_BATCH(batch);
 970 }
 971
 972 static void
 973 ironlake_pp_state_pointers(VADriverContextP ctx,
 974                            struct i965_post_processing_context *pp_context)
 975 {
 976     struct intel_batchbuffer *batch = pp_context->batch;
 977
 978     BEGIN_BATCH(batch, 3);
 979     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 980     OUT_BATCH(batch, 0);
 981     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 982     ADVANCE_BATCH(batch);
 983 }
 984
 985 static void
 986 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 987                           struct i965_post_processing_context *pp_context)
 988 {
 989     struct intel_batchbuffer *batch = pp_context->batch;
 990
 991     BEGIN_BATCH(batch, 2);
 992     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 993     OUT_BATCH(batch,
 994               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 995               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 996     ADVANCE_BATCH(batch);
 997 }
 998
 999 static void
1000 ironlake_pp_constant_buffer(VADriverContextP ctx,
1001                             struct i965_post_processing_context *pp_context)
1002 {
1003     struct intel_batchbuffer *batch = pp_context->batch;
1004
1005     BEGIN_BATCH(batch, 2);
1006     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1007     OUT_RELOC(batch, pp_context->curbe.bo,
1008               I915_GEM_DOMAIN_INSTRUCTION, 0,
1009               pp_context->urb.size_cs_entry - 1);
1010     ADVANCE_BATCH(batch);
1011 }
1012
1013 static void
1014 ironlake_pp_object_walker(VADriverContextP ctx,
1015                           struct i965_post_processing_context *pp_context)
1016 {
1017     struct intel_batchbuffer *batch = pp_context->batch;
1018     int x, x_steps, y, y_steps;
1019     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1020
1021     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1022     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1023
1024     for (y = 0; y < y_steps; y++) {
1025         for (x = 0; x < x_steps; x++) {
1026             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1027                 BEGIN_BATCH(batch, 20);
1028                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1029                 OUT_BATCH(batch, 0);
1030                 OUT_BATCH(batch, 0); /* no indirect data */
1031                 OUT_BATCH(batch, 0);
1032
1033                 /* inline data grf 5-6 */
1034                 assert(sizeof(*pp_inline_parameter) == 64);
1035                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1036
1037                 ADVANCE_BATCH(batch);
1038             }
1039         }
1040     }
1041 }
1042
1043 static void
1044 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1045                            struct i965_post_processing_context *pp_context)
1046 {
1047     struct intel_batchbuffer *batch = pp_context->batch;
1048
1049     intel_batchbuffer_start_atomic(batch, 0x1000);
1050     intel_batchbuffer_emit_mi_flush(batch);
1051     ironlake_pp_pipeline_select(ctx, pp_context);
1052     ironlake_pp_state_base_address(ctx, pp_context);
1053     ironlake_pp_state_pointers(ctx, pp_context);
1054     ironlake_pp_urb_layout(ctx, pp_context);
1055     ironlake_pp_cs_urb_layout(ctx, pp_context);
1056     ironlake_pp_constant_buffer(ctx, pp_context);
1057     ironlake_pp_object_walker(ctx, pp_context);
1058     intel_batchbuffer_end_atomic(batch);
1059 }
1060
1061 // update u/v offset when the surface format are packed yuv
1062 static void i965_update_src_surface_static_parameter(
1063     VADriverContextP    ctx,
1064     struct i965_post_processing_context *pp_context,
1065     const struct i965_surface *surface)
1066 {
1067     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1068     int fourcc = pp_get_surface_fourcc(ctx, surface);
1069
1070     switch (fourcc) {
1071     case VA_FOURCC('Y', 'U', 'Y', '2'):
1072         pp_static_parameter->grf1.source_packed_u_offset = 1;
1073         pp_static_parameter->grf1.source_packed_v_offset = 3;
1074         break;
1075     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1076         pp_static_parameter->grf1.source_packed_y_offset = 1;
1077         pp_static_parameter->grf1.source_packed_v_offset = 2;
1078         break;
1079     case VA_FOURCC('B', 'G', 'R', 'X'):
1080     case VA_FOURCC('B', 'G', 'R', 'A'):
1081         pp_static_parameter->grf1.source_rgb_layout = 0;
1082         break;
1083     case VA_FOURCC('R', 'G', 'B', 'X'):
1084     case VA_FOURCC('R', 'G', 'B', 'A'):
1085         pp_static_parameter->grf1.source_rgb_layout = 1;
1086         break;
1087     default:
1088         break;
1089     }
1090
1091 }
1092
1093 static void i965_update_dst_surface_static_parameter(
1094     VADriverContextP    ctx,
1095     struct i965_post_processing_context *pp_context,
1096     const struct i965_surface *surface)
1097 {
1098     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1099     int fourcc = pp_get_surface_fourcc(ctx, surface);
1100
1101     switch (fourcc) {
1102     case VA_FOURCC('Y', 'U', 'Y', '2'):
1103         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1104         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1105         break;
1106     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1107         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1108         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1109         break;
1110     case VA_FOURCC('B', 'G', 'R', 'X'):
1111     case VA_FOURCC('B', 'G', 'R', 'A'):
1112         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0;
1113         break;
1114     case VA_FOURCC('R', 'G', 'B', 'X'):
1115     case VA_FOURCC('R', 'G', 'B', 'A'):
1116         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1;
1117         break;
1118     default:
1119         break;
1120     }
1121
1122 }
1123
1124 static void
1125 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1126                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1127                           int width, int height, int pitch, int format,
1128                           int index, int is_target)
1129 {
1130     struct i965_surface_state *ss;
1131     dri_bo *ss_bo;
1132     unsigned int tiling;
1133     unsigned int swizzle;
1134
1135     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1136     ss_bo = pp_context->surface_state_binding_table.bo;
1137     assert(ss_bo);
1138
1139     dri_bo_map(ss_bo, True);
1140     assert(ss_bo->virtual);
1141     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1142     memset(ss, 0, sizeof(*ss));
1143     ss->ss0.surface_type = I965_SURFACE_2D;
1144     ss->ss0.surface_format = format;
1145     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1146     ss->ss2.width = width - 1;
1147     ss->ss2.height = height - 1;
1148     ss->ss3.pitch = pitch - 1;
1149     pp_set_surface_tiling(ss, tiling);
1150     dri_bo_emit_reloc(ss_bo,
1151                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1152                       surf_bo_offset,
1153                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1154                       surf_bo);
1155     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1156     dri_bo_unmap(ss_bo);
1157 }
1158
1159 static void
1160 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1161                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1162                            int width, int height, int wpitch,
1163                            int xoffset, int yoffset,
1164                            int format, int interleave_chroma,
1165                            int index)
1166 {
1167     struct i965_surface_state2 *ss2;
1168     dri_bo *ss2_bo;
1169     unsigned int tiling;
1170     unsigned int swizzle;
1171
1172     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1173     ss2_bo = pp_context->surface_state_binding_table.bo;
1174     assert(ss2_bo);
1175
1176     dri_bo_map(ss2_bo, True);
1177     assert(ss2_bo->virtual);
1178     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1179     memset(ss2, 0, sizeof(*ss2));
1180     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1181     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1182     ss2->ss1.width = width - 1;
1183     ss2->ss1.height = height - 1;
1184     ss2->ss2.pitch = wpitch - 1;
1185     ss2->ss2.interleave_chroma = interleave_chroma;
1186     ss2->ss2.surface_format = format;
1187     ss2->ss3.x_offset_for_cb = xoffset;
1188     ss2->ss3.y_offset_for_cb = yoffset;
1189     pp_set_surface2_tiling(ss2, tiling);
1190     dri_bo_emit_reloc(ss2_bo,
1191                       I915_GEM_DOMAIN_RENDER, 0,
1192                       surf_bo_offset,
1193                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1194                       surf_bo);
1195     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1196     dri_bo_unmap(ss2_bo);
1197 }
1198
1199 static void
1200 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1201                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1202                           int width, int height, int pitch, int format,
1203                           int index, int is_target)
1204 {
1205     struct gen7_surface_state *ss;
1206     dri_bo *ss_bo;
1207     unsigned int tiling;
1208     unsigned int swizzle;
1209
1210     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1211     ss_bo = pp_context->surface_state_binding_table.bo;
1212     assert(ss_bo);
1213
1214     dri_bo_map(ss_bo, True);
1215     assert(ss_bo->virtual);
1216     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1217     memset(ss, 0, sizeof(*ss));
1218     ss->ss0.surface_type = I965_SURFACE_2D;
1219     ss->ss0.surface_format = format;
1220     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1221     ss->ss2.width = width - 1;
1222     ss->ss2.height = height - 1;
1223     ss->ss3.pitch = pitch - 1;
1224     gen7_pp_set_surface_tiling(ss, tiling);
1225     dri_bo_emit_reloc(ss_bo,
1226                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1227                       surf_bo_offset,
1228                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1229                       surf_bo);
1230     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1231     dri_bo_unmap(ss_bo);
1232 }
1233
1234 static void
1235 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1236                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1237                            int width, int height, int wpitch,
1238                            int xoffset, int yoffset,
1239                            int format, int interleave_chroma,
1240                            int index)
1241 {
1242     struct gen7_surface_state2 *ss2;
1243     dri_bo *ss2_bo;
1244     unsigned int tiling;
1245     unsigned int swizzle;
1246
1247     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1248     ss2_bo = pp_context->surface_state_binding_table.bo;
1249     assert(ss2_bo);
1250
1251     dri_bo_map(ss2_bo, True);
1252     assert(ss2_bo->virtual);
1253     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1254     memset(ss2, 0, sizeof(*ss2));
1255     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1256     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1257     ss2->ss1.width = width - 1;
1258     ss2->ss1.height = height - 1;
1259     ss2->ss2.pitch = wpitch - 1;
1260     ss2->ss2.interleave_chroma = interleave_chroma;
1261     ss2->ss2.surface_format = format;
1262     ss2->ss3.x_offset_for_cb = xoffset;
1263     ss2->ss3.y_offset_for_cb = yoffset;
1264     gen7_pp_set_surface2_tiling(ss2, tiling);
1265     dri_bo_emit_reloc(ss2_bo,
1266                       I915_GEM_DOMAIN_RENDER, 0,
1267                       surf_bo_offset,
1268                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1269                       surf_bo);
1270     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1271     dri_bo_unmap(ss2_bo);
1272 }
1273
1274 static void
1275 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1276                                 const struct i965_surface *surface,
1277                                 int base_index, int is_target,
1278                                 int *width, int *height, int *pitch, int *offset)
1279 {
1280     struct i965_driver_data *i965 = i965_driver_data(ctx);
1281     struct object_surface *obj_surface;
1282     struct object_image *obj_image;
1283     dri_bo *bo;
1284     int fourcc = pp_get_surface_fourcc(ctx, surface);
1285     const int Y = 0;
1286     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1287     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1288     const int UV = 1;
1289     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1290     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1291     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1292                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1293                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1294                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1295     int scale_factor_of_1st_plane_width_in_byte = 1;
1296
1297     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1298         obj_surface = SURFACE(surface->id);
1299         bo = obj_surface->bo;
1300         width[0] = obj_surface->orig_width;
1301         height[0] = obj_surface->orig_height;
1302         pitch[0] = obj_surface->width;
1303         offset[0] = 0;
1304
1305         if (full_packed_format) {
1306             scale_factor_of_1st_plane_width_in_byte = 4;
1307             pitch[0] = obj_surface->width * 4;
1308         }
1309         else if (packed_yuv ) {
1310             scale_factor_of_1st_plane_width_in_byte =  2;
1311             pitch[0] = obj_surface->width * 2;
1312         }
1313         else if (interleaved_uv) {
1314             width[1] = obj_surface->orig_width;
1315             height[1] = obj_surface->orig_height / 2;
1316             pitch[1] = obj_surface->width;
1317             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1318         } else {
1319             width[1] = obj_surface->orig_width / 2;
1320             height[1] = obj_surface->orig_height / 2;
1321             pitch[1] = obj_surface->width / 2;
1322             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1323             width[2] = obj_surface->orig_width / 2;
1324             height[2] = obj_surface->orig_height / 2;
1325             pitch[2] = obj_surface->width / 2;
1326             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1327         }
1328     } else {
1329         obj_image = IMAGE(surface->id);
1330         bo = obj_image->bo;
1331         width[0] = obj_image->image.width;
1332         height[0] = obj_image->image.height;
1333         pitch[0] = obj_image->image.pitches[0];
1334         offset[0] = obj_image->image.offsets[0];
1335
1336         if (full_packed_format) {
1337             scale_factor_of_1st_plane_width_in_byte = 4;
1338         }
1339         else if (packed_yuv ) {
1340             scale_factor_of_1st_plane_width_in_byte = 2;
1341         }
1342         else if (interleaved_uv) {
1343             width[1] = obj_image->image.width;
1344             height[1] = obj_image->image.height / 2;
1345             pitch[1] = obj_image->image.pitches[1];
1346             offset[1] = obj_image->image.offsets[1];
1347         } else {
1348             width[1] = obj_image->image.width / 2;
1349             height[1] = obj_image->image.height / 2;
1350             pitch[1] = obj_image->image.pitches[1];
1351             offset[1] = obj_image->image.offsets[1];
1352             width[2] = obj_image->image.width / 2;
1353             height[2] = obj_image->image.height / 2;
1354             pitch[2] = obj_image->image.pitches[2];
1355             offset[2] = obj_image->image.offsets[2];
1356         }
1357     }
1358
1359     /* Y surface */
1360     i965_pp_set_surface_state(ctx, pp_context,
1361                               bo, offset[Y],
1362                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1363                               base_index, is_target);
1364
1365     if (!packed_yuv && !full_packed_format) {
1366         if (interleaved_uv) {
1367             i965_pp_set_surface_state(ctx, pp_context,
1368                                       bo, offset[UV],
1369                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1370                                       base_index + 1, is_target);
1371         } else {
1372             /* U surface */
1373             i965_pp_set_surface_state(ctx, pp_context,
1374                                       bo, offset[U],
1375                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1376                                       base_index + 1, is_target);
1377
1378             /* V surface */
1379             i965_pp_set_surface_state(ctx, pp_context,
1380                                       bo, offset[V],
1381                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1382                                       base_index + 2, is_target);
1383         }
1384     }
1385
1386 }
1387
1388 static void
1389 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1390                                      const struct i965_surface *surface,
1391                                      int base_index, int is_target,
1392                                      int *width, int *height, int *pitch, int *offset)
1393 {
1394     struct i965_driver_data *i965 = i965_driver_data(ctx);
1395     struct object_surface *obj_surface;
1396     struct object_image *obj_image;
1397     dri_bo *bo;
1398     int fourcc = pp_get_surface_fourcc(ctx, surface);
1399     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1400                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1401     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1402                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1403     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1404     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1405
1406     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1407         obj_surface = SURFACE(surface->id);
1408         bo = obj_surface->bo;
1409         width[0] = obj_surface->orig_width;
1410         height[0] = obj_surface->orig_height;
1411         pitch[0] = obj_surface->width;
1412         offset[0] = 0;
1413
1414         if (packed_yuv) {
1415             if (is_target)
1416                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1417             else
1418                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1419
1420             pitch[0] = obj_surface->width * 2;
1421         }
1422
1423         width[1] = obj_surface->cb_cr_width;
1424         height[1] = obj_surface->cb_cr_height;
1425         pitch[1] = obj_surface->cb_cr_pitch;
1426         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1427
1428         width[2] = obj_surface->cb_cr_width;
1429         height[2] = obj_surface->cb_cr_height;
1430         pitch[2] = obj_surface->cb_cr_pitch;
1431         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1432     } else {
1433         obj_image = IMAGE(surface->id);
1434         bo = obj_image->bo;
1435         width[0] = obj_image->image.width;
1436         height[0] = obj_image->image.height;
1437         pitch[0] = obj_image->image.pitches[0];
1438         offset[0] = obj_image->image.offsets[0];
1439
1440         if (packed_yuv) {
1441             if (is_target)
1442                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1443             else
1444                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1445         } else if (interleaved_uv) {
1446             width[1] = obj_image->image.width / 2;
1447             height[1] = obj_image->image.height / 2;
1448             pitch[1] = obj_image->image.pitches[1];
1449             offset[1] = obj_image->image.offsets[1];
1450         } else {
1451             width[1] = obj_image->image.width / 2;
1452             height[1] = obj_image->image.height / 2;
1453             pitch[1] = obj_image->image.pitches[U];
1454             offset[1] = obj_image->image.offsets[U];
1455             width[2] = obj_image->image.width / 2;
1456             height[2] = obj_image->image.height / 2;
1457             pitch[2] = obj_image->image.pitches[V];
1458             offset[2] = obj_image->image.offsets[V];
1459         }
1460     }
1461
1462     if (is_target) {
1463         gen7_pp_set_surface_state(ctx, pp_context,
1464                                   bo, 0,
1465                                   width[0] / 4, height[0], pitch[0],
1466                                   I965_SURFACEFORMAT_R8_SINT,
1467                                   base_index, 1);
1468
1469         if (!packed_yuv) {
1470             if (interleaved_uv) {
1471                 gen7_pp_set_surface_state(ctx, pp_context,
1472                                           bo, offset[1],
1473                                           width[1] / 2, height[1], pitch[1],
1474                                           I965_SURFACEFORMAT_R8G8_SINT,
1475                                           base_index + 1, 1);
1476             } else {
1477                 gen7_pp_set_surface_state(ctx, pp_context,
1478                                           bo, offset[1],
1479                                           width[1] / 4, height[1], pitch[1],
1480                                           I965_SURFACEFORMAT_R8_SINT,
1481                                           base_index + 1, 1);
1482                 gen7_pp_set_surface_state(ctx, pp_context,
1483                                           bo, offset[2],
1484                                           width[2] / 4, height[2], pitch[2],
1485                                           I965_SURFACEFORMAT_R8_SINT,
1486                                           base_index + 2, 1);
1487             }
1488         }
1489     } else {
1490         int format0 = SURFACE_FORMAT_Y8_UNORM;
1491
1492         switch (fourcc) {
1493         case VA_FOURCC('Y', 'U', 'Y', '2'):
1494             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1495             break;
1496
1497         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1498             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1499             break;
1500
1501         default:
1502             break;
1503         }
1504
1505         gen7_pp_set_surface2_state(ctx, pp_context,
1506                                    bo, offset[0],
1507                                    width[0], height[0], pitch[0],
1508                                    0, 0,
1509                                    format0, 0,
1510                                    base_index);
1511
1512         if (!packed_yuv) {
1513             if (interleaved_uv) {
1514                 gen7_pp_set_surface2_state(ctx, pp_context,
1515                                            bo, offset[1],
1516                                            width[1], height[1], pitch[1],
1517                                            0, 0,
1518                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1519                                            base_index + 1);
1520             } else {
1521                 gen7_pp_set_surface2_state(ctx, pp_context,
1522                                            bo, offset[1],
1523                                            width[1], height[1], pitch[1],
1524                                            0, 0,
1525                                            SURFACE_FORMAT_R8_UNORM, 0,
1526                                            base_index + 1);
1527                 gen7_pp_set_surface2_state(ctx, pp_context,
1528                                            bo, offset[2],
1529                                            width[2], height[2], pitch[2],
1530                                            0, 0,
1531                                            SURFACE_FORMAT_R8_UNORM, 0,
1532                                            base_index + 2);
1533             }
1534         }
1535     }
1536 }
1537
1538 static int
1539 pp_null_x_steps(void *private_context)
1540 {
1541     return 1;
1542 }
1543
1544 static int
1545 pp_null_y_steps(void *private_context)
1546 {
1547     return 1;
1548 }
1549
1550 static int
1551 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1552 {
1553     return 0;
1554 }
1555
1556 static VAStatus
1557 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1558                    const struct i965_surface *src_surface,
1559                    const VARectangle *src_rect,
1560                    struct i965_surface *dst_surface,
1561                    const VARectangle *dst_rect,
1562                    void *filter_param)
1563 {
1564     /* private function & data */
1565     pp_context->pp_x_steps = pp_null_x_steps;
1566     pp_context->pp_y_steps = pp_null_y_steps;
1567     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1568
1569     dst_surface->flags = src_surface->flags;
1570
1571     return VA_STATUS_SUCCESS;
1572 }
1573
1574 static int
1575 pp_load_save_x_steps(void *private_context)
1576 {
1577     return 1;
1578 }
1579
1580 static int
1581 pp_load_save_y_steps(void *private_context)
1582 {
1583     struct pp_load_save_context *pp_load_save_context = private_context;
1584
1585     return pp_load_save_context->dest_h / 8;
1586 }
1587
1588 static int
1589 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1590 {
1591     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1592
1593     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1594     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1595     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1596     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1597
1598     return 0;
1599 }
1600
1601 static VAStatus
1602 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1603                                 const struct i965_surface *src_surface,
1604                                 const VARectangle *src_rect,
1605                                 struct i965_surface *dst_surface,
1606                                 const VARectangle *dst_rect,
1607                                 void *filter_param)
1608 {
1609     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1610     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1611     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1612     int width[3], height[3], pitch[3], offset[3];
1613     const int Y = 0;
1614
1615     /* source surface */
1616     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1617                                     width, height, pitch, offset);
1618
1619     /* destination surface */
1620     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1621                                     width, height, pitch, offset);
1622
1623     /* private function & data */
1624     pp_context->pp_x_steps = pp_load_save_x_steps;
1625     pp_context->pp_y_steps = pp_load_save_y_steps;
1626     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1627     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1628     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1629
1630     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1631     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1632
1633     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1634     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1635
1636     // update u/v offset for packed yuv
1637     i965_update_src_surface_static_parameter (ctx, pp_context, src_surface);
1638     i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface);
1639
1640     dst_surface->flags = src_surface->flags;
1641
1642     return VA_STATUS_SUCCESS;
1643 }
1644
1645 static int
1646 pp_scaling_x_steps(void *private_context)
1647 {
1648     return 1;
1649 }
1650
1651 static int
1652 pp_scaling_y_steps(void *private_context)
1653 {
1654     struct pp_scaling_context *pp_scaling_context = private_context;
1655
1656     return pp_scaling_context->dest_h / 8;
1657 }
1658
1659 static int
1660 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1661 {
1662     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1663     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1664     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1665     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1666     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1667
1668     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1669     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1670     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1671     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1672
1673     return 0;
1674 }
1675
1676 static VAStatus
1677 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1678                            const struct i965_surface *src_surface,
1679                            const VARectangle *src_rect,
1680                            struct i965_surface *dst_surface,
1681                            const VARectangle *dst_rect,
1682                            void *filter_param)
1683 {
1684     struct i965_driver_data *i965 = i965_driver_data(ctx);
1685     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1686     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1687     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1688     struct object_surface *obj_surface;
1689     struct i965_sampler_state *sampler_state;
1690     int in_w, in_h, in_wpitch, in_hpitch;
1691     int out_w, out_h, out_wpitch, out_hpitch;
1692
1693     /* source surface */
1694     obj_surface = SURFACE(src_surface->id);
1695     in_w = obj_surface->orig_width;
1696     in_h = obj_surface->orig_height;
1697     in_wpitch = obj_surface->width;
1698     in_hpitch = obj_surface->height;
1699
1700     /* source Y surface index 1 */
1701     i965_pp_set_surface_state(ctx, pp_context,
1702                               obj_surface->bo, 0,
1703                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1704                               1, 0);
1705
1706     /* source UV surface index 2 */
1707     i965_pp_set_surface_state(ctx, pp_context,
1708                               obj_surface->bo, in_wpitch * in_hpitch,
1709                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1710                               2, 0);
1711
1712     /* destination surface */
1713     obj_surface = SURFACE(dst_surface->id);
1714     out_w = obj_surface->orig_width;
1715     out_h = obj_surface->orig_height;
1716     out_wpitch = obj_surface->width;
1717     out_hpitch = obj_surface->height;
1718
1719     /* destination Y surface index 7 */
1720     i965_pp_set_surface_state(ctx, pp_context,
1721                               obj_surface->bo, 0,
1722                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1723                               7, 1);
1724
1725     /* destination UV surface index 8 */
1726     i965_pp_set_surface_state(ctx, pp_context,
1727                               obj_surface->bo, out_wpitch * out_hpitch,
1728                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1729                               8, 1);
1730
1731     /* sampler state */
1732     dri_bo_map(pp_context->sampler_state_table.bo, True);
1733     assert(pp_context->sampler_state_table.bo->virtual);
1734     sampler_state = pp_context->sampler_state_table.bo->virtual;
1735
1736     /* SIMD16 Y index 1 */
1737     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1738     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1739     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1740     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1741     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1742
1743     /* SIMD16 UV index 2 */
1744     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1745     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1746     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1747     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1748     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1749
1750     dri_bo_unmap(pp_context->sampler_state_table.bo);
1751
1752     /* private function & data */
1753     pp_context->pp_x_steps = pp_scaling_x_steps;
1754     pp_context->pp_y_steps = pp_scaling_y_steps;
1755     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1756
1757     pp_scaling_context->dest_x = dst_rect->x;
1758     pp_scaling_context->dest_y = dst_rect->y;
1759     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1760     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1761     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1762     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1763
1764     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1765
1766     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1767     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1768     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1769     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1770     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1771
1772     dst_surface->flags = src_surface->flags;
1773
1774     return VA_STATUS_SUCCESS;
1775 }
1776
1777 static int
1778 pp_avs_x_steps(void *private_context)
1779 {
1780     struct pp_avs_context *pp_avs_context = private_context;
1781
1782     return pp_avs_context->dest_w / 16;
1783 }
1784
1785 static int
1786 pp_avs_y_steps(void *private_context)
1787 {
1788     return 1;
1789 }
1790
1791 static int
1792 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1793 {
1794     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1795     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1796     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1797     float src_x_steping, src_y_steping, video_step_delta;
1798     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1799
1800     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1801         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1802         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1803     } else if (tmp_w >= pp_avs_context->dest_w) {
1804         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1805         pp_inline_parameter->grf6.video_step_delta = 0;
1806
1807         if (x == 0) {
1808             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1809                 pp_avs_context->src_normalized_x;
1810         } else {
1811             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1812             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1813             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1814                 16 * 15 * video_step_delta / 2;
1815         }
1816     } else {
1817         int n0, n1, n2, nls_left, nls_right;
1818         int factor_a = 5, factor_b = 4;
1819         float f;
1820
1821         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1822         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1823         n2 = tmp_w / (16 * factor_a);
1824         nls_left = n0 + n2;
1825         nls_right = n1 + n2;
1826         f = (float) n2 * 16 / tmp_w;
1827
1828         if (n0 < 5) {
1829             pp_inline_parameter->grf6.video_step_delta = 0.0;
1830
1831             if (x == 0) {
1832                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1833                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1834             } else {
1835                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1836                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1837                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1838                     16 * 15 * video_step_delta / 2;
1839             }
1840         } else {
1841             if (x < nls_left) {
1842                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1843                 float a = f / (nls_left * 16 * factor_b);
1844                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1845
1846                 pp_inline_parameter->grf6.video_step_delta = b;
1847
1848                 if (x == 0) {
1849                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1850                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1851                 } else {
1852                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1853                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1854                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1855                         16 * 15 * video_step_delta / 2;
1856                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1857                 }
1858             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1859                 /* scale the center linearly */
1860                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1861                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1862                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1863                     16 * 15 * video_step_delta / 2;
1864                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1865                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1866             } else {
1867                 float a = f / (nls_right * 16 * factor_b);
1868                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1869
1870                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1871                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1872                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1873                     16 * 15 * video_step_delta / 2;
1874                 pp_inline_parameter->grf6.video_step_delta = -b;
1875
1876                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1877                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1878                 else
1879                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1880             }
1881         }
1882     }
1883
1884     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1885     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1886     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1887     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1888
1889     return 0;
1890 }
1891
1892 static VAStatus
1893 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1894                        const struct i965_surface *src_surface,
1895                        const VARectangle *src_rect,
1896                        struct i965_surface *dst_surface,
1897                        const VARectangle *dst_rect,
1898                        void *filter_param,
1899                        int nlas)
1900 {
1901     struct i965_driver_data *i965 = i965_driver_data(ctx);
1902     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1903     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1904     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1905     struct object_surface *obj_surface;
1906     struct i965_sampler_8x8 *sampler_8x8;
1907     struct i965_sampler_8x8_state *sampler_8x8_state;
1908     int index;
1909     int in_w, in_h, in_wpitch, in_hpitch;
1910     int out_w, out_h, out_wpitch, out_hpitch;
1911     int i;
1912
1913     /* surface */
1914     obj_surface = SURFACE(src_surface->id);
1915     in_w = obj_surface->orig_width;
1916     in_h = obj_surface->orig_height;
1917     in_wpitch = obj_surface->width;
1918     in_hpitch = obj_surface->height;
1919
1920     /* source Y surface index 1 */
1921     i965_pp_set_surface2_state(ctx, pp_context,
1922                                obj_surface->bo, 0,
1923                                in_w, in_h, in_wpitch,
1924                                0, 0,
1925                                SURFACE_FORMAT_Y8_UNORM, 0,
1926                                1);
1927
1928     /* source UV surface index 2 */
1929     i965_pp_set_surface2_state(ctx, pp_context,
1930                                obj_surface->bo, in_wpitch * in_hpitch,
1931                                in_w / 2, in_h / 2, in_wpitch,
1932                                0, 0,
1933                                SURFACE_FORMAT_R8B8_UNORM, 0,
1934                                2);
1935
1936     /* destination surface */
1937     obj_surface = SURFACE(dst_surface->id);
1938     out_w = obj_surface->orig_width;
1939     out_h = obj_surface->orig_height;
1940     out_wpitch = obj_surface->width;
1941     out_hpitch = obj_surface->height;
1942     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1943
1944     /* destination Y surface index 7 */
1945     i965_pp_set_surface_state(ctx, pp_context,
1946                               obj_surface->bo, 0,
1947                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1948                               7, 1);
1949
1950     /* destination UV surface index 8 */
1951     i965_pp_set_surface_state(ctx, pp_context,
1952                               obj_surface->bo, out_wpitch * out_hpitch,
1953                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1954                               8, 1);
1955
1956     /* sampler 8x8 state */
1957     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1958     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1959     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1960     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1961     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1962
1963     for (i = 0; i < 17; i++) {
1964         /* for Y channel, currently ignore */
1965         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1966         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1967         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1968         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1969         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1970         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1971         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1972         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1973         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1974         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1975         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1976         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1977         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1978         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1979         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1980         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1981         /* for U/V channel, 0.25 */
1982         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1983         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1984         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1985         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1986         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1987         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1988         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1989         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1990         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1991         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1992         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1993         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1994         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1995         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1996         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1997         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1998     }
1999
2000     sampler_8x8_state->dw136.default_sharpness_level = 0;
2001     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2002     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2003     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2004     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2005
2006     /* sampler 8x8 */
2007     dri_bo_map(pp_context->sampler_state_table.bo, True);
2008     assert(pp_context->sampler_state_table.bo->virtual);
2009     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
2010     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2011
2012     /* sample_8x8 Y index 1 */
2013     index = 1;
2014     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2015     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2016     sampler_8x8[index].dw0.ief_bypass = 1;
2017     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2018     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2019     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2020     sampler_8x8[index].dw2.global_noise_estimation = 22;
2021     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2022     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2023     sampler_8x8[index].dw3.strong_edge_weight = 7;
2024     sampler_8x8[index].dw3.regular_weight = 2;
2025     sampler_8x8[index].dw3.non_edge_weight = 0;
2026     sampler_8x8[index].dw3.gain_factor = 40;
2027     sampler_8x8[index].dw4.steepness_boost = 0;
2028     sampler_8x8[index].dw4.steepness_threshold = 0;
2029     sampler_8x8[index].dw4.mr_boost = 0;
2030     sampler_8x8[index].dw4.mr_threshold = 5;
2031     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2032     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2033     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2034     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2035     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2036     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2037     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2038     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2039     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2040     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2041     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2042     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2043     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2044     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2045     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2046     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2047     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2048     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2049     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2050     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2051     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2052     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2053     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2054     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2055     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2056     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2057     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2058     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2059     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2060     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2061     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2062     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2063     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2064     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2065     sampler_8x8[index].dw13.limiter_boost = 0;
2066     sampler_8x8[index].dw13.minimum_limiter = 10;
2067     sampler_8x8[index].dw13.maximum_limiter = 11;
2068     sampler_8x8[index].dw14.clip_limiter = 130;
2069     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2070                       I915_GEM_DOMAIN_RENDER,
2071                       0,
2072                       0,
2073                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2074                       pp_context->sampler_state_table.bo_8x8);
2075
2076     /* sample_8x8 UV index 2 */
2077     index = 2;
2078     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2079     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2080     sampler_8x8[index].dw0.ief_bypass = 1;
2081     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2082     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2083     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2084     sampler_8x8[index].dw2.global_noise_estimation = 22;
2085     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2086     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2087     sampler_8x8[index].dw3.strong_edge_weight = 7;
2088     sampler_8x8[index].dw3.regular_weight = 2;
2089     sampler_8x8[index].dw3.non_edge_weight = 0;
2090     sampler_8x8[index].dw3.gain_factor = 40;
2091     sampler_8x8[index].dw4.steepness_boost = 0;
2092     sampler_8x8[index].dw4.steepness_threshold = 0;
2093     sampler_8x8[index].dw4.mr_boost = 0;
2094     sampler_8x8[index].dw4.mr_threshold = 5;
2095     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2096     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2097     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2098     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2099     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2100     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2101     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2102     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2103     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2104     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2105     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2106     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2107     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2108     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2109     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2110     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2111     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2112     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2113     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2114     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2115     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2116     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2117     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2118     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2119     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2120     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2121     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2122     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2123     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2124     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2125     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2126     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2127     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2128     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2129     sampler_8x8[index].dw13.limiter_boost = 0;
2130     sampler_8x8[index].dw13.minimum_limiter = 10;
2131     sampler_8x8[index].dw13.maximum_limiter = 11;
2132     sampler_8x8[index].dw14.clip_limiter = 130;
2133     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2134                       I915_GEM_DOMAIN_RENDER,
2135                       0,
2136                       0,
2137                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2138                       pp_context->sampler_state_table.bo_8x8);
2139
2140     dri_bo_unmap(pp_context->sampler_state_table.bo);
2141
2142     /* private function & data */
2143     pp_context->pp_x_steps = pp_avs_x_steps;
2144     pp_context->pp_y_steps = pp_avs_y_steps;
2145     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2146
2147     pp_avs_context->dest_x = dst_rect->x;
2148     pp_avs_context->dest_y = dst_rect->y;
2149     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2150     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2151     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2152     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2153     pp_avs_context->src_w = src_rect->width;
2154     pp_avs_context->src_h = src_rect->height;
2155
2156     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2157     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2158
2159     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2160     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2161     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2162     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2163     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2164     pp_inline_parameter->grf6.video_step_delta = 0.0;
2165
2166     dst_surface->flags = src_surface->flags;
2167
2168     return VA_STATUS_SUCCESS;
2169 }
2170
2171 static VAStatus
2172 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2173                             const struct i965_surface *src_surface,
2174                             const VARectangle *src_rect,
2175                             struct i965_surface *dst_surface,
2176                             const VARectangle *dst_rect,
2177                             void *filter_param)
2178 {
2179     return pp_nv12_avs_initialize(ctx, pp_context,
2180                                   src_surface,
2181                                   src_rect,
2182                                   dst_surface,
2183                                   dst_rect,
2184                                   filter_param,
2185                                   1);
2186 }
2187
2188 static VAStatus
2189 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2190                              const struct i965_surface *src_surface,
2191                              const VARectangle *src_rect,
2192                              struct i965_surface *dst_surface,
2193                              const VARectangle *dst_rect,
2194                              void *filter_param)
2195 {
2196     return pp_nv12_avs_initialize(ctx, pp_context,
2197                                   src_surface,
2198                                   src_rect,
2199                                   dst_surface,
2200                                   dst_rect,
2201                                   filter_param,
2202                                   0);
2203 }
2204
2205 static int
2206 gen7_pp_avs_x_steps(void *private_context)
2207 {
2208     struct pp_avs_context *pp_avs_context = private_context;
2209
2210     return pp_avs_context->dest_w / 16;
2211 }
2212
2213 static int
2214 gen7_pp_avs_y_steps(void *private_context)
2215 {
2216     struct pp_avs_context *pp_avs_context = private_context;
2217
2218     return pp_avs_context->dest_h / 16;
2219 }
2220
2221 static int
2222 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2223 {
2224     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2225     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2226
2227     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2228     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2229     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2230     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2231
2232     return 0;
2233 }
2234
2235 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2236                                               struct i965_post_processing_context *pp_context,
2237                                               const struct i965_surface *surface)
2238 {
2239     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2240     int fourcc = pp_get_surface_fourcc(ctx, surface);
2241
2242     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2243         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2244         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2245         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2246     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2247         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2248         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2249         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2250     }
2251 }
2252
2253 static VAStatus
2254 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2255                            const struct i965_surface *src_surface,
2256                            const VARectangle *src_rect,
2257                            struct i965_surface *dst_surface,
2258                            const VARectangle *dst_rect,
2259                            void *filter_param)
2260 {
2261     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2262     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2263     struct gen7_sampler_8x8 *sampler_8x8;
2264     struct i965_sampler_8x8_state *sampler_8x8_state;
2265     int index, i;
2266     int width[3], height[3], pitch[3], offset[3];
2267
2268     /* source surface */
2269     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2270                                          width, height, pitch, offset);
2271
2272     /* destination surface */
2273     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2274                                          width, height, pitch, offset);
2275
2276     /* sampler 8x8 state */
2277     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2278     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2279     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2280     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2281     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2282
2283     for (i = 0; i < 17; i++) {
2284         /* for Y channel, currently ignore */
2285         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2286         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2287         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2288         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2289         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2290         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2291         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2292         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2293         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2294         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2295         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2296         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2297         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2298         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2299         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2300         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2301         /* for U/V channel, 0.25 */
2302         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2303         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2304         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2305         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2306         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2307         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2308         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2309         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2310         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2311         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2312         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2313         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2314         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2315         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2316         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2317         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2318     }
2319
2320     sampler_8x8_state->dw136.default_sharpness_level = 0;
2321     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2322     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2323     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2324     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2325
2326     /* sampler 8x8 */
2327     dri_bo_map(pp_context->sampler_state_table.bo, True);
2328     assert(pp_context->sampler_state_table.bo->virtual);
2329     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2330     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2331
2332     /* sample_8x8 Y index 4 */
2333     index = 4;
2334     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2335     sampler_8x8[index].dw0.global_noise_estimation = 255;
2336     sampler_8x8[index].dw0.ief_bypass = 1;
2337
2338     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2339
2340     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2341     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2342     sampler_8x8[index].dw2.r5x_coefficient = 9;
2343     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2344     sampler_8x8[index].dw2.r5c_coefficient = 3;
2345
2346     sampler_8x8[index].dw3.r3x_coefficient = 27;
2347     sampler_8x8[index].dw3.r3c_coefficient = 5;
2348     sampler_8x8[index].dw3.gain_factor = 40;
2349     sampler_8x8[index].dw3.non_edge_weight = 1;
2350     sampler_8x8[index].dw3.regular_weight = 2;
2351     sampler_8x8[index].dw3.strong_edge_weight = 7;
2352     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2353
2354     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2355                       I915_GEM_DOMAIN_RENDER,
2356                       0,
2357                       0,
2358                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2359                       pp_context->sampler_state_table.bo_8x8);
2360
2361     /* sample_8x8 UV index 8 */
2362     index = 8;
2363     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2364     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2365     sampler_8x8[index].dw0.global_noise_estimation = 255;
2366     sampler_8x8[index].dw0.ief_bypass = 1;
2367     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2368     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2369     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2370     sampler_8x8[index].dw2.r5x_coefficient = 9;
2371     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2372     sampler_8x8[index].dw2.r5c_coefficient = 3;
2373     sampler_8x8[index].dw3.r3x_coefficient = 27;
2374     sampler_8x8[index].dw3.r3c_coefficient = 5;
2375     sampler_8x8[index].dw3.gain_factor = 40;
2376     sampler_8x8[index].dw3.non_edge_weight = 1;
2377     sampler_8x8[index].dw3.regular_weight = 2;
2378     sampler_8x8[index].dw3.strong_edge_weight = 7;
2379     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2380
2381     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2382                       I915_GEM_DOMAIN_RENDER,
2383                       0,
2384                       0,
2385                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2386                       pp_context->sampler_state_table.bo_8x8);
2387
2388     /* sampler_8x8 V, index 12 */
2389     index = 12;
2390     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2391     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2392     sampler_8x8[index].dw0.global_noise_estimation = 255;
2393     sampler_8x8[index].dw0.ief_bypass = 1;
2394     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2395     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2396     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2397     sampler_8x8[index].dw2.r5x_coefficient = 9;
2398     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2399     sampler_8x8[index].dw2.r5c_coefficient = 3;
2400     sampler_8x8[index].dw3.r3x_coefficient = 27;
2401     sampler_8x8[index].dw3.r3c_coefficient = 5;
2402     sampler_8x8[index].dw3.gain_factor = 40;
2403     sampler_8x8[index].dw3.non_edge_weight = 1;
2404     sampler_8x8[index].dw3.regular_weight = 2;
2405     sampler_8x8[index].dw3.strong_edge_weight = 7;
2406     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2407
2408     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2409                       I915_GEM_DOMAIN_RENDER,
2410                       0,
2411                       0,
2412                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2413                       pp_context->sampler_state_table.bo_8x8);
2414
2415     dri_bo_unmap(pp_context->sampler_state_table.bo);
2416
2417     /* private function & data */
2418     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2419     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2420     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2421
2422     pp_avs_context->dest_x = dst_rect->x;
2423     pp_avs_context->dest_y = dst_rect->y;
2424     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2425     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2426     pp_avs_context->src_w = src_rect->width;
2427     pp_avs_context->src_h = src_rect->height;
2428
2429     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2430     dw = MAX(dw, pp_avs_context->dest_w);
2431
2432     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2433     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2434     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2435     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2436     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2437
2438     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2439
2440     dst_surface->flags = src_surface->flags;
2441
2442     return VA_STATUS_SUCCESS;
2443 }
2444
2445 static int
2446 pp_dndi_x_steps(void *private_context)
2447 {
2448     return 1;
2449 }
2450
2451 static int
2452 pp_dndi_y_steps(void *private_context)
2453 {
2454     struct pp_dndi_context *pp_dndi_context = private_context;
2455
2456     return pp_dndi_context->dest_h / 4;
2457 }
2458
2459 static int
2460 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2461 {
2462     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2463
2464     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2465     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2466
2467     return 0;
2468 }
2469
2470 static VAStatus
2471 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2472                         const struct i965_surface *src_surface,
2473                         const VARectangle *src_rect,
2474                         struct i965_surface *dst_surface,
2475                         const VARectangle *dst_rect,
2476                         void *filter_param)
2477 {
2478     struct i965_driver_data *i965 = i965_driver_data(ctx);
2479     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2480     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2481     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2482     struct object_surface *obj_surface;
2483     struct i965_sampler_dndi *sampler_dndi;
2484     int index;
2485     int w, h;
2486     int orig_w, orig_h;
2487     int dndi_top_first = 1;
2488
2489     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2490         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2491
2492     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2493         dndi_top_first = 1;
2494     else
2495         dndi_top_first = 0;
2496
2497     /* surface */
2498     obj_surface = SURFACE(src_surface->id);
2499     orig_w = obj_surface->orig_width;
2500     orig_h = obj_surface->orig_height;
2501     w = obj_surface->width;
2502     h = obj_surface->height;
2503
2504     if (pp_context->stmm.bo == NULL) {
2505         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2506                                            "STMM surface",
2507                                            w * h,
2508                                            4096);
2509         assert(pp_context->stmm.bo);
2510     }
2511
2512     /* source UV surface index 2 */
2513     i965_pp_set_surface_state(ctx, pp_context,
2514                               obj_surface->bo, w * h,
2515                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2516                               2, 0);
2517
2518     /* source YUV surface index 4 */
2519     i965_pp_set_surface2_state(ctx, pp_context,
2520                                obj_surface->bo, 0,
2521                                orig_w, orig_h, w,
2522                                0, h,
2523                                SURFACE_FORMAT_PLANAR_420_8, 1,
2524                                4);
2525
2526     /* source STMM surface index 20 */
2527     i965_pp_set_surface_state(ctx, pp_context,
2528                               pp_context->stmm.bo, 0,
2529                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2530                               20, 1);
2531
2532     /* destination surface */
2533     obj_surface = SURFACE(dst_surface->id);
2534     orig_w = obj_surface->orig_width;
2535     orig_h = obj_surface->orig_height;
2536     w = obj_surface->width;
2537     h = obj_surface->height;
2538
2539     /* destination Y surface index 7 */
2540     i965_pp_set_surface_state(ctx, pp_context,
2541                               obj_surface->bo, 0,
2542                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2543                               7, 1);
2544
2545     /* destination UV surface index 8 */
2546     i965_pp_set_surface_state(ctx, pp_context,
2547                               obj_surface->bo, w * h,
2548                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2549                               8, 1);
2550     /* sampler dndi */
2551     dri_bo_map(pp_context->sampler_state_table.bo, True);
2552     assert(pp_context->sampler_state_table.bo->virtual);
2553     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2554     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2555
2556     /* sample dndi index 1 */
2557     index = 0;
2558     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2559     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2560     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2561     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2562
2563     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2564     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2565     sampler_dndi[index].dw1.stmm_c2 = 1;
2566     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2567     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2568
2569     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2570     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2571     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2572     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2573
2574     sampler_dndi[index].dw3.maximum_stmm = 128;
2575     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2576     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2577     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2578     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2579
2580     sampler_dndi[index].dw4.sdi_delta = 8;
2581     sampler_dndi[index].dw4.sdi_threshold = 128;
2582     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2583     sampler_dndi[index].dw4.stmm_shift_up = 0;
2584     sampler_dndi[index].dw4.stmm_shift_down = 0;
2585     sampler_dndi[index].dw4.minimum_stmm = 0;
2586
2587     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2588     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2589     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2590     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2591
2592     sampler_dndi[index].dw6.dn_enable = 1;
2593     sampler_dndi[index].dw6.di_enable = 1;
2594     sampler_dndi[index].dw6.di_partial = 0;
2595     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2596     sampler_dndi[index].dw6.dndi_stream_id = 0;
2597     sampler_dndi[index].dw6.dndi_first_frame = 1;
2598     sampler_dndi[index].dw6.progressive_dn = 0;
2599     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2600     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2601     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2602
2603     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2604     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2605     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2606     sampler_dndi[index].dw7.column_width_minus1 = 0;
2607
2608     dri_bo_unmap(pp_context->sampler_state_table.bo);
2609
2610     /* private function & data */
2611     pp_context->pp_x_steps = pp_dndi_x_steps;
2612     pp_context->pp_y_steps = pp_dndi_y_steps;
2613     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2614
2615     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2616     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2617     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2618     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2619
2620     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2621     pp_inline_parameter->grf5.number_blocks = w / 16;
2622     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2623     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2624
2625     pp_dndi_context->dest_w = w;
2626     pp_dndi_context->dest_h = h;
2627
2628     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2629
2630     return VA_STATUS_SUCCESS;
2631 }
2632
2633 static int
2634 pp_dn_x_steps(void *private_context)
2635 {
2636     return 1;
2637 }
2638
2639 static int
2640 pp_dn_y_steps(void *private_context)
2641 {
2642     struct pp_dn_context *pp_dn_context = private_context;
2643
2644     return pp_dn_context->dest_h / 8;
2645 }
2646
2647 static int
2648 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2649 {
2650     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2651
2652     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2653     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2654
2655     return 0;
2656 }
2657
2658 static VAStatus
2659 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2660                       const struct i965_surface *src_surface,
2661                       const VARectangle *src_rect,
2662                       struct i965_surface *dst_surface,
2663                       const VARectangle *dst_rect,
2664                       void *filter_param)
2665 {
2666     struct i965_driver_data *i965 = i965_driver_data(ctx);
2667     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2668     struct object_surface *obj_surface;
2669     struct i965_sampler_dndi *sampler_dndi;
2670     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2671     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2672     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2673     int index;
2674     int w, h;
2675     int orig_w, orig_h;
2676     int dn_strength = 15;
2677     int dndi_top_first = 1;
2678     int dn_progressive = 0;
2679
2680     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2681         dndi_top_first = 1;
2682         dn_progressive = 1;
2683     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2684         dndi_top_first = 1;
2685         dn_progressive = 0;
2686     } else {
2687         dndi_top_first = 0;
2688         dn_progressive = 0;
2689     }
2690
2691     if (dn_filter_param) {
2692         float value = dn_filter_param->value;
2693
2694         if (value > 1.0)
2695             value = 1.0;
2696
2697         if (value < 0.0)
2698             value = 0.0;
2699
2700         dn_strength = (int)(value * 31.0F);
2701     }
2702
2703     /* surface */
2704     obj_surface = SURFACE(src_surface->id);
2705     orig_w = obj_surface->orig_width;
2706     orig_h = obj_surface->orig_height;
2707     w = obj_surface->width;
2708     h = obj_surface->height;
2709
2710     if (pp_context->stmm.bo == NULL) {
2711         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2712                                            "STMM surface",
2713                                            w * h,
2714                                            4096);
2715         assert(pp_context->stmm.bo);
2716     }
2717
2718     /* source UV surface index 2 */
2719     i965_pp_set_surface_state(ctx, pp_context,
2720                               obj_surface->bo, w * h,
2721                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2722                               2, 0);
2723
2724     /* source YUV surface index 4 */
2725     i965_pp_set_surface2_state(ctx, pp_context,
2726                                obj_surface->bo, 0,
2727                                orig_w, orig_h, w,
2728                                0, h,
2729                                SURFACE_FORMAT_PLANAR_420_8, 1,
2730                                4);
2731
2732     /* source STMM surface index 20 */
2733     i965_pp_set_surface_state(ctx, pp_context,
2734                               pp_context->stmm.bo, 0,
2735                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2736                               20, 1);
2737
2738     /* destination surface */
2739     obj_surface = SURFACE(dst_surface->id);
2740     orig_w = obj_surface->orig_width;
2741     orig_h = obj_surface->orig_height;
2742     w = obj_surface->width;
2743     h = obj_surface->height;
2744
2745     /* destination Y surface index 7 */
2746     i965_pp_set_surface_state(ctx, pp_context,
2747                               obj_surface->bo, 0,
2748                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2749                               7, 1);
2750
2751     /* destination UV surface index 8 */
2752     i965_pp_set_surface_state(ctx, pp_context,
2753                               obj_surface->bo, w * h,
2754                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2755                               8, 1);
2756     /* sampler dn */
2757     dri_bo_map(pp_context->sampler_state_table.bo, True);
2758     assert(pp_context->sampler_state_table.bo->virtual);
2759     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2760     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2761
2762     /* sample dndi index 1 */
2763     index = 0;
2764     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2765     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2766     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2767     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2768
2769     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2770     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2771     sampler_dndi[index].dw1.stmm_c2 = 0;
2772     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2773     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2774
2775     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2776     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2777     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2778     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2779
2780     sampler_dndi[index].dw3.maximum_stmm = 128;
2781     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2782     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2783     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2784     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2785
2786     sampler_dndi[index].dw4.sdi_delta = 8;
2787     sampler_dndi[index].dw4.sdi_threshold = 128;
2788     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2789     sampler_dndi[index].dw4.stmm_shift_up = 0;
2790     sampler_dndi[index].dw4.stmm_shift_down = 0;
2791     sampler_dndi[index].dw4.minimum_stmm = 0;
2792
2793     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2794     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2795     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2796     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2797
2798     sampler_dndi[index].dw6.dn_enable = 1;
2799     sampler_dndi[index].dw6.di_enable = 0;
2800     sampler_dndi[index].dw6.di_partial = 0;
2801     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2802     sampler_dndi[index].dw6.dndi_stream_id = 1;
2803     sampler_dndi[index].dw6.dndi_first_frame = 1;
2804     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2805     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2806     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2807     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2808
2809     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2810     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2811     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2812     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2813
2814     dri_bo_unmap(pp_context->sampler_state_table.bo);
2815
2816     /* private function & data */
2817     pp_context->pp_x_steps = pp_dn_x_steps;
2818     pp_context->pp_y_steps = pp_dn_y_steps;
2819     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2820
2821     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2822     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2823     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2824     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2825
2826     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2827     pp_inline_parameter->grf5.number_blocks = w / 16;
2828     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2829     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2830
2831     pp_dn_context->dest_w = w;
2832     pp_dn_context->dest_h = h;
2833
2834     dst_surface->flags = src_surface->flags;
2835
2836     return VA_STATUS_SUCCESS;
2837 }
2838
2839 static int
2840 gen7_pp_dndi_x_steps(void *private_context)
2841 {
2842     struct pp_dndi_context *pp_dndi_context = private_context;
2843
2844     return pp_dndi_context->dest_w / 16;
2845 }
2846
2847 static int
2848 gen7_pp_dndi_y_steps(void *private_context)
2849 {
2850     struct pp_dndi_context *pp_dndi_context = private_context;
2851
2852     return pp_dndi_context->dest_h / 4;
2853 }
2854
2855 static int
2856 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2857 {
2858     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2859
2860     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2861     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2862
2863     return 0;
2864 }
2865
2866 static VAStatus
2867 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2868                              const struct i965_surface *src_surface,
2869                              const VARectangle *src_rect,
2870                              struct i965_surface *dst_surface,
2871                              const VARectangle *dst_rect,
2872                              void *filter_param)
2873 {
2874     struct i965_driver_data *i965 = i965_driver_data(ctx);
2875     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2876     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2877     struct object_surface *obj_surface;
2878     struct gen7_sampler_dndi *sampler_dndi;
2879     int index;
2880     int w, h;
2881     int orig_w, orig_h;
2882     int dndi_top_first = 1;
2883
2884     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2885         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2886
2887     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2888         dndi_top_first = 1;
2889     else
2890         dndi_top_first = 0;
2891
2892     /* surface */
2893     obj_surface = SURFACE(src_surface->id);
2894     orig_w = obj_surface->orig_width;
2895     orig_h = obj_surface->orig_height;
2896     w = obj_surface->width;
2897     h = obj_surface->height;
2898
2899     if (pp_context->stmm.bo == NULL) {
2900         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2901                                            "STMM surface",
2902                                            w * h,
2903                                            4096);
2904         assert(pp_context->stmm.bo);
2905     }
2906
2907     /* source UV surface index 1 */
2908     gen7_pp_set_surface_state(ctx, pp_context,
2909                               obj_surface->bo, w * h,
2910                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2911                               1, 0);
2912
2913     /* source YUV surface index 3 */
2914     gen7_pp_set_surface2_state(ctx, pp_context,
2915                                obj_surface->bo, 0,
2916                                orig_w, orig_h, w,
2917                                0, h,
2918                                SURFACE_FORMAT_PLANAR_420_8, 1,
2919                                3);
2920
2921     /* source (temporal reference) YUV surface index 4 */
2922     gen7_pp_set_surface2_state(ctx, pp_context,
2923                                obj_surface->bo, 0,
2924                                orig_w, orig_h, w,
2925                                0, h,
2926                                SURFACE_FORMAT_PLANAR_420_8, 1,
2927                                4);
2928
2929     /* STMM / History Statistics input surface, index 5 */
2930     gen7_pp_set_surface_state(ctx, pp_context,
2931                               pp_context->stmm.bo, 0,
2932                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2933                               5, 1);
2934
2935     /* destination surface */
2936     obj_surface = SURFACE(dst_surface->id);
2937     orig_w = obj_surface->orig_width;
2938     orig_h = obj_surface->orig_height;
2939     w = obj_surface->width;
2940     h = obj_surface->height;
2941
2942     /* destination(Previous frame) Y surface index 27 */
2943     gen7_pp_set_surface_state(ctx, pp_context,
2944                               obj_surface->bo, 0,
2945                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2946                               27, 1);
2947
2948     /* destination(Previous frame) UV surface index 28 */
2949     gen7_pp_set_surface_state(ctx, pp_context,
2950                               obj_surface->bo, w * h,
2951                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2952                               28, 1);
2953
2954     /* destination(Current frame) Y surface index 30 */
2955     gen7_pp_set_surface_state(ctx, pp_context,
2956                               obj_surface->bo, 0,
2957                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2958                               30, 1);
2959
2960     /* destination(Current frame) UV surface index 31 */
2961     gen7_pp_set_surface_state(ctx, pp_context,
2962                               obj_surface->bo, w * h,
2963                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2964                               31, 1);
2965
2966     /* STMM output surface, index 33 */
2967     gen7_pp_set_surface_state(ctx, pp_context,
2968                               pp_context->stmm.bo, 0,
2969                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2970                               33, 1);
2971
2972
2973     /* sampler dndi */
2974     dri_bo_map(pp_context->sampler_state_table.bo, True);
2975     assert(pp_context->sampler_state_table.bo->virtual);
2976     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2977     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2978
2979     /* sample dndi index 0 */
2980     index = 0;
2981     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2982     sampler_dndi[index].dw0.dnmh_delt = 8;
2983     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2984     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2985     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2986     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2987
2988     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2989     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2990     sampler_dndi[index].dw1.stmm_c2 = 0;
2991     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2992     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2993
2994     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2995     sampler_dndi[index].dw2.bne_edge_th = 1;
2996     sampler_dndi[index].dw2.smooth_mv_th = 0;
2997     sampler_dndi[index].dw2.sad_tight_th = 5;
2998     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2999     sampler_dndi[index].dw2.good_neighbor_th = 4;
3000
3001     sampler_dndi[index].dw3.maximum_stmm = 128;
3002     sampler_dndi[index].dw3.multipler_for_vecm = 2;
3003     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3004     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3005     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
3006
3007     sampler_dndi[index].dw4.sdi_delta = 8;
3008     sampler_dndi[index].dw4.sdi_threshold = 128;
3009     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3010     sampler_dndi[index].dw4.stmm_shift_up = 0;
3011     sampler_dndi[index].dw4.stmm_shift_down = 0;
3012     sampler_dndi[index].dw4.minimum_stmm = 0;
3013
3014     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
3015     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
3016     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3017     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3018
3019     sampler_dndi[index].dw6.dn_enable = 0;
3020     sampler_dndi[index].dw6.di_enable = 1;
3021     sampler_dndi[index].dw6.di_partial = 0;
3022     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
3023     sampler_dndi[index].dw6.dndi_stream_id = 1;
3024     sampler_dndi[index].dw6.dndi_first_frame = 1;
3025     sampler_dndi[index].dw6.progressive_dn = 0;
3026     sampler_dndi[index].dw6.mcdi_enable = 0;
3027     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3028     sampler_dndi[index].dw6.cat_th1 = 0;
3029     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3030     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3031
3032     sampler_dndi[index].dw7.sad_tha = 5;
3033     sampler_dndi[index].dw7.sad_thb = 10;
3034     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3035     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3036     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3037     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3038     sampler_dndi[index].dw7.neighborpixel_th = 10;
3039     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3040
3041     dri_bo_unmap(pp_context->sampler_state_table.bo);
3042
3043     /* private function & data */
3044     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3045     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3046     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3047
3048     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3049     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3050     pp_static_parameter->grf1.di_top_field_first = 0;
3051     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3052
3053     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3054     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3055     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3056
3057     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3058     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3059
3060     pp_dndi_context->dest_w = w;
3061     pp_dndi_context->dest_h = h;
3062
3063     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3064
3065     return VA_STATUS_SUCCESS;
3066 }
3067
3068 static int
3069 gen7_pp_dn_x_steps(void *private_context)
3070 {
3071     return 1;
3072 }
3073
3074 static int
3075 gen7_pp_dn_y_steps(void *private_context)
3076 {
3077     struct pp_dn_context *pp_dn_context = private_context;
3078
3079     return pp_dn_context->dest_h / 4;
3080 }
3081
3082 static int
3083 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3084 {
3085     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3086
3087     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3088     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3089
3090     return 0;
3091 }
3092
3093 static VAStatus
3094 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3095                            const struct i965_surface *src_surface,
3096                            const VARectangle *src_rect,
3097                            struct i965_surface *dst_surface,
3098                            const VARectangle *dst_rect,
3099                            void *filter_param)
3100 {
3101     struct i965_driver_data *i965 = i965_driver_data(ctx);
3102     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3103     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3104     struct object_surface *obj_surface;
3105     struct gen7_sampler_dndi *sampler_dn;
3106     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3107     int index;
3108     int w, h;
3109     int orig_w, orig_h;
3110     int dn_strength = 15;
3111     int dndi_top_first = 1;
3112     int dn_progressive = 0;
3113
3114     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3115         dndi_top_first = 1;
3116         dn_progressive = 1;
3117     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3118         dndi_top_first = 1;
3119         dn_progressive = 0;
3120     } else {
3121         dndi_top_first = 0;
3122         dn_progressive = 0;
3123     }
3124
3125     if (dn_filter_param) {
3126         float value = dn_filter_param->value;
3127
3128         if (value > 1.0)
3129             value = 1.0;
3130
3131         if (value < 0.0)
3132             value = 0.0;
3133
3134         dn_strength = (int)(value * 31.0F);
3135     }
3136
3137     /* surface */
3138     obj_surface = SURFACE(src_surface->id);
3139     orig_w = obj_surface->orig_width;
3140     orig_h = obj_surface->orig_height;
3141     w = obj_surface->width;
3142     h = obj_surface->height;
3143
3144     if (pp_context->stmm.bo == NULL) {
3145         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3146                                            "STMM surface",
3147                                            w * h,
3148                                            4096);
3149         assert(pp_context->stmm.bo);
3150     }
3151
3152     /* source UV surface index 1 */
3153     gen7_pp_set_surface_state(ctx, pp_context,
3154                               obj_surface->bo, w * h,
3155                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3156                               1, 0);
3157
3158     /* source YUV surface index 3 */
3159     gen7_pp_set_surface2_state(ctx, pp_context,
3160                                obj_surface->bo, 0,
3161                                orig_w, orig_h, w,
3162                                0, h,
3163                                SURFACE_FORMAT_PLANAR_420_8, 1,
3164                                3);
3165
3166     /* source STMM surface index 5 */
3167     gen7_pp_set_surface_state(ctx, pp_context,
3168                               pp_context->stmm.bo, 0,
3169                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3170                               5, 1);
3171
3172     /* destination surface */
3173     obj_surface = SURFACE(dst_surface->id);
3174     orig_w = obj_surface->orig_width;
3175     orig_h = obj_surface->orig_height;
3176     w = obj_surface->width;
3177     h = obj_surface->height;
3178
3179     /* destination Y surface index 7 */
3180     gen7_pp_set_surface_state(ctx, pp_context,
3181                               obj_surface->bo, 0,
3182                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3183                               7, 1);
3184
3185     /* destination UV surface index 8 */
3186     gen7_pp_set_surface_state(ctx, pp_context,
3187                               obj_surface->bo, w * h,
3188                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3189                               8, 1);
3190     /* sampler dn */
3191     dri_bo_map(pp_context->sampler_state_table.bo, True);
3192     assert(pp_context->sampler_state_table.bo->virtual);
3193     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3194     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3195
3196     /* sample dn index 1 */
3197     index = 0;
3198     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3199     sampler_dn[index].dw0.dnmh_delt = 8;
3200     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3201     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3202     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3203     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3204
3205     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3206     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3207     sampler_dn[index].dw1.stmm_c2 = 0;
3208     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3209     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3210
3211     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3212     sampler_dn[index].dw2.bne_edge_th = 1;
3213     sampler_dn[index].dw2.smooth_mv_th = 0;
3214     sampler_dn[index].dw2.sad_tight_th = 5;
3215     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3216     sampler_dn[index].dw2.good_neighbor_th = 4;
3217
3218     sampler_dn[index].dw3.maximum_stmm = 128;
3219     sampler_dn[index].dw3.multipler_for_vecm = 2;
3220     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3221     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3222     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3223
3224     sampler_dn[index].dw4.sdi_delta = 8;
3225     sampler_dn[index].dw4.sdi_threshold = 128;
3226     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3227     sampler_dn[index].dw4.stmm_shift_up = 0;
3228     sampler_dn[index].dw4.stmm_shift_down = 0;
3229     sampler_dn[index].dw4.minimum_stmm = 0;
3230
3231     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3232     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3233     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3234     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3235
3236     sampler_dn[index].dw6.dn_enable = 1;
3237     sampler_dn[index].dw6.di_enable = 0;
3238     sampler_dn[index].dw6.di_partial = 0;
3239     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3240     sampler_dn[index].dw6.dndi_stream_id = 1;
3241     sampler_dn[index].dw6.dndi_first_frame = 1;
3242     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3243     sampler_dn[index].dw6.mcdi_enable = 0;
3244     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3245     sampler_dn[index].dw6.cat_th1 = 0;
3246     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3247     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3248
3249     sampler_dn[index].dw7.sad_tha = 5;
3250     sampler_dn[index].dw7.sad_thb = 10;
3251     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3252     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3253     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3254     sampler_dn[index].dw7.vdi_walker_enable = 0;
3255     sampler_dn[index].dw7.neighborpixel_th = 10;
3256     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3257
3258     dri_bo_unmap(pp_context->sampler_state_table.bo);
3259
3260     /* private function & data */
3261     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3262     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3263     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3264
3265     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3266     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3267     pp_static_parameter->grf1.di_top_field_first = 0;
3268     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3269
3270     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3271     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3272     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3273
3274     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3275     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3276
3277     pp_dn_context->dest_w = w;
3278     pp_dn_context->dest_h = h;
3279
3280     dst_surface->flags = src_surface->flags;
3281
3282     return VA_STATUS_SUCCESS;
3283 }
3284
3285 static VAStatus
3286 ironlake_pp_initialize(
3287     VADriverContextP   ctx,
3288     struct i965_post_processing_context *pp_context,
3289     const struct i965_surface *src_surface,
3290     const VARectangle *src_rect,
3291     struct i965_surface *dst_surface,
3292     const VARectangle *dst_rect,
3293     int                pp_index,
3294     void *filter_param
3295 )
3296 {
3297     VAStatus va_status;
3298     struct i965_driver_data *i965 = i965_driver_data(ctx);
3299     struct pp_module *pp_module;
3300     dri_bo *bo;
3301     int static_param_size, inline_param_size;
3302
3303     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3304     bo = dri_bo_alloc(i965->intel.bufmgr,
3305                       "surface state & binding table",
3306                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3307                       4096);
3308     assert(bo);
3309     pp_context->surface_state_binding_table.bo = bo;
3310
3311     dri_bo_unreference(pp_context->curbe.bo);
3312     bo = dri_bo_alloc(i965->intel.bufmgr,
3313                       "constant buffer",
3314                       4096,
3315                       4096);
3316     assert(bo);
3317     pp_context->curbe.bo = bo;
3318
3319     dri_bo_unreference(pp_context->idrt.bo);
3320     bo = dri_bo_alloc(i965->intel.bufmgr,
3321                       "interface discriptor",
3322                       sizeof(struct i965_interface_descriptor),
3323                       4096);
3324     assert(bo);
3325     pp_context->idrt.bo = bo;
3326     pp_context->idrt.num_interface_descriptors = 0;
3327
3328     dri_bo_unreference(pp_context->sampler_state_table.bo);
3329     bo = dri_bo_alloc(i965->intel.bufmgr,
3330                       "sampler state table",
3331                       4096,
3332                       4096);
3333     assert(bo);
3334     dri_bo_map(bo, True);
3335     memset(bo->virtual, 0, bo->size);
3336     dri_bo_unmap(bo);
3337     pp_context->sampler_state_table.bo = bo;
3338
3339     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3340     bo = dri_bo_alloc(i965->intel.bufmgr,
3341                       "sampler 8x8 state ",
3342                       4096,
3343                       4096);
3344     assert(bo);
3345     pp_context->sampler_state_table.bo_8x8 = bo;
3346
3347     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3348     bo = dri_bo_alloc(i965->intel.bufmgr,
3349                       "sampler 8x8 state ",
3350                       4096,
3351                       4096);
3352     assert(bo);
3353     pp_context->sampler_state_table.bo_8x8_uv = bo;
3354
3355     dri_bo_unreference(pp_context->vfe_state.bo);
3356     bo = dri_bo_alloc(i965->intel.bufmgr,
3357                       "vfe state",
3358                       sizeof(struct i965_vfe_state),
3359                       4096);
3360     assert(bo);
3361     pp_context->vfe_state.bo = bo;
3362
3363     static_param_size = sizeof(struct pp_static_parameter);
3364     inline_param_size = sizeof(struct pp_inline_parameter);
3365
3366     memset(pp_context->pp_static_parameter, 0, static_param_size);
3367     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3368
3369     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3370     pp_context->current_pp = pp_index;
3371     pp_module = &pp_context->pp_modules[pp_index];
3372
3373     if (pp_module->initialize)
3374         va_status = pp_module->initialize(ctx, pp_context,
3375                                           src_surface,
3376                                           src_rect,
3377                                           dst_surface,
3378                                           dst_rect,
3379                                           filter_param);
3380     else
3381         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3382
3383     return va_status;
3384 }
3385
3386 static VAStatus
3387 ironlake_post_processing(
3388     VADriverContextP   ctx,
3389     struct i965_post_processing_context *pp_context,
3390     const struct i965_surface *src_surface,
3391     const VARectangle *src_rect,
3392     struct i965_surface *dst_surface,
3393     const VARectangle *dst_rect,
3394     int                pp_index,
3395     void *filter_param
3396 )
3397 {
3398     VAStatus va_status;
3399
3400     va_status = ironlake_pp_initialize(ctx, pp_context,
3401                                        src_surface,
3402                                        src_rect,
3403                                        dst_surface,
3404                                        dst_rect,
3405                                        pp_index,
3406                                        filter_param);
3407
3408     if (va_status == VA_STATUS_SUCCESS) {
3409         ironlake_pp_states_setup(ctx, pp_context);
3410         ironlake_pp_pipeline_setup(ctx, pp_context);
3411     }
3412
3413     return va_status;
3414 }
3415
3416 static VAStatus
3417 gen6_pp_initialize(
3418     VADriverContextP   ctx,
3419     struct i965_post_processing_context *pp_context,
3420     const struct i965_surface *src_surface,
3421     const VARectangle *src_rect,
3422     struct i965_surface *dst_surface,
3423     const VARectangle *dst_rect,
3424     int                pp_index,
3425     void *filter_param
3426 )
3427 {
3428     VAStatus va_status;
3429     struct i965_driver_data *i965 = i965_driver_data(ctx);
3430     struct pp_module *pp_module;
3431     dri_bo *bo;
3432     int static_param_size, inline_param_size;
3433
3434     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3435     bo = dri_bo_alloc(i965->intel.bufmgr,
3436                       "surface state & binding table",
3437                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3438                       4096);
3439     assert(bo);
3440     pp_context->surface_state_binding_table.bo = bo;
3441
3442     dri_bo_unreference(pp_context->curbe.bo);
3443     bo = dri_bo_alloc(i965->intel.bufmgr,
3444                       "constant buffer",
3445                       4096,
3446                       4096);
3447     assert(bo);
3448     pp_context->curbe.bo = bo;
3449
3450     dri_bo_unreference(pp_context->idrt.bo);
3451     bo = dri_bo_alloc(i965->intel.bufmgr,
3452                       "interface discriptor",
3453                       sizeof(struct gen6_interface_descriptor_data),
3454                       4096);
3455     assert(bo);
3456     pp_context->idrt.bo = bo;
3457     pp_context->idrt.num_interface_descriptors = 0;
3458
3459     dri_bo_unreference(pp_context->sampler_state_table.bo);
3460     bo = dri_bo_alloc(i965->intel.bufmgr,
3461                       "sampler state table",
3462                       4096,
3463                       4096);
3464     assert(bo);
3465     dri_bo_map(bo, True);
3466     memset(bo->virtual, 0, bo->size);
3467     dri_bo_unmap(bo);
3468     pp_context->sampler_state_table.bo = bo;
3469
3470     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3471     bo = dri_bo_alloc(i965->intel.bufmgr,
3472                       "sampler 8x8 state ",
3473                       4096,
3474                       4096);
3475     assert(bo);
3476     pp_context->sampler_state_table.bo_8x8 = bo;
3477
3478     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3479     bo = dri_bo_alloc(i965->intel.bufmgr,
3480                       "sampler 8x8 state ",
3481                       4096,
3482                       4096);
3483     assert(bo);
3484     pp_context->sampler_state_table.bo_8x8_uv = bo;
3485
3486     dri_bo_unreference(pp_context->vfe_state.bo);
3487     bo = dri_bo_alloc(i965->intel.bufmgr,
3488                       "vfe state",
3489                       sizeof(struct i965_vfe_state),
3490                       4096);
3491     assert(bo);
3492     pp_context->vfe_state.bo = bo;
3493
3494     if (IS_GEN7(i965->intel.device_id)) {
3495         static_param_size = sizeof(struct gen7_pp_static_parameter);
3496         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3497     } else {
3498         static_param_size = sizeof(struct pp_static_parameter);
3499         inline_param_size = sizeof(struct pp_inline_parameter);
3500     }
3501
3502     memset(pp_context->pp_static_parameter, 0, static_param_size);
3503     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3504
3505     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3506     pp_context->current_pp = pp_index;
3507     pp_module = &pp_context->pp_modules[pp_index];
3508
3509     if (pp_module->initialize)
3510         va_status = pp_module->initialize(ctx, pp_context,
3511                                           src_surface,
3512                                           src_rect,
3513                                           dst_surface,
3514                                           dst_rect,
3515                                           filter_param);
3516     else
3517         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3518
3519     return va_status;
3520 }
3521
3522 static void
3523 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3524                                    struct i965_post_processing_context *pp_context)
3525 {
3526     struct i965_driver_data *i965 = i965_driver_data(ctx);
3527     struct gen6_interface_descriptor_data *desc;
3528     dri_bo *bo;
3529     int pp_index = pp_context->current_pp;
3530
3531     bo = pp_context->idrt.bo;
3532     dri_bo_map(bo, True);
3533     assert(bo->virtual);
3534     desc = bo->virtual;
3535     memset(desc, 0, sizeof(*desc));
3536     desc->desc0.kernel_start_pointer =
3537         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3538     desc->desc1.single_program_flow = 1;
3539     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3540     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3541     desc->desc2.sampler_state_pointer =
3542         pp_context->sampler_state_table.bo->offset >> 5;
3543     desc->desc3.binding_table_entry_count = 0;
3544     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3545     desc->desc4.constant_urb_entry_read_offset = 0;
3546
3547     if (IS_GEN7(i965->intel.device_id))
3548         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3549     else
3550         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3551
3552     dri_bo_emit_reloc(bo,
3553                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3554                       0,
3555                       offsetof(struct gen6_interface_descriptor_data, desc0),
3556                       pp_context->pp_modules[pp_index].kernel.bo);
3557
3558     dri_bo_emit_reloc(bo,
3559                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3560                       desc->desc2.sampler_count << 2,
3561                       offsetof(struct gen6_interface_descriptor_data, desc2),
3562                       pp_context->sampler_state_table.bo);
3563
3564     dri_bo_unmap(bo);
3565     pp_context->idrt.num_interface_descriptors++;
3566 }
3567
3568 static void
3569 gen6_pp_upload_constants(VADriverContextP ctx,
3570                          struct i965_post_processing_context *pp_context)
3571 {
3572     struct i965_driver_data *i965 = i965_driver_data(ctx);
3573     unsigned char *constant_buffer;
3574     int param_size;
3575
3576     assert(sizeof(struct pp_static_parameter) == 128);
3577     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3578
3579     if (IS_GEN7(i965->intel.device_id))
3580         param_size = sizeof(struct gen7_pp_static_parameter);
3581     else
3582         param_size = sizeof(struct pp_static_parameter);
3583
3584     dri_bo_map(pp_context->curbe.bo, 1);
3585     assert(pp_context->curbe.bo->virtual);
3586     constant_buffer = pp_context->curbe.bo->virtual;
3587     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3588     dri_bo_unmap(pp_context->curbe.bo);
3589 }
3590
3591 static void
3592 gen6_pp_states_setup(VADriverContextP ctx,
3593                      struct i965_post_processing_context *pp_context)
3594 {
3595     gen6_pp_interface_descriptor_table(ctx, pp_context);
3596     gen6_pp_upload_constants(ctx, pp_context);
3597 }
3598
3599 static void
3600 gen6_pp_pipeline_select(VADriverContextP ctx,
3601                         struct i965_post_processing_context *pp_context)
3602 {
3603     struct intel_batchbuffer *batch = pp_context->batch;
3604
3605     BEGIN_BATCH(batch, 1);
3606     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3607     ADVANCE_BATCH(batch);
3608 }
3609
3610 static void
3611 gen6_pp_state_base_address(VADriverContextP ctx,
3612                            struct i965_post_processing_context *pp_context)
3613 {
3614     struct intel_batchbuffer *batch = pp_context->batch;
3615
3616     BEGIN_BATCH(batch, 10);
3617     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3618     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3619     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3620     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3621     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3622     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3623     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3624     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3625     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3626     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3627     ADVANCE_BATCH(batch);
3628 }
3629
3630 static void
3631 gen6_pp_vfe_state(VADriverContextP ctx,
3632                   struct i965_post_processing_context *pp_context)
3633 {
3634     struct intel_batchbuffer *batch = pp_context->batch;
3635
3636     BEGIN_BATCH(batch, 8);
3637     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3638     OUT_BATCH(batch, 0);
3639     OUT_BATCH(batch,
3640               (pp_context->urb.num_vfe_entries - 1) << 16 |
3641               pp_context->urb.num_vfe_entries << 8);
3642     OUT_BATCH(batch, 0);
3643     OUT_BATCH(batch,
3644               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3645               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3646     OUT_BATCH(batch, 0);
3647     OUT_BATCH(batch, 0);
3648     OUT_BATCH(batch, 0);
3649     ADVANCE_BATCH(batch);
3650 }
3651
3652 static void
3653 gen6_pp_curbe_load(VADriverContextP ctx,
3654                    struct i965_post_processing_context *pp_context)
3655 {
3656     struct intel_batchbuffer *batch = pp_context->batch;
3657
3658     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3659
3660     BEGIN_BATCH(batch, 4);
3661     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3662     OUT_BATCH(batch, 0);
3663     OUT_BATCH(batch,
3664               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3665     OUT_RELOC(batch,
3666               pp_context->curbe.bo,
3667               I915_GEM_DOMAIN_INSTRUCTION, 0,
3668               0);
3669     ADVANCE_BATCH(batch);
3670 }
3671
3672 static void
3673 gen6_interface_descriptor_load(VADriverContextP ctx,
3674                                struct i965_post_processing_context *pp_context)
3675 {
3676     struct intel_batchbuffer *batch = pp_context->batch;
3677
3678     BEGIN_BATCH(batch, 4);
3679     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3680     OUT_BATCH(batch, 0);
3681     OUT_BATCH(batch,
3682               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3683     OUT_RELOC(batch,
3684               pp_context->idrt.bo,
3685               I915_GEM_DOMAIN_INSTRUCTION, 0,
3686               0);
3687     ADVANCE_BATCH(batch);
3688 }
3689
3690 static void
3691 gen6_pp_object_walker(VADriverContextP ctx,
3692                       struct i965_post_processing_context *pp_context)
3693 {
3694     struct i965_driver_data *i965 = i965_driver_data(ctx);
3695     struct intel_batchbuffer *batch = pp_context->batch;
3696     int x, x_steps, y, y_steps;
3697     int param_size, command_length_in_dws;
3698     dri_bo *command_buffer;
3699     unsigned int *command_ptr;
3700
3701     if (IS_GEN7(i965->intel.device_id))
3702         param_size = sizeof(struct gen7_pp_inline_parameter);
3703     else
3704         param_size = sizeof(struct pp_inline_parameter);
3705
3706     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3707     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3708     command_length_in_dws = 6 + (param_size >> 2);
3709     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3710                                   "command objects buffer",
3711                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3712                                   4096);
3713
3714     dri_bo_map(command_buffer, 1);
3715     command_ptr = command_buffer->virtual;
3716
3717     for (y = 0; y < y_steps; y++) {
3718         for (x = 0; x < x_steps; x++) {
3719             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3720                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3721                 *command_ptr++ = 0;
3722                 *command_ptr++ = 0;
3723                 *command_ptr++ = 0;
3724                 *command_ptr++ = 0;
3725                 *command_ptr++ = 0;
3726                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3727                 command_ptr += (param_size >> 2);
3728             }
3729         }
3730     }
3731
3732     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3733         *command_ptr++ = 0;
3734
3735     *command_ptr = MI_BATCH_BUFFER_END;
3736
3737     dri_bo_unmap(command_buffer);
3738
3739     BEGIN_BATCH(batch, 2);
3740     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3741     OUT_RELOC(batch, command_buffer,
3742               I915_GEM_DOMAIN_COMMAND, 0,
3743               0);
3744     ADVANCE_BATCH(batch);
3745
3746     dri_bo_unreference(command_buffer);
3747
3748     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3749      * will cause control to pass back to ring buffer
3750      */
3751     intel_batchbuffer_end_atomic(batch);
3752     intel_batchbuffer_flush(batch);
3753     intel_batchbuffer_start_atomic(batch, 0x1000);
3754 }
3755
3756 static void
3757 gen6_pp_pipeline_setup(VADriverContextP ctx,
3758                        struct i965_post_processing_context *pp_context)
3759 {
3760     struct intel_batchbuffer *batch = pp_context->batch;
3761
3762     intel_batchbuffer_start_atomic(batch, 0x1000);
3763     intel_batchbuffer_emit_mi_flush(batch);
3764     gen6_pp_pipeline_select(ctx, pp_context);
3765     gen6_pp_state_base_address(ctx, pp_context);
3766     gen6_pp_vfe_state(ctx, pp_context);
3767     gen6_pp_curbe_load(ctx, pp_context);
3768     gen6_interface_descriptor_load(ctx, pp_context);
3769     gen6_pp_object_walker(ctx, pp_context);
3770     intel_batchbuffer_end_atomic(batch);
3771 }
3772
3773 static VAStatus
3774 gen6_post_processing(
3775     VADriverContextP   ctx,
3776     struct i965_post_processing_context *pp_context,
3777     const struct i965_surface *src_surface,
3778     const VARectangle *src_rect,
3779     struct i965_surface *dst_surface,
3780     const VARectangle *dst_rect,
3781     int                pp_index,
3782     void * filter_param
3783 )
3784 {
3785     VAStatus va_status;
3786
3787     va_status = gen6_pp_initialize(ctx, pp_context,
3788                                    src_surface,
3789                                    src_rect,
3790                                    dst_surface,
3791                                    dst_rect,
3792                                    pp_index,
3793                                    filter_param);
3794
3795     if (va_status == VA_STATUS_SUCCESS) {
3796         gen6_pp_states_setup(ctx, pp_context);
3797         gen6_pp_pipeline_setup(ctx, pp_context);
3798     }
3799
3800     return va_status;
3801 }
3802
3803 static VAStatus
3804 i965_post_processing_internal(
3805     VADriverContextP   ctx,
3806     struct i965_post_processing_context *pp_context,
3807     const struct i965_surface *src_surface,
3808     const VARectangle *src_rect,
3809     struct i965_surface *dst_surface,
3810     const VARectangle *dst_rect,
3811     int                pp_index,
3812     void *filter_param
3813 )
3814 {
3815     struct i965_driver_data *i965 = i965_driver_data(ctx);
3816     VAStatus va_status;
3817
3818     if (IS_GEN6(i965->intel.device_id) ||
3819         IS_GEN7(i965->intel.device_id))
3820         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3821     else
3822         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3823
3824     return va_status;
3825 }
3826
3827 VAStatus
3828 i965_DestroySurfaces(VADriverContextP ctx,
3829                      VASurfaceID *surface_list,
3830                      int num_surfaces);
3831 VAStatus
3832 i965_CreateSurfaces(VADriverContextP ctx,
3833                     int width,
3834                     int height,
3835                     int format,
3836                     int num_surfaces,
3837                     VASurfaceID *surfaces);
3838
3839 static void
3840 rgb_to_yuv(unsigned int argb,
3841            unsigned char *y,
3842            unsigned char *u,
3843            unsigned char *v,
3844            unsigned char *a)
3845 {
3846     int r = ((argb >> 16) & 0xff);
3847     int g = ((argb >> 8) & 0xff);
3848     int b = ((argb >> 0) & 0xff);
3849
3850     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3851     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3852     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3853     *a = ((argb >> 24) & 0xff);
3854 }
3855
3856 static void
3857 i965_vpp_clear_surface(VADriverContextP ctx,
3858                        struct i965_post_processing_context *pp_context,
3859                        VASurfaceID surface,
3860                        unsigned int color)
3861 {
3862     struct i965_driver_data *i965 = i965_driver_data(ctx);
3863     struct intel_batchbuffer *batch = pp_context->batch;
3864     struct object_surface *obj_surface = SURFACE(surface);
3865     unsigned int blt_cmd, br13;
3866     unsigned int tiling = 0, swizzle = 0;
3867     int pitch;
3868     unsigned char y, u, v, a = 0;
3869
3870     /* Currently only support NV12 surface */
3871     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3872         return;
3873
3874     rgb_to_yuv(color, &y, &u, &v, &a);
3875
3876     if (a == 0)
3877         return;
3878
3879     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3880     blt_cmd = XY_COLOR_BLT_CMD;
3881     pitch = obj_surface->width;
3882
3883     if (tiling != I915_TILING_NONE) {
3884         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3885         pitch >>= 2;
3886     }
3887
3888     br13 = 0xf0 << 16;
3889     br13 |= BR13_8;
3890     br13 |= pitch;
3891
3892     if (IS_GEN6(i965->intel.device_id) ||
3893         IS_GEN7(i965->intel.device_id)) {
3894         intel_batchbuffer_start_atomic_blt(batch, 48);
3895         BEGIN_BLT_BATCH(batch, 12);
3896     } else {
3897         intel_batchbuffer_start_atomic(batch, 48);
3898         BEGIN_BATCH(batch, 12);
3899     }
3900
3901     OUT_BATCH(batch, blt_cmd);
3902     OUT_BATCH(batch, br13);
3903     OUT_BATCH(batch,
3904               0 << 16 |
3905               0);
3906     OUT_BATCH(batch,
3907               obj_surface->height << 16 |
3908               obj_surface->width);
3909     OUT_RELOC(batch, obj_surface->bo,
3910               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3911               0);
3912     OUT_BATCH(batch, y);
3913
3914     br13 = 0xf0 << 16;
3915     br13 |= BR13_565;
3916     br13 |= pitch;
3917
3918     OUT_BATCH(batch, blt_cmd);
3919     OUT_BATCH(batch, br13);
3920     OUT_BATCH(batch,
3921               0 << 16 |
3922               0);
3923     OUT_BATCH(batch,
3924               obj_surface->height / 2 << 16 |
3925               obj_surface->width / 2);
3926     OUT_RELOC(batch, obj_surface->bo,
3927               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3928               obj_surface->width * obj_surface->y_cb_offset);
3929     OUT_BATCH(batch, v << 8 | u);
3930
3931     ADVANCE_BATCH(batch);
3932     intel_batchbuffer_end_atomic(batch);
3933 }
3934
3935 VASurfaceID
3936 i965_post_processing(
3937     VADriverContextP   ctx,
3938     VASurfaceID        surface,
3939     const VARectangle *src_rect,
3940     const VARectangle *dst_rect,
3941     unsigned int       flags,
3942     int               *has_done_scaling
3943 )
3944 {
3945     struct i965_driver_data *i965 = i965_driver_data(ctx);
3946     VASurfaceID in_surface_id = surface;
3947     VASurfaceID out_surface_id = VA_INVALID_ID;
3948
3949     *has_done_scaling = 0;
3950
3951     if (HAS_PP(i965)) {
3952         struct object_surface *obj_surface;
3953         VAStatus status;
3954         struct i965_surface src_surface;
3955         struct i965_surface dst_surface;
3956
3957         obj_surface = SURFACE(in_surface_id);
3958
3959         /* Currently only support post processing for NV12 surface */
3960         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3961             return out_surface_id;
3962
3963         _i965LockMutex(&i965->pp_mutex);
3964
3965         if (flags & I965_PP_FLAG_MCDI) {
3966             status = i965_CreateSurfaces(ctx,
3967                                          obj_surface->orig_width,
3968                                          obj_surface->orig_height,
3969                                          VA_RT_FORMAT_YUV420,
3970                                          1,
3971                                          &out_surface_id);
3972             assert(status == VA_STATUS_SUCCESS);
3973             obj_surface = SURFACE(out_surface_id);
3974             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3975             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3976             src_surface.id = in_surface_id;
3977             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3978             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3979                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3980             dst_surface.id = out_surface_id;
3981             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3982             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3983
3984             i965_post_processing_internal(ctx, i965->pp_context,
3985                                           &src_surface,
3986                                           src_rect,
3987                                           &dst_surface,
3988                                           dst_rect,
3989                                           PP_NV12_DNDI,
3990                                           NULL);
3991         }
3992
3993         if (flags & I965_PP_FLAG_AVS) {
3994             struct i965_render_state *render_state = &i965->render_state;
3995             struct intel_region *dest_region = render_state->draw_region;
3996
3997             if (out_surface_id != VA_INVALID_ID)
3998                 in_surface_id = out_surface_id;
3999
4000             status = i965_CreateSurfaces(ctx,
4001                                          dest_region->width,
4002                                          dest_region->height,
4003                                          VA_RT_FORMAT_YUV420,
4004                                          1,
4005                                          &out_surface_id);
4006             assert(status == VA_STATUS_SUCCESS);
4007             obj_surface = SURFACE(out_surface_id);
4008             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4009             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4010             src_surface.id = in_surface_id;
4011             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4012             src_surface.flags = I965_SURFACE_FLAG_FRAME;
4013             dst_surface.id = out_surface_id;
4014             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4015             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4016
4017             i965_post_processing_internal(ctx, i965->pp_context,
4018                                           &src_surface,
4019                                           src_rect,
4020                                           &dst_surface,
4021                                           dst_rect,
4022                                           PP_NV12_AVS,
4023                                           NULL);
4024
4025             if (in_surface_id != surface)
4026                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4027
4028             *has_done_scaling = 1;
4029         }
4030
4031         _i965UnlockMutex(&i965->pp_mutex);
4032     }
4033
4034     return out_surface_id;
4035 }
4036
4037 static VAStatus
4038 i965_image_pl3_processing(VADriverContextP ctx,
4039                           const struct i965_surface *src_surface,
4040                           const VARectangle *src_rect,
4041                           struct i965_surface *dst_surface,
4042                           const VARectangle *dst_rect)
4043 {
4044     struct i965_driver_data *i965 = i965_driver_data(ctx);
4045     struct i965_post_processing_context *pp_context = i965->pp_context;
4046     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4047     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4048
4049     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4050         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4051                                                  src_surface,
4052                                                  src_rect,
4053                                                  dst_surface,
4054                                                  dst_rect,
4055                                                  PP_PL3_LOAD_SAVE_N12,
4056                                                  NULL);
4057     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4058                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4059                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4060                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4061         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4062                                                  src_surface,
4063                                                  src_rect,
4064                                                  dst_surface,
4065                                                  dst_rect,
4066                                                  PP_PL3_LOAD_SAVE_PL3,
4067                                                  NULL);
4068     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4069                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4070         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4071                                                  src_surface,
4072                                                  src_rect,
4073                                                  dst_surface,
4074                                                  dst_rect,
4075                                                  PP_PL3_LOAD_SAVE_PA,
4076                                                  NULL);
4077     }
4078     else {
4079         assert(0);
4080     }
4081
4082     intel_batchbuffer_flush(pp_context->batch);
4083
4084     return vaStatus;
4085 }
4086
4087 static VAStatus
4088 i965_image_pl2_processing(VADriverContextP ctx,
4089                           const struct i965_surface *src_surface,
4090                           const VARectangle *src_rect,
4091                           struct i965_surface *dst_surface,
4092                           const VARectangle *dst_rect)
4093 {
4094     struct i965_driver_data *i965 = i965_driver_data(ctx);
4095     struct i965_post_processing_context *pp_context = i965->pp_context;
4096     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4097     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4098
4099     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4100         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4101                                                  src_surface,
4102                                                  src_rect,
4103                                                  dst_surface,
4104                                                  dst_rect,
4105                                                  PP_NV12_LOAD_SAVE_N12,
4106                                                  NULL);
4107     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4108                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4109                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4110                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4111         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4112                                                  src_surface,
4113                                                  src_rect,
4114                                                  dst_surface,
4115                                                  dst_rect,
4116                                                  PP_NV12_LOAD_SAVE_PL3,
4117                                                  NULL);
4118     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4119                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4120         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4121                                                  src_surface,
4122                                                  src_rect,
4123                                                  dst_surface,
4124                                                  dst_rect,
4125                                                  PP_NV12_LOAD_SAVE_PA,
4126                                                      NULL);
4127     }
4128
4129     intel_batchbuffer_flush(pp_context->batch);
4130
4131     return vaStatus;
4132 }
4133
4134 static VAStatus
4135 i965_image_pl1_processing(VADriverContextP ctx,
4136                           const struct i965_surface *src_surface,
4137                           const VARectangle *src_rect,
4138                           struct i965_surface *dst_surface,
4139                           const VARectangle *dst_rect)
4140 {
4141     struct i965_driver_data *i965 = i965_driver_data(ctx);
4142     struct i965_post_processing_context *pp_context = i965->pp_context;
4143     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4144
4145     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4146         i965_post_processing_internal(ctx, i965->pp_context,
4147                                       src_surface,
4148                                       src_rect,
4149                                       dst_surface,
4150                                       dst_rect,
4151                                       PP_PA_LOAD_SAVE_NV12,
4152                                       NULL);
4153     }
4154     else if (fourcc == VA_FOURCC_YV12) {
4155         i965_post_processing_internal(ctx, i965->pp_context,
4156                                       src_surface,
4157                                       src_rect,
4158                                       dst_surface,
4159                                       dst_rect,
4160                                       PP_PA_LOAD_SAVE_PL3,
4161                                       NULL);
4162
4163     }
4164     else {
4165         return VA_STATUS_ERROR_UNKNOWN;
4166     }
4167
4168     intel_batchbuffer_flush(pp_context->batch);
4169
4170     return VA_STATUS_SUCCESS;
4171 }
4172
4173 VAStatus
4174 i965_image_processing(VADriverContextP ctx,
4175                       const struct i965_surface *src_surface,
4176                       const VARectangle *src_rect,
4177                       struct i965_surface *dst_surface,
4178                       const VARectangle *dst_rect)
4179 {
4180     struct i965_driver_data *i965 = i965_driver_data(ctx);
4181     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4182
4183     if (HAS_PP(i965)) {
4184         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4185
4186         _i965LockMutex(&i965->pp_mutex);
4187
4188         switch (fourcc) {
4189         case VA_FOURCC('Y', 'V', '1', '2'):
4190         case VA_FOURCC('I', '4', '2', '0'):
4191         case VA_FOURCC('I', 'M', 'C', '1'):
4192         case VA_FOURCC('I', 'M', 'C', '3'):
4193             status = i965_image_pl3_processing(ctx,
4194                                                src_surface,
4195                                                src_rect,
4196                                                dst_surface,
4197                                                dst_rect);
4198             break;
4199
4200         case  VA_FOURCC('N', 'V', '1', '2'):
4201             status = i965_image_pl2_processing(ctx,
4202                                                src_surface,
4203                                                src_rect,
4204                                                dst_surface,
4205                                                dst_rect);
4206             break;
4207         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4208         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4209             status = i965_image_pl1_processing(ctx,
4210                                                src_surface,
4211                                                src_rect,
4212                                                dst_surface,
4213                                                dst_rect);
4214             break;
4215
4216         default:
4217             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4218             break;
4219         }
4220
4221         _i965UnlockMutex(&i965->pp_mutex);
4222     }
4223
4224     return status;
4225 }
4226
4227 static void
4228 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4229 {
4230     int i;
4231
4232     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4233     pp_context->surface_state_binding_table.bo = NULL;
4234
4235     dri_bo_unreference(pp_context->curbe.bo);
4236     pp_context->curbe.bo = NULL;
4237
4238     dri_bo_unreference(pp_context->sampler_state_table.bo);
4239     pp_context->sampler_state_table.bo = NULL;
4240
4241     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4242     pp_context->sampler_state_table.bo_8x8 = NULL;
4243
4244     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4245     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4246
4247     dri_bo_unreference(pp_context->idrt.bo);
4248     pp_context->idrt.bo = NULL;
4249     pp_context->idrt.num_interface_descriptors = 0;
4250
4251     dri_bo_unreference(pp_context->vfe_state.bo);
4252     pp_context->vfe_state.bo = NULL;
4253
4254     dri_bo_unreference(pp_context->stmm.bo);
4255     pp_context->stmm.bo = NULL;
4256
4257     for (i = 0; i < NUM_PP_MODULES; i++) {
4258         struct pp_module *pp_module = &pp_context->pp_modules[i];
4259
4260         dri_bo_unreference(pp_module->kernel.bo);
4261         pp_module->kernel.bo = NULL;
4262     }
4263
4264     free(pp_context->pp_static_parameter);
4265     free(pp_context->pp_inline_parameter);
4266     pp_context->pp_static_parameter = NULL;
4267     pp_context->pp_inline_parameter = NULL;
4268 }
4269
4270 Bool
4271 i965_post_processing_terminate(VADriverContextP ctx)
4272 {
4273     struct i965_driver_data *i965 = i965_driver_data(ctx);
4274     struct i965_post_processing_context *pp_context = i965->pp_context;
4275
4276     if (pp_context) {
4277         i965_post_processing_context_finalize(pp_context);
4278         free(pp_context);
4279     }
4280
4281     i965->pp_context = NULL;
4282
4283     return True;
4284 }
4285
4286 static void
4287 i965_post_processing_context_init(VADriverContextP ctx,
4288                                   struct i965_post_processing_context *pp_context,
4289                                   struct intel_batchbuffer *batch)
4290 {
4291     struct i965_driver_data *i965 = i965_driver_data(ctx);
4292     int i;
4293
4294     pp_context->urb.size = URB_SIZE((&i965->intel));
4295     pp_context->urb.num_vfe_entries = 32;
4296     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4297     pp_context->urb.num_cs_entries = 1;
4298
4299     if (IS_GEN7(i965->intel.device_id))
4300         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4301     else
4302         pp_context->urb.size_cs_entry = 2;
4303
4304     pp_context->urb.vfe_start = 0;
4305     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4306         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4307     assert(pp_context->urb.cs_start +
4308            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4309
4310     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4311     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4312     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4313
4314     if (IS_GEN7(i965->intel.device_id))
4315         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4316     else if (IS_GEN6(i965->intel.device_id))
4317         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4318     else if (IS_IRONLAKE(i965->intel.device_id))
4319         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4320
4321     for (i = 0; i < NUM_PP_MODULES; i++) {
4322         struct pp_module *pp_module = &pp_context->pp_modules[i];
4323         dri_bo_unreference(pp_module->kernel.bo);
4324         if (pp_module->kernel.bin && pp_module->kernel.size) {
4325             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4326                                                 pp_module->kernel.name,
4327                                                 pp_module->kernel.size,
4328                                                 4096);
4329             assert(pp_module->kernel.bo);
4330             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4331         } else {
4332             pp_module->kernel.bo = NULL;
4333         }
4334     }
4335
4336     /* static & inline parameters */
4337     if (IS_GEN7(i965->intel.device_id)) {
4338         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4339         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4340     } else {
4341         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4342         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4343     }
4344
4345     pp_context->batch = batch;
4346 }
4347
4348 Bool
4349 i965_post_processing_init(VADriverContextP ctx)
4350 {
4351     struct i965_driver_data *i965 = i965_driver_data(ctx);
4352     struct i965_post_processing_context *pp_context = i965->pp_context;
4353
4354     if (HAS_PP(i965)) {
4355         if (pp_context == NULL) {
4356             pp_context = calloc(1, sizeof(*pp_context));
4357             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4358             i965->pp_context = pp_context;
4359         }
4360     }
4361
4362     return True;
4363 }
4364
4365 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4366     PP_NULL,    /* VAProcFilterNone */
4367     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4368     PP_NULL,    /* VAProcFilterDeblocking */
4369     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4370     PP_NULL,    /* VAProcFilterSharpening */
4371     PP_NULL,    /* VAProcFilterColorBalance */
4372     PP_NULL,    /* VAProcFilterColorStandard */
4373     PP_NULL,    /* VAProcFilterFrameRateConversion */
4374 };
4375
4376 static const int proc_frame_to_pp_frame[3] = {
4377     I965_SURFACE_FLAG_FRAME,
4378     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4379     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4380 };
4381
4382 static void
4383 i965_proc_picture(VADriverContextP ctx,
4384                   VAProfile profile,
4385                   union codec_state *codec_state,
4386                   struct hw_context *hw_context)
4387 {
4388     struct i965_driver_data *i965 = i965_driver_data(ctx);
4389     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4390     struct proc_state *proc_state = &codec_state->proc;
4391     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4392     struct object_surface *obj_surface;
4393     struct i965_surface src_surface, dst_surface;
4394     VARectangle src_rect, dst_rect;
4395     VAStatus status;
4396     int i;
4397     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4398     int num_tmp_surfaces = 0;
4399     unsigned int tiling = 0, swizzle = 0;
4400     int in_width, in_height;
4401
4402     assert(pipeline_param->surface != VA_INVALID_ID);
4403     assert(proc_state->current_render_target != VA_INVALID_ID);
4404
4405     obj_surface = SURFACE(pipeline_param->surface);
4406     in_width = obj_surface->orig_width;
4407     in_height = obj_surface->orig_height;
4408     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4409
4410     src_surface.id = pipeline_param->surface;
4411     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4412     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4413
4414     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4415         VASurfaceID out_surface_id = VA_INVALID_ID;
4416
4417         src_surface.id = pipeline_param->surface;
4418         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4419         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4420         src_rect.x = 0;
4421         src_rect.y = 0;
4422         src_rect.width = in_width;
4423         src_rect.height = in_height;
4424
4425         status = i965_CreateSurfaces(ctx,
4426                                      in_width,
4427                                      in_height,
4428                                      VA_RT_FORMAT_YUV420,
4429                                      1,
4430                                      &out_surface_id);
4431         assert(status == VA_STATUS_SUCCESS);
4432         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4433         obj_surface = SURFACE(out_surface_id);
4434         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4435
4436         dst_surface.id = out_surface_id;
4437         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4438         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4439         dst_rect.x = 0;
4440         dst_rect.y = 0;
4441         dst_rect.width = in_width;
4442         dst_rect.height = in_height;
4443
4444         status = i965_image_processing(ctx,
4445                                        &src_surface,
4446                                        &src_rect,
4447                                        &dst_surface,
4448                                        &dst_rect);
4449         assert(status == VA_STATUS_SUCCESS);
4450
4451         src_surface.id = out_surface_id;
4452         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4453         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4454     }
4455
4456     if (pipeline_param->surface_region) {
4457         src_rect.x = pipeline_param->surface_region->x;
4458         src_rect.y = pipeline_param->surface_region->y;
4459         src_rect.width = pipeline_param->surface_region->width;
4460         src_rect.height = pipeline_param->surface_region->height;
4461     } else {
4462         src_rect.x = 0;
4463         src_rect.y = 0;
4464         src_rect.width = in_width;
4465         src_rect.height = in_height;
4466     }
4467
4468     if (pipeline_param->output_region) {
4469         dst_rect.x = pipeline_param->output_region->x;
4470         dst_rect.y = pipeline_param->output_region->y;
4471         dst_rect.width = pipeline_param->output_region->width;
4472         dst_rect.height = pipeline_param->output_region->height;
4473     } else {
4474         dst_rect.x = 0;
4475         dst_rect.y = 0;
4476         dst_rect.width = in_width;
4477         dst_rect.height = in_height;
4478     }
4479
4480     obj_surface = SURFACE(proc_state->current_render_target);
4481     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4482     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4483
4484     for (i = 0; i < pipeline_param->num_filters; i++) {
4485         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4486         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4487         VAProcFilterType filter_type = filter_param->type;
4488         VASurfaceID out_surface_id = VA_INVALID_ID;
4489         int kernel_index = procfilter_to_pp_flag[filter_type];
4490
4491         if (kernel_index != PP_NULL &&
4492             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4493             status = i965_CreateSurfaces(ctx,
4494                                          in_width,
4495                                          in_height,
4496                                          VA_RT_FORMAT_YUV420,
4497                                          1,
4498                                          &out_surface_id);
4499             assert(status == VA_STATUS_SUCCESS);
4500             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4501             obj_surface = SURFACE(out_surface_id);
4502             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4503             dst_surface.id = out_surface_id;
4504             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4505             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4506                                                    &src_surface,
4507                                                    &src_rect,
4508                                                    &dst_surface,
4509                                                    &src_rect,
4510                                                    kernel_index,
4511                                                    filter_param);
4512
4513             if (status == VA_STATUS_SUCCESS) {
4514                 src_surface.id = dst_surface.id;
4515                 src_surface.type = dst_surface.type;
4516                 src_surface.flags = dst_surface.flags;
4517             }
4518         }
4519     }
4520
4521     dst_surface.id = proc_state->current_render_target;
4522     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4523
4524     if (src_rect.width == dst_rect.width &&
4525         src_rect.height == dst_rect.height) {
4526         i965_post_processing_internal(ctx, &proc_context->pp_context,
4527                                       &src_surface,
4528                                       &src_rect,
4529                                       &dst_surface,
4530                                       &dst_rect,
4531                                       PP_NV12_LOAD_SAVE_N12,
4532                                       NULL);
4533     } else {
4534
4535         i965_post_processing_internal(ctx, &proc_context->pp_context,
4536                                       &src_surface,
4537                                       &src_rect,
4538                                       &dst_surface,
4539                                       &dst_rect,
4540                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4541                                       PP_NV12_AVS : PP_NV12_SCALING,
4542                                       NULL);
4543     }
4544
4545     if (num_tmp_surfaces)
4546         i965_DestroySurfaces(ctx,
4547                              tmp_surfaces,
4548                              num_tmp_surfaces);
4549
4550     intel_batchbuffer_flush(hw_context->batch);
4551 }
4552
4553 static void
4554 i965_proc_context_destroy(void *hw_context)
4555 {
4556     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4557
4558     i965_post_processing_context_finalize(&proc_context->pp_context);
4559     intel_batchbuffer_free(proc_context->base.batch);
4560     free(proc_context);
4561 }
4562
4563 struct hw_context *
4564 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4565 {
4566     struct intel_driver_data *intel = intel_driver_data(ctx);
4567     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4568
4569     proc_context->base.destroy = i965_proc_context_destroy;
4570     proc_context->base.run = i965_proc_picture;
4571     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4572     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4573
4574     return (struct hw_context *)proc_context;
4575 }