2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_post_processing.h"
40 #include "i965_render.h"
42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \
43 IS_GEN6((ctx)->intel.device_id) || \
44 IS_GEN7((ctx)->intel.device_id))
46 #define SURFACE_STATE_PADDED_SIZE_0_I965 ALIGN(sizeof(struct i965_surface_state), 32)
47 #define SURFACE_STATE_PADDED_SIZE_1_I965 ALIGN(sizeof(struct i965_surface_state2), 32)
48 #define SURFACE_STATE_PADDED_SIZE_I965 MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
52 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
54 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
55 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
56 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
58 static const uint32_t pp_null_gen5[][4] = {
59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
82 static const uint32_t pp_nv12_avs_gen5[][4] = {
83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
90 static const uint32_t pp_nv12_dn_gen5[][4] = {
91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
111 const struct i965_surface *src_surface,
112 const VARectangle *src_rect,
113 struct i965_surface *dst_surface,
114 const VARectangle *dst_rect,
116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
117 const struct i965_surface *src_surface,
118 const VARectangle *src_rect,
119 struct i965_surface *dst_surface,
120 const VARectangle *dst_rect,
122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
123 const struct i965_surface *src_surface,
124 const VARectangle *src_rect,
125 struct i965_surface *dst_surface,
126 const VARectangle *dst_rect,
128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
129 const struct i965_surface *src_surface,
130 const VARectangle *src_rect,
131 struct i965_surface *dst_surface,
132 const VARectangle *dst_rect,
134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
135 const struct i965_surface *src_surface,
136 const VARectangle *src_rect,
137 struct i965_surface *dst_surface,
138 const VARectangle *dst_rect,
140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
141 const struct i965_surface *src_surface,
142 const VARectangle *src_rect,
143 struct i965_surface *dst_surface,
144 const VARectangle *dst_rect,
146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
147 const struct i965_surface *src_surface,
148 const VARectangle *src_rect,
149 struct i965_surface *dst_surface,
150 const VARectangle *dst_rect,
153 static struct pp_module pp_modules_gen5[] = {
156 "NULL module (for testing)",
159 sizeof(pp_null_gen5),
169 PP_NV12_LOAD_SAVE_N12,
170 pp_nv12_load_save_nv12_gen5,
171 sizeof(pp_nv12_load_save_nv12_gen5),
175 pp_plx_load_save_plx_initialize,
181 PP_NV12_LOAD_SAVE_PL3,
182 pp_nv12_load_save_pl3_gen5,
183 sizeof(pp_nv12_load_save_pl3_gen5),
187 pp_plx_load_save_plx_initialize,
193 PP_PL3_LOAD_SAVE_N12,
194 pp_pl3_load_save_nv12_gen5,
195 sizeof(pp_pl3_load_save_nv12_gen5),
199 pp_plx_load_save_plx_initialize,
205 PP_PL3_LOAD_SAVE_N12,
206 pp_pl3_load_save_pl3_gen5,
207 sizeof(pp_pl3_load_save_pl3_gen5),
211 pp_plx_load_save_plx_initialize
216 "NV12 Scaling module",
218 pp_nv12_scaling_gen5,
219 sizeof(pp_nv12_scaling_gen5),
223 pp_nv12_scaling_initialize,
231 sizeof(pp_nv12_avs_gen5),
235 pp_nv12_avs_initialize_nlas,
243 sizeof(pp_nv12_dndi_gen5),
247 pp_nv12_dndi_initialize,
255 sizeof(pp_nv12_dn_gen5),
259 pp_nv12_dn_initialize,
265 PP_NV12_LOAD_SAVE_PA,
266 pp_nv12_load_save_pa_gen5,
267 sizeof(pp_nv12_load_save_pa_gen5),
271 pp_plx_load_save_plx_initialize,
278 pp_pl3_load_save_pa_gen5,
279 sizeof(pp_pl3_load_save_pa_gen5),
283 pp_plx_load_save_plx_initialize,
289 PP_PA_LOAD_SAVE_NV12,
290 pp_pa_load_save_nv12_gen5,
291 sizeof(pp_pa_load_save_nv12_gen5),
295 pp_plx_load_save_plx_initialize,
302 pp_pa_load_save_pl3_gen5,
303 sizeof(pp_pa_load_save_pl3_gen5),
307 pp_plx_load_save_plx_initialize,
312 static const uint32_t pp_null_gen6[][4] = {
313 #include "shaders/post_processing/gen5_6/null.g6b"
316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
336 static const uint32_t pp_nv12_avs_gen6[][4] = {
337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
344 static const uint32_t pp_nv12_dn_gen6[][4] = {
345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
364 static struct pp_module pp_modules_gen6[] = {
367 "NULL module (for testing)",
370 sizeof(pp_null_gen6),
380 PP_NV12_LOAD_SAVE_N12,
381 pp_nv12_load_save_nv12_gen6,
382 sizeof(pp_nv12_load_save_nv12_gen6),
386 pp_plx_load_save_plx_initialize,
392 PP_NV12_LOAD_SAVE_PL3,
393 pp_nv12_load_save_pl3_gen6,
394 sizeof(pp_nv12_load_save_pl3_gen6),
398 pp_plx_load_save_plx_initialize,
404 PP_PL3_LOAD_SAVE_N12,
405 pp_pl3_load_save_nv12_gen6,
406 sizeof(pp_pl3_load_save_nv12_gen6),
410 pp_plx_load_save_plx_initialize,
416 PP_PL3_LOAD_SAVE_N12,
417 pp_pl3_load_save_pl3_gen6,
418 sizeof(pp_pl3_load_save_pl3_gen6),
422 pp_plx_load_save_plx_initialize,
427 "NV12 Scaling module",
429 pp_nv12_scaling_gen6,
430 sizeof(pp_nv12_scaling_gen6),
434 gen6_nv12_scaling_initialize,
442 sizeof(pp_nv12_avs_gen6),
446 pp_nv12_avs_initialize_nlas,
454 sizeof(pp_nv12_dndi_gen6),
458 pp_nv12_dndi_initialize,
466 sizeof(pp_nv12_dn_gen6),
470 pp_nv12_dn_initialize,
475 PP_NV12_LOAD_SAVE_PA,
476 pp_nv12_load_save_pa_gen6,
477 sizeof(pp_nv12_load_save_pa_gen6),
481 pp_plx_load_save_plx_initialize,
488 pp_pl3_load_save_pa_gen6,
489 sizeof(pp_pl3_load_save_pa_gen6),
493 pp_plx_load_save_plx_initialize,
499 PP_PA_LOAD_SAVE_NV12,
500 pp_pa_load_save_nv12_gen6,
501 sizeof(pp_pa_load_save_nv12_gen6),
505 pp_plx_load_save_plx_initialize,
512 pp_pa_load_save_pl3_gen6,
513 sizeof(pp_pa_load_save_pl3_gen6),
517 pp_plx_load_save_plx_initialize,
522 static const uint32_t pp_null_gen7[][4] = {
525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
542 #include "shaders/post_processing/gen7/avs.g7b"
545 static const uint32_t pp_nv12_avs_gen7[][4] = {
546 #include "shaders/post_processing/gen7/avs.g7b"
549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
550 // #include "shaders/post_processing/gen7/dndi.g7b"
553 static const uint32_t pp_nv12_dn_gen7[][4] = {
555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
557 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
559 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
561 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
564 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
565 const struct i965_surface *src_surface,
566 const VARectangle *src_rect,
567 struct i965_surface *dst_surface,
568 const VARectangle *dst_rect,
570 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
571 const struct i965_surface *src_surface,
572 const VARectangle *src_rect,
573 struct i965_surface *dst_surface,
574 const VARectangle *dst_rect,
576 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
577 const struct i965_surface *src_surface,
578 const VARectangle *src_rect,
579 struct i965_surface *dst_surface,
580 const VARectangle *dst_rect,
583 static struct pp_module pp_modules_gen7[] = {
586 "NULL module (for testing)",
589 sizeof(pp_null_gen7),
599 PP_NV12_LOAD_SAVE_N12,
600 pp_nv12_load_save_nv12_gen7,
601 sizeof(pp_nv12_load_save_nv12_gen7),
605 gen7_pp_plx_avs_initialize,
611 PP_NV12_LOAD_SAVE_PL3,
612 pp_nv12_load_save_pl3_gen7,
613 sizeof(pp_nv12_load_save_pl3_gen7),
617 gen7_pp_plx_avs_initialize,
623 PP_PL3_LOAD_SAVE_N12,
624 pp_pl3_load_save_nv12_gen7,
625 sizeof(pp_pl3_load_save_nv12_gen7),
629 gen7_pp_plx_avs_initialize,
635 PP_PL3_LOAD_SAVE_N12,
636 pp_pl3_load_save_pl3_gen7,
637 sizeof(pp_pl3_load_save_pl3_gen7),
641 gen7_pp_plx_avs_initialize,
646 "NV12 Scaling module",
648 pp_nv12_scaling_gen7,
649 sizeof(pp_nv12_scaling_gen7),
653 gen7_pp_plx_avs_initialize,
661 sizeof(pp_nv12_avs_gen7),
665 gen7_pp_plx_avs_initialize,
673 sizeof(pp_nv12_dndi_gen7),
677 gen7_pp_nv12_dndi_initialize,
685 sizeof(pp_nv12_dn_gen7),
689 gen7_pp_nv12_dn_initialize,
694 PP_NV12_LOAD_SAVE_PA,
695 pp_nv12_load_save_pa_gen7,
696 sizeof(pp_nv12_load_save_pa_gen7),
700 pp_plx_load_save_plx_initialize,
707 pp_pl3_load_save_pa_gen7,
708 sizeof(pp_pl3_load_save_pa_gen7),
712 pp_plx_load_save_plx_initialize,
718 PP_PA_LOAD_SAVE_NV12,
719 pp_pa_load_save_nv12_gen7,
720 sizeof(pp_pa_load_save_nv12_gen7),
724 pp_plx_load_save_plx_initialize,
731 pp_pa_load_save_pl3_gen7,
732 sizeof(pp_pa_load_save_pl3_gen7),
736 pp_plx_load_save_plx_initialize,
742 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
744 struct i965_driver_data *i965 = i965_driver_data(ctx);
747 if (surface->type == I965_SURFACE_TYPE_IMAGE) {
748 struct object_image *obj_image = IMAGE(surface->id);
749 fourcc = obj_image->image.format.fourcc;
751 struct object_surface *obj_surface = SURFACE(surface->id);
752 fourcc = obj_surface->fourcc;
759 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
762 case I915_TILING_NONE:
763 ss->ss3.tiled_surface = 0;
764 ss->ss3.tile_walk = 0;
767 ss->ss3.tiled_surface = 1;
768 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
771 ss->ss3.tiled_surface = 1;
772 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
778 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
781 case I915_TILING_NONE:
782 ss->ss2.tiled_surface = 0;
783 ss->ss2.tile_walk = 0;
786 ss->ss2.tiled_surface = 1;
787 ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
790 ss->ss2.tiled_surface = 1;
791 ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
797 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
800 case I915_TILING_NONE:
801 ss->ss0.tiled_surface = 0;
802 ss->ss0.tile_walk = 0;
805 ss->ss0.tiled_surface = 1;
806 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
809 ss->ss0.tiled_surface = 1;
810 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
816 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
819 case I915_TILING_NONE:
820 ss->ss2.tiled_surface = 0;
821 ss->ss2.tile_walk = 0;
824 ss->ss2.tiled_surface = 1;
825 ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
828 ss->ss2.tiled_surface = 1;
829 ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
835 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
837 struct i965_interface_descriptor *desc;
839 int pp_index = pp_context->current_pp;
841 bo = pp_context->idrt.bo;
845 memset(desc, 0, sizeof(*desc));
846 desc->desc0.grf_reg_blocks = 10;
847 desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
848 desc->desc1.const_urb_entry_read_offset = 0;
849 desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
850 desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
851 desc->desc2.sampler_count = 0;
852 desc->desc3.binding_table_entry_count = 0;
853 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
855 dri_bo_emit_reloc(bo,
856 I915_GEM_DOMAIN_INSTRUCTION, 0,
857 desc->desc0.grf_reg_blocks,
858 offsetof(struct i965_interface_descriptor, desc0),
859 pp_context->pp_modules[pp_index].kernel.bo);
861 dri_bo_emit_reloc(bo,
862 I915_GEM_DOMAIN_INSTRUCTION, 0,
863 desc->desc2.sampler_count << 2,
864 offsetof(struct i965_interface_descriptor, desc2),
865 pp_context->sampler_state_table.bo);
868 pp_context->idrt.num_interface_descriptors++;
872 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
874 struct i965_vfe_state *vfe_state;
877 bo = pp_context->vfe_state.bo;
880 vfe_state = bo->virtual;
881 memset(vfe_state, 0, sizeof(*vfe_state));
882 vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
883 vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
884 vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
885 vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
886 vfe_state->vfe1.children_present = 0;
887 vfe_state->vfe2.interface_descriptor_base =
888 pp_context->idrt.bo->offset >> 4; /* reloc */
889 dri_bo_emit_reloc(bo,
890 I915_GEM_DOMAIN_INSTRUCTION, 0,
892 offsetof(struct i965_vfe_state, vfe2),
893 pp_context->idrt.bo);
898 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
900 unsigned char *constant_buffer;
901 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
903 assert(sizeof(*pp_static_parameter) == 128);
904 dri_bo_map(pp_context->curbe.bo, 1);
905 assert(pp_context->curbe.bo->virtual);
906 constant_buffer = pp_context->curbe.bo->virtual;
907 memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
908 dri_bo_unmap(pp_context->curbe.bo);
912 ironlake_pp_states_setup(VADriverContextP ctx,
913 struct i965_post_processing_context *pp_context)
915 ironlake_pp_interface_descriptor_table(pp_context);
916 ironlake_pp_vfe_state(pp_context);
917 ironlake_pp_upload_constants(pp_context);
921 ironlake_pp_pipeline_select(VADriverContextP ctx,
922 struct i965_post_processing_context *pp_context)
924 struct intel_batchbuffer *batch = pp_context->batch;
926 BEGIN_BATCH(batch, 1);
927 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
928 ADVANCE_BATCH(batch);
932 ironlake_pp_urb_layout(VADriverContextP ctx,
933 struct i965_post_processing_context *pp_context)
935 struct intel_batchbuffer *batch = pp_context->batch;
936 unsigned int vfe_fence, cs_fence;
938 vfe_fence = pp_context->urb.cs_start;
939 cs_fence = pp_context->urb.size;
941 BEGIN_BATCH(batch, 3);
942 OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
945 (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */
946 (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */
947 ADVANCE_BATCH(batch);
951 ironlake_pp_state_base_address(VADriverContextP ctx,
952 struct i965_post_processing_context *pp_context)
954 struct intel_batchbuffer *batch = pp_context->batch;
956 BEGIN_BATCH(batch, 8);
957 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
958 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
959 OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
960 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
961 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
962 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
963 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
964 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
965 ADVANCE_BATCH(batch);
969 ironlake_pp_state_pointers(VADriverContextP ctx,
970 struct i965_post_processing_context *pp_context)
972 struct intel_batchbuffer *batch = pp_context->batch;
974 BEGIN_BATCH(batch, 3);
975 OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
977 OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
978 ADVANCE_BATCH(batch);
982 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
983 struct i965_post_processing_context *pp_context)
985 struct intel_batchbuffer *batch = pp_context->batch;
987 BEGIN_BATCH(batch, 2);
988 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
990 ((pp_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */
991 (pp_context->urb.num_cs_entries << 0)); /* Number of URB Entries */
992 ADVANCE_BATCH(batch);
996 ironlake_pp_constant_buffer(VADriverContextP ctx,
997 struct i965_post_processing_context *pp_context)
999 struct intel_batchbuffer *batch = pp_context->batch;
1001 BEGIN_BATCH(batch, 2);
1002 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1003 OUT_RELOC(batch, pp_context->curbe.bo,
1004 I915_GEM_DOMAIN_INSTRUCTION, 0,
1005 pp_context->urb.size_cs_entry - 1);
1006 ADVANCE_BATCH(batch);
1010 ironlake_pp_object_walker(VADriverContextP ctx,
1011 struct i965_post_processing_context *pp_context)
1013 struct intel_batchbuffer *batch = pp_context->batch;
1014 int x, x_steps, y, y_steps;
1015 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1017 x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1018 y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1020 for (y = 0; y < y_steps; y++) {
1021 for (x = 0; x < x_steps; x++) {
1022 if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1023 BEGIN_BATCH(batch, 20);
1024 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1025 OUT_BATCH(batch, 0);
1026 OUT_BATCH(batch, 0); /* no indirect data */
1027 OUT_BATCH(batch, 0);
1029 /* inline data grf 5-6 */
1030 assert(sizeof(*pp_inline_parameter) == 64);
1031 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1033 ADVANCE_BATCH(batch);
1040 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1041 struct i965_post_processing_context *pp_context)
1043 struct intel_batchbuffer *batch = pp_context->batch;
1045 intel_batchbuffer_start_atomic(batch, 0x1000);
1046 intel_batchbuffer_emit_mi_flush(batch);
1047 ironlake_pp_pipeline_select(ctx, pp_context);
1048 ironlake_pp_state_base_address(ctx, pp_context);
1049 ironlake_pp_state_pointers(ctx, pp_context);
1050 ironlake_pp_urb_layout(ctx, pp_context);
1051 ironlake_pp_cs_urb_layout(ctx, pp_context);
1052 ironlake_pp_constant_buffer(ctx, pp_context);
1053 ironlake_pp_object_walker(ctx, pp_context);
1054 intel_batchbuffer_end_atomic(batch);
1057 // update u/v offset when the surface format are packed yuv
1058 static void i965_update_src_surface_uv_offset(
1059 VADriverContextP ctx,
1060 struct i965_post_processing_context *pp_context,
1061 const struct i965_surface *surface)
1063 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1064 int fourcc = pp_get_surface_fourcc(ctx, surface);
1066 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1067 pp_static_parameter->grf1.source_packed_u_offset = 1;
1068 pp_static_parameter->grf1.source_packed_v_offset = 3;
1070 else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1071 pp_static_parameter->grf1.source_packed_y_offset = 1;
1072 pp_static_parameter->grf1.source_packed_v_offset = 2;
1077 static void i965_update_dst_surface_uv_offset(
1078 VADriverContextP ctx,
1079 struct i965_post_processing_context *pp_context,
1080 const struct i965_surface *surface)
1082 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1083 int fourcc = pp_get_surface_fourcc(ctx, surface);
1085 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1086 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1087 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1089 else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1090 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1091 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1097 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1098 dri_bo *surf_bo, unsigned long surf_bo_offset,
1099 int width, int height, int pitch, int format,
1100 int index, int is_target)
1102 struct i965_surface_state *ss;
1104 unsigned int tiling;
1105 unsigned int swizzle;
1107 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1108 ss_bo = pp_context->surface_state_binding_table.bo;
1111 dri_bo_map(ss_bo, True);
1112 assert(ss_bo->virtual);
1113 ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1114 memset(ss, 0, sizeof(*ss));
1115 ss->ss0.surface_type = I965_SURFACE_2D;
1116 ss->ss0.surface_format = format;
1117 ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1118 ss->ss2.width = width - 1;
1119 ss->ss2.height = height - 1;
1120 ss->ss3.pitch = pitch - 1;
1121 pp_set_surface_tiling(ss, tiling);
1122 dri_bo_emit_reloc(ss_bo,
1123 I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1125 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1127 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1128 dri_bo_unmap(ss_bo);
1132 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1133 dri_bo *surf_bo, unsigned long surf_bo_offset,
1134 int width, int height, int wpitch,
1135 int xoffset, int yoffset,
1136 int format, int interleave_chroma,
1139 struct i965_surface_state2 *ss2;
1141 unsigned int tiling;
1142 unsigned int swizzle;
1144 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1145 ss2_bo = pp_context->surface_state_binding_table.bo;
1148 dri_bo_map(ss2_bo, True);
1149 assert(ss2_bo->virtual);
1150 ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1151 memset(ss2, 0, sizeof(*ss2));
1152 ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1153 ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1154 ss2->ss1.width = width - 1;
1155 ss2->ss1.height = height - 1;
1156 ss2->ss2.pitch = wpitch - 1;
1157 ss2->ss2.interleave_chroma = interleave_chroma;
1158 ss2->ss2.surface_format = format;
1159 ss2->ss3.x_offset_for_cb = xoffset;
1160 ss2->ss3.y_offset_for_cb = yoffset;
1161 pp_set_surface2_tiling(ss2, tiling);
1162 dri_bo_emit_reloc(ss2_bo,
1163 I915_GEM_DOMAIN_RENDER, 0,
1165 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1167 ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1168 dri_bo_unmap(ss2_bo);
1172 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1173 dri_bo *surf_bo, unsigned long surf_bo_offset,
1174 int width, int height, int pitch, int format,
1175 int index, int is_target)
1177 struct gen7_surface_state *ss;
1179 unsigned int tiling;
1180 unsigned int swizzle;
1182 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1183 ss_bo = pp_context->surface_state_binding_table.bo;
1186 dri_bo_map(ss_bo, True);
1187 assert(ss_bo->virtual);
1188 ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1189 memset(ss, 0, sizeof(*ss));
1190 ss->ss0.surface_type = I965_SURFACE_2D;
1191 ss->ss0.surface_format = format;
1192 ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1193 ss->ss2.width = width - 1;
1194 ss->ss2.height = height - 1;
1195 ss->ss3.pitch = pitch - 1;
1196 gen7_pp_set_surface_tiling(ss, tiling);
1197 dri_bo_emit_reloc(ss_bo,
1198 I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1200 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1202 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1203 dri_bo_unmap(ss_bo);
1207 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1208 dri_bo *surf_bo, unsigned long surf_bo_offset,
1209 int width, int height, int wpitch,
1210 int xoffset, int yoffset,
1211 int format, int interleave_chroma,
1214 struct gen7_surface_state2 *ss2;
1216 unsigned int tiling;
1217 unsigned int swizzle;
1219 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1220 ss2_bo = pp_context->surface_state_binding_table.bo;
1223 dri_bo_map(ss2_bo, True);
1224 assert(ss2_bo->virtual);
1225 ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1226 memset(ss2, 0, sizeof(*ss2));
1227 ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1228 ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1229 ss2->ss1.width = width - 1;
1230 ss2->ss1.height = height - 1;
1231 ss2->ss2.pitch = wpitch - 1;
1232 ss2->ss2.interleave_chroma = interleave_chroma;
1233 ss2->ss2.surface_format = format;
1234 ss2->ss3.x_offset_for_cb = xoffset;
1235 ss2->ss3.y_offset_for_cb = yoffset;
1236 gen7_pp_set_surface2_tiling(ss2, tiling);
1237 dri_bo_emit_reloc(ss2_bo,
1238 I915_GEM_DOMAIN_RENDER, 0,
1240 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1242 ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1243 dri_bo_unmap(ss2_bo);
1247 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1248 const struct i965_surface *surface,
1249 int base_index, int is_target,
1250 int *width, int *height, int *pitch, int *offset)
1252 struct i965_driver_data *i965 = i965_driver_data(ctx);
1253 struct object_surface *obj_surface;
1254 struct object_image *obj_image;
1256 int fourcc = pp_get_surface_fourcc(ctx, surface);
1258 const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1259 const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1261 int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1262 int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1264 if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1265 obj_surface = SURFACE(surface->id);
1266 bo = obj_surface->bo;
1267 width[0] = obj_surface->orig_width;
1268 height[0] = obj_surface->orig_height;
1269 pitch[0] = obj_surface->width;
1273 width[0] = obj_surface->orig_width * 2;
1274 pitch[0] = obj_surface->width * 2;
1276 else if (interleaved_uv) {
1277 width[1] = obj_surface->orig_width;
1278 height[1] = obj_surface->orig_height / 2;
1279 pitch[1] = obj_surface->width;
1280 offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1282 width[1] = obj_surface->orig_width / 2;
1283 height[1] = obj_surface->orig_height / 2;
1284 pitch[1] = obj_surface->width / 2;
1285 offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1286 width[2] = obj_surface->orig_width / 2;
1287 height[2] = obj_surface->orig_height / 2;
1288 pitch[2] = obj_surface->width / 2;
1289 offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1292 obj_image = IMAGE(surface->id);
1294 width[0] = obj_image->image.width;
1295 height[0] = obj_image->image.height;
1296 pitch[0] = obj_image->image.pitches[0];
1297 offset[0] = obj_image->image.offsets[0];
1300 width[0] = obj_image->image.width * 2;
1302 else if (interleaved_uv) {
1303 width[1] = obj_image->image.width;
1304 height[1] = obj_image->image.height / 2;
1305 pitch[1] = obj_image->image.pitches[1];
1306 offset[1] = obj_image->image.offsets[1];
1308 width[1] = obj_image->image.width / 2;
1309 height[1] = obj_image->image.height / 2;
1310 pitch[1] = obj_image->image.pitches[1];
1311 offset[1] = obj_image->image.offsets[1];
1312 width[2] = obj_image->image.width / 2;
1313 height[2] = obj_image->image.height / 2;
1314 pitch[2] = obj_image->image.pitches[2];
1315 offset[2] = obj_image->image.offsets[2];
1320 i965_pp_set_surface_state(ctx, pp_context,
1322 width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1323 base_index, is_target);
1326 if (interleaved_uv) {
1327 i965_pp_set_surface_state(ctx, pp_context,
1329 width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1330 base_index + 1, is_target);
1333 i965_pp_set_surface_state(ctx, pp_context,
1335 width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1336 base_index + 1, is_target);
1339 i965_pp_set_surface_state(ctx, pp_context,
1341 width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1342 base_index + 2, is_target);
1349 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1350 const struct i965_surface *surface,
1351 int base_index, int is_target,
1352 int *width, int *height, int *pitch, int *offset)
1354 struct i965_driver_data *i965 = i965_driver_data(ctx);
1355 struct object_surface *obj_surface;
1356 struct object_image *obj_image;
1358 int fourcc = pp_get_surface_fourcc(ctx, surface);
1359 const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1360 fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1361 const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1362 fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1363 int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1365 if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1366 obj_surface = SURFACE(surface->id);
1367 bo = obj_surface->bo;
1368 width[0] = obj_surface->orig_width;
1369 height[0] = obj_surface->orig_height;
1370 pitch[0] = obj_surface->width;
1373 width[1] = obj_surface->cb_cr_width;
1374 height[1] = obj_surface->cb_cr_height;
1375 pitch[1] = obj_surface->cb_cr_pitch;
1376 offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1378 width[2] = obj_surface->cb_cr_width;
1379 height[2] = obj_surface->cb_cr_height;
1380 pitch[2] = obj_surface->cb_cr_pitch;
1381 offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1383 obj_image = IMAGE(surface->id);
1385 width[0] = obj_image->image.width;
1386 height[0] = obj_image->image.height;
1387 pitch[0] = obj_image->image.pitches[0];
1388 offset[0] = obj_image->image.offsets[0];
1390 if (interleaved_uv) {
1391 width[1] = obj_image->image.width;
1392 height[1] = obj_image->image.height / 2;
1393 pitch[1] = obj_image->image.pitches[1];
1394 offset[1] = obj_image->image.offsets[1];
1396 width[1] = obj_image->image.width / 2;
1397 height[1] = obj_image->image.height / 2;
1398 pitch[1] = obj_image->image.pitches[U];
1399 offset[1] = obj_image->image.offsets[U];
1400 width[2] = obj_image->image.width / 2;
1401 height[2] = obj_image->image.height / 2;
1402 pitch[2] = obj_image->image.pitches[V];
1403 offset[2] = obj_image->image.offsets[V];
1408 gen7_pp_set_surface_state(ctx, pp_context,
1410 width[0] / 4, height[0], pitch[0],
1411 I965_SURFACEFORMAT_R8_SINT,
1414 if (interleaved_uv) {
1415 gen7_pp_set_surface_state(ctx, pp_context,
1417 width[1] / 2, height[1], pitch[1],
1418 I965_SURFACEFORMAT_R8G8_SINT,
1421 gen7_pp_set_surface_state(ctx, pp_context,
1423 width[1] / 4, height[1], pitch[1],
1424 I965_SURFACEFORMAT_R8_SINT,
1426 gen7_pp_set_surface_state(ctx, pp_context,
1428 width[2] / 4, height[2], pitch[2],
1429 I965_SURFACEFORMAT_R8_SINT,
1433 gen7_pp_set_surface2_state(ctx, pp_context,
1435 width[0], height[0], pitch[0],
1437 SURFACE_FORMAT_Y8_UNORM, 0,
1440 if (interleaved_uv) {
1441 gen7_pp_set_surface2_state(ctx, pp_context,
1443 width[1], height[1], pitch[1],
1445 SURFACE_FORMAT_R8B8_UNORM, 0,
1448 gen7_pp_set_surface2_state(ctx, pp_context,
1450 width[1], height[1], pitch[1],
1452 SURFACE_FORMAT_R8_UNORM, 0,
1454 gen7_pp_set_surface2_state(ctx, pp_context,
1456 width[2], height[2], pitch[2],
1458 SURFACE_FORMAT_R8_UNORM, 0,
1465 pp_null_x_steps(void *private_context)
1471 pp_null_y_steps(void *private_context)
1477 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1483 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1484 const struct i965_surface *src_surface,
1485 const VARectangle *src_rect,
1486 struct i965_surface *dst_surface,
1487 const VARectangle *dst_rect,
1490 /* private function & data */
1491 pp_context->pp_x_steps = pp_null_x_steps;
1492 pp_context->pp_y_steps = pp_null_y_steps;
1493 pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1495 dst_surface->flags = src_surface->flags;
1497 return VA_STATUS_SUCCESS;
1501 pp_load_save_x_steps(void *private_context)
1507 pp_load_save_y_steps(void *private_context)
1509 struct pp_load_save_context *pp_load_save_context = private_context;
1511 return pp_load_save_context->dest_h / 8;
1515 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1517 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1519 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1520 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1521 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1522 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1528 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1529 const struct i965_surface *src_surface,
1530 const VARectangle *src_rect,
1531 struct i965_surface *dst_surface,
1532 const VARectangle *dst_rect,
1535 struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1536 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1537 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1538 int width[3], height[3], pitch[3], offset[3];
1541 /* source surface */
1542 pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1543 width, height, pitch, offset);
1545 /* destination surface */
1546 pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1547 width, height, pitch, offset);
1549 /* private function & data */
1550 pp_context->pp_x_steps = pp_load_save_x_steps;
1551 pp_context->pp_y_steps = pp_load_save_y_steps;
1552 pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1553 pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1554 pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1556 pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16; /* 1 x N */
1557 pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1559 pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1560 pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1562 // update u/v offset for packed yuv
1563 i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
1564 i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
1566 dst_surface->flags = src_surface->flags;
1568 return VA_STATUS_SUCCESS;
1572 pp_scaling_x_steps(void *private_context)
1578 pp_scaling_y_steps(void *private_context)
1580 struct pp_scaling_context *pp_scaling_context = private_context;
1582 return pp_scaling_context->dest_h / 8;
1586 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1588 struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1589 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1590 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1591 float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1592 float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1594 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1595 pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1596 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1597 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1603 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1604 const struct i965_surface *src_surface,
1605 const VARectangle *src_rect,
1606 struct i965_surface *dst_surface,
1607 const VARectangle *dst_rect,
1610 struct i965_driver_data *i965 = i965_driver_data(ctx);
1611 struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1612 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1613 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1614 struct object_surface *obj_surface;
1615 struct i965_sampler_state *sampler_state;
1616 int in_w, in_h, in_wpitch, in_hpitch;
1617 int out_w, out_h, out_wpitch, out_hpitch;
1619 /* source surface */
1620 obj_surface = SURFACE(src_surface->id);
1621 in_w = obj_surface->orig_width;
1622 in_h = obj_surface->orig_height;
1623 in_wpitch = obj_surface->width;
1624 in_hpitch = obj_surface->height;
1626 /* source Y surface index 1 */
1627 i965_pp_set_surface_state(ctx, pp_context,
1629 in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1632 /* source UV surface index 2 */
1633 i965_pp_set_surface_state(ctx, pp_context,
1634 obj_surface->bo, in_wpitch * in_hpitch,
1635 in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1638 /* destination surface */
1639 obj_surface = SURFACE(dst_surface->id);
1640 out_w = obj_surface->orig_width;
1641 out_h = obj_surface->orig_height;
1642 out_wpitch = obj_surface->width;
1643 out_hpitch = obj_surface->height;
1645 /* destination Y surface index 7 */
1646 i965_pp_set_surface_state(ctx, pp_context,
1648 out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1651 /* destination UV surface index 8 */
1652 i965_pp_set_surface_state(ctx, pp_context,
1653 obj_surface->bo, out_wpitch * out_hpitch,
1654 out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1658 dri_bo_map(pp_context->sampler_state_table.bo, True);
1659 assert(pp_context->sampler_state_table.bo->virtual);
1660 sampler_state = pp_context->sampler_state_table.bo->virtual;
1662 /* SIMD16 Y index 1 */
1663 sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1664 sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1665 sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1666 sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1667 sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1669 /* SIMD16 UV index 2 */
1670 sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1671 sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1672 sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1673 sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1674 sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1676 dri_bo_unmap(pp_context->sampler_state_table.bo);
1678 /* private function & data */
1679 pp_context->pp_x_steps = pp_scaling_x_steps;
1680 pp_context->pp_y_steps = pp_scaling_y_steps;
1681 pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1683 pp_scaling_context->dest_x = dst_rect->x;
1684 pp_scaling_context->dest_y = dst_rect->y;
1685 pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1686 pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1687 pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1688 pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1690 pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1692 pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1693 pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16; /* 1 x N */
1694 pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1695 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1696 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1698 dst_surface->flags = src_surface->flags;
1700 return VA_STATUS_SUCCESS;
1704 pp_avs_x_steps(void *private_context)
1706 struct pp_avs_context *pp_avs_context = private_context;
1708 return pp_avs_context->dest_w / 16;
1712 pp_avs_y_steps(void *private_context)
1718 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1720 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1721 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1722 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1723 float src_x_steping, src_y_steping, video_step_delta;
1724 int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1726 if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1727 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1728 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1729 } else if (tmp_w >= pp_avs_context->dest_w) {
1730 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1731 pp_inline_parameter->grf6.video_step_delta = 0;
1734 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1735 pp_avs_context->src_normalized_x;
1737 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1738 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1739 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1740 16 * 15 * video_step_delta / 2;
1743 int n0, n1, n2, nls_left, nls_right;
1744 int factor_a = 5, factor_b = 4;
1747 n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1748 n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1749 n2 = tmp_w / (16 * factor_a);
1751 nls_right = n1 + n2;
1752 f = (float) n2 * 16 / tmp_w;
1755 pp_inline_parameter->grf6.video_step_delta = 0.0;
1758 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1759 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1761 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1762 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1763 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1764 16 * 15 * video_step_delta / 2;
1768 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1769 float a = f / (nls_left * 16 * factor_b);
1770 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1772 pp_inline_parameter->grf6.video_step_delta = b;
1775 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1776 pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1778 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1779 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1780 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1781 16 * 15 * video_step_delta / 2;
1782 pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1784 } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1785 /* scale the center linearly */
1786 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1787 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1788 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1789 16 * 15 * video_step_delta / 2;
1790 pp_inline_parameter->grf6.video_step_delta = 0.0;
1791 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1793 float a = f / (nls_right * 16 * factor_b);
1794 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1796 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1797 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1798 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1799 16 * 15 * video_step_delta / 2;
1800 pp_inline_parameter->grf6.video_step_delta = -b;
1802 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1803 pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16 - 1) * b;
1805 pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1810 src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1811 pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1812 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1813 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1819 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1820 const struct i965_surface *src_surface,
1821 const VARectangle *src_rect,
1822 struct i965_surface *dst_surface,
1823 const VARectangle *dst_rect,
1827 struct i965_driver_data *i965 = i965_driver_data(ctx);
1828 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1829 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1830 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1831 struct object_surface *obj_surface;
1832 struct i965_sampler_8x8 *sampler_8x8;
1833 struct i965_sampler_8x8_state *sampler_8x8_state;
1835 int in_w, in_h, in_wpitch, in_hpitch;
1836 int out_w, out_h, out_wpitch, out_hpitch;
1840 obj_surface = SURFACE(src_surface->id);
1841 in_w = obj_surface->orig_width;
1842 in_h = obj_surface->orig_height;
1843 in_wpitch = obj_surface->width;
1844 in_hpitch = obj_surface->height;
1846 /* source Y surface index 1 */
1847 i965_pp_set_surface2_state(ctx, pp_context,
1849 in_w, in_h, in_wpitch,
1851 SURFACE_FORMAT_Y8_UNORM, 0,
1854 /* source UV surface index 2 */
1855 i965_pp_set_surface2_state(ctx, pp_context,
1856 obj_surface->bo, in_wpitch * in_hpitch,
1857 in_w / 2, in_h / 2, in_wpitch,
1859 SURFACE_FORMAT_R8B8_UNORM, 0,
1862 /* destination surface */
1863 obj_surface = SURFACE(dst_surface->id);
1864 out_w = obj_surface->orig_width;
1865 out_h = obj_surface->orig_height;
1866 out_wpitch = obj_surface->width;
1867 out_hpitch = obj_surface->height;
1868 assert(out_w <= out_wpitch && out_h <= out_hpitch);
1870 /* destination Y surface index 7 */
1871 i965_pp_set_surface_state(ctx, pp_context,
1873 out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1876 /* destination UV surface index 8 */
1877 i965_pp_set_surface_state(ctx, pp_context,
1878 obj_surface->bo, out_wpitch * out_hpitch,
1879 out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1882 /* sampler 8x8 state */
1883 dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1884 assert(pp_context->sampler_state_table.bo_8x8->virtual);
1885 assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1886 sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1887 memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1889 for (i = 0; i < 17; i++) {
1890 /* for Y channel, currently ignore */
1891 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1892 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1893 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1894 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1895 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1896 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1897 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1898 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1899 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1900 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1901 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1902 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1903 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1904 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1905 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1906 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1907 /* for U/V channel, 0.25 */
1908 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1909 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1910 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1911 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1912 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1913 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1914 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1915 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1916 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1917 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1918 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1919 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1920 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1921 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1922 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1923 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1926 sampler_8x8_state->dw136.default_sharpness_level = 0;
1927 sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1928 sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1929 sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1930 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1933 dri_bo_map(pp_context->sampler_state_table.bo, True);
1934 assert(pp_context->sampler_state_table.bo->virtual);
1935 assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1936 sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1938 /* sample_8x8 Y index 1 */
1940 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1941 sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1942 sampler_8x8[index].dw0.ief_bypass = 1;
1943 sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1944 sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1945 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1946 sampler_8x8[index].dw2.global_noise_estimation = 22;
1947 sampler_8x8[index].dw2.strong_edge_threshold = 8;
1948 sampler_8x8[index].dw2.weak_edge_threshold = 1;
1949 sampler_8x8[index].dw3.strong_edge_weight = 7;
1950 sampler_8x8[index].dw3.regular_weight = 2;
1951 sampler_8x8[index].dw3.non_edge_weight = 0;
1952 sampler_8x8[index].dw3.gain_factor = 40;
1953 sampler_8x8[index].dw4.steepness_boost = 0;
1954 sampler_8x8[index].dw4.steepness_threshold = 0;
1955 sampler_8x8[index].dw4.mr_boost = 0;
1956 sampler_8x8[index].dw4.mr_threshold = 5;
1957 sampler_8x8[index].dw5.pwl1_point_1 = 4;
1958 sampler_8x8[index].dw5.pwl1_point_2 = 12;
1959 sampler_8x8[index].dw5.pwl1_point_3 = 16;
1960 sampler_8x8[index].dw5.pwl1_point_4 = 26;
1961 sampler_8x8[index].dw6.pwl1_point_5 = 40;
1962 sampler_8x8[index].dw6.pwl1_point_6 = 160;
1963 sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1964 sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1965 sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1966 sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1967 sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1968 sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1969 sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1970 sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1971 sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1972 sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1973 sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1974 sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1975 sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1976 sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1977 sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1978 sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1979 sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1980 sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1981 sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1982 sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1983 sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1984 sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1985 sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1986 sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1987 sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1988 sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1989 sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1990 sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1991 sampler_8x8[index].dw13.limiter_boost = 0;
1992 sampler_8x8[index].dw13.minimum_limiter = 10;
1993 sampler_8x8[index].dw13.maximum_limiter = 11;
1994 sampler_8x8[index].dw14.clip_limiter = 130;
1995 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1996 I915_GEM_DOMAIN_RENDER,
1999 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2000 pp_context->sampler_state_table.bo_8x8);
2002 /* sample_8x8 UV index 2 */
2004 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2005 sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2006 sampler_8x8[index].dw0.ief_bypass = 1;
2007 sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2008 sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2009 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2010 sampler_8x8[index].dw2.global_noise_estimation = 22;
2011 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2012 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2013 sampler_8x8[index].dw3.strong_edge_weight = 7;
2014 sampler_8x8[index].dw3.regular_weight = 2;
2015 sampler_8x8[index].dw3.non_edge_weight = 0;
2016 sampler_8x8[index].dw3.gain_factor = 40;
2017 sampler_8x8[index].dw4.steepness_boost = 0;
2018 sampler_8x8[index].dw4.steepness_threshold = 0;
2019 sampler_8x8[index].dw4.mr_boost = 0;
2020 sampler_8x8[index].dw4.mr_threshold = 5;
2021 sampler_8x8[index].dw5.pwl1_point_1 = 4;
2022 sampler_8x8[index].dw5.pwl1_point_2 = 12;
2023 sampler_8x8[index].dw5.pwl1_point_3 = 16;
2024 sampler_8x8[index].dw5.pwl1_point_4 = 26;
2025 sampler_8x8[index].dw6.pwl1_point_5 = 40;
2026 sampler_8x8[index].dw6.pwl1_point_6 = 160;
2027 sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2028 sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2029 sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2030 sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2031 sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2032 sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2033 sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2034 sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2035 sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2036 sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2037 sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2038 sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2039 sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2040 sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2041 sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2042 sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2043 sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2044 sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2045 sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2046 sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2047 sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2048 sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2049 sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2050 sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2051 sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2052 sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2053 sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2054 sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2055 sampler_8x8[index].dw13.limiter_boost = 0;
2056 sampler_8x8[index].dw13.minimum_limiter = 10;
2057 sampler_8x8[index].dw13.maximum_limiter = 11;
2058 sampler_8x8[index].dw14.clip_limiter = 130;
2059 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2060 I915_GEM_DOMAIN_RENDER,
2063 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2064 pp_context->sampler_state_table.bo_8x8);
2066 dri_bo_unmap(pp_context->sampler_state_table.bo);
2068 /* private function & data */
2069 pp_context->pp_x_steps = pp_avs_x_steps;
2070 pp_context->pp_y_steps = pp_avs_y_steps;
2071 pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2073 pp_avs_context->dest_x = dst_rect->x;
2074 pp_avs_context->dest_y = dst_rect->y;
2075 pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2076 pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2077 pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2078 pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2079 pp_avs_context->src_w = src_rect->width;
2080 pp_avs_context->src_h = src_rect->height;
2082 pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2083 pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2085 pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2086 pp_inline_parameter->grf5.block_count_x = 1; /* M x 1 */
2087 pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2088 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2089 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2090 pp_inline_parameter->grf6.video_step_delta = 0.0;
2092 dst_surface->flags = src_surface->flags;
2094 return VA_STATUS_SUCCESS;
2098 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2099 const struct i965_surface *src_surface,
2100 const VARectangle *src_rect,
2101 struct i965_surface *dst_surface,
2102 const VARectangle *dst_rect,
2105 return pp_nv12_avs_initialize(ctx, pp_context,
2115 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2116 const struct i965_surface *src_surface,
2117 const VARectangle *src_rect,
2118 struct i965_surface *dst_surface,
2119 const VARectangle *dst_rect,
2122 return pp_nv12_avs_initialize(ctx, pp_context,
2132 gen7_pp_avs_x_steps(void *private_context)
2134 struct pp_avs_context *pp_avs_context = private_context;
2136 return pp_avs_context->dest_w / 16;
2140 gen7_pp_avs_y_steps(void *private_context)
2142 struct pp_avs_context *pp_avs_context = private_context;
2144 return pp_avs_context->dest_h / 16;
2148 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2150 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2151 struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2153 pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2154 pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2155 pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2156 pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2162 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2163 const struct i965_surface *src_surface,
2164 const VARectangle *src_rect,
2165 struct i965_surface *dst_surface,
2166 const VARectangle *dst_rect,
2169 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2170 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2171 struct gen7_sampler_8x8 *sampler_8x8;
2172 struct i965_sampler_8x8_state *sampler_8x8_state;
2174 int width[3], height[3], pitch[3], offset[3];
2176 /* source surface */
2177 gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2178 width, height, pitch, offset);
2180 /* destination surface */
2181 gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2182 width, height, pitch, offset);
2184 /* sampler 8x8 state */
2185 dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2186 assert(pp_context->sampler_state_table.bo_8x8->virtual);
2187 assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2188 sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2189 memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2191 for (i = 0; i < 17; i++) {
2192 /* for Y channel, currently ignore */
2193 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2194 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2195 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2196 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2197 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2198 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2199 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2200 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2201 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2202 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2203 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2204 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2205 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2206 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2207 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2208 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2209 /* for U/V channel, 0.25 */
2210 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2211 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2212 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2213 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2214 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2215 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2216 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2217 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2218 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2219 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2220 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2221 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2222 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2223 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2224 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2225 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2228 sampler_8x8_state->dw136.default_sharpness_level = 0;
2229 sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2230 sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2231 sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2232 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2235 dri_bo_map(pp_context->sampler_state_table.bo, True);
2236 assert(pp_context->sampler_state_table.bo->virtual);
2237 assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2238 sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2240 /* sample_8x8 Y index 4 */
2242 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2243 sampler_8x8[index].dw0.global_noise_estimation = 255;
2244 sampler_8x8[index].dw0.ief_bypass = 1;
2246 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2248 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2249 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2250 sampler_8x8[index].dw2.r5x_coefficient = 9;
2251 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2252 sampler_8x8[index].dw2.r5c_coefficient = 3;
2254 sampler_8x8[index].dw3.r3x_coefficient = 27;
2255 sampler_8x8[index].dw3.r3c_coefficient = 5;
2256 sampler_8x8[index].dw3.gain_factor = 40;
2257 sampler_8x8[index].dw3.non_edge_weight = 1;
2258 sampler_8x8[index].dw3.regular_weight = 2;
2259 sampler_8x8[index].dw3.strong_edge_weight = 7;
2260 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2262 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2263 I915_GEM_DOMAIN_RENDER,
2266 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2267 pp_context->sampler_state_table.bo_8x8);
2269 /* sample_8x8 UV index 8 */
2271 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2272 sampler_8x8[index].dw0.disable_8x8_filter = 0;
2273 sampler_8x8[index].dw0.global_noise_estimation = 255;
2274 sampler_8x8[index].dw0.ief_bypass = 1;
2275 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2276 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2277 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2278 sampler_8x8[index].dw2.r5x_coefficient = 9;
2279 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2280 sampler_8x8[index].dw2.r5c_coefficient = 3;
2281 sampler_8x8[index].dw3.r3x_coefficient = 27;
2282 sampler_8x8[index].dw3.r3c_coefficient = 5;
2283 sampler_8x8[index].dw3.gain_factor = 40;
2284 sampler_8x8[index].dw3.non_edge_weight = 1;
2285 sampler_8x8[index].dw3.regular_weight = 2;
2286 sampler_8x8[index].dw3.strong_edge_weight = 7;
2287 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2289 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2290 I915_GEM_DOMAIN_RENDER,
2293 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2294 pp_context->sampler_state_table.bo_8x8);
2296 /* sampler_8x8 V, index 12 */
2298 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2299 sampler_8x8[index].dw0.disable_8x8_filter = 0;
2300 sampler_8x8[index].dw0.global_noise_estimation = 255;
2301 sampler_8x8[index].dw0.ief_bypass = 1;
2302 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2303 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2304 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2305 sampler_8x8[index].dw2.r5x_coefficient = 9;
2306 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2307 sampler_8x8[index].dw2.r5c_coefficient = 3;
2308 sampler_8x8[index].dw3.r3x_coefficient = 27;
2309 sampler_8x8[index].dw3.r3c_coefficient = 5;
2310 sampler_8x8[index].dw3.gain_factor = 40;
2311 sampler_8x8[index].dw3.non_edge_weight = 1;
2312 sampler_8x8[index].dw3.regular_weight = 2;
2313 sampler_8x8[index].dw3.strong_edge_weight = 7;
2314 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2316 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2317 I915_GEM_DOMAIN_RENDER,
2320 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2321 pp_context->sampler_state_table.bo_8x8);
2323 dri_bo_unmap(pp_context->sampler_state_table.bo);
2325 /* private function & data */
2326 pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2327 pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2328 pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2330 pp_avs_context->dest_x = dst_rect->x;
2331 pp_avs_context->dest_y = dst_rect->y;
2332 pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2333 pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2334 pp_avs_context->src_w = src_rect->width;
2335 pp_avs_context->src_h = src_rect->height;
2337 int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2338 dw = MAX(dw, pp_avs_context->dest_w);
2340 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2341 pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2342 pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2343 pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2344 pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2346 dst_surface->flags = src_surface->flags;
2348 return VA_STATUS_SUCCESS;
2352 pp_dndi_x_steps(void *private_context)
2358 pp_dndi_y_steps(void *private_context)
2360 struct pp_dndi_context *pp_dndi_context = private_context;
2362 return pp_dndi_context->dest_h / 4;
2366 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2368 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2370 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2371 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2377 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2378 const struct i965_surface *src_surface,
2379 const VARectangle *src_rect,
2380 struct i965_surface *dst_surface,
2381 const VARectangle *dst_rect,
2384 struct i965_driver_data *i965 = i965_driver_data(ctx);
2385 struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2386 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2387 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2388 struct object_surface *obj_surface;
2389 struct i965_sampler_dndi *sampler_dndi;
2393 int dndi_top_first = 1;
2395 if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2396 return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2398 if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2404 obj_surface = SURFACE(src_surface->id);
2405 orig_w = obj_surface->orig_width;
2406 orig_h = obj_surface->orig_height;
2407 w = obj_surface->width;
2408 h = obj_surface->height;
2410 if (pp_context->stmm.bo == NULL) {
2411 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2415 assert(pp_context->stmm.bo);
2418 /* source UV surface index 2 */
2419 i965_pp_set_surface_state(ctx, pp_context,
2420 obj_surface->bo, w * h,
2421 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2424 /* source YUV surface index 4 */
2425 i965_pp_set_surface2_state(ctx, pp_context,
2429 SURFACE_FORMAT_PLANAR_420_8, 1,
2432 /* source STMM surface index 20 */
2433 i965_pp_set_surface_state(ctx, pp_context,
2434 pp_context->stmm.bo, 0,
2435 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2438 /* destination surface */
2439 obj_surface = SURFACE(dst_surface->id);
2440 orig_w = obj_surface->orig_width;
2441 orig_h = obj_surface->orig_height;
2442 w = obj_surface->width;
2443 h = obj_surface->height;
2445 /* destination Y surface index 7 */
2446 i965_pp_set_surface_state(ctx, pp_context,
2448 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2451 /* destination UV surface index 8 */
2452 i965_pp_set_surface_state(ctx, pp_context,
2453 obj_surface->bo, w * h,
2454 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2457 dri_bo_map(pp_context->sampler_state_table.bo, True);
2458 assert(pp_context->sampler_state_table.bo->virtual);
2459 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2460 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2462 /* sample dndi index 1 */
2464 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2465 sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8
2466 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2467 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2469 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2470 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2471 sampler_dndi[index].dw1.stmm_c2 = 1;
2472 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2473 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2475 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15; // 0-31
2476 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15
2477 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15
2478 sampler_dndi[index].dw2.good_neighbor_threshold = 4; // 0-63
2480 sampler_dndi[index].dw3.maximum_stmm = 128;
2481 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2482 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2483 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2484 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2486 sampler_dndi[index].dw4.sdi_delta = 8;
2487 sampler_dndi[index].dw4.sdi_threshold = 128;
2488 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2489 sampler_dndi[index].dw4.stmm_shift_up = 0;
2490 sampler_dndi[index].dw4.stmm_shift_down = 0;
2491 sampler_dndi[index].dw4.minimum_stmm = 0;
2493 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2494 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2495 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2496 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2498 sampler_dndi[index].dw6.dn_enable = 1;
2499 sampler_dndi[index].dw6.di_enable = 1;
2500 sampler_dndi[index].dw6.di_partial = 0;
2501 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2502 sampler_dndi[index].dw6.dndi_stream_id = 0;
2503 sampler_dndi[index].dw6.dndi_first_frame = 1;
2504 sampler_dndi[index].dw6.progressive_dn = 0;
2505 sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2506 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2507 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2509 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2510 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2511 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2512 sampler_dndi[index].dw7.column_width_minus1 = 0;
2514 dri_bo_unmap(pp_context->sampler_state_table.bo);
2516 /* private function & data */
2517 pp_context->pp_x_steps = pp_dndi_x_steps;
2518 pp_context->pp_y_steps = pp_dndi_y_steps;
2519 pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2521 pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2522 pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2523 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2524 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2526 pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */
2527 pp_inline_parameter->grf5.number_blocks = w / 16;
2528 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2529 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2531 pp_dndi_context->dest_w = w;
2532 pp_dndi_context->dest_h = h;
2534 dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2536 return VA_STATUS_SUCCESS;
2540 pp_dn_x_steps(void *private_context)
2546 pp_dn_y_steps(void *private_context)
2548 struct pp_dn_context *pp_dn_context = private_context;
2550 return pp_dn_context->dest_h / 8;
2554 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2556 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2558 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2559 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2565 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2566 const struct i965_surface *src_surface,
2567 const VARectangle *src_rect,
2568 struct i965_surface *dst_surface,
2569 const VARectangle *dst_rect,
2572 struct i965_driver_data *i965 = i965_driver_data(ctx);
2573 struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2574 struct object_surface *obj_surface;
2575 struct i965_sampler_dndi *sampler_dndi;
2576 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2577 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2578 VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2582 int dn_strength = 15;
2583 int dndi_top_first = 1;
2584 int dn_progressive = 0;
2586 if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2589 } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2597 if (dn_filter_param) {
2598 float value = dn_filter_param->value;
2606 dn_strength = (int)(value * 31.0F);
2610 obj_surface = SURFACE(src_surface->id);
2611 orig_w = obj_surface->orig_width;
2612 orig_h = obj_surface->orig_height;
2613 w = obj_surface->width;
2614 h = obj_surface->height;
2616 if (pp_context->stmm.bo == NULL) {
2617 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2621 assert(pp_context->stmm.bo);
2624 /* source UV surface index 2 */
2625 i965_pp_set_surface_state(ctx, pp_context,
2626 obj_surface->bo, w * h,
2627 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2630 /* source YUV surface index 4 */
2631 i965_pp_set_surface2_state(ctx, pp_context,
2635 SURFACE_FORMAT_PLANAR_420_8, 1,
2638 /* source STMM surface index 20 */
2639 i965_pp_set_surface_state(ctx, pp_context,
2640 pp_context->stmm.bo, 0,
2641 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2644 /* destination surface */
2645 obj_surface = SURFACE(dst_surface->id);
2646 orig_w = obj_surface->orig_width;
2647 orig_h = obj_surface->orig_height;
2648 w = obj_surface->width;
2649 h = obj_surface->height;
2651 /* destination Y surface index 7 */
2652 i965_pp_set_surface_state(ctx, pp_context,
2654 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2657 /* destination UV surface index 8 */
2658 i965_pp_set_surface_state(ctx, pp_context,
2659 obj_surface->bo, w * h,
2660 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2663 dri_bo_map(pp_context->sampler_state_table.bo, True);
2664 assert(pp_context->sampler_state_table.bo->virtual);
2665 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2666 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2668 /* sample dndi index 1 */
2670 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2671 sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8
2672 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2673 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2675 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2676 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2677 sampler_dndi[index].dw1.stmm_c2 = 0;
2678 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2679 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2681 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31
2682 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15
2683 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15
2684 sampler_dndi[index].dw2.good_neighbor_threshold = 7; // 0-63
2686 sampler_dndi[index].dw3.maximum_stmm = 128;
2687 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2688 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2689 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2690 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2692 sampler_dndi[index].dw4.sdi_delta = 8;
2693 sampler_dndi[index].dw4.sdi_threshold = 128;
2694 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2695 sampler_dndi[index].dw4.stmm_shift_up = 0;
2696 sampler_dndi[index].dw4.stmm_shift_down = 0;
2697 sampler_dndi[index].dw4.minimum_stmm = 0;
2699 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2700 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2701 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2702 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2704 sampler_dndi[index].dw6.dn_enable = 1;
2705 sampler_dndi[index].dw6.di_enable = 0;
2706 sampler_dndi[index].dw6.di_partial = 0;
2707 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2708 sampler_dndi[index].dw6.dndi_stream_id = 1;
2709 sampler_dndi[index].dw6.dndi_first_frame = 1;
2710 sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2711 sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2712 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2713 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2715 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2716 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2717 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2718 sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2720 dri_bo_unmap(pp_context->sampler_state_table.bo);
2722 /* private function & data */
2723 pp_context->pp_x_steps = pp_dn_x_steps;
2724 pp_context->pp_y_steps = pp_dn_y_steps;
2725 pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2727 pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2728 pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2729 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2730 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2732 pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */
2733 pp_inline_parameter->grf5.number_blocks = w / 16;
2734 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2735 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2737 pp_dn_context->dest_w = w;
2738 pp_dn_context->dest_h = h;
2740 dst_surface->flags = src_surface->flags;
2742 return VA_STATUS_SUCCESS;
2746 gen7_pp_dndi_x_steps(void *private_context)
2748 struct pp_dndi_context *pp_dndi_context = private_context;
2750 return pp_dndi_context->dest_w / 16;
2754 gen7_pp_dndi_y_steps(void *private_context)
2756 struct pp_dndi_context *pp_dndi_context = private_context;
2758 return pp_dndi_context->dest_h / 4;
2762 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2764 struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2766 pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2767 pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2773 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2774 const struct i965_surface *src_surface,
2775 const VARectangle *src_rect,
2776 struct i965_surface *dst_surface,
2777 const VARectangle *dst_rect,
2780 struct i965_driver_data *i965 = i965_driver_data(ctx);
2781 struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2782 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2783 struct object_surface *obj_surface;
2784 struct gen7_sampler_dndi *sampler_dndi;
2788 int dndi_top_first = 1;
2790 if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2791 return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2793 if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2799 obj_surface = SURFACE(src_surface->id);
2800 orig_w = obj_surface->orig_width;
2801 orig_h = obj_surface->orig_height;
2802 w = obj_surface->width;
2803 h = obj_surface->height;
2805 if (pp_context->stmm.bo == NULL) {
2806 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2810 assert(pp_context->stmm.bo);
2813 /* source UV surface index 1 */
2814 gen7_pp_set_surface_state(ctx, pp_context,
2815 obj_surface->bo, w * h,
2816 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2819 /* source YUV surface index 3 */
2820 gen7_pp_set_surface2_state(ctx, pp_context,
2824 SURFACE_FORMAT_PLANAR_420_8, 1,
2827 /* source (temporal reference) YUV surface index 4 */
2828 gen7_pp_set_surface2_state(ctx, pp_context,
2832 SURFACE_FORMAT_PLANAR_420_8, 1,
2835 /* STMM / History Statistics input surface, index 5 */
2836 gen7_pp_set_surface_state(ctx, pp_context,
2837 pp_context->stmm.bo, 0,
2838 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2841 /* destination surface */
2842 obj_surface = SURFACE(dst_surface->id);
2843 orig_w = obj_surface->orig_width;
2844 orig_h = obj_surface->orig_height;
2845 w = obj_surface->width;
2846 h = obj_surface->height;
2848 /* destination(Previous frame) Y surface index 27 */
2849 gen7_pp_set_surface_state(ctx, pp_context,
2851 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2854 /* destination(Previous frame) UV surface index 28 */
2855 gen7_pp_set_surface_state(ctx, pp_context,
2856 obj_surface->bo, w * h,
2857 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2860 /* destination(Current frame) Y surface index 30 */
2861 gen7_pp_set_surface_state(ctx, pp_context,
2863 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2866 /* destination(Current frame) UV surface index 31 */
2867 gen7_pp_set_surface_state(ctx, pp_context,
2868 obj_surface->bo, w * h,
2869 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2872 /* STMM output surface, index 33 */
2873 gen7_pp_set_surface_state(ctx, pp_context,
2874 pp_context->stmm.bo, 0,
2875 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2880 dri_bo_map(pp_context->sampler_state_table.bo, True);
2881 assert(pp_context->sampler_state_table.bo->virtual);
2882 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2883 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2885 /* sample dndi index 0 */
2887 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2888 sampler_dndi[index].dw0.dnmh_delt = 8;
2889 sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2890 sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2891 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2892 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2894 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2895 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2896 sampler_dndi[index].dw1.stmm_c2 = 0;
2897 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2898 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2900 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15; // 0-31
2901 sampler_dndi[index].dw2.bne_edge_th = 1;
2902 sampler_dndi[index].dw2.smooth_mv_th = 0;
2903 sampler_dndi[index].dw2.sad_tight_th = 5;
2904 sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2905 sampler_dndi[index].dw2.good_neighbor_th = 4;
2907 sampler_dndi[index].dw3.maximum_stmm = 128;
2908 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2909 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2910 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2911 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2913 sampler_dndi[index].dw4.sdi_delta = 8;
2914 sampler_dndi[index].dw4.sdi_threshold = 128;
2915 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2916 sampler_dndi[index].dw4.stmm_shift_up = 0;
2917 sampler_dndi[index].dw4.stmm_shift_down = 0;
2918 sampler_dndi[index].dw4.minimum_stmm = 0;
2920 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2921 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2922 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2923 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2925 sampler_dndi[index].dw6.dn_enable = 0;
2926 sampler_dndi[index].dw6.di_enable = 1;
2927 sampler_dndi[index].dw6.di_partial = 0;
2928 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2929 sampler_dndi[index].dw6.dndi_stream_id = 1;
2930 sampler_dndi[index].dw6.dndi_first_frame = 1;
2931 sampler_dndi[index].dw6.progressive_dn = 0;
2932 sampler_dndi[index].dw6.mcdi_enable = 0;
2933 sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2934 sampler_dndi[index].dw6.cat_th1 = 0;
2935 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2936 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2938 sampler_dndi[index].dw7.sad_tha = 5;
2939 sampler_dndi[index].dw7.sad_thb = 10;
2940 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2941 sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2942 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2943 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2944 sampler_dndi[index].dw7.neighborpixel_th = 10;
2945 sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2947 dri_bo_unmap(pp_context->sampler_state_table.bo);
2949 /* private function & data */
2950 pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2951 pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2952 pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2954 pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2955 pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2956 pp_static_parameter->grf1.di_top_field_first = 0;
2957 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2959 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2960 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2961 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2963 pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2964 pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2966 pp_dndi_context->dest_w = w;
2967 pp_dndi_context->dest_h = h;
2969 dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2971 return VA_STATUS_SUCCESS;
2975 gen7_pp_dn_x_steps(void *private_context)
2981 gen7_pp_dn_y_steps(void *private_context)
2983 struct pp_dn_context *pp_dn_context = private_context;
2985 return pp_dn_context->dest_h / 4;
2989 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2991 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2993 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2994 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3000 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3001 const struct i965_surface *src_surface,
3002 const VARectangle *src_rect,
3003 struct i965_surface *dst_surface,
3004 const VARectangle *dst_rect,
3007 struct i965_driver_data *i965 = i965_driver_data(ctx);
3008 struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3009 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3010 struct object_surface *obj_surface;
3011 struct gen7_sampler_dndi *sampler_dn;
3012 VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3016 int dn_strength = 15;
3017 int dndi_top_first = 1;
3018 int dn_progressive = 0;
3020 if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3023 } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3031 if (dn_filter_param) {
3032 float value = dn_filter_param->value;
3040 dn_strength = (int)(value * 31.0F);
3044 obj_surface = SURFACE(src_surface->id);
3045 orig_w = obj_surface->orig_width;
3046 orig_h = obj_surface->orig_height;
3047 w = obj_surface->width;
3048 h = obj_surface->height;
3050 if (pp_context->stmm.bo == NULL) {
3051 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3055 assert(pp_context->stmm.bo);
3058 /* source UV surface index 1 */
3059 gen7_pp_set_surface_state(ctx, pp_context,
3060 obj_surface->bo, w * h,
3061 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3064 /* source YUV surface index 3 */
3065 gen7_pp_set_surface2_state(ctx, pp_context,
3069 SURFACE_FORMAT_PLANAR_420_8, 1,
3072 /* source STMM surface index 5 */
3073 gen7_pp_set_surface_state(ctx, pp_context,
3074 pp_context->stmm.bo, 0,
3075 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3078 /* destination surface */
3079 obj_surface = SURFACE(dst_surface->id);
3080 orig_w = obj_surface->orig_width;
3081 orig_h = obj_surface->orig_height;
3082 w = obj_surface->width;
3083 h = obj_surface->height;
3085 /* destination Y surface index 7 */
3086 gen7_pp_set_surface_state(ctx, pp_context,
3088 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3091 /* destination UV surface index 8 */
3092 gen7_pp_set_surface_state(ctx, pp_context,
3093 obj_surface->bo, w * h,
3094 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3097 dri_bo_map(pp_context->sampler_state_table.bo, True);
3098 assert(pp_context->sampler_state_table.bo->virtual);
3099 assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3100 sampler_dn = pp_context->sampler_state_table.bo->virtual;
3102 /* sample dn index 1 */
3104 sampler_dn[index].dw0.denoise_asd_threshold = 0;
3105 sampler_dn[index].dw0.dnmh_delt = 8;
3106 sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3107 sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3108 sampler_dn[index].dw0.denoise_maximum_history = 128; // 128-240
3109 sampler_dn[index].dw0.denoise_stad_threshold = 0;
3111 sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3112 sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3113 sampler_dn[index].dw1.stmm_c2 = 0;
3114 sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3115 sampler_dn[index].dw1.temporal_difference_threshold = 16;
3117 sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31
3118 sampler_dn[index].dw2.bne_edge_th = 1;
3119 sampler_dn[index].dw2.smooth_mv_th = 0;
3120 sampler_dn[index].dw2.sad_tight_th = 5;
3121 sampler_dn[index].dw2.cat_slope_minus1 = 9;
3122 sampler_dn[index].dw2.good_neighbor_th = 4;
3124 sampler_dn[index].dw3.maximum_stmm = 128;
3125 sampler_dn[index].dw3.multipler_for_vecm = 2;
3126 sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3127 sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3128 sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3130 sampler_dn[index].dw4.sdi_delta = 8;
3131 sampler_dn[index].dw4.sdi_threshold = 128;
3132 sampler_dn[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
3133 sampler_dn[index].dw4.stmm_shift_up = 0;
3134 sampler_dn[index].dw4.stmm_shift_down = 0;
3135 sampler_dn[index].dw4.minimum_stmm = 0;
3137 sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3138 sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3139 sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3140 sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3142 sampler_dn[index].dw6.dn_enable = 1;
3143 sampler_dn[index].dw6.di_enable = 0;
3144 sampler_dn[index].dw6.di_partial = 0;
3145 sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3146 sampler_dn[index].dw6.dndi_stream_id = 1;
3147 sampler_dn[index].dw6.dndi_first_frame = 1;
3148 sampler_dn[index].dw6.progressive_dn = dn_progressive;
3149 sampler_dn[index].dw6.mcdi_enable = 0;
3150 sampler_dn[index].dw6.fmd_tear_threshold = 32;
3151 sampler_dn[index].dw6.cat_th1 = 0;
3152 sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3153 sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3155 sampler_dn[index].dw7.sad_tha = 5;
3156 sampler_dn[index].dw7.sad_thb = 10;
3157 sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3158 sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3159 sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3160 sampler_dn[index].dw7.vdi_walker_enable = 0;
3161 sampler_dn[index].dw7.neighborpixel_th = 10;
3162 sampler_dn[index].dw7.column_width_minus1 = w / 16;
3164 dri_bo_unmap(pp_context->sampler_state_table.bo);
3166 /* private function & data */
3167 pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3168 pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3169 pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3171 pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3172 pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3173 pp_static_parameter->grf1.di_top_field_first = 0;
3174 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3176 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3177 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3178 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3180 pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3181 pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3183 pp_dn_context->dest_w = w;
3184 pp_dn_context->dest_h = h;
3186 dst_surface->flags = src_surface->flags;
3188 return VA_STATUS_SUCCESS;
3192 ironlake_pp_initialize(
3193 VADriverContextP ctx,
3194 struct i965_post_processing_context *pp_context,
3195 const struct i965_surface *src_surface,
3196 const VARectangle *src_rect,
3197 struct i965_surface *dst_surface,
3198 const VARectangle *dst_rect,
3204 struct i965_driver_data *i965 = i965_driver_data(ctx);
3205 struct pp_module *pp_module;
3207 int static_param_size, inline_param_size;
3209 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3210 bo = dri_bo_alloc(i965->intel.bufmgr,
3211 "surface state & binding table",
3212 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3215 pp_context->surface_state_binding_table.bo = bo;
3217 dri_bo_unreference(pp_context->curbe.bo);
3218 bo = dri_bo_alloc(i965->intel.bufmgr,
3223 pp_context->curbe.bo = bo;
3225 dri_bo_unreference(pp_context->idrt.bo);
3226 bo = dri_bo_alloc(i965->intel.bufmgr,
3227 "interface discriptor",
3228 sizeof(struct i965_interface_descriptor),
3231 pp_context->idrt.bo = bo;
3232 pp_context->idrt.num_interface_descriptors = 0;
3234 dri_bo_unreference(pp_context->sampler_state_table.bo);
3235 bo = dri_bo_alloc(i965->intel.bufmgr,
3236 "sampler state table",
3240 dri_bo_map(bo, True);
3241 memset(bo->virtual, 0, bo->size);
3243 pp_context->sampler_state_table.bo = bo;
3245 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3246 bo = dri_bo_alloc(i965->intel.bufmgr,
3247 "sampler 8x8 state ",
3251 pp_context->sampler_state_table.bo_8x8 = bo;
3253 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3254 bo = dri_bo_alloc(i965->intel.bufmgr,
3255 "sampler 8x8 state ",
3259 pp_context->sampler_state_table.bo_8x8_uv = bo;
3261 dri_bo_unreference(pp_context->vfe_state.bo);
3262 bo = dri_bo_alloc(i965->intel.bufmgr,
3264 sizeof(struct i965_vfe_state),
3267 pp_context->vfe_state.bo = bo;
3269 static_param_size = sizeof(struct pp_static_parameter);
3270 inline_param_size = sizeof(struct pp_inline_parameter);
3272 memset(pp_context->pp_static_parameter, 0, static_param_size);
3273 memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3275 assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3276 pp_context->current_pp = pp_index;
3277 pp_module = &pp_context->pp_modules[pp_index];
3279 if (pp_module->initialize)
3280 va_status = pp_module->initialize(ctx, pp_context,
3287 va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3293 ironlake_post_processing(
3294 VADriverContextP ctx,
3295 struct i965_post_processing_context *pp_context,
3296 const struct i965_surface *src_surface,
3297 const VARectangle *src_rect,
3298 struct i965_surface *dst_surface,
3299 const VARectangle *dst_rect,
3306 va_status = ironlake_pp_initialize(ctx, pp_context,
3314 if (va_status == VA_STATUS_SUCCESS) {
3315 ironlake_pp_states_setup(ctx, pp_context);
3316 ironlake_pp_pipeline_setup(ctx, pp_context);
3324 VADriverContextP ctx,
3325 struct i965_post_processing_context *pp_context,
3326 const struct i965_surface *src_surface,
3327 const VARectangle *src_rect,
3328 struct i965_surface *dst_surface,
3329 const VARectangle *dst_rect,
3335 struct i965_driver_data *i965 = i965_driver_data(ctx);
3336 struct pp_module *pp_module;
3338 int static_param_size, inline_param_size;
3340 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3341 bo = dri_bo_alloc(i965->intel.bufmgr,
3342 "surface state & binding table",
3343 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3346 pp_context->surface_state_binding_table.bo = bo;
3348 dri_bo_unreference(pp_context->curbe.bo);
3349 bo = dri_bo_alloc(i965->intel.bufmgr,
3354 pp_context->curbe.bo = bo;
3356 dri_bo_unreference(pp_context->idrt.bo);
3357 bo = dri_bo_alloc(i965->intel.bufmgr,
3358 "interface discriptor",
3359 sizeof(struct gen6_interface_descriptor_data),
3362 pp_context->idrt.bo = bo;
3363 pp_context->idrt.num_interface_descriptors = 0;
3365 dri_bo_unreference(pp_context->sampler_state_table.bo);
3366 bo = dri_bo_alloc(i965->intel.bufmgr,
3367 "sampler state table",
3371 dri_bo_map(bo, True);
3372 memset(bo->virtual, 0, bo->size);
3374 pp_context->sampler_state_table.bo = bo;
3376 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3377 bo = dri_bo_alloc(i965->intel.bufmgr,
3378 "sampler 8x8 state ",
3382 pp_context->sampler_state_table.bo_8x8 = bo;
3384 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3385 bo = dri_bo_alloc(i965->intel.bufmgr,
3386 "sampler 8x8 state ",
3390 pp_context->sampler_state_table.bo_8x8_uv = bo;
3392 dri_bo_unreference(pp_context->vfe_state.bo);
3393 bo = dri_bo_alloc(i965->intel.bufmgr,
3395 sizeof(struct i965_vfe_state),
3398 pp_context->vfe_state.bo = bo;
3400 if (IS_GEN7(i965->intel.device_id)) {
3401 static_param_size = sizeof(struct gen7_pp_static_parameter);
3402 inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3404 static_param_size = sizeof(struct pp_static_parameter);
3405 inline_param_size = sizeof(struct pp_inline_parameter);
3408 memset(pp_context->pp_static_parameter, 0, static_param_size);
3409 memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3411 assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3412 pp_context->current_pp = pp_index;
3413 pp_module = &pp_context->pp_modules[pp_index];
3415 if (pp_module->initialize)
3416 va_status = pp_module->initialize(ctx, pp_context,
3423 va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3429 gen6_pp_interface_descriptor_table(VADriverContextP ctx,
3430 struct i965_post_processing_context *pp_context)
3432 struct i965_driver_data *i965 = i965_driver_data(ctx);
3433 struct gen6_interface_descriptor_data *desc;
3435 int pp_index = pp_context->current_pp;
3437 bo = pp_context->idrt.bo;
3438 dri_bo_map(bo, True);
3439 assert(bo->virtual);
3441 memset(desc, 0, sizeof(*desc));
3442 desc->desc0.kernel_start_pointer =
3443 pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3444 desc->desc1.single_program_flow = 1;
3445 desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3446 desc->desc2.sampler_count = 1; /* 1 - 4 samplers used */
3447 desc->desc2.sampler_state_pointer =
3448 pp_context->sampler_state_table.bo->offset >> 5;
3449 desc->desc3.binding_table_entry_count = 0;
3450 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3451 desc->desc4.constant_urb_entry_read_offset = 0;
3453 if (IS_GEN7(i965->intel.device_id))
3454 desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3456 desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3458 dri_bo_emit_reloc(bo,
3459 I915_GEM_DOMAIN_INSTRUCTION, 0,
3461 offsetof(struct gen6_interface_descriptor_data, desc0),
3462 pp_context->pp_modules[pp_index].kernel.bo);
3464 dri_bo_emit_reloc(bo,
3465 I915_GEM_DOMAIN_INSTRUCTION, 0,
3466 desc->desc2.sampler_count << 2,
3467 offsetof(struct gen6_interface_descriptor_data, desc2),
3468 pp_context->sampler_state_table.bo);
3471 pp_context->idrt.num_interface_descriptors++;
3475 gen6_pp_upload_constants(VADriverContextP ctx,
3476 struct i965_post_processing_context *pp_context)
3478 struct i965_driver_data *i965 = i965_driver_data(ctx);
3479 unsigned char *constant_buffer;
3482 assert(sizeof(struct pp_static_parameter) == 128);
3483 assert(sizeof(struct gen7_pp_static_parameter) == 192);
3485 if (IS_GEN7(i965->intel.device_id))
3486 param_size = sizeof(struct gen7_pp_static_parameter);
3488 param_size = sizeof(struct pp_static_parameter);
3490 dri_bo_map(pp_context->curbe.bo, 1);
3491 assert(pp_context->curbe.bo->virtual);
3492 constant_buffer = pp_context->curbe.bo->virtual;
3493 memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3494 dri_bo_unmap(pp_context->curbe.bo);
3498 gen6_pp_states_setup(VADriverContextP ctx,
3499 struct i965_post_processing_context *pp_context)
3501 gen6_pp_interface_descriptor_table(ctx, pp_context);
3502 gen6_pp_upload_constants(ctx, pp_context);
3506 gen6_pp_pipeline_select(VADriverContextP ctx,
3507 struct i965_post_processing_context *pp_context)
3509 struct intel_batchbuffer *batch = pp_context->batch;
3511 BEGIN_BATCH(batch, 1);
3512 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3513 ADVANCE_BATCH(batch);
3517 gen6_pp_state_base_address(VADriverContextP ctx,
3518 struct i965_post_processing_context *pp_context)
3520 struct intel_batchbuffer *batch = pp_context->batch;
3522 BEGIN_BATCH(batch, 10);
3523 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3524 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3525 OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3526 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3527 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3528 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3529 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3530 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3531 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3532 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3533 ADVANCE_BATCH(batch);
3537 gen6_pp_vfe_state(VADriverContextP ctx,
3538 struct i965_post_processing_context *pp_context)
3540 struct intel_batchbuffer *batch = pp_context->batch;
3542 BEGIN_BATCH(batch, 8);
3543 OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3544 OUT_BATCH(batch, 0);
3546 (pp_context->urb.num_vfe_entries - 1) << 16 |
3547 pp_context->urb.num_vfe_entries << 8);
3548 OUT_BATCH(batch, 0);
3550 (pp_context->urb.size_vfe_entry * 2) << 16 | /* URB Entry Allocation Size, in 256 bits unit */
3551 (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3552 OUT_BATCH(batch, 0);
3553 OUT_BATCH(batch, 0);
3554 OUT_BATCH(batch, 0);
3555 ADVANCE_BATCH(batch);
3559 gen6_pp_curbe_load(VADriverContextP ctx,
3560 struct i965_post_processing_context *pp_context)
3562 struct intel_batchbuffer *batch = pp_context->batch;
3564 assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3566 BEGIN_BATCH(batch, 4);
3567 OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3568 OUT_BATCH(batch, 0);
3570 pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3572 pp_context->curbe.bo,
3573 I915_GEM_DOMAIN_INSTRUCTION, 0,
3575 ADVANCE_BATCH(batch);
3579 gen6_interface_descriptor_load(VADriverContextP ctx,
3580 struct i965_post_processing_context *pp_context)
3582 struct intel_batchbuffer *batch = pp_context->batch;
3584 BEGIN_BATCH(batch, 4);
3585 OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3586 OUT_BATCH(batch, 0);
3588 pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3590 pp_context->idrt.bo,
3591 I915_GEM_DOMAIN_INSTRUCTION, 0,
3593 ADVANCE_BATCH(batch);
3597 gen6_pp_object_walker(VADriverContextP ctx,
3598 struct i965_post_processing_context *pp_context)
3600 struct i965_driver_data *i965 = i965_driver_data(ctx);
3601 struct intel_batchbuffer *batch = pp_context->batch;
3602 int x, x_steps, y, y_steps;
3603 int param_size, command_length_in_dws;
3604 dri_bo *command_buffer;
3605 unsigned int *command_ptr;
3607 if (IS_GEN7(i965->intel.device_id))
3608 param_size = sizeof(struct gen7_pp_inline_parameter);
3610 param_size = sizeof(struct pp_inline_parameter);
3612 x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3613 y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3614 command_length_in_dws = 6 + (param_size >> 2);
3615 command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3616 "command objects buffer",
3617 command_length_in_dws * 4 * x_steps * y_steps + 8,
3620 dri_bo_map(command_buffer, 1);
3621 command_ptr = command_buffer->virtual;
3623 for (y = 0; y < y_steps; y++) {
3624 for (x = 0; x < x_steps; x++) {
3625 if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3626 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3632 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3633 command_ptr += (param_size >> 2);
3638 if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3641 *command_ptr = MI_BATCH_BUFFER_END;
3643 dri_bo_unmap(command_buffer);
3645 BEGIN_BATCH(batch, 2);
3646 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3647 OUT_RELOC(batch, command_buffer,
3648 I915_GEM_DOMAIN_COMMAND, 0,
3650 ADVANCE_BATCH(batch);
3652 dri_bo_unreference(command_buffer);
3654 /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3655 * will cause control to pass back to ring buffer
3657 intel_batchbuffer_end_atomic(batch);
3658 intel_batchbuffer_flush(batch);
3659 intel_batchbuffer_start_atomic(batch, 0x1000);
3663 gen6_pp_pipeline_setup(VADriverContextP ctx,
3664 struct i965_post_processing_context *pp_context)
3666 struct intel_batchbuffer *batch = pp_context->batch;
3668 intel_batchbuffer_start_atomic(batch, 0x1000);
3669 intel_batchbuffer_emit_mi_flush(batch);
3670 gen6_pp_pipeline_select(ctx, pp_context);
3671 gen6_pp_state_base_address(ctx, pp_context);
3672 gen6_pp_vfe_state(ctx, pp_context);
3673 gen6_pp_curbe_load(ctx, pp_context);
3674 gen6_interface_descriptor_load(ctx, pp_context);
3675 gen6_pp_object_walker(ctx, pp_context);
3676 intel_batchbuffer_end_atomic(batch);
3680 gen6_post_processing(
3681 VADriverContextP ctx,
3682 struct i965_post_processing_context *pp_context,
3683 const struct i965_surface *src_surface,
3684 const VARectangle *src_rect,
3685 struct i965_surface *dst_surface,
3686 const VARectangle *dst_rect,
3693 va_status = gen6_pp_initialize(ctx, pp_context,
3701 if (va_status == VA_STATUS_SUCCESS) {
3702 gen6_pp_states_setup(ctx, pp_context);
3703 gen6_pp_pipeline_setup(ctx, pp_context);
3710 i965_post_processing_internal(
3711 VADriverContextP ctx,
3712 struct i965_post_processing_context *pp_context,
3713 const struct i965_surface *src_surface,
3714 const VARectangle *src_rect,
3715 struct i965_surface *dst_surface,
3716 const VARectangle *dst_rect,
3721 struct i965_driver_data *i965 = i965_driver_data(ctx);
3724 if (IS_GEN6(i965->intel.device_id) ||
3725 IS_GEN7(i965->intel.device_id))
3726 va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3728 va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3734 i965_DestroySurfaces(VADriverContextP ctx,
3735 VASurfaceID *surface_list,
3738 i965_CreateSurfaces(VADriverContextP ctx,
3743 VASurfaceID *surfaces);
3746 rgb_to_yuv(unsigned int argb,
3752 int r = ((argb >> 16) & 0xff);
3753 int g = ((argb >> 8) & 0xff);
3754 int b = ((argb >> 0) & 0xff);
3756 *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3757 *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3758 *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3759 *a = ((argb >> 24) & 0xff);
3763 i965_vpp_clear_surface(VADriverContextP ctx,
3764 struct i965_post_processing_context *pp_context,
3765 VASurfaceID surface,
3768 struct i965_driver_data *i965 = i965_driver_data(ctx);
3769 struct intel_batchbuffer *batch = pp_context->batch;
3770 struct object_surface *obj_surface = SURFACE(surface);
3771 unsigned int blt_cmd, br13;
3772 unsigned int tiling = 0, swizzle = 0;
3774 unsigned char y, u, v, a = 0;
3776 /* Currently only support NV12 surface */
3777 if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3780 rgb_to_yuv(color, &y, &u, &v, &a);
3785 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3786 blt_cmd = XY_COLOR_BLT_CMD;
3787 pitch = obj_surface->width;
3789 if (tiling != I915_TILING_NONE) {
3790 blt_cmd |= XY_COLOR_BLT_DST_TILED;
3798 if (IS_GEN6(i965->intel.device_id) ||
3799 IS_GEN7(i965->intel.device_id)) {
3800 intel_batchbuffer_start_atomic_blt(batch, 48);
3801 BEGIN_BLT_BATCH(batch, 12);
3803 intel_batchbuffer_start_atomic(batch, 48);
3804 BEGIN_BATCH(batch, 12);
3807 OUT_BATCH(batch, blt_cmd);
3808 OUT_BATCH(batch, br13);
3813 obj_surface->height << 16 |
3814 obj_surface->width);
3815 OUT_RELOC(batch, obj_surface->bo,
3816 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3818 OUT_BATCH(batch, y);
3824 OUT_BATCH(batch, blt_cmd);
3825 OUT_BATCH(batch, br13);
3830 obj_surface->height / 2 << 16 |
3831 obj_surface->width / 2);
3832 OUT_RELOC(batch, obj_surface->bo,
3833 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3834 obj_surface->width * obj_surface->y_cb_offset);
3835 OUT_BATCH(batch, v << 8 | u);
3837 ADVANCE_BATCH(batch);
3838 intel_batchbuffer_end_atomic(batch);
3842 i965_post_processing(
3843 VADriverContextP ctx,
3844 VASurfaceID surface,
3845 const VARectangle *src_rect,
3846 const VARectangle *dst_rect,
3848 int *has_done_scaling
3851 struct i965_driver_data *i965 = i965_driver_data(ctx);
3852 VASurfaceID in_surface_id = surface;
3853 VASurfaceID out_surface_id = VA_INVALID_ID;
3855 *has_done_scaling = 0;
3858 struct object_surface *obj_surface;
3860 struct i965_surface src_surface;
3861 struct i965_surface dst_surface;
3863 obj_surface = SURFACE(in_surface_id);
3865 /* Currently only support post processing for NV12 surface */
3866 if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3867 return out_surface_id;
3869 _i965LockMutex(&i965->pp_mutex);
3871 if (flags & I965_PP_FLAG_MCDI) {
3872 status = i965_CreateSurfaces(ctx,
3873 obj_surface->orig_width,
3874 obj_surface->orig_height,
3875 VA_RT_FORMAT_YUV420,
3878 assert(status == VA_STATUS_SUCCESS);
3879 obj_surface = SURFACE(out_surface_id);
3880 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3881 i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3882 src_surface.id = in_surface_id;
3883 src_surface.type = I965_SURFACE_TYPE_SURFACE;
3884 src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3885 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3886 dst_surface.id = out_surface_id;
3887 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3888 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3890 i965_post_processing_internal(ctx, i965->pp_context,
3899 if (flags & I965_PP_FLAG_AVS) {
3900 struct i965_render_state *render_state = &i965->render_state;
3901 struct intel_region *dest_region = render_state->draw_region;
3903 if (out_surface_id != VA_INVALID_ID)
3904 in_surface_id = out_surface_id;
3906 status = i965_CreateSurfaces(ctx,
3908 dest_region->height,
3909 VA_RT_FORMAT_YUV420,
3912 assert(status == VA_STATUS_SUCCESS);
3913 obj_surface = SURFACE(out_surface_id);
3914 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3915 i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3916 src_surface.id = in_surface_id;
3917 src_surface.type = I965_SURFACE_TYPE_SURFACE;
3918 src_surface.flags = I965_SURFACE_FLAG_FRAME;
3919 dst_surface.id = out_surface_id;
3920 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3921 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3923 i965_post_processing_internal(ctx, i965->pp_context,
3931 if (in_surface_id != surface)
3932 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3934 *has_done_scaling = 1;
3937 _i965UnlockMutex(&i965->pp_mutex);
3940 return out_surface_id;
3944 i965_image_pl3_processing(VADriverContextP ctx,
3945 const struct i965_surface *src_surface,
3946 const VARectangle *src_rect,
3947 struct i965_surface *dst_surface,
3948 const VARectangle *dst_rect)
3950 struct i965_driver_data *i965 = i965_driver_data(ctx);
3951 struct i965_post_processing_context *pp_context = i965->pp_context;
3952 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3953 VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
3955 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3956 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3961 PP_PL3_LOAD_SAVE_N12,
3963 } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
3964 fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
3965 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3970 PP_PL3_LOAD_SAVE_PL3,
3972 } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3973 if (IS_GEN6(i965->intel.device_id))
3974 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3979 PP_PL3_LOAD_SAVE_PA,
3986 intel_batchbuffer_flush(pp_context->batch);
3992 i965_image_pl2_processing(VADriverContextP ctx,
3993 const struct i965_surface *src_surface,
3994 const VARectangle *src_rect,
3995 struct i965_surface *dst_surface,
3996 const VARectangle *dst_rect)
3998 struct i965_driver_data *i965 = i965_driver_data(ctx);
3999 struct i965_post_processing_context *pp_context = i965->pp_context;
4000 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4001 VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4003 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4004 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4009 PP_NV12_LOAD_SAVE_N12,
4011 } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4012 fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
4013 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4018 PP_NV12_LOAD_SAVE_PL3,
4020 } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
4021 if (IS_GEN6(i965->intel.device_id))
4022 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4027 PP_NV12_LOAD_SAVE_PA,
4031 intel_batchbuffer_flush(pp_context->batch);
4037 i965_image_pl1_processing(VADriverContextP ctx,
4038 const struct i965_surface *src_surface,
4039 const VARectangle *src_rect,
4040 struct i965_surface *dst_surface,
4041 const VARectangle *dst_rect)
4043 struct i965_driver_data *i965 = i965_driver_data(ctx);
4044 struct i965_post_processing_context *pp_context = i965->pp_context;
4045 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4047 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4048 i965_post_processing_internal(ctx, i965->pp_context,
4053 PP_PA_LOAD_SAVE_NV12,
4056 else if (fourcc == VA_FOURCC_YV12) {
4057 i965_post_processing_internal(ctx, i965->pp_context,
4062 PP_PA_LOAD_SAVE_PL3,
4067 return VA_STATUS_ERROR_UNKNOWN;
4070 intel_batchbuffer_flush(pp_context->batch);
4072 return VA_STATUS_SUCCESS;
4076 i965_image_processing(VADriverContextP ctx,
4077 const struct i965_surface *src_surface,
4078 const VARectangle *src_rect,
4079 struct i965_surface *dst_surface,
4080 const VARectangle *dst_rect)
4082 struct i965_driver_data *i965 = i965_driver_data(ctx);
4083 VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4086 int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4088 _i965LockMutex(&i965->pp_mutex);
4091 case VA_FOURCC('Y', 'V', '1', '2'):
4092 case VA_FOURCC('I', '4', '2', '0'):
4093 case VA_FOURCC('I', 'M', 'C', '1'):
4094 case VA_FOURCC('I', 'M', 'C', '3'):
4095 status = i965_image_pl3_processing(ctx,
4102 case VA_FOURCC('N', 'V', '1', '2'):
4103 status = i965_image_pl2_processing(ctx,
4109 case VA_FOURCC('Y', 'U', 'Y', '2'):
4110 if (IS_GEN6(i965->intel.device_id))
4111 status = i965_image_pl1_processing(ctx,
4119 status = VA_STATUS_ERROR_UNIMPLEMENTED;
4123 _i965UnlockMutex(&i965->pp_mutex);
4130 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4134 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4135 pp_context->surface_state_binding_table.bo = NULL;
4137 dri_bo_unreference(pp_context->curbe.bo);
4138 pp_context->curbe.bo = NULL;
4140 dri_bo_unreference(pp_context->sampler_state_table.bo);
4141 pp_context->sampler_state_table.bo = NULL;
4143 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4144 pp_context->sampler_state_table.bo_8x8 = NULL;
4146 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4147 pp_context->sampler_state_table.bo_8x8_uv = NULL;
4149 dri_bo_unreference(pp_context->idrt.bo);
4150 pp_context->idrt.bo = NULL;
4151 pp_context->idrt.num_interface_descriptors = 0;
4153 dri_bo_unreference(pp_context->vfe_state.bo);
4154 pp_context->vfe_state.bo = NULL;
4156 dri_bo_unreference(pp_context->stmm.bo);
4157 pp_context->stmm.bo = NULL;
4159 for (i = 0; i < NUM_PP_MODULES; i++) {
4160 struct pp_module *pp_module = &pp_context->pp_modules[i];
4162 dri_bo_unreference(pp_module->kernel.bo);
4163 pp_module->kernel.bo = NULL;
4166 free(pp_context->pp_static_parameter);
4167 free(pp_context->pp_inline_parameter);
4168 pp_context->pp_static_parameter = NULL;
4169 pp_context->pp_inline_parameter = NULL;
4173 i965_post_processing_terminate(VADriverContextP ctx)
4175 struct i965_driver_data *i965 = i965_driver_data(ctx);
4176 struct i965_post_processing_context *pp_context = i965->pp_context;
4179 i965_post_processing_context_finalize(pp_context);
4183 i965->pp_context = NULL;
4189 i965_post_processing_context_init(VADriverContextP ctx,
4190 struct i965_post_processing_context *pp_context,
4191 struct intel_batchbuffer *batch)
4193 struct i965_driver_data *i965 = i965_driver_data(ctx);
4196 pp_context->urb.size = URB_SIZE((&i965->intel));
4197 pp_context->urb.num_vfe_entries = 32;
4198 pp_context->urb.size_vfe_entry = 1; /* in 512 bits unit */
4199 pp_context->urb.num_cs_entries = 1;
4201 if (IS_GEN7(i965->intel.device_id))
4202 pp_context->urb.size_cs_entry = 4; /* in 512 bits unit */
4204 pp_context->urb.size_cs_entry = 2;
4206 pp_context->urb.vfe_start = 0;
4207 pp_context->urb.cs_start = pp_context->urb.vfe_start +
4208 pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4209 assert(pp_context->urb.cs_start +
4210 pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4212 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4213 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4214 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4216 if (IS_GEN7(i965->intel.device_id))
4217 memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4218 else if (IS_GEN6(i965->intel.device_id))
4219 memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4220 else if (IS_IRONLAKE(i965->intel.device_id))
4221 memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4223 for (i = 0; i < NUM_PP_MODULES; i++) {
4224 struct pp_module *pp_module = &pp_context->pp_modules[i];
4225 dri_bo_unreference(pp_module->kernel.bo);
4226 if (pp_module->kernel.bin && pp_module->kernel.size) {
4227 pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4228 pp_module->kernel.name,
4229 pp_module->kernel.size,
4231 assert(pp_module->kernel.bo);
4232 dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4234 pp_module->kernel.bo = NULL;
4238 /* static & inline parameters */
4239 if (IS_GEN7(i965->intel.device_id)) {
4240 pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4241 pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4243 pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4244 pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4247 pp_context->batch = batch;
4251 i965_post_processing_init(VADriverContextP ctx)
4253 struct i965_driver_data *i965 = i965_driver_data(ctx);
4254 struct i965_post_processing_context *pp_context = i965->pp_context;
4257 if (pp_context == NULL) {
4258 pp_context = calloc(1, sizeof(*pp_context));
4259 i965_post_processing_context_init(ctx, pp_context, i965->batch);
4260 i965->pp_context = pp_context;
4267 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4268 PP_NULL, /* VAProcFilterNone */
4269 PP_NV12_DN, /* VAProcFilterNoiseReduction */
4270 PP_NULL, /* VAProcFilterDeblocking */
4271 PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4272 PP_NULL, /* VAProcFilterSharpening */
4273 PP_NULL, /* VAProcFilterColorBalance */
4274 PP_NULL, /* VAProcFilterColorStandard */
4275 PP_NULL, /* VAProcFilterFrameRateConversion */
4278 static const int proc_frame_to_pp_frame[3] = {
4279 I965_SURFACE_FLAG_FRAME,
4280 I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4281 I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4285 i965_proc_picture(VADriverContextP ctx,
4287 union codec_state *codec_state,
4288 struct hw_context *hw_context)
4290 struct i965_driver_data *i965 = i965_driver_data(ctx);
4291 struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4292 struct proc_state *proc_state = &codec_state->proc;
4293 VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4294 struct object_surface *obj_surface;
4295 struct i965_surface src_surface, dst_surface;
4296 VARectangle src_rect, dst_rect;
4299 VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4300 int num_tmp_surfaces = 0;
4301 unsigned int tiling = 0, swizzle = 0;
4302 int in_width, in_height;
4304 assert(pipeline_param->surface != VA_INVALID_ID);
4305 assert(proc_state->current_render_target != VA_INVALID_ID);
4307 obj_surface = SURFACE(pipeline_param->surface);
4308 in_width = obj_surface->orig_width;
4309 in_height = obj_surface->orig_height;
4310 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4312 src_surface.id = pipeline_param->surface;
4313 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4314 src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4316 if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4317 VASurfaceID out_surface_id = VA_INVALID_ID;
4319 src_surface.id = pipeline_param->surface;
4320 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4321 src_surface.flags = I965_SURFACE_FLAG_FRAME;
4324 src_rect.width = in_width;
4325 src_rect.height = in_height;
4327 status = i965_CreateSurfaces(ctx,
4330 VA_RT_FORMAT_YUV420,
4333 assert(status == VA_STATUS_SUCCESS);
4334 tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4335 obj_surface = SURFACE(out_surface_id);
4336 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4338 dst_surface.id = out_surface_id;
4339 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4340 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4343 dst_rect.width = in_width;
4344 dst_rect.height = in_height;
4346 status = i965_image_processing(ctx,
4351 assert(status == VA_STATUS_SUCCESS);
4353 src_surface.id = out_surface_id;
4354 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4355 src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4358 if (pipeline_param->surface_region) {
4359 src_rect.x = pipeline_param->surface_region->x;
4360 src_rect.y = pipeline_param->surface_region->y;
4361 src_rect.width = pipeline_param->surface_region->width;
4362 src_rect.height = pipeline_param->surface_region->height;
4366 src_rect.width = in_width;
4367 src_rect.height = in_height;
4370 if (pipeline_param->output_region) {
4371 dst_rect.x = pipeline_param->output_region->x;
4372 dst_rect.y = pipeline_param->output_region->y;
4373 dst_rect.width = pipeline_param->output_region->width;
4374 dst_rect.height = pipeline_param->output_region->height;
4378 dst_rect.width = in_width;
4379 dst_rect.height = in_height;
4382 obj_surface = SURFACE(proc_state->current_render_target);
4383 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4384 i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4386 for (i = 0; i < pipeline_param->num_filters; i++) {
4387 struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4388 VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4389 VAProcFilterType filter_type = filter_param->type;
4390 VASurfaceID out_surface_id = VA_INVALID_ID;
4391 int kernel_index = procfilter_to_pp_flag[filter_type];
4393 if (kernel_index != PP_NULL &&
4394 proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4395 status = i965_CreateSurfaces(ctx,
4398 VA_RT_FORMAT_YUV420,
4401 assert(status == VA_STATUS_SUCCESS);
4402 tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4403 obj_surface = SURFACE(out_surface_id);
4404 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4405 dst_surface.id = out_surface_id;
4406 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4407 status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4415 if (status == VA_STATUS_SUCCESS) {
4416 src_surface.id = dst_surface.id;
4417 src_surface.type = dst_surface.type;
4418 src_surface.flags = dst_surface.flags;
4423 dst_surface.id = proc_state->current_render_target;
4424 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4426 if (src_rect.width == dst_rect.width &&
4427 src_rect.height == dst_rect.height) {
4428 i965_post_processing_internal(ctx, &proc_context->pp_context,
4433 PP_NV12_LOAD_SAVE_N12,
4437 i965_post_processing_internal(ctx, &proc_context->pp_context,
4442 (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4443 PP_NV12_AVS : PP_NV12_SCALING,
4447 if (num_tmp_surfaces)
4448 i965_DestroySurfaces(ctx,
4452 intel_batchbuffer_flush(hw_context->batch);
4456 i965_proc_context_destroy(void *hw_context)
4458 struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4460 i965_post_processing_context_finalize(&proc_context->pp_context);
4461 intel_batchbuffer_free(proc_context->base.batch);
4466 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4468 struct intel_driver_data *intel = intel_driver_data(ctx);
4469 struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4471 proc_context->base.destroy = i965_proc_context_destroy;
4472 proc_context->base.run = i965_proc_picture;
4473 proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4474 i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4476 return (struct hw_context *)proc_context;