src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  95                                    const struct i965_surface *src_surface,
  96                                    const VARectangle *src_rect,
  97                                    struct i965_surface *dst_surface,
  98                                    const VARectangle *dst_rect,
  99                                    void *filter_param);
 100 static VAStatus pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 101                                        const struct i965_surface *src_surface,
 102                                        const VARectangle *src_rect,
 103                                        struct i965_surface *dst_surface,
 104                                        const VARectangle *dst_rect,
 105                                        void *filter_param);
 106 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 107                                            const struct i965_surface *src_surface,
 108                                            const VARectangle *src_rect,
 109                                            struct i965_surface *dst_surface,
 110                                            const VARectangle *dst_rect,
 111                                            void *filter_param);
 112 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 113                                                 const struct i965_surface *src_surface,
 114                                                 const VARectangle *src_rect,
 115                                                 struct i965_surface *dst_surface,
 116                                                 const VARectangle *dst_rect,
 117                                                 void *filter_param);
 118 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                         const struct i965_surface *src_surface,
 120                                         const VARectangle *src_rect,
 121                                         struct i965_surface *dst_surface,
 122                                         const VARectangle *dst_rect,
 123                                         void *filter_param);
 124 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                       const struct i965_surface *src_surface,
 126                                       const VARectangle *src_rect,
 127                                       struct i965_surface *dst_surface,
 128                                       const VARectangle *dst_rect,
 129                                       void *filter_param);
 130
 131 static struct pp_module pp_modules_gen5[] = {
 132     {
 133         {
 134             "NULL module (for testing)",
 135             PP_NULL,
 136             pp_null_gen5,
 137             sizeof(pp_null_gen5),
 138             NULL,
 139         },
 140
 141         pp_null_initialize,
 142     },
 143
 144     {
 145         {
 146             "NV12_NV12",
 147             PP_NV12_LOAD_SAVE_N12,
 148             pp_nv12_load_save_nv12_gen5,
 149             sizeof(pp_nv12_load_save_nv12_gen5),
 150             NULL,
 151         },
 152
 153         pp_plx_load_save_plx_initialize,
 154     },
 155
 156     {
 157         {
 158             "NV12_PL3",
 159             PP_NV12_LOAD_SAVE_PL3,
 160             pp_nv12_load_save_pl3_gen5,
 161             sizeof(pp_nv12_load_save_pl3_gen5),
 162             NULL,
 163         },
 164
 165         pp_plx_load_save_plx_initialize,
 166     },
 167
 168     {
 169         {
 170             "PL3_NV12",
 171             PP_PL3_LOAD_SAVE_N12,
 172             pp_pl3_load_save_nv12_gen5,
 173             sizeof(pp_pl3_load_save_nv12_gen5),
 174             NULL,
 175         },
 176
 177         pp_plx_load_save_plx_initialize,
 178     },
 179
 180     {
 181         {
 182             "PL3_PL3",
 183             PP_PL3_LOAD_SAVE_N12,
 184             pp_pl3_load_save_pl3_gen5,
 185             sizeof(pp_pl3_load_save_pl3_gen5),
 186             NULL,
 187         },
 188
 189         pp_plx_load_save_plx_initialize
 190     },
 191
 192     {
 193         {
 194             "NV12 Scaling module",
 195             PP_NV12_SCALING,
 196             pp_nv12_scaling_gen5,
 197             sizeof(pp_nv12_scaling_gen5),
 198             NULL,
 199         },
 200
 201         pp_nv12_scaling_initialize,
 202     },
 203
 204     {
 205         {
 206             "NV12 AVS module",
 207             PP_NV12_AVS,
 208             pp_nv12_avs_gen5,
 209             sizeof(pp_nv12_avs_gen5),
 210             NULL,
 211         },
 212
 213         pp_nv12_avs_initialize,
 214     },
 215
 216     {
 217         {
 218             "NV12 DNDI module",
 219             PP_NV12_DNDI,
 220             pp_nv12_dndi_gen5,
 221             sizeof(pp_nv12_dndi_gen5),
 222             NULL,
 223         },
 224
 225         pp_nv12_dndi_initialize,
 226     },
 227
 228     {
 229         {
 230             "NV12 DN module",
 231             PP_NV12_DN,
 232             pp_nv12_dn_gen5,
 233             sizeof(pp_nv12_dn_gen5),
 234             NULL,
 235         },
 236
 237         pp_nv12_dn_initialize,
 238     },
 239 };
 240
 241 static const uint32_t pp_null_gen6[][4] = {
 242 #include "shaders/post_processing/gen5_6/null.g6b"
 243 };
 244
 245 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 246 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 247 };
 248
 249 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 250 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 251 };
 252
 253 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 254 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 255 };
 256
 257 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 258 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 259 };
 260
 261 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 262 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g6b"
 263 };
 264
 265 static const uint32_t pp_nv12_avs_gen6[][4] = {
 266 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 267 };
 268
 269 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 270 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 271 };
 272
 273 static const uint32_t pp_nv12_dn_gen6[][4] = {
 274 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 275 };
 276
 277 static struct pp_module pp_modules_gen6[] = {
 278     {
 279         {
 280             "NULL module (for testing)",
 281             PP_NULL,
 282             pp_null_gen6,
 283             sizeof(pp_null_gen6),
 284             NULL,
 285         },
 286
 287         pp_null_initialize,
 288     },
 289
 290     {
 291         {
 292             "NV12_NV12",
 293             PP_NV12_LOAD_SAVE_N12,
 294             pp_nv12_load_save_nv12_gen6,
 295             sizeof(pp_nv12_load_save_nv12_gen6),
 296             NULL,
 297         },
 298
 299         pp_plx_load_save_plx_initialize,
 300     },
 301
 302     {
 303         {
 304             "NV12_PL3",
 305             PP_NV12_LOAD_SAVE_PL3,
 306             pp_nv12_load_save_pl3_gen6,
 307             sizeof(pp_nv12_load_save_pl3_gen6),
 308             NULL,
 309         },
 310
 311         pp_plx_load_save_plx_initialize,
 312     },
 313
 314     {
 315         {
 316             "PL3_NV12",
 317             PP_PL3_LOAD_SAVE_N12,
 318             pp_pl3_load_save_nv12_gen6,
 319             sizeof(pp_pl3_load_save_nv12_gen6),
 320             NULL,
 321         },
 322
 323         pp_plx_load_save_plx_initialize,
 324     },
 325
 326     {
 327         {
 328             "PL3_PL3",
 329             PP_PL3_LOAD_SAVE_N12,
 330             pp_pl3_load_save_pl3_gen6,
 331             sizeof(pp_pl3_load_save_pl3_gen6),
 332             NULL,
 333         },
 334
 335         pp_plx_load_save_plx_initialize,
 336     },
 337
 338     {
 339         {
 340             "NV12 Scaling module",
 341             PP_NV12_SCALING,
 342             pp_nv12_scaling_gen6,
 343             sizeof(pp_nv12_scaling_gen6),
 344             NULL,
 345         },
 346
 347         pp_nv12_scaling_initialize,
 348     },
 349
 350     {
 351         {
 352             "NV12 AVS module",
 353             PP_NV12_AVS,
 354             pp_nv12_avs_gen6,
 355             sizeof(pp_nv12_avs_gen6),
 356             NULL,
 357         },
 358
 359         pp_nv12_avs_initialize,
 360     },
 361
 362     {
 363         {
 364             "NV12 DNDI module",
 365             PP_NV12_DNDI,
 366             pp_nv12_dndi_gen6,
 367             sizeof(pp_nv12_dndi_gen6),
 368             NULL,
 369         },
 370
 371         pp_nv12_dndi_initialize,
 372     },
 373
 374     {
 375         {
 376             "NV12 DN module",
 377             PP_NV12_DN,
 378             pp_nv12_dn_gen6,
 379             sizeof(pp_nv12_dn_gen6),
 380             NULL,
 381         },
 382
 383         pp_nv12_dn_initialize,
 384     },
 385 };
 386
 387 static const uint32_t pp_null_gen7[][4] = {
 388 };
 389
 390 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 391 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 392 };
 393
 394 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 395 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 396 };
 397
 398 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 399 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 400 };
 401
 402 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 403 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 404 };
 405
 406 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 407 #include "shaders/post_processing/gen7/avs.g7b"
 408 };
 409
 410 static const uint32_t pp_nv12_avs_gen7[][4] = {
 411 #include "shaders/post_processing/gen7/avs.g7b"
 412 };
 413
 414 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 415 #include "shaders/post_processing/gen7/dndi.g7b"
 416 };
 417
 418 static const uint32_t pp_nv12_dn_gen7[][4] = {
 419 };
 420
 421 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 422                                            const struct i965_surface *src_surface,
 423                                            const VARectangle *src_rect,
 424                                            struct i965_surface *dst_surface,
 425                                            const VARectangle *dst_rect,
 426                                            void *filter_param);
 427 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 428                                              const struct i965_surface *src_surface,
 429                                              const VARectangle *src_rect,
 430                                              struct i965_surface *dst_surface,
 431                                              const VARectangle *dst_rect,
 432                                              void *filter_param);
 433 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 434                                            const struct i965_surface *src_surface,
 435                                            const VARectangle *src_rect,
 436                                            struct i965_surface *dst_surface,
 437                                            const VARectangle *dst_rect,
 438                                            void *filter_param);
 439
 440 static struct pp_module pp_modules_gen7[] = {
 441     {
 442         {
 443             "NULL module (for testing)",
 444             PP_NULL,
 445             pp_null_gen7,
 446             sizeof(pp_null_gen7),
 447             NULL,
 448         },
 449
 450         pp_null_initialize,
 451     },
 452
 453     {
 454         {
 455             "NV12_NV12",
 456             PP_NV12_LOAD_SAVE_N12,
 457             pp_nv12_load_save_nv12_gen7,
 458             sizeof(pp_nv12_load_save_nv12_gen7),
 459             NULL,
 460         },
 461
 462         gen7_pp_plx_avs_initialize,
 463     },
 464
 465     {
 466         {
 467             "NV12_PL3",
 468             PP_NV12_LOAD_SAVE_PL3,
 469             pp_nv12_load_save_pl3_gen7,
 470             sizeof(pp_nv12_load_save_pl3_gen7),
 471             NULL,
 472         },
 473
 474         gen7_pp_plx_avs_initialize,
 475     },
 476
 477     {
 478         {
 479             "PL3_NV12",
 480             PP_PL3_LOAD_SAVE_N12,
 481             pp_pl3_load_save_nv12_gen7,
 482             sizeof(pp_pl3_load_save_nv12_gen7),
 483             NULL,
 484         },
 485
 486         gen7_pp_plx_avs_initialize,
 487     },
 488
 489     {
 490         {
 491             "PL3_PL3",
 492             PP_PL3_LOAD_SAVE_N12,
 493             pp_pl3_load_save_pl3_gen7,
 494             sizeof(pp_pl3_load_save_pl3_gen7),
 495             NULL,
 496         },
 497
 498         gen7_pp_plx_avs_initialize,
 499     },
 500
 501     {
 502         {
 503             "NV12 Scaling module",
 504             PP_NV12_SCALING,
 505             pp_nv12_scaling_gen7,
 506             sizeof(pp_nv12_scaling_gen7),
 507             NULL,
 508         },
 509
 510         gen7_pp_plx_avs_initialize,
 511     },
 512
 513     {
 514         {
 515             "NV12 AVS module",
 516             PP_NV12_AVS,
 517             pp_nv12_avs_gen7,
 518             sizeof(pp_nv12_avs_gen7),
 519             NULL,
 520         },
 521
 522         gen7_pp_plx_avs_initialize,
 523     },
 524
 525     {
 526         {
 527             "NV12 DNDI module",
 528             PP_NV12_DNDI,
 529             pp_nv12_dndi_gen7,
 530             sizeof(pp_nv12_dndi_gen7),
 531             NULL,
 532         },
 533
 534         gen7_pp_nv12_dndi_initialize,
 535     },
 536
 537     {
 538         {
 539             "NV12 DN module",
 540             PP_NV12_DN,
 541             pp_nv12_dn_gen7,
 542             sizeof(pp_nv12_dn_gen7),
 543             NULL,
 544         },
 545
 546         gen7_pp_nv12_dn_initialize,
 547     },
 548 };
 549
 550 static int
 551 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 552 {
 553     struct i965_driver_data *i965 = i965_driver_data(ctx);
 554     int fourcc;
 555
 556     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 557         struct object_image *obj_image = IMAGE(surface->id);
 558         fourcc = obj_image->image.format.fourcc;
 559     } else {
 560         struct object_surface *obj_surface = SURFACE(surface->id);
 561         fourcc = obj_surface->fourcc;
 562     }
 563
 564     return fourcc;
 565 }
 566
 567 static void
 568 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 569 {
 570     switch (tiling) {
 571     case I915_TILING_NONE:
 572         ss->ss3.tiled_surface = 0;
 573         ss->ss3.tile_walk = 0;
 574         break;
 575     case I915_TILING_X:
 576         ss->ss3.tiled_surface = 1;
 577         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 578         break;
 579     case I915_TILING_Y:
 580         ss->ss3.tiled_surface = 1;
 581         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 582         break;
 583     }
 584 }
 585
 586 static void
 587 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 588 {
 589     switch (tiling) {
 590     case I915_TILING_NONE:
 591         ss->ss2.tiled_surface = 0;
 592         ss->ss2.tile_walk = 0;
 593         break;
 594     case I915_TILING_X:
 595         ss->ss2.tiled_surface = 1;
 596         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 597         break;
 598     case I915_TILING_Y:
 599         ss->ss2.tiled_surface = 1;
 600         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 601         break;
 602     }
 603 }
 604
 605 static void
 606 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 607 {
 608     switch (tiling) {
 609     case I915_TILING_NONE:
 610         ss->ss0.tiled_surface = 0;
 611         ss->ss0.tile_walk = 0;
 612         break;
 613     case I915_TILING_X:
 614         ss->ss0.tiled_surface = 1;
 615         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 616         break;
 617     case I915_TILING_Y:
 618         ss->ss0.tiled_surface = 1;
 619         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 620         break;
 621     }
 622 }
 623
 624 static void
 625 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 626 {
 627     switch (tiling) {
 628     case I915_TILING_NONE:
 629         ss->ss2.tiled_surface = 0;
 630         ss->ss2.tile_walk = 0;
 631         break;
 632     case I915_TILING_X:
 633         ss->ss2.tiled_surface = 1;
 634         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 635         break;
 636     case I915_TILING_Y:
 637         ss->ss2.tiled_surface = 1;
 638         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 639         break;
 640     }
 641 }
 642
 643 static void
 644 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 645 {
 646     struct i965_interface_descriptor *desc;
 647     dri_bo *bo;
 648     int pp_index = pp_context->current_pp;
 649
 650     bo = pp_context->idrt.bo;
 651     dri_bo_map(bo, 1);
 652     assert(bo->virtual);
 653     desc = bo->virtual;
 654     memset(desc, 0, sizeof(*desc));
 655     desc->desc0.grf_reg_blocks = 10;
 656     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 657     desc->desc1.const_urb_entry_read_offset = 0;
 658     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 659     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 660     desc->desc2.sampler_count = 0;
 661     desc->desc3.binding_table_entry_count = 0;
 662     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 663
 664     dri_bo_emit_reloc(bo,
 665                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 666                       desc->desc0.grf_reg_blocks,
 667                       offsetof(struct i965_interface_descriptor, desc0),
 668                       pp_context->pp_modules[pp_index].kernel.bo);
 669
 670     dri_bo_emit_reloc(bo,
 671                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 672                       desc->desc2.sampler_count << 2,
 673                       offsetof(struct i965_interface_descriptor, desc2),
 674                       pp_context->sampler_state_table.bo);
 675
 676     dri_bo_unmap(bo);
 677     pp_context->idrt.num_interface_descriptors++;
 678 }
 679
 680 static void
 681 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 682 {
 683     struct i965_vfe_state *vfe_state;
 684     dri_bo *bo;
 685
 686     bo = pp_context->vfe_state.bo;
 687     dri_bo_map(bo, 1);
 688     assert(bo->virtual);
 689     vfe_state = bo->virtual;
 690     memset(vfe_state, 0, sizeof(*vfe_state));
 691     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 692     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 693     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 694     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 695     vfe_state->vfe1.children_present = 0;
 696     vfe_state->vfe2.interface_descriptor_base =
 697         pp_context->idrt.bo->offset >> 4; /* reloc */
 698     dri_bo_emit_reloc(bo,
 699                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 700                       0,
 701                       offsetof(struct i965_vfe_state, vfe2),
 702                       pp_context->idrt.bo);
 703     dri_bo_unmap(bo);
 704 }
 705
 706 static void
 707 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 708 {
 709     unsigned char *constant_buffer;
 710     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 711
 712     assert(sizeof(*pp_static_parameter) == 128);
 713     dri_bo_map(pp_context->curbe.bo, 1);
 714     assert(pp_context->curbe.bo->virtual);
 715     constant_buffer = pp_context->curbe.bo->virtual;
 716     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 717     dri_bo_unmap(pp_context->curbe.bo);
 718 }
 719
 720 static void
 721 ironlake_pp_states_setup(VADriverContextP ctx,
 722                          struct i965_post_processing_context *pp_context)
 723 {
 724     ironlake_pp_interface_descriptor_table(pp_context);
 725     ironlake_pp_vfe_state(pp_context);
 726     ironlake_pp_upload_constants(pp_context);
 727 }
 728
 729 static void
 730 ironlake_pp_pipeline_select(VADriverContextP ctx,
 731                             struct i965_post_processing_context *pp_context)
 732 {
 733     struct intel_batchbuffer *batch = pp_context->batch;
 734
 735     BEGIN_BATCH(batch, 1);
 736     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 737     ADVANCE_BATCH(batch);
 738 }
 739
 740 static void
 741 ironlake_pp_urb_layout(VADriverContextP ctx,
 742                        struct i965_post_processing_context *pp_context)
 743 {
 744     struct intel_batchbuffer *batch = pp_context->batch;
 745     unsigned int vfe_fence, cs_fence;
 746
 747     vfe_fence = pp_context->urb.cs_start;
 748     cs_fence = pp_context->urb.size;
 749
 750     BEGIN_BATCH(batch, 3);
 751     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 752     OUT_BATCH(batch, 0);
 753     OUT_BATCH(batch,
 754               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 755               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 756     ADVANCE_BATCH(batch);
 757 }
 758
 759 static void
 760 ironlake_pp_state_base_address(VADriverContextP ctx,
 761                                struct i965_post_processing_context *pp_context)
 762 {
 763     struct intel_batchbuffer *batch = pp_context->batch;
 764
 765     BEGIN_BATCH(batch, 8);
 766     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 767     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 768     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 769     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 770     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 771     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 772     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 773     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 774     ADVANCE_BATCH(batch);
 775 }
 776
 777 static void
 778 ironlake_pp_state_pointers(VADriverContextP ctx,
 779                            struct i965_post_processing_context *pp_context)
 780 {
 781     struct intel_batchbuffer *batch = pp_context->batch;
 782
 783     BEGIN_BATCH(batch, 3);
 784     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 785     OUT_BATCH(batch, 0);
 786     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 787     ADVANCE_BATCH(batch);
 788 }
 789
 790 static void
 791 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 792                           struct i965_post_processing_context *pp_context)
 793 {
 794     struct intel_batchbuffer *batch = pp_context->batch;
 795
 796     BEGIN_BATCH(batch, 2);
 797     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 798     OUT_BATCH(batch,
 799               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 800               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 801     ADVANCE_BATCH(batch);
 802 }
 803
 804 static void
 805 ironlake_pp_constant_buffer(VADriverContextP ctx,
 806                             struct i965_post_processing_context *pp_context)
 807 {
 808     struct intel_batchbuffer *batch = pp_context->batch;
 809
 810     BEGIN_BATCH(batch, 2);
 811     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 812     OUT_RELOC(batch, pp_context->curbe.bo,
 813               I915_GEM_DOMAIN_INSTRUCTION, 0,
 814               pp_context->urb.size_cs_entry - 1);
 815     ADVANCE_BATCH(batch);
 816 }
 817
 818 static void
 819 ironlake_pp_object_walker(VADriverContextP ctx,
 820                           struct i965_post_processing_context *pp_context)
 821 {
 822     struct intel_batchbuffer *batch = pp_context->batch;
 823     int x, x_steps, y, y_steps;
 824     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
 825
 826     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
 827     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
 828
 829     for (y = 0; y < y_steps; y++) {
 830         for (x = 0; x < x_steps; x++) {
 831             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
 832                 BEGIN_BATCH(batch, 20);
 833                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
 834                 OUT_BATCH(batch, 0);
 835                 OUT_BATCH(batch, 0); /* no indirect data */
 836                 OUT_BATCH(batch, 0);
 837
 838                 /* inline data grf 5-6 */
 839                 assert(sizeof(*pp_inline_parameter) == 64);
 840                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
 841
 842                 ADVANCE_BATCH(batch);
 843             }
 844         }
 845     }
 846 }
 847
 848 static void
 849 ironlake_pp_pipeline_setup(VADriverContextP ctx,
 850                            struct i965_post_processing_context *pp_context)
 851 {
 852     struct intel_batchbuffer *batch = pp_context->batch;
 853
 854     intel_batchbuffer_start_atomic(batch, 0x1000);
 855     intel_batchbuffer_emit_mi_flush(batch);
 856     ironlake_pp_pipeline_select(ctx, pp_context);
 857     ironlake_pp_state_base_address(ctx, pp_context);
 858     ironlake_pp_state_pointers(ctx, pp_context);
 859     ironlake_pp_urb_layout(ctx, pp_context);
 860     ironlake_pp_cs_urb_layout(ctx, pp_context);
 861     ironlake_pp_constant_buffer(ctx, pp_context);
 862     ironlake_pp_object_walker(ctx, pp_context);
 863     intel_batchbuffer_end_atomic(batch);
 864 }
 865
 866 static void
 867 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 868                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 869                           int width, int height, int pitch, int format,
 870                           int index, int is_target)
 871 {
 872     struct i965_surface_state *ss;
 873     dri_bo *ss_bo;
 874     unsigned int tiling;
 875     unsigned int swizzle;
 876
 877     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 878     ss_bo = pp_context->surface_state_binding_table.bo;
 879     assert(ss_bo);
 880
 881     dri_bo_map(ss_bo, True);
 882     assert(ss_bo->virtual);
 883     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 884     memset(ss, 0, sizeof(*ss));
 885     ss->ss0.surface_type = I965_SURFACE_2D;
 886     ss->ss0.surface_format = format;
 887     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 888     ss->ss2.width = width - 1;
 889     ss->ss2.height = height - 1;
 890     ss->ss3.pitch = pitch - 1;
 891     pp_set_surface_tiling(ss, tiling);
 892     dri_bo_emit_reloc(ss_bo,
 893                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 894                       surf_bo_offset,
 895                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 896                       surf_bo);
 897     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 898     dri_bo_unmap(ss_bo);
 899 }
 900
 901 static void
 902 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 903                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 904                            int width, int height, int wpitch,
 905                            int xoffset, int yoffset,
 906                            int format, int interleave_chroma,
 907                            int index)
 908 {
 909     struct i965_surface_state2 *ss2;
 910     dri_bo *ss2_bo;
 911     unsigned int tiling;
 912     unsigned int swizzle;
 913
 914     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 915     ss2_bo = pp_context->surface_state_binding_table.bo;
 916     assert(ss2_bo);
 917
 918     dri_bo_map(ss2_bo, True);
 919     assert(ss2_bo->virtual);
 920     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 921     memset(ss2, 0, sizeof(*ss2));
 922     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 923     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 924     ss2->ss1.width = width - 1;
 925     ss2->ss1.height = height - 1;
 926     ss2->ss2.pitch = wpitch - 1;
 927     ss2->ss2.interleave_chroma = interleave_chroma;
 928     ss2->ss2.surface_format = format;
 929     ss2->ss3.x_offset_for_cb = xoffset;
 930     ss2->ss3.y_offset_for_cb = yoffset;
 931     pp_set_surface2_tiling(ss2, tiling);
 932     dri_bo_emit_reloc(ss2_bo,
 933                       I915_GEM_DOMAIN_RENDER, 0,
 934                       surf_bo_offset,
 935                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
 936                       surf_bo);
 937     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 938     dri_bo_unmap(ss2_bo);
 939 }
 940
 941 static void
 942 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 943                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 944                           int width, int height, int pitch, int format,
 945                           int index, int is_target)
 946 {
 947     struct gen7_surface_state *ss;
 948     dri_bo *ss_bo;
 949     unsigned int tiling;
 950     unsigned int swizzle;
 951
 952     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 953     ss_bo = pp_context->surface_state_binding_table.bo;
 954     assert(ss_bo);
 955
 956     dri_bo_map(ss_bo, True);
 957     assert(ss_bo->virtual);
 958     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 959     memset(ss, 0, sizeof(*ss));
 960     ss->ss0.surface_type = I965_SURFACE_2D;
 961     ss->ss0.surface_format = format;
 962     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 963     ss->ss2.width = width - 1;
 964     ss->ss2.height = height - 1;
 965     ss->ss3.pitch = pitch - 1;
 966     gen7_pp_set_surface_tiling(ss, tiling);
 967     dri_bo_emit_reloc(ss_bo,
 968                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 969                       surf_bo_offset,
 970                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 971                       surf_bo);
 972     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 973     dri_bo_unmap(ss_bo);
 974 }
 975
 976 static void
 977 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 978                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 979                            int width, int height, int wpitch,
 980                            int xoffset, int yoffset,
 981                            int format, int interleave_chroma,
 982                            int index)
 983 {
 984     struct gen7_surface_state2 *ss2;
 985     dri_bo *ss2_bo;
 986     unsigned int tiling;
 987     unsigned int swizzle;
 988
 989     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 990     ss2_bo = pp_context->surface_state_binding_table.bo;
 991     assert(ss2_bo);
 992
 993     dri_bo_map(ss2_bo, True);
 994     assert(ss2_bo->virtual);
 995     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 996     memset(ss2, 0, sizeof(*ss2));
 997     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 998     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 999     ss2->ss1.width = width - 1;
1000     ss2->ss1.height = height - 1;
1001     ss2->ss2.pitch = wpitch - 1;
1002     ss2->ss2.interleave_chroma = interleave_chroma;
1003     ss2->ss2.surface_format = format;
1004     ss2->ss3.x_offset_for_cb = xoffset;
1005     ss2->ss3.y_offset_for_cb = yoffset;
1006     gen7_pp_set_surface2_tiling(ss2, tiling);
1007     dri_bo_emit_reloc(ss2_bo,
1008                       I915_GEM_DOMAIN_RENDER, 0,
1009                       surf_bo_offset,
1010                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1011                       surf_bo);
1012     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1013     dri_bo_unmap(ss2_bo);
1014 }
1015
1016 static void
1017 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1018                                 const struct i965_surface *surface,
1019                                 int base_index, int is_target,
1020                                 int *width, int *height, int *pitch, int *offset)
1021 {
1022     struct i965_driver_data *i965 = i965_driver_data(ctx);
1023     struct object_surface *obj_surface;
1024     struct object_image *obj_image;
1025     dri_bo *bo;
1026     int fourcc = pp_get_surface_fourcc(ctx, surface);
1027     const int Y = 0;
1028     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1029     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1030     const int UV = 1;
1031     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1032
1033     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1034         obj_surface = SURFACE(surface->id);
1035         bo = obj_surface->bo;
1036         width[0] = obj_surface->orig_width;
1037         height[0] = obj_surface->orig_height;
1038         pitch[0] = obj_surface->width;
1039         offset[0] = 0;
1040
1041         if (interleaved_uv) {
1042             width[1] = obj_surface->orig_width;
1043             height[1] = obj_surface->orig_height / 2;
1044             pitch[1] = obj_surface->width;
1045             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1046         } else {
1047             width[1] = obj_surface->orig_width / 2;
1048             height[1] = obj_surface->orig_height / 2;
1049             pitch[1] = obj_surface->width / 2;
1050             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1051             width[2] = obj_surface->orig_width / 2;
1052             height[2] = obj_surface->orig_height / 2;
1053             pitch[2] = obj_surface->width / 2;
1054             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1055         }
1056     } else {
1057         obj_image = IMAGE(surface->id);
1058         bo = obj_image->bo;
1059         width[0] = obj_image->image.width;
1060         height[0] = obj_image->image.height;
1061         pitch[0] = obj_image->image.pitches[0];
1062         offset[0] = obj_image->image.offsets[0];
1063
1064         if (interleaved_uv) {
1065             width[1] = obj_image->image.width;
1066             height[1] = obj_image->image.height / 2;
1067             pitch[1] = obj_image->image.pitches[1];
1068             offset[1] = obj_image->image.offsets[1];
1069         } else {
1070             width[1] = obj_image->image.width / 2;
1071             height[1] = obj_image->image.height / 2;
1072             pitch[1] = obj_image->image.pitches[1];
1073             offset[1] = obj_image->image.offsets[1];
1074             width[2] = obj_image->image.width / 2;
1075             height[2] = obj_image->image.height / 2;
1076             pitch[2] = obj_image->image.pitches[2];
1077             offset[2] = obj_image->image.offsets[2];
1078         }
1079     }
1080
1081     /* Y surface */
1082     i965_pp_set_surface_state(ctx, pp_context,
1083                               bo, offset[Y],
1084                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1085                               base_index, is_target);
1086
1087     if (interleaved_uv) {
1088         i965_pp_set_surface_state(ctx, pp_context,
1089                                   bo, offset[UV],
1090                                   width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1091                                   base_index + 1, is_target);
1092     } else {
1093         /* U surface */
1094         i965_pp_set_surface_state(ctx, pp_context,
1095                                   bo, offset[U],
1096                                   width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1097                                   base_index + 1, is_target);
1098
1099         /* V surface */
1100         i965_pp_set_surface_state(ctx, pp_context,
1101                                   bo, offset[V],
1102                                   width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1103                                   base_index + 2, is_target);
1104     }
1105
1106 }
1107
1108 static void
1109 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1110                                      const struct i965_surface *surface,
1111                                      int base_index, int is_target,
1112                                      int *width, int *height, int *pitch, int *offset)
1113 {
1114     struct i965_driver_data *i965 = i965_driver_data(ctx);
1115     struct object_surface *obj_surface;
1116     struct object_image *obj_image;
1117     dri_bo *bo;
1118     int fourcc = pp_get_surface_fourcc(ctx, surface);
1119     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1120                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1121     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1122                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1123     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1124
1125     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1126         obj_surface = SURFACE(surface->id);
1127         bo = obj_surface->bo;
1128         width[0] = obj_surface->orig_width;
1129         height[0] = obj_surface->orig_height;
1130         pitch[0] = obj_surface->width;
1131         offset[0] = 0;
1132
1133         width[1] = obj_surface->cb_cr_width;
1134         height[1] = obj_surface->cb_cr_height;
1135         pitch[1] = obj_surface->cb_cr_pitch;
1136         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1137
1138         width[2] = obj_surface->cb_cr_width;
1139         height[2] = obj_surface->cb_cr_height;
1140         pitch[2] = obj_surface->cb_cr_pitch;
1141         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1142     } else {
1143         obj_image = IMAGE(surface->id);
1144         bo = obj_image->bo;
1145         width[0] = obj_image->image.width;
1146         height[0] = obj_image->image.height;
1147         pitch[0] = obj_image->image.pitches[0];
1148         offset[0] = obj_image->image.offsets[0];
1149
1150         if (interleaved_uv) {
1151             width[1] = obj_image->image.width;
1152             height[1] = obj_image->image.height / 2;
1153             pitch[1] = obj_image->image.pitches[1];
1154             offset[1] = obj_image->image.offsets[1];
1155         } else {
1156             width[1] = obj_image->image.width / 2;
1157             height[1] = obj_image->image.height / 2;
1158             pitch[1] = obj_image->image.pitches[U];
1159             offset[1] = obj_image->image.offsets[U];
1160             width[2] = obj_image->image.width / 2;
1161             height[2] = obj_image->image.height / 2;
1162             pitch[2] = obj_image->image.pitches[V];
1163             offset[2] = obj_image->image.offsets[V];
1164         }
1165     }
1166
1167     if (is_target) {
1168         gen7_pp_set_surface_state(ctx, pp_context,
1169                                   bo, 0,
1170                                   width[0] / 4, height[0], pitch[0],
1171                                   I965_SURFACEFORMAT_R8_SINT,
1172                                   base_index, 1);
1173
1174         if (interleaved_uv) {
1175             gen7_pp_set_surface_state(ctx, pp_context,
1176                                       bo, offset[1],
1177                                       width[1] / 2, height[1], pitch[1],
1178                                       I965_SURFACEFORMAT_R8G8_SINT,
1179                                       base_index + 1, 1);
1180         } else {
1181             gen7_pp_set_surface_state(ctx, pp_context,
1182                                       bo, offset[1],
1183                                       width[1] / 4, height[1], pitch[1],
1184                                       I965_SURFACEFORMAT_R8_SINT,
1185                                       base_index + 1, 1);
1186             gen7_pp_set_surface_state(ctx, pp_context,
1187                                       bo, offset[2],
1188                                       width[2] / 4, height[2], pitch[2],
1189                                       I965_SURFACEFORMAT_R8_SINT,
1190                                       base_index + 2, 1);
1191         }
1192     } else {
1193         gen7_pp_set_surface2_state(ctx, pp_context,
1194                                    bo, offset[0],
1195                                    width[0], height[0], pitch[0],
1196                                    0, 0,
1197                                    SURFACE_FORMAT_Y8_UNORM, 0,
1198                                    base_index);
1199
1200         if (interleaved_uv) {
1201             gen7_pp_set_surface2_state(ctx, pp_context,
1202                                        bo, offset[1],
1203                                        width[1], height[1], pitch[1],
1204                                        0, 0,
1205                                        SURFACE_FORMAT_R8B8_UNORM, 0,
1206                                        base_index + 1);
1207         } else {
1208             gen7_pp_set_surface2_state(ctx, pp_context,
1209                                        bo, offset[1],
1210                                        width[1], height[1], pitch[1],
1211                                        0, 0,
1212                                        SURFACE_FORMAT_R8_UNORM, 0,
1213                                        base_index + 1);
1214             gen7_pp_set_surface2_state(ctx, pp_context,
1215                                        bo, offset[2],
1216                                        width[2], height[2], pitch[2],
1217                                        0, 0,
1218                                        SURFACE_FORMAT_R8_UNORM, 0,
1219                                        base_index + 2);
1220         }
1221     }
1222 }
1223
1224 static int
1225 pp_null_x_steps(void *private_context)
1226 {
1227     return 1;
1228 }
1229
1230 static int
1231 pp_null_y_steps(void *private_context)
1232 {
1233     return 1;
1234 }
1235
1236 static int
1237 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1238 {
1239     return 0;
1240 }
1241
1242 static VAStatus
1243 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1244                    const struct i965_surface *src_surface,
1245                    const VARectangle *src_rect,
1246                    struct i965_surface *dst_surface,
1247                    const VARectangle *dst_rect,
1248                    void *filter_param)
1249 {
1250     /* private function & data */
1251     pp_context->pp_x_steps = pp_null_x_steps;
1252     pp_context->pp_y_steps = pp_null_y_steps;
1253     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1254
1255     dst_surface->flags = src_surface->flags;
1256
1257     return VA_STATUS_SUCCESS;
1258 }
1259
1260 static int
1261 pp_load_save_x_steps(void *private_context)
1262 {
1263     return 1;
1264 }
1265
1266 static int
1267 pp_load_save_y_steps(void *private_context)
1268 {
1269     struct pp_load_save_context *pp_load_save_context = private_context;
1270
1271     return pp_load_save_context->dest_h / 8;
1272 }
1273
1274 static int
1275 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1276 {
1277     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1278
1279     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1280     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1281     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1282     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1283
1284     return 0;
1285 }
1286
1287 static VAStatus
1288 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1289                                 const struct i965_surface *src_surface,
1290                                 const VARectangle *src_rect,
1291                                 struct i965_surface *dst_surface,
1292                                 const VARectangle *dst_rect,
1293                                 void *filter_param)
1294 {
1295     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1296     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1297     int width[3], height[3], pitch[3], offset[3];
1298     const int Y = 0;
1299
1300     /* source surface */
1301     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1302                                     width, height, pitch, offset);
1303
1304     /* destination surface */
1305     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1306                                     width, height, pitch, offset);
1307
1308     /* private function & data */
1309     pp_context->pp_x_steps = pp_load_save_x_steps;
1310     pp_context->pp_y_steps = pp_load_save_y_steps;
1311     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1312     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1313     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1314
1315     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1316     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1317
1318     dst_surface->flags = src_surface->flags;
1319
1320     return VA_STATUS_SUCCESS;
1321 }
1322
1323 static int
1324 pp_scaling_x_steps(void *private_context)
1325 {
1326     return 1;
1327 }
1328
1329 static int
1330 pp_scaling_y_steps(void *private_context)
1331 {
1332     struct pp_scaling_context *pp_scaling_context = private_context;
1333
1334     return pp_scaling_context->dest_h / 8;
1335 }
1336
1337 static int
1338 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1339 {
1340     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1341     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1342     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1343     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1344     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1345
1346     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1347     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1348     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1349     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1350
1351     return 0;
1352 }
1353
1354 static VAStatus
1355 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1356                            const struct i965_surface *src_surface,
1357                            const VARectangle *src_rect,
1358                            struct i965_surface *dst_surface,
1359                            const VARectangle *dst_rect,
1360                            void *filter_param)
1361 {
1362     struct i965_driver_data *i965 = i965_driver_data(ctx);
1363     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1364     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1365     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1366     struct object_surface *obj_surface;
1367     struct i965_sampler_state *sampler_state;
1368     int in_w, in_h, in_wpitch, in_hpitch;
1369     int out_w, out_h, out_wpitch, out_hpitch;
1370
1371     /* source surface */
1372     obj_surface = SURFACE(src_surface->id);
1373     in_w = obj_surface->orig_width;
1374     in_h = obj_surface->orig_height;
1375     in_wpitch = obj_surface->width;
1376     in_hpitch = obj_surface->height;
1377
1378     /* source Y surface index 1 */
1379     i965_pp_set_surface_state(ctx, pp_context,
1380                               obj_surface->bo, 0,
1381                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1382                               1, 0);
1383
1384     /* source UV surface index 2 */
1385     i965_pp_set_surface_state(ctx, pp_context,
1386                               obj_surface->bo, in_wpitch * in_hpitch,
1387                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1388                               2, 0);
1389
1390     /* destination surface */
1391     obj_surface = SURFACE(dst_surface->id);
1392     out_w = obj_surface->orig_width;
1393     out_h = obj_surface->orig_height;
1394     out_wpitch = obj_surface->width;
1395     out_hpitch = obj_surface->height;
1396
1397     /* destination Y surface index 7 */
1398     i965_pp_set_surface_state(ctx, pp_context,
1399                               obj_surface->bo, 0,
1400                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1401                               7, 1);
1402
1403     /* destination UV surface index 8 */
1404     i965_pp_set_surface_state(ctx, pp_context,
1405                               obj_surface->bo, out_wpitch * out_hpitch,
1406                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1407                               8, 1);
1408
1409     /* sampler state */
1410     dri_bo_map(pp_context->sampler_state_table.bo, True);
1411     assert(pp_context->sampler_state_table.bo->virtual);
1412     sampler_state = pp_context->sampler_state_table.bo->virtual;
1413
1414     /* SIMD16 Y index 1 */
1415     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1416     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1417     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1418     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1419     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1420
1421     /* SIMD16 UV index 2 */
1422     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1423     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1424     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1425     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1426     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1427
1428     dri_bo_unmap(pp_context->sampler_state_table.bo);
1429
1430     /* private function & data */
1431     pp_context->pp_x_steps = pp_scaling_x_steps;
1432     pp_context->pp_y_steps = pp_scaling_y_steps;
1433     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1434
1435     pp_scaling_context->dest_x = dst_rect->x;
1436     pp_scaling_context->dest_y = dst_rect->y;
1437     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1438     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1439     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1440     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1441
1442     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1443
1444     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1445     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1446     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1447     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1448     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1449
1450     dst_surface->flags = src_surface->flags;
1451
1452     return VA_STATUS_SUCCESS;
1453 }
1454
1455 static int
1456 pp_avs_x_steps(void *private_context)
1457 {
1458     struct pp_avs_context *pp_avs_context = private_context;
1459
1460     return pp_avs_context->dest_w / 16;
1461 }
1462
1463 static int
1464 pp_avs_y_steps(void *private_context)
1465 {
1466     return 1;
1467 }
1468
1469 static int
1470 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1471 {
1472     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1473     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1474     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1475     float src_x_steping, src_y_steping, video_step_delta;
1476     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1477
1478     if (tmp_w >= pp_avs_context->dest_w) {
1479         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1480         pp_inline_parameter->grf6.video_step_delta = 0;
1481
1482         if (x == 0) {
1483             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1484                 pp_avs_context->src_normalized_x;
1485         } else {
1486             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1487             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1488             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1489                 16 * 15 * video_step_delta / 2;
1490         }
1491     } else {
1492         int n0, n1, n2, nls_left, nls_right;
1493         int factor_a = 5, factor_b = 4;
1494         float f;
1495
1496         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1497         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1498         n2 = tmp_w / (16 * factor_a);
1499         nls_left = n0 + n2;
1500         nls_right = n1 + n2;
1501         f = (float) n2 * 16 / tmp_w;
1502
1503         if (n0 < 5) {
1504             pp_inline_parameter->grf6.video_step_delta = 0.0;
1505
1506             if (x == 0) {
1507                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1508                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1509             } else {
1510                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1511                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1512                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1513                     16 * 15 * video_step_delta / 2;
1514             }
1515         } else {
1516             if (x < nls_left) {
1517                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1518                 float a = f / (nls_left * 16 * factor_b);
1519                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1520
1521                 pp_inline_parameter->grf6.video_step_delta = b;
1522
1523                 if (x == 0) {
1524                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1525                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1526                 } else {
1527                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1528                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1529                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1530                         16 * 15 * video_step_delta / 2;
1531                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1532                 }
1533             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1534                 /* scale the center linearly */
1535                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1536                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1537                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1538                     16 * 15 * video_step_delta / 2;
1539                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1540                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1541             } else {
1542                 float a = f / (nls_right * 16 * factor_b);
1543                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1544
1545                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1546                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1547                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1548                     16 * 15 * video_step_delta / 2;
1549                 pp_inline_parameter->grf6.video_step_delta = -b;
1550
1551                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1552                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1553                 else
1554                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1555             }
1556         }
1557     }
1558
1559     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1560     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1561     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1562     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1563
1564     return 0;
1565 }
1566
1567 static VAStatus
1568 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1569                        const struct i965_surface *src_surface,
1570                        const VARectangle *src_rect,
1571                        struct i965_surface *dst_surface,
1572                        const VARectangle *dst_rect,
1573                        void *filter_param)
1574 {
1575     struct i965_driver_data *i965 = i965_driver_data(ctx);
1576     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1577     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1578     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1579     struct object_surface *obj_surface;
1580     struct i965_sampler_8x8 *sampler_8x8;
1581     struct i965_sampler_8x8_state *sampler_8x8_state;
1582     int index;
1583     int in_w, in_h, in_wpitch, in_hpitch;
1584     int out_w, out_h, out_wpitch, out_hpitch;
1585     int i;
1586
1587     /* surface */
1588     obj_surface = SURFACE(src_surface->id);
1589     in_w = obj_surface->orig_width;
1590     in_h = obj_surface->orig_height;
1591     in_wpitch = obj_surface->width;
1592     in_hpitch = obj_surface->height;
1593
1594     /* source Y surface index 1 */
1595     i965_pp_set_surface2_state(ctx, pp_context,
1596                                obj_surface->bo, 0,
1597                                in_w, in_h, in_wpitch,
1598                                0, 0,
1599                                SURFACE_FORMAT_Y8_UNORM, 0,
1600                                1);
1601
1602     /* source UV surface index 2 */
1603     i965_pp_set_surface2_state(ctx, pp_context,
1604                                obj_surface->bo, in_wpitch * in_hpitch,
1605                                in_w / 2, in_h / 2, in_wpitch,
1606                                0, 0,
1607                                SURFACE_FORMAT_R8B8_UNORM, 0,
1608                                2);
1609
1610     /* destination surface */
1611     obj_surface = SURFACE(dst_surface->id);
1612     out_w = obj_surface->orig_width;
1613     out_h = obj_surface->orig_height;
1614     out_wpitch = obj_surface->width;
1615     out_hpitch = obj_surface->height;
1616     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1617
1618     /* destination Y surface index 7 */
1619     i965_pp_set_surface_state(ctx, pp_context,
1620                               obj_surface->bo, 0,
1621                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1622                               7, 1);
1623
1624     /* destination UV surface index 8 */
1625     i965_pp_set_surface_state(ctx, pp_context,
1626                               obj_surface->bo, out_wpitch * out_hpitch,
1627                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1628                               8, 1);
1629
1630     /* sampler 8x8 state */
1631     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1632     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1633     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1634     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1635     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1636
1637     for (i = 0; i < 17; i++) {
1638         /* for Y channel, currently ignore */
1639         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1640         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1641         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1642         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1643         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1644         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1645         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1646         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1647         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1648         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1649         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1650         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1651         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1652         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1653         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1654         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1655         /* for U/V channel, 0.25 */
1656         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1657         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1658         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1659         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1660         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1661         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1662         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1663         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1664         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1665         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1666         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1667         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1668         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1669         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1670         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1671         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1672     }
1673
1674     sampler_8x8_state->dw136.default_sharpness_level = 0;
1675     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1676     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1677     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1678     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1679
1680     /* sampler 8x8 */
1681     dri_bo_map(pp_context->sampler_state_table.bo, True);
1682     assert(pp_context->sampler_state_table.bo->virtual);
1683     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1684     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1685
1686     /* sample_8x8 Y index 1 */
1687     index = 1;
1688     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1689     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1690     sampler_8x8[index].dw0.ief_bypass = 1;
1691     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1692     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1693     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1694     sampler_8x8[index].dw2.global_noise_estimation = 22;
1695     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1696     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1697     sampler_8x8[index].dw3.strong_edge_weight = 7;
1698     sampler_8x8[index].dw3.regular_weight = 2;
1699     sampler_8x8[index].dw3.non_edge_weight = 0;
1700     sampler_8x8[index].dw3.gain_factor = 40;
1701     sampler_8x8[index].dw4.steepness_boost = 0;
1702     sampler_8x8[index].dw4.steepness_threshold = 0;
1703     sampler_8x8[index].dw4.mr_boost = 0;
1704     sampler_8x8[index].dw4.mr_threshold = 5;
1705     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1706     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1707     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1708     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1709     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1710     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1711     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1712     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1713     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1714     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1715     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1716     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1717     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1718     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1719     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1720     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1721     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1722     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1723     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1724     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1725     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1726     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1727     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1728     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1729     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1730     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1731     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1732     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1733     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1734     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1735     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1736     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1737     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1738     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1739     sampler_8x8[index].dw13.limiter_boost = 0;
1740     sampler_8x8[index].dw13.minimum_limiter = 10;
1741     sampler_8x8[index].dw13.maximum_limiter = 11;
1742     sampler_8x8[index].dw14.clip_limiter = 130;
1743     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1744                       I915_GEM_DOMAIN_RENDER,
1745                       0,
1746                       0,
1747                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1748                       pp_context->sampler_state_table.bo_8x8);
1749
1750     /* sample_8x8 UV index 2 */
1751     index = 2;
1752     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1753     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1754     sampler_8x8[index].dw0.ief_bypass = 1;
1755     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1756     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1757     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1758     sampler_8x8[index].dw2.global_noise_estimation = 22;
1759     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1760     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1761     sampler_8x8[index].dw3.strong_edge_weight = 7;
1762     sampler_8x8[index].dw3.regular_weight = 2;
1763     sampler_8x8[index].dw3.non_edge_weight = 0;
1764     sampler_8x8[index].dw3.gain_factor = 40;
1765     sampler_8x8[index].dw4.steepness_boost = 0;
1766     sampler_8x8[index].dw4.steepness_threshold = 0;
1767     sampler_8x8[index].dw4.mr_boost = 0;
1768     sampler_8x8[index].dw4.mr_threshold = 5;
1769     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1770     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1771     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1772     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1773     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1774     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1775     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1776     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1777     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1778     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1779     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1780     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1781     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1782     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1783     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1784     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1785     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1786     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1787     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1788     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1789     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1790     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1791     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1792     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1793     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1794     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1795     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1796     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1797     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1798     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1799     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1800     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1801     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1802     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1803     sampler_8x8[index].dw13.limiter_boost = 0;
1804     sampler_8x8[index].dw13.minimum_limiter = 10;
1805     sampler_8x8[index].dw13.maximum_limiter = 11;
1806     sampler_8x8[index].dw14.clip_limiter = 130;
1807     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1808                       I915_GEM_DOMAIN_RENDER,
1809                       0,
1810                       0,
1811                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1812                       pp_context->sampler_state_table.bo_8x8);
1813
1814     dri_bo_unmap(pp_context->sampler_state_table.bo);
1815
1816     /* private function & data */
1817     pp_context->pp_x_steps = pp_avs_x_steps;
1818     pp_context->pp_y_steps = pp_avs_y_steps;
1819     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
1820
1821     pp_avs_context->dest_x = dst_rect->x;
1822     pp_avs_context->dest_y = dst_rect->y;
1823     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
1824     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1825     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
1826     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
1827     pp_avs_context->src_w = src_rect->width;
1828     pp_avs_context->src_h = src_rect->height;
1829
1830     pp_static_parameter->grf4.r4_2.avs.nlas = 1;
1831     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1832
1833     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1834     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
1835     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
1836     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1837     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1838     pp_inline_parameter->grf6.video_step_delta = 0.0;
1839
1840     dst_surface->flags = src_surface->flags;
1841
1842     return VA_STATUS_SUCCESS;
1843 }
1844
1845 static int
1846 gen7_pp_avs_x_steps(void *private_context)
1847 {
1848     struct pp_avs_context *pp_avs_context = private_context;
1849
1850     return pp_avs_context->dest_w / 16;
1851 }
1852
1853 static int
1854 gen7_pp_avs_y_steps(void *private_context)
1855 {
1856     struct pp_avs_context *pp_avs_context = private_context;
1857
1858     return pp_avs_context->dest_h / 16;
1859 }
1860
1861 static int
1862 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1863 {
1864     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1865     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1866
1867     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1868     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
1869     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
1870     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
1871
1872     return 0;
1873 }
1874
1875 static VAStatus
1876 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1877                            const struct i965_surface *src_surface,
1878                            const VARectangle *src_rect,
1879                            struct i965_surface *dst_surface,
1880                            const VARectangle *dst_rect,
1881                            void *filter_param)
1882 {
1883     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1884     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1885     struct gen7_sampler_8x8 *sampler_8x8;
1886     struct i965_sampler_8x8_state *sampler_8x8_state;
1887     int index, i;
1888     int width[3], height[3], pitch[3], offset[3];
1889
1890     /* source surface */
1891     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
1892                                          width, height, pitch, offset);
1893
1894     /* destination surface */
1895     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
1896                                          width, height, pitch, offset);
1897
1898     /* sampler 8x8 state */
1899     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1900     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1901     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1902     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1903     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1904
1905     for (i = 0; i < 17; i++) {
1906         /* for Y channel, currently ignore */
1907         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
1908         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
1909         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
1910         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
1911         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
1912         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
1913         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
1914         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
1915         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
1916         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
1917         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
1918         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
1919         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
1920         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
1921         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
1922         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
1923         /* for U/V channel, 0.25 */
1924         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1925         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1926         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1927         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1928         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1929         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1930         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1931         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1932         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1933         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1934         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1935         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1936         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1937         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1938         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1939         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1940     }
1941
1942     sampler_8x8_state->dw136.default_sharpness_level = 0;
1943     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1944     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1945     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1946     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1947
1948     /* sampler 8x8 */
1949     dri_bo_map(pp_context->sampler_state_table.bo, True);
1950     assert(pp_context->sampler_state_table.bo->virtual);
1951     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
1952     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1953
1954     /* sample_8x8 Y index 4 */
1955     index = 4;
1956     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1957     sampler_8x8[index].dw0.global_noise_estimation = 255;
1958     sampler_8x8[index].dw0.ief_bypass = 1;
1959
1960     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1961
1962     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1963     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1964     sampler_8x8[index].dw2.r5x_coefficient = 9;
1965     sampler_8x8[index].dw2.r5cx_coefficient = 8;
1966     sampler_8x8[index].dw2.r5c_coefficient = 3;
1967
1968     sampler_8x8[index].dw3.r3x_coefficient = 27;
1969     sampler_8x8[index].dw3.r3c_coefficient = 5;
1970     sampler_8x8[index].dw3.gain_factor = 40;
1971     sampler_8x8[index].dw3.non_edge_weight = 1;
1972     sampler_8x8[index].dw3.regular_weight = 2;
1973     sampler_8x8[index].dw3.strong_edge_weight = 7;
1974     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
1975
1976     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1977                       I915_GEM_DOMAIN_RENDER,
1978                       0,
1979                       0,
1980                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1981                       pp_context->sampler_state_table.bo_8x8);
1982
1983     /* sample_8x8 UV index 8 */
1984     index = 8;
1985     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1986     sampler_8x8[index].dw0.disable_8x8_filter = 0;
1987     sampler_8x8[index].dw0.global_noise_estimation = 255;
1988     sampler_8x8[index].dw0.ief_bypass = 1;
1989     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1990     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1991     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1992     sampler_8x8[index].dw2.r5x_coefficient = 9;
1993     sampler_8x8[index].dw2.r5cx_coefficient = 8;
1994     sampler_8x8[index].dw2.r5c_coefficient = 3;
1995     sampler_8x8[index].dw3.r3x_coefficient = 27;
1996     sampler_8x8[index].dw3.r3c_coefficient = 5;
1997     sampler_8x8[index].dw3.gain_factor = 40;
1998     sampler_8x8[index].dw3.non_edge_weight = 1;
1999     sampler_8x8[index].dw3.regular_weight = 2;
2000     sampler_8x8[index].dw3.strong_edge_weight = 7;
2001     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2002
2003     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2004                       I915_GEM_DOMAIN_RENDER,
2005                       0,
2006                       0,
2007                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2008                       pp_context->sampler_state_table.bo_8x8);
2009
2010     dri_bo_unmap(pp_context->sampler_state_table.bo);
2011
2012     /* sampler_8x8 V, index 12 */
2013     index = 12;
2014     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2015     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2016     sampler_8x8[index].dw0.global_noise_estimation = 255;
2017     sampler_8x8[index].dw0.ief_bypass = 1;
2018     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2019     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2020     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2021     sampler_8x8[index].dw2.r5x_coefficient = 9;
2022     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2023     sampler_8x8[index].dw2.r5c_coefficient = 3;
2024     sampler_8x8[index].dw3.r3x_coefficient = 27;
2025     sampler_8x8[index].dw3.r3c_coefficient = 5;
2026     sampler_8x8[index].dw3.gain_factor = 40;
2027     sampler_8x8[index].dw3.non_edge_weight = 1;
2028     sampler_8x8[index].dw3.regular_weight = 2;
2029     sampler_8x8[index].dw3.strong_edge_weight = 7;
2030     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2031
2032     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2033                       I915_GEM_DOMAIN_RENDER,
2034                       0,
2035                       0,
2036                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2037                       pp_context->sampler_state_table.bo_8x8);
2038
2039     dri_bo_unmap(pp_context->sampler_state_table.bo);
2040
2041     /* private function & data */
2042     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2043     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2044     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2045
2046     pp_avs_context->dest_x = dst_rect->x;
2047     pp_avs_context->dest_y = dst_rect->y;
2048     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2049     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2050     pp_avs_context->src_w = src_rect->width;
2051     pp_avs_context->src_h = src_rect->height;
2052
2053     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2054     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / pp_avs_context->dest_w;
2055     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2056     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2057     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / pp_avs_context->dest_w;
2058
2059     dst_surface->flags = src_surface->flags;
2060
2061     return VA_STATUS_SUCCESS;
2062 }
2063
2064 static int
2065 pp_dndi_x_steps(void *private_context)
2066 {
2067     return 1;
2068 }
2069
2070 static int
2071 pp_dndi_y_steps(void *private_context)
2072 {
2073     struct pp_dndi_context *pp_dndi_context = private_context;
2074
2075     return pp_dndi_context->dest_h / 4;
2076 }
2077
2078 static int
2079 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2080 {
2081     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2082
2083     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2084     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2085
2086     return 0;
2087 }
2088
2089 static VAStatus
2090 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2091                         const struct i965_surface *src_surface,
2092                         const VARectangle *src_rect,
2093                         struct i965_surface *dst_surface,
2094                         const VARectangle *dst_rect,
2095                         void *filter_param)
2096 {
2097     struct i965_driver_data *i965 = i965_driver_data(ctx);
2098     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2099     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2100     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2101     struct object_surface *obj_surface;
2102     struct i965_sampler_dndi *sampler_dndi;
2103     int index;
2104     int w, h;
2105     int orig_w, orig_h;
2106     int dndi_top_first = 1;
2107
2108     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2109         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2110
2111     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2112         dndi_top_first = 1;
2113     else
2114         dndi_top_first = 0;
2115
2116     /* surface */
2117     obj_surface = SURFACE(src_surface->id);
2118     orig_w = obj_surface->orig_width;
2119     orig_h = obj_surface->orig_height;
2120     w = obj_surface->width;
2121     h = obj_surface->height;
2122
2123     if (pp_context->stmm.bo == NULL) {
2124         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2125                                            "STMM surface",
2126                                            w * h,
2127                                            4096);
2128         assert(pp_context->stmm.bo);
2129     }
2130
2131     /* source UV surface index 2 */
2132     i965_pp_set_surface_state(ctx, pp_context,
2133                               obj_surface->bo, w * h,
2134                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2135                               2, 0);
2136
2137     /* source YUV surface index 4 */
2138     i965_pp_set_surface2_state(ctx, pp_context,
2139                                obj_surface->bo, 0,
2140                                orig_w, orig_h, w,
2141                                0, h,
2142                                SURFACE_FORMAT_PLANAR_420_8, 1,
2143                                4);
2144
2145     /* source STMM surface index 20 */
2146     i965_pp_set_surface_state(ctx, pp_context,
2147                               pp_context->stmm.bo, 0,
2148                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2149                               20, 1);
2150
2151     /* destination surface */
2152     obj_surface = SURFACE(dst_surface->id);
2153     orig_w = obj_surface->orig_width;
2154     orig_h = obj_surface->orig_height;
2155     w = obj_surface->width;
2156     h = obj_surface->height;
2157
2158     /* destination Y surface index 7 */
2159     i965_pp_set_surface_state(ctx, pp_context,
2160                               obj_surface->bo, 0,
2161                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2162                               7, 1);
2163
2164     /* destination UV surface index 8 */
2165     i965_pp_set_surface_state(ctx, pp_context,
2166                               obj_surface->bo, w * h,
2167                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2168                               8, 1);
2169     /* sampler dndi */
2170     dri_bo_map(pp_context->sampler_state_table.bo, True);
2171     assert(pp_context->sampler_state_table.bo->virtual);
2172     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2173     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2174
2175     /* sample dndi index 1 */
2176     index = 0;
2177     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2178     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2179     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2180     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2181
2182     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2183     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2184     sampler_dndi[index].dw1.stmm_c2 = 1;
2185     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2186     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2187
2188     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2189     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2190     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2191     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2192
2193     sampler_dndi[index].dw3.maximum_stmm = 128;
2194     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2195     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2196     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2197     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2198
2199     sampler_dndi[index].dw4.sdi_delta = 8;
2200     sampler_dndi[index].dw4.sdi_threshold = 128;
2201     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2202     sampler_dndi[index].dw4.stmm_shift_up = 0;
2203     sampler_dndi[index].dw4.stmm_shift_down = 0;
2204     sampler_dndi[index].dw4.minimum_stmm = 0;
2205
2206     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2207     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2208     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2209     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2210
2211     sampler_dndi[index].dw6.dn_enable = 1;
2212     sampler_dndi[index].dw6.di_enable = 1;
2213     sampler_dndi[index].dw6.di_partial = 0;
2214     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2215     sampler_dndi[index].dw6.dndi_stream_id = 0;
2216     sampler_dndi[index].dw6.dndi_first_frame = 1;
2217     sampler_dndi[index].dw6.progressive_dn = 0;
2218     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2219     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2220     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2221
2222     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2223     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2224     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2225     sampler_dndi[index].dw7.column_width_minus1 = 0;
2226
2227     dri_bo_unmap(pp_context->sampler_state_table.bo);
2228
2229     /* private function & data */
2230     pp_context->pp_x_steps = pp_dndi_x_steps;
2231     pp_context->pp_y_steps = pp_dndi_y_steps;
2232     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2233
2234     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2235     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2236     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2237     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2238
2239     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2240     pp_inline_parameter->grf5.number_blocks = w / 16;
2241     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2242     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2243
2244     pp_dndi_context->dest_w = w;
2245     pp_dndi_context->dest_h = h;
2246
2247     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2248
2249     return VA_STATUS_SUCCESS;
2250 }
2251
2252 static int
2253 pp_dn_x_steps(void *private_context)
2254 {
2255     return 1;
2256 }
2257
2258 static int
2259 pp_dn_y_steps(void *private_context)
2260 {
2261     struct pp_dn_context *pp_dn_context = private_context;
2262
2263     return pp_dn_context->dest_h / 8;
2264 }
2265
2266 static int
2267 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2268 {
2269     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2270
2271     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2272     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2273
2274     return 0;
2275 }
2276
2277 static VAStatus
2278 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2279                       const struct i965_surface *src_surface,
2280                       const VARectangle *src_rect,
2281                       struct i965_surface *dst_surface,
2282                       const VARectangle *dst_rect,
2283                       void *filter_param)
2284 {
2285     struct i965_driver_data *i965 = i965_driver_data(ctx);
2286     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2287     struct object_surface *obj_surface;
2288     struct i965_sampler_dndi *sampler_dndi;
2289     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2290     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2291     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2292     int index;
2293     int w, h;
2294     int orig_w, orig_h;
2295     int dn_strength = 15;
2296     int dndi_top_first = 1;
2297     int dn_progressive = 0;
2298
2299     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2300         dndi_top_first = 1;
2301         dn_progressive = 1;
2302     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2303         dndi_top_first = 1;
2304         dn_progressive = 0;
2305     } else {
2306         dndi_top_first = 0;
2307         dn_progressive = 0;
2308     }
2309
2310     if (dn_filter_param) {
2311         float value = dn_filter_param->value;
2312
2313         if (value > 1.0)
2314             value = 1.0;
2315
2316         if (value < 0.0)
2317             value = 0.0;
2318
2319         dn_strength = (int)(value * 31.0F);
2320     }
2321
2322     /* surface */
2323     obj_surface = SURFACE(src_surface->id);
2324     orig_w = obj_surface->orig_width;
2325     orig_h = obj_surface->orig_height;
2326     w = obj_surface->width;
2327     h = obj_surface->height;
2328
2329     if (pp_context->stmm.bo == NULL) {
2330         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2331                                            "STMM surface",
2332                                            w * h,
2333                                            4096);
2334         assert(pp_context->stmm.bo);
2335     }
2336
2337     /* source UV surface index 2 */
2338     i965_pp_set_surface_state(ctx, pp_context,
2339                               obj_surface->bo, w * h,
2340                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2341                               2, 0);
2342
2343     /* source YUV surface index 4 */
2344     i965_pp_set_surface2_state(ctx, pp_context,
2345                                obj_surface->bo, 0,
2346                                orig_w, orig_h, w,
2347                                0, h,
2348                                SURFACE_FORMAT_PLANAR_420_8, 1,
2349                                4);
2350
2351     /* source STMM surface index 20 */
2352     i965_pp_set_surface_state(ctx, pp_context,
2353                               pp_context->stmm.bo, 0,
2354                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2355                               20, 1);
2356
2357     /* destination surface */
2358     obj_surface = SURFACE(dst_surface->id);
2359     orig_w = obj_surface->orig_width;
2360     orig_h = obj_surface->orig_height;
2361     w = obj_surface->width;
2362     h = obj_surface->height;
2363
2364     /* destination Y surface index 7 */
2365     i965_pp_set_surface_state(ctx, pp_context,
2366                               obj_surface->bo, 0,
2367                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2368                               7, 1);
2369
2370     /* destination UV surface index 8 */
2371     i965_pp_set_surface_state(ctx, pp_context,
2372                               obj_surface->bo, w * h,
2373                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2374                               8, 1);
2375     /* sampler dn */
2376     dri_bo_map(pp_context->sampler_state_table.bo, True);
2377     assert(pp_context->sampler_state_table.bo->virtual);
2378     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2379     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2380
2381     /* sample dndi index 1 */
2382     index = 0;
2383     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2384     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2385     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2386     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2387
2388     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2389     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2390     sampler_dndi[index].dw1.stmm_c2 = 0;
2391     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2392     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2393
2394     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2395     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2396     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2397     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2398
2399     sampler_dndi[index].dw3.maximum_stmm = 128;
2400     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2401     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2402     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2403     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2404
2405     sampler_dndi[index].dw4.sdi_delta = 8;
2406     sampler_dndi[index].dw4.sdi_threshold = 128;
2407     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2408     sampler_dndi[index].dw4.stmm_shift_up = 0;
2409     sampler_dndi[index].dw4.stmm_shift_down = 0;
2410     sampler_dndi[index].dw4.minimum_stmm = 0;
2411
2412     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2413     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2414     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2415     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2416
2417     sampler_dndi[index].dw6.dn_enable = 1;
2418     sampler_dndi[index].dw6.di_enable = 0;
2419     sampler_dndi[index].dw6.di_partial = 0;
2420     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2421     sampler_dndi[index].dw6.dndi_stream_id = 1;
2422     sampler_dndi[index].dw6.dndi_first_frame = 1;
2423     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2424     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2425     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2426     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2427
2428     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2429     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2430     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2431     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2432
2433     dri_bo_unmap(pp_context->sampler_state_table.bo);
2434
2435     /* private function & data */
2436     pp_context->pp_x_steps = pp_dn_x_steps;
2437     pp_context->pp_y_steps = pp_dn_y_steps;
2438     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2439
2440     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2441     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2442     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2443     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2444
2445     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2446     pp_inline_parameter->grf5.number_blocks = w / 16;
2447     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2448     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2449
2450     pp_dn_context->dest_w = w;
2451     pp_dn_context->dest_h = h;
2452
2453     dst_surface->flags = src_surface->flags;
2454
2455     return VA_STATUS_SUCCESS;
2456 }
2457
2458 static int
2459 gen7_pp_dndi_x_steps(void *private_context)
2460 {
2461     struct pp_dndi_context *pp_dndi_context = private_context;
2462
2463     return pp_dndi_context->dest_w / 16;
2464 }
2465
2466 static int
2467 gen7_pp_dndi_y_steps(void *private_context)
2468 {
2469     struct pp_dndi_context *pp_dndi_context = private_context;
2470
2471     return pp_dndi_context->dest_h / 4;
2472 }
2473
2474 static int
2475 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2476 {
2477     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2478
2479     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2480     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2481
2482     return 0;
2483 }
2484
2485 static VAStatus
2486 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2487                              const struct i965_surface *src_surface,
2488                              const VARectangle *src_rect,
2489                              struct i965_surface *dst_surface,
2490                              const VARectangle *dst_rect,
2491                              void *filter_param)
2492 {
2493     struct i965_driver_data *i965 = i965_driver_data(ctx);
2494     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2495     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2496     struct object_surface *obj_surface;
2497     struct gen7_sampler_dndi *sampler_dndi;
2498     int index;
2499     int w, h;
2500     int orig_w, orig_h;
2501     int dndi_top_first = 1;
2502
2503     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2504         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2505
2506     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2507         dndi_top_first = 1;
2508     else
2509         dndi_top_first = 0;
2510
2511     /* surface */
2512     obj_surface = SURFACE(src_surface->id);
2513     orig_w = obj_surface->orig_width;
2514     orig_h = obj_surface->orig_height;
2515     w = obj_surface->width;
2516     h = obj_surface->height;
2517
2518     if (pp_context->stmm.bo == NULL) {
2519         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2520                                            "STMM surface",
2521                                            w * h,
2522                                            4096);
2523         assert(pp_context->stmm.bo);
2524     }
2525
2526     /* source UV surface index 1 */
2527     gen7_pp_set_surface_state(ctx, pp_context,
2528                               obj_surface->bo, w * h,
2529                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2530                               1, 0);
2531
2532     /* source YUV surface index 3 */
2533     gen7_pp_set_surface2_state(ctx, pp_context,
2534                                obj_surface->bo, 0,
2535                                orig_w, orig_h, w,
2536                                0, h,
2537                                SURFACE_FORMAT_PLANAR_420_8, 1,
2538                                3);
2539
2540     /* source (temporal reference) YUV surface index 4 */
2541     gen7_pp_set_surface2_state(ctx, pp_context,
2542                                obj_surface->bo, 0,
2543                                orig_w, orig_h, w,
2544                                0, h,
2545                                SURFACE_FORMAT_PLANAR_420_8, 1,
2546                                4);
2547
2548     /* STMM / History Statistics input surface, index 5 */
2549     gen7_pp_set_surface_state(ctx, pp_context,
2550                               pp_context->stmm.bo, 0,
2551                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2552                               5, 1);
2553
2554     /* destination surface */
2555     obj_surface = SURFACE(dst_surface->id);
2556     orig_w = obj_surface->orig_width;
2557     orig_h = obj_surface->orig_height;
2558     w = obj_surface->width;
2559     h = obj_surface->height;
2560
2561     /* destination(Previous frame) Y surface index 27 */
2562     gen7_pp_set_surface_state(ctx, pp_context,
2563                               obj_surface->bo, 0,
2564                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2565                               27, 1);
2566
2567     /* destination(Previous frame) UV surface index 28 */
2568     gen7_pp_set_surface_state(ctx, pp_context,
2569                               obj_surface->bo, w * h,
2570                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2571                               28, 1);
2572
2573     /* destination(Current frame) Y surface index 30 */
2574     gen7_pp_set_surface_state(ctx, pp_context,
2575                               obj_surface->bo, 0,
2576                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2577                               30, 1);
2578
2579     /* destination(Current frame) UV surface index 31 */
2580     gen7_pp_set_surface_state(ctx, pp_context,
2581                               obj_surface->bo, w * h,
2582                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2583                               31, 1);
2584
2585     /* STMM output surface, index 33 */
2586     gen7_pp_set_surface_state(ctx, pp_context,
2587                               pp_context->stmm.bo, 0,
2588                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2589                               33, 1);
2590
2591
2592     /* sampler dndi */
2593     dri_bo_map(pp_context->sampler_state_table.bo, True);
2594     assert(pp_context->sampler_state_table.bo->virtual);
2595     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2596     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2597
2598     /* sample dndi index 0 */
2599     index = 0;
2600     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2601     sampler_dndi[index].dw0.dnmh_delt = 8;
2602     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2603     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2604     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2605     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2606
2607     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2608     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2609     sampler_dndi[index].dw1.stmm_c2 = 0;
2610     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2611     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2612
2613     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2614     sampler_dndi[index].dw2.bne_edge_th = 1;
2615     sampler_dndi[index].dw2.smooth_mv_th = 0;
2616     sampler_dndi[index].dw2.sad_tight_th = 5;
2617     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2618     sampler_dndi[index].dw2.good_neighbor_th = 4;
2619
2620     sampler_dndi[index].dw3.maximum_stmm = 128;
2621     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2622     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2623     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2624     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2625
2626     sampler_dndi[index].dw4.sdi_delta = 8;
2627     sampler_dndi[index].dw4.sdi_threshold = 128;
2628     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2629     sampler_dndi[index].dw4.stmm_shift_up = 0;
2630     sampler_dndi[index].dw4.stmm_shift_down = 0;
2631     sampler_dndi[index].dw4.minimum_stmm = 0;
2632
2633     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2634     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2635     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2636     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2637
2638     sampler_dndi[index].dw6.dn_enable = 0;
2639     sampler_dndi[index].dw6.di_enable = 1;
2640     sampler_dndi[index].dw6.di_partial = 0;
2641     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2642     sampler_dndi[index].dw6.dndi_stream_id = 1;
2643     sampler_dndi[index].dw6.dndi_first_frame = 1;
2644     sampler_dndi[index].dw6.progressive_dn = 0;
2645     sampler_dndi[index].dw6.mcdi_enable = 0;
2646     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2647     sampler_dndi[index].dw6.cat_th1 = 0;
2648     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2649     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2650
2651     sampler_dndi[index].dw7.sad_tha = 5;
2652     sampler_dndi[index].dw7.sad_thb = 10;
2653     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2654     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2655     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2656     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2657     sampler_dndi[index].dw7.neighborpixel_th = 10;
2658     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2659
2660     dri_bo_unmap(pp_context->sampler_state_table.bo);
2661
2662     /* private function & data */
2663     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2664     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2665     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2666
2667     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2668     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2669     pp_static_parameter->grf1.di_top_field_first = 0;
2670     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2671
2672     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2673     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2674     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2675
2676     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2677     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2678
2679     pp_dndi_context->dest_w = w;
2680     pp_dndi_context->dest_h = h;
2681
2682     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2683
2684     return VA_STATUS_SUCCESS;
2685 }
2686
2687 static int
2688 gen7_pp_dn_x_steps(void *private_context)
2689 {
2690     return 1;
2691 }
2692
2693 static int
2694 gen7_pp_dn_y_steps(void *private_context)
2695 {
2696     struct pp_dn_context *pp_dn_context = private_context;
2697
2698     return pp_dn_context->dest_h / 4;
2699 }
2700
2701 static int
2702 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2703 {
2704     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2705
2706     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2707     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2708
2709     return 0;
2710 }
2711
2712 static VAStatus
2713 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2714                            const struct i965_surface *src_surface,
2715                            const VARectangle *src_rect,
2716                            struct i965_surface *dst_surface,
2717                            const VARectangle *dst_rect,
2718                            void *filter_param)
2719 {
2720     struct i965_driver_data *i965 = i965_driver_data(ctx);
2721     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2722     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2723     struct object_surface *obj_surface;
2724     struct gen7_sampler_dndi *sampler_dn;
2725     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2726     int index;
2727     int w, h;
2728     int orig_w, orig_h;
2729     int dn_strength = 15;
2730     int dndi_top_first = 1;
2731     int dn_progressive = 0;
2732
2733     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2734         dndi_top_first = 1;
2735         dn_progressive = 1;
2736     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2737         dndi_top_first = 1;
2738         dn_progressive = 0;
2739     } else {
2740         dndi_top_first = 0;
2741         dn_progressive = 0;
2742     }
2743
2744     if (dn_filter_param) {
2745         float value = dn_filter_param->value;
2746
2747         if (value > 1.0)
2748             value = 1.0;
2749
2750         if (value < 0.0)
2751             value = 0.0;
2752
2753         dn_strength = (int)(value * 31.0F);
2754     }
2755
2756     /* surface */
2757     obj_surface = SURFACE(src_surface->id);
2758     orig_w = obj_surface->orig_width;
2759     orig_h = obj_surface->orig_height;
2760     w = obj_surface->width;
2761     h = obj_surface->height;
2762
2763     if (pp_context->stmm.bo == NULL) {
2764         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2765                                            "STMM surface",
2766                                            w * h,
2767                                            4096);
2768         assert(pp_context->stmm.bo);
2769     }
2770
2771     /* source UV surface index 1 */
2772     gen7_pp_set_surface_state(ctx, pp_context,
2773                               obj_surface->bo, w * h,
2774                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2775                               1, 0);
2776
2777     /* source YUV surface index 3 */
2778     gen7_pp_set_surface2_state(ctx, pp_context,
2779                                obj_surface->bo, 0,
2780                                orig_w, orig_h, w,
2781                                0, h,
2782                                SURFACE_FORMAT_PLANAR_420_8, 1,
2783                                3);
2784
2785     /* source STMM surface index 5 */
2786     gen7_pp_set_surface_state(ctx, pp_context,
2787                               pp_context->stmm.bo, 0,
2788                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2789                               5, 1);
2790
2791     /* destination surface */
2792     obj_surface = SURFACE(dst_surface->id);
2793     orig_w = obj_surface->orig_width;
2794     orig_h = obj_surface->orig_height;
2795     w = obj_surface->width;
2796     h = obj_surface->height;
2797
2798     /* destination Y surface index 7 */
2799     gen7_pp_set_surface_state(ctx, pp_context,
2800                               obj_surface->bo, 0,
2801                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2802                               7, 1);
2803
2804     /* destination UV surface index 8 */
2805     gen7_pp_set_surface_state(ctx, pp_context,
2806                               obj_surface->bo, w * h,
2807                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2808                               8, 1);
2809     /* sampler dn */
2810     dri_bo_map(pp_context->sampler_state_table.bo, True);
2811     assert(pp_context->sampler_state_table.bo->virtual);
2812     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
2813     sampler_dn = pp_context->sampler_state_table.bo->virtual;
2814
2815     /* sample dn index 1 */
2816     index = 0;
2817     sampler_dn[index].dw0.denoise_asd_threshold = 0;
2818     sampler_dn[index].dw0.dnmh_delt = 8;
2819     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
2820     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
2821     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
2822     sampler_dn[index].dw0.denoise_stad_threshold = 0;
2823
2824     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2825     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
2826     sampler_dn[index].dw1.stmm_c2 = 0;
2827     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
2828     sampler_dn[index].dw1.temporal_difference_threshold = 16;
2829
2830     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2831     sampler_dn[index].dw2.bne_edge_th = 1;
2832     sampler_dn[index].dw2.smooth_mv_th = 0;
2833     sampler_dn[index].dw2.sad_tight_th = 5;
2834     sampler_dn[index].dw2.cat_slope_minus1 = 9;
2835     sampler_dn[index].dw2.good_neighbor_th = 4;
2836
2837     sampler_dn[index].dw3.maximum_stmm = 128;
2838     sampler_dn[index].dw3.multipler_for_vecm = 2;
2839     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2840     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2841     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
2842
2843     sampler_dn[index].dw4.sdi_delta = 8;
2844     sampler_dn[index].dw4.sdi_threshold = 128;
2845     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2846     sampler_dn[index].dw4.stmm_shift_up = 0;
2847     sampler_dn[index].dw4.stmm_shift_down = 0;
2848     sampler_dn[index].dw4.minimum_stmm = 0;
2849
2850     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
2851     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
2852     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2853     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2854
2855     sampler_dn[index].dw6.dn_enable = 1;
2856     sampler_dn[index].dw6.di_enable = 0;
2857     sampler_dn[index].dw6.di_partial = 0;
2858     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
2859     sampler_dn[index].dw6.dndi_stream_id = 1;
2860     sampler_dn[index].dw6.dndi_first_frame = 1;
2861     sampler_dn[index].dw6.progressive_dn = dn_progressive;
2862     sampler_dn[index].dw6.mcdi_enable = 0;
2863     sampler_dn[index].dw6.fmd_tear_threshold = 32;
2864     sampler_dn[index].dw6.cat_th1 = 0;
2865     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
2866     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
2867
2868     sampler_dn[index].dw7.sad_tha = 5;
2869     sampler_dn[index].dw7.sad_thb = 10;
2870     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2871     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
2872     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2873     sampler_dn[index].dw7.vdi_walker_enable = 0;
2874     sampler_dn[index].dw7.neighborpixel_th = 10;
2875     sampler_dn[index].dw7.column_width_minus1 = w / 16;
2876
2877     dri_bo_unmap(pp_context->sampler_state_table.bo);
2878
2879     /* private function & data */
2880     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
2881     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
2882     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
2883
2884     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2885     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2886     pp_static_parameter->grf1.di_top_field_first = 0;
2887     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2888
2889     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2890     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2891     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2892
2893     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2894     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2895
2896     pp_dn_context->dest_w = w;
2897     pp_dn_context->dest_h = h;
2898
2899     dst_surface->flags = src_surface->flags;
2900
2901     return VA_STATUS_SUCCESS;
2902 }
2903
2904 static VAStatus
2905 ironlake_pp_initialize(
2906     VADriverContextP   ctx,
2907     struct i965_post_processing_context *pp_context,
2908     const struct i965_surface *src_surface,
2909     const VARectangle *src_rect,
2910     struct i965_surface *dst_surface,
2911     const VARectangle *dst_rect,
2912     int                pp_index,
2913     void *filter_param
2914 )
2915 {
2916     VAStatus va_status;
2917     struct i965_driver_data *i965 = i965_driver_data(ctx);
2918     struct pp_module *pp_module;
2919     dri_bo *bo;
2920     int static_param_size, inline_param_size;
2921
2922     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
2923     bo = dri_bo_alloc(i965->intel.bufmgr,
2924                       "surface state & binding table",
2925                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
2926                       4096);
2927     assert(bo);
2928     pp_context->surface_state_binding_table.bo = bo;
2929
2930     dri_bo_unreference(pp_context->curbe.bo);
2931     bo = dri_bo_alloc(i965->intel.bufmgr,
2932                       "constant buffer",
2933                       4096,
2934                       4096);
2935     assert(bo);
2936     pp_context->curbe.bo = bo;
2937
2938     dri_bo_unreference(pp_context->idrt.bo);
2939     bo = dri_bo_alloc(i965->intel.bufmgr,
2940                       "interface discriptor",
2941                       sizeof(struct i965_interface_descriptor),
2942                       4096);
2943     assert(bo);
2944     pp_context->idrt.bo = bo;
2945     pp_context->idrt.num_interface_descriptors = 0;
2946
2947     dri_bo_unreference(pp_context->sampler_state_table.bo);
2948     bo = dri_bo_alloc(i965->intel.bufmgr,
2949                       "sampler state table",
2950                       4096,
2951                       4096);
2952     assert(bo);
2953     dri_bo_map(bo, True);
2954     memset(bo->virtual, 0, bo->size);
2955     dri_bo_unmap(bo);
2956     pp_context->sampler_state_table.bo = bo;
2957
2958     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
2959     bo = dri_bo_alloc(i965->intel.bufmgr,
2960                       "sampler 8x8 state ",
2961                       4096,
2962                       4096);
2963     assert(bo);
2964     pp_context->sampler_state_table.bo_8x8 = bo;
2965
2966     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
2967     bo = dri_bo_alloc(i965->intel.bufmgr,
2968                       "sampler 8x8 state ",
2969                       4096,
2970                       4096);
2971     assert(bo);
2972     pp_context->sampler_state_table.bo_8x8_uv = bo;
2973
2974     dri_bo_unreference(pp_context->vfe_state.bo);
2975     bo = dri_bo_alloc(i965->intel.bufmgr,
2976                       "vfe state",
2977                       sizeof(struct i965_vfe_state),
2978                       4096);
2979     assert(bo);
2980     pp_context->vfe_state.bo = bo;
2981
2982     if (IS_GEN7(i965->intel.device_id)) {
2983         static_param_size = sizeof(struct gen7_pp_static_parameter);
2984         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
2985     } else {
2986         static_param_size = sizeof(struct pp_static_parameter);
2987         inline_param_size = sizeof(struct pp_inline_parameter);
2988     }
2989
2990     memset(pp_context->pp_static_parameter, 0, static_param_size);
2991     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
2992     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
2993     pp_context->current_pp = pp_index;
2994     pp_module = &pp_context->pp_modules[pp_index];
2995
2996     if (pp_module->initialize)
2997         va_status = pp_module->initialize(ctx, pp_context,
2998                                           src_surface,
2999                                           src_rect,
3000                                           dst_surface,
3001                                           dst_rect,
3002                                           filter_param);
3003     else
3004         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3005
3006     return va_status;
3007 }
3008
3009 static VAStatus
3010 ironlake_post_processing(
3011     VADriverContextP   ctx,
3012     struct i965_post_processing_context *pp_context,
3013     const struct i965_surface *src_surface,
3014     const VARectangle *src_rect,
3015     struct i965_surface *dst_surface,
3016     const VARectangle *dst_rect,
3017     int                pp_index,
3018     void *filter_param
3019 )
3020 {
3021     VAStatus va_status;
3022
3023     va_status = ironlake_pp_initialize(ctx, pp_context,
3024                                        src_surface,
3025                                        src_rect,
3026                                        dst_surface,
3027                                        dst_rect,
3028                                        pp_index,
3029                                        filter_param);
3030
3031     if (va_status == VA_STATUS_SUCCESS) {
3032         ironlake_pp_states_setup(ctx, pp_context);
3033         ironlake_pp_pipeline_setup(ctx, pp_context);
3034     }
3035
3036     return va_status;
3037 }
3038
3039 static VAStatus
3040 gen6_pp_initialize(
3041     VADriverContextP   ctx,
3042     struct i965_post_processing_context *pp_context,
3043     const struct i965_surface *src_surface,
3044     const VARectangle *src_rect,
3045     struct i965_surface *dst_surface,
3046     const VARectangle *dst_rect,
3047     int                pp_index,
3048     void *filter_param
3049 )
3050 {
3051     VAStatus va_status;
3052     struct i965_driver_data *i965 = i965_driver_data(ctx);
3053     struct pp_module *pp_module;
3054     dri_bo *bo;
3055     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3056     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3057
3058     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3059     bo = dri_bo_alloc(i965->intel.bufmgr,
3060                       "surface state & binding table",
3061                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3062                       4096);
3063     assert(bo);
3064     pp_context->surface_state_binding_table.bo = bo;
3065
3066     dri_bo_unreference(pp_context->curbe.bo);
3067     bo = dri_bo_alloc(i965->intel.bufmgr,
3068                       "constant buffer",
3069                       4096,
3070                       4096);
3071     assert(bo);
3072     pp_context->curbe.bo = bo;
3073
3074     dri_bo_unreference(pp_context->idrt.bo);
3075     bo = dri_bo_alloc(i965->intel.bufmgr,
3076                       "interface discriptor",
3077                       sizeof(struct gen6_interface_descriptor_data),
3078                       4096);
3079     assert(bo);
3080     pp_context->idrt.bo = bo;
3081     pp_context->idrt.num_interface_descriptors = 0;
3082
3083     dri_bo_unreference(pp_context->sampler_state_table.bo);
3084     bo = dri_bo_alloc(i965->intel.bufmgr,
3085                       "sampler state table",
3086                       4096,
3087                       4096);
3088     assert(bo);
3089     dri_bo_map(bo, True);
3090     memset(bo->virtual, 0, bo->size);
3091     dri_bo_unmap(bo);
3092     pp_context->sampler_state_table.bo = bo;
3093
3094     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3095     bo = dri_bo_alloc(i965->intel.bufmgr,
3096                       "sampler 8x8 state ",
3097                       4096,
3098                       4096);
3099     assert(bo);
3100     pp_context->sampler_state_table.bo_8x8 = bo;
3101
3102     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3103     bo = dri_bo_alloc(i965->intel.bufmgr,
3104                       "sampler 8x8 state ",
3105                       4096,
3106                       4096);
3107     assert(bo);
3108     pp_context->sampler_state_table.bo_8x8_uv = bo;
3109
3110     dri_bo_unreference(pp_context->vfe_state.bo);
3111     bo = dri_bo_alloc(i965->intel.bufmgr,
3112                       "vfe state",
3113                       sizeof(struct i965_vfe_state),
3114                       4096);
3115     assert(bo);
3116     pp_context->vfe_state.bo = bo;
3117
3118     memset(pp_static_parameter, 0, sizeof(*pp_static_parameter));
3119     memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter));
3120     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3121     pp_context->current_pp = pp_index;
3122     pp_module = &pp_context->pp_modules[pp_index];
3123
3124     if (pp_module->initialize)
3125         va_status = pp_module->initialize(ctx, pp_context,
3126                                           src_surface,
3127                                           src_rect,
3128                                           dst_surface,
3129                                           dst_rect,
3130                                           filter_param);
3131     else
3132         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3133
3134     return va_status;
3135 }
3136
3137 static void
3138 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3139                                    struct i965_post_processing_context *pp_context)
3140 {
3141     struct i965_driver_data *i965 = i965_driver_data(ctx);
3142     struct gen6_interface_descriptor_data *desc;
3143     dri_bo *bo;
3144     int pp_index = pp_context->current_pp;
3145
3146     bo = pp_context->idrt.bo;
3147     dri_bo_map(bo, True);
3148     assert(bo->virtual);
3149     desc = bo->virtual;
3150     memset(desc, 0, sizeof(*desc));
3151     desc->desc0.kernel_start_pointer =
3152         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3153     desc->desc1.single_program_flow = 1;
3154     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3155     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3156     desc->desc2.sampler_state_pointer =
3157         pp_context->sampler_state_table.bo->offset >> 5;
3158     desc->desc3.binding_table_entry_count = 0;
3159     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3160     desc->desc4.constant_urb_entry_read_offset = 0;
3161
3162     if (IS_GEN7(i965->intel.device_id))
3163         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3164     else
3165         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3166
3167     dri_bo_emit_reloc(bo,
3168                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3169                       0,
3170                       offsetof(struct gen6_interface_descriptor_data, desc0),
3171                       pp_context->pp_modules[pp_index].kernel.bo);
3172
3173     dri_bo_emit_reloc(bo,
3174                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3175                       desc->desc2.sampler_count << 2,
3176                       offsetof(struct gen6_interface_descriptor_data, desc2),
3177                       pp_context->sampler_state_table.bo);
3178
3179     dri_bo_unmap(bo);
3180     pp_context->idrt.num_interface_descriptors++;
3181 }
3182
3183 static void
3184 gen6_pp_upload_constants(VADriverContextP ctx,
3185                          struct i965_post_processing_context *pp_context)
3186 {
3187     struct i965_driver_data *i965 = i965_driver_data(ctx);
3188     unsigned char *constant_buffer;
3189     int param_size;
3190
3191     assert(sizeof(struct pp_static_parameter) == 128);
3192     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3193
3194     if (IS_GEN7(i965->intel.device_id))
3195         param_size = sizeof(struct gen7_pp_static_parameter);
3196     else
3197         param_size = sizeof(struct pp_static_parameter);
3198
3199     dri_bo_map(pp_context->curbe.bo, 1);
3200     assert(pp_context->curbe.bo->virtual);
3201     constant_buffer = pp_context->curbe.bo->virtual;
3202     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3203     dri_bo_unmap(pp_context->curbe.bo);
3204 }
3205
3206 static void
3207 gen6_pp_states_setup(VADriverContextP ctx,
3208                      struct i965_post_processing_context *pp_context)
3209 {
3210     gen6_pp_interface_descriptor_table(ctx, pp_context);
3211     gen6_pp_upload_constants(ctx, pp_context);
3212 }
3213
3214 static void
3215 gen6_pp_pipeline_select(VADriverContextP ctx,
3216                         struct i965_post_processing_context *pp_context)
3217 {
3218     struct intel_batchbuffer *batch = pp_context->batch;
3219
3220     BEGIN_BATCH(batch, 1);
3221     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3222     ADVANCE_BATCH(batch);
3223 }
3224
3225 static void
3226 gen6_pp_state_base_address(VADriverContextP ctx,
3227                            struct i965_post_processing_context *pp_context)
3228 {
3229     struct intel_batchbuffer *batch = pp_context->batch;
3230
3231     BEGIN_BATCH(batch, 10);
3232     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3233     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3234     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3235     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3236     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3237     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3238     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3239     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3240     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3241     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3242     ADVANCE_BATCH(batch);
3243 }
3244
3245 static void
3246 gen6_pp_vfe_state(VADriverContextP ctx,
3247                   struct i965_post_processing_context *pp_context)
3248 {
3249     struct intel_batchbuffer *batch = pp_context->batch;
3250
3251     BEGIN_BATCH(batch, 8);
3252     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3253     OUT_BATCH(batch, 0);
3254     OUT_BATCH(batch,
3255               (pp_context->urb.num_vfe_entries - 1) << 16 |
3256               pp_context->urb.num_vfe_entries << 8);
3257     OUT_BATCH(batch, 0);
3258     OUT_BATCH(batch,
3259               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3260               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3261     OUT_BATCH(batch, 0);
3262     OUT_BATCH(batch, 0);
3263     OUT_BATCH(batch, 0);
3264     ADVANCE_BATCH(batch);
3265 }
3266
3267 static void
3268 gen6_pp_curbe_load(VADriverContextP ctx,
3269                    struct i965_post_processing_context *pp_context)
3270 {
3271     struct intel_batchbuffer *batch = pp_context->batch;
3272
3273     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3274
3275     BEGIN_BATCH(batch, 4);
3276     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3277     OUT_BATCH(batch, 0);
3278     OUT_BATCH(batch,
3279               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3280     OUT_RELOC(batch,
3281               pp_context->curbe.bo,
3282               I915_GEM_DOMAIN_INSTRUCTION, 0,
3283               0);
3284     ADVANCE_BATCH(batch);
3285 }
3286
3287 static void
3288 gen6_interface_descriptor_load(VADriverContextP ctx,
3289                                struct i965_post_processing_context *pp_context)
3290 {
3291     struct intel_batchbuffer *batch = pp_context->batch;
3292
3293     BEGIN_BATCH(batch, 4);
3294     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3295     OUT_BATCH(batch, 0);
3296     OUT_BATCH(batch,
3297               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3298     OUT_RELOC(batch,
3299               pp_context->idrt.bo,
3300               I915_GEM_DOMAIN_INSTRUCTION, 0,
3301               0);
3302     ADVANCE_BATCH(batch);
3303 }
3304
3305 static void
3306 gen6_pp_object_walker(VADriverContextP ctx,
3307                       struct i965_post_processing_context *pp_context)
3308 {
3309     struct i965_driver_data *i965 = i965_driver_data(ctx);
3310     struct intel_batchbuffer *batch = pp_context->batch;
3311     int x, x_steps, y, y_steps;
3312     int param_size, command_length_in_dws;
3313     dri_bo *command_buffer;
3314     unsigned int *command_ptr;
3315
3316     if (IS_GEN7(i965->intel.device_id))
3317         param_size = sizeof(struct gen7_pp_inline_parameter);
3318     else
3319         param_size = sizeof(struct pp_inline_parameter);
3320
3321     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3322     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3323     command_length_in_dws = 6 + (param_size >> 2);
3324     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3325                                   "command objects buffer",
3326                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3327                                   4096);
3328
3329     dri_bo_map(command_buffer, 1);
3330     command_ptr = command_buffer->virtual;
3331
3332     for (y = 0; y < y_steps; y++) {
3333         for (x = 0; x < x_steps; x++) {
3334             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3335                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3336                 *command_ptr++ = 0;
3337                 *command_ptr++ = 0;
3338                 *command_ptr++ = 0;
3339                 *command_ptr++ = 0;
3340                 *command_ptr++ = 0;
3341                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3342                 command_ptr += (param_size >> 2);
3343             }
3344         }
3345     }
3346
3347     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3348         *command_ptr++ = 0;
3349
3350     *command_ptr = MI_BATCH_BUFFER_END;
3351
3352     dri_bo_unmap(command_buffer);
3353
3354     BEGIN_BATCH(batch, 2);
3355     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3356     OUT_RELOC(batch, command_buffer,
3357               I915_GEM_DOMAIN_COMMAND, 0,
3358               0);
3359     ADVANCE_BATCH(batch);
3360
3361     dri_bo_unreference(command_buffer);
3362
3363     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3364      * will cause control to pass back to ring buffer
3365      */
3366     intel_batchbuffer_end_atomic(batch);
3367     intel_batchbuffer_flush(batch);
3368     intel_batchbuffer_start_atomic(batch, 0x1000);
3369 }
3370
3371 static void
3372 gen6_pp_pipeline_setup(VADriverContextP ctx,
3373                        struct i965_post_processing_context *pp_context)
3374 {
3375     struct intel_batchbuffer *batch = pp_context->batch;
3376
3377     intel_batchbuffer_start_atomic(batch, 0x1000);
3378     intel_batchbuffer_emit_mi_flush(batch);
3379     gen6_pp_pipeline_select(ctx, pp_context);
3380     gen6_pp_state_base_address(ctx, pp_context);
3381     gen6_pp_vfe_state(ctx, pp_context);
3382     gen6_pp_curbe_load(ctx, pp_context);
3383     gen6_interface_descriptor_load(ctx, pp_context);
3384     gen6_pp_object_walker(ctx, pp_context);
3385     intel_batchbuffer_end_atomic(batch);
3386 }
3387
3388 static VAStatus
3389 gen6_post_processing(
3390     VADriverContextP   ctx,
3391     struct i965_post_processing_context *pp_context,
3392     const struct i965_surface *src_surface,
3393     const VARectangle *src_rect,
3394     struct i965_surface *dst_surface,
3395     const VARectangle *dst_rect,
3396     int                pp_index,
3397     void * filter_param
3398 )
3399 {
3400     VAStatus va_status;
3401
3402     va_status = gen6_pp_initialize(ctx, pp_context,
3403                                    src_surface,
3404                                    src_rect,
3405                                    dst_surface,
3406                                    dst_rect,
3407                                    pp_index,
3408                                    filter_param);
3409
3410     if (va_status == VA_STATUS_SUCCESS) {
3411         gen6_pp_states_setup(ctx, pp_context);
3412         gen6_pp_pipeline_setup(ctx, pp_context);
3413     }
3414
3415     return va_status;
3416 }
3417
3418 static VAStatus
3419 i965_post_processing_internal(
3420     VADriverContextP   ctx,
3421     struct i965_post_processing_context *pp_context,
3422     const struct i965_surface *src_surface,
3423     const VARectangle *src_rect,
3424     struct i965_surface *dst_surface,
3425     const VARectangle *dst_rect,
3426     int                pp_index,
3427     void *filter_param
3428 )
3429 {
3430     struct i965_driver_data *i965 = i965_driver_data(ctx);
3431     VAStatus va_status;
3432
3433     if (IS_GEN6(i965->intel.device_id) ||
3434         IS_GEN7(i965->intel.device_id))
3435         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3436     else
3437         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3438
3439     return va_status;
3440 }
3441
3442 VAStatus
3443 i965_DestroySurfaces(VADriverContextP ctx,
3444                      VASurfaceID *surface_list,
3445                      int num_surfaces);
3446 VAStatus
3447 i965_CreateSurfaces(VADriverContextP ctx,
3448                     int width,
3449                     int height,
3450                     int format,
3451                     int num_surfaces,
3452                     VASurfaceID *surfaces);
3453
3454 static void
3455 i965_vpp_clear_surface(VADriverContextP ctx,
3456                        struct i965_post_processing_context *pp_context,
3457                        VASurfaceID surface,
3458                        unsigned int color)
3459 {
3460     struct i965_driver_data *i965 = i965_driver_data(ctx);
3461     struct intel_batchbuffer *batch = pp_context->batch;
3462     struct object_surface *obj_surface = SURFACE(surface);
3463     unsigned int blt_cmd, br13;
3464     unsigned int tiling = 0, swizzle = 0;
3465     int pitch;
3466
3467     /* Currently only support NV12 surface */
3468     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3469         return;
3470
3471     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3472     blt_cmd = XY_COLOR_BLT_CMD;
3473     pitch = obj_surface->width;
3474
3475     if (tiling != I915_TILING_NONE) {
3476         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3477         pitch >>= 2;
3478     }
3479
3480     br13 = 0xf0 << 16;
3481     br13 |= BR13_8;
3482     br13 |= pitch;
3483
3484     if (IS_GEN6(i965->intel.device_id) ||
3485         IS_GEN7(i965->intel.device_id)) {
3486         intel_batchbuffer_start_atomic_blt(batch, 48);
3487         BEGIN_BLT_BATCH(batch, 12);
3488     } else {
3489         intel_batchbuffer_start_atomic(batch, 48);
3490         BEGIN_BATCH(batch, 12);
3491     }
3492
3493     OUT_BATCH(batch, blt_cmd);
3494     OUT_BATCH(batch, br13);
3495     OUT_BATCH(batch,
3496               0 << 16 |
3497               0);
3498     OUT_BATCH(batch,
3499               obj_surface->height << 16 |
3500               obj_surface->width);
3501     OUT_RELOC(batch, obj_surface->bo,
3502               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3503               0);
3504     OUT_BATCH(batch, 0x10);
3505
3506     OUT_BATCH(batch, blt_cmd);
3507     OUT_BATCH(batch, br13);
3508     OUT_BATCH(batch,
3509               0 << 16 |
3510               0);
3511     OUT_BATCH(batch,
3512               obj_surface->height / 2 << 16 |
3513               obj_surface->width);
3514     OUT_RELOC(batch, obj_surface->bo,
3515               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3516               obj_surface->width * obj_surface->y_cb_offset);
3517     OUT_BATCH(batch, 0x80);
3518
3519     ADVANCE_BATCH(batch);
3520     intel_batchbuffer_end_atomic(batch);
3521 }
3522
3523 VASurfaceID
3524 i965_post_processing(
3525     VADriverContextP   ctx,
3526     VASurfaceID        surface,
3527     const VARectangle *src_rect,
3528     const VARectangle *dst_rect,
3529     unsigned int       flags,
3530     int               *has_done_scaling
3531 )
3532 {
3533     struct i965_driver_data *i965 = i965_driver_data(ctx);
3534     VASurfaceID in_surface_id = surface;
3535     VASurfaceID out_surface_id = VA_INVALID_ID;
3536
3537     *has_done_scaling = 0;
3538
3539     if (HAS_PP(i965)) {
3540         struct object_surface *obj_surface;
3541         VAStatus status;
3542         struct i965_surface src_surface;
3543         struct i965_surface dst_surface;
3544
3545         obj_surface = SURFACE(in_surface_id);
3546
3547         /* Currently only support post processing for NV12 surface */
3548         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3549             return out_surface_id;
3550
3551         if (flags & I965_PP_FLAG_DEINTERLACING) {
3552             status = i965_CreateSurfaces(ctx,
3553                                          obj_surface->orig_width,
3554                                          obj_surface->orig_height,
3555                                          VA_RT_FORMAT_YUV420,
3556                                          1,
3557                                          &out_surface_id);
3558             assert(status == VA_STATUS_SUCCESS);
3559             obj_surface = SURFACE(out_surface_id);
3560             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3561             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3562             src_surface.id = in_surface_id;
3563             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3564             src_surface.flags = (flags & I965_PP_FLAG_DEINTERLACING_TOP_FISRT) ?
3565                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3566             dst_surface.id = out_surface_id;
3567             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3568             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3569
3570             i965_post_processing_internal(ctx, i965->pp_context,
3571                                           &src_surface,
3572                                           src_rect,
3573                                           &dst_surface,
3574                                           dst_rect,
3575                                           PP_NV12_DNDI,
3576                                           NULL);
3577         }
3578
3579         if (flags & I965_PP_FLAG_AVS) {
3580             struct i965_render_state *render_state = &i965->render_state;
3581             struct intel_region *dest_region = render_state->draw_region;
3582
3583             if (out_surface_id != VA_INVALID_ID)
3584                 in_surface_id = out_surface_id;
3585
3586             status = i965_CreateSurfaces(ctx,
3587                                          dest_region->width,
3588                                          dest_region->height,
3589                                          VA_RT_FORMAT_YUV420,
3590                                          1,
3591                                          &out_surface_id);
3592             assert(status == VA_STATUS_SUCCESS);
3593             obj_surface = SURFACE(out_surface_id);
3594             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3595             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3596             src_surface.id = in_surface_id;
3597             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3598             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3599             dst_surface.id = out_surface_id;
3600             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3601             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3602
3603             i965_post_processing_internal(ctx, i965->pp_context,
3604                                           &src_surface,
3605                                           src_rect,
3606                                           &dst_surface,
3607                                           dst_rect,
3608                                           PP_NV12_AVS,
3609                                           NULL);
3610
3611             if (in_surface_id != surface)
3612                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3613
3614             *has_done_scaling = 1;
3615         }
3616     }
3617
3618     return out_surface_id;
3619 }
3620
3621 static VAStatus
3622 i965_image_pl3_processing(VADriverContextP ctx,
3623                           const struct i965_surface *src_surface,
3624                           const VARectangle *src_rect,
3625                           struct i965_surface *dst_surface,
3626                           const VARectangle *dst_rect)
3627 {
3628     struct i965_driver_data *i965 = i965_driver_data(ctx);
3629     struct i965_post_processing_context *pp_context = i965->pp_context;
3630     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3631
3632     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3633         i965_post_processing_internal(ctx, i965->pp_context,
3634                                       src_surface,
3635                                       src_rect,
3636                                       dst_surface,
3637                                       dst_rect,
3638                                       PP_PL3_LOAD_SAVE_N12,
3639                                       NULL);
3640     } else {
3641         i965_post_processing_internal(ctx, i965->pp_context,
3642                                       src_surface,
3643                                       src_rect,
3644                                       dst_surface,
3645                                       dst_rect,
3646                                       PP_PL3_LOAD_SAVE_PL3,
3647                                       NULL);
3648     }
3649
3650     intel_batchbuffer_flush(pp_context->batch);
3651
3652     return VA_STATUS_SUCCESS;
3653 }
3654
3655 static VAStatus
3656 i965_image_pl2_processing(VADriverContextP ctx,
3657                           const struct i965_surface *src_surface,
3658                           const VARectangle *src_rect,
3659                           struct i965_surface *dst_surface,
3660                           const VARectangle *dst_rect)
3661 {
3662     struct i965_driver_data *i965 = i965_driver_data(ctx);
3663     struct i965_post_processing_context *pp_context = i965->pp_context;
3664     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3665
3666     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3667         i965_post_processing_internal(ctx, i965->pp_context,
3668                                       src_surface,
3669                                       src_rect,
3670                                       dst_surface,
3671                                       dst_rect,
3672                                       PP_NV12_LOAD_SAVE_N12,
3673                                       NULL);
3674     } else {
3675         i965_post_processing_internal(ctx, i965->pp_context,
3676                                       src_surface,
3677                                       src_rect,
3678                                       dst_surface,
3679                                       dst_rect,
3680                                       PP_NV12_LOAD_SAVE_PL3,
3681                                       NULL);
3682     }
3683
3684     intel_batchbuffer_flush(pp_context->batch);
3685
3686     return VA_STATUS_SUCCESS;
3687 }
3688
3689 VAStatus
3690 i965_image_processing(VADriverContextP ctx,
3691                       const struct i965_surface *src_surface,
3692                       const VARectangle *src_rect,
3693                       struct i965_surface *dst_surface,
3694                       const VARectangle *dst_rect)
3695 {
3696     struct i965_driver_data *i965 = i965_driver_data(ctx);
3697     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
3698
3699     if (HAS_PP(i965)) {
3700         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
3701
3702         switch (fourcc) {
3703         case VA_FOURCC('Y', 'V', '1', '2'):
3704         case VA_FOURCC('I', '4', '2', '0'):
3705         case VA_FOURCC('I', 'M', 'C', '1'):
3706         case VA_FOURCC('I', 'M', 'C', '3'):
3707             status = i965_image_pl3_processing(ctx,
3708                                                src_surface,
3709                                                src_rect,
3710                                                dst_surface,
3711                                                dst_rect);
3712             break;
3713
3714         case  VA_FOURCC('N', 'V', '1', '2'):
3715             status = i965_image_pl2_processing(ctx,
3716                                                src_surface,
3717                                                src_rect,
3718                                                dst_surface,
3719                                                dst_rect);
3720             break;
3721
3722         default:
3723             status = VA_STATUS_ERROR_UNIMPLEMENTED;
3724             break;
3725         }
3726     }
3727
3728     return status;
3729 }
3730
3731 static void
3732 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
3733 {
3734     int i;
3735
3736     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3737     pp_context->surface_state_binding_table.bo = NULL;
3738
3739     dri_bo_unreference(pp_context->curbe.bo);
3740     pp_context->curbe.bo = NULL;
3741
3742     dri_bo_unreference(pp_context->sampler_state_table.bo);
3743     pp_context->sampler_state_table.bo = NULL;
3744
3745     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3746     pp_context->sampler_state_table.bo_8x8 = NULL;
3747
3748     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3749     pp_context->sampler_state_table.bo_8x8_uv = NULL;
3750
3751     dri_bo_unreference(pp_context->idrt.bo);
3752     pp_context->idrt.bo = NULL;
3753     pp_context->idrt.num_interface_descriptors = 0;
3754
3755     dri_bo_unreference(pp_context->vfe_state.bo);
3756     pp_context->vfe_state.bo = NULL;
3757
3758     dri_bo_unreference(pp_context->stmm.bo);
3759     pp_context->stmm.bo = NULL;
3760
3761     for (i = 0; i < NUM_PP_MODULES; i++) {
3762         struct pp_module *pp_module = &pp_context->pp_modules[i];
3763
3764         dri_bo_unreference(pp_module->kernel.bo);
3765         pp_module->kernel.bo = NULL;
3766     }
3767
3768     free(pp_context->pp_static_parameter);
3769     free(pp_context->pp_inline_parameter);
3770     pp_context->pp_static_parameter = NULL;
3771     pp_context->pp_inline_parameter = NULL;
3772 }
3773
3774 Bool
3775 i965_post_processing_terminate(VADriverContextP ctx)
3776 {
3777     struct i965_driver_data *i965 = i965_driver_data(ctx);
3778     struct i965_post_processing_context *pp_context = i965->pp_context;
3779
3780     if (pp_context) {
3781         i965_post_processing_context_finalize(pp_context);
3782         free(pp_context);
3783     }
3784
3785     i965->pp_context = NULL;
3786
3787     return True;
3788 }
3789
3790 static void
3791 i965_post_processing_context_init(VADriverContextP ctx,
3792                                   struct i965_post_processing_context *pp_context,
3793                                   struct intel_batchbuffer *batch)
3794 {
3795     struct i965_driver_data *i965 = i965_driver_data(ctx);
3796     int i;
3797
3798     pp_context->urb.size = URB_SIZE((&i965->intel));
3799     pp_context->urb.num_vfe_entries = 32;
3800     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
3801     pp_context->urb.num_cs_entries = 1;
3802
3803     if (IS_GEN7(i965->intel.device_id))
3804         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
3805     else
3806         pp_context->urb.size_cs_entry = 2;
3807
3808     pp_context->urb.vfe_start = 0;
3809     pp_context->urb.cs_start = pp_context->urb.vfe_start +
3810         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
3811     assert(pp_context->urb.cs_start +
3812            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
3813
3814     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
3815     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
3816     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
3817
3818     if (IS_GEN7(i965->intel.device_id))
3819         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
3820     else if (IS_GEN6(i965->intel.device_id))
3821         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
3822     else if (IS_IRONLAKE(i965->intel.device_id))
3823         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
3824
3825     for (i = 0; i < NUM_PP_MODULES; i++) {
3826         struct pp_module *pp_module = &pp_context->pp_modules[i];
3827         dri_bo_unreference(pp_module->kernel.bo);
3828         if (pp_module->kernel.bin && pp_module->kernel.size) {
3829             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
3830                                                 pp_module->kernel.name,
3831                                                 pp_module->kernel.size,
3832                                                 4096);
3833             assert(pp_module->kernel.bo);
3834             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
3835         } else {
3836             pp_module->kernel.bo = NULL;
3837         }
3838     }
3839
3840     /* static & inline parameters */
3841     if (IS_GEN7(i965->intel.device_id)) {
3842         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
3843         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
3844     } else {
3845         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
3846         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
3847     }
3848
3849     pp_context->batch = batch;
3850 }
3851
3852 Bool
3853 i965_post_processing_init(VADriverContextP ctx)
3854 {
3855     struct i965_driver_data *i965 = i965_driver_data(ctx);
3856     struct i965_post_processing_context *pp_context = i965->pp_context;
3857
3858     if (HAS_PP(i965)) {
3859         if (pp_context == NULL) {
3860             pp_context = calloc(1, sizeof(*pp_context));
3861             i965_post_processing_context_init(ctx, pp_context, i965->batch);
3862             i965->pp_context = pp_context;
3863         }
3864     }
3865
3866     return True;
3867 }
3868
3869 static const int procfilter_to_pp_flag[10] = {
3870     PP_NULL,    /* VAProcFilterNone */
3871     PP_NULL,    /* VAProcFilterDering */
3872     PP_NULL,    /* VAProcFilterDeblocking */
3873     PP_NV12_DN, /* VAProcFilterNoiseReduction */
3874     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
3875     PP_NULL,    /* VAProcFilterSharpening */
3876     PP_NULL,    /* VAProcFilterColorEnhancement */
3877     PP_NULL,    /* VAProcFilterProcAmp */
3878     PP_NULL,    /* VAProcFilterComposition */
3879     PP_NULL,    /* VAProcFilterFrameRateConversion */
3880 };
3881
3882 static const int proc_frame_to_pp_frame[3] = {
3883     I965_SURFACE_FLAG_FRAME,
3884     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
3885     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
3886 };
3887
3888 static void
3889 i965_proc_picture(VADriverContextP ctx,
3890                   VAProfile profile,
3891                   union codec_state *codec_state,
3892                   struct hw_context *hw_context)
3893 {
3894     struct i965_driver_data *i965 = i965_driver_data(ctx);
3895     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
3896     struct proc_state *proc_state = &codec_state->proc;
3897     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
3898     struct object_surface *obj_surface;
3899     struct i965_surface src_surface, dst_surface;
3900     VARectangle src_rect, dst_rect;
3901     VAStatus status;
3902     int i;
3903     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
3904     int num_tmp_surfaces = 0;
3905     unsigned int tiling = 0, swizzle = 0;
3906     int in_width, in_height;
3907
3908     assert(pipeline_param->surface != VA_INVALID_ID);
3909     assert(proc_state->current_render_target != VA_INVALID_ID);
3910
3911     obj_surface = SURFACE(pipeline_param->surface);
3912     in_width = obj_surface->orig_width;
3913     in_height = obj_surface->orig_height;
3914     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3915
3916     src_surface.id = pipeline_param->surface;
3917     src_surface.type = I965_SURFACE_TYPE_SURFACE;
3918     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
3919
3920     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
3921         VASurfaceID out_surface_id = VA_INVALID_ID;
3922
3923         src_surface.id = pipeline_param->surface;
3924         src_surface.type = I965_SURFACE_TYPE_SURFACE;
3925         src_surface.flags = I965_SURFACE_FLAG_FRAME;
3926         src_rect.x = 0;
3927         src_rect.y = 0;
3928         src_rect.width = in_width;
3929         src_rect.height = in_height;
3930
3931         status = i965_CreateSurfaces(ctx,
3932                                      in_width,
3933                                      in_height,
3934                                      VA_RT_FORMAT_YUV420,
3935                                      1,
3936                                      &out_surface_id);
3937         assert(status == VA_STATUS_SUCCESS);
3938         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
3939         obj_surface = SURFACE(out_surface_id);
3940         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
3941
3942         dst_surface.id = out_surface_id;
3943         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3944         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3945         dst_rect.x = 0;
3946         dst_rect.y = 0;
3947         dst_rect.width = in_width;
3948         dst_rect.height = in_height;
3949
3950         status = i965_image_processing(ctx,
3951                                        &src_surface,
3952                                        &src_rect,
3953                                        &dst_surface,
3954                                        &dst_rect);
3955         assert(status == VA_STATUS_SUCCESS);
3956
3957         src_surface.id = out_surface_id;
3958         src_surface.type = I965_SURFACE_TYPE_SURFACE;
3959         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
3960     }
3961
3962     if (pipeline_param->surface_region) {
3963         src_rect.x = pipeline_param->surface_region->x;
3964         src_rect.y = pipeline_param->surface_region->y;
3965         src_rect.width = pipeline_param->surface_region->width;
3966         src_rect.height = pipeline_param->surface_region->height;
3967     } else {
3968         src_rect.x = 0;
3969         src_rect.y = 0;
3970         src_rect.width = in_width;
3971         src_rect.height = in_height;
3972     }
3973
3974     if (pipeline_param->output_region) {
3975         dst_rect.x = pipeline_param->output_region->x;
3976         dst_rect.y = pipeline_param->output_region->y;
3977         dst_rect.width = pipeline_param->output_region->width;
3978         dst_rect.height = pipeline_param->output_region->height;
3979     } else {
3980         dst_rect.x = 0;
3981         dst_rect.y = 0;
3982         dst_rect.width = in_width;
3983         dst_rect.height = in_height;
3984     }
3985
3986     obj_surface = SURFACE(proc_state->current_render_target);
3987     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3988
3989     for (i = 0; i < pipeline_param->num_filters; i++) {
3990         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
3991         VAProcFilterParameterBufferBase *base = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
3992         VAProcFilterType filter_type = base->type;
3993         VASurfaceID out_surface_id = VA_INVALID_ID;
3994         void *filter_param = NULL;
3995
3996         if (procfilter_to_pp_flag[filter_type] != PP_NULL) {
3997             if (proc_state->filter_param[filter_type])
3998                 filter_param = proc_state->filter_param[filter_type]->buffer;
3999
4000             status = i965_CreateSurfaces(ctx,
4001                                          in_width,
4002                                          in_height,
4003                                          VA_RT_FORMAT_YUV420,
4004                                          1,
4005                                          &out_surface_id);
4006             assert(status == VA_STATUS_SUCCESS);
4007             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4008             obj_surface = SURFACE(out_surface_id);
4009             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4010             dst_surface.id = out_surface_id;
4011             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4012             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4013                                                    &src_surface,
4014                                                    &src_rect,
4015                                                    &dst_surface,
4016                                                    &src_rect,
4017                                                    procfilter_to_pp_flag[filter_type],
4018                                                    filter_param);
4019
4020             if (status == VA_STATUS_SUCCESS) {
4021                 src_surface.id = dst_surface.id;
4022                 src_surface.type = dst_surface.type;
4023                 src_surface.flags = dst_surface.flags;
4024             }
4025         }
4026     }
4027
4028     dst_surface.id = proc_state->current_render_target;
4029     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4030     i965_post_processing_internal(ctx, &proc_context->pp_context,
4031                                   &src_surface,
4032                                   &src_rect,
4033                                   &dst_surface,
4034                                   &dst_rect,
4035                                   (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4036                                   PP_NV12_AVS : PP_NV12_SCALING,
4037                                   NULL);
4038
4039     if (num_tmp_surfaces)
4040         i965_DestroySurfaces(ctx,
4041                              tmp_surfaces,
4042                              num_tmp_surfaces);
4043
4044     intel_batchbuffer_flush(hw_context->batch);
4045 }
4046
4047 static void
4048 i965_proc_context_destroy(void *hw_context)
4049 {
4050     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4051
4052     i965_post_processing_context_finalize(&proc_context->pp_context);
4053     intel_batchbuffer_free(proc_context->base.batch);
4054     free(proc_context);
4055 }
4056
4057 struct hw_context *
4058 i965_proc_context_init(VADriverContextP ctx, VAProfile profile)
4059 {
4060     struct intel_driver_data *intel = intel_driver_data(ctx);
4061     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4062
4063     proc_context->base.destroy = i965_proc_context_destroy;
4064     proc_context->base.run = i965_proc_picture;
4065     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4066     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4067
4068     return (struct hw_context *)proc_context;
4069 }