src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = {
 111 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5"
 112 };
 113
 114 static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = {
 115 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5"
 116 };
 117
 118 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                    const struct i965_surface *src_surface,
 120                                    const VARectangle *src_rect,
 121                                    struct i965_surface *dst_surface,
 122                                    const VARectangle *dst_rect,
 123                                    void *filter_param);
 124 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                             const struct i965_surface *src_surface,
 126                                             const VARectangle *src_rect,
 127                                             struct i965_surface *dst_surface,
 128                                             const VARectangle *dst_rect,
 129                                             void *filter_param);
 130 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 131                                            const struct i965_surface *src_surface,
 132                                            const VARectangle *src_rect,
 133                                            struct i965_surface *dst_surface,
 134                                            const VARectangle *dst_rect,
 135                                            void *filter_param);
 136 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 137                                              const struct i965_surface *src_surface,
 138                                              const VARectangle *src_rect,
 139                                              struct i965_surface *dst_surface,
 140                                              const VARectangle *dst_rect,
 141                                              void *filter_param);
 142 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 143                                                 const struct i965_surface *src_surface,
 144                                                 const VARectangle *src_rect,
 145                                                 struct i965_surface *dst_surface,
 146                                                 const VARectangle *dst_rect,
 147                                                 void *filter_param);
 148 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 149                                         const struct i965_surface *src_surface,
 150                                         const VARectangle *src_rect,
 151                                         struct i965_surface *dst_surface,
 152                                         const VARectangle *dst_rect,
 153                                         void *filter_param);
 154 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 155                                       const struct i965_surface *src_surface,
 156                                       const VARectangle *src_rect,
 157                                       struct i965_surface *dst_surface,
 158                                       const VARectangle *dst_rect,
 159                                       void *filter_param);
 160
 161 static struct pp_module pp_modules_gen5[] = {
 162     {
 163         {
 164             "NULL module (for testing)",
 165             PP_NULL,
 166             pp_null_gen5,
 167             sizeof(pp_null_gen5),
 168             NULL,
 169         },
 170
 171         pp_null_initialize,
 172     },
 173
 174     {
 175         {
 176             "NV12_NV12",
 177             PP_NV12_LOAD_SAVE_N12,
 178             pp_nv12_load_save_nv12_gen5,
 179             sizeof(pp_nv12_load_save_nv12_gen5),
 180             NULL,
 181         },
 182
 183         pp_plx_load_save_plx_initialize,
 184     },
 185
 186     {
 187         {
 188             "NV12_PL3",
 189             PP_NV12_LOAD_SAVE_PL3,
 190             pp_nv12_load_save_pl3_gen5,
 191             sizeof(pp_nv12_load_save_pl3_gen5),
 192             NULL,
 193         },
 194
 195         pp_plx_load_save_plx_initialize,
 196     },
 197
 198     {
 199         {
 200             "PL3_NV12",
 201             PP_PL3_LOAD_SAVE_N12,
 202             pp_pl3_load_save_nv12_gen5,
 203             sizeof(pp_pl3_load_save_nv12_gen5),
 204             NULL,
 205         },
 206
 207         pp_plx_load_save_plx_initialize,
 208     },
 209
 210     {
 211         {
 212             "PL3_PL3",
 213             PP_PL3_LOAD_SAVE_N12,
 214             pp_pl3_load_save_pl3_gen5,
 215             sizeof(pp_pl3_load_save_pl3_gen5),
 216             NULL,
 217         },
 218
 219         pp_plx_load_save_plx_initialize
 220     },
 221
 222     {
 223         {
 224             "NV12 Scaling module",
 225             PP_NV12_SCALING,
 226             pp_nv12_scaling_gen5,
 227             sizeof(pp_nv12_scaling_gen5),
 228             NULL,
 229         },
 230
 231         pp_nv12_scaling_initialize,
 232     },
 233
 234     {
 235         {
 236             "NV12 AVS module",
 237             PP_NV12_AVS,
 238             pp_nv12_avs_gen5,
 239             sizeof(pp_nv12_avs_gen5),
 240             NULL,
 241         },
 242
 243         pp_nv12_avs_initialize_nlas,
 244     },
 245
 246     {
 247         {
 248             "NV12 DNDI module",
 249             PP_NV12_DNDI,
 250             pp_nv12_dndi_gen5,
 251             sizeof(pp_nv12_dndi_gen5),
 252             NULL,
 253         },
 254
 255         pp_nv12_dndi_initialize,
 256     },
 257
 258     {
 259         {
 260             "NV12 DN module",
 261             PP_NV12_DN,
 262             pp_nv12_dn_gen5,
 263             sizeof(pp_nv12_dn_gen5),
 264             NULL,
 265         },
 266
 267         pp_nv12_dn_initialize,
 268     },
 269
 270     {
 271         {
 272             "NV12_PA module",
 273             PP_NV12_LOAD_SAVE_PA,
 274             pp_nv12_load_save_pa_gen5,
 275             sizeof(pp_nv12_load_save_pa_gen5),
 276             NULL,
 277         },
 278
 279         pp_plx_load_save_plx_initialize,
 280     },
 281
 282     {
 283         {
 284             "PL3_PA module",
 285             PP_PL3_LOAD_SAVE_PA,
 286             pp_pl3_load_save_pa_gen5,
 287             sizeof(pp_pl3_load_save_pa_gen5),
 288             NULL,
 289         },
 290
 291         pp_plx_load_save_plx_initialize,
 292     },
 293
 294     {
 295         {
 296             "PA_NV12 module",
 297             PP_PA_LOAD_SAVE_NV12,
 298             pp_pa_load_save_nv12_gen5,
 299             sizeof(pp_pa_load_save_nv12_gen5),
 300             NULL,
 301         },
 302
 303         pp_plx_load_save_plx_initialize,
 304     },
 305
 306     {
 307         {
 308             "PA_PL3 module",
 309             PP_PA_LOAD_SAVE_PL3,
 310             pp_pa_load_save_pl3_gen5,
 311             sizeof(pp_pa_load_save_pl3_gen5),
 312             NULL,
 313         },
 314
 315         pp_plx_load_save_plx_initialize,
 316     },
 317
 318     {
 319         {
 320             "RGBX_NV12 module",
 321             PP_RGBX_LOAD_SAVE_NV12,
 322             pp_rgbx_load_save_nv12_gen5,
 323             sizeof(pp_rgbx_load_save_nv12_gen5),
 324             NULL,
 325         },
 326
 327         pp_plx_load_save_plx_initialize,
 328     },
 329
 330     {
 331         {
 332             "NV12_RGBX module",
 333             PP_NV12_LOAD_SAVE_RGBX,
 334             pp_nv12_load_save_rgbx_gen5,
 335             sizeof(pp_nv12_load_save_rgbx_gen5),
 336             NULL,
 337         },
 338
 339         pp_plx_load_save_plx_initialize,
 340     },
 341
 342 };
 343
 344 static const uint32_t pp_null_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/null.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 350 };
 351
 352 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 354 };
 355
 356 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 362 };
 363
 364 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 365 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 366 };
 367
 368 static const uint32_t pp_nv12_avs_gen6[][4] = {
 369 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 370 };
 371
 372 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 373 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 374 };
 375
 376 static const uint32_t pp_nv12_dn_gen6[][4] = {
 377 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 378 };
 379
 380 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 381 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 382 };
 383
 384 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 385 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 386 };
 387
 388 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 389 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 390 };
 391
 392 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 393 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 394 };
 395
 396 static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = {
 397 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b"
 398 };
 399
 400 static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = {
 401 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b"
 402 };
 403
 404 static struct pp_module pp_modules_gen6[] = {
 405     {
 406         {
 407             "NULL module (for testing)",
 408             PP_NULL,
 409             pp_null_gen6,
 410             sizeof(pp_null_gen6),
 411             NULL,
 412         },
 413
 414         pp_null_initialize,
 415     },
 416
 417     {
 418         {
 419             "NV12_NV12",
 420             PP_NV12_LOAD_SAVE_N12,
 421             pp_nv12_load_save_nv12_gen6,
 422             sizeof(pp_nv12_load_save_nv12_gen6),
 423             NULL,
 424         },
 425
 426         pp_plx_load_save_plx_initialize,
 427     },
 428
 429     {
 430         {
 431             "NV12_PL3",
 432             PP_NV12_LOAD_SAVE_PL3,
 433             pp_nv12_load_save_pl3_gen6,
 434             sizeof(pp_nv12_load_save_pl3_gen6),
 435             NULL,
 436         },
 437
 438         pp_plx_load_save_plx_initialize,
 439     },
 440
 441     {
 442         {
 443             "PL3_NV12",
 444             PP_PL3_LOAD_SAVE_N12,
 445             pp_pl3_load_save_nv12_gen6,
 446             sizeof(pp_pl3_load_save_nv12_gen6),
 447             NULL,
 448         },
 449
 450         pp_plx_load_save_plx_initialize,
 451     },
 452
 453     {
 454         {
 455             "PL3_PL3",
 456             PP_PL3_LOAD_SAVE_N12,
 457             pp_pl3_load_save_pl3_gen6,
 458             sizeof(pp_pl3_load_save_pl3_gen6),
 459             NULL,
 460         },
 461
 462         pp_plx_load_save_plx_initialize,
 463     },
 464
 465     {
 466         {
 467             "NV12 Scaling module",
 468             PP_NV12_SCALING,
 469             pp_nv12_scaling_gen6,
 470             sizeof(pp_nv12_scaling_gen6),
 471             NULL,
 472         },
 473
 474         gen6_nv12_scaling_initialize,
 475     },
 476
 477     {
 478         {
 479             "NV12 AVS module",
 480             PP_NV12_AVS,
 481             pp_nv12_avs_gen6,
 482             sizeof(pp_nv12_avs_gen6),
 483             NULL,
 484         },
 485
 486         pp_nv12_avs_initialize_nlas,
 487     },
 488
 489     {
 490         {
 491             "NV12 DNDI module",
 492             PP_NV12_DNDI,
 493             pp_nv12_dndi_gen6,
 494             sizeof(pp_nv12_dndi_gen6),
 495             NULL,
 496         },
 497
 498         pp_nv12_dndi_initialize,
 499     },
 500
 501     {
 502         {
 503             "NV12 DN module",
 504             PP_NV12_DN,
 505             pp_nv12_dn_gen6,
 506             sizeof(pp_nv12_dn_gen6),
 507             NULL,
 508         },
 509
 510         pp_nv12_dn_initialize,
 511     },
 512     {
 513         {
 514             "NV12_PA module",
 515             PP_NV12_LOAD_SAVE_PA,
 516             pp_nv12_load_save_pa_gen6,
 517             sizeof(pp_nv12_load_save_pa_gen6),
 518             NULL,
 519         },
 520
 521         pp_plx_load_save_plx_initialize,
 522     },
 523
 524     {
 525         {
 526             "PL3_PA module",
 527             PP_PL3_LOAD_SAVE_PA,
 528             pp_pl3_load_save_pa_gen6,
 529             sizeof(pp_pl3_load_save_pa_gen6),
 530             NULL,
 531         },
 532
 533         pp_plx_load_save_plx_initialize,
 534     },
 535
 536     {
 537         {
 538             "PA_NV12 module",
 539             PP_PA_LOAD_SAVE_NV12,
 540             pp_pa_load_save_nv12_gen6,
 541             sizeof(pp_pa_load_save_nv12_gen6),
 542             NULL,
 543         },
 544
 545         pp_plx_load_save_plx_initialize,
 546     },
 547
 548     {
 549         {
 550             "PA_PL3 module",
 551             PP_PA_LOAD_SAVE_PL3,
 552             pp_pa_load_save_pl3_gen6,
 553             sizeof(pp_pa_load_save_pl3_gen6),
 554             NULL,
 555         },
 556
 557         pp_plx_load_save_plx_initialize,
 558     },
 559
 560     {
 561         {
 562             "RGBX_NV12 module",
 563             PP_RGBX_LOAD_SAVE_NV12,
 564             pp_rgbx_load_save_nv12_gen6,
 565             sizeof(pp_rgbx_load_save_nv12_gen6),
 566             NULL,
 567         },
 568
 569         pp_plx_load_save_plx_initialize,
 570     },
 571
 572     {
 573         {
 574             "NV12_RGBX module",
 575             PP_NV12_LOAD_SAVE_RGBX,
 576             pp_nv12_load_save_rgbx_gen6,
 577             sizeof(pp_nv12_load_save_rgbx_gen6),
 578             NULL,
 579         },
 580
 581         pp_plx_load_save_plx_initialize,
 582     },
 583 };
 584
 585 static const uint32_t pp_null_gen7[][4] = {
 586 };
 587
 588 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 589 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 590 };
 591
 592 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 593 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 594 };
 595
 596 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 597 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 598 };
 599
 600 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 601 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 602 };
 603
 604 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 605 #include "shaders/post_processing/gen7/avs.g7b"
 606 };
 607
 608 static const uint32_t pp_nv12_avs_gen7[][4] = {
 609 #include "shaders/post_processing/gen7/avs.g7b"
 610 };
 611
 612 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 613 #include "shaders/post_processing/gen7/dndi.g7b"
 614 };
 615
 616 static const uint32_t pp_nv12_dn_gen7[][4] = {
 617 #include "shaders/post_processing/gen7/nv12_dn_nv12.g7b"
 618 };
 619 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 620 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 621 };
 622 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 623 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 624 };
 625 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 626 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 627 };
 628 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 629 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 630 };
 631 static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = {
 632 };
 633 static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = {
 634 };
 635
 636 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 637                                            const struct i965_surface *src_surface,
 638                                            const VARectangle *src_rect,
 639                                            struct i965_surface *dst_surface,
 640                                            const VARectangle *dst_rect,
 641                                            void *filter_param);
 642 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 643                                              const struct i965_surface *src_surface,
 644                                              const VARectangle *src_rect,
 645                                              struct i965_surface *dst_surface,
 646                                              const VARectangle *dst_rect,
 647                                              void *filter_param);
 648 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 649                                            const struct i965_surface *src_surface,
 650                                            const VARectangle *src_rect,
 651                                            struct i965_surface *dst_surface,
 652                                            const VARectangle *dst_rect,
 653                                            void *filter_param);
 654
 655 static struct pp_module pp_modules_gen7[] = {
 656     {
 657         {
 658             "NULL module (for testing)",
 659             PP_NULL,
 660             pp_null_gen7,
 661             sizeof(pp_null_gen7),
 662             NULL,
 663         },
 664
 665         pp_null_initialize,
 666     },
 667
 668     {
 669         {
 670             "NV12_NV12",
 671             PP_NV12_LOAD_SAVE_N12,
 672             pp_nv12_load_save_nv12_gen7,
 673             sizeof(pp_nv12_load_save_nv12_gen7),
 674             NULL,
 675         },
 676
 677         gen7_pp_plx_avs_initialize,
 678     },
 679
 680     {
 681         {
 682             "NV12_PL3",
 683             PP_NV12_LOAD_SAVE_PL3,
 684             pp_nv12_load_save_pl3_gen7,
 685             sizeof(pp_nv12_load_save_pl3_gen7),
 686             NULL,
 687         },
 688
 689         gen7_pp_plx_avs_initialize,
 690     },
 691
 692     {
 693         {
 694             "PL3_NV12",
 695             PP_PL3_LOAD_SAVE_N12,
 696             pp_pl3_load_save_nv12_gen7,
 697             sizeof(pp_pl3_load_save_nv12_gen7),
 698             NULL,
 699         },
 700
 701         gen7_pp_plx_avs_initialize,
 702     },
 703
 704     {
 705         {
 706             "PL3_PL3",
 707             PP_PL3_LOAD_SAVE_N12,
 708             pp_pl3_load_save_pl3_gen7,
 709             sizeof(pp_pl3_load_save_pl3_gen7),
 710             NULL,
 711         },
 712
 713         gen7_pp_plx_avs_initialize,
 714     },
 715
 716     {
 717         {
 718             "NV12 Scaling module",
 719             PP_NV12_SCALING,
 720             pp_nv12_scaling_gen7,
 721             sizeof(pp_nv12_scaling_gen7),
 722             NULL,
 723         },
 724
 725         gen7_pp_plx_avs_initialize,
 726     },
 727
 728     {
 729         {
 730             "NV12 AVS module",
 731             PP_NV12_AVS,
 732             pp_nv12_avs_gen7,
 733             sizeof(pp_nv12_avs_gen7),
 734             NULL,
 735         },
 736
 737         gen7_pp_plx_avs_initialize,
 738     },
 739
 740     {
 741         {
 742             "NV12 DNDI module",
 743             PP_NV12_DNDI,
 744             pp_nv12_dndi_gen7,
 745             sizeof(pp_nv12_dndi_gen7),
 746             NULL,
 747         },
 748
 749         gen7_pp_nv12_dndi_initialize,
 750     },
 751
 752     {
 753         {
 754             "NV12 DN module",
 755             PP_NV12_DN,
 756             pp_nv12_dn_gen7,
 757             sizeof(pp_nv12_dn_gen7),
 758             NULL,
 759         },
 760
 761         gen7_pp_nv12_dn_initialize,
 762     },
 763     {
 764         {
 765             "NV12_PA module",
 766             PP_NV12_LOAD_SAVE_PA,
 767             pp_nv12_load_save_pa_gen7,
 768             sizeof(pp_nv12_load_save_pa_gen7),
 769             NULL,
 770         },
 771
 772         gen7_pp_plx_avs_initialize,
 773     },
 774
 775     {
 776         {
 777             "PL3_PA module",
 778             PP_PL3_LOAD_SAVE_PA,
 779             pp_pl3_load_save_pa_gen7,
 780             sizeof(pp_pl3_load_save_pa_gen7),
 781             NULL,
 782         },
 783
 784         gen7_pp_plx_avs_initialize,
 785     },
 786
 787     {
 788         {
 789             "PA_NV12 module",
 790             PP_PA_LOAD_SAVE_NV12,
 791             pp_pa_load_save_nv12_gen7,
 792             sizeof(pp_pa_load_save_nv12_gen7),
 793             NULL,
 794         },
 795
 796         gen7_pp_plx_avs_initialize,
 797     },
 798
 799     {
 800         {
 801             "PA_PL3 module",
 802             PP_PA_LOAD_SAVE_PL3,
 803             pp_pa_load_save_pl3_gen7,
 804             sizeof(pp_pa_load_save_pl3_gen7),
 805             NULL,
 806         },
 807
 808         gen7_pp_plx_avs_initialize,
 809     },
 810
 811     {
 812         {
 813             "RGBX_NV12 module",
 814             PP_RGBX_LOAD_SAVE_NV12,
 815             pp_rgbx_load_save_nv12_gen7,
 816             sizeof(pp_rgbx_load_save_nv12_gen7),
 817             NULL,
 818         },
 819
 820         pp_plx_load_save_plx_initialize,
 821     },
 822
 823     {
 824         {
 825             "NV12_RGBX module",
 826             PP_NV12_LOAD_SAVE_RGBX,
 827             pp_nv12_load_save_rgbx_gen7,
 828             sizeof(pp_nv12_load_save_rgbx_gen7),
 829             NULL,
 830         },
 831
 832         pp_plx_load_save_plx_initialize,
 833     },
 834
 835 };
 836
 837 static int
 838 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 839 {
 840     struct i965_driver_data *i965 = i965_driver_data(ctx);
 841     int fourcc;
 842
 843     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 844         struct object_image *obj_image = IMAGE(surface->id);
 845         fourcc = obj_image->image.format.fourcc;
 846     } else {
 847         struct object_surface *obj_surface = SURFACE(surface->id);
 848         fourcc = obj_surface->fourcc;
 849     }
 850
 851     return fourcc;
 852 }
 853
 854 static void
 855 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 856 {
 857     switch (tiling) {
 858     case I915_TILING_NONE:
 859         ss->ss3.tiled_surface = 0;
 860         ss->ss3.tile_walk = 0;
 861         break;
 862     case I915_TILING_X:
 863         ss->ss3.tiled_surface = 1;
 864         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 865         break;
 866     case I915_TILING_Y:
 867         ss->ss3.tiled_surface = 1;
 868         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 869         break;
 870     }
 871 }
 872
 873 static void
 874 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 875 {
 876     switch (tiling) {
 877     case I915_TILING_NONE:
 878         ss->ss2.tiled_surface = 0;
 879         ss->ss2.tile_walk = 0;
 880         break;
 881     case I915_TILING_X:
 882         ss->ss2.tiled_surface = 1;
 883         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 884         break;
 885     case I915_TILING_Y:
 886         ss->ss2.tiled_surface = 1;
 887         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 888         break;
 889     }
 890 }
 891
 892 static void
 893 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 894 {
 895     switch (tiling) {
 896     case I915_TILING_NONE:
 897         ss->ss0.tiled_surface = 0;
 898         ss->ss0.tile_walk = 0;
 899         break;
 900     case I915_TILING_X:
 901         ss->ss0.tiled_surface = 1;
 902         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 903         break;
 904     case I915_TILING_Y:
 905         ss->ss0.tiled_surface = 1;
 906         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 907         break;
 908     }
 909 }
 910
 911 static void
 912 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 913 {
 914     switch (tiling) {
 915     case I915_TILING_NONE:
 916         ss->ss2.tiled_surface = 0;
 917         ss->ss2.tile_walk = 0;
 918         break;
 919     case I915_TILING_X:
 920         ss->ss2.tiled_surface = 1;
 921         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 922         break;
 923     case I915_TILING_Y:
 924         ss->ss2.tiled_surface = 1;
 925         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 926         break;
 927     }
 928 }
 929
 930 static void
 931 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 932 {
 933     struct i965_interface_descriptor *desc;
 934     dri_bo *bo;
 935     int pp_index = pp_context->current_pp;
 936
 937     bo = pp_context->idrt.bo;
 938     dri_bo_map(bo, 1);
 939     assert(bo->virtual);
 940     desc = bo->virtual;
 941     memset(desc, 0, sizeof(*desc));
 942     desc->desc0.grf_reg_blocks = 10;
 943     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 944     desc->desc1.const_urb_entry_read_offset = 0;
 945     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 946     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 947     desc->desc2.sampler_count = 0;
 948     desc->desc3.binding_table_entry_count = 0;
 949     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 950
 951     dri_bo_emit_reloc(bo,
 952                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 953                       desc->desc0.grf_reg_blocks,
 954                       offsetof(struct i965_interface_descriptor, desc0),
 955                       pp_context->pp_modules[pp_index].kernel.bo);
 956
 957     dri_bo_emit_reloc(bo,
 958                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 959                       desc->desc2.sampler_count << 2,
 960                       offsetof(struct i965_interface_descriptor, desc2),
 961                       pp_context->sampler_state_table.bo);
 962
 963     dri_bo_unmap(bo);
 964     pp_context->idrt.num_interface_descriptors++;
 965 }
 966
 967 static void
 968 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 969 {
 970     struct i965_vfe_state *vfe_state;
 971     dri_bo *bo;
 972
 973     bo = pp_context->vfe_state.bo;
 974     dri_bo_map(bo, 1);
 975     assert(bo->virtual);
 976     vfe_state = bo->virtual;
 977     memset(vfe_state, 0, sizeof(*vfe_state));
 978     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 979     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 980     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 981     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 982     vfe_state->vfe1.children_present = 0;
 983     vfe_state->vfe2.interface_descriptor_base =
 984         pp_context->idrt.bo->offset >> 4; /* reloc */
 985     dri_bo_emit_reloc(bo,
 986                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 987                       0,
 988                       offsetof(struct i965_vfe_state, vfe2),
 989                       pp_context->idrt.bo);
 990     dri_bo_unmap(bo);
 991 }
 992
 993 static void
 994 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 995 {
 996     unsigned char *constant_buffer;
 997     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 998
 999     assert(sizeof(*pp_static_parameter) == 128);
1000     dri_bo_map(pp_context->curbe.bo, 1);
1001     assert(pp_context->curbe.bo->virtual);
1002     constant_buffer = pp_context->curbe.bo->virtual;
1003     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
1004     dri_bo_unmap(pp_context->curbe.bo);
1005 }
1006
1007 static void
1008 ironlake_pp_states_setup(VADriverContextP ctx,
1009                          struct i965_post_processing_context *pp_context)
1010 {
1011     ironlake_pp_interface_descriptor_table(pp_context);
1012     ironlake_pp_vfe_state(pp_context);
1013     ironlake_pp_upload_constants(pp_context);
1014 }
1015
1016 static void
1017 ironlake_pp_pipeline_select(VADriverContextP ctx,
1018                             struct i965_post_processing_context *pp_context)
1019 {
1020     struct intel_batchbuffer *batch = pp_context->batch;
1021
1022     BEGIN_BATCH(batch, 1);
1023     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
1024     ADVANCE_BATCH(batch);
1025 }
1026
1027 static void
1028 ironlake_pp_urb_layout(VADriverContextP ctx,
1029                        struct i965_post_processing_context *pp_context)
1030 {
1031     struct intel_batchbuffer *batch = pp_context->batch;
1032     unsigned int vfe_fence, cs_fence;
1033
1034     vfe_fence = pp_context->urb.cs_start;
1035     cs_fence = pp_context->urb.size;
1036
1037     BEGIN_BATCH(batch, 3);
1038     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
1039     OUT_BATCH(batch, 0);
1040     OUT_BATCH(batch,
1041               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
1042               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
1043     ADVANCE_BATCH(batch);
1044 }
1045
1046 static void
1047 ironlake_pp_state_base_address(VADriverContextP ctx,
1048                                struct i965_post_processing_context *pp_context)
1049 {
1050     struct intel_batchbuffer *batch = pp_context->batch;
1051
1052     BEGIN_BATCH(batch, 8);
1053     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1054     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1055     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1056     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1057     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1058     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1059     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1060     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1061     ADVANCE_BATCH(batch);
1062 }
1063
1064 static void
1065 ironlake_pp_state_pointers(VADriverContextP ctx,
1066                            struct i965_post_processing_context *pp_context)
1067 {
1068     struct intel_batchbuffer *batch = pp_context->batch;
1069
1070     BEGIN_BATCH(batch, 3);
1071     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
1072     OUT_BATCH(batch, 0);
1073     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1074     ADVANCE_BATCH(batch);
1075 }
1076
1077 static void
1078 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
1079                           struct i965_post_processing_context *pp_context)
1080 {
1081     struct intel_batchbuffer *batch = pp_context->batch;
1082
1083     BEGIN_BATCH(batch, 2);
1084     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1085     OUT_BATCH(batch,
1086               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
1087               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
1088     ADVANCE_BATCH(batch);
1089 }
1090
1091 static void
1092 ironlake_pp_constant_buffer(VADriverContextP ctx,
1093                             struct i965_post_processing_context *pp_context)
1094 {
1095     struct intel_batchbuffer *batch = pp_context->batch;
1096
1097     BEGIN_BATCH(batch, 2);
1098     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1099     OUT_RELOC(batch, pp_context->curbe.bo,
1100               I915_GEM_DOMAIN_INSTRUCTION, 0,
1101               pp_context->urb.size_cs_entry - 1);
1102     ADVANCE_BATCH(batch);
1103 }
1104
1105 static void
1106 ironlake_pp_object_walker(VADriverContextP ctx,
1107                           struct i965_post_processing_context *pp_context)
1108 {
1109     struct intel_batchbuffer *batch = pp_context->batch;
1110     int x, x_steps, y, y_steps;
1111     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1112
1113     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1114     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1115
1116     for (y = 0; y < y_steps; y++) {
1117         for (x = 0; x < x_steps; x++) {
1118             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1119                 BEGIN_BATCH(batch, 20);
1120                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1121                 OUT_BATCH(batch, 0);
1122                 OUT_BATCH(batch, 0); /* no indirect data */
1123                 OUT_BATCH(batch, 0);
1124
1125                 /* inline data grf 5-6 */
1126                 assert(sizeof(*pp_inline_parameter) == 64);
1127                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1128
1129                 ADVANCE_BATCH(batch);
1130             }
1131         }
1132     }
1133 }
1134
1135 static void
1136 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1137                            struct i965_post_processing_context *pp_context)
1138 {
1139     struct intel_batchbuffer *batch = pp_context->batch;
1140
1141     intel_batchbuffer_start_atomic(batch, 0x1000);
1142     intel_batchbuffer_emit_mi_flush(batch);
1143     ironlake_pp_pipeline_select(ctx, pp_context);
1144     ironlake_pp_state_base_address(ctx, pp_context);
1145     ironlake_pp_state_pointers(ctx, pp_context);
1146     ironlake_pp_urb_layout(ctx, pp_context);
1147     ironlake_pp_cs_urb_layout(ctx, pp_context);
1148     ironlake_pp_constant_buffer(ctx, pp_context);
1149     ironlake_pp_object_walker(ctx, pp_context);
1150     intel_batchbuffer_end_atomic(batch);
1151 }
1152
1153 // update u/v offset when the surface format are packed yuv
1154 static void i965_update_src_surface_static_parameter(
1155     VADriverContextP    ctx,
1156     struct i965_post_processing_context *pp_context,
1157     const struct i965_surface *surface)
1158 {
1159     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1160     int fourcc = pp_get_surface_fourcc(ctx, surface);
1161
1162     switch (fourcc) {
1163     case VA_FOURCC('Y', 'U', 'Y', '2'):
1164         pp_static_parameter->grf1.source_packed_u_offset = 1;
1165         pp_static_parameter->grf1.source_packed_v_offset = 3;
1166         break;
1167     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1168         pp_static_parameter->grf1.source_packed_y_offset = 1;
1169         pp_static_parameter->grf1.source_packed_v_offset = 2;
1170         break;
1171     case VA_FOURCC('B', 'G', 'R', 'X'):
1172     case VA_FOURCC('B', 'G', 'R', 'A'):
1173         pp_static_parameter->grf1.source_rgb_layout = 0;
1174         break;
1175     case VA_FOURCC('R', 'G', 'B', 'X'):
1176     case VA_FOURCC('R', 'G', 'B', 'A'):
1177         pp_static_parameter->grf1.source_rgb_layout = 1;
1178         break;
1179     default:
1180         break;
1181     }
1182
1183 }
1184
1185 static void i965_update_dst_surface_static_parameter(
1186     VADriverContextP    ctx,
1187     struct i965_post_processing_context *pp_context,
1188     const struct i965_surface *surface)
1189 {
1190     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1191     int fourcc = pp_get_surface_fourcc(ctx, surface);
1192
1193     switch (fourcc) {
1194     case VA_FOURCC('Y', 'U', 'Y', '2'):
1195         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1196         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1197         break;
1198     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1199         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1200         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1201         break;
1202     case VA_FOURCC('B', 'G', 'R', 'X'):
1203     case VA_FOURCC('B', 'G', 'R', 'A'):
1204         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0;
1205         break;
1206     case VA_FOURCC('R', 'G', 'B', 'X'):
1207     case VA_FOURCC('R', 'G', 'B', 'A'):
1208         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1;
1209         break;
1210     default:
1211         break;
1212     }
1213
1214 }
1215
1216 static void
1217 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1218                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1219                           int width, int height, int pitch, int format,
1220                           int index, int is_target)
1221 {
1222     struct i965_surface_state *ss;
1223     dri_bo *ss_bo;
1224     unsigned int tiling;
1225     unsigned int swizzle;
1226
1227     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1228     ss_bo = pp_context->surface_state_binding_table.bo;
1229     assert(ss_bo);
1230
1231     dri_bo_map(ss_bo, True);
1232     assert(ss_bo->virtual);
1233     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1234     memset(ss, 0, sizeof(*ss));
1235     ss->ss0.surface_type = I965_SURFACE_2D;
1236     ss->ss0.surface_format = format;
1237     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1238     ss->ss2.width = width - 1;
1239     ss->ss2.height = height - 1;
1240     ss->ss3.pitch = pitch - 1;
1241     pp_set_surface_tiling(ss, tiling);
1242     dri_bo_emit_reloc(ss_bo,
1243                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1244                       surf_bo_offset,
1245                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1246                       surf_bo);
1247     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1248     dri_bo_unmap(ss_bo);
1249 }
1250
1251 static void
1252 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1253                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1254                            int width, int height, int wpitch,
1255                            int xoffset, int yoffset,
1256                            int format, int interleave_chroma,
1257                            int index)
1258 {
1259     struct i965_surface_state2 *ss2;
1260     dri_bo *ss2_bo;
1261     unsigned int tiling;
1262     unsigned int swizzle;
1263
1264     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1265     ss2_bo = pp_context->surface_state_binding_table.bo;
1266     assert(ss2_bo);
1267
1268     dri_bo_map(ss2_bo, True);
1269     assert(ss2_bo->virtual);
1270     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1271     memset(ss2, 0, sizeof(*ss2));
1272     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1273     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1274     ss2->ss1.width = width - 1;
1275     ss2->ss1.height = height - 1;
1276     ss2->ss2.pitch = wpitch - 1;
1277     ss2->ss2.interleave_chroma = interleave_chroma;
1278     ss2->ss2.surface_format = format;
1279     ss2->ss3.x_offset_for_cb = xoffset;
1280     ss2->ss3.y_offset_for_cb = yoffset;
1281     pp_set_surface2_tiling(ss2, tiling);
1282     dri_bo_emit_reloc(ss2_bo,
1283                       I915_GEM_DOMAIN_RENDER, 0,
1284                       surf_bo_offset,
1285                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1286                       surf_bo);
1287     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1288     dri_bo_unmap(ss2_bo);
1289 }
1290
1291 static void
1292 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1293                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1294                           int width, int height, int pitch, int format,
1295                           int index, int is_target)
1296 {
1297     struct gen7_surface_state *ss;
1298     dri_bo *ss_bo;
1299     unsigned int tiling;
1300     unsigned int swizzle;
1301
1302     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1303     ss_bo = pp_context->surface_state_binding_table.bo;
1304     assert(ss_bo);
1305
1306     dri_bo_map(ss_bo, True);
1307     assert(ss_bo->virtual);
1308     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1309     memset(ss, 0, sizeof(*ss));
1310     ss->ss0.surface_type = I965_SURFACE_2D;
1311     ss->ss0.surface_format = format;
1312     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1313     ss->ss2.width = width - 1;
1314     ss->ss2.height = height - 1;
1315     ss->ss3.pitch = pitch - 1;
1316     gen7_pp_set_surface_tiling(ss, tiling);
1317     dri_bo_emit_reloc(ss_bo,
1318                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1319                       surf_bo_offset,
1320                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1321                       surf_bo);
1322     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1323     dri_bo_unmap(ss_bo);
1324 }
1325
1326 static void
1327 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1328                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1329                            int width, int height, int wpitch,
1330                            int xoffset, int yoffset,
1331                            int format, int interleave_chroma,
1332                            int index)
1333 {
1334     struct gen7_surface_state2 *ss2;
1335     dri_bo *ss2_bo;
1336     unsigned int tiling;
1337     unsigned int swizzle;
1338
1339     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1340     ss2_bo = pp_context->surface_state_binding_table.bo;
1341     assert(ss2_bo);
1342
1343     dri_bo_map(ss2_bo, True);
1344     assert(ss2_bo->virtual);
1345     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1346     memset(ss2, 0, sizeof(*ss2));
1347     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1348     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1349     ss2->ss1.width = width - 1;
1350     ss2->ss1.height = height - 1;
1351     ss2->ss2.pitch = wpitch - 1;
1352     ss2->ss2.interleave_chroma = interleave_chroma;
1353     ss2->ss2.surface_format = format;
1354     ss2->ss3.x_offset_for_cb = xoffset;
1355     ss2->ss3.y_offset_for_cb = yoffset;
1356     gen7_pp_set_surface2_tiling(ss2, tiling);
1357     dri_bo_emit_reloc(ss2_bo,
1358                       I915_GEM_DOMAIN_RENDER, 0,
1359                       surf_bo_offset,
1360                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1361                       surf_bo);
1362     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1363     dri_bo_unmap(ss2_bo);
1364 }
1365
1366 static void
1367 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1368                                 const struct i965_surface *surface,
1369                                 int base_index, int is_target,
1370                                 int *width, int *height, int *pitch, int *offset)
1371 {
1372     struct i965_driver_data *i965 = i965_driver_data(ctx);
1373     struct object_surface *obj_surface;
1374     struct object_image *obj_image;
1375     dri_bo *bo;
1376     int fourcc = pp_get_surface_fourcc(ctx, surface);
1377     const int Y = 0;
1378     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1379     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1380     const int UV = 1;
1381     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1382     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1383     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1384                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1385                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1386                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1387     int scale_factor_of_1st_plane_width_in_byte = 1;
1388
1389     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1390         obj_surface = SURFACE(surface->id);
1391         bo = obj_surface->bo;
1392         width[0] = obj_surface->orig_width;
1393         height[0] = obj_surface->orig_height;
1394         pitch[0] = obj_surface->width;
1395         offset[0] = 0;
1396
1397         if (full_packed_format) {
1398             scale_factor_of_1st_plane_width_in_byte = 4;
1399             pitch[0] = obj_surface->width * 4;
1400         }
1401         else if (packed_yuv ) {
1402             scale_factor_of_1st_plane_width_in_byte =  2;
1403             pitch[0] = obj_surface->width * 2;
1404         }
1405         else if (interleaved_uv) {
1406             width[1] = obj_surface->orig_width;
1407             height[1] = obj_surface->orig_height / 2;
1408             pitch[1] = obj_surface->width;
1409             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1410         } else {
1411             width[1] = obj_surface->orig_width / 2;
1412             height[1] = obj_surface->orig_height / 2;
1413             pitch[1] = obj_surface->width / 2;
1414             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1415             width[2] = obj_surface->orig_width / 2;
1416             height[2] = obj_surface->orig_height / 2;
1417             pitch[2] = obj_surface->width / 2;
1418             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1419         }
1420     } else {
1421         obj_image = IMAGE(surface->id);
1422         bo = obj_image->bo;
1423         width[0] = obj_image->image.width;
1424         height[0] = obj_image->image.height;
1425         pitch[0] = obj_image->image.pitches[0];
1426         offset[0] = obj_image->image.offsets[0];
1427
1428         if (full_packed_format) {
1429             scale_factor_of_1st_plane_width_in_byte = 4;
1430         }
1431         else if (packed_yuv ) {
1432             scale_factor_of_1st_plane_width_in_byte = 2;
1433         }
1434         else if (interleaved_uv) {
1435             width[1] = obj_image->image.width;
1436             height[1] = obj_image->image.height / 2;
1437             pitch[1] = obj_image->image.pitches[1];
1438             offset[1] = obj_image->image.offsets[1];
1439         } else {
1440             width[1] = obj_image->image.width / 2;
1441             height[1] = obj_image->image.height / 2;
1442             pitch[1] = obj_image->image.pitches[1];
1443             offset[1] = obj_image->image.offsets[1];
1444             width[2] = obj_image->image.width / 2;
1445             height[2] = obj_image->image.height / 2;
1446             pitch[2] = obj_image->image.pitches[2];
1447             offset[2] = obj_image->image.offsets[2];
1448         }
1449     }
1450
1451     /* Y surface */
1452     i965_pp_set_surface_state(ctx, pp_context,
1453                               bo, offset[Y],
1454                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1455                               base_index, is_target);
1456
1457     if (!packed_yuv && !full_packed_format) {
1458         if (interleaved_uv) {
1459             i965_pp_set_surface_state(ctx, pp_context,
1460                                       bo, offset[UV],
1461                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1462                                       base_index + 1, is_target);
1463         } else {
1464             /* U surface */
1465             i965_pp_set_surface_state(ctx, pp_context,
1466                                       bo, offset[U],
1467                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1468                                       base_index + 1, is_target);
1469
1470             /* V surface */
1471             i965_pp_set_surface_state(ctx, pp_context,
1472                                       bo, offset[V],
1473                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1474                                       base_index + 2, is_target);
1475         }
1476     }
1477
1478 }
1479
1480 static void
1481 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1482                                      const struct i965_surface *surface,
1483                                      int base_index, int is_target,
1484                                      int *width, int *height, int *pitch, int *offset)
1485 {
1486     struct i965_driver_data *i965 = i965_driver_data(ctx);
1487     struct object_surface *obj_surface;
1488     struct object_image *obj_image;
1489     dri_bo *bo;
1490     int fourcc = pp_get_surface_fourcc(ctx, surface);
1491     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1492                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1493     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1494                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1495     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1496     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1497
1498     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1499         obj_surface = SURFACE(surface->id);
1500         bo = obj_surface->bo;
1501         width[0] = obj_surface->orig_width;
1502         height[0] = obj_surface->orig_height;
1503         pitch[0] = obj_surface->width;
1504         offset[0] = 0;
1505
1506         if (packed_yuv) {
1507             if (is_target)
1508                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1509             else
1510                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1511
1512             pitch[0] = obj_surface->width * 2;
1513         }
1514
1515         width[1] = obj_surface->cb_cr_width;
1516         height[1] = obj_surface->cb_cr_height;
1517         pitch[1] = obj_surface->cb_cr_pitch;
1518         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1519
1520         width[2] = obj_surface->cb_cr_width;
1521         height[2] = obj_surface->cb_cr_height;
1522         pitch[2] = obj_surface->cb_cr_pitch;
1523         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1524     } else {
1525         obj_image = IMAGE(surface->id);
1526         bo = obj_image->bo;
1527         width[0] = obj_image->image.width;
1528         height[0] = obj_image->image.height;
1529         pitch[0] = obj_image->image.pitches[0];
1530         offset[0] = obj_image->image.offsets[0];
1531
1532         if (packed_yuv) {
1533             if (is_target)
1534                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1535             else
1536                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1537         } else if (interleaved_uv) {
1538             width[1] = obj_image->image.width / 2;
1539             height[1] = obj_image->image.height / 2;
1540             pitch[1] = obj_image->image.pitches[1];
1541             offset[1] = obj_image->image.offsets[1];
1542         } else {
1543             width[1] = obj_image->image.width / 2;
1544             height[1] = obj_image->image.height / 2;
1545             pitch[1] = obj_image->image.pitches[U];
1546             offset[1] = obj_image->image.offsets[U];
1547             width[2] = obj_image->image.width / 2;
1548             height[2] = obj_image->image.height / 2;
1549             pitch[2] = obj_image->image.pitches[V];
1550             offset[2] = obj_image->image.offsets[V];
1551         }
1552     }
1553
1554     if (is_target) {
1555         gen7_pp_set_surface_state(ctx, pp_context,
1556                                   bo, 0,
1557                                   width[0] / 4, height[0], pitch[0],
1558                                   I965_SURFACEFORMAT_R8_SINT,
1559                                   base_index, 1);
1560
1561         if (!packed_yuv) {
1562             if (interleaved_uv) {
1563                 gen7_pp_set_surface_state(ctx, pp_context,
1564                                           bo, offset[1],
1565                                           width[1] / 2, height[1], pitch[1],
1566                                           I965_SURFACEFORMAT_R8G8_SINT,
1567                                           base_index + 1, 1);
1568             } else {
1569                 gen7_pp_set_surface_state(ctx, pp_context,
1570                                           bo, offset[1],
1571                                           width[1] / 4, height[1], pitch[1],
1572                                           I965_SURFACEFORMAT_R8_SINT,
1573                                           base_index + 1, 1);
1574                 gen7_pp_set_surface_state(ctx, pp_context,
1575                                           bo, offset[2],
1576                                           width[2] / 4, height[2], pitch[2],
1577                                           I965_SURFACEFORMAT_R8_SINT,
1578                                           base_index + 2, 1);
1579             }
1580         }
1581     } else {
1582         int format0 = SURFACE_FORMAT_Y8_UNORM;
1583
1584         switch (fourcc) {
1585         case VA_FOURCC('Y', 'U', 'Y', '2'):
1586             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1587             break;
1588
1589         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1590             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1591             break;
1592
1593         default:
1594             break;
1595         }
1596
1597         gen7_pp_set_surface2_state(ctx, pp_context,
1598                                    bo, offset[0],
1599                                    width[0], height[0], pitch[0],
1600                                    0, 0,
1601                                    format0, 0,
1602                                    base_index);
1603
1604         if (!packed_yuv) {
1605             if (interleaved_uv) {
1606                 gen7_pp_set_surface2_state(ctx, pp_context,
1607                                            bo, offset[1],
1608                                            width[1], height[1], pitch[1],
1609                                            0, 0,
1610                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1611                                            base_index + 1);
1612             } else {
1613                 gen7_pp_set_surface2_state(ctx, pp_context,
1614                                            bo, offset[1],
1615                                            width[1], height[1], pitch[1],
1616                                            0, 0,
1617                                            SURFACE_FORMAT_R8_UNORM, 0,
1618                                            base_index + 1);
1619                 gen7_pp_set_surface2_state(ctx, pp_context,
1620                                            bo, offset[2],
1621                                            width[2], height[2], pitch[2],
1622                                            0, 0,
1623                                            SURFACE_FORMAT_R8_UNORM, 0,
1624                                            base_index + 2);
1625             }
1626         }
1627     }
1628 }
1629
1630 static int
1631 pp_null_x_steps(void *private_context)
1632 {
1633     return 1;
1634 }
1635
1636 static int
1637 pp_null_y_steps(void *private_context)
1638 {
1639     return 1;
1640 }
1641
1642 static int
1643 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1644 {
1645     return 0;
1646 }
1647
1648 static VAStatus
1649 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1650                    const struct i965_surface *src_surface,
1651                    const VARectangle *src_rect,
1652                    struct i965_surface *dst_surface,
1653                    const VARectangle *dst_rect,
1654                    void *filter_param)
1655 {
1656     /* private function & data */
1657     pp_context->pp_x_steps = pp_null_x_steps;
1658     pp_context->pp_y_steps = pp_null_y_steps;
1659     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1660
1661     dst_surface->flags = src_surface->flags;
1662
1663     return VA_STATUS_SUCCESS;
1664 }
1665
1666 static int
1667 pp_load_save_x_steps(void *private_context)
1668 {
1669     return 1;
1670 }
1671
1672 static int
1673 pp_load_save_y_steps(void *private_context)
1674 {
1675     struct pp_load_save_context *pp_load_save_context = private_context;
1676
1677     return pp_load_save_context->dest_h / 8;
1678 }
1679
1680 static int
1681 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1682 {
1683     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1684
1685     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1686     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1687     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1688     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1689
1690     return 0;
1691 }
1692
1693 static VAStatus
1694 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1695                                 const struct i965_surface *src_surface,
1696                                 const VARectangle *src_rect,
1697                                 struct i965_surface *dst_surface,
1698                                 const VARectangle *dst_rect,
1699                                 void *filter_param)
1700 {
1701     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1702     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1703     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1704     int width[3], height[3], pitch[3], offset[3];
1705     const int Y = 0;
1706
1707     /* source surface */
1708     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1709                                     width, height, pitch, offset);
1710
1711     /* destination surface */
1712     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1713                                     width, height, pitch, offset);
1714
1715     /* private function & data */
1716     pp_context->pp_x_steps = pp_load_save_x_steps;
1717     pp_context->pp_y_steps = pp_load_save_y_steps;
1718     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1719     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1720     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1721
1722     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1723     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1724
1725     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1726     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1727
1728     // update u/v offset for packed yuv
1729     i965_update_src_surface_static_parameter (ctx, pp_context, src_surface);
1730     i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface);
1731
1732     dst_surface->flags = src_surface->flags;
1733
1734     return VA_STATUS_SUCCESS;
1735 }
1736
1737 static int
1738 pp_scaling_x_steps(void *private_context)
1739 {
1740     return 1;
1741 }
1742
1743 static int
1744 pp_scaling_y_steps(void *private_context)
1745 {
1746     struct pp_scaling_context *pp_scaling_context = private_context;
1747
1748     return pp_scaling_context->dest_h / 8;
1749 }
1750
1751 static int
1752 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1753 {
1754     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1755     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1756     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1757     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1758     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1759
1760     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1761     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1762     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1763     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1764
1765     return 0;
1766 }
1767
1768 static VAStatus
1769 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1770                            const struct i965_surface *src_surface,
1771                            const VARectangle *src_rect,
1772                            struct i965_surface *dst_surface,
1773                            const VARectangle *dst_rect,
1774                            void *filter_param)
1775 {
1776     struct i965_driver_data *i965 = i965_driver_data(ctx);
1777     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1778     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1779     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1780     struct object_surface *obj_surface;
1781     struct i965_sampler_state *sampler_state;
1782     int in_w, in_h, in_wpitch, in_hpitch;
1783     int out_w, out_h, out_wpitch, out_hpitch;
1784
1785     /* source surface */
1786     obj_surface = SURFACE(src_surface->id);
1787     in_w = obj_surface->orig_width;
1788     in_h = obj_surface->orig_height;
1789     in_wpitch = obj_surface->width;
1790     in_hpitch = obj_surface->height;
1791
1792     /* source Y surface index 1 */
1793     i965_pp_set_surface_state(ctx, pp_context,
1794                               obj_surface->bo, 0,
1795                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1796                               1, 0);
1797
1798     /* source UV surface index 2 */
1799     i965_pp_set_surface_state(ctx, pp_context,
1800                               obj_surface->bo, in_wpitch * in_hpitch,
1801                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1802                               2, 0);
1803
1804     /* destination surface */
1805     obj_surface = SURFACE(dst_surface->id);
1806     out_w = obj_surface->orig_width;
1807     out_h = obj_surface->orig_height;
1808     out_wpitch = obj_surface->width;
1809     out_hpitch = obj_surface->height;
1810
1811     /* destination Y surface index 7 */
1812     i965_pp_set_surface_state(ctx, pp_context,
1813                               obj_surface->bo, 0,
1814                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1815                               7, 1);
1816
1817     /* destination UV surface index 8 */
1818     i965_pp_set_surface_state(ctx, pp_context,
1819                               obj_surface->bo, out_wpitch * out_hpitch,
1820                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1821                               8, 1);
1822
1823     /* sampler state */
1824     dri_bo_map(pp_context->sampler_state_table.bo, True);
1825     assert(pp_context->sampler_state_table.bo->virtual);
1826     sampler_state = pp_context->sampler_state_table.bo->virtual;
1827
1828     /* SIMD16 Y index 1 */
1829     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1830     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1831     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1832     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1833     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1834
1835     /* SIMD16 UV index 2 */
1836     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1837     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1838     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1839     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1840     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1841
1842     dri_bo_unmap(pp_context->sampler_state_table.bo);
1843
1844     /* private function & data */
1845     pp_context->pp_x_steps = pp_scaling_x_steps;
1846     pp_context->pp_y_steps = pp_scaling_y_steps;
1847     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1848
1849     pp_scaling_context->dest_x = dst_rect->x;
1850     pp_scaling_context->dest_y = dst_rect->y;
1851     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1852     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1853     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1854     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1855
1856     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1857
1858     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1859     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1860     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1861     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1862     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1863
1864     dst_surface->flags = src_surface->flags;
1865
1866     return VA_STATUS_SUCCESS;
1867 }
1868
1869 static int
1870 pp_avs_x_steps(void *private_context)
1871 {
1872     struct pp_avs_context *pp_avs_context = private_context;
1873
1874     return pp_avs_context->dest_w / 16;
1875 }
1876
1877 static int
1878 pp_avs_y_steps(void *private_context)
1879 {
1880     return 1;
1881 }
1882
1883 static int
1884 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1885 {
1886     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1887     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1888     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1889     float src_x_steping, src_y_steping, video_step_delta;
1890     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1891
1892     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1893         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1894         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1895     } else if (tmp_w >= pp_avs_context->dest_w) {
1896         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1897         pp_inline_parameter->grf6.video_step_delta = 0;
1898
1899         if (x == 0) {
1900             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1901                 pp_avs_context->src_normalized_x;
1902         } else {
1903             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1904             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1905             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1906                 16 * 15 * video_step_delta / 2;
1907         }
1908     } else {
1909         int n0, n1, n2, nls_left, nls_right;
1910         int factor_a = 5, factor_b = 4;
1911         float f;
1912
1913         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1914         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1915         n2 = tmp_w / (16 * factor_a);
1916         nls_left = n0 + n2;
1917         nls_right = n1 + n2;
1918         f = (float) n2 * 16 / tmp_w;
1919
1920         if (n0 < 5) {
1921             pp_inline_parameter->grf6.video_step_delta = 0.0;
1922
1923             if (x == 0) {
1924                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1925                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1926             } else {
1927                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1928                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1929                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1930                     16 * 15 * video_step_delta / 2;
1931             }
1932         } else {
1933             if (x < nls_left) {
1934                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1935                 float a = f / (nls_left * 16 * factor_b);
1936                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1937
1938                 pp_inline_parameter->grf6.video_step_delta = b;
1939
1940                 if (x == 0) {
1941                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1942                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1943                 } else {
1944                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1945                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1946                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1947                         16 * 15 * video_step_delta / 2;
1948                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1949                 }
1950             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1951                 /* scale the center linearly */
1952                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1953                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1954                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1955                     16 * 15 * video_step_delta / 2;
1956                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1957                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1958             } else {
1959                 float a = f / (nls_right * 16 * factor_b);
1960                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1961
1962                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1963                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1964                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1965                     16 * 15 * video_step_delta / 2;
1966                 pp_inline_parameter->grf6.video_step_delta = -b;
1967
1968                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1969                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1970                 else
1971                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1972             }
1973         }
1974     }
1975
1976     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1977     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1978     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1979     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1980
1981     return 0;
1982 }
1983
1984 static VAStatus
1985 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1986                        const struct i965_surface *src_surface,
1987                        const VARectangle *src_rect,
1988                        struct i965_surface *dst_surface,
1989                        const VARectangle *dst_rect,
1990                        void *filter_param,
1991                        int nlas)
1992 {
1993     struct i965_driver_data *i965 = i965_driver_data(ctx);
1994     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1995     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1996     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1997     struct object_surface *obj_surface;
1998     struct i965_sampler_8x8 *sampler_8x8;
1999     struct i965_sampler_8x8_state *sampler_8x8_state;
2000     int index;
2001     int in_w, in_h, in_wpitch, in_hpitch;
2002     int out_w, out_h, out_wpitch, out_hpitch;
2003     int i;
2004
2005     /* surface */
2006     obj_surface = SURFACE(src_surface->id);
2007     in_w = obj_surface->orig_width;
2008     in_h = obj_surface->orig_height;
2009     in_wpitch = obj_surface->width;
2010     in_hpitch = obj_surface->height;
2011
2012     /* source Y surface index 1 */
2013     i965_pp_set_surface2_state(ctx, pp_context,
2014                                obj_surface->bo, 0,
2015                                in_w, in_h, in_wpitch,
2016                                0, 0,
2017                                SURFACE_FORMAT_Y8_UNORM, 0,
2018                                1);
2019
2020     /* source UV surface index 2 */
2021     i965_pp_set_surface2_state(ctx, pp_context,
2022                                obj_surface->bo, in_wpitch * in_hpitch,
2023                                in_w / 2, in_h / 2, in_wpitch,
2024                                0, 0,
2025                                SURFACE_FORMAT_R8B8_UNORM, 0,
2026                                2);
2027
2028     /* destination surface */
2029     obj_surface = SURFACE(dst_surface->id);
2030     out_w = obj_surface->orig_width;
2031     out_h = obj_surface->orig_height;
2032     out_wpitch = obj_surface->width;
2033     out_hpitch = obj_surface->height;
2034     assert(out_w <= out_wpitch && out_h <= out_hpitch);
2035
2036     /* destination Y surface index 7 */
2037     i965_pp_set_surface_state(ctx, pp_context,
2038                               obj_surface->bo, 0,
2039                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2040                               7, 1);
2041
2042     /* destination UV surface index 8 */
2043     i965_pp_set_surface_state(ctx, pp_context,
2044                               obj_surface->bo, out_wpitch * out_hpitch,
2045                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2046                               8, 1);
2047
2048     /* sampler 8x8 state */
2049     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2050     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2051     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2052     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2053     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2054
2055     for (i = 0; i < 17; i++) {
2056         /* for Y channel, currently ignore */
2057         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
2058         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
2059         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
2060         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
2061         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
2062         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
2063         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
2064         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
2065         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
2066         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
2067         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
2068         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
2069         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
2070         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
2071         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
2072         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
2073         /* for U/V channel, 0.25 */
2074         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2075         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2076         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2077         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2078         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2079         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2080         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2081         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2082         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2083         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2084         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2085         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2086         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2087         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2088         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2089         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2090     }
2091
2092     sampler_8x8_state->dw136.default_sharpness_level = 0;
2093     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2094     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2095     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2096     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2097
2098     /* sampler 8x8 */
2099     dri_bo_map(pp_context->sampler_state_table.bo, True);
2100     assert(pp_context->sampler_state_table.bo->virtual);
2101     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
2102     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2103
2104     /* sample_8x8 Y index 1 */
2105     index = 1;
2106     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2107     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2108     sampler_8x8[index].dw0.ief_bypass = 1;
2109     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2110     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2111     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2112     sampler_8x8[index].dw2.global_noise_estimation = 22;
2113     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2114     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2115     sampler_8x8[index].dw3.strong_edge_weight = 7;
2116     sampler_8x8[index].dw3.regular_weight = 2;
2117     sampler_8x8[index].dw3.non_edge_weight = 0;
2118     sampler_8x8[index].dw3.gain_factor = 40;
2119     sampler_8x8[index].dw4.steepness_boost = 0;
2120     sampler_8x8[index].dw4.steepness_threshold = 0;
2121     sampler_8x8[index].dw4.mr_boost = 0;
2122     sampler_8x8[index].dw4.mr_threshold = 5;
2123     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2124     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2125     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2126     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2127     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2128     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2129     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2130     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2131     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2132     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2133     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2134     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2135     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2136     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2137     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2138     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2139     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2140     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2141     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2142     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2143     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2144     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2145     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2146     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2147     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2148     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2149     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2150     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2151     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2152     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2153     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2154     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2155     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2156     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2157     sampler_8x8[index].dw13.limiter_boost = 0;
2158     sampler_8x8[index].dw13.minimum_limiter = 10;
2159     sampler_8x8[index].dw13.maximum_limiter = 11;
2160     sampler_8x8[index].dw14.clip_limiter = 130;
2161     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2162                       I915_GEM_DOMAIN_RENDER,
2163                       0,
2164                       0,
2165                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2166                       pp_context->sampler_state_table.bo_8x8);
2167
2168     /* sample_8x8 UV index 2 */
2169     index = 2;
2170     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2171     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2172     sampler_8x8[index].dw0.ief_bypass = 1;
2173     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2174     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2175     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2176     sampler_8x8[index].dw2.global_noise_estimation = 22;
2177     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2178     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2179     sampler_8x8[index].dw3.strong_edge_weight = 7;
2180     sampler_8x8[index].dw3.regular_weight = 2;
2181     sampler_8x8[index].dw3.non_edge_weight = 0;
2182     sampler_8x8[index].dw3.gain_factor = 40;
2183     sampler_8x8[index].dw4.steepness_boost = 0;
2184     sampler_8x8[index].dw4.steepness_threshold = 0;
2185     sampler_8x8[index].dw4.mr_boost = 0;
2186     sampler_8x8[index].dw4.mr_threshold = 5;
2187     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2188     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2189     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2190     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2191     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2192     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2193     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2194     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2195     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2196     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2197     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2198     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2199     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2200     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2201     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2202     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2203     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2204     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2205     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2206     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2207     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2208     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2209     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2210     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2211     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2212     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2213     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2214     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2215     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2216     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2217     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2218     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2219     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2220     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2221     sampler_8x8[index].dw13.limiter_boost = 0;
2222     sampler_8x8[index].dw13.minimum_limiter = 10;
2223     sampler_8x8[index].dw13.maximum_limiter = 11;
2224     sampler_8x8[index].dw14.clip_limiter = 130;
2225     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2226                       I915_GEM_DOMAIN_RENDER,
2227                       0,
2228                       0,
2229                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2230                       pp_context->sampler_state_table.bo_8x8);
2231
2232     dri_bo_unmap(pp_context->sampler_state_table.bo);
2233
2234     /* private function & data */
2235     pp_context->pp_x_steps = pp_avs_x_steps;
2236     pp_context->pp_y_steps = pp_avs_y_steps;
2237     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2238
2239     pp_avs_context->dest_x = dst_rect->x;
2240     pp_avs_context->dest_y = dst_rect->y;
2241     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2242     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2243     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2244     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2245     pp_avs_context->src_w = src_rect->width;
2246     pp_avs_context->src_h = src_rect->height;
2247
2248     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2249     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2250
2251     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2252     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2253     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2254     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2255     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2256     pp_inline_parameter->grf6.video_step_delta = 0.0;
2257
2258     dst_surface->flags = src_surface->flags;
2259
2260     return VA_STATUS_SUCCESS;
2261 }
2262
2263 static VAStatus
2264 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2265                             const struct i965_surface *src_surface,
2266                             const VARectangle *src_rect,
2267                             struct i965_surface *dst_surface,
2268                             const VARectangle *dst_rect,
2269                             void *filter_param)
2270 {
2271     return pp_nv12_avs_initialize(ctx, pp_context,
2272                                   src_surface,
2273                                   src_rect,
2274                                   dst_surface,
2275                                   dst_rect,
2276                                   filter_param,
2277                                   1);
2278 }
2279
2280 static VAStatus
2281 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2282                              const struct i965_surface *src_surface,
2283                              const VARectangle *src_rect,
2284                              struct i965_surface *dst_surface,
2285                              const VARectangle *dst_rect,
2286                              void *filter_param)
2287 {
2288     return pp_nv12_avs_initialize(ctx, pp_context,
2289                                   src_surface,
2290                                   src_rect,
2291                                   dst_surface,
2292                                   dst_rect,
2293                                   filter_param,
2294                                   0);
2295 }
2296
2297 static int
2298 gen7_pp_avs_x_steps(void *private_context)
2299 {
2300     struct pp_avs_context *pp_avs_context = private_context;
2301
2302     return pp_avs_context->dest_w / 16;
2303 }
2304
2305 static int
2306 gen7_pp_avs_y_steps(void *private_context)
2307 {
2308     struct pp_avs_context *pp_avs_context = private_context;
2309
2310     return pp_avs_context->dest_h / 16;
2311 }
2312
2313 static int
2314 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2315 {
2316     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2317     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2318
2319     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2320     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2321     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2322     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2323
2324     return 0;
2325 }
2326
2327 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2328                                               struct i965_post_processing_context *pp_context,
2329                                               const struct i965_surface *surface)
2330 {
2331     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2332     int fourcc = pp_get_surface_fourcc(ctx, surface);
2333
2334     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2335         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2336         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2337         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2338     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2339         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2340         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2341         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2342     }
2343 }
2344
2345 static VAStatus
2346 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2347                            const struct i965_surface *src_surface,
2348                            const VARectangle *src_rect,
2349                            struct i965_surface *dst_surface,
2350                            const VARectangle *dst_rect,
2351                            void *filter_param)
2352 {
2353     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2354     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2355     struct gen7_sampler_8x8 *sampler_8x8;
2356     struct i965_sampler_8x8_state *sampler_8x8_state;
2357     int index, i;
2358     int width[3], height[3], pitch[3], offset[3];
2359     int src_width, src_height;
2360
2361     /* source surface */
2362     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2363                                          width, height, pitch, offset);
2364     src_width = width[0];
2365     src_height = height[0];
2366
2367     /* destination surface */
2368     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2369                                          width, height, pitch, offset);
2370
2371     /* sampler 8x8 state */
2372     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2373     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2374     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2375     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2376     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2377
2378     for (i = 0; i < 17; i++) {
2379         /* for Y channel, currently ignore */
2380         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2381         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2382         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2383         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2384         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2385         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2386         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2387         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2388         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2389         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2390         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2391         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2392         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2393         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2394         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2395         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2396         /* for U/V channel, 0.25 */
2397         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2398         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2399         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2400         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2401         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2402         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2403         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2404         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2405         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2406         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2407         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2408         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2409         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2410         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2411         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2412         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2413     }
2414
2415     sampler_8x8_state->dw136.default_sharpness_level = 0;
2416     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2417     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2418     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2419     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2420
2421     /* sampler 8x8 */
2422     dri_bo_map(pp_context->sampler_state_table.bo, True);
2423     assert(pp_context->sampler_state_table.bo->virtual);
2424     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2425     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2426
2427     /* sample_8x8 Y index 4 */
2428     index = 4;
2429     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2430     sampler_8x8[index].dw0.global_noise_estimation = 255;
2431     sampler_8x8[index].dw0.ief_bypass = 1;
2432
2433     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2434
2435     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2436     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2437     sampler_8x8[index].dw2.r5x_coefficient = 9;
2438     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2439     sampler_8x8[index].dw2.r5c_coefficient = 3;
2440
2441     sampler_8x8[index].dw3.r3x_coefficient = 27;
2442     sampler_8x8[index].dw3.r3c_coefficient = 5;
2443     sampler_8x8[index].dw3.gain_factor = 40;
2444     sampler_8x8[index].dw3.non_edge_weight = 1;
2445     sampler_8x8[index].dw3.regular_weight = 2;
2446     sampler_8x8[index].dw3.strong_edge_weight = 7;
2447     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2448
2449     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2450                       I915_GEM_DOMAIN_RENDER,
2451                       0,
2452                       0,
2453                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2454                       pp_context->sampler_state_table.bo_8x8);
2455
2456     /* sample_8x8 UV index 8 */
2457     index = 8;
2458     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2459     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2460     sampler_8x8[index].dw0.global_noise_estimation = 255;
2461     sampler_8x8[index].dw0.ief_bypass = 1;
2462     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2463     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2464     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2465     sampler_8x8[index].dw2.r5x_coefficient = 9;
2466     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2467     sampler_8x8[index].dw2.r5c_coefficient = 3;
2468     sampler_8x8[index].dw3.r3x_coefficient = 27;
2469     sampler_8x8[index].dw3.r3c_coefficient = 5;
2470     sampler_8x8[index].dw3.gain_factor = 40;
2471     sampler_8x8[index].dw3.non_edge_weight = 1;
2472     sampler_8x8[index].dw3.regular_weight = 2;
2473     sampler_8x8[index].dw3.strong_edge_weight = 7;
2474     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2475
2476     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2477                       I915_GEM_DOMAIN_RENDER,
2478                       0,
2479                       0,
2480                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2481                       pp_context->sampler_state_table.bo_8x8);
2482
2483     /* sampler_8x8 V, index 12 */
2484     index = 12;
2485     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2486     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2487     sampler_8x8[index].dw0.global_noise_estimation = 255;
2488     sampler_8x8[index].dw0.ief_bypass = 1;
2489     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2490     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2491     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2492     sampler_8x8[index].dw2.r5x_coefficient = 9;
2493     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2494     sampler_8x8[index].dw2.r5c_coefficient = 3;
2495     sampler_8x8[index].dw3.r3x_coefficient = 27;
2496     sampler_8x8[index].dw3.r3c_coefficient = 5;
2497     sampler_8x8[index].dw3.gain_factor = 40;
2498     sampler_8x8[index].dw3.non_edge_weight = 1;
2499     sampler_8x8[index].dw3.regular_weight = 2;
2500     sampler_8x8[index].dw3.strong_edge_weight = 7;
2501     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2502
2503     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2504                       I915_GEM_DOMAIN_RENDER,
2505                       0,
2506                       0,
2507                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2508                       pp_context->sampler_state_table.bo_8x8);
2509
2510     dri_bo_unmap(pp_context->sampler_state_table.bo);
2511
2512     /* private function & data */
2513     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2514     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2515     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2516
2517     pp_avs_context->dest_x = dst_rect->x;
2518     pp_avs_context->dest_y = dst_rect->y;
2519     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2520     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2521     pp_avs_context->src_w = src_rect->width;
2522     pp_avs_context->src_h = src_rect->height;
2523
2524     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2525     dw = MAX(dw, pp_avs_context->dest_w);
2526
2527     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2528     pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */
2529     pp_static_parameter->grf2.avs_wa_width = dw;
2530     pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw);
2531     pp_static_parameter->grf2.avs_wa_five_div_256_width = (float) 5.0 / (256 * dw);
2532
2533     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2534     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) src_rect->height / src_height / pp_avs_context->dest_h;
2535     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2536     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2537
2538     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2539
2540     dst_surface->flags = src_surface->flags;
2541
2542     return VA_STATUS_SUCCESS;
2543 }
2544
2545 static int
2546 pp_dndi_x_steps(void *private_context)
2547 {
2548     return 1;
2549 }
2550
2551 static int
2552 pp_dndi_y_steps(void *private_context)
2553 {
2554     struct pp_dndi_context *pp_dndi_context = private_context;
2555
2556     return pp_dndi_context->dest_h / 4;
2557 }
2558
2559 static int
2560 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2561 {
2562     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2563
2564     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2565     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2566
2567     return 0;
2568 }
2569
2570 static VAStatus
2571 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2572                         const struct i965_surface *src_surface,
2573                         const VARectangle *src_rect,
2574                         struct i965_surface *dst_surface,
2575                         const VARectangle *dst_rect,
2576                         void *filter_param)
2577 {
2578     struct i965_driver_data *i965 = i965_driver_data(ctx);
2579     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2580     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2581     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2582     struct object_surface *obj_surface;
2583     struct i965_sampler_dndi *sampler_dndi;
2584     int index;
2585     int w, h;
2586     int orig_w, orig_h;
2587     int dndi_top_first = 1;
2588
2589     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2590         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2591
2592     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2593         dndi_top_first = 1;
2594     else
2595         dndi_top_first = 0;
2596
2597     /* surface */
2598     obj_surface = SURFACE(src_surface->id);
2599     orig_w = obj_surface->orig_width;
2600     orig_h = obj_surface->orig_height;
2601     w = obj_surface->width;
2602     h = obj_surface->height;
2603
2604     if (pp_context->stmm.bo == NULL) {
2605         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2606                                            "STMM surface",
2607                                            w * h,
2608                                            4096);
2609         assert(pp_context->stmm.bo);
2610     }
2611
2612     /* source UV surface index 2 */
2613     i965_pp_set_surface_state(ctx, pp_context,
2614                               obj_surface->bo, w * h,
2615                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2616                               2, 0);
2617
2618     /* source YUV surface index 4 */
2619     i965_pp_set_surface2_state(ctx, pp_context,
2620                                obj_surface->bo, 0,
2621                                orig_w, orig_h, w,
2622                                0, h,
2623                                SURFACE_FORMAT_PLANAR_420_8, 1,
2624                                4);
2625
2626     /* source STMM surface index 20 */
2627     i965_pp_set_surface_state(ctx, pp_context,
2628                               pp_context->stmm.bo, 0,
2629                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2630                               20, 1);
2631
2632     /* destination surface */
2633     obj_surface = SURFACE(dst_surface->id);
2634     orig_w = obj_surface->orig_width;
2635     orig_h = obj_surface->orig_height;
2636     w = obj_surface->width;
2637     h = obj_surface->height;
2638
2639     /* destination Y surface index 7 */
2640     i965_pp_set_surface_state(ctx, pp_context,
2641                               obj_surface->bo, 0,
2642                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2643                               7, 1);
2644
2645     /* destination UV surface index 8 */
2646     i965_pp_set_surface_state(ctx, pp_context,
2647                               obj_surface->bo, w * h,
2648                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2649                               8, 1);
2650     /* sampler dndi */
2651     dri_bo_map(pp_context->sampler_state_table.bo, True);
2652     assert(pp_context->sampler_state_table.bo->virtual);
2653     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2654     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2655
2656     /* sample dndi index 1 */
2657     index = 0;
2658     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2659     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2660     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2661     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2662
2663     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2664     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2665     sampler_dndi[index].dw1.stmm_c2 = 1;
2666     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2667     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2668
2669     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2670     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2671     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2672     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2673
2674     sampler_dndi[index].dw3.maximum_stmm = 128;
2675     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2676     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2677     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2678     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2679
2680     sampler_dndi[index].dw4.sdi_delta = 8;
2681     sampler_dndi[index].dw4.sdi_threshold = 128;
2682     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2683     sampler_dndi[index].dw4.stmm_shift_up = 0;
2684     sampler_dndi[index].dw4.stmm_shift_down = 0;
2685     sampler_dndi[index].dw4.minimum_stmm = 0;
2686
2687     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2688     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2689     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2690     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2691
2692     sampler_dndi[index].dw6.dn_enable = 1;
2693     sampler_dndi[index].dw6.di_enable = 1;
2694     sampler_dndi[index].dw6.di_partial = 0;
2695     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2696     sampler_dndi[index].dw6.dndi_stream_id = 0;
2697     sampler_dndi[index].dw6.dndi_first_frame = 1;
2698     sampler_dndi[index].dw6.progressive_dn = 0;
2699     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2700     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2701     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2702
2703     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2704     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2705     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2706     sampler_dndi[index].dw7.column_width_minus1 = 0;
2707
2708     dri_bo_unmap(pp_context->sampler_state_table.bo);
2709
2710     /* private function & data */
2711     pp_context->pp_x_steps = pp_dndi_x_steps;
2712     pp_context->pp_y_steps = pp_dndi_y_steps;
2713     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2714
2715     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2716     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2717     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2718     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2719
2720     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2721     pp_inline_parameter->grf5.number_blocks = w / 16;
2722     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2723     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2724
2725     pp_dndi_context->dest_w = w;
2726     pp_dndi_context->dest_h = h;
2727
2728     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2729
2730     return VA_STATUS_SUCCESS;
2731 }
2732
2733 static int
2734 pp_dn_x_steps(void *private_context)
2735 {
2736     return 1;
2737 }
2738
2739 static int
2740 pp_dn_y_steps(void *private_context)
2741 {
2742     struct pp_dn_context *pp_dn_context = private_context;
2743
2744     return pp_dn_context->dest_h / 8;
2745 }
2746
2747 static int
2748 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2749 {
2750     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2751
2752     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2753     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2754
2755     return 0;
2756 }
2757
2758 static VAStatus
2759 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2760                       const struct i965_surface *src_surface,
2761                       const VARectangle *src_rect,
2762                       struct i965_surface *dst_surface,
2763                       const VARectangle *dst_rect,
2764                       void *filter_param)
2765 {
2766     struct i965_driver_data *i965 = i965_driver_data(ctx);
2767     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2768     struct object_surface *obj_surface;
2769     struct i965_sampler_dndi *sampler_dndi;
2770     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2771     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2772     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2773     int index;
2774     int w, h;
2775     int orig_w, orig_h;
2776     int dn_strength = 15;
2777     int dndi_top_first = 1;
2778     int dn_progressive = 0;
2779
2780     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2781         dndi_top_first = 1;
2782         dn_progressive = 1;
2783     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2784         dndi_top_first = 1;
2785         dn_progressive = 0;
2786     } else {
2787         dndi_top_first = 0;
2788         dn_progressive = 0;
2789     }
2790
2791     if (dn_filter_param) {
2792         float value = dn_filter_param->value;
2793
2794         if (value > 1.0)
2795             value = 1.0;
2796
2797         if (value < 0.0)
2798             value = 0.0;
2799
2800         dn_strength = (int)(value * 31.0F);
2801     }
2802
2803     /* surface */
2804     obj_surface = SURFACE(src_surface->id);
2805     orig_w = obj_surface->orig_width;
2806     orig_h = obj_surface->orig_height;
2807     w = obj_surface->width;
2808     h = obj_surface->height;
2809
2810     if (pp_context->stmm.bo == NULL) {
2811         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2812                                            "STMM surface",
2813                                            w * h,
2814                                            4096);
2815         assert(pp_context->stmm.bo);
2816     }
2817
2818     /* source UV surface index 2 */
2819     i965_pp_set_surface_state(ctx, pp_context,
2820                               obj_surface->bo, w * h,
2821                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2822                               2, 0);
2823
2824     /* source YUV surface index 4 */
2825     i965_pp_set_surface2_state(ctx, pp_context,
2826                                obj_surface->bo, 0,
2827                                orig_w, orig_h, w,
2828                                0, h,
2829                                SURFACE_FORMAT_PLANAR_420_8, 1,
2830                                4);
2831
2832     /* source STMM surface index 20 */
2833     i965_pp_set_surface_state(ctx, pp_context,
2834                               pp_context->stmm.bo, 0,
2835                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2836                               20, 1);
2837
2838     /* destination surface */
2839     obj_surface = SURFACE(dst_surface->id);
2840     orig_w = obj_surface->orig_width;
2841     orig_h = obj_surface->orig_height;
2842     w = obj_surface->width;
2843     h = obj_surface->height;
2844
2845     /* destination Y surface index 7 */
2846     i965_pp_set_surface_state(ctx, pp_context,
2847                               obj_surface->bo, 0,
2848                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2849                               7, 1);
2850
2851     /* destination UV surface index 8 */
2852     i965_pp_set_surface_state(ctx, pp_context,
2853                               obj_surface->bo, w * h,
2854                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2855                               8, 1);
2856     /* sampler dn */
2857     dri_bo_map(pp_context->sampler_state_table.bo, True);
2858     assert(pp_context->sampler_state_table.bo->virtual);
2859     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2860     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2861
2862     /* sample dndi index 1 */
2863     index = 0;
2864     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2865     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2866     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2867     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2868
2869     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2870     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2871     sampler_dndi[index].dw1.stmm_c2 = 0;
2872     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2873     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2874
2875     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2876     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2877     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2878     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2879
2880     sampler_dndi[index].dw3.maximum_stmm = 128;
2881     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2882     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2883     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2884     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2885
2886     sampler_dndi[index].dw4.sdi_delta = 8;
2887     sampler_dndi[index].dw4.sdi_threshold = 128;
2888     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2889     sampler_dndi[index].dw4.stmm_shift_up = 0;
2890     sampler_dndi[index].dw4.stmm_shift_down = 0;
2891     sampler_dndi[index].dw4.minimum_stmm = 0;
2892
2893     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2894     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2895     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2896     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2897
2898     sampler_dndi[index].dw6.dn_enable = 1;
2899     sampler_dndi[index].dw6.di_enable = 0;
2900     sampler_dndi[index].dw6.di_partial = 0;
2901     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2902     sampler_dndi[index].dw6.dndi_stream_id = 1;
2903     sampler_dndi[index].dw6.dndi_first_frame = 1;
2904     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2905     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2906     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2907     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2908
2909     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2910     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2911     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2912     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2913
2914     dri_bo_unmap(pp_context->sampler_state_table.bo);
2915
2916     /* private function & data */
2917     pp_context->pp_x_steps = pp_dn_x_steps;
2918     pp_context->pp_y_steps = pp_dn_y_steps;
2919     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2920
2921     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2922     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2923     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2924     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2925
2926     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2927     pp_inline_parameter->grf5.number_blocks = w / 16;
2928     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2929     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2930
2931     pp_dn_context->dest_w = w;
2932     pp_dn_context->dest_h = h;
2933
2934     dst_surface->flags = src_surface->flags;
2935
2936     return VA_STATUS_SUCCESS;
2937 }
2938
2939 static int
2940 gen7_pp_dndi_x_steps(void *private_context)
2941 {
2942     struct pp_dndi_context *pp_dndi_context = private_context;
2943
2944     return pp_dndi_context->dest_w / 16;
2945 }
2946
2947 static int
2948 gen7_pp_dndi_y_steps(void *private_context)
2949 {
2950     struct pp_dndi_context *pp_dndi_context = private_context;
2951
2952     return pp_dndi_context->dest_h / 4;
2953 }
2954
2955 static int
2956 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2957 {
2958     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2959
2960     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2961     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2962
2963     return 0;
2964 }
2965
2966 static VAStatus
2967 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2968                              const struct i965_surface *src_surface,
2969                              const VARectangle *src_rect,
2970                              struct i965_surface *dst_surface,
2971                              const VARectangle *dst_rect,
2972                              void *filter_param)
2973 {
2974     struct i965_driver_data *i965 = i965_driver_data(ctx);
2975     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2976     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2977     struct object_surface *obj_surface;
2978     struct gen7_sampler_dndi *sampler_dndi;
2979     int index;
2980     int w, h;
2981     int orig_w, orig_h;
2982     int dndi_top_first = 1;
2983
2984     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2985         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2986
2987     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2988         dndi_top_first = 1;
2989     else
2990         dndi_top_first = 0;
2991
2992     /* surface */
2993     obj_surface = SURFACE(src_surface->id);
2994     orig_w = obj_surface->orig_width;
2995     orig_h = obj_surface->orig_height;
2996     w = obj_surface->width;
2997     h = obj_surface->height;
2998
2999     if (pp_context->stmm.bo == NULL) {
3000         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3001                                            "STMM surface",
3002                                            w * h,
3003                                            4096);
3004         assert(pp_context->stmm.bo);
3005     }
3006
3007     /* source UV surface index 1 */
3008     gen7_pp_set_surface_state(ctx, pp_context,
3009                               obj_surface->bo, w * h,
3010                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3011                               1, 0);
3012
3013     /* source YUV surface index 3 */
3014     gen7_pp_set_surface2_state(ctx, pp_context,
3015                                obj_surface->bo, 0,
3016                                orig_w, orig_h, w,
3017                                0, h,
3018                                SURFACE_FORMAT_PLANAR_420_8, 1,
3019                                3);
3020
3021     /* source (temporal reference) YUV surface index 4 */
3022     gen7_pp_set_surface2_state(ctx, pp_context,
3023                                obj_surface->bo, 0,
3024                                orig_w, orig_h, w,
3025                                0, h,
3026                                SURFACE_FORMAT_PLANAR_420_8, 1,
3027                                4);
3028
3029     /* STMM / History Statistics input surface, index 5 */
3030     gen7_pp_set_surface_state(ctx, pp_context,
3031                               pp_context->stmm.bo, 0,
3032                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3033                               5, 1);
3034
3035     /* destination surface */
3036     obj_surface = SURFACE(dst_surface->id);
3037     orig_w = obj_surface->orig_width;
3038     orig_h = obj_surface->orig_height;
3039     w = obj_surface->width;
3040     h = obj_surface->height;
3041
3042     /* destination(Previous frame) Y surface index 27 */
3043     gen7_pp_set_surface_state(ctx, pp_context,
3044                               obj_surface->bo, 0,
3045                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3046                               27, 1);
3047
3048     /* destination(Previous frame) UV surface index 28 */
3049     gen7_pp_set_surface_state(ctx, pp_context,
3050                               obj_surface->bo, w * h,
3051                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3052                               28, 1);
3053
3054     /* destination(Current frame) Y surface index 30 */
3055     gen7_pp_set_surface_state(ctx, pp_context,
3056                               obj_surface->bo, 0,
3057                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3058                               30, 1);
3059
3060     /* destination(Current frame) UV surface index 31 */
3061     gen7_pp_set_surface_state(ctx, pp_context,
3062                               obj_surface->bo, w * h,
3063                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3064                               31, 1);
3065
3066     /* STMM output surface, index 33 */
3067     gen7_pp_set_surface_state(ctx, pp_context,
3068                               pp_context->stmm.bo, 0,
3069                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3070                               33, 1);
3071
3072
3073     /* sampler dndi */
3074     dri_bo_map(pp_context->sampler_state_table.bo, True);
3075     assert(pp_context->sampler_state_table.bo->virtual);
3076     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
3077     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
3078
3079     /* sample dndi index 0 */
3080     index = 0;
3081     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
3082     sampler_dndi[index].dw0.dnmh_delt = 8;
3083     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
3084     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
3085     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
3086     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
3087
3088     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3089     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
3090     sampler_dndi[index].dw1.stmm_c2 = 0;
3091     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
3092     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
3093
3094     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
3095     sampler_dndi[index].dw2.bne_edge_th = 1;
3096     sampler_dndi[index].dw2.smooth_mv_th = 0;
3097     sampler_dndi[index].dw2.sad_tight_th = 5;
3098     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
3099     sampler_dndi[index].dw2.good_neighbor_th = 4;
3100
3101     sampler_dndi[index].dw3.maximum_stmm = 128;
3102     sampler_dndi[index].dw3.multipler_for_vecm = 2;
3103     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3104     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3105     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
3106
3107     sampler_dndi[index].dw4.sdi_delta = 8;
3108     sampler_dndi[index].dw4.sdi_threshold = 128;
3109     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3110     sampler_dndi[index].dw4.stmm_shift_up = 0;
3111     sampler_dndi[index].dw4.stmm_shift_down = 0;
3112     sampler_dndi[index].dw4.minimum_stmm = 0;
3113
3114     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
3115     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
3116     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3117     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3118
3119     sampler_dndi[index].dw6.dn_enable = 0;
3120     sampler_dndi[index].dw6.di_enable = 1;
3121     sampler_dndi[index].dw6.di_partial = 0;
3122     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
3123     sampler_dndi[index].dw6.dndi_stream_id = 1;
3124     sampler_dndi[index].dw6.dndi_first_frame = 1;
3125     sampler_dndi[index].dw6.progressive_dn = 0;
3126     sampler_dndi[index].dw6.mcdi_enable = 0;
3127     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3128     sampler_dndi[index].dw6.cat_th1 = 0;
3129     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3130     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3131
3132     sampler_dndi[index].dw7.sad_tha = 5;
3133     sampler_dndi[index].dw7.sad_thb = 10;
3134     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3135     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3136     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3137     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3138     sampler_dndi[index].dw7.neighborpixel_th = 10;
3139     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3140
3141     dri_bo_unmap(pp_context->sampler_state_table.bo);
3142
3143     /* private function & data */
3144     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3145     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3146     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3147
3148     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3149     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3150     pp_static_parameter->grf1.di_top_field_first = 0;
3151     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3152
3153     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3154     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3155     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3156
3157     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3158     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3159
3160     pp_dndi_context->dest_w = w;
3161     pp_dndi_context->dest_h = h;
3162
3163     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3164
3165     return VA_STATUS_SUCCESS;
3166 }
3167
3168 static int
3169 gen7_pp_dn_x_steps(void *private_context)
3170 {
3171     struct pp_dn_context *pp_dn_context = private_context;
3172
3173     return pp_dn_context->dest_w / 16;
3174 }
3175
3176 static int
3177 gen7_pp_dn_y_steps(void *private_context)
3178 {
3179     struct pp_dn_context *pp_dn_context = private_context;
3180
3181     return pp_dn_context->dest_h / 4;
3182 }
3183
3184 static int
3185 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3186 {
3187     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3188
3189     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3190     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3191
3192     return 0;
3193 }
3194
3195 static VAStatus
3196 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3197                            const struct i965_surface *src_surface,
3198                            const VARectangle *src_rect,
3199                            struct i965_surface *dst_surface,
3200                            const VARectangle *dst_rect,
3201                            void *filter_param)
3202 {
3203     struct i965_driver_data *i965 = i965_driver_data(ctx);
3204     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3205     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3206     struct object_surface *obj_surface;
3207     struct gen7_sampler_dndi *sampler_dn;
3208     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3209     int index;
3210     int w, h;
3211     int orig_w, orig_h;
3212     int dn_strength = 15;
3213     int dndi_top_first = 1;
3214     int dn_progressive = 0;
3215
3216     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3217         dndi_top_first = 1;
3218         dn_progressive = 1;
3219     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3220         dndi_top_first = 1;
3221         dn_progressive = 0;
3222     } else {
3223         dndi_top_first = 0;
3224         dn_progressive = 0;
3225     }
3226
3227     if (dn_filter_param) {
3228         float value = dn_filter_param->value;
3229
3230         if (value > 1.0)
3231             value = 1.0;
3232
3233         if (value < 0.0)
3234             value = 0.0;
3235
3236         dn_strength = (int)(value * 31.0F);
3237     }
3238
3239     /* surface */
3240     obj_surface = SURFACE(src_surface->id);
3241     orig_w = obj_surface->orig_width;
3242     orig_h = obj_surface->orig_height;
3243     w = obj_surface->width;
3244     h = obj_surface->height;
3245
3246     if (pp_context->stmm.bo == NULL) {
3247         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3248                                            "STMM surface",
3249                                            w * h,
3250                                            4096);
3251         assert(pp_context->stmm.bo);
3252     }
3253
3254     /* source UV surface index 1 */
3255     gen7_pp_set_surface_state(ctx, pp_context,
3256                               obj_surface->bo, w * h,
3257                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3258                               1, 0);
3259
3260     /* source YUV surface index 3 */
3261     gen7_pp_set_surface2_state(ctx, pp_context,
3262                                obj_surface->bo, 0,
3263                                orig_w, orig_h, w,
3264                                0, h,
3265                                SURFACE_FORMAT_PLANAR_420_8, 1,
3266                                3);
3267
3268     /* source (temporal reference) YUV surface index 4 */
3269     gen7_pp_set_surface2_state(ctx, pp_context,
3270                                obj_surface->bo, 0,
3271                                orig_w, orig_h, w,
3272                                0, h,
3273                                SURFACE_FORMAT_PLANAR_420_8, 1,
3274                                4);
3275
3276     /* STMM / History Statistics input surface, index 5 */
3277     gen7_pp_set_surface_state(ctx, pp_context,
3278                               pp_context->stmm.bo, 0,
3279                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3280                               5, 1);
3281
3282     /* destination surface */
3283     obj_surface = SURFACE(dst_surface->id);
3284     orig_w = obj_surface->orig_width;
3285     orig_h = obj_surface->orig_height;
3286     w = obj_surface->width;
3287     h = obj_surface->height;
3288
3289     /* destination Y surface index 24 */
3290     gen7_pp_set_surface_state(ctx, pp_context,
3291                               obj_surface->bo, 0,
3292                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3293                               24, 1);
3294
3295     /* destination UV surface index 25 */
3296     gen7_pp_set_surface_state(ctx, pp_context,
3297                               obj_surface->bo, w * h,
3298                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3299                               25, 1);
3300
3301     /* sampler dn */
3302     dri_bo_map(pp_context->sampler_state_table.bo, True);
3303     assert(pp_context->sampler_state_table.bo->virtual);
3304     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3305     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3306
3307     /* sample dn index 1 */
3308     index = 0;
3309     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3310     sampler_dn[index].dw0.dnmh_delt = 8;
3311     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3312     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3313     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3314     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3315
3316     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3317     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3318     sampler_dn[index].dw1.stmm_c2 = 0;
3319     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3320     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3321
3322     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3323     sampler_dn[index].dw2.bne_edge_th = 1;
3324     sampler_dn[index].dw2.smooth_mv_th = 0;
3325     sampler_dn[index].dw2.sad_tight_th = 5;
3326     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3327     sampler_dn[index].dw2.good_neighbor_th = 4;
3328
3329     sampler_dn[index].dw3.maximum_stmm = 128;
3330     sampler_dn[index].dw3.multipler_for_vecm = 2;
3331     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3332     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3333     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3334
3335     sampler_dn[index].dw4.sdi_delta = 8;
3336     sampler_dn[index].dw4.sdi_threshold = 128;
3337     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3338     sampler_dn[index].dw4.stmm_shift_up = 0;
3339     sampler_dn[index].dw4.stmm_shift_down = 0;
3340     sampler_dn[index].dw4.minimum_stmm = 0;
3341
3342     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3343     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3344     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3345     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3346
3347     sampler_dn[index].dw6.dn_enable = 1;
3348     sampler_dn[index].dw6.di_enable = 0;
3349     sampler_dn[index].dw6.di_partial = 0;
3350     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3351     sampler_dn[index].dw6.dndi_stream_id = 1;
3352     sampler_dn[index].dw6.dndi_first_frame = 1;
3353     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3354     sampler_dn[index].dw6.mcdi_enable = 0;
3355     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3356     sampler_dn[index].dw6.cat_th1 = 0;
3357     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3358     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3359
3360     sampler_dn[index].dw7.sad_tha = 5;
3361     sampler_dn[index].dw7.sad_thb = 10;
3362     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3363     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3364     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3365     sampler_dn[index].dw7.vdi_walker_enable = 0;
3366     sampler_dn[index].dw7.neighborpixel_th = 10;
3367     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3368
3369     dri_bo_unmap(pp_context->sampler_state_table.bo);
3370
3371     /* private function & data */
3372     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3373     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3374     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3375
3376     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3377     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3378     pp_static_parameter->grf1.di_top_field_first = 0;
3379     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3380
3381     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3382     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3383     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3384
3385     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3386     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3387
3388     pp_dn_context->dest_w = w;
3389     pp_dn_context->dest_h = h;
3390
3391     dst_surface->flags = src_surface->flags;
3392
3393     return VA_STATUS_SUCCESS;
3394 }
3395
3396 static VAStatus
3397 ironlake_pp_initialize(
3398     VADriverContextP   ctx,
3399     struct i965_post_processing_context *pp_context,
3400     const struct i965_surface *src_surface,
3401     const VARectangle *src_rect,
3402     struct i965_surface *dst_surface,
3403     const VARectangle *dst_rect,
3404     int                pp_index,
3405     void *filter_param
3406 )
3407 {
3408     VAStatus va_status;
3409     struct i965_driver_data *i965 = i965_driver_data(ctx);
3410     struct pp_module *pp_module;
3411     dri_bo *bo;
3412     int static_param_size, inline_param_size;
3413
3414     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3415     bo = dri_bo_alloc(i965->intel.bufmgr,
3416                       "surface state & binding table",
3417                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3418                       4096);
3419     assert(bo);
3420     pp_context->surface_state_binding_table.bo = bo;
3421
3422     dri_bo_unreference(pp_context->curbe.bo);
3423     bo = dri_bo_alloc(i965->intel.bufmgr,
3424                       "constant buffer",
3425                       4096,
3426                       4096);
3427     assert(bo);
3428     pp_context->curbe.bo = bo;
3429
3430     dri_bo_unreference(pp_context->idrt.bo);
3431     bo = dri_bo_alloc(i965->intel.bufmgr,
3432                       "interface discriptor",
3433                       sizeof(struct i965_interface_descriptor),
3434                       4096);
3435     assert(bo);
3436     pp_context->idrt.bo = bo;
3437     pp_context->idrt.num_interface_descriptors = 0;
3438
3439     dri_bo_unreference(pp_context->sampler_state_table.bo);
3440     bo = dri_bo_alloc(i965->intel.bufmgr,
3441                       "sampler state table",
3442                       4096,
3443                       4096);
3444     assert(bo);
3445     dri_bo_map(bo, True);
3446     memset(bo->virtual, 0, bo->size);
3447     dri_bo_unmap(bo);
3448     pp_context->sampler_state_table.bo = bo;
3449
3450     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3451     bo = dri_bo_alloc(i965->intel.bufmgr,
3452                       "sampler 8x8 state ",
3453                       4096,
3454                       4096);
3455     assert(bo);
3456     pp_context->sampler_state_table.bo_8x8 = bo;
3457
3458     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3459     bo = dri_bo_alloc(i965->intel.bufmgr,
3460                       "sampler 8x8 state ",
3461                       4096,
3462                       4096);
3463     assert(bo);
3464     pp_context->sampler_state_table.bo_8x8_uv = bo;
3465
3466     dri_bo_unreference(pp_context->vfe_state.bo);
3467     bo = dri_bo_alloc(i965->intel.bufmgr,
3468                       "vfe state",
3469                       sizeof(struct i965_vfe_state),
3470                       4096);
3471     assert(bo);
3472     pp_context->vfe_state.bo = bo;
3473
3474     static_param_size = sizeof(struct pp_static_parameter);
3475     inline_param_size = sizeof(struct pp_inline_parameter);
3476
3477     memset(pp_context->pp_static_parameter, 0, static_param_size);
3478     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3479
3480     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3481     pp_context->current_pp = pp_index;
3482     pp_module = &pp_context->pp_modules[pp_index];
3483
3484     if (pp_module->initialize)
3485         va_status = pp_module->initialize(ctx, pp_context,
3486                                           src_surface,
3487                                           src_rect,
3488                                           dst_surface,
3489                                           dst_rect,
3490                                           filter_param);
3491     else
3492         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3493
3494     return va_status;
3495 }
3496
3497 static VAStatus
3498 ironlake_post_processing(
3499     VADriverContextP   ctx,
3500     struct i965_post_processing_context *pp_context,
3501     const struct i965_surface *src_surface,
3502     const VARectangle *src_rect,
3503     struct i965_surface *dst_surface,
3504     const VARectangle *dst_rect,
3505     int                pp_index,
3506     void *filter_param
3507 )
3508 {
3509     VAStatus va_status;
3510
3511     va_status = ironlake_pp_initialize(ctx, pp_context,
3512                                        src_surface,
3513                                        src_rect,
3514                                        dst_surface,
3515                                        dst_rect,
3516                                        pp_index,
3517                                        filter_param);
3518
3519     if (va_status == VA_STATUS_SUCCESS) {
3520         ironlake_pp_states_setup(ctx, pp_context);
3521         ironlake_pp_pipeline_setup(ctx, pp_context);
3522     }
3523
3524     return va_status;
3525 }
3526
3527 static VAStatus
3528 gen6_pp_initialize(
3529     VADriverContextP   ctx,
3530     struct i965_post_processing_context *pp_context,
3531     const struct i965_surface *src_surface,
3532     const VARectangle *src_rect,
3533     struct i965_surface *dst_surface,
3534     const VARectangle *dst_rect,
3535     int                pp_index,
3536     void *filter_param
3537 )
3538 {
3539     VAStatus va_status;
3540     struct i965_driver_data *i965 = i965_driver_data(ctx);
3541     struct pp_module *pp_module;
3542     dri_bo *bo;
3543     int static_param_size, inline_param_size;
3544
3545     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3546     bo = dri_bo_alloc(i965->intel.bufmgr,
3547                       "surface state & binding table",
3548                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3549                       4096);
3550     assert(bo);
3551     pp_context->surface_state_binding_table.bo = bo;
3552
3553     dri_bo_unreference(pp_context->curbe.bo);
3554     bo = dri_bo_alloc(i965->intel.bufmgr,
3555                       "constant buffer",
3556                       4096,
3557                       4096);
3558     assert(bo);
3559     pp_context->curbe.bo = bo;
3560
3561     dri_bo_unreference(pp_context->idrt.bo);
3562     bo = dri_bo_alloc(i965->intel.bufmgr,
3563                       "interface discriptor",
3564                       sizeof(struct gen6_interface_descriptor_data),
3565                       4096);
3566     assert(bo);
3567     pp_context->idrt.bo = bo;
3568     pp_context->idrt.num_interface_descriptors = 0;
3569
3570     dri_bo_unreference(pp_context->sampler_state_table.bo);
3571     bo = dri_bo_alloc(i965->intel.bufmgr,
3572                       "sampler state table",
3573                       4096,
3574                       4096);
3575     assert(bo);
3576     dri_bo_map(bo, True);
3577     memset(bo->virtual, 0, bo->size);
3578     dri_bo_unmap(bo);
3579     pp_context->sampler_state_table.bo = bo;
3580
3581     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3582     bo = dri_bo_alloc(i965->intel.bufmgr,
3583                       "sampler 8x8 state ",
3584                       4096,
3585                       4096);
3586     assert(bo);
3587     pp_context->sampler_state_table.bo_8x8 = bo;
3588
3589     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3590     bo = dri_bo_alloc(i965->intel.bufmgr,
3591                       "sampler 8x8 state ",
3592                       4096,
3593                       4096);
3594     assert(bo);
3595     pp_context->sampler_state_table.bo_8x8_uv = bo;
3596
3597     dri_bo_unreference(pp_context->vfe_state.bo);
3598     bo = dri_bo_alloc(i965->intel.bufmgr,
3599                       "vfe state",
3600                       sizeof(struct i965_vfe_state),
3601                       4096);
3602     assert(bo);
3603     pp_context->vfe_state.bo = bo;
3604
3605     if (IS_GEN7(i965->intel.device_id)) {
3606         static_param_size = sizeof(struct gen7_pp_static_parameter);
3607         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3608     } else {
3609         static_param_size = sizeof(struct pp_static_parameter);
3610         inline_param_size = sizeof(struct pp_inline_parameter);
3611     }
3612
3613     memset(pp_context->pp_static_parameter, 0, static_param_size);
3614     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3615
3616     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3617     pp_context->current_pp = pp_index;
3618     pp_module = &pp_context->pp_modules[pp_index];
3619
3620     if (pp_module->initialize)
3621         va_status = pp_module->initialize(ctx, pp_context,
3622                                           src_surface,
3623                                           src_rect,
3624                                           dst_surface,
3625                                           dst_rect,
3626                                           filter_param);
3627     else
3628         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3629
3630     return va_status;
3631 }
3632
3633 static void
3634 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3635                                    struct i965_post_processing_context *pp_context)
3636 {
3637     struct i965_driver_data *i965 = i965_driver_data(ctx);
3638     struct gen6_interface_descriptor_data *desc;
3639     dri_bo *bo;
3640     int pp_index = pp_context->current_pp;
3641
3642     bo = pp_context->idrt.bo;
3643     dri_bo_map(bo, True);
3644     assert(bo->virtual);
3645     desc = bo->virtual;
3646     memset(desc, 0, sizeof(*desc));
3647     desc->desc0.kernel_start_pointer =
3648         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3649     desc->desc1.single_program_flow = 1;
3650     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3651     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3652     desc->desc2.sampler_state_pointer =
3653         pp_context->sampler_state_table.bo->offset >> 5;
3654     desc->desc3.binding_table_entry_count = 0;
3655     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3656     desc->desc4.constant_urb_entry_read_offset = 0;
3657
3658     if (IS_GEN7(i965->intel.device_id))
3659         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3660     else
3661         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3662
3663     dri_bo_emit_reloc(bo,
3664                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3665                       0,
3666                       offsetof(struct gen6_interface_descriptor_data, desc0),
3667                       pp_context->pp_modules[pp_index].kernel.bo);
3668
3669     dri_bo_emit_reloc(bo,
3670                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3671                       desc->desc2.sampler_count << 2,
3672                       offsetof(struct gen6_interface_descriptor_data, desc2),
3673                       pp_context->sampler_state_table.bo);
3674
3675     dri_bo_unmap(bo);
3676     pp_context->idrt.num_interface_descriptors++;
3677 }
3678
3679 static void
3680 gen6_pp_upload_constants(VADriverContextP ctx,
3681                          struct i965_post_processing_context *pp_context)
3682 {
3683     struct i965_driver_data *i965 = i965_driver_data(ctx);
3684     unsigned char *constant_buffer;
3685     int param_size;
3686
3687     assert(sizeof(struct pp_static_parameter) == 128);
3688     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3689
3690     if (IS_GEN7(i965->intel.device_id))
3691         param_size = sizeof(struct gen7_pp_static_parameter);
3692     else
3693         param_size = sizeof(struct pp_static_parameter);
3694
3695     dri_bo_map(pp_context->curbe.bo, 1);
3696     assert(pp_context->curbe.bo->virtual);
3697     constant_buffer = pp_context->curbe.bo->virtual;
3698     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3699     dri_bo_unmap(pp_context->curbe.bo);
3700 }
3701
3702 static void
3703 gen6_pp_states_setup(VADriverContextP ctx,
3704                      struct i965_post_processing_context *pp_context)
3705 {
3706     gen6_pp_interface_descriptor_table(ctx, pp_context);
3707     gen6_pp_upload_constants(ctx, pp_context);
3708 }
3709
3710 static void
3711 gen6_pp_pipeline_select(VADriverContextP ctx,
3712                         struct i965_post_processing_context *pp_context)
3713 {
3714     struct intel_batchbuffer *batch = pp_context->batch;
3715
3716     BEGIN_BATCH(batch, 1);
3717     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3718     ADVANCE_BATCH(batch);
3719 }
3720
3721 static void
3722 gen6_pp_state_base_address(VADriverContextP ctx,
3723                            struct i965_post_processing_context *pp_context)
3724 {
3725     struct intel_batchbuffer *batch = pp_context->batch;
3726
3727     BEGIN_BATCH(batch, 10);
3728     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3729     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3730     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3731     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3732     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3733     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3734     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3735     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3736     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3737     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3738     ADVANCE_BATCH(batch);
3739 }
3740
3741 static void
3742 gen6_pp_vfe_state(VADriverContextP ctx,
3743                   struct i965_post_processing_context *pp_context)
3744 {
3745     struct intel_batchbuffer *batch = pp_context->batch;
3746
3747     BEGIN_BATCH(batch, 8);
3748     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3749     OUT_BATCH(batch, 0);
3750     OUT_BATCH(batch,
3751               (pp_context->urb.num_vfe_entries - 1) << 16 |
3752               pp_context->urb.num_vfe_entries << 8);
3753     OUT_BATCH(batch, 0);
3754     OUT_BATCH(batch,
3755               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3756               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3757     OUT_BATCH(batch, 0);
3758     OUT_BATCH(batch, 0);
3759     OUT_BATCH(batch, 0);
3760     ADVANCE_BATCH(batch);
3761 }
3762
3763 static void
3764 gen6_pp_curbe_load(VADriverContextP ctx,
3765                    struct i965_post_processing_context *pp_context)
3766 {
3767     struct intel_batchbuffer *batch = pp_context->batch;
3768
3769     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3770
3771     BEGIN_BATCH(batch, 4);
3772     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3773     OUT_BATCH(batch, 0);
3774     OUT_BATCH(batch,
3775               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3776     OUT_RELOC(batch,
3777               pp_context->curbe.bo,
3778               I915_GEM_DOMAIN_INSTRUCTION, 0,
3779               0);
3780     ADVANCE_BATCH(batch);
3781 }
3782
3783 static void
3784 gen6_interface_descriptor_load(VADriverContextP ctx,
3785                                struct i965_post_processing_context *pp_context)
3786 {
3787     struct intel_batchbuffer *batch = pp_context->batch;
3788
3789     BEGIN_BATCH(batch, 4);
3790     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3791     OUT_BATCH(batch, 0);
3792     OUT_BATCH(batch,
3793               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3794     OUT_RELOC(batch,
3795               pp_context->idrt.bo,
3796               I915_GEM_DOMAIN_INSTRUCTION, 0,
3797               0);
3798     ADVANCE_BATCH(batch);
3799 }
3800
3801 static void
3802 gen6_pp_object_walker(VADriverContextP ctx,
3803                       struct i965_post_processing_context *pp_context)
3804 {
3805     struct i965_driver_data *i965 = i965_driver_data(ctx);
3806     struct intel_batchbuffer *batch = pp_context->batch;
3807     int x, x_steps, y, y_steps;
3808     int param_size, command_length_in_dws;
3809     dri_bo *command_buffer;
3810     unsigned int *command_ptr;
3811
3812     if (IS_GEN7(i965->intel.device_id))
3813         param_size = sizeof(struct gen7_pp_inline_parameter);
3814     else
3815         param_size = sizeof(struct pp_inline_parameter);
3816
3817     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3818     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3819     command_length_in_dws = 6 + (param_size >> 2);
3820     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3821                                   "command objects buffer",
3822                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3823                                   4096);
3824
3825     dri_bo_map(command_buffer, 1);
3826     command_ptr = command_buffer->virtual;
3827
3828     for (y = 0; y < y_steps; y++) {
3829         for (x = 0; x < x_steps; x++) {
3830             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3831                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3832                 *command_ptr++ = 0;
3833                 *command_ptr++ = 0;
3834                 *command_ptr++ = 0;
3835                 *command_ptr++ = 0;
3836                 *command_ptr++ = 0;
3837                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3838                 command_ptr += (param_size >> 2);
3839             }
3840         }
3841     }
3842
3843     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3844         *command_ptr++ = 0;
3845
3846     *command_ptr = MI_BATCH_BUFFER_END;
3847
3848     dri_bo_unmap(command_buffer);
3849
3850     BEGIN_BATCH(batch, 2);
3851     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3852     OUT_RELOC(batch, command_buffer,
3853               I915_GEM_DOMAIN_COMMAND, 0,
3854               0);
3855     ADVANCE_BATCH(batch);
3856
3857     dri_bo_unreference(command_buffer);
3858
3859     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3860      * will cause control to pass back to ring buffer
3861      */
3862     intel_batchbuffer_end_atomic(batch);
3863     intel_batchbuffer_flush(batch);
3864     intel_batchbuffer_start_atomic(batch, 0x1000);
3865 }
3866
3867 static void
3868 gen6_pp_pipeline_setup(VADriverContextP ctx,
3869                        struct i965_post_processing_context *pp_context)
3870 {
3871     struct intel_batchbuffer *batch = pp_context->batch;
3872
3873     intel_batchbuffer_start_atomic(batch, 0x1000);
3874     intel_batchbuffer_emit_mi_flush(batch);
3875     gen6_pp_pipeline_select(ctx, pp_context);
3876     gen6_pp_state_base_address(ctx, pp_context);
3877     gen6_pp_vfe_state(ctx, pp_context);
3878     gen6_pp_curbe_load(ctx, pp_context);
3879     gen6_interface_descriptor_load(ctx, pp_context);
3880     gen6_pp_object_walker(ctx, pp_context);
3881     intel_batchbuffer_end_atomic(batch);
3882 }
3883
3884 static VAStatus
3885 gen6_post_processing(
3886     VADriverContextP   ctx,
3887     struct i965_post_processing_context *pp_context,
3888     const struct i965_surface *src_surface,
3889     const VARectangle *src_rect,
3890     struct i965_surface *dst_surface,
3891     const VARectangle *dst_rect,
3892     int                pp_index,
3893     void * filter_param
3894 )
3895 {
3896     VAStatus va_status;
3897
3898     va_status = gen6_pp_initialize(ctx, pp_context,
3899                                    src_surface,
3900                                    src_rect,
3901                                    dst_surface,
3902                                    dst_rect,
3903                                    pp_index,
3904                                    filter_param);
3905
3906     if (va_status == VA_STATUS_SUCCESS) {
3907         gen6_pp_states_setup(ctx, pp_context);
3908         gen6_pp_pipeline_setup(ctx, pp_context);
3909     }
3910
3911     return va_status;
3912 }
3913
3914 static VAStatus
3915 i965_post_processing_internal(
3916     VADriverContextP   ctx,
3917     struct i965_post_processing_context *pp_context,
3918     const struct i965_surface *src_surface,
3919     const VARectangle *src_rect,
3920     struct i965_surface *dst_surface,
3921     const VARectangle *dst_rect,
3922     int                pp_index,
3923     void *filter_param
3924 )
3925 {
3926     struct i965_driver_data *i965 = i965_driver_data(ctx);
3927     VAStatus va_status;
3928
3929     if (IS_GEN6(i965->intel.device_id) ||
3930         IS_GEN7(i965->intel.device_id))
3931         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3932     else
3933         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3934
3935     return va_status;
3936 }
3937
3938 VAStatus
3939 i965_DestroySurfaces(VADriverContextP ctx,
3940                      VASurfaceID *surface_list,
3941                      int num_surfaces);
3942 VAStatus
3943 i965_CreateSurfaces(VADriverContextP ctx,
3944                     int width,
3945                     int height,
3946                     int format,
3947                     int num_surfaces,
3948                     VASurfaceID *surfaces);
3949
3950 static void
3951 rgb_to_yuv(unsigned int argb,
3952            unsigned char *y,
3953            unsigned char *u,
3954            unsigned char *v,
3955            unsigned char *a)
3956 {
3957     int r = ((argb >> 16) & 0xff);
3958     int g = ((argb >> 8) & 0xff);
3959     int b = ((argb >> 0) & 0xff);
3960
3961     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3962     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3963     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3964     *a = ((argb >> 24) & 0xff);
3965 }
3966
3967 static void
3968 i965_vpp_clear_surface(VADriverContextP ctx,
3969                        struct i965_post_processing_context *pp_context,
3970                        VASurfaceID surface,
3971                        unsigned int color)
3972 {
3973     struct i965_driver_data *i965 = i965_driver_data(ctx);
3974     struct intel_batchbuffer *batch = pp_context->batch;
3975     struct object_surface *obj_surface = SURFACE(surface);
3976     unsigned int blt_cmd, br13;
3977     unsigned int tiling = 0, swizzle = 0;
3978     int pitch;
3979     unsigned char y, u, v, a = 0;
3980
3981     /* Currently only support NV12 surface */
3982     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3983         return;
3984
3985     rgb_to_yuv(color, &y, &u, &v, &a);
3986
3987     if (a == 0)
3988         return;
3989
3990     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3991     blt_cmd = XY_COLOR_BLT_CMD;
3992     pitch = obj_surface->width;
3993
3994     if (tiling != I915_TILING_NONE) {
3995         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3996         pitch >>= 2;
3997     }
3998
3999     br13 = 0xf0 << 16;
4000     br13 |= BR13_8;
4001     br13 |= pitch;
4002
4003     if (IS_GEN6(i965->intel.device_id) ||
4004         IS_GEN7(i965->intel.device_id)) {
4005         intel_batchbuffer_start_atomic_blt(batch, 48);
4006         BEGIN_BLT_BATCH(batch, 12);
4007     } else {
4008         intel_batchbuffer_start_atomic(batch, 48);
4009         BEGIN_BATCH(batch, 12);
4010     }
4011
4012     OUT_BATCH(batch, blt_cmd);
4013     OUT_BATCH(batch, br13);
4014     OUT_BATCH(batch,
4015               0 << 16 |
4016               0);
4017     OUT_BATCH(batch,
4018               obj_surface->height << 16 |
4019               obj_surface->width);
4020     OUT_RELOC(batch, obj_surface->bo,
4021               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4022               0);
4023     OUT_BATCH(batch, y);
4024
4025     br13 = 0xf0 << 16;
4026     br13 |= BR13_565;
4027     br13 |= pitch;
4028
4029     OUT_BATCH(batch, blt_cmd);
4030     OUT_BATCH(batch, br13);
4031     OUT_BATCH(batch,
4032               0 << 16 |
4033               0);
4034     OUT_BATCH(batch,
4035               obj_surface->height / 2 << 16 |
4036               obj_surface->width / 2);
4037     OUT_RELOC(batch, obj_surface->bo,
4038               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4039               obj_surface->width * obj_surface->y_cb_offset);
4040     OUT_BATCH(batch, v << 8 | u);
4041
4042     ADVANCE_BATCH(batch);
4043     intel_batchbuffer_end_atomic(batch);
4044 }
4045
4046 VASurfaceID
4047 i965_post_processing(
4048     VADriverContextP   ctx,
4049     VASurfaceID        surface,
4050     const VARectangle *src_rect,
4051     const VARectangle *dst_rect,
4052     unsigned int       flags,
4053     int               *has_done_scaling
4054 )
4055 {
4056     struct i965_driver_data *i965 = i965_driver_data(ctx);
4057     VASurfaceID in_surface_id = surface;
4058     VASurfaceID out_surface_id = VA_INVALID_ID;
4059
4060     *has_done_scaling = 0;
4061
4062     if (HAS_PP(i965)) {
4063         struct object_surface *obj_surface;
4064         VAStatus status;
4065         struct i965_surface src_surface;
4066         struct i965_surface dst_surface;
4067
4068         obj_surface = SURFACE(in_surface_id);
4069
4070         /* Currently only support post processing for NV12 surface */
4071         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
4072             return out_surface_id;
4073
4074         _i965LockMutex(&i965->pp_mutex);
4075
4076         if (flags & I965_PP_FLAG_MCDI) {
4077             status = i965_CreateSurfaces(ctx,
4078                                          obj_surface->orig_width,
4079                                          obj_surface->orig_height,
4080                                          VA_RT_FORMAT_YUV420,
4081                                          1,
4082                                          &out_surface_id);
4083             assert(status == VA_STATUS_SUCCESS);
4084             obj_surface = SURFACE(out_surface_id);
4085             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4086             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4087             src_surface.id = in_surface_id;
4088             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4089             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
4090                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
4091             dst_surface.id = out_surface_id;
4092             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4093             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4094
4095             i965_post_processing_internal(ctx, i965->pp_context,
4096                                           &src_surface,
4097                                           src_rect,
4098                                           &dst_surface,
4099                                           dst_rect,
4100                                           PP_NV12_DNDI,
4101                                           NULL);
4102         }
4103
4104         if (flags & I965_PP_FLAG_AVS) {
4105             struct i965_render_state *render_state = &i965->render_state;
4106             struct intel_region *dest_region = render_state->draw_region;
4107
4108             if (out_surface_id != VA_INVALID_ID)
4109                 in_surface_id = out_surface_id;
4110
4111             status = i965_CreateSurfaces(ctx,
4112                                          dest_region->width,
4113                                          dest_region->height,
4114                                          VA_RT_FORMAT_YUV420,
4115                                          1,
4116                                          &out_surface_id);
4117             assert(status == VA_STATUS_SUCCESS);
4118             obj_surface = SURFACE(out_surface_id);
4119             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4120             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4121             src_surface.id = in_surface_id;
4122             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4123             src_surface.flags = I965_SURFACE_FLAG_FRAME;
4124             dst_surface.id = out_surface_id;
4125             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4126             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4127
4128             i965_post_processing_internal(ctx, i965->pp_context,
4129                                           &src_surface,
4130                                           src_rect,
4131                                           &dst_surface,
4132                                           dst_rect,
4133                                           PP_NV12_AVS,
4134                                           NULL);
4135
4136             if (in_surface_id != surface)
4137                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4138
4139             *has_done_scaling = 1;
4140         }
4141
4142         _i965UnlockMutex(&i965->pp_mutex);
4143     }
4144
4145     return out_surface_id;
4146 }
4147
4148 static VAStatus
4149 i965_image_pl1_rgbx_processing(VADriverContextP ctx,
4150                           const struct i965_surface *src_surface,
4151                           const VARectangle *src_rect,
4152                           struct i965_surface *dst_surface,
4153                           const VARectangle *dst_rect)
4154 {
4155     struct i965_driver_data *i965 = i965_driver_data(ctx);
4156     struct i965_post_processing_context *pp_context = i965->pp_context;
4157     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4158
4159     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4160         i965_post_processing_internal(ctx, i965->pp_context,
4161                                       src_surface,
4162                                       src_rect,
4163                                       dst_surface,
4164                                       dst_rect,
4165                                       PP_RGBX_LOAD_SAVE_NV12,
4166                                       NULL);
4167     } else {
4168         assert(0);
4169         return VA_STATUS_ERROR_UNKNOWN;
4170     }
4171
4172     intel_batchbuffer_flush(pp_context->batch);
4173
4174     return VA_STATUS_SUCCESS;
4175 }
4176
4177 static VAStatus
4178 i965_image_pl3_processing(VADriverContextP ctx,
4179                           const struct i965_surface *src_surface,
4180                           const VARectangle *src_rect,
4181                           struct i965_surface *dst_surface,
4182                           const VARectangle *dst_rect)
4183 {
4184     struct i965_driver_data *i965 = i965_driver_data(ctx);
4185     struct i965_post_processing_context *pp_context = i965->pp_context;
4186     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4187     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4188
4189     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4190         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4191                                                  src_surface,
4192                                                  src_rect,
4193                                                  dst_surface,
4194                                                  dst_rect,
4195                                                  PP_PL3_LOAD_SAVE_N12,
4196                                                  NULL);
4197     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4198                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4199                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4200                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4201         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4202                                                  src_surface,
4203                                                  src_rect,
4204                                                  dst_surface,
4205                                                  dst_rect,
4206                                                  PP_PL3_LOAD_SAVE_PL3,
4207                                                  NULL);
4208     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4209                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4210         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4211                                                  src_surface,
4212                                                  src_rect,
4213                                                  dst_surface,
4214                                                  dst_rect,
4215                                                  PP_PL3_LOAD_SAVE_PA,
4216                                                  NULL);
4217     }
4218     else {
4219         assert(0);
4220     }
4221
4222     intel_batchbuffer_flush(pp_context->batch);
4223
4224     return vaStatus;
4225 }
4226
4227 static VAStatus
4228 i965_image_pl2_processing(VADriverContextP ctx,
4229                           const struct i965_surface *src_surface,
4230                           const VARectangle *src_rect,
4231                           struct i965_surface *dst_surface,
4232                           const VARectangle *dst_rect)
4233 {
4234     struct i965_driver_data *i965 = i965_driver_data(ctx);
4235     struct i965_post_processing_context *pp_context = i965->pp_context;
4236     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4237     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4238
4239     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4240         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4241                                                  src_surface,
4242                                                  src_rect,
4243                                                  dst_surface,
4244                                                  dst_rect,
4245                                                  PP_NV12_LOAD_SAVE_N12,
4246                                                  NULL);
4247     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4248                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4249                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4250                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4251         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4252                                                  src_surface,
4253                                                  src_rect,
4254                                                  dst_surface,
4255                                                  dst_rect,
4256                                                  PP_NV12_LOAD_SAVE_PL3,
4257                                                  NULL);
4258     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4259                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4260         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4261                                                  src_surface,
4262                                                  src_rect,
4263                                                  dst_surface,
4264                                                  dst_rect,
4265                                                  PP_NV12_LOAD_SAVE_PA,
4266                                                      NULL);
4267     } else if (fourcc == VA_FOURCC('B', 'G', 'R', 'X') ||
4268                fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
4269                fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
4270                fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) {
4271         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4272                                       src_surface,
4273                                       src_rect,
4274                                       dst_surface,
4275                                       dst_rect,
4276                                       PP_NV12_LOAD_SAVE_RGBX,
4277                                       NULL);
4278     } else {
4279         assert(0);
4280         return VA_STATUS_ERROR_UNKNOWN;
4281     }
4282
4283     intel_batchbuffer_flush(pp_context->batch);
4284
4285     return vaStatus;
4286 }
4287
4288 static VAStatus
4289 i965_image_pl1_processing(VADriverContextP ctx,
4290                           const struct i965_surface *src_surface,
4291                           const VARectangle *src_rect,
4292                           struct i965_surface *dst_surface,
4293                           const VARectangle *dst_rect)
4294 {
4295     struct i965_driver_data *i965 = i965_driver_data(ctx);
4296     struct i965_post_processing_context *pp_context = i965->pp_context;
4297     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4298
4299     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4300         i965_post_processing_internal(ctx, i965->pp_context,
4301                                       src_surface,
4302                                       src_rect,
4303                                       dst_surface,
4304                                       dst_rect,
4305                                       PP_PA_LOAD_SAVE_NV12,
4306                                       NULL);
4307     }
4308     else if (fourcc == VA_FOURCC_YV12) {
4309         i965_post_processing_internal(ctx, i965->pp_context,
4310                                       src_surface,
4311                                       src_rect,
4312                                       dst_surface,
4313                                       dst_rect,
4314                                       PP_PA_LOAD_SAVE_PL3,
4315                                       NULL);
4316
4317     }
4318     else {
4319         return VA_STATUS_ERROR_UNKNOWN;
4320     }
4321
4322     intel_batchbuffer_flush(pp_context->batch);
4323
4324     return VA_STATUS_SUCCESS;
4325 }
4326
4327 VAStatus
4328 i965_image_processing(VADriverContextP ctx,
4329                       const struct i965_surface *src_surface,
4330                       const VARectangle *src_rect,
4331                       struct i965_surface *dst_surface,
4332                       const VARectangle *dst_rect)
4333 {
4334     struct i965_driver_data *i965 = i965_driver_data(ctx);
4335     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4336
4337     if (HAS_PP(i965)) {
4338         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4339
4340         _i965LockMutex(&i965->pp_mutex);
4341
4342         switch (fourcc) {
4343         case VA_FOURCC('Y', 'V', '1', '2'):
4344         case VA_FOURCC('I', '4', '2', '0'):
4345         case VA_FOURCC('I', 'M', 'C', '1'):
4346         case VA_FOURCC('I', 'M', 'C', '3'):
4347             status = i965_image_pl3_processing(ctx,
4348                                                src_surface,
4349                                                src_rect,
4350                                                dst_surface,
4351                                                dst_rect);
4352             break;
4353
4354         case  VA_FOURCC('N', 'V', '1', '2'):
4355             status = i965_image_pl2_processing(ctx,
4356                                                src_surface,
4357                                                src_rect,
4358                                                dst_surface,
4359                                                dst_rect);
4360             break;
4361         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4362         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4363             status = i965_image_pl1_processing(ctx,
4364                                                src_surface,
4365                                                src_rect,
4366                                                dst_surface,
4367                                                dst_rect);
4368             break;
4369         case VA_FOURCC('B', 'G', 'R', 'A'):
4370         case VA_FOURCC('B', 'G', 'R', 'X'):
4371         case VA_FOURCC('R', 'G', 'B', 'A'):
4372         case VA_FOURCC('R', 'G', 'B', 'X'):
4373             status = i965_image_pl1_rgbx_processing(ctx,
4374                                                src_surface,
4375                                                src_rect,
4376                                                dst_surface,
4377                                                dst_rect);
4378             break;
4379         default:
4380             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4381             break;
4382         }
4383
4384         _i965UnlockMutex(&i965->pp_mutex);
4385     }
4386
4387     return status;
4388 }
4389
4390 static void
4391 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4392 {
4393     int i;
4394
4395     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4396     pp_context->surface_state_binding_table.bo = NULL;
4397
4398     dri_bo_unreference(pp_context->curbe.bo);
4399     pp_context->curbe.bo = NULL;
4400
4401     dri_bo_unreference(pp_context->sampler_state_table.bo);
4402     pp_context->sampler_state_table.bo = NULL;
4403
4404     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4405     pp_context->sampler_state_table.bo_8x8 = NULL;
4406
4407     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4408     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4409
4410     dri_bo_unreference(pp_context->idrt.bo);
4411     pp_context->idrt.bo = NULL;
4412     pp_context->idrt.num_interface_descriptors = 0;
4413
4414     dri_bo_unreference(pp_context->vfe_state.bo);
4415     pp_context->vfe_state.bo = NULL;
4416
4417     dri_bo_unreference(pp_context->stmm.bo);
4418     pp_context->stmm.bo = NULL;
4419
4420     for (i = 0; i < NUM_PP_MODULES; i++) {
4421         struct pp_module *pp_module = &pp_context->pp_modules[i];
4422
4423         dri_bo_unreference(pp_module->kernel.bo);
4424         pp_module->kernel.bo = NULL;
4425     }
4426
4427     free(pp_context->pp_static_parameter);
4428     free(pp_context->pp_inline_parameter);
4429     pp_context->pp_static_parameter = NULL;
4430     pp_context->pp_inline_parameter = NULL;
4431 }
4432
4433 Bool
4434 i965_post_processing_terminate(VADriverContextP ctx)
4435 {
4436     struct i965_driver_data *i965 = i965_driver_data(ctx);
4437     struct i965_post_processing_context *pp_context = i965->pp_context;
4438
4439     if (pp_context) {
4440         i965_post_processing_context_finalize(pp_context);
4441         free(pp_context);
4442     }
4443
4444     i965->pp_context = NULL;
4445
4446     return True;
4447 }
4448
4449 static void
4450 i965_post_processing_context_init(VADriverContextP ctx,
4451                                   struct i965_post_processing_context *pp_context,
4452                                   struct intel_batchbuffer *batch)
4453 {
4454     struct i965_driver_data *i965 = i965_driver_data(ctx);
4455     int i;
4456
4457     pp_context->urb.size = URB_SIZE((&i965->intel));
4458     pp_context->urb.num_vfe_entries = 32;
4459     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4460     pp_context->urb.num_cs_entries = 1;
4461
4462     if (IS_GEN7(i965->intel.device_id))
4463         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4464     else
4465         pp_context->urb.size_cs_entry = 2;
4466
4467     pp_context->urb.vfe_start = 0;
4468     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4469         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4470     assert(pp_context->urb.cs_start +
4471            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4472
4473     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4474     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4475     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4476
4477     if (IS_GEN7(i965->intel.device_id))
4478         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4479     else if (IS_GEN6(i965->intel.device_id))
4480         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4481     else if (IS_IRONLAKE(i965->intel.device_id))
4482         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4483
4484     for (i = 0; i < NUM_PP_MODULES; i++) {
4485         struct pp_module *pp_module = &pp_context->pp_modules[i];
4486         dri_bo_unreference(pp_module->kernel.bo);
4487         if (pp_module->kernel.bin && pp_module->kernel.size) {
4488             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4489                                                 pp_module->kernel.name,
4490                                                 pp_module->kernel.size,
4491                                                 4096);
4492             assert(pp_module->kernel.bo);
4493             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4494         } else {
4495             pp_module->kernel.bo = NULL;
4496         }
4497     }
4498
4499     /* static & inline parameters */
4500     if (IS_GEN7(i965->intel.device_id)) {
4501         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4502         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4503     } else {
4504         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4505         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4506     }
4507
4508     pp_context->batch = batch;
4509 }
4510
4511 Bool
4512 i965_post_processing_init(VADriverContextP ctx)
4513 {
4514     struct i965_driver_data *i965 = i965_driver_data(ctx);
4515     struct i965_post_processing_context *pp_context = i965->pp_context;
4516
4517     if (HAS_PP(i965)) {
4518         if (pp_context == NULL) {
4519             pp_context = calloc(1, sizeof(*pp_context));
4520             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4521             i965->pp_context = pp_context;
4522         }
4523     }
4524
4525     return True;
4526 }
4527
4528 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4529     PP_NULL,    /* VAProcFilterNone */
4530     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4531     PP_NULL,    /* VAProcFilterDeblocking */
4532     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4533     PP_NULL,    /* VAProcFilterSharpening */
4534     PP_NULL,    /* VAProcFilterColorBalance */
4535     PP_NULL,    /* VAProcFilterColorStandard */
4536     PP_NULL,    /* VAProcFilterFrameRateConversion */
4537 };
4538
4539 static const int proc_frame_to_pp_frame[3] = {
4540     I965_SURFACE_FLAG_FRAME,
4541     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4542     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4543 };
4544
4545 static void
4546 i965_proc_picture(VADriverContextP ctx,
4547                   VAProfile profile,
4548                   union codec_state *codec_state,
4549                   struct hw_context *hw_context)
4550 {
4551     struct i965_driver_data *i965 = i965_driver_data(ctx);
4552     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4553     struct proc_state *proc_state = &codec_state->proc;
4554     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4555     struct object_surface *obj_surface;
4556     struct i965_surface src_surface, dst_surface;
4557     VARectangle src_rect, dst_rect;
4558     VAStatus status;
4559     int i;
4560     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4561     int num_tmp_surfaces = 0;
4562     unsigned int tiling = 0, swizzle = 0;
4563     int in_width, in_height;
4564
4565     assert(pipeline_param->surface != VA_INVALID_ID);
4566     assert(proc_state->current_render_target != VA_INVALID_ID);
4567
4568     obj_surface = SURFACE(pipeline_param->surface);
4569     in_width = obj_surface->orig_width;
4570     in_height = obj_surface->orig_height;
4571     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4572
4573     src_surface.id = pipeline_param->surface;
4574     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4575     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4576
4577     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4578         VASurfaceID out_surface_id = VA_INVALID_ID;
4579
4580         src_surface.id = pipeline_param->surface;
4581         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4582         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4583         src_rect.x = 0;
4584         src_rect.y = 0;
4585         src_rect.width = in_width;
4586         src_rect.height = in_height;
4587
4588         status = i965_CreateSurfaces(ctx,
4589                                      in_width,
4590                                      in_height,
4591                                      VA_RT_FORMAT_YUV420,
4592                                      1,
4593                                      &out_surface_id);
4594         assert(status == VA_STATUS_SUCCESS);
4595         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4596         obj_surface = SURFACE(out_surface_id);
4597         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4598
4599         dst_surface.id = out_surface_id;
4600         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4601         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4602         dst_rect.x = 0;
4603         dst_rect.y = 0;
4604         dst_rect.width = in_width;
4605         dst_rect.height = in_height;
4606
4607         status = i965_image_processing(ctx,
4608                                        &src_surface,
4609                                        &src_rect,
4610                                        &dst_surface,
4611                                        &dst_rect);
4612         assert(status == VA_STATUS_SUCCESS);
4613
4614         src_surface.id = out_surface_id;
4615         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4616         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4617     }
4618
4619     if (pipeline_param->surface_region) {
4620         src_rect.x = pipeline_param->surface_region->x;
4621         src_rect.y = pipeline_param->surface_region->y;
4622         src_rect.width = pipeline_param->surface_region->width;
4623         src_rect.height = pipeline_param->surface_region->height;
4624     } else {
4625         src_rect.x = 0;
4626         src_rect.y = 0;
4627         src_rect.width = in_width;
4628         src_rect.height = in_height;
4629     }
4630
4631     if (pipeline_param->output_region) {
4632         dst_rect.x = pipeline_param->output_region->x;
4633         dst_rect.y = pipeline_param->output_region->y;
4634         dst_rect.width = pipeline_param->output_region->width;
4635         dst_rect.height = pipeline_param->output_region->height;
4636     } else {
4637         dst_rect.x = 0;
4638         dst_rect.y = 0;
4639         dst_rect.width = in_width;
4640         dst_rect.height = in_height;
4641     }
4642
4643     obj_surface = SURFACE(proc_state->current_render_target);
4644     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4645     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4646
4647     for (i = 0; i < pipeline_param->num_filters; i++) {
4648         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4649         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4650         VAProcFilterType filter_type = filter_param->type;
4651         VASurfaceID out_surface_id = VA_INVALID_ID;
4652         int kernel_index = procfilter_to_pp_flag[filter_type];
4653
4654         if (kernel_index != PP_NULL &&
4655             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4656             status = i965_CreateSurfaces(ctx,
4657                                          in_width,
4658                                          in_height,
4659                                          VA_RT_FORMAT_YUV420,
4660                                          1,
4661                                          &out_surface_id);
4662             assert(status == VA_STATUS_SUCCESS);
4663             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4664             obj_surface = SURFACE(out_surface_id);
4665             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4666             dst_surface.id = out_surface_id;
4667             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4668             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4669                                                    &src_surface,
4670                                                    &src_rect,
4671                                                    &dst_surface,
4672                                                    &src_rect,
4673                                                    kernel_index,
4674                                                    filter_param);
4675
4676             if (status == VA_STATUS_SUCCESS) {
4677                 src_surface.id = dst_surface.id;
4678                 src_surface.type = dst_surface.type;
4679                 src_surface.flags = dst_surface.flags;
4680             }
4681         }
4682     }
4683
4684     dst_surface.id = proc_state->current_render_target;
4685     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4686
4687     if (src_rect.width == dst_rect.width &&
4688         src_rect.height == dst_rect.height) {
4689         i965_post_processing_internal(ctx, &proc_context->pp_context,
4690                                       &src_surface,
4691                                       &src_rect,
4692                                       &dst_surface,
4693                                       &dst_rect,
4694                                       PP_NV12_LOAD_SAVE_N12,
4695                                       NULL);
4696     } else {
4697
4698         i965_post_processing_internal(ctx, &proc_context->pp_context,
4699                                       &src_surface,
4700                                       &src_rect,
4701                                       &dst_surface,
4702                                       &dst_rect,
4703                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4704                                       PP_NV12_AVS : PP_NV12_SCALING,
4705                                       NULL);
4706     }
4707
4708     if (num_tmp_surfaces)
4709         i965_DestroySurfaces(ctx,
4710                              tmp_surfaces,
4711                              num_tmp_surfaces);
4712
4713     intel_batchbuffer_flush(hw_context->batch);
4714 }
4715
4716 static void
4717 i965_proc_context_destroy(void *hw_context)
4718 {
4719     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4720
4721     i965_post_processing_context_finalize(&proc_context->pp_context);
4722     intel_batchbuffer_free(proc_context->base.batch);
4723     free(proc_context);
4724 }
4725
4726 struct hw_context *
4727 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4728 {
4729     struct intel_driver_data *intel = intel_driver_data(ctx);
4730     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4731
4732     proc_context->base.destroy = i965_proc_context_destroy;
4733     proc_context->base.run = i965_proc_picture;
4734     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4735     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4736
4737     return (struct hw_context *)proc_context;
4738 }