src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = {
 111 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5"
 112 };
 113
 114 static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = {
 115 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5"
 116 };
 117
 118 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                    const struct i965_surface *src_surface,
 120                                    const VARectangle *src_rect,
 121                                    struct i965_surface *dst_surface,
 122                                    const VARectangle *dst_rect,
 123                                    void *filter_param);
 124 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                             const struct i965_surface *src_surface,
 126                                             const VARectangle *src_rect,
 127                                             struct i965_surface *dst_surface,
 128                                             const VARectangle *dst_rect,
 129                                             void *filter_param);
 130 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 131                                            const struct i965_surface *src_surface,
 132                                            const VARectangle *src_rect,
 133                                            struct i965_surface *dst_surface,
 134                                            const VARectangle *dst_rect,
 135                                            void *filter_param);
 136 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 137                                              const struct i965_surface *src_surface,
 138                                              const VARectangle *src_rect,
 139                                              struct i965_surface *dst_surface,
 140                                              const VARectangle *dst_rect,
 141                                              void *filter_param);
 142 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 143                                                 const struct i965_surface *src_surface,
 144                                                 const VARectangle *src_rect,
 145                                                 struct i965_surface *dst_surface,
 146                                                 const VARectangle *dst_rect,
 147                                                 void *filter_param);
 148 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 149                                         const struct i965_surface *src_surface,
 150                                         const VARectangle *src_rect,
 151                                         struct i965_surface *dst_surface,
 152                                         const VARectangle *dst_rect,
 153                                         void *filter_param);
 154 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 155                                       const struct i965_surface *src_surface,
 156                                       const VARectangle *src_rect,
 157                                       struct i965_surface *dst_surface,
 158                                       const VARectangle *dst_rect,
 159                                       void *filter_param);
 160
 161 static struct pp_module pp_modules_gen5[] = {
 162     {
 163         {
 164             "NULL module (for testing)",
 165             PP_NULL,
 166             pp_null_gen5,
 167             sizeof(pp_null_gen5),
 168             NULL,
 169         },
 170
 171         pp_null_initialize,
 172     },
 173
 174     {
 175         {
 176             "NV12_NV12",
 177             PP_NV12_LOAD_SAVE_N12,
 178             pp_nv12_load_save_nv12_gen5,
 179             sizeof(pp_nv12_load_save_nv12_gen5),
 180             NULL,
 181         },
 182
 183         pp_plx_load_save_plx_initialize,
 184     },
 185
 186     {
 187         {
 188             "NV12_PL3",
 189             PP_NV12_LOAD_SAVE_PL3,
 190             pp_nv12_load_save_pl3_gen5,
 191             sizeof(pp_nv12_load_save_pl3_gen5),
 192             NULL,
 193         },
 194
 195         pp_plx_load_save_plx_initialize,
 196     },
 197
 198     {
 199         {
 200             "PL3_NV12",
 201             PP_PL3_LOAD_SAVE_N12,
 202             pp_pl3_load_save_nv12_gen5,
 203             sizeof(pp_pl3_load_save_nv12_gen5),
 204             NULL,
 205         },
 206
 207         pp_plx_load_save_plx_initialize,
 208     },
 209
 210     {
 211         {
 212             "PL3_PL3",
 213             PP_PL3_LOAD_SAVE_N12,
 214             pp_pl3_load_save_pl3_gen5,
 215             sizeof(pp_pl3_load_save_pl3_gen5),
 216             NULL,
 217         },
 218
 219         pp_plx_load_save_plx_initialize
 220     },
 221
 222     {
 223         {
 224             "NV12 Scaling module",
 225             PP_NV12_SCALING,
 226             pp_nv12_scaling_gen5,
 227             sizeof(pp_nv12_scaling_gen5),
 228             NULL,
 229         },
 230
 231         pp_nv12_scaling_initialize,
 232     },
 233
 234     {
 235         {
 236             "NV12 AVS module",
 237             PP_NV12_AVS,
 238             pp_nv12_avs_gen5,
 239             sizeof(pp_nv12_avs_gen5),
 240             NULL,
 241         },
 242
 243         pp_nv12_avs_initialize_nlas,
 244     },
 245
 246     {
 247         {
 248             "NV12 DNDI module",
 249             PP_NV12_DNDI,
 250             pp_nv12_dndi_gen5,
 251             sizeof(pp_nv12_dndi_gen5),
 252             NULL,
 253         },
 254
 255         pp_nv12_dndi_initialize,
 256     },
 257
 258     {
 259         {
 260             "NV12 DN module",
 261             PP_NV12_DN,
 262             pp_nv12_dn_gen5,
 263             sizeof(pp_nv12_dn_gen5),
 264             NULL,
 265         },
 266
 267         pp_nv12_dn_initialize,
 268     },
 269
 270     {
 271         {
 272             "NV12_PA module",
 273             PP_NV12_LOAD_SAVE_PA,
 274             pp_nv12_load_save_pa_gen5,
 275             sizeof(pp_nv12_load_save_pa_gen5),
 276             NULL,
 277         },
 278
 279         pp_plx_load_save_plx_initialize,
 280     },
 281
 282     {
 283         {
 284             "PL3_PA module",
 285             PP_PL3_LOAD_SAVE_PA,
 286             pp_pl3_load_save_pa_gen5,
 287             sizeof(pp_pl3_load_save_pa_gen5),
 288             NULL,
 289         },
 290
 291         pp_plx_load_save_plx_initialize,
 292     },
 293
 294     {
 295         {
 296             "PA_NV12 module",
 297             PP_PA_LOAD_SAVE_NV12,
 298             pp_pa_load_save_nv12_gen5,
 299             sizeof(pp_pa_load_save_nv12_gen5),
 300             NULL,
 301         },
 302
 303         pp_plx_load_save_plx_initialize,
 304     },
 305
 306     {
 307         {
 308             "PA_PL3 module",
 309             PP_PA_LOAD_SAVE_PL3,
 310             pp_pa_load_save_pl3_gen5,
 311             sizeof(pp_pa_load_save_pl3_gen5),
 312             NULL,
 313         },
 314
 315         pp_plx_load_save_plx_initialize,
 316     },
 317
 318     {
 319         {
 320             "RGBX_NV12 module",
 321             PP_RGBX_LOAD_SAVE_NV12,
 322             pp_rgbx_load_save_nv12_gen5,
 323             sizeof(pp_rgbx_load_save_nv12_gen5),
 324             NULL,
 325         },
 326
 327         pp_plx_load_save_plx_initialize,
 328     },
 329
 330     {
 331         {
 332             "NV12_RGBX module",
 333             PP_NV12_LOAD_SAVE_RGBX,
 334             pp_nv12_load_save_rgbx_gen5,
 335             sizeof(pp_nv12_load_save_rgbx_gen5),
 336             NULL,
 337         },
 338
 339         pp_plx_load_save_plx_initialize,
 340     },
 341
 342 };
 343
 344 static const uint32_t pp_null_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/null.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 350 };
 351
 352 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 354 };
 355
 356 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 362 };
 363
 364 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 365 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 366 };
 367
 368 static const uint32_t pp_nv12_avs_gen6[][4] = {
 369 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 370 };
 371
 372 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 373 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 374 };
 375
 376 static const uint32_t pp_nv12_dn_gen6[][4] = {
 377 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 378 };
 379
 380 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 381 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 382 };
 383
 384 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 385 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 386 };
 387
 388 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 389 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 390 };
 391
 392 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 393 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 394 };
 395
 396 static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = {
 397 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b"
 398 };
 399
 400 static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = {
 401 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b"
 402 };
 403
 404 static struct pp_module pp_modules_gen6[] = {
 405     {
 406         {
 407             "NULL module (for testing)",
 408             PP_NULL,
 409             pp_null_gen6,
 410             sizeof(pp_null_gen6),
 411             NULL,
 412         },
 413
 414         pp_null_initialize,
 415     },
 416
 417     {
 418         {
 419             "NV12_NV12",
 420             PP_NV12_LOAD_SAVE_N12,
 421             pp_nv12_load_save_nv12_gen6,
 422             sizeof(pp_nv12_load_save_nv12_gen6),
 423             NULL,
 424         },
 425
 426         pp_plx_load_save_plx_initialize,
 427     },
 428
 429     {
 430         {
 431             "NV12_PL3",
 432             PP_NV12_LOAD_SAVE_PL3,
 433             pp_nv12_load_save_pl3_gen6,
 434             sizeof(pp_nv12_load_save_pl3_gen6),
 435             NULL,
 436         },
 437
 438         pp_plx_load_save_plx_initialize,
 439     },
 440
 441     {
 442         {
 443             "PL3_NV12",
 444             PP_PL3_LOAD_SAVE_N12,
 445             pp_pl3_load_save_nv12_gen6,
 446             sizeof(pp_pl3_load_save_nv12_gen6),
 447             NULL,
 448         },
 449
 450         pp_plx_load_save_plx_initialize,
 451     },
 452
 453     {
 454         {
 455             "PL3_PL3",
 456             PP_PL3_LOAD_SAVE_N12,
 457             pp_pl3_load_save_pl3_gen6,
 458             sizeof(pp_pl3_load_save_pl3_gen6),
 459             NULL,
 460         },
 461
 462         pp_plx_load_save_plx_initialize,
 463     },
 464
 465     {
 466         {
 467             "NV12 Scaling module",
 468             PP_NV12_SCALING,
 469             pp_nv12_scaling_gen6,
 470             sizeof(pp_nv12_scaling_gen6),
 471             NULL,
 472         },
 473
 474         gen6_nv12_scaling_initialize,
 475     },
 476
 477     {
 478         {
 479             "NV12 AVS module",
 480             PP_NV12_AVS,
 481             pp_nv12_avs_gen6,
 482             sizeof(pp_nv12_avs_gen6),
 483             NULL,
 484         },
 485
 486         pp_nv12_avs_initialize_nlas,
 487     },
 488
 489     {
 490         {
 491             "NV12 DNDI module",
 492             PP_NV12_DNDI,
 493             pp_nv12_dndi_gen6,
 494             sizeof(pp_nv12_dndi_gen6),
 495             NULL,
 496         },
 497
 498         pp_nv12_dndi_initialize,
 499     },
 500
 501     {
 502         {
 503             "NV12 DN module",
 504             PP_NV12_DN,
 505             pp_nv12_dn_gen6,
 506             sizeof(pp_nv12_dn_gen6),
 507             NULL,
 508         },
 509
 510         pp_nv12_dn_initialize,
 511     },
 512     {
 513         {
 514             "NV12_PA module",
 515             PP_NV12_LOAD_SAVE_PA,
 516             pp_nv12_load_save_pa_gen6,
 517             sizeof(pp_nv12_load_save_pa_gen6),
 518             NULL,
 519         },
 520
 521         pp_plx_load_save_plx_initialize,
 522     },
 523
 524     {
 525         {
 526             "PL3_PA module",
 527             PP_PL3_LOAD_SAVE_PA,
 528             pp_pl3_load_save_pa_gen6,
 529             sizeof(pp_pl3_load_save_pa_gen6),
 530             NULL,
 531         },
 532
 533         pp_plx_load_save_plx_initialize,
 534     },
 535
 536     {
 537         {
 538             "PA_NV12 module",
 539             PP_PA_LOAD_SAVE_NV12,
 540             pp_pa_load_save_nv12_gen6,
 541             sizeof(pp_pa_load_save_nv12_gen6),
 542             NULL,
 543         },
 544
 545         pp_plx_load_save_plx_initialize,
 546     },
 547
 548     {
 549         {
 550             "PA_PL3 module",
 551             PP_PA_LOAD_SAVE_PL3,
 552             pp_pa_load_save_pl3_gen6,
 553             sizeof(pp_pa_load_save_pl3_gen6),
 554             NULL,
 555         },
 556
 557         pp_plx_load_save_plx_initialize,
 558     },
 559
 560     {
 561         {
 562             "RGBX_NV12 module",
 563             PP_RGBX_LOAD_SAVE_NV12,
 564             pp_rgbx_load_save_nv12_gen6,
 565             sizeof(pp_rgbx_load_save_nv12_gen6),
 566             NULL,
 567         },
 568
 569         pp_plx_load_save_plx_initialize,
 570     },
 571
 572     {
 573         {
 574             "NV12_RGBX module",
 575             PP_NV12_LOAD_SAVE_RGBX,
 576             pp_nv12_load_save_rgbx_gen6,
 577             sizeof(pp_nv12_load_save_rgbx_gen6),
 578             NULL,
 579         },
 580
 581         pp_plx_load_save_plx_initialize,
 582     },
 583 };
 584
 585 static const uint32_t pp_null_gen7[][4] = {
 586 };
 587
 588 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 589 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 590 };
 591
 592 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 593 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 594 };
 595
 596 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 597 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 598 };
 599
 600 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 601 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 602 };
 603
 604 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 605 #include "shaders/post_processing/gen7/avs.g7b"
 606 };
 607
 608 static const uint32_t pp_nv12_avs_gen7[][4] = {
 609 #include "shaders/post_processing/gen7/avs.g7b"
 610 };
 611
 612 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 613 // #include "shaders/post_processing/gen7/dndi.g7b"
 614 };
 615
 616 static const uint32_t pp_nv12_dn_gen7[][4] = {
 617 #include "shaders/post_processing/gen7/nv12_dn_nv12.g7b"
 618 };
 619 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 620 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 621 };
 622 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 623 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 624 };
 625 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 626 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 627 };
 628 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 629 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 630 };
 631 static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = {
 632 };
 633 static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = {
 634 };
 635
 636 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 637                                            const struct i965_surface *src_surface,
 638                                            const VARectangle *src_rect,
 639                                            struct i965_surface *dst_surface,
 640                                            const VARectangle *dst_rect,
 641                                            void *filter_param);
 642 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 643                                              const struct i965_surface *src_surface,
 644                                              const VARectangle *src_rect,
 645                                              struct i965_surface *dst_surface,
 646                                              const VARectangle *dst_rect,
 647                                              void *filter_param);
 648 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 649                                            const struct i965_surface *src_surface,
 650                                            const VARectangle *src_rect,
 651                                            struct i965_surface *dst_surface,
 652                                            const VARectangle *dst_rect,
 653                                            void *filter_param);
 654
 655 static struct pp_module pp_modules_gen7[] = {
 656     {
 657         {
 658             "NULL module (for testing)",
 659             PP_NULL,
 660             pp_null_gen7,
 661             sizeof(pp_null_gen7),
 662             NULL,
 663         },
 664
 665         pp_null_initialize,
 666     },
 667
 668     {
 669         {
 670             "NV12_NV12",
 671             PP_NV12_LOAD_SAVE_N12,
 672             pp_nv12_load_save_nv12_gen7,
 673             sizeof(pp_nv12_load_save_nv12_gen7),
 674             NULL,
 675         },
 676
 677         gen7_pp_plx_avs_initialize,
 678     },
 679
 680     {
 681         {
 682             "NV12_PL3",
 683             PP_NV12_LOAD_SAVE_PL3,
 684             pp_nv12_load_save_pl3_gen7,
 685             sizeof(pp_nv12_load_save_pl3_gen7),
 686             NULL,
 687         },
 688
 689         gen7_pp_plx_avs_initialize,
 690     },
 691
 692     {
 693         {
 694             "PL3_NV12",
 695             PP_PL3_LOAD_SAVE_N12,
 696             pp_pl3_load_save_nv12_gen7,
 697             sizeof(pp_pl3_load_save_nv12_gen7),
 698             NULL,
 699         },
 700
 701         gen7_pp_plx_avs_initialize,
 702     },
 703
 704     {
 705         {
 706             "PL3_PL3",
 707             PP_PL3_LOAD_SAVE_N12,
 708             pp_pl3_load_save_pl3_gen7,
 709             sizeof(pp_pl3_load_save_pl3_gen7),
 710             NULL,
 711         },
 712
 713         gen7_pp_plx_avs_initialize,
 714     },
 715
 716     {
 717         {
 718             "NV12 Scaling module",
 719             PP_NV12_SCALING,
 720             pp_nv12_scaling_gen7,
 721             sizeof(pp_nv12_scaling_gen7),
 722             NULL,
 723         },
 724
 725         gen7_pp_plx_avs_initialize,
 726     },
 727
 728     {
 729         {
 730             "NV12 AVS module",
 731             PP_NV12_AVS,
 732             pp_nv12_avs_gen7,
 733             sizeof(pp_nv12_avs_gen7),
 734             NULL,
 735         },
 736
 737         gen7_pp_plx_avs_initialize,
 738     },
 739
 740     {
 741         {
 742             "NV12 DNDI module",
 743             PP_NV12_DNDI,
 744             pp_nv12_dndi_gen7,
 745             sizeof(pp_nv12_dndi_gen7),
 746             NULL,
 747         },
 748
 749         gen7_pp_nv12_dndi_initialize,
 750     },
 751
 752     {
 753         {
 754             "NV12 DN module",
 755             PP_NV12_DN,
 756             pp_nv12_dn_gen7,
 757             sizeof(pp_nv12_dn_gen7),
 758             NULL,
 759         },
 760
 761         gen7_pp_nv12_dn_initialize,
 762     },
 763     {
 764         {
 765             "NV12_PA module",
 766             PP_NV12_LOAD_SAVE_PA,
 767             pp_nv12_load_save_pa_gen7,
 768             sizeof(pp_nv12_load_save_pa_gen7),
 769             NULL,
 770         },
 771
 772         gen7_pp_plx_avs_initialize,
 773     },
 774
 775     {
 776         {
 777             "PL3_PA module",
 778             PP_PL3_LOAD_SAVE_PA,
 779             pp_pl3_load_save_pa_gen7,
 780             sizeof(pp_pl3_load_save_pa_gen7),
 781             NULL,
 782         },
 783
 784         gen7_pp_plx_avs_initialize,
 785     },
 786
 787     {
 788         {
 789             "PA_NV12 module",
 790             PP_PA_LOAD_SAVE_NV12,
 791             pp_pa_load_save_nv12_gen7,
 792             sizeof(pp_pa_load_save_nv12_gen7),
 793             NULL,
 794         },
 795
 796         gen7_pp_plx_avs_initialize,
 797     },
 798
 799     {
 800         {
 801             "PA_PL3 module",
 802             PP_PA_LOAD_SAVE_PL3,
 803             pp_pa_load_save_pl3_gen7,
 804             sizeof(pp_pa_load_save_pl3_gen7),
 805             NULL,
 806         },
 807
 808         gen7_pp_plx_avs_initialize,
 809     },
 810
 811     {
 812         {
 813             "RGBX_NV12 module",
 814             PP_RGBX_LOAD_SAVE_NV12,
 815             pp_rgbx_load_save_nv12_gen7,
 816             sizeof(pp_rgbx_load_save_nv12_gen7),
 817             NULL,
 818         },
 819
 820         pp_plx_load_save_plx_initialize,
 821     },
 822
 823     {
 824         {
 825             "NV12_RGBX module",
 826             PP_NV12_LOAD_SAVE_RGBX,
 827             pp_nv12_load_save_rgbx_gen7,
 828             sizeof(pp_nv12_load_save_rgbx_gen7),
 829             NULL,
 830         },
 831
 832         pp_plx_load_save_plx_initialize,
 833     },
 834
 835 };
 836
 837 static int
 838 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 839 {
 840     struct i965_driver_data *i965 = i965_driver_data(ctx);
 841     int fourcc;
 842
 843     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 844         struct object_image *obj_image = IMAGE(surface->id);
 845         fourcc = obj_image->image.format.fourcc;
 846     } else {
 847         struct object_surface *obj_surface = SURFACE(surface->id);
 848         fourcc = obj_surface->fourcc;
 849     }
 850
 851     return fourcc;
 852 }
 853
 854 static void
 855 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 856 {
 857     switch (tiling) {
 858     case I915_TILING_NONE:
 859         ss->ss3.tiled_surface = 0;
 860         ss->ss3.tile_walk = 0;
 861         break;
 862     case I915_TILING_X:
 863         ss->ss3.tiled_surface = 1;
 864         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 865         break;
 866     case I915_TILING_Y:
 867         ss->ss3.tiled_surface = 1;
 868         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 869         break;
 870     }
 871 }
 872
 873 static void
 874 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 875 {
 876     switch (tiling) {
 877     case I915_TILING_NONE:
 878         ss->ss2.tiled_surface = 0;
 879         ss->ss2.tile_walk = 0;
 880         break;
 881     case I915_TILING_X:
 882         ss->ss2.tiled_surface = 1;
 883         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 884         break;
 885     case I915_TILING_Y:
 886         ss->ss2.tiled_surface = 1;
 887         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 888         break;
 889     }
 890 }
 891
 892 static void
 893 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 894 {
 895     switch (tiling) {
 896     case I915_TILING_NONE:
 897         ss->ss0.tiled_surface = 0;
 898         ss->ss0.tile_walk = 0;
 899         break;
 900     case I915_TILING_X:
 901         ss->ss0.tiled_surface = 1;
 902         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 903         break;
 904     case I915_TILING_Y:
 905         ss->ss0.tiled_surface = 1;
 906         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 907         break;
 908     }
 909 }
 910
 911 static void
 912 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 913 {
 914     switch (tiling) {
 915     case I915_TILING_NONE:
 916         ss->ss2.tiled_surface = 0;
 917         ss->ss2.tile_walk = 0;
 918         break;
 919     case I915_TILING_X:
 920         ss->ss2.tiled_surface = 1;
 921         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 922         break;
 923     case I915_TILING_Y:
 924         ss->ss2.tiled_surface = 1;
 925         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 926         break;
 927     }
 928 }
 929
 930 static void
 931 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 932 {
 933     struct i965_interface_descriptor *desc;
 934     dri_bo *bo;
 935     int pp_index = pp_context->current_pp;
 936
 937     bo = pp_context->idrt.bo;
 938     dri_bo_map(bo, 1);
 939     assert(bo->virtual);
 940     desc = bo->virtual;
 941     memset(desc, 0, sizeof(*desc));
 942     desc->desc0.grf_reg_blocks = 10;
 943     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 944     desc->desc1.const_urb_entry_read_offset = 0;
 945     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 946     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 947     desc->desc2.sampler_count = 0;
 948     desc->desc3.binding_table_entry_count = 0;
 949     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 950
 951     dri_bo_emit_reloc(bo,
 952                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 953                       desc->desc0.grf_reg_blocks,
 954                       offsetof(struct i965_interface_descriptor, desc0),
 955                       pp_context->pp_modules[pp_index].kernel.bo);
 956
 957     dri_bo_emit_reloc(bo,
 958                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 959                       desc->desc2.sampler_count << 2,
 960                       offsetof(struct i965_interface_descriptor, desc2),
 961                       pp_context->sampler_state_table.bo);
 962
 963     dri_bo_unmap(bo);
 964     pp_context->idrt.num_interface_descriptors++;
 965 }
 966
 967 static void
 968 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 969 {
 970     struct i965_vfe_state *vfe_state;
 971     dri_bo *bo;
 972
 973     bo = pp_context->vfe_state.bo;
 974     dri_bo_map(bo, 1);
 975     assert(bo->virtual);
 976     vfe_state = bo->virtual;
 977     memset(vfe_state, 0, sizeof(*vfe_state));
 978     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 979     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 980     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 981     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 982     vfe_state->vfe1.children_present = 0;
 983     vfe_state->vfe2.interface_descriptor_base =
 984         pp_context->idrt.bo->offset >> 4; /* reloc */
 985     dri_bo_emit_reloc(bo,
 986                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 987                       0,
 988                       offsetof(struct i965_vfe_state, vfe2),
 989                       pp_context->idrt.bo);
 990     dri_bo_unmap(bo);
 991 }
 992
 993 static void
 994 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 995 {
 996     unsigned char *constant_buffer;
 997     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 998
 999     assert(sizeof(*pp_static_parameter) == 128);
1000     dri_bo_map(pp_context->curbe.bo, 1);
1001     assert(pp_context->curbe.bo->virtual);
1002     constant_buffer = pp_context->curbe.bo->virtual;
1003     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
1004     dri_bo_unmap(pp_context->curbe.bo);
1005 }
1006
1007 static void
1008 ironlake_pp_states_setup(VADriverContextP ctx,
1009                          struct i965_post_processing_context *pp_context)
1010 {
1011     ironlake_pp_interface_descriptor_table(pp_context);
1012     ironlake_pp_vfe_state(pp_context);
1013     ironlake_pp_upload_constants(pp_context);
1014 }
1015
1016 static void
1017 ironlake_pp_pipeline_select(VADriverContextP ctx,
1018                             struct i965_post_processing_context *pp_context)
1019 {
1020     struct intel_batchbuffer *batch = pp_context->batch;
1021
1022     BEGIN_BATCH(batch, 1);
1023     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
1024     ADVANCE_BATCH(batch);
1025 }
1026
1027 static void
1028 ironlake_pp_urb_layout(VADriverContextP ctx,
1029                        struct i965_post_processing_context *pp_context)
1030 {
1031     struct intel_batchbuffer *batch = pp_context->batch;
1032     unsigned int vfe_fence, cs_fence;
1033
1034     vfe_fence = pp_context->urb.cs_start;
1035     cs_fence = pp_context->urb.size;
1036
1037     BEGIN_BATCH(batch, 3);
1038     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
1039     OUT_BATCH(batch, 0);
1040     OUT_BATCH(batch,
1041               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
1042               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
1043     ADVANCE_BATCH(batch);
1044 }
1045
1046 static void
1047 ironlake_pp_state_base_address(VADriverContextP ctx,
1048                                struct i965_post_processing_context *pp_context)
1049 {
1050     struct intel_batchbuffer *batch = pp_context->batch;
1051
1052     BEGIN_BATCH(batch, 8);
1053     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1054     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1055     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1056     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1057     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1058     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1059     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1060     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1061     ADVANCE_BATCH(batch);
1062 }
1063
1064 static void
1065 ironlake_pp_state_pointers(VADriverContextP ctx,
1066                            struct i965_post_processing_context *pp_context)
1067 {
1068     struct intel_batchbuffer *batch = pp_context->batch;
1069
1070     BEGIN_BATCH(batch, 3);
1071     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
1072     OUT_BATCH(batch, 0);
1073     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1074     ADVANCE_BATCH(batch);
1075 }
1076
1077 static void
1078 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
1079                           struct i965_post_processing_context *pp_context)
1080 {
1081     struct intel_batchbuffer *batch = pp_context->batch;
1082
1083     BEGIN_BATCH(batch, 2);
1084     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1085     OUT_BATCH(batch,
1086               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
1087               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
1088     ADVANCE_BATCH(batch);
1089 }
1090
1091 static void
1092 ironlake_pp_constant_buffer(VADriverContextP ctx,
1093                             struct i965_post_processing_context *pp_context)
1094 {
1095     struct intel_batchbuffer *batch = pp_context->batch;
1096
1097     BEGIN_BATCH(batch, 2);
1098     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1099     OUT_RELOC(batch, pp_context->curbe.bo,
1100               I915_GEM_DOMAIN_INSTRUCTION, 0,
1101               pp_context->urb.size_cs_entry - 1);
1102     ADVANCE_BATCH(batch);
1103 }
1104
1105 static void
1106 ironlake_pp_object_walker(VADriverContextP ctx,
1107                           struct i965_post_processing_context *pp_context)
1108 {
1109     struct intel_batchbuffer *batch = pp_context->batch;
1110     int x, x_steps, y, y_steps;
1111     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1112
1113     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1114     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1115
1116     for (y = 0; y < y_steps; y++) {
1117         for (x = 0; x < x_steps; x++) {
1118             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1119                 BEGIN_BATCH(batch, 20);
1120                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1121                 OUT_BATCH(batch, 0);
1122                 OUT_BATCH(batch, 0); /* no indirect data */
1123                 OUT_BATCH(batch, 0);
1124
1125                 /* inline data grf 5-6 */
1126                 assert(sizeof(*pp_inline_parameter) == 64);
1127                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1128
1129                 ADVANCE_BATCH(batch);
1130             }
1131         }
1132     }
1133 }
1134
1135 static void
1136 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1137                            struct i965_post_processing_context *pp_context)
1138 {
1139     struct intel_batchbuffer *batch = pp_context->batch;
1140
1141     intel_batchbuffer_start_atomic(batch, 0x1000);
1142     intel_batchbuffer_emit_mi_flush(batch);
1143     ironlake_pp_pipeline_select(ctx, pp_context);
1144     ironlake_pp_state_base_address(ctx, pp_context);
1145     ironlake_pp_state_pointers(ctx, pp_context);
1146     ironlake_pp_urb_layout(ctx, pp_context);
1147     ironlake_pp_cs_urb_layout(ctx, pp_context);
1148     ironlake_pp_constant_buffer(ctx, pp_context);
1149     ironlake_pp_object_walker(ctx, pp_context);
1150     intel_batchbuffer_end_atomic(batch);
1151 }
1152
1153 // update u/v offset when the surface format are packed yuv
1154 static void i965_update_src_surface_static_parameter(
1155     VADriverContextP    ctx,
1156     struct i965_post_processing_context *pp_context,
1157     const struct i965_surface *surface)
1158 {
1159     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1160     int fourcc = pp_get_surface_fourcc(ctx, surface);
1161
1162     switch (fourcc) {
1163     case VA_FOURCC('Y', 'U', 'Y', '2'):
1164         pp_static_parameter->grf1.source_packed_u_offset = 1;
1165         pp_static_parameter->grf1.source_packed_v_offset = 3;
1166         break;
1167     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1168         pp_static_parameter->grf1.source_packed_y_offset = 1;
1169         pp_static_parameter->grf1.source_packed_v_offset = 2;
1170         break;
1171     case VA_FOURCC('B', 'G', 'R', 'X'):
1172     case VA_FOURCC('B', 'G', 'R', 'A'):
1173         pp_static_parameter->grf1.source_rgb_layout = 0;
1174         break;
1175     case VA_FOURCC('R', 'G', 'B', 'X'):
1176     case VA_FOURCC('R', 'G', 'B', 'A'):
1177         pp_static_parameter->grf1.source_rgb_layout = 1;
1178         break;
1179     default:
1180         break;
1181     }
1182
1183 }
1184
1185 static void i965_update_dst_surface_static_parameter(
1186     VADriverContextP    ctx,
1187     struct i965_post_processing_context *pp_context,
1188     const struct i965_surface *surface)
1189 {
1190     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1191     int fourcc = pp_get_surface_fourcc(ctx, surface);
1192
1193     switch (fourcc) {
1194     case VA_FOURCC('Y', 'U', 'Y', '2'):
1195         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1196         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1197         break;
1198     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1199         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1200         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1201         break;
1202     case VA_FOURCC('B', 'G', 'R', 'X'):
1203     case VA_FOURCC('B', 'G', 'R', 'A'):
1204         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0;
1205         break;
1206     case VA_FOURCC('R', 'G', 'B', 'X'):
1207     case VA_FOURCC('R', 'G', 'B', 'A'):
1208         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1;
1209         break;
1210     default:
1211         break;
1212     }
1213
1214 }
1215
1216 static void
1217 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1218                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1219                           int width, int height, int pitch, int format,
1220                           int index, int is_target)
1221 {
1222     struct i965_surface_state *ss;
1223     dri_bo *ss_bo;
1224     unsigned int tiling;
1225     unsigned int swizzle;
1226
1227     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1228     ss_bo = pp_context->surface_state_binding_table.bo;
1229     assert(ss_bo);
1230
1231     dri_bo_map(ss_bo, True);
1232     assert(ss_bo->virtual);
1233     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1234     memset(ss, 0, sizeof(*ss));
1235     ss->ss0.surface_type = I965_SURFACE_2D;
1236     ss->ss0.surface_format = format;
1237     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1238     ss->ss2.width = width - 1;
1239     ss->ss2.height = height - 1;
1240     ss->ss3.pitch = pitch - 1;
1241     pp_set_surface_tiling(ss, tiling);
1242     dri_bo_emit_reloc(ss_bo,
1243                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1244                       surf_bo_offset,
1245                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1246                       surf_bo);
1247     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1248     dri_bo_unmap(ss_bo);
1249 }
1250
1251 static void
1252 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1253                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1254                            int width, int height, int wpitch,
1255                            int xoffset, int yoffset,
1256                            int format, int interleave_chroma,
1257                            int index)
1258 {
1259     struct i965_surface_state2 *ss2;
1260     dri_bo *ss2_bo;
1261     unsigned int tiling;
1262     unsigned int swizzle;
1263
1264     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1265     ss2_bo = pp_context->surface_state_binding_table.bo;
1266     assert(ss2_bo);
1267
1268     dri_bo_map(ss2_bo, True);
1269     assert(ss2_bo->virtual);
1270     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1271     memset(ss2, 0, sizeof(*ss2));
1272     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1273     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1274     ss2->ss1.width = width - 1;
1275     ss2->ss1.height = height - 1;
1276     ss2->ss2.pitch = wpitch - 1;
1277     ss2->ss2.interleave_chroma = interleave_chroma;
1278     ss2->ss2.surface_format = format;
1279     ss2->ss3.x_offset_for_cb = xoffset;
1280     ss2->ss3.y_offset_for_cb = yoffset;
1281     pp_set_surface2_tiling(ss2, tiling);
1282     dri_bo_emit_reloc(ss2_bo,
1283                       I915_GEM_DOMAIN_RENDER, 0,
1284                       surf_bo_offset,
1285                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1286                       surf_bo);
1287     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1288     dri_bo_unmap(ss2_bo);
1289 }
1290
1291 static void
1292 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1293                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1294                           int width, int height, int pitch, int format,
1295                           int index, int is_target)
1296 {
1297     struct gen7_surface_state *ss;
1298     dri_bo *ss_bo;
1299     unsigned int tiling;
1300     unsigned int swizzle;
1301
1302     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1303     ss_bo = pp_context->surface_state_binding_table.bo;
1304     assert(ss_bo);
1305
1306     dri_bo_map(ss_bo, True);
1307     assert(ss_bo->virtual);
1308     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1309     memset(ss, 0, sizeof(*ss));
1310     ss->ss0.surface_type = I965_SURFACE_2D;
1311     ss->ss0.surface_format = format;
1312     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1313     ss->ss2.width = width - 1;
1314     ss->ss2.height = height - 1;
1315     ss->ss3.pitch = pitch - 1;
1316     gen7_pp_set_surface_tiling(ss, tiling);
1317     dri_bo_emit_reloc(ss_bo,
1318                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1319                       surf_bo_offset,
1320                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1321                       surf_bo);
1322     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1323     dri_bo_unmap(ss_bo);
1324 }
1325
1326 static void
1327 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1328                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1329                            int width, int height, int wpitch,
1330                            int xoffset, int yoffset,
1331                            int format, int interleave_chroma,
1332                            int index)
1333 {
1334     struct gen7_surface_state2 *ss2;
1335     dri_bo *ss2_bo;
1336     unsigned int tiling;
1337     unsigned int swizzle;
1338
1339     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1340     ss2_bo = pp_context->surface_state_binding_table.bo;
1341     assert(ss2_bo);
1342
1343     dri_bo_map(ss2_bo, True);
1344     assert(ss2_bo->virtual);
1345     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1346     memset(ss2, 0, sizeof(*ss2));
1347     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1348     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1349     ss2->ss1.width = width - 1;
1350     ss2->ss1.height = height - 1;
1351     ss2->ss2.pitch = wpitch - 1;
1352     ss2->ss2.interleave_chroma = interleave_chroma;
1353     ss2->ss2.surface_format = format;
1354     ss2->ss3.x_offset_for_cb = xoffset;
1355     ss2->ss3.y_offset_for_cb = yoffset;
1356     gen7_pp_set_surface2_tiling(ss2, tiling);
1357     dri_bo_emit_reloc(ss2_bo,
1358                       I915_GEM_DOMAIN_RENDER, 0,
1359                       surf_bo_offset,
1360                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1361                       surf_bo);
1362     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1363     dri_bo_unmap(ss2_bo);
1364 }
1365
1366 static void
1367 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1368                                 const struct i965_surface *surface,
1369                                 int base_index, int is_target,
1370                                 int *width, int *height, int *pitch, int *offset)
1371 {
1372     struct i965_driver_data *i965 = i965_driver_data(ctx);
1373     struct object_surface *obj_surface;
1374     struct object_image *obj_image;
1375     dri_bo *bo;
1376     int fourcc = pp_get_surface_fourcc(ctx, surface);
1377     const int Y = 0;
1378     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1379     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1380     const int UV = 1;
1381     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1382     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1383     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1384                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1385                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1386                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1387     int scale_factor_of_1st_plane_width_in_byte = 1;
1388
1389     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1390         obj_surface = SURFACE(surface->id);
1391         bo = obj_surface->bo;
1392         width[0] = obj_surface->orig_width;
1393         height[0] = obj_surface->orig_height;
1394         pitch[0] = obj_surface->width;
1395         offset[0] = 0;
1396
1397         if (full_packed_format) {
1398             scale_factor_of_1st_plane_width_in_byte = 4;
1399             pitch[0] = obj_surface->width * 4;
1400         }
1401         else if (packed_yuv ) {
1402             scale_factor_of_1st_plane_width_in_byte =  2;
1403             pitch[0] = obj_surface->width * 2;
1404         }
1405         else if (interleaved_uv) {
1406             width[1] = obj_surface->orig_width;
1407             height[1] = obj_surface->orig_height / 2;
1408             pitch[1] = obj_surface->width;
1409             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1410         } else {
1411             width[1] = obj_surface->orig_width / 2;
1412             height[1] = obj_surface->orig_height / 2;
1413             pitch[1] = obj_surface->width / 2;
1414             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1415             width[2] = obj_surface->orig_width / 2;
1416             height[2] = obj_surface->orig_height / 2;
1417             pitch[2] = obj_surface->width / 2;
1418             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1419         }
1420     } else {
1421         obj_image = IMAGE(surface->id);
1422         bo = obj_image->bo;
1423         width[0] = obj_image->image.width;
1424         height[0] = obj_image->image.height;
1425         pitch[0] = obj_image->image.pitches[0];
1426         offset[0] = obj_image->image.offsets[0];
1427
1428         if (full_packed_format) {
1429             scale_factor_of_1st_plane_width_in_byte = 4;
1430         }
1431         else if (packed_yuv ) {
1432             scale_factor_of_1st_plane_width_in_byte = 2;
1433         }
1434         else if (interleaved_uv) {
1435             width[1] = obj_image->image.width;
1436             height[1] = obj_image->image.height / 2;
1437             pitch[1] = obj_image->image.pitches[1];
1438             offset[1] = obj_image->image.offsets[1];
1439         } else {
1440             width[1] = obj_image->image.width / 2;
1441             height[1] = obj_image->image.height / 2;
1442             pitch[1] = obj_image->image.pitches[1];
1443             offset[1] = obj_image->image.offsets[1];
1444             width[2] = obj_image->image.width / 2;
1445             height[2] = obj_image->image.height / 2;
1446             pitch[2] = obj_image->image.pitches[2];
1447             offset[2] = obj_image->image.offsets[2];
1448         }
1449     }
1450
1451     /* Y surface */
1452     i965_pp_set_surface_state(ctx, pp_context,
1453                               bo, offset[Y],
1454                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1455                               base_index, is_target);
1456
1457     if (!packed_yuv && !full_packed_format) {
1458         if (interleaved_uv) {
1459             i965_pp_set_surface_state(ctx, pp_context,
1460                                       bo, offset[UV],
1461                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1462                                       base_index + 1, is_target);
1463         } else {
1464             /* U surface */
1465             i965_pp_set_surface_state(ctx, pp_context,
1466                                       bo, offset[U],
1467                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1468                                       base_index + 1, is_target);
1469
1470             /* V surface */
1471             i965_pp_set_surface_state(ctx, pp_context,
1472                                       bo, offset[V],
1473                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1474                                       base_index + 2, is_target);
1475         }
1476     }
1477
1478 }
1479
1480 static void
1481 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1482                                      const struct i965_surface *surface,
1483                                      int base_index, int is_target,
1484                                      int *width, int *height, int *pitch, int *offset)
1485 {
1486     struct i965_driver_data *i965 = i965_driver_data(ctx);
1487     struct object_surface *obj_surface;
1488     struct object_image *obj_image;
1489     dri_bo *bo;
1490     int fourcc = pp_get_surface_fourcc(ctx, surface);
1491     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1492                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1493     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1494                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1495     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1496     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1497
1498     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1499         obj_surface = SURFACE(surface->id);
1500         bo = obj_surface->bo;
1501         width[0] = obj_surface->orig_width;
1502         height[0] = obj_surface->orig_height;
1503         pitch[0] = obj_surface->width;
1504         offset[0] = 0;
1505
1506         if (packed_yuv) {
1507             if (is_target)
1508                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1509             else
1510                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1511
1512             pitch[0] = obj_surface->width * 2;
1513         }
1514
1515         width[1] = obj_surface->cb_cr_width;
1516         height[1] = obj_surface->cb_cr_height;
1517         pitch[1] = obj_surface->cb_cr_pitch;
1518         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1519
1520         width[2] = obj_surface->cb_cr_width;
1521         height[2] = obj_surface->cb_cr_height;
1522         pitch[2] = obj_surface->cb_cr_pitch;
1523         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1524     } else {
1525         obj_image = IMAGE(surface->id);
1526         bo = obj_image->bo;
1527         width[0] = obj_image->image.width;
1528         height[0] = obj_image->image.height;
1529         pitch[0] = obj_image->image.pitches[0];
1530         offset[0] = obj_image->image.offsets[0];
1531
1532         if (packed_yuv) {
1533             if (is_target)
1534                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1535             else
1536                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1537         } else if (interleaved_uv) {
1538             width[1] = obj_image->image.width / 2;
1539             height[1] = obj_image->image.height / 2;
1540             pitch[1] = obj_image->image.pitches[1];
1541             offset[1] = obj_image->image.offsets[1];
1542         } else {
1543             width[1] = obj_image->image.width / 2;
1544             height[1] = obj_image->image.height / 2;
1545             pitch[1] = obj_image->image.pitches[U];
1546             offset[1] = obj_image->image.offsets[U];
1547             width[2] = obj_image->image.width / 2;
1548             height[2] = obj_image->image.height / 2;
1549             pitch[2] = obj_image->image.pitches[V];
1550             offset[2] = obj_image->image.offsets[V];
1551         }
1552     }
1553
1554     if (is_target) {
1555         gen7_pp_set_surface_state(ctx, pp_context,
1556                                   bo, 0,
1557                                   width[0] / 4, height[0], pitch[0],
1558                                   I965_SURFACEFORMAT_R8_SINT,
1559                                   base_index, 1);
1560
1561         if (!packed_yuv) {
1562             if (interleaved_uv) {
1563                 gen7_pp_set_surface_state(ctx, pp_context,
1564                                           bo, offset[1],
1565                                           width[1] / 2, height[1], pitch[1],
1566                                           I965_SURFACEFORMAT_R8G8_SINT,
1567                                           base_index + 1, 1);
1568             } else {
1569                 gen7_pp_set_surface_state(ctx, pp_context,
1570                                           bo, offset[1],
1571                                           width[1] / 4, height[1], pitch[1],
1572                                           I965_SURFACEFORMAT_R8_SINT,
1573                                           base_index + 1, 1);
1574                 gen7_pp_set_surface_state(ctx, pp_context,
1575                                           bo, offset[2],
1576                                           width[2] / 4, height[2], pitch[2],
1577                                           I965_SURFACEFORMAT_R8_SINT,
1578                                           base_index + 2, 1);
1579             }
1580         }
1581     } else {
1582         int format0 = SURFACE_FORMAT_Y8_UNORM;
1583
1584         switch (fourcc) {
1585         case VA_FOURCC('Y', 'U', 'Y', '2'):
1586             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1587             break;
1588
1589         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1590             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1591             break;
1592
1593         default:
1594             break;
1595         }
1596
1597         gen7_pp_set_surface2_state(ctx, pp_context,
1598                                    bo, offset[0],
1599                                    width[0], height[0], pitch[0],
1600                                    0, 0,
1601                                    format0, 0,
1602                                    base_index);
1603
1604         if (!packed_yuv) {
1605             if (interleaved_uv) {
1606                 gen7_pp_set_surface2_state(ctx, pp_context,
1607                                            bo, offset[1],
1608                                            width[1], height[1], pitch[1],
1609                                            0, 0,
1610                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1611                                            base_index + 1);
1612             } else {
1613                 gen7_pp_set_surface2_state(ctx, pp_context,
1614                                            bo, offset[1],
1615                                            width[1], height[1], pitch[1],
1616                                            0, 0,
1617                                            SURFACE_FORMAT_R8_UNORM, 0,
1618                                            base_index + 1);
1619                 gen7_pp_set_surface2_state(ctx, pp_context,
1620                                            bo, offset[2],
1621                                            width[2], height[2], pitch[2],
1622                                            0, 0,
1623                                            SURFACE_FORMAT_R8_UNORM, 0,
1624                                            base_index + 2);
1625             }
1626         }
1627     }
1628 }
1629
1630 static int
1631 pp_null_x_steps(void *private_context)
1632 {
1633     return 1;
1634 }
1635
1636 static int
1637 pp_null_y_steps(void *private_context)
1638 {
1639     return 1;
1640 }
1641
1642 static int
1643 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1644 {
1645     return 0;
1646 }
1647
1648 static VAStatus
1649 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1650                    const struct i965_surface *src_surface,
1651                    const VARectangle *src_rect,
1652                    struct i965_surface *dst_surface,
1653                    const VARectangle *dst_rect,
1654                    void *filter_param)
1655 {
1656     /* private function & data */
1657     pp_context->pp_x_steps = pp_null_x_steps;
1658     pp_context->pp_y_steps = pp_null_y_steps;
1659     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1660
1661     dst_surface->flags = src_surface->flags;
1662
1663     return VA_STATUS_SUCCESS;
1664 }
1665
1666 static int
1667 pp_load_save_x_steps(void *private_context)
1668 {
1669     return 1;
1670 }
1671
1672 static int
1673 pp_load_save_y_steps(void *private_context)
1674 {
1675     struct pp_load_save_context *pp_load_save_context = private_context;
1676
1677     return pp_load_save_context->dest_h / 8;
1678 }
1679
1680 static int
1681 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1682 {
1683     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1684
1685     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1686     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1687     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1688     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1689
1690     return 0;
1691 }
1692
1693 static VAStatus
1694 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1695                                 const struct i965_surface *src_surface,
1696                                 const VARectangle *src_rect,
1697                                 struct i965_surface *dst_surface,
1698                                 const VARectangle *dst_rect,
1699                                 void *filter_param)
1700 {
1701     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1702     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1703     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1704     int width[3], height[3], pitch[3], offset[3];
1705     const int Y = 0;
1706
1707     /* source surface */
1708     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1709                                     width, height, pitch, offset);
1710
1711     /* destination surface */
1712     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1713                                     width, height, pitch, offset);
1714
1715     /* private function & data */
1716     pp_context->pp_x_steps = pp_load_save_x_steps;
1717     pp_context->pp_y_steps = pp_load_save_y_steps;
1718     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1719     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1720     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1721
1722     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1723     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1724
1725     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1726     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1727
1728     // update u/v offset for packed yuv
1729     i965_update_src_surface_static_parameter (ctx, pp_context, src_surface);
1730     i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface);
1731
1732     dst_surface->flags = src_surface->flags;
1733
1734     return VA_STATUS_SUCCESS;
1735 }
1736
1737 static int
1738 pp_scaling_x_steps(void *private_context)
1739 {
1740     return 1;
1741 }
1742
1743 static int
1744 pp_scaling_y_steps(void *private_context)
1745 {
1746     struct pp_scaling_context *pp_scaling_context = private_context;
1747
1748     return pp_scaling_context->dest_h / 8;
1749 }
1750
1751 static int
1752 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1753 {
1754     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1755     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1756     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1757     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1758     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1759
1760     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1761     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1762     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1763     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1764
1765     return 0;
1766 }
1767
1768 static VAStatus
1769 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1770                            const struct i965_surface *src_surface,
1771                            const VARectangle *src_rect,
1772                            struct i965_surface *dst_surface,
1773                            const VARectangle *dst_rect,
1774                            void *filter_param)
1775 {
1776     struct i965_driver_data *i965 = i965_driver_data(ctx);
1777     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1778     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1779     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1780     struct object_surface *obj_surface;
1781     struct i965_sampler_state *sampler_state;
1782     int in_w, in_h, in_wpitch, in_hpitch;
1783     int out_w, out_h, out_wpitch, out_hpitch;
1784
1785     /* source surface */
1786     obj_surface = SURFACE(src_surface->id);
1787     in_w = obj_surface->orig_width;
1788     in_h = obj_surface->orig_height;
1789     in_wpitch = obj_surface->width;
1790     in_hpitch = obj_surface->height;
1791
1792     /* source Y surface index 1 */
1793     i965_pp_set_surface_state(ctx, pp_context,
1794                               obj_surface->bo, 0,
1795                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1796                               1, 0);
1797
1798     /* source UV surface index 2 */
1799     i965_pp_set_surface_state(ctx, pp_context,
1800                               obj_surface->bo, in_wpitch * in_hpitch,
1801                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1802                               2, 0);
1803
1804     /* destination surface */
1805     obj_surface = SURFACE(dst_surface->id);
1806     out_w = obj_surface->orig_width;
1807     out_h = obj_surface->orig_height;
1808     out_wpitch = obj_surface->width;
1809     out_hpitch = obj_surface->height;
1810
1811     /* destination Y surface index 7 */
1812     i965_pp_set_surface_state(ctx, pp_context,
1813                               obj_surface->bo, 0,
1814                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1815                               7, 1);
1816
1817     /* destination UV surface index 8 */
1818     i965_pp_set_surface_state(ctx, pp_context,
1819                               obj_surface->bo, out_wpitch * out_hpitch,
1820                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1821                               8, 1);
1822
1823     /* sampler state */
1824     dri_bo_map(pp_context->sampler_state_table.bo, True);
1825     assert(pp_context->sampler_state_table.bo->virtual);
1826     sampler_state = pp_context->sampler_state_table.bo->virtual;
1827
1828     /* SIMD16 Y index 1 */
1829     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1830     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1831     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1832     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1833     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1834
1835     /* SIMD16 UV index 2 */
1836     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1837     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1838     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1839     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1840     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1841
1842     dri_bo_unmap(pp_context->sampler_state_table.bo);
1843
1844     /* private function & data */
1845     pp_context->pp_x_steps = pp_scaling_x_steps;
1846     pp_context->pp_y_steps = pp_scaling_y_steps;
1847     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1848
1849     pp_scaling_context->dest_x = dst_rect->x;
1850     pp_scaling_context->dest_y = dst_rect->y;
1851     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1852     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1853     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1854     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1855
1856     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1857
1858     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1859     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1860     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1861     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1862     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1863
1864     dst_surface->flags = src_surface->flags;
1865
1866     return VA_STATUS_SUCCESS;
1867 }
1868
1869 static int
1870 pp_avs_x_steps(void *private_context)
1871 {
1872     struct pp_avs_context *pp_avs_context = private_context;
1873
1874     return pp_avs_context->dest_w / 16;
1875 }
1876
1877 static int
1878 pp_avs_y_steps(void *private_context)
1879 {
1880     return 1;
1881 }
1882
1883 static int
1884 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1885 {
1886     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1887     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1888     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1889     float src_x_steping, src_y_steping, video_step_delta;
1890     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1891
1892     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1893         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1894         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1895     } else if (tmp_w >= pp_avs_context->dest_w) {
1896         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1897         pp_inline_parameter->grf6.video_step_delta = 0;
1898
1899         if (x == 0) {
1900             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1901                 pp_avs_context->src_normalized_x;
1902         } else {
1903             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1904             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1905             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1906                 16 * 15 * video_step_delta / 2;
1907         }
1908     } else {
1909         int n0, n1, n2, nls_left, nls_right;
1910         int factor_a = 5, factor_b = 4;
1911         float f;
1912
1913         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1914         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1915         n2 = tmp_w / (16 * factor_a);
1916         nls_left = n0 + n2;
1917         nls_right = n1 + n2;
1918         f = (float) n2 * 16 / tmp_w;
1919
1920         if (n0 < 5) {
1921             pp_inline_parameter->grf6.video_step_delta = 0.0;
1922
1923             if (x == 0) {
1924                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1925                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1926             } else {
1927                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1928                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1929                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1930                     16 * 15 * video_step_delta / 2;
1931             }
1932         } else {
1933             if (x < nls_left) {
1934                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1935                 float a = f / (nls_left * 16 * factor_b);
1936                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1937
1938                 pp_inline_parameter->grf6.video_step_delta = b;
1939
1940                 if (x == 0) {
1941                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1942                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1943                 } else {
1944                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1945                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1946                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1947                         16 * 15 * video_step_delta / 2;
1948                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1949                 }
1950             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1951                 /* scale the center linearly */
1952                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1953                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1954                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1955                     16 * 15 * video_step_delta / 2;
1956                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1957                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1958             } else {
1959                 float a = f / (nls_right * 16 * factor_b);
1960                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1961
1962                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1963                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1964                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1965                     16 * 15 * video_step_delta / 2;
1966                 pp_inline_parameter->grf6.video_step_delta = -b;
1967
1968                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1969                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1970                 else
1971                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1972             }
1973         }
1974     }
1975
1976     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1977     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1978     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1979     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1980
1981     return 0;
1982 }
1983
1984 static VAStatus
1985 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1986                        const struct i965_surface *src_surface,
1987                        const VARectangle *src_rect,
1988                        struct i965_surface *dst_surface,
1989                        const VARectangle *dst_rect,
1990                        void *filter_param,
1991                        int nlas)
1992 {
1993     struct i965_driver_data *i965 = i965_driver_data(ctx);
1994     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1995     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1996     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1997     struct object_surface *obj_surface;
1998     struct i965_sampler_8x8 *sampler_8x8;
1999     struct i965_sampler_8x8_state *sampler_8x8_state;
2000     int index;
2001     int in_w, in_h, in_wpitch, in_hpitch;
2002     int out_w, out_h, out_wpitch, out_hpitch;
2003     int i;
2004
2005     /* surface */
2006     obj_surface = SURFACE(src_surface->id);
2007     in_w = obj_surface->orig_width;
2008     in_h = obj_surface->orig_height;
2009     in_wpitch = obj_surface->width;
2010     in_hpitch = obj_surface->height;
2011
2012     /* source Y surface index 1 */
2013     i965_pp_set_surface2_state(ctx, pp_context,
2014                                obj_surface->bo, 0,
2015                                in_w, in_h, in_wpitch,
2016                                0, 0,
2017                                SURFACE_FORMAT_Y8_UNORM, 0,
2018                                1);
2019
2020     /* source UV surface index 2 */
2021     i965_pp_set_surface2_state(ctx, pp_context,
2022                                obj_surface->bo, in_wpitch * in_hpitch,
2023                                in_w / 2, in_h / 2, in_wpitch,
2024                                0, 0,
2025                                SURFACE_FORMAT_R8B8_UNORM, 0,
2026                                2);
2027
2028     /* destination surface */
2029     obj_surface = SURFACE(dst_surface->id);
2030     out_w = obj_surface->orig_width;
2031     out_h = obj_surface->orig_height;
2032     out_wpitch = obj_surface->width;
2033     out_hpitch = obj_surface->height;
2034     assert(out_w <= out_wpitch && out_h <= out_hpitch);
2035
2036     /* destination Y surface index 7 */
2037     i965_pp_set_surface_state(ctx, pp_context,
2038                               obj_surface->bo, 0,
2039                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2040                               7, 1);
2041
2042     /* destination UV surface index 8 */
2043     i965_pp_set_surface_state(ctx, pp_context,
2044                               obj_surface->bo, out_wpitch * out_hpitch,
2045                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2046                               8, 1);
2047
2048     /* sampler 8x8 state */
2049     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2050     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2051     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2052     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2053     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2054
2055     for (i = 0; i < 17; i++) {
2056         /* for Y channel, currently ignore */
2057         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
2058         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
2059         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
2060         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
2061         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
2062         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
2063         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
2064         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
2065         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
2066         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
2067         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
2068         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
2069         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
2070         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
2071         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
2072         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
2073         /* for U/V channel, 0.25 */
2074         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2075         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2076         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2077         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2078         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2079         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2080         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2081         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2082         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2083         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2084         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2085         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2086         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2087         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2088         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2089         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2090     }
2091
2092     sampler_8x8_state->dw136.default_sharpness_level = 0;
2093     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2094     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2095     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2096     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2097
2098     /* sampler 8x8 */
2099     dri_bo_map(pp_context->sampler_state_table.bo, True);
2100     assert(pp_context->sampler_state_table.bo->virtual);
2101     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
2102     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2103
2104     /* sample_8x8 Y index 1 */
2105     index = 1;
2106     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2107     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2108     sampler_8x8[index].dw0.ief_bypass = 1;
2109     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2110     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2111     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2112     sampler_8x8[index].dw2.global_noise_estimation = 22;
2113     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2114     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2115     sampler_8x8[index].dw3.strong_edge_weight = 7;
2116     sampler_8x8[index].dw3.regular_weight = 2;
2117     sampler_8x8[index].dw3.non_edge_weight = 0;
2118     sampler_8x8[index].dw3.gain_factor = 40;
2119     sampler_8x8[index].dw4.steepness_boost = 0;
2120     sampler_8x8[index].dw4.steepness_threshold = 0;
2121     sampler_8x8[index].dw4.mr_boost = 0;
2122     sampler_8x8[index].dw4.mr_threshold = 5;
2123     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2124     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2125     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2126     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2127     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2128     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2129     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2130     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2131     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2132     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2133     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2134     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2135     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2136     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2137     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2138     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2139     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2140     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2141     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2142     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2143     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2144     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2145     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2146     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2147     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2148     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2149     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2150     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2151     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2152     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2153     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2154     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2155     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2156     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2157     sampler_8x8[index].dw13.limiter_boost = 0;
2158     sampler_8x8[index].dw13.minimum_limiter = 10;
2159     sampler_8x8[index].dw13.maximum_limiter = 11;
2160     sampler_8x8[index].dw14.clip_limiter = 130;
2161     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2162                       I915_GEM_DOMAIN_RENDER,
2163                       0,
2164                       0,
2165                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2166                       pp_context->sampler_state_table.bo_8x8);
2167
2168     /* sample_8x8 UV index 2 */
2169     index = 2;
2170     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2171     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2172     sampler_8x8[index].dw0.ief_bypass = 1;
2173     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2174     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2175     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2176     sampler_8x8[index].dw2.global_noise_estimation = 22;
2177     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2178     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2179     sampler_8x8[index].dw3.strong_edge_weight = 7;
2180     sampler_8x8[index].dw3.regular_weight = 2;
2181     sampler_8x8[index].dw3.non_edge_weight = 0;
2182     sampler_8x8[index].dw3.gain_factor = 40;
2183     sampler_8x8[index].dw4.steepness_boost = 0;
2184     sampler_8x8[index].dw4.steepness_threshold = 0;
2185     sampler_8x8[index].dw4.mr_boost = 0;
2186     sampler_8x8[index].dw4.mr_threshold = 5;
2187     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2188     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2189     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2190     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2191     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2192     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2193     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2194     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2195     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2196     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2197     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2198     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2199     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2200     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2201     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2202     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2203     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2204     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2205     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2206     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2207     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2208     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2209     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2210     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2211     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2212     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2213     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2214     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2215     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2216     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2217     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2218     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2219     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2220     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2221     sampler_8x8[index].dw13.limiter_boost = 0;
2222     sampler_8x8[index].dw13.minimum_limiter = 10;
2223     sampler_8x8[index].dw13.maximum_limiter = 11;
2224     sampler_8x8[index].dw14.clip_limiter = 130;
2225     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2226                       I915_GEM_DOMAIN_RENDER,
2227                       0,
2228                       0,
2229                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2230                       pp_context->sampler_state_table.bo_8x8);
2231
2232     dri_bo_unmap(pp_context->sampler_state_table.bo);
2233
2234     /* private function & data */
2235     pp_context->pp_x_steps = pp_avs_x_steps;
2236     pp_context->pp_y_steps = pp_avs_y_steps;
2237     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2238
2239     pp_avs_context->dest_x = dst_rect->x;
2240     pp_avs_context->dest_y = dst_rect->y;
2241     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2242     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2243     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2244     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2245     pp_avs_context->src_w = src_rect->width;
2246     pp_avs_context->src_h = src_rect->height;
2247
2248     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2249     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2250
2251     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2252     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2253     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2254     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2255     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2256     pp_inline_parameter->grf6.video_step_delta = 0.0;
2257
2258     dst_surface->flags = src_surface->flags;
2259
2260     return VA_STATUS_SUCCESS;
2261 }
2262
2263 static VAStatus
2264 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2265                             const struct i965_surface *src_surface,
2266                             const VARectangle *src_rect,
2267                             struct i965_surface *dst_surface,
2268                             const VARectangle *dst_rect,
2269                             void *filter_param)
2270 {
2271     return pp_nv12_avs_initialize(ctx, pp_context,
2272                                   src_surface,
2273                                   src_rect,
2274                                   dst_surface,
2275                                   dst_rect,
2276                                   filter_param,
2277                                   1);
2278 }
2279
2280 static VAStatus
2281 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2282                              const struct i965_surface *src_surface,
2283                              const VARectangle *src_rect,
2284                              struct i965_surface *dst_surface,
2285                              const VARectangle *dst_rect,
2286                              void *filter_param)
2287 {
2288     return pp_nv12_avs_initialize(ctx, pp_context,
2289                                   src_surface,
2290                                   src_rect,
2291                                   dst_surface,
2292                                   dst_rect,
2293                                   filter_param,
2294                                   0);
2295 }
2296
2297 static int
2298 gen7_pp_avs_x_steps(void *private_context)
2299 {
2300     struct pp_avs_context *pp_avs_context = private_context;
2301
2302     return pp_avs_context->dest_w / 16;
2303 }
2304
2305 static int
2306 gen7_pp_avs_y_steps(void *private_context)
2307 {
2308     struct pp_avs_context *pp_avs_context = private_context;
2309
2310     return pp_avs_context->dest_h / 16;
2311 }
2312
2313 static int
2314 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2315 {
2316     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2317     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2318
2319     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2320     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2321     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2322     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2323
2324     return 0;
2325 }
2326
2327 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2328                                               struct i965_post_processing_context *pp_context,
2329                                               const struct i965_surface *surface)
2330 {
2331     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2332     int fourcc = pp_get_surface_fourcc(ctx, surface);
2333
2334     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2335         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2336         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2337         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2338     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2339         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2340         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2341         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2342     }
2343 }
2344
2345 static VAStatus
2346 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2347                            const struct i965_surface *src_surface,
2348                            const VARectangle *src_rect,
2349                            struct i965_surface *dst_surface,
2350                            const VARectangle *dst_rect,
2351                            void *filter_param)
2352 {
2353     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2354     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2355     struct gen7_sampler_8x8 *sampler_8x8;
2356     struct i965_sampler_8x8_state *sampler_8x8_state;
2357     int index, i;
2358     int width[3], height[3], pitch[3], offset[3];
2359
2360     /* source surface */
2361     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2362                                          width, height, pitch, offset);
2363
2364     /* destination surface */
2365     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2366                                          width, height, pitch, offset);
2367
2368     /* sampler 8x8 state */
2369     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2370     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2371     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2372     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2373     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2374
2375     for (i = 0; i < 17; i++) {
2376         /* for Y channel, currently ignore */
2377         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2378         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2379         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2380         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2381         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2382         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2383         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2384         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2385         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2386         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2387         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2388         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2389         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2390         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2391         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2392         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2393         /* for U/V channel, 0.25 */
2394         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2395         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2396         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2397         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2398         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2399         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2400         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2401         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2402         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2403         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2404         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2405         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2406         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2407         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2408         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2409         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2410     }
2411
2412     sampler_8x8_state->dw136.default_sharpness_level = 0;
2413     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2414     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2415     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2416     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2417
2418     /* sampler 8x8 */
2419     dri_bo_map(pp_context->sampler_state_table.bo, True);
2420     assert(pp_context->sampler_state_table.bo->virtual);
2421     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2422     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2423
2424     /* sample_8x8 Y index 4 */
2425     index = 4;
2426     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2427     sampler_8x8[index].dw0.global_noise_estimation = 255;
2428     sampler_8x8[index].dw0.ief_bypass = 1;
2429
2430     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2431
2432     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2433     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2434     sampler_8x8[index].dw2.r5x_coefficient = 9;
2435     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2436     sampler_8x8[index].dw2.r5c_coefficient = 3;
2437
2438     sampler_8x8[index].dw3.r3x_coefficient = 27;
2439     sampler_8x8[index].dw3.r3c_coefficient = 5;
2440     sampler_8x8[index].dw3.gain_factor = 40;
2441     sampler_8x8[index].dw3.non_edge_weight = 1;
2442     sampler_8x8[index].dw3.regular_weight = 2;
2443     sampler_8x8[index].dw3.strong_edge_weight = 7;
2444     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2445
2446     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2447                       I915_GEM_DOMAIN_RENDER,
2448                       0,
2449                       0,
2450                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2451                       pp_context->sampler_state_table.bo_8x8);
2452
2453     /* sample_8x8 UV index 8 */
2454     index = 8;
2455     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2456     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2457     sampler_8x8[index].dw0.global_noise_estimation = 255;
2458     sampler_8x8[index].dw0.ief_bypass = 1;
2459     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2460     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2461     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2462     sampler_8x8[index].dw2.r5x_coefficient = 9;
2463     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2464     sampler_8x8[index].dw2.r5c_coefficient = 3;
2465     sampler_8x8[index].dw3.r3x_coefficient = 27;
2466     sampler_8x8[index].dw3.r3c_coefficient = 5;
2467     sampler_8x8[index].dw3.gain_factor = 40;
2468     sampler_8x8[index].dw3.non_edge_weight = 1;
2469     sampler_8x8[index].dw3.regular_weight = 2;
2470     sampler_8x8[index].dw3.strong_edge_weight = 7;
2471     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2472
2473     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2474                       I915_GEM_DOMAIN_RENDER,
2475                       0,
2476                       0,
2477                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2478                       pp_context->sampler_state_table.bo_8x8);
2479
2480     /* sampler_8x8 V, index 12 */
2481     index = 12;
2482     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2483     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2484     sampler_8x8[index].dw0.global_noise_estimation = 255;
2485     sampler_8x8[index].dw0.ief_bypass = 1;
2486     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2487     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2488     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2489     sampler_8x8[index].dw2.r5x_coefficient = 9;
2490     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2491     sampler_8x8[index].dw2.r5c_coefficient = 3;
2492     sampler_8x8[index].dw3.r3x_coefficient = 27;
2493     sampler_8x8[index].dw3.r3c_coefficient = 5;
2494     sampler_8x8[index].dw3.gain_factor = 40;
2495     sampler_8x8[index].dw3.non_edge_weight = 1;
2496     sampler_8x8[index].dw3.regular_weight = 2;
2497     sampler_8x8[index].dw3.strong_edge_weight = 7;
2498     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2499
2500     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2501                       I915_GEM_DOMAIN_RENDER,
2502                       0,
2503                       0,
2504                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2505                       pp_context->sampler_state_table.bo_8x8);
2506
2507     dri_bo_unmap(pp_context->sampler_state_table.bo);
2508
2509     /* private function & data */
2510     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2511     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2512     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2513
2514     pp_avs_context->dest_x = dst_rect->x;
2515     pp_avs_context->dest_y = dst_rect->y;
2516     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2517     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2518     pp_avs_context->src_w = src_rect->width;
2519     pp_avs_context->src_h = src_rect->height;
2520
2521     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2522     dw = MAX(dw, pp_avs_context->dest_w);
2523
2524     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2525     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2526     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2527     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2528     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2529
2530     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2531
2532     dst_surface->flags = src_surface->flags;
2533
2534     return VA_STATUS_SUCCESS;
2535 }
2536
2537 static int
2538 pp_dndi_x_steps(void *private_context)
2539 {
2540     return 1;
2541 }
2542
2543 static int
2544 pp_dndi_y_steps(void *private_context)
2545 {
2546     struct pp_dndi_context *pp_dndi_context = private_context;
2547
2548     return pp_dndi_context->dest_h / 4;
2549 }
2550
2551 static int
2552 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2553 {
2554     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2555
2556     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2557     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2558
2559     return 0;
2560 }
2561
2562 static VAStatus
2563 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2564                         const struct i965_surface *src_surface,
2565                         const VARectangle *src_rect,
2566                         struct i965_surface *dst_surface,
2567                         const VARectangle *dst_rect,
2568                         void *filter_param)
2569 {
2570     struct i965_driver_data *i965 = i965_driver_data(ctx);
2571     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2572     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2573     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2574     struct object_surface *obj_surface;
2575     struct i965_sampler_dndi *sampler_dndi;
2576     int index;
2577     int w, h;
2578     int orig_w, orig_h;
2579     int dndi_top_first = 1;
2580
2581     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2582         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2583
2584     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2585         dndi_top_first = 1;
2586     else
2587         dndi_top_first = 0;
2588
2589     /* surface */
2590     obj_surface = SURFACE(src_surface->id);
2591     orig_w = obj_surface->orig_width;
2592     orig_h = obj_surface->orig_height;
2593     w = obj_surface->width;
2594     h = obj_surface->height;
2595
2596     if (pp_context->stmm.bo == NULL) {
2597         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2598                                            "STMM surface",
2599                                            w * h,
2600                                            4096);
2601         assert(pp_context->stmm.bo);
2602     }
2603
2604     /* source UV surface index 2 */
2605     i965_pp_set_surface_state(ctx, pp_context,
2606                               obj_surface->bo, w * h,
2607                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2608                               2, 0);
2609
2610     /* source YUV surface index 4 */
2611     i965_pp_set_surface2_state(ctx, pp_context,
2612                                obj_surface->bo, 0,
2613                                orig_w, orig_h, w,
2614                                0, h,
2615                                SURFACE_FORMAT_PLANAR_420_8, 1,
2616                                4);
2617
2618     /* source STMM surface index 20 */
2619     i965_pp_set_surface_state(ctx, pp_context,
2620                               pp_context->stmm.bo, 0,
2621                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2622                               20, 1);
2623
2624     /* destination surface */
2625     obj_surface = SURFACE(dst_surface->id);
2626     orig_w = obj_surface->orig_width;
2627     orig_h = obj_surface->orig_height;
2628     w = obj_surface->width;
2629     h = obj_surface->height;
2630
2631     /* destination Y surface index 7 */
2632     i965_pp_set_surface_state(ctx, pp_context,
2633                               obj_surface->bo, 0,
2634                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2635                               7, 1);
2636
2637     /* destination UV surface index 8 */
2638     i965_pp_set_surface_state(ctx, pp_context,
2639                               obj_surface->bo, w * h,
2640                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2641                               8, 1);
2642     /* sampler dndi */
2643     dri_bo_map(pp_context->sampler_state_table.bo, True);
2644     assert(pp_context->sampler_state_table.bo->virtual);
2645     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2646     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2647
2648     /* sample dndi index 1 */
2649     index = 0;
2650     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2651     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2652     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2653     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2654
2655     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2656     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2657     sampler_dndi[index].dw1.stmm_c2 = 1;
2658     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2659     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2660
2661     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2662     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2663     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2664     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2665
2666     sampler_dndi[index].dw3.maximum_stmm = 128;
2667     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2668     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2669     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2670     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2671
2672     sampler_dndi[index].dw4.sdi_delta = 8;
2673     sampler_dndi[index].dw4.sdi_threshold = 128;
2674     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2675     sampler_dndi[index].dw4.stmm_shift_up = 0;
2676     sampler_dndi[index].dw4.stmm_shift_down = 0;
2677     sampler_dndi[index].dw4.minimum_stmm = 0;
2678
2679     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2680     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2681     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2682     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2683
2684     sampler_dndi[index].dw6.dn_enable = 1;
2685     sampler_dndi[index].dw6.di_enable = 1;
2686     sampler_dndi[index].dw6.di_partial = 0;
2687     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2688     sampler_dndi[index].dw6.dndi_stream_id = 0;
2689     sampler_dndi[index].dw6.dndi_first_frame = 1;
2690     sampler_dndi[index].dw6.progressive_dn = 0;
2691     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2692     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2693     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2694
2695     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2696     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2697     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2698     sampler_dndi[index].dw7.column_width_minus1 = 0;
2699
2700     dri_bo_unmap(pp_context->sampler_state_table.bo);
2701
2702     /* private function & data */
2703     pp_context->pp_x_steps = pp_dndi_x_steps;
2704     pp_context->pp_y_steps = pp_dndi_y_steps;
2705     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2706
2707     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2708     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2709     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2710     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2711
2712     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2713     pp_inline_parameter->grf5.number_blocks = w / 16;
2714     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2715     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2716
2717     pp_dndi_context->dest_w = w;
2718     pp_dndi_context->dest_h = h;
2719
2720     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2721
2722     return VA_STATUS_SUCCESS;
2723 }
2724
2725 static int
2726 pp_dn_x_steps(void *private_context)
2727 {
2728     return 1;
2729 }
2730
2731 static int
2732 pp_dn_y_steps(void *private_context)
2733 {
2734     struct pp_dn_context *pp_dn_context = private_context;
2735
2736     return pp_dn_context->dest_h / 8;
2737 }
2738
2739 static int
2740 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2741 {
2742     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2743
2744     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2745     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2746
2747     return 0;
2748 }
2749
2750 static VAStatus
2751 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2752                       const struct i965_surface *src_surface,
2753                       const VARectangle *src_rect,
2754                       struct i965_surface *dst_surface,
2755                       const VARectangle *dst_rect,
2756                       void *filter_param)
2757 {
2758     struct i965_driver_data *i965 = i965_driver_data(ctx);
2759     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2760     struct object_surface *obj_surface;
2761     struct i965_sampler_dndi *sampler_dndi;
2762     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2763     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2764     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2765     int index;
2766     int w, h;
2767     int orig_w, orig_h;
2768     int dn_strength = 15;
2769     int dndi_top_first = 1;
2770     int dn_progressive = 0;
2771
2772     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2773         dndi_top_first = 1;
2774         dn_progressive = 1;
2775     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2776         dndi_top_first = 1;
2777         dn_progressive = 0;
2778     } else {
2779         dndi_top_first = 0;
2780         dn_progressive = 0;
2781     }
2782
2783     if (dn_filter_param) {
2784         float value = dn_filter_param->value;
2785
2786         if (value > 1.0)
2787             value = 1.0;
2788
2789         if (value < 0.0)
2790             value = 0.0;
2791
2792         dn_strength = (int)(value * 31.0F);
2793     }
2794
2795     /* surface */
2796     obj_surface = SURFACE(src_surface->id);
2797     orig_w = obj_surface->orig_width;
2798     orig_h = obj_surface->orig_height;
2799     w = obj_surface->width;
2800     h = obj_surface->height;
2801
2802     if (pp_context->stmm.bo == NULL) {
2803         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2804                                            "STMM surface",
2805                                            w * h,
2806                                            4096);
2807         assert(pp_context->stmm.bo);
2808     }
2809
2810     /* source UV surface index 2 */
2811     i965_pp_set_surface_state(ctx, pp_context,
2812                               obj_surface->bo, w * h,
2813                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2814                               2, 0);
2815
2816     /* source YUV surface index 4 */
2817     i965_pp_set_surface2_state(ctx, pp_context,
2818                                obj_surface->bo, 0,
2819                                orig_w, orig_h, w,
2820                                0, h,
2821                                SURFACE_FORMAT_PLANAR_420_8, 1,
2822                                4);
2823
2824     /* source STMM surface index 20 */
2825     i965_pp_set_surface_state(ctx, pp_context,
2826                               pp_context->stmm.bo, 0,
2827                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2828                               20, 1);
2829
2830     /* destination surface */
2831     obj_surface = SURFACE(dst_surface->id);
2832     orig_w = obj_surface->orig_width;
2833     orig_h = obj_surface->orig_height;
2834     w = obj_surface->width;
2835     h = obj_surface->height;
2836
2837     /* destination Y surface index 7 */
2838     i965_pp_set_surface_state(ctx, pp_context,
2839                               obj_surface->bo, 0,
2840                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2841                               7, 1);
2842
2843     /* destination UV surface index 8 */
2844     i965_pp_set_surface_state(ctx, pp_context,
2845                               obj_surface->bo, w * h,
2846                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2847                               8, 1);
2848     /* sampler dn */
2849     dri_bo_map(pp_context->sampler_state_table.bo, True);
2850     assert(pp_context->sampler_state_table.bo->virtual);
2851     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2852     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2853
2854     /* sample dndi index 1 */
2855     index = 0;
2856     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2857     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2858     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2859     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2860
2861     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2862     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2863     sampler_dndi[index].dw1.stmm_c2 = 0;
2864     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2865     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2866
2867     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2868     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2869     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2870     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2871
2872     sampler_dndi[index].dw3.maximum_stmm = 128;
2873     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2874     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2875     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2876     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2877
2878     sampler_dndi[index].dw4.sdi_delta = 8;
2879     sampler_dndi[index].dw4.sdi_threshold = 128;
2880     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2881     sampler_dndi[index].dw4.stmm_shift_up = 0;
2882     sampler_dndi[index].dw4.stmm_shift_down = 0;
2883     sampler_dndi[index].dw4.minimum_stmm = 0;
2884
2885     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2886     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2887     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2888     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2889
2890     sampler_dndi[index].dw6.dn_enable = 1;
2891     sampler_dndi[index].dw6.di_enable = 0;
2892     sampler_dndi[index].dw6.di_partial = 0;
2893     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2894     sampler_dndi[index].dw6.dndi_stream_id = 1;
2895     sampler_dndi[index].dw6.dndi_first_frame = 1;
2896     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2897     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2898     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2899     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2900
2901     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2902     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2903     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2904     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2905
2906     dri_bo_unmap(pp_context->sampler_state_table.bo);
2907
2908     /* private function & data */
2909     pp_context->pp_x_steps = pp_dn_x_steps;
2910     pp_context->pp_y_steps = pp_dn_y_steps;
2911     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2912
2913     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2914     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2915     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2916     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2917
2918     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2919     pp_inline_parameter->grf5.number_blocks = w / 16;
2920     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2921     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2922
2923     pp_dn_context->dest_w = w;
2924     pp_dn_context->dest_h = h;
2925
2926     dst_surface->flags = src_surface->flags;
2927
2928     return VA_STATUS_SUCCESS;
2929 }
2930
2931 static int
2932 gen7_pp_dndi_x_steps(void *private_context)
2933 {
2934     struct pp_dndi_context *pp_dndi_context = private_context;
2935
2936     return pp_dndi_context->dest_w / 16;
2937 }
2938
2939 static int
2940 gen7_pp_dndi_y_steps(void *private_context)
2941 {
2942     struct pp_dndi_context *pp_dndi_context = private_context;
2943
2944     return pp_dndi_context->dest_h / 4;
2945 }
2946
2947 static int
2948 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2949 {
2950     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2951
2952     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2953     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2954
2955     return 0;
2956 }
2957
2958 static VAStatus
2959 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2960                              const struct i965_surface *src_surface,
2961                              const VARectangle *src_rect,
2962                              struct i965_surface *dst_surface,
2963                              const VARectangle *dst_rect,
2964                              void *filter_param)
2965 {
2966     struct i965_driver_data *i965 = i965_driver_data(ctx);
2967     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2968     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2969     struct object_surface *obj_surface;
2970     struct gen7_sampler_dndi *sampler_dndi;
2971     int index;
2972     int w, h;
2973     int orig_w, orig_h;
2974     int dndi_top_first = 1;
2975
2976     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2977         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2978
2979     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2980         dndi_top_first = 1;
2981     else
2982         dndi_top_first = 0;
2983
2984     /* surface */
2985     obj_surface = SURFACE(src_surface->id);
2986     orig_w = obj_surface->orig_width;
2987     orig_h = obj_surface->orig_height;
2988     w = obj_surface->width;
2989     h = obj_surface->height;
2990
2991     if (pp_context->stmm.bo == NULL) {
2992         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2993                                            "STMM surface",
2994                                            w * h,
2995                                            4096);
2996         assert(pp_context->stmm.bo);
2997     }
2998
2999     /* source UV surface index 1 */
3000     gen7_pp_set_surface_state(ctx, pp_context,
3001                               obj_surface->bo, w * h,
3002                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3003                               1, 0);
3004
3005     /* source YUV surface index 3 */
3006     gen7_pp_set_surface2_state(ctx, pp_context,
3007                                obj_surface->bo, 0,
3008                                orig_w, orig_h, w,
3009                                0, h,
3010                                SURFACE_FORMAT_PLANAR_420_8, 1,
3011                                3);
3012
3013     /* source (temporal reference) YUV surface index 4 */
3014     gen7_pp_set_surface2_state(ctx, pp_context,
3015                                obj_surface->bo, 0,
3016                                orig_w, orig_h, w,
3017                                0, h,
3018                                SURFACE_FORMAT_PLANAR_420_8, 1,
3019                                4);
3020
3021     /* STMM / History Statistics input surface, index 5 */
3022     gen7_pp_set_surface_state(ctx, pp_context,
3023                               pp_context->stmm.bo, 0,
3024                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3025                               5, 1);
3026
3027     /* destination surface */
3028     obj_surface = SURFACE(dst_surface->id);
3029     orig_w = obj_surface->orig_width;
3030     orig_h = obj_surface->orig_height;
3031     w = obj_surface->width;
3032     h = obj_surface->height;
3033
3034     /* destination(Previous frame) Y surface index 27 */
3035     gen7_pp_set_surface_state(ctx, pp_context,
3036                               obj_surface->bo, 0,
3037                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3038                               27, 1);
3039
3040     /* destination(Previous frame) UV surface index 28 */
3041     gen7_pp_set_surface_state(ctx, pp_context,
3042                               obj_surface->bo, w * h,
3043                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3044                               28, 1);
3045
3046     /* destination(Current frame) Y surface index 30 */
3047     gen7_pp_set_surface_state(ctx, pp_context,
3048                               obj_surface->bo, 0,
3049                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3050                               30, 1);
3051
3052     /* destination(Current frame) UV surface index 31 */
3053     gen7_pp_set_surface_state(ctx, pp_context,
3054                               obj_surface->bo, w * h,
3055                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3056                               31, 1);
3057
3058     /* STMM output surface, index 33 */
3059     gen7_pp_set_surface_state(ctx, pp_context,
3060                               pp_context->stmm.bo, 0,
3061                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3062                               33, 1);
3063
3064
3065     /* sampler dndi */
3066     dri_bo_map(pp_context->sampler_state_table.bo, True);
3067     assert(pp_context->sampler_state_table.bo->virtual);
3068     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
3069     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
3070
3071     /* sample dndi index 0 */
3072     index = 0;
3073     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
3074     sampler_dndi[index].dw0.dnmh_delt = 8;
3075     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
3076     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
3077     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
3078     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
3079
3080     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3081     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
3082     sampler_dndi[index].dw1.stmm_c2 = 0;
3083     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
3084     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
3085
3086     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
3087     sampler_dndi[index].dw2.bne_edge_th = 1;
3088     sampler_dndi[index].dw2.smooth_mv_th = 0;
3089     sampler_dndi[index].dw2.sad_tight_th = 5;
3090     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
3091     sampler_dndi[index].dw2.good_neighbor_th = 4;
3092
3093     sampler_dndi[index].dw3.maximum_stmm = 128;
3094     sampler_dndi[index].dw3.multipler_for_vecm = 2;
3095     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3096     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3097     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
3098
3099     sampler_dndi[index].dw4.sdi_delta = 8;
3100     sampler_dndi[index].dw4.sdi_threshold = 128;
3101     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3102     sampler_dndi[index].dw4.stmm_shift_up = 0;
3103     sampler_dndi[index].dw4.stmm_shift_down = 0;
3104     sampler_dndi[index].dw4.minimum_stmm = 0;
3105
3106     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
3107     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
3108     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3109     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3110
3111     sampler_dndi[index].dw6.dn_enable = 0;
3112     sampler_dndi[index].dw6.di_enable = 1;
3113     sampler_dndi[index].dw6.di_partial = 0;
3114     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
3115     sampler_dndi[index].dw6.dndi_stream_id = 1;
3116     sampler_dndi[index].dw6.dndi_first_frame = 1;
3117     sampler_dndi[index].dw6.progressive_dn = 0;
3118     sampler_dndi[index].dw6.mcdi_enable = 0;
3119     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3120     sampler_dndi[index].dw6.cat_th1 = 0;
3121     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3122     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3123
3124     sampler_dndi[index].dw7.sad_tha = 5;
3125     sampler_dndi[index].dw7.sad_thb = 10;
3126     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3127     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3128     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3129     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3130     sampler_dndi[index].dw7.neighborpixel_th = 10;
3131     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3132
3133     dri_bo_unmap(pp_context->sampler_state_table.bo);
3134
3135     /* private function & data */
3136     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3137     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3138     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3139
3140     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3141     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3142     pp_static_parameter->grf1.di_top_field_first = 0;
3143     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3144
3145     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3146     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3147     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3148
3149     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3150     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3151
3152     pp_dndi_context->dest_w = w;
3153     pp_dndi_context->dest_h = h;
3154
3155     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3156
3157     return VA_STATUS_SUCCESS;
3158 }
3159
3160 static int
3161 gen7_pp_dn_x_steps(void *private_context)
3162 {
3163     struct pp_dn_context *pp_dn_context = private_context;
3164
3165     return pp_dn_context->dest_w / 16;
3166 }
3167
3168 static int
3169 gen7_pp_dn_y_steps(void *private_context)
3170 {
3171     struct pp_dn_context *pp_dn_context = private_context;
3172
3173     return pp_dn_context->dest_h / 4;
3174 }
3175
3176 static int
3177 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3178 {
3179     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3180
3181     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3182     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3183
3184     return 0;
3185 }
3186
3187 static VAStatus
3188 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3189                            const struct i965_surface *src_surface,
3190                            const VARectangle *src_rect,
3191                            struct i965_surface *dst_surface,
3192                            const VARectangle *dst_rect,
3193                            void *filter_param)
3194 {
3195     struct i965_driver_data *i965 = i965_driver_data(ctx);
3196     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3197     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3198     struct object_surface *obj_surface;
3199     struct gen7_sampler_dndi *sampler_dn;
3200     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3201     int index;
3202     int w, h;
3203     int orig_w, orig_h;
3204     int dn_strength = 15;
3205     int dndi_top_first = 1;
3206     int dn_progressive = 0;
3207
3208     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3209         dndi_top_first = 1;
3210         dn_progressive = 1;
3211     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3212         dndi_top_first = 1;
3213         dn_progressive = 0;
3214     } else {
3215         dndi_top_first = 0;
3216         dn_progressive = 0;
3217     }
3218
3219     if (dn_filter_param) {
3220         float value = dn_filter_param->value;
3221
3222         if (value > 1.0)
3223             value = 1.0;
3224
3225         if (value < 0.0)
3226             value = 0.0;
3227
3228         dn_strength = (int)(value * 31.0F);
3229     }
3230
3231     /* surface */
3232     obj_surface = SURFACE(src_surface->id);
3233     orig_w = obj_surface->orig_width;
3234     orig_h = obj_surface->orig_height;
3235     w = obj_surface->width;
3236     h = obj_surface->height;
3237
3238     if (pp_context->stmm.bo == NULL) {
3239         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3240                                            "STMM surface",
3241                                            w * h,
3242                                            4096);
3243         assert(pp_context->stmm.bo);
3244     }
3245
3246     /* source UV surface index 1 */
3247     gen7_pp_set_surface_state(ctx, pp_context,
3248                               obj_surface->bo, w * h,
3249                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3250                               1, 0);
3251
3252     /* source YUV surface index 3 */
3253     gen7_pp_set_surface2_state(ctx, pp_context,
3254                                obj_surface->bo, 0,
3255                                orig_w, orig_h, w,
3256                                0, h,
3257                                SURFACE_FORMAT_PLANAR_420_8, 1,
3258                                3);
3259
3260     /* source (temporal reference) YUV surface index 4 */
3261     gen7_pp_set_surface2_state(ctx, pp_context,
3262                                obj_surface->bo, 0,
3263                                orig_w, orig_h, w,
3264                                0, h,
3265                                SURFACE_FORMAT_PLANAR_420_8, 1,
3266                                4);
3267
3268     /* STMM / History Statistics input surface, index 5 */
3269     gen7_pp_set_surface_state(ctx, pp_context,
3270                               pp_context->stmm.bo, 0,
3271                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3272                               5, 1);
3273
3274     /* destination surface */
3275     obj_surface = SURFACE(dst_surface->id);
3276     orig_w = obj_surface->orig_width;
3277     orig_h = obj_surface->orig_height;
3278     w = obj_surface->width;
3279     h = obj_surface->height;
3280
3281     /* destination Y surface index 24 */
3282     gen7_pp_set_surface_state(ctx, pp_context,
3283                               obj_surface->bo, 0,
3284                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3285                               24, 1);
3286
3287     /* destination UV surface index 25 */
3288     gen7_pp_set_surface_state(ctx, pp_context,
3289                               obj_surface->bo, w * h,
3290                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3291                               25, 1);
3292
3293     /* sampler dn */
3294     dri_bo_map(pp_context->sampler_state_table.bo, True);
3295     assert(pp_context->sampler_state_table.bo->virtual);
3296     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3297     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3298
3299     /* sample dn index 1 */
3300     index = 0;
3301     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3302     sampler_dn[index].dw0.dnmh_delt = 8;
3303     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3304     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3305     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3306     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3307
3308     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3309     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3310     sampler_dn[index].dw1.stmm_c2 = 0;
3311     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3312     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3313
3314     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3315     sampler_dn[index].dw2.bne_edge_th = 1;
3316     sampler_dn[index].dw2.smooth_mv_th = 0;
3317     sampler_dn[index].dw2.sad_tight_th = 5;
3318     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3319     sampler_dn[index].dw2.good_neighbor_th = 4;
3320
3321     sampler_dn[index].dw3.maximum_stmm = 128;
3322     sampler_dn[index].dw3.multipler_for_vecm = 2;
3323     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3324     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3325     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3326
3327     sampler_dn[index].dw4.sdi_delta = 8;
3328     sampler_dn[index].dw4.sdi_threshold = 128;
3329     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3330     sampler_dn[index].dw4.stmm_shift_up = 0;
3331     sampler_dn[index].dw4.stmm_shift_down = 0;
3332     sampler_dn[index].dw4.minimum_stmm = 0;
3333
3334     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3335     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3336     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3337     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3338
3339     sampler_dn[index].dw6.dn_enable = 1;
3340     sampler_dn[index].dw6.di_enable = 0;
3341     sampler_dn[index].dw6.di_partial = 0;
3342     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3343     sampler_dn[index].dw6.dndi_stream_id = 1;
3344     sampler_dn[index].dw6.dndi_first_frame = 1;
3345     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3346     sampler_dn[index].dw6.mcdi_enable = 0;
3347     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3348     sampler_dn[index].dw6.cat_th1 = 0;
3349     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3350     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3351
3352     sampler_dn[index].dw7.sad_tha = 5;
3353     sampler_dn[index].dw7.sad_thb = 10;
3354     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3355     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3356     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3357     sampler_dn[index].dw7.vdi_walker_enable = 0;
3358     sampler_dn[index].dw7.neighborpixel_th = 10;
3359     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3360
3361     dri_bo_unmap(pp_context->sampler_state_table.bo);
3362
3363     /* private function & data */
3364     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3365     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3366     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3367
3368     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3369     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3370     pp_static_parameter->grf1.di_top_field_first = 0;
3371     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3372
3373     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3374     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3375     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3376
3377     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3378     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3379
3380     pp_dn_context->dest_w = w;
3381     pp_dn_context->dest_h = h;
3382
3383     dst_surface->flags = src_surface->flags;
3384
3385     return VA_STATUS_SUCCESS;
3386 }
3387
3388 static VAStatus
3389 ironlake_pp_initialize(
3390     VADriverContextP   ctx,
3391     struct i965_post_processing_context *pp_context,
3392     const struct i965_surface *src_surface,
3393     const VARectangle *src_rect,
3394     struct i965_surface *dst_surface,
3395     const VARectangle *dst_rect,
3396     int                pp_index,
3397     void *filter_param
3398 )
3399 {
3400     VAStatus va_status;
3401     struct i965_driver_data *i965 = i965_driver_data(ctx);
3402     struct pp_module *pp_module;
3403     dri_bo *bo;
3404     int static_param_size, inline_param_size;
3405
3406     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3407     bo = dri_bo_alloc(i965->intel.bufmgr,
3408                       "surface state & binding table",
3409                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3410                       4096);
3411     assert(bo);
3412     pp_context->surface_state_binding_table.bo = bo;
3413
3414     dri_bo_unreference(pp_context->curbe.bo);
3415     bo = dri_bo_alloc(i965->intel.bufmgr,
3416                       "constant buffer",
3417                       4096,
3418                       4096);
3419     assert(bo);
3420     pp_context->curbe.bo = bo;
3421
3422     dri_bo_unreference(pp_context->idrt.bo);
3423     bo = dri_bo_alloc(i965->intel.bufmgr,
3424                       "interface discriptor",
3425                       sizeof(struct i965_interface_descriptor),
3426                       4096);
3427     assert(bo);
3428     pp_context->idrt.bo = bo;
3429     pp_context->idrt.num_interface_descriptors = 0;
3430
3431     dri_bo_unreference(pp_context->sampler_state_table.bo);
3432     bo = dri_bo_alloc(i965->intel.bufmgr,
3433                       "sampler state table",
3434                       4096,
3435                       4096);
3436     assert(bo);
3437     dri_bo_map(bo, True);
3438     memset(bo->virtual, 0, bo->size);
3439     dri_bo_unmap(bo);
3440     pp_context->sampler_state_table.bo = bo;
3441
3442     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3443     bo = dri_bo_alloc(i965->intel.bufmgr,
3444                       "sampler 8x8 state ",
3445                       4096,
3446                       4096);
3447     assert(bo);
3448     pp_context->sampler_state_table.bo_8x8 = bo;
3449
3450     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3451     bo = dri_bo_alloc(i965->intel.bufmgr,
3452                       "sampler 8x8 state ",
3453                       4096,
3454                       4096);
3455     assert(bo);
3456     pp_context->sampler_state_table.bo_8x8_uv = bo;
3457
3458     dri_bo_unreference(pp_context->vfe_state.bo);
3459     bo = dri_bo_alloc(i965->intel.bufmgr,
3460                       "vfe state",
3461                       sizeof(struct i965_vfe_state),
3462                       4096);
3463     assert(bo);
3464     pp_context->vfe_state.bo = bo;
3465
3466     static_param_size = sizeof(struct pp_static_parameter);
3467     inline_param_size = sizeof(struct pp_inline_parameter);
3468
3469     memset(pp_context->pp_static_parameter, 0, static_param_size);
3470     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3471
3472     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3473     pp_context->current_pp = pp_index;
3474     pp_module = &pp_context->pp_modules[pp_index];
3475
3476     if (pp_module->initialize)
3477         va_status = pp_module->initialize(ctx, pp_context,
3478                                           src_surface,
3479                                           src_rect,
3480                                           dst_surface,
3481                                           dst_rect,
3482                                           filter_param);
3483     else
3484         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3485
3486     return va_status;
3487 }
3488
3489 static VAStatus
3490 ironlake_post_processing(
3491     VADriverContextP   ctx,
3492     struct i965_post_processing_context *pp_context,
3493     const struct i965_surface *src_surface,
3494     const VARectangle *src_rect,
3495     struct i965_surface *dst_surface,
3496     const VARectangle *dst_rect,
3497     int                pp_index,
3498     void *filter_param
3499 )
3500 {
3501     VAStatus va_status;
3502
3503     va_status = ironlake_pp_initialize(ctx, pp_context,
3504                                        src_surface,
3505                                        src_rect,
3506                                        dst_surface,
3507                                        dst_rect,
3508                                        pp_index,
3509                                        filter_param);
3510
3511     if (va_status == VA_STATUS_SUCCESS) {
3512         ironlake_pp_states_setup(ctx, pp_context);
3513         ironlake_pp_pipeline_setup(ctx, pp_context);
3514     }
3515
3516     return va_status;
3517 }
3518
3519 static VAStatus
3520 gen6_pp_initialize(
3521     VADriverContextP   ctx,
3522     struct i965_post_processing_context *pp_context,
3523     const struct i965_surface *src_surface,
3524     const VARectangle *src_rect,
3525     struct i965_surface *dst_surface,
3526     const VARectangle *dst_rect,
3527     int                pp_index,
3528     void *filter_param
3529 )
3530 {
3531     VAStatus va_status;
3532     struct i965_driver_data *i965 = i965_driver_data(ctx);
3533     struct pp_module *pp_module;
3534     dri_bo *bo;
3535     int static_param_size, inline_param_size;
3536
3537     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3538     bo = dri_bo_alloc(i965->intel.bufmgr,
3539                       "surface state & binding table",
3540                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3541                       4096);
3542     assert(bo);
3543     pp_context->surface_state_binding_table.bo = bo;
3544
3545     dri_bo_unreference(pp_context->curbe.bo);
3546     bo = dri_bo_alloc(i965->intel.bufmgr,
3547                       "constant buffer",
3548                       4096,
3549                       4096);
3550     assert(bo);
3551     pp_context->curbe.bo = bo;
3552
3553     dri_bo_unreference(pp_context->idrt.bo);
3554     bo = dri_bo_alloc(i965->intel.bufmgr,
3555                       "interface discriptor",
3556                       sizeof(struct gen6_interface_descriptor_data),
3557                       4096);
3558     assert(bo);
3559     pp_context->idrt.bo = bo;
3560     pp_context->idrt.num_interface_descriptors = 0;
3561
3562     dri_bo_unreference(pp_context->sampler_state_table.bo);
3563     bo = dri_bo_alloc(i965->intel.bufmgr,
3564                       "sampler state table",
3565                       4096,
3566                       4096);
3567     assert(bo);
3568     dri_bo_map(bo, True);
3569     memset(bo->virtual, 0, bo->size);
3570     dri_bo_unmap(bo);
3571     pp_context->sampler_state_table.bo = bo;
3572
3573     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3574     bo = dri_bo_alloc(i965->intel.bufmgr,
3575                       "sampler 8x8 state ",
3576                       4096,
3577                       4096);
3578     assert(bo);
3579     pp_context->sampler_state_table.bo_8x8 = bo;
3580
3581     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3582     bo = dri_bo_alloc(i965->intel.bufmgr,
3583                       "sampler 8x8 state ",
3584                       4096,
3585                       4096);
3586     assert(bo);
3587     pp_context->sampler_state_table.bo_8x8_uv = bo;
3588
3589     dri_bo_unreference(pp_context->vfe_state.bo);
3590     bo = dri_bo_alloc(i965->intel.bufmgr,
3591                       "vfe state",
3592                       sizeof(struct i965_vfe_state),
3593                       4096);
3594     assert(bo);
3595     pp_context->vfe_state.bo = bo;
3596
3597     if (IS_GEN7(i965->intel.device_id)) {
3598         static_param_size = sizeof(struct gen7_pp_static_parameter);
3599         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3600     } else {
3601         static_param_size = sizeof(struct pp_static_parameter);
3602         inline_param_size = sizeof(struct pp_inline_parameter);
3603     }
3604
3605     memset(pp_context->pp_static_parameter, 0, static_param_size);
3606     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3607
3608     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3609     pp_context->current_pp = pp_index;
3610     pp_module = &pp_context->pp_modules[pp_index];
3611
3612     if (pp_module->initialize)
3613         va_status = pp_module->initialize(ctx, pp_context,
3614                                           src_surface,
3615                                           src_rect,
3616                                           dst_surface,
3617                                           dst_rect,
3618                                           filter_param);
3619     else
3620         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3621
3622     return va_status;
3623 }
3624
3625 static void
3626 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3627                                    struct i965_post_processing_context *pp_context)
3628 {
3629     struct i965_driver_data *i965 = i965_driver_data(ctx);
3630     struct gen6_interface_descriptor_data *desc;
3631     dri_bo *bo;
3632     int pp_index = pp_context->current_pp;
3633
3634     bo = pp_context->idrt.bo;
3635     dri_bo_map(bo, True);
3636     assert(bo->virtual);
3637     desc = bo->virtual;
3638     memset(desc, 0, sizeof(*desc));
3639     desc->desc0.kernel_start_pointer =
3640         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3641     desc->desc1.single_program_flow = 1;
3642     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3643     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3644     desc->desc2.sampler_state_pointer =
3645         pp_context->sampler_state_table.bo->offset >> 5;
3646     desc->desc3.binding_table_entry_count = 0;
3647     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3648     desc->desc4.constant_urb_entry_read_offset = 0;
3649
3650     if (IS_GEN7(i965->intel.device_id))
3651         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3652     else
3653         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3654
3655     dri_bo_emit_reloc(bo,
3656                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3657                       0,
3658                       offsetof(struct gen6_interface_descriptor_data, desc0),
3659                       pp_context->pp_modules[pp_index].kernel.bo);
3660
3661     dri_bo_emit_reloc(bo,
3662                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3663                       desc->desc2.sampler_count << 2,
3664                       offsetof(struct gen6_interface_descriptor_data, desc2),
3665                       pp_context->sampler_state_table.bo);
3666
3667     dri_bo_unmap(bo);
3668     pp_context->idrt.num_interface_descriptors++;
3669 }
3670
3671 static void
3672 gen6_pp_upload_constants(VADriverContextP ctx,
3673                          struct i965_post_processing_context *pp_context)
3674 {
3675     struct i965_driver_data *i965 = i965_driver_data(ctx);
3676     unsigned char *constant_buffer;
3677     int param_size;
3678
3679     assert(sizeof(struct pp_static_parameter) == 128);
3680     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3681
3682     if (IS_GEN7(i965->intel.device_id))
3683         param_size = sizeof(struct gen7_pp_static_parameter);
3684     else
3685         param_size = sizeof(struct pp_static_parameter);
3686
3687     dri_bo_map(pp_context->curbe.bo, 1);
3688     assert(pp_context->curbe.bo->virtual);
3689     constant_buffer = pp_context->curbe.bo->virtual;
3690     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3691     dri_bo_unmap(pp_context->curbe.bo);
3692 }
3693
3694 static void
3695 gen6_pp_states_setup(VADriverContextP ctx,
3696                      struct i965_post_processing_context *pp_context)
3697 {
3698     gen6_pp_interface_descriptor_table(ctx, pp_context);
3699     gen6_pp_upload_constants(ctx, pp_context);
3700 }
3701
3702 static void
3703 gen6_pp_pipeline_select(VADriverContextP ctx,
3704                         struct i965_post_processing_context *pp_context)
3705 {
3706     struct intel_batchbuffer *batch = pp_context->batch;
3707
3708     BEGIN_BATCH(batch, 1);
3709     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3710     ADVANCE_BATCH(batch);
3711 }
3712
3713 static void
3714 gen6_pp_state_base_address(VADriverContextP ctx,
3715                            struct i965_post_processing_context *pp_context)
3716 {
3717     struct intel_batchbuffer *batch = pp_context->batch;
3718
3719     BEGIN_BATCH(batch, 10);
3720     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3721     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3722     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3723     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3724     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3725     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3726     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3727     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3728     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3729     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3730     ADVANCE_BATCH(batch);
3731 }
3732
3733 static void
3734 gen6_pp_vfe_state(VADriverContextP ctx,
3735                   struct i965_post_processing_context *pp_context)
3736 {
3737     struct intel_batchbuffer *batch = pp_context->batch;
3738
3739     BEGIN_BATCH(batch, 8);
3740     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3741     OUT_BATCH(batch, 0);
3742     OUT_BATCH(batch,
3743               (pp_context->urb.num_vfe_entries - 1) << 16 |
3744               pp_context->urb.num_vfe_entries << 8);
3745     OUT_BATCH(batch, 0);
3746     OUT_BATCH(batch,
3747               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3748               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3749     OUT_BATCH(batch, 0);
3750     OUT_BATCH(batch, 0);
3751     OUT_BATCH(batch, 0);
3752     ADVANCE_BATCH(batch);
3753 }
3754
3755 static void
3756 gen6_pp_curbe_load(VADriverContextP ctx,
3757                    struct i965_post_processing_context *pp_context)
3758 {
3759     struct intel_batchbuffer *batch = pp_context->batch;
3760
3761     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3762
3763     BEGIN_BATCH(batch, 4);
3764     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3765     OUT_BATCH(batch, 0);
3766     OUT_BATCH(batch,
3767               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3768     OUT_RELOC(batch,
3769               pp_context->curbe.bo,
3770               I915_GEM_DOMAIN_INSTRUCTION, 0,
3771               0);
3772     ADVANCE_BATCH(batch);
3773 }
3774
3775 static void
3776 gen6_interface_descriptor_load(VADriverContextP ctx,
3777                                struct i965_post_processing_context *pp_context)
3778 {
3779     struct intel_batchbuffer *batch = pp_context->batch;
3780
3781     BEGIN_BATCH(batch, 4);
3782     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3783     OUT_BATCH(batch, 0);
3784     OUT_BATCH(batch,
3785               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3786     OUT_RELOC(batch,
3787               pp_context->idrt.bo,
3788               I915_GEM_DOMAIN_INSTRUCTION, 0,
3789               0);
3790     ADVANCE_BATCH(batch);
3791 }
3792
3793 static void
3794 gen6_pp_object_walker(VADriverContextP ctx,
3795                       struct i965_post_processing_context *pp_context)
3796 {
3797     struct i965_driver_data *i965 = i965_driver_data(ctx);
3798     struct intel_batchbuffer *batch = pp_context->batch;
3799     int x, x_steps, y, y_steps;
3800     int param_size, command_length_in_dws;
3801     dri_bo *command_buffer;
3802     unsigned int *command_ptr;
3803
3804     if (IS_GEN7(i965->intel.device_id))
3805         param_size = sizeof(struct gen7_pp_inline_parameter);
3806     else
3807         param_size = sizeof(struct pp_inline_parameter);
3808
3809     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3810     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3811     command_length_in_dws = 6 + (param_size >> 2);
3812     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3813                                   "command objects buffer",
3814                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3815                                   4096);
3816
3817     dri_bo_map(command_buffer, 1);
3818     command_ptr = command_buffer->virtual;
3819
3820     for (y = 0; y < y_steps; y++) {
3821         for (x = 0; x < x_steps; x++) {
3822             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3823                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3824                 *command_ptr++ = 0;
3825                 *command_ptr++ = 0;
3826                 *command_ptr++ = 0;
3827                 *command_ptr++ = 0;
3828                 *command_ptr++ = 0;
3829                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3830                 command_ptr += (param_size >> 2);
3831             }
3832         }
3833     }
3834
3835     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3836         *command_ptr++ = 0;
3837
3838     *command_ptr = MI_BATCH_BUFFER_END;
3839
3840     dri_bo_unmap(command_buffer);
3841
3842     BEGIN_BATCH(batch, 2);
3843     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3844     OUT_RELOC(batch, command_buffer,
3845               I915_GEM_DOMAIN_COMMAND, 0,
3846               0);
3847     ADVANCE_BATCH(batch);
3848
3849     dri_bo_unreference(command_buffer);
3850
3851     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3852      * will cause control to pass back to ring buffer
3853      */
3854     intel_batchbuffer_end_atomic(batch);
3855     intel_batchbuffer_flush(batch);
3856     intel_batchbuffer_start_atomic(batch, 0x1000);
3857 }
3858
3859 static void
3860 gen6_pp_pipeline_setup(VADriverContextP ctx,
3861                        struct i965_post_processing_context *pp_context)
3862 {
3863     struct intel_batchbuffer *batch = pp_context->batch;
3864
3865     intel_batchbuffer_start_atomic(batch, 0x1000);
3866     intel_batchbuffer_emit_mi_flush(batch);
3867     gen6_pp_pipeline_select(ctx, pp_context);
3868     gen6_pp_state_base_address(ctx, pp_context);
3869     gen6_pp_vfe_state(ctx, pp_context);
3870     gen6_pp_curbe_load(ctx, pp_context);
3871     gen6_interface_descriptor_load(ctx, pp_context);
3872     gen6_pp_object_walker(ctx, pp_context);
3873     intel_batchbuffer_end_atomic(batch);
3874 }
3875
3876 static VAStatus
3877 gen6_post_processing(
3878     VADriverContextP   ctx,
3879     struct i965_post_processing_context *pp_context,
3880     const struct i965_surface *src_surface,
3881     const VARectangle *src_rect,
3882     struct i965_surface *dst_surface,
3883     const VARectangle *dst_rect,
3884     int                pp_index,
3885     void * filter_param
3886 )
3887 {
3888     VAStatus va_status;
3889
3890     va_status = gen6_pp_initialize(ctx, pp_context,
3891                                    src_surface,
3892                                    src_rect,
3893                                    dst_surface,
3894                                    dst_rect,
3895                                    pp_index,
3896                                    filter_param);
3897
3898     if (va_status == VA_STATUS_SUCCESS) {
3899         gen6_pp_states_setup(ctx, pp_context);
3900         gen6_pp_pipeline_setup(ctx, pp_context);
3901     }
3902
3903     return va_status;
3904 }
3905
3906 static VAStatus
3907 i965_post_processing_internal(
3908     VADriverContextP   ctx,
3909     struct i965_post_processing_context *pp_context,
3910     const struct i965_surface *src_surface,
3911     const VARectangle *src_rect,
3912     struct i965_surface *dst_surface,
3913     const VARectangle *dst_rect,
3914     int                pp_index,
3915     void *filter_param
3916 )
3917 {
3918     struct i965_driver_data *i965 = i965_driver_data(ctx);
3919     VAStatus va_status;
3920
3921     if (IS_GEN6(i965->intel.device_id) ||
3922         IS_GEN7(i965->intel.device_id))
3923         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3924     else
3925         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3926
3927     return va_status;
3928 }
3929
3930 VAStatus
3931 i965_DestroySurfaces(VADriverContextP ctx,
3932                      VASurfaceID *surface_list,
3933                      int num_surfaces);
3934 VAStatus
3935 i965_CreateSurfaces(VADriverContextP ctx,
3936                     int width,
3937                     int height,
3938                     int format,
3939                     int num_surfaces,
3940                     VASurfaceID *surfaces);
3941
3942 static void
3943 rgb_to_yuv(unsigned int argb,
3944            unsigned char *y,
3945            unsigned char *u,
3946            unsigned char *v,
3947            unsigned char *a)
3948 {
3949     int r = ((argb >> 16) & 0xff);
3950     int g = ((argb >> 8) & 0xff);
3951     int b = ((argb >> 0) & 0xff);
3952
3953     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3954     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3955     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3956     *a = ((argb >> 24) & 0xff);
3957 }
3958
3959 static void
3960 i965_vpp_clear_surface(VADriverContextP ctx,
3961                        struct i965_post_processing_context *pp_context,
3962                        VASurfaceID surface,
3963                        unsigned int color)
3964 {
3965     struct i965_driver_data *i965 = i965_driver_data(ctx);
3966     struct intel_batchbuffer *batch = pp_context->batch;
3967     struct object_surface *obj_surface = SURFACE(surface);
3968     unsigned int blt_cmd, br13;
3969     unsigned int tiling = 0, swizzle = 0;
3970     int pitch;
3971     unsigned char y, u, v, a = 0;
3972
3973     /* Currently only support NV12 surface */
3974     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3975         return;
3976
3977     rgb_to_yuv(color, &y, &u, &v, &a);
3978
3979     if (a == 0)
3980         return;
3981
3982     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3983     blt_cmd = XY_COLOR_BLT_CMD;
3984     pitch = obj_surface->width;
3985
3986     if (tiling != I915_TILING_NONE) {
3987         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3988         pitch >>= 2;
3989     }
3990
3991     br13 = 0xf0 << 16;
3992     br13 |= BR13_8;
3993     br13 |= pitch;
3994
3995     if (IS_GEN6(i965->intel.device_id) ||
3996         IS_GEN7(i965->intel.device_id)) {
3997         intel_batchbuffer_start_atomic_blt(batch, 48);
3998         BEGIN_BLT_BATCH(batch, 12);
3999     } else {
4000         intel_batchbuffer_start_atomic(batch, 48);
4001         BEGIN_BATCH(batch, 12);
4002     }
4003
4004     OUT_BATCH(batch, blt_cmd);
4005     OUT_BATCH(batch, br13);
4006     OUT_BATCH(batch,
4007               0 << 16 |
4008               0);
4009     OUT_BATCH(batch,
4010               obj_surface->height << 16 |
4011               obj_surface->width);
4012     OUT_RELOC(batch, obj_surface->bo,
4013               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4014               0);
4015     OUT_BATCH(batch, y);
4016
4017     br13 = 0xf0 << 16;
4018     br13 |= BR13_565;
4019     br13 |= pitch;
4020
4021     OUT_BATCH(batch, blt_cmd);
4022     OUT_BATCH(batch, br13);
4023     OUT_BATCH(batch,
4024               0 << 16 |
4025               0);
4026     OUT_BATCH(batch,
4027               obj_surface->height / 2 << 16 |
4028               obj_surface->width / 2);
4029     OUT_RELOC(batch, obj_surface->bo,
4030               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4031               obj_surface->width * obj_surface->y_cb_offset);
4032     OUT_BATCH(batch, v << 8 | u);
4033
4034     ADVANCE_BATCH(batch);
4035     intel_batchbuffer_end_atomic(batch);
4036 }
4037
4038 VASurfaceID
4039 i965_post_processing(
4040     VADriverContextP   ctx,
4041     VASurfaceID        surface,
4042     const VARectangle *src_rect,
4043     const VARectangle *dst_rect,
4044     unsigned int       flags,
4045     int               *has_done_scaling
4046 )
4047 {
4048     struct i965_driver_data *i965 = i965_driver_data(ctx);
4049     VASurfaceID in_surface_id = surface;
4050     VASurfaceID out_surface_id = VA_INVALID_ID;
4051
4052     *has_done_scaling = 0;
4053
4054     if (HAS_PP(i965)) {
4055         struct object_surface *obj_surface;
4056         VAStatus status;
4057         struct i965_surface src_surface;
4058         struct i965_surface dst_surface;
4059
4060         obj_surface = SURFACE(in_surface_id);
4061
4062         /* Currently only support post processing for NV12 surface */
4063         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
4064             return out_surface_id;
4065
4066         _i965LockMutex(&i965->pp_mutex);
4067
4068         if (flags & I965_PP_FLAG_MCDI) {
4069             status = i965_CreateSurfaces(ctx,
4070                                          obj_surface->orig_width,
4071                                          obj_surface->orig_height,
4072                                          VA_RT_FORMAT_YUV420,
4073                                          1,
4074                                          &out_surface_id);
4075             assert(status == VA_STATUS_SUCCESS);
4076             obj_surface = SURFACE(out_surface_id);
4077             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4078             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4079             src_surface.id = in_surface_id;
4080             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4081             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
4082                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
4083             dst_surface.id = out_surface_id;
4084             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4085             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4086
4087             i965_post_processing_internal(ctx, i965->pp_context,
4088                                           &src_surface,
4089                                           src_rect,
4090                                           &dst_surface,
4091                                           dst_rect,
4092                                           PP_NV12_DNDI,
4093                                           NULL);
4094         }
4095
4096         if (flags & I965_PP_FLAG_AVS) {
4097             struct i965_render_state *render_state = &i965->render_state;
4098             struct intel_region *dest_region = render_state->draw_region;
4099
4100             if (out_surface_id != VA_INVALID_ID)
4101                 in_surface_id = out_surface_id;
4102
4103             status = i965_CreateSurfaces(ctx,
4104                                          dest_region->width,
4105                                          dest_region->height,
4106                                          VA_RT_FORMAT_YUV420,
4107                                          1,
4108                                          &out_surface_id);
4109             assert(status == VA_STATUS_SUCCESS);
4110             obj_surface = SURFACE(out_surface_id);
4111             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4112             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4113             src_surface.id = in_surface_id;
4114             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4115             src_surface.flags = I965_SURFACE_FLAG_FRAME;
4116             dst_surface.id = out_surface_id;
4117             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4118             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4119
4120             i965_post_processing_internal(ctx, i965->pp_context,
4121                                           &src_surface,
4122                                           src_rect,
4123                                           &dst_surface,
4124                                           dst_rect,
4125                                           PP_NV12_AVS,
4126                                           NULL);
4127
4128             if (in_surface_id != surface)
4129                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4130
4131             *has_done_scaling = 1;
4132         }
4133
4134         _i965UnlockMutex(&i965->pp_mutex);
4135     }
4136
4137     return out_surface_id;
4138 }
4139
4140 static VAStatus
4141 i965_image_pl1_rgbx_processing(VADriverContextP ctx,
4142                           const struct i965_surface *src_surface,
4143                           const VARectangle *src_rect,
4144                           struct i965_surface *dst_surface,
4145                           const VARectangle *dst_rect)
4146 {
4147     struct i965_driver_data *i965 = i965_driver_data(ctx);
4148     struct i965_post_processing_context *pp_context = i965->pp_context;
4149     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4150
4151     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4152         i965_post_processing_internal(ctx, i965->pp_context,
4153                                       src_surface,
4154                                       src_rect,
4155                                       dst_surface,
4156                                       dst_rect,
4157                                       PP_RGBX_LOAD_SAVE_NV12,
4158                                       NULL);
4159     } else {
4160         assert(0);
4161         return VA_STATUS_ERROR_UNKNOWN;
4162     }
4163
4164     intel_batchbuffer_flush(pp_context->batch);
4165
4166     return VA_STATUS_SUCCESS;
4167 }
4168
4169 static VAStatus
4170 i965_image_pl3_processing(VADriverContextP ctx,
4171                           const struct i965_surface *src_surface,
4172                           const VARectangle *src_rect,
4173                           struct i965_surface *dst_surface,
4174                           const VARectangle *dst_rect)
4175 {
4176     struct i965_driver_data *i965 = i965_driver_data(ctx);
4177     struct i965_post_processing_context *pp_context = i965->pp_context;
4178     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4179     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4180
4181     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4182         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4183                                                  src_surface,
4184                                                  src_rect,
4185                                                  dst_surface,
4186                                                  dst_rect,
4187                                                  PP_PL3_LOAD_SAVE_N12,
4188                                                  NULL);
4189     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4190                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4191                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4192                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4193         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4194                                                  src_surface,
4195                                                  src_rect,
4196                                                  dst_surface,
4197                                                  dst_rect,
4198                                                  PP_PL3_LOAD_SAVE_PL3,
4199                                                  NULL);
4200     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4201                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4202         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4203                                                  src_surface,
4204                                                  src_rect,
4205                                                  dst_surface,
4206                                                  dst_rect,
4207                                                  PP_PL3_LOAD_SAVE_PA,
4208                                                  NULL);
4209     }
4210     else {
4211         assert(0);
4212     }
4213
4214     intel_batchbuffer_flush(pp_context->batch);
4215
4216     return vaStatus;
4217 }
4218
4219 static VAStatus
4220 i965_image_pl2_processing(VADriverContextP ctx,
4221                           const struct i965_surface *src_surface,
4222                           const VARectangle *src_rect,
4223                           struct i965_surface *dst_surface,
4224                           const VARectangle *dst_rect)
4225 {
4226     struct i965_driver_data *i965 = i965_driver_data(ctx);
4227     struct i965_post_processing_context *pp_context = i965->pp_context;
4228     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4229     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4230
4231     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4232         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4233                                                  src_surface,
4234                                                  src_rect,
4235                                                  dst_surface,
4236                                                  dst_rect,
4237                                                  PP_NV12_LOAD_SAVE_N12,
4238                                                  NULL);
4239     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4240                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4241                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4242                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4243         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4244                                                  src_surface,
4245                                                  src_rect,
4246                                                  dst_surface,
4247                                                  dst_rect,
4248                                                  PP_NV12_LOAD_SAVE_PL3,
4249                                                  NULL);
4250     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4251                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4252         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4253                                                  src_surface,
4254                                                  src_rect,
4255                                                  dst_surface,
4256                                                  dst_rect,
4257                                                  PP_NV12_LOAD_SAVE_PA,
4258                                                      NULL);
4259     } else if (fourcc == VA_FOURCC('B', 'G', 'R', 'X') ||
4260                fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
4261                fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
4262                fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) {
4263         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4264                                       src_surface,
4265                                       src_rect,
4266                                       dst_surface,
4267                                       dst_rect,
4268                                       PP_NV12_LOAD_SAVE_RGBX,
4269                                       NULL);
4270     } else {
4271         assert(0);
4272         return VA_STATUS_ERROR_UNKNOWN;
4273     }
4274
4275     intel_batchbuffer_flush(pp_context->batch);
4276
4277     return vaStatus;
4278 }
4279
4280 static VAStatus
4281 i965_image_pl1_processing(VADriverContextP ctx,
4282                           const struct i965_surface *src_surface,
4283                           const VARectangle *src_rect,
4284                           struct i965_surface *dst_surface,
4285                           const VARectangle *dst_rect)
4286 {
4287     struct i965_driver_data *i965 = i965_driver_data(ctx);
4288     struct i965_post_processing_context *pp_context = i965->pp_context;
4289     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4290
4291     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4292         i965_post_processing_internal(ctx, i965->pp_context,
4293                                       src_surface,
4294                                       src_rect,
4295                                       dst_surface,
4296                                       dst_rect,
4297                                       PP_PA_LOAD_SAVE_NV12,
4298                                       NULL);
4299     }
4300     else if (fourcc == VA_FOURCC_YV12) {
4301         i965_post_processing_internal(ctx, i965->pp_context,
4302                                       src_surface,
4303                                       src_rect,
4304                                       dst_surface,
4305                                       dst_rect,
4306                                       PP_PA_LOAD_SAVE_PL3,
4307                                       NULL);
4308
4309     }
4310     else {
4311         return VA_STATUS_ERROR_UNKNOWN;
4312     }
4313
4314     intel_batchbuffer_flush(pp_context->batch);
4315
4316     return VA_STATUS_SUCCESS;
4317 }
4318
4319 VAStatus
4320 i965_image_processing(VADriverContextP ctx,
4321                       const struct i965_surface *src_surface,
4322                       const VARectangle *src_rect,
4323                       struct i965_surface *dst_surface,
4324                       const VARectangle *dst_rect)
4325 {
4326     struct i965_driver_data *i965 = i965_driver_data(ctx);
4327     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4328
4329     if (HAS_PP(i965)) {
4330         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4331
4332         _i965LockMutex(&i965->pp_mutex);
4333
4334         switch (fourcc) {
4335         case VA_FOURCC('Y', 'V', '1', '2'):
4336         case VA_FOURCC('I', '4', '2', '0'):
4337         case VA_FOURCC('I', 'M', 'C', '1'):
4338         case VA_FOURCC('I', 'M', 'C', '3'):
4339             status = i965_image_pl3_processing(ctx,
4340                                                src_surface,
4341                                                src_rect,
4342                                                dst_surface,
4343                                                dst_rect);
4344             break;
4345
4346         case  VA_FOURCC('N', 'V', '1', '2'):
4347             status = i965_image_pl2_processing(ctx,
4348                                                src_surface,
4349                                                src_rect,
4350                                                dst_surface,
4351                                                dst_rect);
4352             break;
4353         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4354         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4355             status = i965_image_pl1_processing(ctx,
4356                                                src_surface,
4357                                                src_rect,
4358                                                dst_surface,
4359                                                dst_rect);
4360             break;
4361         case VA_FOURCC('B', 'G', 'R', 'A'):
4362         case VA_FOURCC('B', 'G', 'R', 'X'):
4363         case VA_FOURCC('R', 'G', 'B', 'A'):
4364         case VA_FOURCC('R', 'G', 'B', 'X'):
4365             status = i965_image_pl1_rgbx_processing(ctx,
4366                                                src_surface,
4367                                                src_rect,
4368                                                dst_surface,
4369                                                dst_rect);
4370             break;
4371         default:
4372             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4373             break;
4374         }
4375
4376         _i965UnlockMutex(&i965->pp_mutex);
4377     }
4378
4379     return status;
4380 }
4381
4382 static void
4383 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4384 {
4385     int i;
4386
4387     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4388     pp_context->surface_state_binding_table.bo = NULL;
4389
4390     dri_bo_unreference(pp_context->curbe.bo);
4391     pp_context->curbe.bo = NULL;
4392
4393     dri_bo_unreference(pp_context->sampler_state_table.bo);
4394     pp_context->sampler_state_table.bo = NULL;
4395
4396     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4397     pp_context->sampler_state_table.bo_8x8 = NULL;
4398
4399     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4400     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4401
4402     dri_bo_unreference(pp_context->idrt.bo);
4403     pp_context->idrt.bo = NULL;
4404     pp_context->idrt.num_interface_descriptors = 0;
4405
4406     dri_bo_unreference(pp_context->vfe_state.bo);
4407     pp_context->vfe_state.bo = NULL;
4408
4409     dri_bo_unreference(pp_context->stmm.bo);
4410     pp_context->stmm.bo = NULL;
4411
4412     for (i = 0; i < NUM_PP_MODULES; i++) {
4413         struct pp_module *pp_module = &pp_context->pp_modules[i];
4414
4415         dri_bo_unreference(pp_module->kernel.bo);
4416         pp_module->kernel.bo = NULL;
4417     }
4418
4419     free(pp_context->pp_static_parameter);
4420     free(pp_context->pp_inline_parameter);
4421     pp_context->pp_static_parameter = NULL;
4422     pp_context->pp_inline_parameter = NULL;
4423 }
4424
4425 Bool
4426 i965_post_processing_terminate(VADriverContextP ctx)
4427 {
4428     struct i965_driver_data *i965 = i965_driver_data(ctx);
4429     struct i965_post_processing_context *pp_context = i965->pp_context;
4430
4431     if (pp_context) {
4432         i965_post_processing_context_finalize(pp_context);
4433         free(pp_context);
4434     }
4435
4436     i965->pp_context = NULL;
4437
4438     return True;
4439 }
4440
4441 static void
4442 i965_post_processing_context_init(VADriverContextP ctx,
4443                                   struct i965_post_processing_context *pp_context,
4444                                   struct intel_batchbuffer *batch)
4445 {
4446     struct i965_driver_data *i965 = i965_driver_data(ctx);
4447     int i;
4448
4449     pp_context->urb.size = URB_SIZE((&i965->intel));
4450     pp_context->urb.num_vfe_entries = 32;
4451     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4452     pp_context->urb.num_cs_entries = 1;
4453
4454     if (IS_GEN7(i965->intel.device_id))
4455         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4456     else
4457         pp_context->urb.size_cs_entry = 2;
4458
4459     pp_context->urb.vfe_start = 0;
4460     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4461         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4462     assert(pp_context->urb.cs_start +
4463            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4464
4465     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4466     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4467     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4468
4469     if (IS_GEN7(i965->intel.device_id))
4470         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4471     else if (IS_GEN6(i965->intel.device_id))
4472         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4473     else if (IS_IRONLAKE(i965->intel.device_id))
4474         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4475
4476     for (i = 0; i < NUM_PP_MODULES; i++) {
4477         struct pp_module *pp_module = &pp_context->pp_modules[i];
4478         dri_bo_unreference(pp_module->kernel.bo);
4479         if (pp_module->kernel.bin && pp_module->kernel.size) {
4480             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4481                                                 pp_module->kernel.name,
4482                                                 pp_module->kernel.size,
4483                                                 4096);
4484             assert(pp_module->kernel.bo);
4485             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4486         } else {
4487             pp_module->kernel.bo = NULL;
4488         }
4489     }
4490
4491     /* static & inline parameters */
4492     if (IS_GEN7(i965->intel.device_id)) {
4493         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4494         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4495     } else {
4496         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4497         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4498     }
4499
4500     pp_context->batch = batch;
4501 }
4502
4503 Bool
4504 i965_post_processing_init(VADriverContextP ctx)
4505 {
4506     struct i965_driver_data *i965 = i965_driver_data(ctx);
4507     struct i965_post_processing_context *pp_context = i965->pp_context;
4508
4509     if (HAS_PP(i965)) {
4510         if (pp_context == NULL) {
4511             pp_context = calloc(1, sizeof(*pp_context));
4512             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4513             i965->pp_context = pp_context;
4514         }
4515     }
4516
4517     return True;
4518 }
4519
4520 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4521     PP_NULL,    /* VAProcFilterNone */
4522     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4523     PP_NULL,    /* VAProcFilterDeblocking */
4524     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4525     PP_NULL,    /* VAProcFilterSharpening */
4526     PP_NULL,    /* VAProcFilterColorBalance */
4527     PP_NULL,    /* VAProcFilterColorStandard */
4528     PP_NULL,    /* VAProcFilterFrameRateConversion */
4529 };
4530
4531 static const int proc_frame_to_pp_frame[3] = {
4532     I965_SURFACE_FLAG_FRAME,
4533     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4534     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4535 };
4536
4537 static void
4538 i965_proc_picture(VADriverContextP ctx,
4539                   VAProfile profile,
4540                   union codec_state *codec_state,
4541                   struct hw_context *hw_context)
4542 {
4543     struct i965_driver_data *i965 = i965_driver_data(ctx);
4544     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4545     struct proc_state *proc_state = &codec_state->proc;
4546     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4547     struct object_surface *obj_surface;
4548     struct i965_surface src_surface, dst_surface;
4549     VARectangle src_rect, dst_rect;
4550     VAStatus status;
4551     int i;
4552     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4553     int num_tmp_surfaces = 0;
4554     unsigned int tiling = 0, swizzle = 0;
4555     int in_width, in_height;
4556
4557     assert(pipeline_param->surface != VA_INVALID_ID);
4558     assert(proc_state->current_render_target != VA_INVALID_ID);
4559
4560     obj_surface = SURFACE(pipeline_param->surface);
4561     in_width = obj_surface->orig_width;
4562     in_height = obj_surface->orig_height;
4563     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4564
4565     src_surface.id = pipeline_param->surface;
4566     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4567     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4568
4569     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4570         VASurfaceID out_surface_id = VA_INVALID_ID;
4571
4572         src_surface.id = pipeline_param->surface;
4573         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4574         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4575         src_rect.x = 0;
4576         src_rect.y = 0;
4577         src_rect.width = in_width;
4578         src_rect.height = in_height;
4579
4580         status = i965_CreateSurfaces(ctx,
4581                                      in_width,
4582                                      in_height,
4583                                      VA_RT_FORMAT_YUV420,
4584                                      1,
4585                                      &out_surface_id);
4586         assert(status == VA_STATUS_SUCCESS);
4587         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4588         obj_surface = SURFACE(out_surface_id);
4589         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4590
4591         dst_surface.id = out_surface_id;
4592         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4593         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4594         dst_rect.x = 0;
4595         dst_rect.y = 0;
4596         dst_rect.width = in_width;
4597         dst_rect.height = in_height;
4598
4599         status = i965_image_processing(ctx,
4600                                        &src_surface,
4601                                        &src_rect,
4602                                        &dst_surface,
4603                                        &dst_rect);
4604         assert(status == VA_STATUS_SUCCESS);
4605
4606         src_surface.id = out_surface_id;
4607         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4608         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4609     }
4610
4611     if (pipeline_param->surface_region) {
4612         src_rect.x = pipeline_param->surface_region->x;
4613         src_rect.y = pipeline_param->surface_region->y;
4614         src_rect.width = pipeline_param->surface_region->width;
4615         src_rect.height = pipeline_param->surface_region->height;
4616     } else {
4617         src_rect.x = 0;
4618         src_rect.y = 0;
4619         src_rect.width = in_width;
4620         src_rect.height = in_height;
4621     }
4622
4623     if (pipeline_param->output_region) {
4624         dst_rect.x = pipeline_param->output_region->x;
4625         dst_rect.y = pipeline_param->output_region->y;
4626         dst_rect.width = pipeline_param->output_region->width;
4627         dst_rect.height = pipeline_param->output_region->height;
4628     } else {
4629         dst_rect.x = 0;
4630         dst_rect.y = 0;
4631         dst_rect.width = in_width;
4632         dst_rect.height = in_height;
4633     }
4634
4635     obj_surface = SURFACE(proc_state->current_render_target);
4636     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4637     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4638
4639     for (i = 0; i < pipeline_param->num_filters; i++) {
4640         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4641         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4642         VAProcFilterType filter_type = filter_param->type;
4643         VASurfaceID out_surface_id = VA_INVALID_ID;
4644         int kernel_index = procfilter_to_pp_flag[filter_type];
4645
4646         if (kernel_index != PP_NULL &&
4647             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4648             status = i965_CreateSurfaces(ctx,
4649                                          in_width,
4650                                          in_height,
4651                                          VA_RT_FORMAT_YUV420,
4652                                          1,
4653                                          &out_surface_id);
4654             assert(status == VA_STATUS_SUCCESS);
4655             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4656             obj_surface = SURFACE(out_surface_id);
4657             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4658             dst_surface.id = out_surface_id;
4659             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4660             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4661                                                    &src_surface,
4662                                                    &src_rect,
4663                                                    &dst_surface,
4664                                                    &src_rect,
4665                                                    kernel_index,
4666                                                    filter_param);
4667
4668             if (status == VA_STATUS_SUCCESS) {
4669                 src_surface.id = dst_surface.id;
4670                 src_surface.type = dst_surface.type;
4671                 src_surface.flags = dst_surface.flags;
4672             }
4673         }
4674     }
4675
4676     dst_surface.id = proc_state->current_render_target;
4677     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4678
4679     if (src_rect.width == dst_rect.width &&
4680         src_rect.height == dst_rect.height) {
4681         i965_post_processing_internal(ctx, &proc_context->pp_context,
4682                                       &src_surface,
4683                                       &src_rect,
4684                                       &dst_surface,
4685                                       &dst_rect,
4686                                       PP_NV12_LOAD_SAVE_N12,
4687                                       NULL);
4688     } else {
4689
4690         i965_post_processing_internal(ctx, &proc_context->pp_context,
4691                                       &src_surface,
4692                                       &src_rect,
4693                                       &dst_surface,
4694                                       &dst_rect,
4695                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4696                                       PP_NV12_AVS : PP_NV12_SCALING,
4697                                       NULL);
4698     }
4699
4700     if (num_tmp_surfaces)
4701         i965_DestroySurfaces(ctx,
4702                              tmp_surfaces,
4703                              num_tmp_surfaces);
4704
4705     intel_batchbuffer_flush(hw_context->batch);
4706 }
4707
4708 static void
4709 i965_proc_context_destroy(void *hw_context)
4710 {
4711     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4712
4713     i965_post_processing_context_finalize(&proc_context->pp_context);
4714     intel_batchbuffer_free(proc_context->base.batch);
4715     free(proc_context);
4716 }
4717
4718 struct hw_context *
4719 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4720 {
4721     struct intel_driver_data *intel = intel_driver_data(ctx);
4722     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4723
4724     proc_context->base.destroy = i965_proc_context_destroy;
4725     proc_context->base.run = i965_proc_picture;
4726     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4727     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4728
4729     return (struct hw_context *)proc_context;
4730 }