src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  95                                    const struct i965_surface *src_surface,
  96                                    const VARectangle *src_rect,
  97                                    struct i965_surface *dst_surface,
  98                                    const VARectangle *dst_rect,
  99                                    void *filter_param);
 100 static VAStatus pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 101                                        const struct i965_surface *src_surface,
 102                                        const VARectangle *src_rect,
 103                                        struct i965_surface *dst_surface,
 104                                        const VARectangle *dst_rect,
 105                                        void *filter_param);
 106 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 107                                            const struct i965_surface *src_surface,
 108                                            const VARectangle *src_rect,
 109                                            struct i965_surface *dst_surface,
 110                                            const VARectangle *dst_rect,
 111                                            void *filter_param);
 112 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 113                                                 const struct i965_surface *src_surface,
 114                                                 const VARectangle *src_rect,
 115                                                 struct i965_surface *dst_surface,
 116                                                 const VARectangle *dst_rect,
 117                                                 void *filter_param);
 118 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                         const struct i965_surface *src_surface,
 120                                         const VARectangle *src_rect,
 121                                         struct i965_surface *dst_surface,
 122                                         const VARectangle *dst_rect,
 123                                         void *filter_param);
 124 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                       const struct i965_surface *src_surface,
 126                                       const VARectangle *src_rect,
 127                                       struct i965_surface *dst_surface,
 128                                       const VARectangle *dst_rect,
 129                                       void *filter_param);
 130
 131 static struct pp_module pp_modules_gen5[] = {
 132     {
 133         {
 134             "NULL module (for testing)",
 135             PP_NULL,
 136             pp_null_gen5,
 137             sizeof(pp_null_gen5),
 138             NULL,
 139         },
 140
 141         pp_null_initialize,
 142     },
 143
 144     {
 145         {
 146             "NV12_NV12",
 147             PP_NV12_LOAD_SAVE_N12,
 148             pp_nv12_load_save_nv12_gen5,
 149             sizeof(pp_nv12_load_save_nv12_gen5),
 150             NULL,
 151         },
 152
 153         pp_plx_load_save_plx_initialize,
 154     },
 155
 156     {
 157         {
 158             "NV12_PL3",
 159             PP_NV12_LOAD_SAVE_PL3,
 160             pp_nv12_load_save_pl3_gen5,
 161             sizeof(pp_nv12_load_save_pl3_gen5),
 162             NULL,
 163         },
 164
 165         pp_plx_load_save_plx_initialize,
 166     },
 167
 168     {
 169         {
 170             "PL3_NV12",
 171             PP_PL3_LOAD_SAVE_N12,
 172             pp_pl3_load_save_nv12_gen5,
 173             sizeof(pp_pl3_load_save_nv12_gen5),
 174             NULL,
 175         },
 176
 177         pp_plx_load_save_plx_initialize,
 178     },
 179
 180     {
 181         {
 182             "PL3_PL3",
 183             PP_PL3_LOAD_SAVE_N12,
 184             pp_pl3_load_save_pl3_gen5,
 185             sizeof(pp_pl3_load_save_pl3_gen5),
 186             NULL,
 187         },
 188
 189         pp_plx_load_save_plx_initialize
 190     },
 191
 192     {
 193         {
 194             "NV12 Scaling module",
 195             PP_NV12_SCALING,
 196             pp_nv12_scaling_gen5,
 197             sizeof(pp_nv12_scaling_gen5),
 198             NULL,
 199         },
 200
 201         pp_nv12_scaling_initialize,
 202     },
 203
 204     {
 205         {
 206             "NV12 AVS module",
 207             PP_NV12_AVS,
 208             pp_nv12_avs_gen5,
 209             sizeof(pp_nv12_avs_gen5),
 210             NULL,
 211         },
 212
 213         pp_nv12_avs_initialize,
 214     },
 215
 216     {
 217         {
 218             "NV12 DNDI module",
 219             PP_NV12_DNDI,
 220             pp_nv12_dndi_gen5,
 221             sizeof(pp_nv12_dndi_gen5),
 222             NULL,
 223         },
 224
 225         pp_nv12_dndi_initialize,
 226     },
 227
 228     {
 229         {
 230             "NV12 DN module",
 231             PP_NV12_DN,
 232             pp_nv12_dn_gen5,
 233             sizeof(pp_nv12_dn_gen5),
 234             NULL,
 235         },
 236
 237         pp_nv12_dn_initialize,
 238     },
 239 };
 240
 241 static const uint32_t pp_null_gen6[][4] = {
 242 #include "shaders/post_processing/gen5_6/null.g6b"
 243 };
 244
 245 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 246 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 247 };
 248
 249 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 250 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 251 };
 252
 253 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 254 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 255 };
 256
 257 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 258 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 259 };
 260
 261 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 262 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g6b"
 263 };
 264
 265 static const uint32_t pp_nv12_avs_gen6[][4] = {
 266 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 267 };
 268
 269 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 270 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 271 };
 272
 273 static const uint32_t pp_nv12_dn_gen6[][4] = {
 274 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 275 };
 276
 277 static struct pp_module pp_modules_gen6[] = {
 278     {
 279         {
 280             "NULL module (for testing)",
 281             PP_NULL,
 282             pp_null_gen6,
 283             sizeof(pp_null_gen6),
 284             NULL,
 285         },
 286
 287         pp_null_initialize,
 288     },
 289
 290     {
 291         {
 292             "NV12_NV12",
 293             PP_NV12_LOAD_SAVE_N12,
 294             pp_nv12_load_save_nv12_gen6,
 295             sizeof(pp_nv12_load_save_nv12_gen6),
 296             NULL,
 297         },
 298
 299         pp_plx_load_save_plx_initialize,
 300     },
 301
 302     {
 303         {
 304             "NV12_PL3",
 305             PP_NV12_LOAD_SAVE_PL3,
 306             pp_nv12_load_save_pl3_gen6,
 307             sizeof(pp_nv12_load_save_pl3_gen6),
 308             NULL,
 309         },
 310
 311         pp_plx_load_save_plx_initialize,
 312     },
 313
 314     {
 315         {
 316             "PL3_NV12",
 317             PP_PL3_LOAD_SAVE_N12,
 318             pp_pl3_load_save_nv12_gen6,
 319             sizeof(pp_pl3_load_save_nv12_gen6),
 320             NULL,
 321         },
 322
 323         pp_plx_load_save_plx_initialize,
 324     },
 325
 326     {
 327         {
 328             "PL3_PL3",
 329             PP_PL3_LOAD_SAVE_N12,
 330             pp_pl3_load_save_pl3_gen6,
 331             sizeof(pp_pl3_load_save_pl3_gen6),
 332             NULL,
 333         },
 334
 335         pp_plx_load_save_plx_initialize,
 336     },
 337
 338     {
 339         {
 340             "NV12 Scaling module",
 341             PP_NV12_SCALING,
 342             pp_nv12_scaling_gen6,
 343             sizeof(pp_nv12_scaling_gen6),
 344             NULL,
 345         },
 346
 347         pp_nv12_scaling_initialize,
 348     },
 349
 350     {
 351         {
 352             "NV12 AVS module",
 353             PP_NV12_AVS,
 354             pp_nv12_avs_gen6,
 355             sizeof(pp_nv12_avs_gen6),
 356             NULL,
 357         },
 358
 359         pp_nv12_avs_initialize,
 360     },
 361
 362     {
 363         {
 364             "NV12 DNDI module",
 365             PP_NV12_DNDI,
 366             pp_nv12_dndi_gen6,
 367             sizeof(pp_nv12_dndi_gen6),
 368             NULL,
 369         },
 370
 371         pp_nv12_dndi_initialize,
 372     },
 373
 374     {
 375         {
 376             "NV12 DN module",
 377             PP_NV12_DN,
 378             pp_nv12_dn_gen6,
 379             sizeof(pp_nv12_dn_gen6),
 380             NULL,
 381         },
 382
 383         pp_nv12_dn_initialize,
 384     },
 385 };
 386
 387 static const uint32_t pp_null_gen7[][4] = {
 388 };
 389
 390 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 391 };
 392
 393 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 394 };
 395
 396 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 397 };
 398
 399 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 400 };
 401
 402 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 403 #include "shaders/post_processing/gen7/avs.g7b"
 404 };
 405
 406 static const uint32_t pp_nv12_avs_gen7[][4] = {
 407 #include "shaders/post_processing/gen7/avs.g7b"
 408 };
 409
 410 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 411 #include "shaders/post_processing/gen7/dndi.g7b"
 412 };
 413
 414 static const uint32_t pp_nv12_dn_gen7[][4] = {
 415 };
 416
 417 static VAStatus gen7_pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 418                                             const struct i965_surface *src_surface,
 419                                             const VARectangle *src_rect,
 420                                             struct i965_surface *dst_surface,
 421                                             const VARectangle *dst_rect,
 422                                             void *filter_param);
 423 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 424                                              const struct i965_surface *src_surface,
 425                                              const VARectangle *src_rect,
 426                                              struct i965_surface *dst_surface,
 427                                              const VARectangle *dst_rect,
 428                                              void *filter_param);
 429 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 430                                            const struct i965_surface *src_surface,
 431                                            const VARectangle *src_rect,
 432                                            struct i965_surface *dst_surface,
 433                                            const VARectangle *dst_rect,
 434                                            void *filter_param);
 435
 436 static struct pp_module pp_modules_gen7[] = {
 437     {
 438         {
 439             "NULL module (for testing)",
 440             PP_NULL,
 441             pp_null_gen7,
 442             sizeof(pp_null_gen7),
 443             NULL,
 444         },
 445
 446         pp_null_initialize,
 447     },
 448
 449     {
 450         {
 451             "NV12_NV12",
 452             PP_NV12_LOAD_SAVE_N12,
 453             pp_nv12_load_save_nv12_gen7,
 454             sizeof(pp_nv12_load_save_nv12_gen7),
 455             NULL,
 456         },
 457
 458         pp_plx_load_save_plx_initialize,
 459     },
 460
 461     {
 462         {
 463             "NV12_PL3",
 464             PP_NV12_LOAD_SAVE_PL3,
 465             pp_nv12_load_save_pl3_gen7,
 466             sizeof(pp_nv12_load_save_pl3_gen7),
 467             NULL,
 468         },
 469
 470         pp_plx_load_save_plx_initialize,
 471     },
 472
 473     {
 474         {
 475             "PL3_NV12",
 476             PP_PL3_LOAD_SAVE_N12,
 477             pp_pl3_load_save_nv12_gen7,
 478             sizeof(pp_pl3_load_save_nv12_gen7),
 479             NULL,
 480         },
 481
 482         pp_plx_load_save_plx_initialize,
 483     },
 484
 485     {
 486         {
 487             "PL3_PL3",
 488             PP_PL3_LOAD_SAVE_N12,
 489             pp_pl3_load_save_pl3_gen7,
 490             sizeof(pp_pl3_load_save_pl3_gen7),
 491             NULL,
 492         },
 493
 494         pp_plx_load_save_plx_initialize,
 495     },
 496
 497     {
 498         {
 499             "NV12 Scaling module",
 500             PP_NV12_SCALING,
 501             pp_nv12_scaling_gen7,
 502             sizeof(pp_nv12_scaling_gen7),
 503             NULL,
 504         },
 505
 506         gen7_pp_nv12_avs_initialize,
 507     },
 508
 509     {
 510         {
 511             "NV12 AVS module",
 512             PP_NV12_AVS,
 513             pp_nv12_avs_gen7,
 514             sizeof(pp_nv12_avs_gen7),
 515             NULL,
 516         },
 517
 518         gen7_pp_nv12_avs_initialize,
 519     },
 520
 521     {
 522         {
 523             "NV12 DNDI module",
 524             PP_NV12_DNDI,
 525             pp_nv12_dndi_gen7,
 526             sizeof(pp_nv12_dndi_gen7),
 527             NULL,
 528         },
 529
 530         gen7_pp_nv12_dndi_initialize,
 531     },
 532
 533     {
 534         {
 535             "NV12 DN module",
 536             PP_NV12_DN,
 537             pp_nv12_dn_gen7,
 538             sizeof(pp_nv12_dn_gen7),
 539             NULL,
 540         },
 541
 542         gen7_pp_nv12_dn_initialize,
 543     },
 544 };
 545
 546 static int
 547 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 548 {
 549     struct i965_driver_data *i965 = i965_driver_data(ctx);
 550     int fourcc;
 551
 552     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 553         struct object_image *obj_image = IMAGE(surface->id);
 554         fourcc = obj_image->image.format.fourcc;
 555     } else {
 556         struct object_surface *obj_surface = SURFACE(surface->id);
 557         fourcc = obj_surface->fourcc;
 558     }
 559
 560     return fourcc;
 561 }
 562
 563 static void
 564 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 565 {
 566     switch (tiling) {
 567     case I915_TILING_NONE:
 568         ss->ss3.tiled_surface = 0;
 569         ss->ss3.tile_walk = 0;
 570         break;
 571     case I915_TILING_X:
 572         ss->ss3.tiled_surface = 1;
 573         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 574         break;
 575     case I915_TILING_Y:
 576         ss->ss3.tiled_surface = 1;
 577         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 578         break;
 579     }
 580 }
 581
 582 static void
 583 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 584 {
 585     switch (tiling) {
 586     case I915_TILING_NONE:
 587         ss->ss2.tiled_surface = 0;
 588         ss->ss2.tile_walk = 0;
 589         break;
 590     case I915_TILING_X:
 591         ss->ss2.tiled_surface = 1;
 592         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 593         break;
 594     case I915_TILING_Y:
 595         ss->ss2.tiled_surface = 1;
 596         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 597         break;
 598     }
 599 }
 600
 601 static void
 602 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 603 {
 604     switch (tiling) {
 605     case I915_TILING_NONE:
 606         ss->ss0.tiled_surface = 0;
 607         ss->ss0.tile_walk = 0;
 608         break;
 609     case I915_TILING_X:
 610         ss->ss0.tiled_surface = 1;
 611         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 612         break;
 613     case I915_TILING_Y:
 614         ss->ss0.tiled_surface = 1;
 615         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 616         break;
 617     }
 618 }
 619
 620 static void
 621 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 622 {
 623     switch (tiling) {
 624     case I915_TILING_NONE:
 625         ss->ss2.tiled_surface = 0;
 626         ss->ss2.tile_walk = 0;
 627         break;
 628     case I915_TILING_X:
 629         ss->ss2.tiled_surface = 1;
 630         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 631         break;
 632     case I915_TILING_Y:
 633         ss->ss2.tiled_surface = 1;
 634         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 635         break;
 636     }
 637 }
 638
 639 static void
 640 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 641 {
 642     struct i965_interface_descriptor *desc;
 643     dri_bo *bo;
 644     int pp_index = pp_context->current_pp;
 645
 646     bo = pp_context->idrt.bo;
 647     dri_bo_map(bo, 1);
 648     assert(bo->virtual);
 649     desc = bo->virtual;
 650     memset(desc, 0, sizeof(*desc));
 651     desc->desc0.grf_reg_blocks = 10;
 652     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 653     desc->desc1.const_urb_entry_read_offset = 0;
 654     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 655     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 656     desc->desc2.sampler_count = 0;
 657     desc->desc3.binding_table_entry_count = 0;
 658     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 659
 660     dri_bo_emit_reloc(bo,
 661                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 662                       desc->desc0.grf_reg_blocks,
 663                       offsetof(struct i965_interface_descriptor, desc0),
 664                       pp_context->pp_modules[pp_index].kernel.bo);
 665
 666     dri_bo_emit_reloc(bo,
 667                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 668                       desc->desc2.sampler_count << 2,
 669                       offsetof(struct i965_interface_descriptor, desc2),
 670                       pp_context->sampler_state_table.bo);
 671
 672     dri_bo_unmap(bo);
 673     pp_context->idrt.num_interface_descriptors++;
 674 }
 675
 676 static void
 677 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 678 {
 679     struct i965_vfe_state *vfe_state;
 680     dri_bo *bo;
 681
 682     bo = pp_context->vfe_state.bo;
 683     dri_bo_map(bo, 1);
 684     assert(bo->virtual);
 685     vfe_state = bo->virtual;
 686     memset(vfe_state, 0, sizeof(*vfe_state));
 687     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 688     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 689     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 690     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 691     vfe_state->vfe1.children_present = 0;
 692     vfe_state->vfe2.interface_descriptor_base =
 693         pp_context->idrt.bo->offset >> 4; /* reloc */
 694     dri_bo_emit_reloc(bo,
 695                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 696                       0,
 697                       offsetof(struct i965_vfe_state, vfe2),
 698                       pp_context->idrt.bo);
 699     dri_bo_unmap(bo);
 700 }
 701
 702 static void
 703 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 704 {
 705     unsigned char *constant_buffer;
 706     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 707
 708     assert(sizeof(*pp_static_parameter) == 128);
 709     dri_bo_map(pp_context->curbe.bo, 1);
 710     assert(pp_context->curbe.bo->virtual);
 711     constant_buffer = pp_context->curbe.bo->virtual;
 712     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 713     dri_bo_unmap(pp_context->curbe.bo);
 714 }
 715
 716 static void
 717 ironlake_pp_states_setup(VADriverContextP ctx,
 718                          struct i965_post_processing_context *pp_context)
 719 {
 720     ironlake_pp_interface_descriptor_table(pp_context);
 721     ironlake_pp_vfe_state(pp_context);
 722     ironlake_pp_upload_constants(pp_context);
 723 }
 724
 725 static void
 726 ironlake_pp_pipeline_select(VADriverContextP ctx,
 727                             struct i965_post_processing_context *pp_context)
 728 {
 729     struct intel_batchbuffer *batch = pp_context->batch;
 730
 731     BEGIN_BATCH(batch, 1);
 732     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 733     ADVANCE_BATCH(batch);
 734 }
 735
 736 static void
 737 ironlake_pp_urb_layout(VADriverContextP ctx,
 738                        struct i965_post_processing_context *pp_context)
 739 {
 740     struct intel_batchbuffer *batch = pp_context->batch;
 741     unsigned int vfe_fence, cs_fence;
 742
 743     vfe_fence = pp_context->urb.cs_start;
 744     cs_fence = pp_context->urb.size;
 745
 746     BEGIN_BATCH(batch, 3);
 747     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 748     OUT_BATCH(batch, 0);
 749     OUT_BATCH(batch,
 750               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 751               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 752     ADVANCE_BATCH(batch);
 753 }
 754
 755 static void
 756 ironlake_pp_state_base_address(VADriverContextP ctx,
 757                                struct i965_post_processing_context *pp_context)
 758 {
 759     struct intel_batchbuffer *batch = pp_context->batch;
 760
 761     BEGIN_BATCH(batch, 8);
 762     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 763     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 764     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 765     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 766     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 767     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 768     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 769     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 770     ADVANCE_BATCH(batch);
 771 }
 772
 773 static void
 774 ironlake_pp_state_pointers(VADriverContextP ctx,
 775                            struct i965_post_processing_context *pp_context)
 776 {
 777     struct intel_batchbuffer *batch = pp_context->batch;
 778
 779     BEGIN_BATCH(batch, 3);
 780     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 781     OUT_BATCH(batch, 0);
 782     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 783     ADVANCE_BATCH(batch);
 784 }
 785
 786 static void
 787 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 788                           struct i965_post_processing_context *pp_context)
 789 {
 790     struct intel_batchbuffer *batch = pp_context->batch;
 791
 792     BEGIN_BATCH(batch, 2);
 793     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 794     OUT_BATCH(batch,
 795               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 796               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 797     ADVANCE_BATCH(batch);
 798 }
 799
 800 static void
 801 ironlake_pp_constant_buffer(VADriverContextP ctx,
 802                             struct i965_post_processing_context *pp_context)
 803 {
 804     struct intel_batchbuffer *batch = pp_context->batch;
 805
 806     BEGIN_BATCH(batch, 2);
 807     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 808     OUT_RELOC(batch, pp_context->curbe.bo,
 809               I915_GEM_DOMAIN_INSTRUCTION, 0,
 810               pp_context->urb.size_cs_entry - 1);
 811     ADVANCE_BATCH(batch);
 812 }
 813
 814 static void
 815 ironlake_pp_object_walker(VADriverContextP ctx,
 816                           struct i965_post_processing_context *pp_context)
 817 {
 818     struct intel_batchbuffer *batch = pp_context->batch;
 819     int x, x_steps, y, y_steps;
 820     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
 821
 822     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
 823     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
 824
 825     for (y = 0; y < y_steps; y++) {
 826         for (x = 0; x < x_steps; x++) {
 827             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
 828                 BEGIN_BATCH(batch, 20);
 829                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
 830                 OUT_BATCH(batch, 0);
 831                 OUT_BATCH(batch, 0); /* no indirect data */
 832                 OUT_BATCH(batch, 0);
 833
 834                 /* inline data grf 5-6 */
 835                 assert(sizeof(*pp_inline_parameter) == 64);
 836                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
 837
 838                 ADVANCE_BATCH(batch);
 839             }
 840         }
 841     }
 842 }
 843
 844 static void
 845 ironlake_pp_pipeline_setup(VADriverContextP ctx,
 846                            struct i965_post_processing_context *pp_context)
 847 {
 848     struct intel_batchbuffer *batch = pp_context->batch;
 849
 850     intel_batchbuffer_start_atomic(batch, 0x1000);
 851     intel_batchbuffer_emit_mi_flush(batch);
 852     ironlake_pp_pipeline_select(ctx, pp_context);
 853     ironlake_pp_state_base_address(ctx, pp_context);
 854     ironlake_pp_state_pointers(ctx, pp_context);
 855     ironlake_pp_urb_layout(ctx, pp_context);
 856     ironlake_pp_cs_urb_layout(ctx, pp_context);
 857     ironlake_pp_constant_buffer(ctx, pp_context);
 858     ironlake_pp_object_walker(ctx, pp_context);
 859     intel_batchbuffer_end_atomic(batch);
 860 }
 861
 862 static void
 863 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 864                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 865                           int width, int height, int pitch, int format,
 866                           int index, int is_target)
 867 {
 868     struct i965_surface_state *ss;
 869     dri_bo *ss_bo;
 870     unsigned int tiling;
 871     unsigned int swizzle;
 872
 873     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 874     ss_bo = pp_context->surface_state_binding_table.bo;
 875     assert(ss_bo);
 876
 877     dri_bo_map(ss_bo, True);
 878     assert(ss_bo->virtual);
 879     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 880     memset(ss, 0, sizeof(*ss));
 881     ss->ss0.surface_type = I965_SURFACE_2D;
 882     ss->ss0.surface_format = format;
 883     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 884     ss->ss2.width = width - 1;
 885     ss->ss2.height = height - 1;
 886     ss->ss3.pitch = pitch - 1;
 887     pp_set_surface_tiling(ss, tiling);
 888     dri_bo_emit_reloc(ss_bo,
 889                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 890                       surf_bo_offset,
 891                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 892                       surf_bo);
 893     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 894     dri_bo_unmap(ss_bo);
 895 }
 896
 897 static void
 898 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 899                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 900                            int width, int height, int wpitch,
 901                            int xoffset, int yoffset,
 902                            int format, int interleave_chroma,
 903                            int index)
 904 {
 905     struct i965_surface_state2 *ss2;
 906     dri_bo *ss2_bo;
 907     unsigned int tiling;
 908     unsigned int swizzle;
 909
 910     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 911     ss2_bo = pp_context->surface_state_binding_table.bo;
 912     assert(ss2_bo);
 913
 914     dri_bo_map(ss2_bo, True);
 915     assert(ss2_bo->virtual);
 916     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 917     memset(ss2, 0, sizeof(*ss2));
 918     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 919     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 920     ss2->ss1.width = width - 1;
 921     ss2->ss1.height = height - 1;
 922     ss2->ss2.pitch = wpitch - 1;
 923     ss2->ss2.interleave_chroma = interleave_chroma;
 924     ss2->ss2.surface_format = format;
 925     ss2->ss3.x_offset_for_cb = xoffset;
 926     ss2->ss3.y_offset_for_cb = yoffset;
 927     pp_set_surface2_tiling(ss2, tiling);
 928     dri_bo_emit_reloc(ss2_bo,
 929                       I915_GEM_DOMAIN_RENDER, 0,
 930                       surf_bo_offset,
 931                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
 932                       surf_bo);
 933     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 934     dri_bo_unmap(ss2_bo);
 935 }
 936
 937 static void
 938 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 939                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 940                           int width, int height, int pitch, int format,
 941                           int index, int is_target)
 942 {
 943     struct gen7_surface_state *ss;
 944     dri_bo *ss_bo;
 945     unsigned int tiling;
 946     unsigned int swizzle;
 947
 948     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 949     ss_bo = pp_context->surface_state_binding_table.bo;
 950     assert(ss_bo);
 951
 952     dri_bo_map(ss_bo, True);
 953     assert(ss_bo->virtual);
 954     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 955     memset(ss, 0, sizeof(*ss));
 956     ss->ss0.surface_type = I965_SURFACE_2D;
 957     ss->ss0.surface_format = format;
 958     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 959     ss->ss2.width = width - 1;
 960     ss->ss2.height = height - 1;
 961     ss->ss3.pitch = pitch - 1;
 962     gen7_pp_set_surface_tiling(ss, tiling);
 963     dri_bo_emit_reloc(ss_bo,
 964                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 965                       surf_bo_offset,
 966                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 967                       surf_bo);
 968     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 969     dri_bo_unmap(ss_bo);
 970 }
 971
 972 static void
 973 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 974                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 975                            int width, int height, int wpitch,
 976                            int xoffset, int yoffset,
 977                            int format, int interleave_chroma,
 978                            int index)
 979 {
 980     struct gen7_surface_state2 *ss2;
 981     dri_bo *ss2_bo;
 982     unsigned int tiling;
 983     unsigned int swizzle;
 984
 985     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 986     ss2_bo = pp_context->surface_state_binding_table.bo;
 987     assert(ss2_bo);
 988
 989     dri_bo_map(ss2_bo, True);
 990     assert(ss2_bo->virtual);
 991     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 992     memset(ss2, 0, sizeof(*ss2));
 993     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 994     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 995     ss2->ss1.width = width - 1;
 996     ss2->ss1.height = height - 1;
 997     ss2->ss2.pitch = wpitch - 1;
 998     ss2->ss2.interleave_chroma = interleave_chroma;
 999     ss2->ss2.surface_format = format;
1000     ss2->ss3.x_offset_for_cb = xoffset;
1001     ss2->ss3.y_offset_for_cb = yoffset;
1002     gen7_pp_set_surface2_tiling(ss2, tiling);
1003     dri_bo_emit_reloc(ss2_bo,
1004                       I915_GEM_DOMAIN_RENDER, 0,
1005                       surf_bo_offset,
1006                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1007                       surf_bo);
1008     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1009     dri_bo_unmap(ss2_bo);
1010 }
1011
1012 static void
1013 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1014                                 const struct i965_surface *surface,
1015                                 int base_index, int is_target,
1016                                 int *width, int *height, int *pitch, int *offset)
1017 {
1018     struct i965_driver_data *i965 = i965_driver_data(ctx);
1019     struct object_surface *obj_surface;
1020     struct object_image *obj_image;
1021     dri_bo *bo;
1022     int fourcc = pp_get_surface_fourcc(ctx, surface);
1023     const int Y = 0;
1024     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1025     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1026     const int UV = 1;
1027     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1028
1029     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1030         obj_surface = SURFACE(surface->id);
1031         bo = obj_surface->bo;
1032         width[0] = obj_surface->orig_width;
1033         height[0] = obj_surface->orig_height;
1034         pitch[0] = obj_surface->width;
1035         offset[0] = 0;
1036
1037         if (interleaved_uv) {
1038             width[1] = obj_surface->orig_width;
1039             height[1] = obj_surface->orig_height / 2;
1040             pitch[1] = obj_surface->width;
1041             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1042         } else {
1043             width[1] = obj_surface->orig_width / 2;
1044             height[1] = obj_surface->orig_height / 2;
1045             pitch[1] = obj_surface->width / 2;
1046             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1047             width[2] = obj_surface->orig_width / 2;
1048             height[2] = obj_surface->orig_height / 2;
1049             pitch[2] = obj_surface->width / 2;
1050             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1051         }
1052     } else {
1053         obj_image = IMAGE(surface->id);
1054         bo = obj_image->bo;
1055         width[0] = obj_image->image.width;
1056         height[0] = obj_image->image.height;
1057         pitch[0] = obj_image->image.pitches[0];
1058         offset[0] = obj_image->image.offsets[0];
1059
1060         if (interleaved_uv) {
1061             width[1] = obj_image->image.width;
1062             height[1] = obj_image->image.height / 2;
1063             pitch[1] = obj_image->image.pitches[1];
1064             offset[1] = obj_image->image.offsets[1];
1065         } else {
1066             width[1] = obj_image->image.width / 2;
1067             height[1] = obj_image->image.height / 2;
1068             pitch[1] = obj_image->image.pitches[1];
1069             offset[1] = obj_image->image.offsets[1];
1070             width[2] = obj_image->image.width / 2;
1071             height[2] = obj_image->image.height / 2;
1072             pitch[2] = obj_image->image.pitches[2];
1073             offset[2] = obj_image->image.offsets[2];
1074         }
1075     }
1076
1077     /* Y surface */
1078     i965_pp_set_surface_state(ctx, pp_context,
1079                               bo, offset[Y],
1080                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1081                               base_index, is_target);
1082
1083     if (interleaved_uv) {
1084         i965_pp_set_surface_state(ctx, pp_context,
1085                                   bo, offset[UV],
1086                                   width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1087                                   base_index + 1, is_target);
1088     } else {
1089         /* U surface */
1090         i965_pp_set_surface_state(ctx, pp_context,
1091                                   bo, offset[U],
1092                                   width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1093                                   base_index + 1, is_target);
1094
1095         /* V surface */
1096         i965_pp_set_surface_state(ctx, pp_context,
1097                                   bo, offset[V],
1098                                   width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1099                                   base_index + 2, is_target);
1100     }
1101
1102 }
1103
1104 static int
1105 pp_null_x_steps(void *private_context)
1106 {
1107     return 1;
1108 }
1109
1110 static int
1111 pp_null_y_steps(void *private_context)
1112 {
1113     return 1;
1114 }
1115
1116 static int
1117 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1118 {
1119     return 0;
1120 }
1121
1122 static VAStatus
1123 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1124                    const struct i965_surface *src_surface,
1125                    const VARectangle *src_rect,
1126                    struct i965_surface *dst_surface,
1127                    const VARectangle *dst_rect,
1128                    void *filter_param)
1129 {
1130     /* private function & data */
1131     pp_context->pp_x_steps = pp_null_x_steps;
1132     pp_context->pp_y_steps = pp_null_y_steps;
1133     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1134
1135     dst_surface->flags = src_surface->flags;
1136
1137     return VA_STATUS_SUCCESS;
1138 }
1139
1140 static int
1141 pp_load_save_x_steps(void *private_context)
1142 {
1143     return 1;
1144 }
1145
1146 static int
1147 pp_load_save_y_steps(void *private_context)
1148 {
1149     struct pp_load_save_context *pp_load_save_context = private_context;
1150
1151     return pp_load_save_context->dest_h / 8;
1152 }
1153
1154 static int
1155 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1156 {
1157     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1158
1159     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1160     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1161     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1162     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1163
1164     return 0;
1165 }
1166
1167 static VAStatus
1168 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1169                                 const struct i965_surface *src_surface,
1170                                 const VARectangle *src_rect,
1171                                 struct i965_surface *dst_surface,
1172                                 const VARectangle *dst_rect,
1173                                 void *filter_param)
1174 {
1175     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1176     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1177     int width[3], height[3], pitch[3], offset[3];
1178     const int Y = 0;
1179
1180     /* source surface */
1181     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1182                                     width, height, pitch, offset);
1183
1184     /* destination surface */
1185     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1186                                     width, height, pitch, offset);
1187
1188     /* private function & data */
1189     pp_context->pp_x_steps = pp_load_save_x_steps;
1190     pp_context->pp_y_steps = pp_load_save_y_steps;
1191     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1192     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1193     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1194
1195     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1196     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1197
1198     dst_surface->flags = src_surface->flags;
1199
1200     return VA_STATUS_SUCCESS;
1201 }
1202
1203 static int
1204 pp_scaling_x_steps(void *private_context)
1205 {
1206     return 1;
1207 }
1208
1209 static int
1210 pp_scaling_y_steps(void *private_context)
1211 {
1212     struct pp_scaling_context *pp_scaling_context = private_context;
1213
1214     return pp_scaling_context->dest_h / 8;
1215 }
1216
1217 static int
1218 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1219 {
1220     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1221     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1222     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1223     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1224     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1225
1226     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1227     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1228     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1229     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1230
1231     return 0;
1232 }
1233
1234 static VAStatus
1235 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1236                            const struct i965_surface *src_surface,
1237                            const VARectangle *src_rect,
1238                            struct i965_surface *dst_surface,
1239                            const VARectangle *dst_rect,
1240                            void *filter_param)
1241 {
1242     struct i965_driver_data *i965 = i965_driver_data(ctx);
1243     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1244     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1245     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1246     struct object_surface *obj_surface;
1247     struct i965_sampler_state *sampler_state;
1248     int in_w, in_h, in_wpitch, in_hpitch;
1249     int out_w, out_h, out_wpitch, out_hpitch;
1250
1251     /* source surface */
1252     obj_surface = SURFACE(src_surface->id);
1253     in_w = obj_surface->orig_width;
1254     in_h = obj_surface->orig_height;
1255     in_wpitch = obj_surface->width;
1256     in_hpitch = obj_surface->height;
1257
1258     /* source Y surface index 1 */
1259     i965_pp_set_surface_state(ctx, pp_context,
1260                               obj_surface->bo, 0,
1261                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1262                               1, 0);
1263
1264     /* source UV surface index 2 */
1265     i965_pp_set_surface_state(ctx, pp_context,
1266                               obj_surface->bo, in_wpitch * in_hpitch,
1267                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1268                               2, 0);
1269
1270     /* destination surface */
1271     obj_surface = SURFACE(dst_surface->id);
1272     out_w = obj_surface->orig_width;
1273     out_h = obj_surface->orig_height;
1274     out_wpitch = obj_surface->width;
1275     out_hpitch = obj_surface->height;
1276
1277     /* destination Y surface index 7 */
1278     i965_pp_set_surface_state(ctx, pp_context,
1279                               obj_surface->bo, 0,
1280                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1281                               7, 1);
1282
1283     /* destination UV surface index 8 */
1284     i965_pp_set_surface_state(ctx, pp_context,
1285                               obj_surface->bo, out_wpitch * out_hpitch,
1286                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1287                               8, 1);
1288
1289     /* sampler state */
1290     dri_bo_map(pp_context->sampler_state_table.bo, True);
1291     assert(pp_context->sampler_state_table.bo->virtual);
1292     sampler_state = pp_context->sampler_state_table.bo->virtual;
1293
1294     /* SIMD16 Y index 1 */
1295     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1296     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1297     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1298     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1299     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1300
1301     /* SIMD16 UV index 2 */
1302     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1303     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1304     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1305     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1306     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1307
1308     dri_bo_unmap(pp_context->sampler_state_table.bo);
1309
1310     /* private function & data */
1311     pp_context->pp_x_steps = pp_scaling_x_steps;
1312     pp_context->pp_y_steps = pp_scaling_y_steps;
1313     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1314
1315     pp_scaling_context->dest_x = dst_rect->x;
1316     pp_scaling_context->dest_y = dst_rect->y;
1317     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1318     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1319     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1320     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1321
1322     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1323
1324     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1325     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1326     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1327     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1328     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1329
1330     dst_surface->flags = src_surface->flags;
1331
1332     return VA_STATUS_SUCCESS;
1333 }
1334
1335 static int
1336 pp_avs_x_steps(void *private_context)
1337 {
1338     struct pp_avs_context *pp_avs_context = private_context;
1339
1340     return pp_avs_context->dest_w / 16;
1341 }
1342
1343 static int
1344 pp_avs_y_steps(void *private_context)
1345 {
1346     return 1;
1347 }
1348
1349 static int
1350 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1351 {
1352     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1353     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1354     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1355     float src_x_steping, src_y_steping, video_step_delta;
1356     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1357
1358     if (tmp_w >= pp_avs_context->dest_w) {
1359         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1360         pp_inline_parameter->grf6.video_step_delta = 0;
1361
1362         if (x == 0) {
1363             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1364                 pp_avs_context->src_normalized_x;
1365         } else {
1366             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1367             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1368             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1369                 16 * 15 * video_step_delta / 2;
1370         }
1371     } else {
1372         int n0, n1, n2, nls_left, nls_right;
1373         int factor_a = 5, factor_b = 4;
1374         float f;
1375
1376         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1377         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1378         n2 = tmp_w / (16 * factor_a);
1379         nls_left = n0 + n2;
1380         nls_right = n1 + n2;
1381         f = (float) n2 * 16 / tmp_w;
1382
1383         if (n0 < 5) {
1384             pp_inline_parameter->grf6.video_step_delta = 0.0;
1385
1386             if (x == 0) {
1387                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1388                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1389             } else {
1390                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1391                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1392                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1393                     16 * 15 * video_step_delta / 2;
1394             }
1395         } else {
1396             if (x < nls_left) {
1397                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1398                 float a = f / (nls_left * 16 * factor_b);
1399                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1400
1401                 pp_inline_parameter->grf6.video_step_delta = b;
1402
1403                 if (x == 0) {
1404                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1405                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1406                 } else {
1407                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1408                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1409                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1410                         16 * 15 * video_step_delta / 2;
1411                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1412                 }
1413             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1414                 /* scale the center linearly */
1415                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1416                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1417                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1418                     16 * 15 * video_step_delta / 2;
1419                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1420                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1421             } else {
1422                 float a = f / (nls_right * 16 * factor_b);
1423                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1424
1425                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1426                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1427                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1428                     16 * 15 * video_step_delta / 2;
1429                 pp_inline_parameter->grf6.video_step_delta = -b;
1430
1431                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1432                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1433                 else
1434                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1435             }
1436         }
1437     }
1438
1439     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1440     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1441     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1442     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1443
1444     return 0;
1445 }
1446
1447 static VAStatus
1448 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1449                        const struct i965_surface *src_surface,
1450                        const VARectangle *src_rect,
1451                        struct i965_surface *dst_surface,
1452                        const VARectangle *dst_rect,
1453                        void *filter_param)
1454 {
1455     struct i965_driver_data *i965 = i965_driver_data(ctx);
1456     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1457     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1458     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1459     struct object_surface *obj_surface;
1460     struct i965_sampler_8x8 *sampler_8x8;
1461     struct i965_sampler_8x8_state *sampler_8x8_state;
1462     int index;
1463     int in_w, in_h, in_wpitch, in_hpitch;
1464     int out_w, out_h, out_wpitch, out_hpitch;
1465     int i;
1466
1467     /* surface */
1468     obj_surface = SURFACE(src_surface->id);
1469     in_w = obj_surface->orig_width;
1470     in_h = obj_surface->orig_height;
1471     in_wpitch = obj_surface->width;
1472     in_hpitch = obj_surface->height;
1473
1474     /* source Y surface index 1 */
1475     i965_pp_set_surface2_state(ctx, pp_context,
1476                                obj_surface->bo, 0,
1477                                in_w, in_h, in_wpitch,
1478                                0, 0,
1479                                SURFACE_FORMAT_Y8_UNORM, 0,
1480                                1);
1481
1482     /* source UV surface index 2 */
1483     i965_pp_set_surface2_state(ctx, pp_context,
1484                                obj_surface->bo, in_wpitch * in_hpitch,
1485                                in_w / 2, in_h / 2, in_wpitch,
1486                                0, 0,
1487                                SURFACE_FORMAT_R8B8_UNORM, 0,
1488                                2);
1489
1490     /* destination surface */
1491     obj_surface = SURFACE(dst_surface->id);
1492     out_w = obj_surface->orig_width;
1493     out_h = obj_surface->orig_height;
1494     out_wpitch = obj_surface->width;
1495     out_hpitch = obj_surface->height;
1496     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1497
1498     /* destination Y surface index 7 */
1499     i965_pp_set_surface_state(ctx, pp_context,
1500                               obj_surface->bo, 0,
1501                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1502                               7, 1);
1503
1504     /* destination UV surface index 8 */
1505     i965_pp_set_surface_state(ctx, pp_context,
1506                               obj_surface->bo, out_wpitch * out_hpitch,
1507                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1508                               8, 1);
1509
1510     /* sampler 8x8 state */
1511     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1512     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1513     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1514     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1515     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1516
1517     for (i = 0; i < 17; i++) {
1518         /* for Y channel, currently ignore */
1519         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1520         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1521         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1522         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1523         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1524         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1525         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1526         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1527         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1528         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1529         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1530         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1531         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1532         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1533         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1534         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1535         /* for U/V channel, 0.25 */
1536         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1537         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1538         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1539         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1540         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1541         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1542         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1543         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1544         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1545         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1546         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1547         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1548         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1549         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1550         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1551         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1552     }
1553
1554     sampler_8x8_state->dw136.default_sharpness_level = 0;
1555     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1556     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1557     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1558     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1559
1560     /* sampler 8x8 */
1561     dri_bo_map(pp_context->sampler_state_table.bo, True);
1562     assert(pp_context->sampler_state_table.bo->virtual);
1563     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1564     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1565
1566     /* sample_8x8 Y index 1 */
1567     index = 1;
1568     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1569     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1570     sampler_8x8[index].dw0.ief_bypass = 1;
1571     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1572     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1573     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1574     sampler_8x8[index].dw2.global_noise_estimation = 22;
1575     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1576     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1577     sampler_8x8[index].dw3.strong_edge_weight = 7;
1578     sampler_8x8[index].dw3.regular_weight = 2;
1579     sampler_8x8[index].dw3.non_edge_weight = 0;
1580     sampler_8x8[index].dw3.gain_factor = 40;
1581     sampler_8x8[index].dw4.steepness_boost = 0;
1582     sampler_8x8[index].dw4.steepness_threshold = 0;
1583     sampler_8x8[index].dw4.mr_boost = 0;
1584     sampler_8x8[index].dw4.mr_threshold = 5;
1585     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1586     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1587     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1588     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1589     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1590     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1591     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1592     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1593     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1594     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1595     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1596     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1597     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1598     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1599     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1600     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1601     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1602     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1603     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1604     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1605     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1606     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1607     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1608     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1609     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1610     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1611     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1612     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1613     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1614     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1615     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1616     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1617     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1618     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1619     sampler_8x8[index].dw13.limiter_boost = 0;
1620     sampler_8x8[index].dw13.minimum_limiter = 10;
1621     sampler_8x8[index].dw13.maximum_limiter = 11;
1622     sampler_8x8[index].dw14.clip_limiter = 130;
1623     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1624                       I915_GEM_DOMAIN_RENDER,
1625                       0,
1626                       0,
1627                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1628                       pp_context->sampler_state_table.bo_8x8);
1629
1630     /* sample_8x8 UV index 2 */
1631     index = 2;
1632     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1633     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1634     sampler_8x8[index].dw0.ief_bypass = 1;
1635     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1636     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1637     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1638     sampler_8x8[index].dw2.global_noise_estimation = 22;
1639     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1640     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1641     sampler_8x8[index].dw3.strong_edge_weight = 7;
1642     sampler_8x8[index].dw3.regular_weight = 2;
1643     sampler_8x8[index].dw3.non_edge_weight = 0;
1644     sampler_8x8[index].dw3.gain_factor = 40;
1645     sampler_8x8[index].dw4.steepness_boost = 0;
1646     sampler_8x8[index].dw4.steepness_threshold = 0;
1647     sampler_8x8[index].dw4.mr_boost = 0;
1648     sampler_8x8[index].dw4.mr_threshold = 5;
1649     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1650     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1651     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1652     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1653     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1654     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1655     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1656     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1657     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1658     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1659     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1660     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1661     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1662     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1663     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1664     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1665     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1666     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1667     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1668     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1669     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1670     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1671     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1672     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1673     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1674     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1675     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1676     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1677     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1678     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1679     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1680     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1681     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1682     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1683     sampler_8x8[index].dw13.limiter_boost = 0;
1684     sampler_8x8[index].dw13.minimum_limiter = 10;
1685     sampler_8x8[index].dw13.maximum_limiter = 11;
1686     sampler_8x8[index].dw14.clip_limiter = 130;
1687     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1688                       I915_GEM_DOMAIN_RENDER,
1689                       0,
1690                       0,
1691                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1692                       pp_context->sampler_state_table.bo_8x8);
1693
1694     dri_bo_unmap(pp_context->sampler_state_table.bo);
1695
1696     /* private function & data */
1697     pp_context->pp_x_steps = pp_avs_x_steps;
1698     pp_context->pp_y_steps = pp_avs_y_steps;
1699     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
1700
1701     pp_avs_context->dest_x = dst_rect->x;
1702     pp_avs_context->dest_y = dst_rect->y;
1703     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
1704     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1705     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
1706     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
1707     pp_avs_context->src_w = src_rect->width;
1708     pp_avs_context->src_h = src_rect->height;
1709
1710     pp_static_parameter->grf4.r4_2.avs.nlas = 1;
1711     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1712
1713     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1714     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
1715     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
1716     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1717     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1718     pp_inline_parameter->grf6.video_step_delta = 0.0;
1719
1720     dst_surface->flags = src_surface->flags;
1721
1722     return VA_STATUS_SUCCESS;
1723 }
1724
1725 static int
1726 gen7_pp_avs_x_steps(void *private_context)
1727 {
1728     struct pp_avs_context *pp_avs_context = private_context;
1729
1730     return pp_avs_context->dest_w / 16;
1731 }
1732
1733 static int
1734 gen7_pp_avs_y_steps(void *private_context)
1735 {
1736     struct pp_avs_context *pp_avs_context = private_context;
1737
1738     return pp_avs_context->dest_h / 16;
1739 }
1740
1741 static int
1742 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1743 {
1744     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1745     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1746
1747     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1748     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
1749     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
1750     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
1751
1752     return 0;
1753 }
1754
1755 VAStatus
1756 gen7_pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1757                             const struct i965_surface *src_surface,
1758                             const VARectangle *src_rect,
1759                             struct i965_surface *dst_surface,
1760                             const VARectangle *dst_rect,
1761                             void *filter_param)
1762 {
1763     struct i965_driver_data *i965 = i965_driver_data(ctx);
1764     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1765     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1766     struct object_surface *obj_surface;
1767     struct gen7_sampler_8x8 *sampler_8x8;
1768     struct i965_sampler_8x8_state *sampler_8x8_state;
1769     int index, i;
1770     int in_w, in_h, in_wpitch, in_hpitch;
1771     int out_w, out_h, out_wpitch, out_hpitch;
1772
1773     /* surface */
1774     obj_surface = SURFACE(src_surface->id);
1775     in_w = obj_surface->orig_width;
1776     in_h = obj_surface->orig_height;
1777     in_wpitch = obj_surface->width;
1778     in_hpitch = obj_surface->height;
1779
1780     /* source Y surface index 0 */
1781     gen7_pp_set_surface2_state(ctx, pp_context,
1782                                obj_surface->bo, 0,
1783                                in_w, in_h, in_wpitch,
1784                                0, 0,
1785                                SURFACE_FORMAT_Y8_UNORM, 0,
1786                                0);
1787
1788     /* source UV surface index 1 */
1789     gen7_pp_set_surface2_state(ctx, pp_context,
1790                                obj_surface->bo, in_wpitch * in_hpitch,
1791                                in_w / 2, in_h / 2, in_wpitch,
1792                                0, 0,
1793                                SURFACE_FORMAT_R8B8_UNORM, 0,
1794                                1);
1795
1796     /* destination surface */
1797     obj_surface = SURFACE(dst_surface->id);
1798     out_w = obj_surface->orig_width;
1799     out_h = obj_surface->orig_height;
1800     out_wpitch = obj_surface->width;
1801     out_hpitch = obj_surface->height;
1802     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1803
1804     /* destination Y surface index 24 */
1805     gen7_pp_set_surface_state(ctx, pp_context,
1806                               obj_surface->bo, 0,
1807                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_SINT,
1808                               24, 1);
1809
1810     /* destination UV surface index 25 */
1811     gen7_pp_set_surface_state(ctx, pp_context,
1812                               obj_surface->bo, out_wpitch * out_hpitch,
1813                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_SINT,
1814                               25, 1);
1815
1816     /* sampler 8x8 state */
1817     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1818     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1819     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1820     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1821     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1822
1823     for (i = 0; i < 17; i++) {
1824         /* for Y channel, currently ignore */
1825         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
1826         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
1827         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
1828         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
1829         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
1830         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
1831         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
1832         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
1833         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
1834         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
1835         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
1836         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
1837         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
1838         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
1839         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
1840         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
1841         /* for U/V channel, 0.25 */
1842         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1843         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1844         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1845         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1846         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1847         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1848         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1849         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1850         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1851         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1852         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1853         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1854         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1855         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1856         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1857         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1858     }
1859
1860     sampler_8x8_state->dw136.default_sharpness_level = 0;
1861     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1862     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1863     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1864     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1865
1866     /* sampler 8x8 */
1867     dri_bo_map(pp_context->sampler_state_table.bo, True);
1868     assert(pp_context->sampler_state_table.bo->virtual);
1869     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
1870     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1871
1872     /* sample_8x8 Y index 4 */
1873     index = 4;
1874     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1875     sampler_8x8[index].dw0.global_noise_estimation = 255;
1876     sampler_8x8[index].dw0.ief_bypass = 1;
1877
1878     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1879
1880     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1881     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1882     sampler_8x8[index].dw2.r5x_coefficient = 9;
1883     sampler_8x8[index].dw2.r5cx_coefficient = 8;
1884     sampler_8x8[index].dw2.r5c_coefficient = 3;
1885
1886     sampler_8x8[index].dw3.r3x_coefficient = 27;
1887     sampler_8x8[index].dw3.r3c_coefficient = 5;
1888     sampler_8x8[index].dw3.gain_factor = 40;
1889     sampler_8x8[index].dw3.non_edge_weight = 1;
1890     sampler_8x8[index].dw3.regular_weight = 2;
1891     sampler_8x8[index].dw3.strong_edge_weight = 7;
1892     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
1893
1894     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1895                       I915_GEM_DOMAIN_RENDER,
1896                       0,
1897                       0,
1898                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1899                       pp_context->sampler_state_table.bo_8x8);
1900
1901     /* sample_8x8 UV index 8 */
1902     index = 8;
1903     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1904     sampler_8x8[index].dw0.disable_8x8_filter = 0;
1905     sampler_8x8[index].dw0.global_noise_estimation = 255;
1906     sampler_8x8[index].dw0.ief_bypass = 1;
1907     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1908     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1909     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1910     sampler_8x8[index].dw2.r5x_coefficient = 9;
1911     sampler_8x8[index].dw2.r5cx_coefficient = 8;
1912     sampler_8x8[index].dw2.r5c_coefficient = 3;
1913     sampler_8x8[index].dw3.r3x_coefficient = 27;
1914     sampler_8x8[index].dw3.r3c_coefficient = 5;
1915     sampler_8x8[index].dw3.gain_factor = 40;
1916     sampler_8x8[index].dw3.non_edge_weight = 1;
1917     sampler_8x8[index].dw3.regular_weight = 2;
1918     sampler_8x8[index].dw3.strong_edge_weight = 7;
1919     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
1920
1921     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1922                       I915_GEM_DOMAIN_RENDER,
1923                       0,
1924                       0,
1925                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1926                       pp_context->sampler_state_table.bo_8x8);
1927
1928     dri_bo_unmap(pp_context->sampler_state_table.bo);
1929
1930     /* private function & data */
1931     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
1932     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
1933     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
1934
1935     pp_avs_context->dest_x = dst_rect->x;
1936     pp_avs_context->dest_y = dst_rect->y;
1937     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
1938     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1939     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w / out_w;
1940     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h / out_h;
1941     pp_avs_context->src_w = src_rect->width;
1942     pp_avs_context->src_h = src_rect->height;
1943
1944     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
1945     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / pp_avs_context->dest_w;
1946     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
1947     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
1948     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / pp_avs_context->dest_w;
1949
1950     dst_surface->flags = src_surface->flags;
1951
1952     return VA_STATUS_SUCCESS;
1953 }
1954
1955 static int
1956 pp_dndi_x_steps(void *private_context)
1957 {
1958     return 1;
1959 }
1960
1961 static int
1962 pp_dndi_y_steps(void *private_context)
1963 {
1964     struct pp_dndi_context *pp_dndi_context = private_context;
1965
1966     return pp_dndi_context->dest_h / 4;
1967 }
1968
1969 static int
1970 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1971 {
1972     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1973
1974     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1975     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
1976
1977     return 0;
1978 }
1979
1980 static VAStatus
1981 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1982                         const struct i965_surface *src_surface,
1983                         const VARectangle *src_rect,
1984                         struct i965_surface *dst_surface,
1985                         const VARectangle *dst_rect,
1986                         void *filter_param)
1987 {
1988     struct i965_driver_data *i965 = i965_driver_data(ctx);
1989     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
1990     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1991     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1992     struct object_surface *obj_surface;
1993     struct i965_sampler_dndi *sampler_dndi;
1994     int index;
1995     int w, h;
1996     int orig_w, orig_h;
1997     int dndi_top_first = 1;
1998
1999     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2000         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2001
2002     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2003         dndi_top_first = 1;
2004     else
2005         dndi_top_first = 0;
2006
2007     /* surface */
2008     obj_surface = SURFACE(src_surface->id);
2009     orig_w = obj_surface->orig_width;
2010     orig_h = obj_surface->orig_height;
2011     w = obj_surface->width;
2012     h = obj_surface->height;
2013
2014     if (pp_context->stmm.bo == NULL) {
2015         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2016                                            "STMM surface",
2017                                            w * h,
2018                                            4096);
2019         assert(pp_context->stmm.bo);
2020     }
2021
2022     /* source UV surface index 2 */
2023     i965_pp_set_surface_state(ctx, pp_context,
2024                               obj_surface->bo, w * h,
2025                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2026                               2, 0);
2027
2028     /* source YUV surface index 4 */
2029     i965_pp_set_surface2_state(ctx, pp_context,
2030                                obj_surface->bo, 0,
2031                                orig_w, orig_h, w,
2032                                0, h,
2033                                SURFACE_FORMAT_PLANAR_420_8, 1,
2034                                4);
2035
2036     /* source STMM surface index 20 */
2037     i965_pp_set_surface_state(ctx, pp_context,
2038                               pp_context->stmm.bo, 0,
2039                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2040                               20, 1);
2041
2042     /* destination surface */
2043     obj_surface = SURFACE(dst_surface->id);
2044     orig_w = obj_surface->orig_width;
2045     orig_h = obj_surface->orig_height;
2046     w = obj_surface->width;
2047     h = obj_surface->height;
2048
2049     /* destination Y surface index 7 */
2050     i965_pp_set_surface_state(ctx, pp_context,
2051                               obj_surface->bo, 0,
2052                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2053                               7, 1);
2054
2055     /* destination UV surface index 8 */
2056     i965_pp_set_surface_state(ctx, pp_context,
2057                               obj_surface->bo, w * h,
2058                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2059                               8, 1);
2060     /* sampler dndi */
2061     dri_bo_map(pp_context->sampler_state_table.bo, True);
2062     assert(pp_context->sampler_state_table.bo->virtual);
2063     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2064     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2065
2066     /* sample dndi index 1 */
2067     index = 0;
2068     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2069     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2070     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2071     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2072
2073     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2074     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2075     sampler_dndi[index].dw1.stmm_c2 = 1;
2076     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2077     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2078
2079     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2080     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2081     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2082     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2083
2084     sampler_dndi[index].dw3.maximum_stmm = 128;
2085     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2086     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2087     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2088     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2089
2090     sampler_dndi[index].dw4.sdi_delta = 8;
2091     sampler_dndi[index].dw4.sdi_threshold = 128;
2092     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2093     sampler_dndi[index].dw4.stmm_shift_up = 0;
2094     sampler_dndi[index].dw4.stmm_shift_down = 0;
2095     sampler_dndi[index].dw4.minimum_stmm = 0;
2096
2097     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2098     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2099     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2100     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2101
2102     sampler_dndi[index].dw6.dn_enable = 1;
2103     sampler_dndi[index].dw6.di_enable = 1;
2104     sampler_dndi[index].dw6.di_partial = 0;
2105     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2106     sampler_dndi[index].dw6.dndi_stream_id = 0;
2107     sampler_dndi[index].dw6.dndi_first_frame = 1;
2108     sampler_dndi[index].dw6.progressive_dn = 0;
2109     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2110     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2111     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2112
2113     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2114     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2115     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2116     sampler_dndi[index].dw7.column_width_minus1 = 0;
2117
2118     dri_bo_unmap(pp_context->sampler_state_table.bo);
2119
2120     /* private function & data */
2121     pp_context->pp_x_steps = pp_dndi_x_steps;
2122     pp_context->pp_y_steps = pp_dndi_y_steps;
2123     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2124
2125     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2126     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2127     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2128     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2129
2130     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2131     pp_inline_parameter->grf5.number_blocks = w / 16;
2132     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2133     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2134
2135     pp_dndi_context->dest_w = w;
2136     pp_dndi_context->dest_h = h;
2137
2138     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2139
2140     return VA_STATUS_SUCCESS;
2141 }
2142
2143 static int
2144 pp_dn_x_steps(void *private_context)
2145 {
2146     return 1;
2147 }
2148
2149 static int
2150 pp_dn_y_steps(void *private_context)
2151 {
2152     struct pp_dn_context *pp_dn_context = private_context;
2153
2154     return pp_dn_context->dest_h / 8;
2155 }
2156
2157 static int
2158 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2159 {
2160     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2161
2162     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2163     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2164
2165     return 0;
2166 }
2167
2168 static VAStatus
2169 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2170                       const struct i965_surface *src_surface,
2171                       const VARectangle *src_rect,
2172                       struct i965_surface *dst_surface,
2173                       const VARectangle *dst_rect,
2174                       void *filter_param)
2175 {
2176     struct i965_driver_data *i965 = i965_driver_data(ctx);
2177     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2178     struct object_surface *obj_surface;
2179     struct i965_sampler_dndi *sampler_dndi;
2180     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2181     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2182     VAProcFilterBaseParameterBuffer *dn_filter_param = filter_param;
2183     int index;
2184     int w, h;
2185     int orig_w, orig_h;
2186     int dn_strength = 15;
2187     int dndi_top_first = 1;
2188     int dn_progressive = 0;
2189
2190     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2191         dndi_top_first = 1;
2192         dn_progressive = 1;
2193     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2194         dndi_top_first = 1;
2195         dn_progressive = 0;
2196     } else {
2197         dndi_top_first = 0;
2198         dn_progressive = 0;
2199     }
2200
2201     if (dn_filter_param) {
2202         int value = dn_filter_param->value;
2203
2204         if (value > 1.0)
2205             value = 1.0;
2206
2207         if (value < 0.0)
2208             value = 0.0;
2209
2210         dn_strength = (int)(value * 31.0F);
2211     }
2212
2213     /* surface */
2214     obj_surface = SURFACE(src_surface->id);
2215     orig_w = obj_surface->orig_width;
2216     orig_h = obj_surface->orig_height;
2217     w = obj_surface->width;
2218     h = obj_surface->height;
2219
2220     if (pp_context->stmm.bo == NULL) {
2221         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2222                                            "STMM surface",
2223                                            w * h,
2224                                            4096);
2225         assert(pp_context->stmm.bo);
2226     }
2227
2228     /* source UV surface index 2 */
2229     i965_pp_set_surface_state(ctx, pp_context,
2230                               obj_surface->bo, w * h,
2231                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2232                               2, 0);
2233
2234     /* source YUV surface index 4 */
2235     i965_pp_set_surface2_state(ctx, pp_context,
2236                                obj_surface->bo, 0,
2237                                orig_w, orig_h, w,
2238                                0, h,
2239                                SURFACE_FORMAT_PLANAR_420_8, 1,
2240                                4);
2241
2242     /* source STMM surface index 20 */
2243     i965_pp_set_surface_state(ctx, pp_context,
2244                               pp_context->stmm.bo, 0,
2245                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2246                               20, 1);
2247
2248     /* destination surface */
2249     obj_surface = SURFACE(dst_surface->id);
2250     orig_w = obj_surface->orig_width;
2251     orig_h = obj_surface->orig_height;
2252     w = obj_surface->width;
2253     h = obj_surface->height;
2254
2255     /* destination Y surface index 7 */
2256     i965_pp_set_surface_state(ctx, pp_context,
2257                               obj_surface->bo, 0,
2258                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2259                               7, 1);
2260
2261     /* destination UV surface index 8 */
2262     i965_pp_set_surface_state(ctx, pp_context,
2263                               obj_surface->bo, w * h,
2264                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2265                               8, 1);
2266     /* sampler dn */
2267     dri_bo_map(pp_context->sampler_state_table.bo, True);
2268     assert(pp_context->sampler_state_table.bo->virtual);
2269     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2270     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2271
2272     /* sample dndi index 1 */
2273     index = 0;
2274     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2275     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2276     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2277     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2278
2279     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2280     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2281     sampler_dndi[index].dw1.stmm_c2 = 0;
2282     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2283     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2284
2285     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2286     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2287     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2288     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2289
2290     sampler_dndi[index].dw3.maximum_stmm = 128;
2291     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2292     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2293     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2294     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2295
2296     sampler_dndi[index].dw4.sdi_delta = 8;
2297     sampler_dndi[index].dw4.sdi_threshold = 128;
2298     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2299     sampler_dndi[index].dw4.stmm_shift_up = 0;
2300     sampler_dndi[index].dw4.stmm_shift_down = 0;
2301     sampler_dndi[index].dw4.minimum_stmm = 0;
2302
2303     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2304     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2305     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2306     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2307
2308     sampler_dndi[index].dw6.dn_enable = 1;
2309     sampler_dndi[index].dw6.di_enable = 0;
2310     sampler_dndi[index].dw6.di_partial = 0;
2311     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2312     sampler_dndi[index].dw6.dndi_stream_id = 1;
2313     sampler_dndi[index].dw6.dndi_first_frame = 1;
2314     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2315     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2316     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2317     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2318
2319     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2320     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2321     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2322     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2323
2324     dri_bo_unmap(pp_context->sampler_state_table.bo);
2325
2326     /* private function & data */
2327     pp_context->pp_x_steps = pp_dn_x_steps;
2328     pp_context->pp_y_steps = pp_dn_y_steps;
2329     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2330
2331     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2332     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2333     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2334     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2335
2336     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2337     pp_inline_parameter->grf5.number_blocks = w / 16;
2338     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2339     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2340
2341     pp_dn_context->dest_w = w;
2342     pp_dn_context->dest_h = h;
2343
2344     dst_surface->flags = src_surface->flags;
2345
2346     return VA_STATUS_SUCCESS;
2347 }
2348
2349 static int
2350 gen7_pp_dndi_x_steps(void *private_context)
2351 {
2352     struct pp_dndi_context *pp_dndi_context = private_context;
2353
2354     return pp_dndi_context->dest_w / 16;
2355 }
2356
2357 static int
2358 gen7_pp_dndi_y_steps(void *private_context)
2359 {
2360     struct pp_dndi_context *pp_dndi_context = private_context;
2361
2362     return pp_dndi_context->dest_h / 4;
2363 }
2364
2365 static int
2366 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2367 {
2368     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2369
2370     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2371     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2372
2373     return 0;
2374 }
2375
2376 static VAStatus
2377 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2378                              const struct i965_surface *src_surface,
2379                              const VARectangle *src_rect,
2380                              struct i965_surface *dst_surface,
2381                              const VARectangle *dst_rect,
2382                              void *filter_param)
2383 {
2384     struct i965_driver_data *i965 = i965_driver_data(ctx);
2385     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2386     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2387     struct object_surface *obj_surface;
2388     struct gen7_sampler_dndi *sampler_dndi;
2389     int index;
2390     int w, h;
2391     int orig_w, orig_h;
2392     int dndi_top_first = 1;
2393
2394     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2395         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2396
2397     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2398         dndi_top_first = 1;
2399     else
2400         dndi_top_first = 0;
2401
2402     /* surface */
2403     obj_surface = SURFACE(src_surface->id);
2404     orig_w = obj_surface->orig_width;
2405     orig_h = obj_surface->orig_height;
2406     w = obj_surface->width;
2407     h = obj_surface->height;
2408
2409     if (pp_context->stmm.bo == NULL) {
2410         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2411                                            "STMM surface",
2412                                            w * h,
2413                                            4096);
2414         assert(pp_context->stmm.bo);
2415     }
2416
2417     /* source UV surface index 1 */
2418     gen7_pp_set_surface_state(ctx, pp_context,
2419                               obj_surface->bo, w * h,
2420                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2421                               1, 0);
2422
2423     /* source YUV surface index 3 */
2424     gen7_pp_set_surface2_state(ctx, pp_context,
2425                                obj_surface->bo, 0,
2426                                orig_w, orig_h, w,
2427                                0, h,
2428                                SURFACE_FORMAT_PLANAR_420_8, 1,
2429                                3);
2430
2431     /* source (temporal reference) YUV surface index 4 */
2432     gen7_pp_set_surface2_state(ctx, pp_context,
2433                                obj_surface->bo, 0,
2434                                orig_w, orig_h, w,
2435                                0, h,
2436                                SURFACE_FORMAT_PLANAR_420_8, 1,
2437                                4);
2438
2439     /* STMM / History Statistics input surface, index 5 */
2440     gen7_pp_set_surface_state(ctx, pp_context,
2441                               pp_context->stmm.bo, 0,
2442                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2443                               5, 1);
2444
2445     /* destination surface */
2446     obj_surface = SURFACE(dst_surface->id);
2447     orig_w = obj_surface->orig_width;
2448     orig_h = obj_surface->orig_height;
2449     w = obj_surface->width;
2450     h = obj_surface->height;
2451
2452     /* destination(Previous frame) Y surface index 27 */
2453     gen7_pp_set_surface_state(ctx, pp_context,
2454                               obj_surface->bo, 0,
2455                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2456                               27, 1);
2457
2458     /* destination(Previous frame) UV surface index 28 */
2459     gen7_pp_set_surface_state(ctx, pp_context,
2460                               obj_surface->bo, w * h,
2461                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2462                               28, 1);
2463
2464     /* destination(Current frame) Y surface index 30 */
2465     gen7_pp_set_surface_state(ctx, pp_context,
2466                               obj_surface->bo, 0,
2467                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2468                               30, 1);
2469
2470     /* destination(Current frame) UV surface index 31 */
2471     gen7_pp_set_surface_state(ctx, pp_context,
2472                               obj_surface->bo, w * h,
2473                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2474                               31, 1);
2475
2476     /* STMM output surface, index 33 */
2477     gen7_pp_set_surface_state(ctx, pp_context,
2478                               pp_context->stmm.bo, 0,
2479                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2480                               33, 1);
2481
2482
2483     /* sampler dndi */
2484     dri_bo_map(pp_context->sampler_state_table.bo, True);
2485     assert(pp_context->sampler_state_table.bo->virtual);
2486     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2487     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2488
2489     /* sample dndi index 0 */
2490     index = 0;
2491     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2492     sampler_dndi[index].dw0.dnmh_delt = 8;
2493     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2494     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2495     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2496     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2497
2498     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2499     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2500     sampler_dndi[index].dw1.stmm_c2 = 0;
2501     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2502     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2503
2504     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2505     sampler_dndi[index].dw2.bne_edge_th = 1;
2506     sampler_dndi[index].dw2.smooth_mv_th = 0;
2507     sampler_dndi[index].dw2.sad_tight_th = 5;
2508     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2509     sampler_dndi[index].dw2.good_neighbor_th = 4;
2510
2511     sampler_dndi[index].dw3.maximum_stmm = 128;
2512     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2513     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2514     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2515     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2516
2517     sampler_dndi[index].dw4.sdi_delta = 8;
2518     sampler_dndi[index].dw4.sdi_threshold = 128;
2519     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2520     sampler_dndi[index].dw4.stmm_shift_up = 0;
2521     sampler_dndi[index].dw4.stmm_shift_down = 0;
2522     sampler_dndi[index].dw4.minimum_stmm = 0;
2523
2524     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2525     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2526     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2527     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2528
2529     sampler_dndi[index].dw6.dn_enable = 0;
2530     sampler_dndi[index].dw6.di_enable = 1;
2531     sampler_dndi[index].dw6.di_partial = 0;
2532     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2533     sampler_dndi[index].dw6.dndi_stream_id = 1;
2534     sampler_dndi[index].dw6.dndi_first_frame = 1;
2535     sampler_dndi[index].dw6.progressive_dn = 0;
2536     sampler_dndi[index].dw6.mcdi_enable = 0;
2537     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2538     sampler_dndi[index].dw6.cat_th1 = 0;
2539     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2540     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2541
2542     sampler_dndi[index].dw7.sad_tha = 5;
2543     sampler_dndi[index].dw7.sad_thb = 10;
2544     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2545     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2546     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2547     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2548     sampler_dndi[index].dw7.neighborpixel_th = 10;
2549     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2550
2551     dri_bo_unmap(pp_context->sampler_state_table.bo);
2552
2553     /* private function & data */
2554     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2555     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2556     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2557
2558     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2559     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2560     pp_static_parameter->grf1.di_top_field_first = 0;
2561     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2562
2563     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2564     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2565     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2566
2567     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2568     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2569
2570     pp_dndi_context->dest_w = w;
2571     pp_dndi_context->dest_h = h;
2572
2573     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2574
2575     return VA_STATUS_SUCCESS;
2576 }
2577
2578 static int
2579 gen7_pp_dn_x_steps(void *private_context)
2580 {
2581     return 1;
2582 }
2583
2584 static int
2585 gen7_pp_dn_y_steps(void *private_context)
2586 {
2587     struct pp_dn_context *pp_dn_context = private_context;
2588
2589     return pp_dn_context->dest_h / 4;
2590 }
2591
2592 static int
2593 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2594 {
2595     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2596
2597     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2598     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2599
2600     return 0;
2601 }
2602
2603 static VAStatus
2604 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2605                            const struct i965_surface *src_surface,
2606                            const VARectangle *src_rect,
2607                            struct i965_surface *dst_surface,
2608                            const VARectangle *dst_rect,
2609                            void *filter_param)
2610 {
2611     struct i965_driver_data *i965 = i965_driver_data(ctx);
2612     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2613     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2614     struct object_surface *obj_surface;
2615     struct gen7_sampler_dndi *sampler_dn;
2616     VAProcFilterBaseParameterBuffer *dn_filter_param = filter_param;
2617     int index;
2618     int w, h;
2619     int orig_w, orig_h;
2620     int dn_strength = 15;
2621     int dndi_top_first = 1;
2622     int dn_progressive = 0;
2623
2624     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2625         dndi_top_first = 1;
2626         dn_progressive = 1;
2627     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2628         dndi_top_first = 1;
2629         dn_progressive = 0;
2630     } else {
2631         dndi_top_first = 0;
2632         dn_progressive = 0;
2633     }
2634
2635     if (dn_filter_param) {
2636         int value = dn_filter_param->value;
2637
2638         if (value > 1.0)
2639             value = 1.0;
2640
2641         if (value < 0.0)
2642             value = 0.0;
2643
2644         dn_strength = (int)(value * 31.0F);
2645     }
2646
2647     /* surface */
2648     obj_surface = SURFACE(src_surface->id);
2649     orig_w = obj_surface->orig_width;
2650     orig_h = obj_surface->orig_height;
2651     w = obj_surface->width;
2652     h = obj_surface->height;
2653
2654     if (pp_context->stmm.bo == NULL) {
2655         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2656                                            "STMM surface",
2657                                            w * h,
2658                                            4096);
2659         assert(pp_context->stmm.bo);
2660     }
2661
2662     /* source UV surface index 1 */
2663     gen7_pp_set_surface_state(ctx, pp_context,
2664                               obj_surface->bo, w * h,
2665                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2666                               1, 0);
2667
2668     /* source YUV surface index 3 */
2669     gen7_pp_set_surface2_state(ctx, pp_context,
2670                                obj_surface->bo, 0,
2671                                orig_w, orig_h, w,
2672                                0, h,
2673                                SURFACE_FORMAT_PLANAR_420_8, 1,
2674                                3);
2675
2676     /* source STMM surface index 5 */
2677     gen7_pp_set_surface_state(ctx, pp_context,
2678                               pp_context->stmm.bo, 0,
2679                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2680                               5, 1);
2681
2682     /* destination surface */
2683     obj_surface = SURFACE(dst_surface->id);
2684     orig_w = obj_surface->orig_width;
2685     orig_h = obj_surface->orig_height;
2686     w = obj_surface->width;
2687     h = obj_surface->height;
2688
2689     /* destination Y surface index 7 */
2690     gen7_pp_set_surface_state(ctx, pp_context,
2691                               obj_surface->bo, 0,
2692                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2693                               7, 1);
2694
2695     /* destination UV surface index 8 */
2696     gen7_pp_set_surface_state(ctx, pp_context,
2697                               obj_surface->bo, w * h,
2698                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2699                               8, 1);
2700     /* sampler dn */
2701     dri_bo_map(pp_context->sampler_state_table.bo, True);
2702     assert(pp_context->sampler_state_table.bo->virtual);
2703     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
2704     sampler_dn = pp_context->sampler_state_table.bo->virtual;
2705
2706     /* sample dn index 1 */
2707     index = 0;
2708     sampler_dn[index].dw0.denoise_asd_threshold = 0;
2709     sampler_dn[index].dw0.dnmh_delt = 8;
2710     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
2711     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
2712     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
2713     sampler_dn[index].dw0.denoise_stad_threshold = 0;
2714
2715     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2716     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
2717     sampler_dn[index].dw1.stmm_c2 = 0;
2718     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
2719     sampler_dn[index].dw1.temporal_difference_threshold = 16;
2720
2721     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2722     sampler_dn[index].dw2.bne_edge_th = 1;
2723     sampler_dn[index].dw2.smooth_mv_th = 0;
2724     sampler_dn[index].dw2.sad_tight_th = 5;
2725     sampler_dn[index].dw2.cat_slope_minus1 = 9;
2726     sampler_dn[index].dw2.good_neighbor_th = 4;
2727
2728     sampler_dn[index].dw3.maximum_stmm = 128;
2729     sampler_dn[index].dw3.multipler_for_vecm = 2;
2730     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2731     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2732     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
2733
2734     sampler_dn[index].dw4.sdi_delta = 8;
2735     sampler_dn[index].dw4.sdi_threshold = 128;
2736     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2737     sampler_dn[index].dw4.stmm_shift_up = 0;
2738     sampler_dn[index].dw4.stmm_shift_down = 0;
2739     sampler_dn[index].dw4.minimum_stmm = 0;
2740
2741     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
2742     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
2743     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2744     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2745
2746     sampler_dn[index].dw6.dn_enable = 1;
2747     sampler_dn[index].dw6.di_enable = 0;
2748     sampler_dn[index].dw6.di_partial = 0;
2749     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
2750     sampler_dn[index].dw6.dndi_stream_id = 1;
2751     sampler_dn[index].dw6.dndi_first_frame = 1;
2752     sampler_dn[index].dw6.progressive_dn = dn_progressive;
2753     sampler_dn[index].dw6.mcdi_enable = 0;
2754     sampler_dn[index].dw6.fmd_tear_threshold = 32;
2755     sampler_dn[index].dw6.cat_th1 = 0;
2756     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
2757     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
2758
2759     sampler_dn[index].dw7.sad_tha = 5;
2760     sampler_dn[index].dw7.sad_thb = 10;
2761     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2762     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
2763     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2764     sampler_dn[index].dw7.vdi_walker_enable = 0;
2765     sampler_dn[index].dw7.neighborpixel_th = 10;
2766     sampler_dn[index].dw7.column_width_minus1 = w / 16;
2767
2768     dri_bo_unmap(pp_context->sampler_state_table.bo);
2769
2770     /* private function & data */
2771     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
2772     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
2773     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
2774
2775     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2776     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2777     pp_static_parameter->grf1.di_top_field_first = 0;
2778     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2779
2780     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2781     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2782     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2783
2784     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2785     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2786
2787     pp_dn_context->dest_w = w;
2788     pp_dn_context->dest_h = h;
2789
2790     dst_surface->flags = src_surface->flags;
2791
2792     return VA_STATUS_SUCCESS;
2793 }
2794
2795 static VAStatus
2796 ironlake_pp_initialize(
2797     VADriverContextP   ctx,
2798     struct i965_post_processing_context *pp_context,
2799     const struct i965_surface *src_surface,
2800     const VARectangle *src_rect,
2801     struct i965_surface *dst_surface,
2802     const VARectangle *dst_rect,
2803     int                pp_index,
2804     void *filter_param
2805 )
2806 {
2807     VAStatus va_status;
2808     struct i965_driver_data *i965 = i965_driver_data(ctx);
2809     struct pp_module *pp_module;
2810     dri_bo *bo;
2811     int static_param_size, inline_param_size;
2812
2813     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
2814     bo = dri_bo_alloc(i965->intel.bufmgr,
2815                       "surface state & binding table",
2816                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
2817                       4096);
2818     assert(bo);
2819     pp_context->surface_state_binding_table.bo = bo;
2820
2821     dri_bo_unreference(pp_context->curbe.bo);
2822     bo = dri_bo_alloc(i965->intel.bufmgr,
2823                       "constant buffer",
2824                       4096,
2825                       4096);
2826     assert(bo);
2827     pp_context->curbe.bo = bo;
2828
2829     dri_bo_unreference(pp_context->idrt.bo);
2830     bo = dri_bo_alloc(i965->intel.bufmgr,
2831                       "interface discriptor",
2832                       sizeof(struct i965_interface_descriptor),
2833                       4096);
2834     assert(bo);
2835     pp_context->idrt.bo = bo;
2836     pp_context->idrt.num_interface_descriptors = 0;
2837
2838     dri_bo_unreference(pp_context->sampler_state_table.bo);
2839     bo = dri_bo_alloc(i965->intel.bufmgr,
2840                       "sampler state table",
2841                       4096,
2842                       4096);
2843     assert(bo);
2844     dri_bo_map(bo, True);
2845     memset(bo->virtual, 0, bo->size);
2846     dri_bo_unmap(bo);
2847     pp_context->sampler_state_table.bo = bo;
2848
2849     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
2850     bo = dri_bo_alloc(i965->intel.bufmgr,
2851                       "sampler 8x8 state ",
2852                       4096,
2853                       4096);
2854     assert(bo);
2855     pp_context->sampler_state_table.bo_8x8 = bo;
2856
2857     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
2858     bo = dri_bo_alloc(i965->intel.bufmgr,
2859                       "sampler 8x8 state ",
2860                       4096,
2861                       4096);
2862     assert(bo);
2863     pp_context->sampler_state_table.bo_8x8_uv = bo;
2864
2865     dri_bo_unreference(pp_context->vfe_state.bo);
2866     bo = dri_bo_alloc(i965->intel.bufmgr,
2867                       "vfe state",
2868                       sizeof(struct i965_vfe_state),
2869                       4096);
2870     assert(bo);
2871     pp_context->vfe_state.bo = bo;
2872
2873     if (IS_GEN7(i965->intel.device_id)) {
2874         static_param_size = sizeof(struct gen7_pp_static_parameter);
2875         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
2876     } else {
2877         static_param_size = sizeof(struct pp_static_parameter);
2878         inline_param_size = sizeof(struct pp_inline_parameter);
2879     }
2880
2881     memset(pp_context->pp_static_parameter, 0, static_param_size);
2882     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
2883     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
2884     pp_context->current_pp = pp_index;
2885     pp_module = &pp_context->pp_modules[pp_index];
2886
2887     if (pp_module->initialize)
2888         va_status = pp_module->initialize(ctx, pp_context,
2889                                           src_surface,
2890                                           src_rect,
2891                                           dst_surface,
2892                                           dst_rect,
2893                                           filter_param);
2894     else
2895         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
2896
2897     return va_status;
2898 }
2899
2900 static VAStatus
2901 ironlake_post_processing(
2902     VADriverContextP   ctx,
2903     struct i965_post_processing_context *pp_context,
2904     const struct i965_surface *src_surface,
2905     const VARectangle *src_rect,
2906     struct i965_surface *dst_surface,
2907     const VARectangle *dst_rect,
2908     int                pp_index,
2909     void *filter_param
2910 )
2911 {
2912     VAStatus va_status;
2913
2914     va_status = ironlake_pp_initialize(ctx, pp_context,
2915                                        src_surface,
2916                                        src_rect,
2917                                        dst_surface,
2918                                        dst_rect,
2919                                        pp_index,
2920                                        filter_param);
2921
2922     if (va_status == VA_STATUS_SUCCESS) {
2923         ironlake_pp_states_setup(ctx, pp_context);
2924         ironlake_pp_pipeline_setup(ctx, pp_context);
2925     }
2926
2927     return va_status;
2928 }
2929
2930 static VAStatus
2931 gen6_pp_initialize(
2932     VADriverContextP   ctx,
2933     struct i965_post_processing_context *pp_context,
2934     const struct i965_surface *src_surface,
2935     const VARectangle *src_rect,
2936     struct i965_surface *dst_surface,
2937     const VARectangle *dst_rect,
2938     int                pp_index,
2939     void *filter_param
2940 )
2941 {
2942     VAStatus va_status;
2943     struct i965_driver_data *i965 = i965_driver_data(ctx);
2944     struct pp_module *pp_module;
2945     dri_bo *bo;
2946     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2947     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2948
2949     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
2950     bo = dri_bo_alloc(i965->intel.bufmgr,
2951                       "surface state & binding table",
2952                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
2953                       4096);
2954     assert(bo);
2955     pp_context->surface_state_binding_table.bo = bo;
2956
2957     dri_bo_unreference(pp_context->curbe.bo);
2958     bo = dri_bo_alloc(i965->intel.bufmgr,
2959                       "constant buffer",
2960                       4096,
2961                       4096);
2962     assert(bo);
2963     pp_context->curbe.bo = bo;
2964
2965     dri_bo_unreference(pp_context->idrt.bo);
2966     bo = dri_bo_alloc(i965->intel.bufmgr,
2967                       "interface discriptor",
2968                       sizeof(struct gen6_interface_descriptor_data),
2969                       4096);
2970     assert(bo);
2971     pp_context->idrt.bo = bo;
2972     pp_context->idrt.num_interface_descriptors = 0;
2973
2974     dri_bo_unreference(pp_context->sampler_state_table.bo);
2975     bo = dri_bo_alloc(i965->intel.bufmgr,
2976                       "sampler state table",
2977                       4096,
2978                       4096);
2979     assert(bo);
2980     dri_bo_map(bo, True);
2981     memset(bo->virtual, 0, bo->size);
2982     dri_bo_unmap(bo);
2983     pp_context->sampler_state_table.bo = bo;
2984
2985     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
2986     bo = dri_bo_alloc(i965->intel.bufmgr,
2987                       "sampler 8x8 state ",
2988                       4096,
2989                       4096);
2990     assert(bo);
2991     pp_context->sampler_state_table.bo_8x8 = bo;
2992
2993     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
2994     bo = dri_bo_alloc(i965->intel.bufmgr,
2995                       "sampler 8x8 state ",
2996                       4096,
2997                       4096);
2998     assert(bo);
2999     pp_context->sampler_state_table.bo_8x8_uv = bo;
3000
3001     dri_bo_unreference(pp_context->vfe_state.bo);
3002     bo = dri_bo_alloc(i965->intel.bufmgr,
3003                       "vfe state",
3004                       sizeof(struct i965_vfe_state),
3005                       4096);
3006     assert(bo);
3007     pp_context->vfe_state.bo = bo;
3008
3009     memset(pp_static_parameter, 0, sizeof(*pp_static_parameter));
3010     memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter));
3011     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3012     pp_context->current_pp = pp_index;
3013     pp_module = &pp_context->pp_modules[pp_index];
3014
3015     if (pp_module->initialize)
3016         va_status = pp_module->initialize(ctx, pp_context,
3017                                           src_surface,
3018                                           src_rect,
3019                                           dst_surface,
3020                                           dst_rect,
3021                                           filter_param);
3022     else
3023         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3024
3025     return va_status;
3026 }
3027
3028 static void
3029 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3030                                    struct i965_post_processing_context *pp_context)
3031 {
3032     struct i965_driver_data *i965 = i965_driver_data(ctx);
3033     struct gen6_interface_descriptor_data *desc;
3034     dri_bo *bo;
3035     int pp_index = pp_context->current_pp;
3036
3037     bo = pp_context->idrt.bo;
3038     dri_bo_map(bo, True);
3039     assert(bo->virtual);
3040     desc = bo->virtual;
3041     memset(desc, 0, sizeof(*desc));
3042     desc->desc0.kernel_start_pointer =
3043         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3044     desc->desc1.single_program_flow = 1;
3045     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3046     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3047     desc->desc2.sampler_state_pointer =
3048         pp_context->sampler_state_table.bo->offset >> 5;
3049     desc->desc3.binding_table_entry_count = 0;
3050     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3051     desc->desc4.constant_urb_entry_read_offset = 0;
3052
3053     if (IS_GEN7(i965->intel.device_id))
3054         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3055     else
3056         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3057
3058     dri_bo_emit_reloc(bo,
3059                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3060                       0,
3061                       offsetof(struct gen6_interface_descriptor_data, desc0),
3062                       pp_context->pp_modules[pp_index].kernel.bo);
3063
3064     dri_bo_emit_reloc(bo,
3065                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3066                       desc->desc2.sampler_count << 2,
3067                       offsetof(struct gen6_interface_descriptor_data, desc2),
3068                       pp_context->sampler_state_table.bo);
3069
3070     dri_bo_unmap(bo);
3071     pp_context->idrt.num_interface_descriptors++;
3072 }
3073
3074 static void
3075 gen6_pp_upload_constants(VADriverContextP ctx,
3076                          struct i965_post_processing_context *pp_context)
3077 {
3078     struct i965_driver_data *i965 = i965_driver_data(ctx);
3079     unsigned char *constant_buffer;
3080     int param_size;
3081
3082     assert(sizeof(struct pp_static_parameter) == 128);
3083     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3084
3085     if (IS_GEN7(i965->intel.device_id))
3086         param_size = sizeof(struct gen7_pp_static_parameter);
3087     else
3088         param_size = sizeof(struct pp_static_parameter);
3089
3090     dri_bo_map(pp_context->curbe.bo, 1);
3091     assert(pp_context->curbe.bo->virtual);
3092     constant_buffer = pp_context->curbe.bo->virtual;
3093     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3094     dri_bo_unmap(pp_context->curbe.bo);
3095 }
3096
3097 static void
3098 gen6_pp_states_setup(VADriverContextP ctx,
3099                      struct i965_post_processing_context *pp_context)
3100 {
3101     gen6_pp_interface_descriptor_table(ctx, pp_context);
3102     gen6_pp_upload_constants(ctx, pp_context);
3103 }
3104
3105 static void
3106 gen6_pp_pipeline_select(VADriverContextP ctx,
3107                         struct i965_post_processing_context *pp_context)
3108 {
3109     struct intel_batchbuffer *batch = pp_context->batch;
3110
3111     BEGIN_BATCH(batch, 1);
3112     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3113     ADVANCE_BATCH(batch);
3114 }
3115
3116 static void
3117 gen6_pp_state_base_address(VADriverContextP ctx,
3118                            struct i965_post_processing_context *pp_context)
3119 {
3120     struct intel_batchbuffer *batch = pp_context->batch;
3121
3122     BEGIN_BATCH(batch, 10);
3123     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3124     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3125     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3126     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3127     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3128     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3129     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3130     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3131     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3132     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3133     ADVANCE_BATCH(batch);
3134 }
3135
3136 static void
3137 gen6_pp_vfe_state(VADriverContextP ctx,
3138                   struct i965_post_processing_context *pp_context)
3139 {
3140     struct intel_batchbuffer *batch = pp_context->batch;
3141
3142     BEGIN_BATCH(batch, 8);
3143     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3144     OUT_BATCH(batch, 0);
3145     OUT_BATCH(batch,
3146               (pp_context->urb.num_vfe_entries - 1) << 16 |
3147               pp_context->urb.num_vfe_entries << 8);
3148     OUT_BATCH(batch, 0);
3149     OUT_BATCH(batch,
3150               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3151               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3152     OUT_BATCH(batch, 0);
3153     OUT_BATCH(batch, 0);
3154     OUT_BATCH(batch, 0);
3155     ADVANCE_BATCH(batch);
3156 }
3157
3158 static void
3159 gen6_pp_curbe_load(VADriverContextP ctx,
3160                    struct i965_post_processing_context *pp_context)
3161 {
3162     struct intel_batchbuffer *batch = pp_context->batch;
3163
3164     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3165
3166     BEGIN_BATCH(batch, 4);
3167     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3168     OUT_BATCH(batch, 0);
3169     OUT_BATCH(batch,
3170               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3171     OUT_RELOC(batch,
3172               pp_context->curbe.bo,
3173               I915_GEM_DOMAIN_INSTRUCTION, 0,
3174               0);
3175     ADVANCE_BATCH(batch);
3176 }
3177
3178 static void
3179 gen6_interface_descriptor_load(VADriverContextP ctx,
3180                                struct i965_post_processing_context *pp_context)
3181 {
3182     struct intel_batchbuffer *batch = pp_context->batch;
3183
3184     BEGIN_BATCH(batch, 4);
3185     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3186     OUT_BATCH(batch, 0);
3187     OUT_BATCH(batch,
3188               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3189     OUT_RELOC(batch,
3190               pp_context->idrt.bo,
3191               I915_GEM_DOMAIN_INSTRUCTION, 0,
3192               0);
3193     ADVANCE_BATCH(batch);
3194 }
3195
3196 static void
3197 gen6_pp_object_walker(VADriverContextP ctx,
3198                       struct i965_post_processing_context *pp_context)
3199 {
3200     struct i965_driver_data *i965 = i965_driver_data(ctx);
3201     struct intel_batchbuffer *batch = pp_context->batch;
3202     int x, x_steps, y, y_steps;
3203     int param_size, command_length_in_dws;
3204     dri_bo *command_buffer;
3205     unsigned int *command_ptr;
3206
3207     if (IS_GEN7(i965->intel.device_id))
3208         param_size = sizeof(struct gen7_pp_inline_parameter);
3209     else
3210         param_size = sizeof(struct pp_inline_parameter);
3211
3212     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3213     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3214     command_length_in_dws = 6 + (param_size >> 2);
3215     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3216                                   "command objects buffer",
3217                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3218                                   4096);
3219
3220     dri_bo_map(command_buffer, 1);
3221     command_ptr = command_buffer->virtual;
3222
3223     for (y = 0; y < y_steps; y++) {
3224         for (x = 0; x < x_steps; x++) {
3225             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3226                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3227                 *command_ptr++ = 0;
3228                 *command_ptr++ = 0;
3229                 *command_ptr++ = 0;
3230                 *command_ptr++ = 0;
3231                 *command_ptr++ = 0;
3232                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3233                 command_ptr += (param_size >> 2);
3234             }
3235         }
3236     }
3237
3238     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3239         *command_ptr++ = 0;
3240
3241     *command_ptr = MI_BATCH_BUFFER_END;
3242
3243     dri_bo_unmap(command_buffer);
3244
3245     BEGIN_BATCH(batch, 2);
3246     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3247     OUT_RELOC(batch, command_buffer,
3248               I915_GEM_DOMAIN_COMMAND, 0,
3249               0);
3250     ADVANCE_BATCH(batch);
3251
3252     dri_bo_unreference(command_buffer);
3253
3254     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3255      * will cause control to pass back to ring buffer
3256      */
3257     intel_batchbuffer_end_atomic(batch);
3258     intel_batchbuffer_flush(batch);
3259     intel_batchbuffer_start_atomic(batch, 0x1000);
3260 }
3261
3262 static void
3263 gen6_pp_pipeline_setup(VADriverContextP ctx,
3264                        struct i965_post_processing_context *pp_context)
3265 {
3266     struct intel_batchbuffer *batch = pp_context->batch;
3267
3268     intel_batchbuffer_start_atomic(batch, 0x1000);
3269     intel_batchbuffer_emit_mi_flush(batch);
3270     gen6_pp_pipeline_select(ctx, pp_context);
3271     gen6_pp_state_base_address(ctx, pp_context);
3272     gen6_pp_vfe_state(ctx, pp_context);
3273     gen6_pp_curbe_load(ctx, pp_context);
3274     gen6_interface_descriptor_load(ctx, pp_context);
3275     gen6_pp_object_walker(ctx, pp_context);
3276     intel_batchbuffer_end_atomic(batch);
3277 }
3278
3279 static VAStatus
3280 gen6_post_processing(
3281     VADriverContextP   ctx,
3282     struct i965_post_processing_context *pp_context,
3283     const struct i965_surface *src_surface,
3284     const VARectangle *src_rect,
3285     struct i965_surface *dst_surface,
3286     const VARectangle *dst_rect,
3287     int                pp_index,
3288     void * filter_param
3289 )
3290 {
3291     VAStatus va_status;
3292
3293     va_status = gen6_pp_initialize(ctx, pp_context,
3294                                    src_surface,
3295                                    src_rect,
3296                                    dst_surface,
3297                                    dst_rect,
3298                                    pp_index,
3299                                    filter_param);
3300
3301     if (va_status == VA_STATUS_SUCCESS) {
3302         gen6_pp_states_setup(ctx, pp_context);
3303         gen6_pp_pipeline_setup(ctx, pp_context);
3304     }
3305
3306     return va_status;
3307 }
3308
3309 static VAStatus
3310 i965_post_processing_internal(
3311     VADriverContextP   ctx,
3312     struct i965_post_processing_context *pp_context,
3313     const struct i965_surface *src_surface,
3314     const VARectangle *src_rect,
3315     struct i965_surface *dst_surface,
3316     const VARectangle *dst_rect,
3317     int                pp_index,
3318     void *filter_param
3319 )
3320 {
3321     struct i965_driver_data *i965 = i965_driver_data(ctx);
3322     VAStatus va_status;
3323
3324     if (IS_GEN6(i965->intel.device_id) ||
3325         IS_GEN7(i965->intel.device_id))
3326         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3327     else
3328         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3329
3330     return va_status;
3331 }
3332
3333 VAStatus
3334 i965_DestroySurfaces(VADriverContextP ctx,
3335                      VASurfaceID *surface_list,
3336                      int num_surfaces);
3337 VAStatus
3338 i965_CreateSurfaces(VADriverContextP ctx,
3339                     int width,
3340                     int height,
3341                     int format,
3342                     int num_surfaces,
3343                     VASurfaceID *surfaces);
3344
3345 static void
3346 i965_vpp_clear_surface(VADriverContextP ctx,
3347                        struct i965_post_processing_context *pp_context,
3348                        VASurfaceID surface,
3349                        unsigned int color)
3350 {
3351     struct i965_driver_data *i965 = i965_driver_data(ctx);
3352     struct intel_batchbuffer *batch = pp_context->batch;
3353     struct object_surface *obj_surface = SURFACE(surface);
3354     unsigned int blt_cmd, br13;
3355     unsigned int tiling = 0, swizzle = 0;
3356     int pitch;
3357
3358     /* Currently only support NV12 surface */
3359     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3360         return;
3361
3362     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3363     blt_cmd = XY_COLOR_BLT_CMD;
3364     pitch = obj_surface->width;
3365
3366     if (tiling != I915_TILING_NONE) {
3367         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3368         pitch >>= 2;
3369     }
3370
3371     br13 = 0xf0 << 16;
3372     br13 |= BR13_8;
3373     br13 |= pitch;
3374
3375     if (IS_GEN6(i965->intel.device_id) ||
3376         IS_GEN7(i965->intel.device_id)) {
3377         intel_batchbuffer_start_atomic_blt(batch, 48);
3378         BEGIN_BLT_BATCH(batch, 12);
3379     } else {
3380         intel_batchbuffer_start_atomic(batch, 48);
3381         BEGIN_BATCH(batch, 12);
3382     }
3383
3384     OUT_BATCH(batch, blt_cmd);
3385     OUT_BATCH(batch, br13);
3386     OUT_BATCH(batch,
3387               0 << 16 |
3388               0);
3389     OUT_BATCH(batch,
3390               obj_surface->height << 16 |
3391               obj_surface->width);
3392     OUT_RELOC(batch, obj_surface->bo,
3393               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3394               0);
3395     OUT_BATCH(batch, 0x10);
3396
3397     OUT_BATCH(batch, blt_cmd);
3398     OUT_BATCH(batch, br13);
3399     OUT_BATCH(batch,
3400               0 << 16 |
3401               0);
3402     OUT_BATCH(batch,
3403               obj_surface->height / 2 << 16 |
3404               obj_surface->width);
3405     OUT_RELOC(batch, obj_surface->bo,
3406               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3407               obj_surface->width * obj_surface->y_cb_offset);
3408     OUT_BATCH(batch, 0x80);
3409
3410     ADVANCE_BATCH(batch);
3411     intel_batchbuffer_end_atomic(batch);
3412 }
3413
3414 VASurfaceID
3415 i965_post_processing(
3416     VADriverContextP   ctx,
3417     VASurfaceID        surface,
3418     const VARectangle *src_rect,
3419     const VARectangle *dst_rect,
3420     unsigned int       flags,
3421     int               *has_done_scaling
3422 )
3423 {
3424     struct i965_driver_data *i965 = i965_driver_data(ctx);
3425     VASurfaceID in_surface_id = surface;
3426     VASurfaceID out_surface_id = VA_INVALID_ID;
3427
3428     *has_done_scaling = 0;
3429
3430     if (HAS_PP(i965)) {
3431         struct object_surface *obj_surface;
3432         VAStatus status;
3433         struct i965_surface src_surface;
3434         struct i965_surface dst_surface;
3435
3436         obj_surface = SURFACE(in_surface_id);
3437
3438         /* Currently only support post processing for NV12 surface */
3439         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3440             return out_surface_id;
3441
3442         if (flags & I965_PP_FLAG_DEINTERLACING) {
3443             status = i965_CreateSurfaces(ctx,
3444                                          obj_surface->orig_width,
3445                                          obj_surface->orig_height,
3446                                          VA_RT_FORMAT_YUV420,
3447                                          1,
3448                                          &out_surface_id);
3449             assert(status == VA_STATUS_SUCCESS);
3450             obj_surface = SURFACE(out_surface_id);
3451             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3452             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3453             src_surface.id = in_surface_id;
3454             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3455             src_surface.flags = (flags & I965_PP_FLAG_DEINTERLACING_TOP_FISRT) ?
3456                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3457             dst_surface.id = out_surface_id;
3458             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3459             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3460
3461             i965_post_processing_internal(ctx, i965->pp_context,
3462                                           &src_surface,
3463                                           src_rect,
3464                                           &dst_surface,
3465                                           dst_rect,
3466                                           PP_NV12_DNDI,
3467                                           NULL);
3468         }
3469
3470         if (flags & I965_PP_FLAG_AVS) {
3471             struct i965_render_state *render_state = &i965->render_state;
3472             struct intel_region *dest_region = render_state->draw_region;
3473
3474             if (out_surface_id != VA_INVALID_ID)
3475                 in_surface_id = out_surface_id;
3476
3477             status = i965_CreateSurfaces(ctx,
3478                                          dest_region->width,
3479                                          dest_region->height,
3480                                          VA_RT_FORMAT_YUV420,
3481                                          1,
3482                                          &out_surface_id);
3483             assert(status == VA_STATUS_SUCCESS);
3484             obj_surface = SURFACE(out_surface_id);
3485             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3486             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3487             src_surface.id = in_surface_id;
3488             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3489             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3490             dst_surface.id = out_surface_id;
3491             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3492             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3493
3494             i965_post_processing_internal(ctx, i965->pp_context,
3495                                           &src_surface,
3496                                           src_rect,
3497                                           &dst_surface,
3498                                           dst_rect,
3499                                           PP_NV12_AVS,
3500                                           NULL);
3501
3502             if (in_surface_id != surface)
3503                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3504
3505             *has_done_scaling = 1;
3506         }
3507     }
3508
3509     return out_surface_id;
3510 }
3511
3512 static VAStatus
3513 i965_image_i420_processing(VADriverContextP ctx,
3514                            const struct i965_surface *src_surface,
3515                            const VARectangle *src_rect,
3516                            struct i965_surface *dst_surface,
3517                            const VARectangle *dst_rect)
3518 {
3519     struct i965_driver_data *i965 = i965_driver_data(ctx);
3520     struct i965_post_processing_context *pp_context = i965->pp_context;
3521     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3522
3523     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3524         i965_post_processing_internal(ctx, i965->pp_context,
3525                                       src_surface,
3526                                       src_rect,
3527                                       dst_surface,
3528                                       dst_rect,
3529                                       PP_PL3_LOAD_SAVE_N12,
3530                                       NULL);
3531     } else {
3532         i965_post_processing_internal(ctx, i965->pp_context,
3533                                       src_surface,
3534                                       src_rect,
3535                                       dst_surface,
3536                                       dst_rect,
3537                                       PP_PL3_LOAD_SAVE_PL3,
3538                                       NULL);
3539     }
3540
3541     intel_batchbuffer_flush(pp_context->batch);
3542
3543     return VA_STATUS_SUCCESS;
3544 }
3545
3546 static VAStatus
3547 i965_image_nv12_processing(VADriverContextP ctx,
3548                            const struct i965_surface *src_surface,
3549                            const VARectangle *src_rect,
3550                            struct i965_surface *dst_surface,
3551                            const VARectangle *dst_rect)
3552 {
3553     struct i965_driver_data *i965 = i965_driver_data(ctx);
3554     struct i965_post_processing_context *pp_context = i965->pp_context;
3555     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3556
3557     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3558         i965_post_processing_internal(ctx, i965->pp_context,
3559                                       src_surface,
3560                                       src_rect,
3561                                       dst_surface,
3562                                       dst_rect,
3563                                       PP_NV12_LOAD_SAVE_N12,
3564                                       NULL);
3565     } else {
3566         i965_post_processing_internal(ctx, i965->pp_context,
3567                                       src_surface,
3568                                       src_rect,
3569                                       dst_surface,
3570                                       dst_rect,
3571                                       PP_NV12_LOAD_SAVE_PL3,
3572                                       NULL);
3573     }
3574
3575     intel_batchbuffer_flush(pp_context->batch);
3576
3577     return VA_STATUS_SUCCESS;
3578 }
3579
3580 VAStatus
3581 i965_image_processing(VADriverContextP ctx,
3582                       const struct i965_surface *src_surface,
3583                       const VARectangle *src_rect,
3584                       struct i965_surface *dst_surface,
3585                       const VARectangle *dst_rect)
3586 {
3587     struct i965_driver_data *i965 = i965_driver_data(ctx);
3588     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
3589
3590     if (HAS_PP(i965)) {
3591         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
3592
3593         switch (fourcc) {
3594         case VA_FOURCC('Y', 'V', '1', '2'):
3595         case VA_FOURCC('I', '4', '2', '0'):
3596             status = i965_image_i420_processing(ctx,
3597                                                 src_surface,
3598                                                 src_rect,
3599                                                 dst_surface,
3600                                                 dst_rect);
3601             break;
3602
3603         case  VA_FOURCC('N', 'V', '1', '2'):
3604             status = i965_image_nv12_processing(ctx,
3605                                                 src_surface,
3606                                                 src_rect,
3607                                                 dst_surface,
3608                                                 dst_rect);
3609             break;
3610
3611         default:
3612             status = VA_STATUS_ERROR_UNIMPLEMENTED;
3613             break;
3614         }
3615     }
3616
3617     return status;
3618 }
3619
3620 static void
3621 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
3622 {
3623     int i;
3624
3625     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3626     pp_context->surface_state_binding_table.bo = NULL;
3627
3628     dri_bo_unreference(pp_context->curbe.bo);
3629     pp_context->curbe.bo = NULL;
3630
3631     dri_bo_unreference(pp_context->sampler_state_table.bo);
3632     pp_context->sampler_state_table.bo = NULL;
3633
3634     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3635     pp_context->sampler_state_table.bo_8x8 = NULL;
3636
3637     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3638     pp_context->sampler_state_table.bo_8x8_uv = NULL;
3639
3640     dri_bo_unreference(pp_context->idrt.bo);
3641     pp_context->idrt.bo = NULL;
3642     pp_context->idrt.num_interface_descriptors = 0;
3643
3644     dri_bo_unreference(pp_context->vfe_state.bo);
3645     pp_context->vfe_state.bo = NULL;
3646
3647     dri_bo_unreference(pp_context->stmm.bo);
3648     pp_context->stmm.bo = NULL;
3649
3650     for (i = 0; i < NUM_PP_MODULES; i++) {
3651         struct pp_module *pp_module = &pp_context->pp_modules[i];
3652
3653         dri_bo_unreference(pp_module->kernel.bo);
3654         pp_module->kernel.bo = NULL;
3655     }
3656
3657     free(pp_context->pp_static_parameter);
3658     free(pp_context->pp_inline_parameter);
3659     pp_context->pp_static_parameter = NULL;
3660     pp_context->pp_inline_parameter = NULL;
3661 }
3662
3663 Bool
3664 i965_post_processing_terminate(VADriverContextP ctx)
3665 {
3666     struct i965_driver_data *i965 = i965_driver_data(ctx);
3667     struct i965_post_processing_context *pp_context = i965->pp_context;
3668
3669     if (pp_context) {
3670         i965_post_processing_context_finalize(pp_context);
3671         free(pp_context);
3672     }
3673
3674     i965->pp_context = NULL;
3675
3676     return True;
3677 }
3678
3679 static void
3680 i965_post_processing_context_init(VADriverContextP ctx,
3681                                   struct i965_post_processing_context *pp_context,
3682                                   struct intel_batchbuffer *batch)
3683 {
3684     struct i965_driver_data *i965 = i965_driver_data(ctx);
3685     int i;
3686
3687     pp_context->urb.size = URB_SIZE((&i965->intel));
3688     pp_context->urb.num_vfe_entries = 32;
3689     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
3690     pp_context->urb.num_cs_entries = 1;
3691
3692     if (IS_GEN7(i965->intel.device_id))
3693         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
3694     else
3695         pp_context->urb.size_cs_entry = 2;
3696
3697     pp_context->urb.vfe_start = 0;
3698     pp_context->urb.cs_start = pp_context->urb.vfe_start +
3699         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
3700     assert(pp_context->urb.cs_start +
3701            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
3702
3703     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
3704     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
3705     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
3706
3707     if (IS_GEN7(i965->intel.device_id))
3708         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
3709     else if (IS_GEN6(i965->intel.device_id))
3710         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
3711     else if (IS_IRONLAKE(i965->intel.device_id))
3712         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
3713
3714     for (i = 0; i < NUM_PP_MODULES; i++) {
3715         struct pp_module *pp_module = &pp_context->pp_modules[i];
3716         dri_bo_unreference(pp_module->kernel.bo);
3717         if (pp_module->kernel.bin && pp_module->kernel.size) {
3718             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
3719                                                 pp_module->kernel.name,
3720                                                 pp_module->kernel.size,
3721                                                 4096);
3722             assert(pp_module->kernel.bo);
3723             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
3724         } else {
3725             pp_module->kernel.bo = NULL;
3726         }
3727     }
3728
3729     /* static & inline parameters */
3730     if (IS_GEN7(i965->intel.device_id)) {
3731         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
3732         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
3733     } else {
3734         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
3735         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
3736     }
3737
3738     pp_context->batch = batch;
3739 }
3740
3741 Bool
3742 i965_post_processing_init(VADriverContextP ctx)
3743 {
3744     struct i965_driver_data *i965 = i965_driver_data(ctx);
3745     struct i965_post_processing_context *pp_context = i965->pp_context;
3746
3747     if (HAS_PP(i965)) {
3748         if (pp_context == NULL) {
3749             pp_context = calloc(1, sizeof(*pp_context));
3750             i965_post_processing_context_init(ctx, pp_context, i965->batch);
3751             i965->pp_context = pp_context;
3752         }
3753     }
3754
3755     return True;
3756 }
3757
3758 static const int procfilter_to_pp_flag[10] = {
3759     PP_NULL,    /* VAProcFilterNone */
3760     PP_NULL,    /* VAProcFilterDering */
3761     PP_NULL,    /* VAProcFilterDeblocking */
3762     PP_NV12_DN, /* VAProcFilterNoiseReduction */
3763     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
3764     PP_NULL,    /* VAProcFilterSharpening */
3765     PP_NULL,    /* VAProcFilterColorEnhancement */
3766     PP_NULL,    /* VAProcFilterProcAmp */
3767     PP_NULL,    /* VAProcFilterComposition */
3768     PP_NULL,    /* VAProcFilterFrameRateConversion */
3769 };
3770
3771 static const int proc_frame_to_pp_frame[3] = {
3772     I965_SURFACE_FLAG_FRAME,
3773     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
3774     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
3775 };
3776
3777 static void
3778 i965_proc_picture(VADriverContextP ctx,
3779                   VAProfile profile,
3780                   union codec_state *codec_state,
3781                   struct hw_context *hw_context)
3782 {
3783     struct i965_driver_data *i965 = i965_driver_data(ctx);
3784     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
3785     struct proc_state *proc_state = &codec_state->proc;
3786     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
3787     VAProcInputParameterBuffer *input_param = (VAProcInputParameterBuffer *)proc_state->input_param->buffer;
3788     struct object_surface *obj_surface;
3789     struct i965_surface src_surface, dst_surface;
3790     VAStatus status;
3791     int i;
3792     VASurfaceID tmp_surfaces[VA_PROC_PIPELINE_MAX_NUM_FILTERS + 4];
3793     int num_tmp_surfaces = 0;
3794     unsigned int tiling = 0, swizzle = 0;
3795     int in_width, in_height;
3796
3797     assert(input_param->surface != VA_INVALID_ID);
3798     assert(proc_state->current_render_target != VA_INVALID_ID);
3799
3800     obj_surface = SURFACE(input_param->surface);
3801     in_width = obj_surface->orig_width;
3802     in_height = obj_surface->orig_height;
3803     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3804
3805     src_surface.id = input_param->surface;
3806     src_surface.type = I965_SURFACE_TYPE_SURFACE;
3807     src_surface.flags = proc_frame_to_pp_frame[input_param->flags];
3808
3809     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
3810         struct i965_surface src_surface, dst_surface;
3811         VARectangle src_rect, dst_rect;
3812         VASurfaceID out_surface_id = VA_INVALID_ID;
3813
3814         src_surface.id = input_param->surface;
3815         src_surface.type = I965_SURFACE_TYPE_SURFACE;
3816         src_surface.flags = I965_SURFACE_FLAG_FRAME;
3817         src_rect.x = 0;
3818         src_rect.y = 0;
3819         src_rect.width = in_width;
3820         src_rect.height = in_height;
3821
3822         status = i965_CreateSurfaces(ctx,
3823                                      in_width,
3824                                      in_height,
3825                                      VA_RT_FORMAT_YUV420,
3826                                      1,
3827                                      &out_surface_id);
3828         assert(status == VA_STATUS_SUCCESS);
3829         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
3830         obj_surface = SURFACE(out_surface_id);
3831         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
3832
3833         dst_surface.id = out_surface_id;
3834         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3835         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3836         dst_rect.x = 0;
3837         dst_rect.y = 0;
3838         dst_rect.width = in_width;
3839         dst_rect.height = in_height;
3840
3841         status = i965_image_processing(ctx,
3842                                        &src_surface,
3843                                        &src_rect,
3844                                        &dst_surface,
3845                                        &dst_rect);
3846         assert(status == VA_STATUS_SUCCESS);
3847
3848         src_surface.id = out_surface_id;
3849         src_surface.type = I965_SURFACE_TYPE_SURFACE;
3850         src_surface.flags = proc_frame_to_pp_frame[input_param->flags];
3851     }
3852
3853     obj_surface = SURFACE(proc_state->current_render_target);
3854     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3855
3856     for (i = 0; i < VA_PROC_PIPELINE_MAX_NUM_FILTERS; i++) {
3857         VAProcFilterType filter_type = pipeline_param->filter_pipeline[i];
3858         VASurfaceID out_surface_id = VA_INVALID_ID;
3859         void *filter_param = NULL;
3860
3861         if (procfilter_to_pp_flag[filter_type] != PP_NULL) {
3862             if (proc_state->filter_param[filter_type])
3863                 filter_param = proc_state->filter_param[filter_type]->buffer;
3864
3865             status = i965_CreateSurfaces(ctx,
3866                                          in_width,
3867                                          in_height,
3868                                          VA_RT_FORMAT_YUV420,
3869                                          1,
3870                                          &out_surface_id);
3871             assert(status == VA_STATUS_SUCCESS);
3872             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
3873             obj_surface = SURFACE(out_surface_id);
3874             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3875             dst_surface.id = out_surface_id;
3876             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3877             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
3878                                                    &src_surface,
3879                                                    &input_param->region,
3880                                                    &dst_surface,
3881                                                    &input_param->region,
3882                                                    procfilter_to_pp_flag[filter_type],
3883                                                    filter_param);
3884
3885             if (status == VA_STATUS_SUCCESS) {
3886                 src_surface.id = dst_surface.id;
3887                 src_surface.type = dst_surface.type;
3888                 src_surface.flags = dst_surface.flags;
3889             }
3890         }
3891     }
3892
3893     dst_surface.id = proc_state->current_render_target;
3894     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3895     i965_post_processing_internal(ctx, &proc_context->pp_context,
3896                                   &src_surface,
3897                                   &input_param->region,
3898                                   &dst_surface,
3899                                   &pipeline_param->output_region,
3900                                   (pipeline_param->flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
3901                                   PP_NV12_AVS : PP_NV12_SCALING,
3902                                   NULL);
3903
3904     if (num_tmp_surfaces)
3905         i965_DestroySurfaces(ctx,
3906                              tmp_surfaces,
3907                              num_tmp_surfaces);
3908
3909     intel_batchbuffer_flush(hw_context->batch);
3910 }
3911
3912 static void
3913 i965_proc_context_destroy(void *hw_context)
3914 {
3915     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
3916
3917     i965_post_processing_context_finalize(&proc_context->pp_context);
3918     intel_batchbuffer_free(proc_context->base.batch);
3919     free(proc_context);
3920 }
3921
3922 struct hw_context *
3923 i965_proc_context_init(VADriverContextP ctx, VAProfile profile)
3924 {
3925     struct intel_driver_data *intel = intel_driver_data(ctx);
3926     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
3927
3928     proc_context->base.destroy = i965_proc_context_destroy;
3929     proc_context->base.run = i965_proc_picture;
3930     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
3931     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
3932
3933     return (struct hw_context *)proc_context;
3934 }