src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  95                                    const struct i965_surface *src_surface,
  96                                    const VARectangle *src_rect,
  97                                    struct i965_surface *dst_surface,
  98                                    const VARectangle *dst_rect,
  99                                    void *filter_param);
 100 static VAStatus pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 101                                        const struct i965_surface *src_surface,
 102                                        const VARectangle *src_rect,
 103                                        struct i965_surface *dst_surface,
 104                                        const VARectangle *dst_rect,
 105                                        void *filter_param);
 106 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 107                                            const struct i965_surface *src_surface,
 108                                            const VARectangle *src_rect,
 109                                            struct i965_surface *dst_surface,
 110                                            const VARectangle *dst_rect,
 111                                            void *filter_param);
 112 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 113                                                 const struct i965_surface *src_surface,
 114                                                 const VARectangle *src_rect,
 115                                                 struct i965_surface *dst_surface,
 116                                                 const VARectangle *dst_rect,
 117                                                 void *filter_param);
 118 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                         const struct i965_surface *src_surface,
 120                                         const VARectangle *src_rect,
 121                                         struct i965_surface *dst_surface,
 122                                         const VARectangle *dst_rect,
 123                                         void *filter_param);
 124 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                       const struct i965_surface *src_surface,
 126                                       const VARectangle *src_rect,
 127                                       struct i965_surface *dst_surface,
 128                                       const VARectangle *dst_rect,
 129                                       void *filter_param);
 130
 131 static struct pp_module pp_modules_gen5[] = {
 132     {
 133         {
 134             "NULL module (for testing)",
 135             PP_NULL,
 136             pp_null_gen5,
 137             sizeof(pp_null_gen5),
 138             NULL,
 139         },
 140
 141         pp_null_initialize,
 142     },
 143
 144     {
 145         {
 146             "NV12_NV12",
 147             PP_NV12_LOAD_SAVE_N12,
 148             pp_nv12_load_save_nv12_gen5,
 149             sizeof(pp_nv12_load_save_nv12_gen5),
 150             NULL,
 151         },
 152
 153         pp_plx_load_save_plx_initialize,
 154     },
 155
 156     {
 157         {
 158             "NV12_PL3",
 159             PP_NV12_LOAD_SAVE_PL3,
 160             pp_nv12_load_save_pl3_gen5,
 161             sizeof(pp_nv12_load_save_pl3_gen5),
 162             NULL,
 163         },
 164
 165         pp_plx_load_save_plx_initialize,
 166     },
 167
 168     {
 169         {
 170             "PL3_NV12",
 171             PP_PL3_LOAD_SAVE_N12,
 172             pp_pl3_load_save_nv12_gen5,
 173             sizeof(pp_pl3_load_save_nv12_gen5),
 174             NULL,
 175         },
 176
 177         pp_plx_load_save_plx_initialize,
 178     },
 179
 180     {
 181         {
 182             "PL3_PL3",
 183             PP_PL3_LOAD_SAVE_N12,
 184             pp_pl3_load_save_pl3_gen5,
 185             sizeof(pp_pl3_load_save_pl3_gen5),
 186             NULL,
 187         },
 188
 189         pp_plx_load_save_plx_initialize
 190     },
 191
 192     {
 193         {
 194             "NV12 Scaling module",
 195             PP_NV12_SCALING,
 196             pp_nv12_scaling_gen5,
 197             sizeof(pp_nv12_scaling_gen5),
 198             NULL,
 199         },
 200
 201         pp_nv12_scaling_initialize,
 202     },
 203
 204     {
 205         {
 206             "NV12 AVS module",
 207             PP_NV12_AVS,
 208             pp_nv12_avs_gen5,
 209             sizeof(pp_nv12_avs_gen5),
 210             NULL,
 211         },
 212
 213         pp_nv12_avs_initialize,
 214     },
 215
 216     {
 217         {
 218             "NV12 DNDI module",
 219             PP_NV12_DNDI,
 220             pp_nv12_dndi_gen5,
 221             sizeof(pp_nv12_dndi_gen5),
 222             NULL,
 223         },
 224
 225         pp_nv12_dndi_initialize,
 226     },
 227
 228     {
 229         {
 230             "NV12 DN module",
 231             PP_NV12_DN,
 232             pp_nv12_dn_gen5,
 233             sizeof(pp_nv12_dn_gen5),
 234             NULL,
 235         },
 236
 237         pp_nv12_dn_initialize,
 238     },
 239 };
 240
 241 static const uint32_t pp_null_gen6[][4] = {
 242 #include "shaders/post_processing/gen5_6/null.g6b"
 243 };
 244
 245 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 246 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 247 };
 248
 249 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 250 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 251 };
 252
 253 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 254 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 255 };
 256
 257 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 258 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 259 };
 260
 261 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 262 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g6b"
 263 };
 264
 265 static const uint32_t pp_nv12_avs_gen6[][4] = {
 266 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 267 };
 268
 269 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 270 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 271 };
 272
 273 static const uint32_t pp_nv12_dn_gen6[][4] = {
 274 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 275 };
 276
 277 static struct pp_module pp_modules_gen6[] = {
 278     {
 279         {
 280             "NULL module (for testing)",
 281             PP_NULL,
 282             pp_null_gen6,
 283             sizeof(pp_null_gen6),
 284             NULL,
 285         },
 286
 287         pp_null_initialize,
 288     },
 289
 290     {
 291         {
 292             "NV12_NV12",
 293             PP_NV12_LOAD_SAVE_N12,
 294             pp_nv12_load_save_nv12_gen6,
 295             sizeof(pp_nv12_load_save_nv12_gen6),
 296             NULL,
 297         },
 298
 299         pp_plx_load_save_plx_initialize,
 300     },
 301
 302     {
 303         {
 304             "NV12_PL3",
 305             PP_NV12_LOAD_SAVE_PL3,
 306             pp_nv12_load_save_pl3_gen6,
 307             sizeof(pp_nv12_load_save_pl3_gen6),
 308             NULL,
 309         },
 310
 311         pp_plx_load_save_plx_initialize,
 312     },
 313
 314     {
 315         {
 316             "PL3_NV12",
 317             PP_PL3_LOAD_SAVE_N12,
 318             pp_pl3_load_save_nv12_gen6,
 319             sizeof(pp_pl3_load_save_nv12_gen6),
 320             NULL,
 321         },
 322
 323         pp_plx_load_save_plx_initialize,
 324     },
 325
 326     {
 327         {
 328             "PL3_PL3",
 329             PP_PL3_LOAD_SAVE_N12,
 330             pp_pl3_load_save_pl3_gen6,
 331             sizeof(pp_pl3_load_save_pl3_gen6),
 332             NULL,
 333         },
 334
 335         pp_plx_load_save_plx_initialize,
 336     },
 337
 338     {
 339         {
 340             "NV12 Scaling module",
 341             PP_NV12_SCALING,
 342             pp_nv12_scaling_gen6,
 343             sizeof(pp_nv12_scaling_gen6),
 344             NULL,
 345         },
 346
 347         pp_nv12_scaling_initialize,
 348     },
 349
 350     {
 351         {
 352             "NV12 AVS module",
 353             PP_NV12_AVS,
 354             pp_nv12_avs_gen6,
 355             sizeof(pp_nv12_avs_gen6),
 356             NULL,
 357         },
 358
 359         pp_nv12_avs_initialize,
 360     },
 361
 362     {
 363         {
 364             "NV12 DNDI module",
 365             PP_NV12_DNDI,
 366             pp_nv12_dndi_gen6,
 367             sizeof(pp_nv12_dndi_gen6),
 368             NULL,
 369         },
 370
 371         pp_nv12_dndi_initialize,
 372     },
 373
 374     {
 375         {
 376             "NV12 DN module",
 377             PP_NV12_DN,
 378             pp_nv12_dn_gen6,
 379             sizeof(pp_nv12_dn_gen6),
 380             NULL,
 381         },
 382
 383         pp_nv12_dn_initialize,
 384     },
 385 };
 386
 387 static const uint32_t pp_null_gen7[][4] = {
 388 };
 389
 390 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 391 };
 392
 393 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 394 };
 395
 396 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 397 };
 398
 399 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 400 };
 401
 402 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 403 #include "shaders/post_processing/gen7/avs.g7b"
 404 };
 405
 406 static const uint32_t pp_nv12_avs_gen7[][4] = {
 407 #include "shaders/post_processing/gen7/avs.g7b"
 408 };
 409
 410 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 411 #include "shaders/post_processing/gen7/dndi.g7b"
 412 };
 413
 414 static const uint32_t pp_nv12_dn_gen7[][4] = {
 415 };
 416
 417 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 418                                            const struct i965_surface *src_surface,
 419                                            const VARectangle *src_rect,
 420                                            struct i965_surface *dst_surface,
 421                                            const VARectangle *dst_rect,
 422                                            void *filter_param);
 423 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 424                                              const struct i965_surface *src_surface,
 425                                              const VARectangle *src_rect,
 426                                              struct i965_surface *dst_surface,
 427                                              const VARectangle *dst_rect,
 428                                              void *filter_param);
 429 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 430                                            const struct i965_surface *src_surface,
 431                                            const VARectangle *src_rect,
 432                                            struct i965_surface *dst_surface,
 433                                            const VARectangle *dst_rect,
 434                                            void *filter_param);
 435
 436 static struct pp_module pp_modules_gen7[] = {
 437     {
 438         {
 439             "NULL module (for testing)",
 440             PP_NULL,
 441             pp_null_gen7,
 442             sizeof(pp_null_gen7),
 443             NULL,
 444         },
 445
 446         pp_null_initialize,
 447     },
 448
 449     {
 450         {
 451             "NV12_NV12",
 452             PP_NV12_LOAD_SAVE_N12,
 453             pp_nv12_load_save_nv12_gen7,
 454             sizeof(pp_nv12_load_save_nv12_gen7),
 455             NULL,
 456         },
 457
 458         pp_plx_load_save_plx_initialize,
 459     },
 460
 461     {
 462         {
 463             "NV12_PL3",
 464             PP_NV12_LOAD_SAVE_PL3,
 465             pp_nv12_load_save_pl3_gen7,
 466             sizeof(pp_nv12_load_save_pl3_gen7),
 467             NULL,
 468         },
 469
 470         pp_plx_load_save_plx_initialize,
 471     },
 472
 473     {
 474         {
 475             "PL3_NV12",
 476             PP_PL3_LOAD_SAVE_N12,
 477             pp_pl3_load_save_nv12_gen7,
 478             sizeof(pp_pl3_load_save_nv12_gen7),
 479             NULL,
 480         },
 481
 482         pp_plx_load_save_plx_initialize,
 483     },
 484
 485     {
 486         {
 487             "PL3_PL3",
 488             PP_PL3_LOAD_SAVE_N12,
 489             pp_pl3_load_save_pl3_gen7,
 490             sizeof(pp_pl3_load_save_pl3_gen7),
 491             NULL,
 492         },
 493
 494         pp_plx_load_save_plx_initialize,
 495     },
 496
 497     {
 498         {
 499             "NV12 Scaling module",
 500             PP_NV12_SCALING,
 501             pp_nv12_scaling_gen7,
 502             sizeof(pp_nv12_scaling_gen7),
 503             NULL,
 504         },
 505
 506         gen7_pp_plx_avs_initialize,
 507     },
 508
 509     {
 510         {
 511             "NV12 AVS module",
 512             PP_NV12_AVS,
 513             pp_nv12_avs_gen7,
 514             sizeof(pp_nv12_avs_gen7),
 515             NULL,
 516         },
 517
 518         gen7_pp_plx_avs_initialize,
 519     },
 520
 521     {
 522         {
 523             "NV12 DNDI module",
 524             PP_NV12_DNDI,
 525             pp_nv12_dndi_gen7,
 526             sizeof(pp_nv12_dndi_gen7),
 527             NULL,
 528         },
 529
 530         gen7_pp_nv12_dndi_initialize,
 531     },
 532
 533     {
 534         {
 535             "NV12 DN module",
 536             PP_NV12_DN,
 537             pp_nv12_dn_gen7,
 538             sizeof(pp_nv12_dn_gen7),
 539             NULL,
 540         },
 541
 542         gen7_pp_nv12_dn_initialize,
 543     },
 544 };
 545
 546 static int
 547 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 548 {
 549     struct i965_driver_data *i965 = i965_driver_data(ctx);
 550     int fourcc;
 551
 552     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 553         struct object_image *obj_image = IMAGE(surface->id);
 554         fourcc = obj_image->image.format.fourcc;
 555     } else {
 556         struct object_surface *obj_surface = SURFACE(surface->id);
 557         fourcc = obj_surface->fourcc;
 558     }
 559
 560     return fourcc;
 561 }
 562
 563 static void
 564 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 565 {
 566     switch (tiling) {
 567     case I915_TILING_NONE:
 568         ss->ss3.tiled_surface = 0;
 569         ss->ss3.tile_walk = 0;
 570         break;
 571     case I915_TILING_X:
 572         ss->ss3.tiled_surface = 1;
 573         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 574         break;
 575     case I915_TILING_Y:
 576         ss->ss3.tiled_surface = 1;
 577         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 578         break;
 579     }
 580 }
 581
 582 static void
 583 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 584 {
 585     switch (tiling) {
 586     case I915_TILING_NONE:
 587         ss->ss2.tiled_surface = 0;
 588         ss->ss2.tile_walk = 0;
 589         break;
 590     case I915_TILING_X:
 591         ss->ss2.tiled_surface = 1;
 592         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 593         break;
 594     case I915_TILING_Y:
 595         ss->ss2.tiled_surface = 1;
 596         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 597         break;
 598     }
 599 }
 600
 601 static void
 602 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 603 {
 604     switch (tiling) {
 605     case I915_TILING_NONE:
 606         ss->ss0.tiled_surface = 0;
 607         ss->ss0.tile_walk = 0;
 608         break;
 609     case I915_TILING_X:
 610         ss->ss0.tiled_surface = 1;
 611         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 612         break;
 613     case I915_TILING_Y:
 614         ss->ss0.tiled_surface = 1;
 615         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 616         break;
 617     }
 618 }
 619
 620 static void
 621 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 622 {
 623     switch (tiling) {
 624     case I915_TILING_NONE:
 625         ss->ss2.tiled_surface = 0;
 626         ss->ss2.tile_walk = 0;
 627         break;
 628     case I915_TILING_X:
 629         ss->ss2.tiled_surface = 1;
 630         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 631         break;
 632     case I915_TILING_Y:
 633         ss->ss2.tiled_surface = 1;
 634         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 635         break;
 636     }
 637 }
 638
 639 static void
 640 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 641 {
 642     struct i965_interface_descriptor *desc;
 643     dri_bo *bo;
 644     int pp_index = pp_context->current_pp;
 645
 646     bo = pp_context->idrt.bo;
 647     dri_bo_map(bo, 1);
 648     assert(bo->virtual);
 649     desc = bo->virtual;
 650     memset(desc, 0, sizeof(*desc));
 651     desc->desc0.grf_reg_blocks = 10;
 652     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 653     desc->desc1.const_urb_entry_read_offset = 0;
 654     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 655     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 656     desc->desc2.sampler_count = 0;
 657     desc->desc3.binding_table_entry_count = 0;
 658     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 659
 660     dri_bo_emit_reloc(bo,
 661                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 662                       desc->desc0.grf_reg_blocks,
 663                       offsetof(struct i965_interface_descriptor, desc0),
 664                       pp_context->pp_modules[pp_index].kernel.bo);
 665
 666     dri_bo_emit_reloc(bo,
 667                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 668                       desc->desc2.sampler_count << 2,
 669                       offsetof(struct i965_interface_descriptor, desc2),
 670                       pp_context->sampler_state_table.bo);
 671
 672     dri_bo_unmap(bo);
 673     pp_context->idrt.num_interface_descriptors++;
 674 }
 675
 676 static void
 677 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 678 {
 679     struct i965_vfe_state *vfe_state;
 680     dri_bo *bo;
 681
 682     bo = pp_context->vfe_state.bo;
 683     dri_bo_map(bo, 1);
 684     assert(bo->virtual);
 685     vfe_state = bo->virtual;
 686     memset(vfe_state, 0, sizeof(*vfe_state));
 687     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 688     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 689     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 690     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 691     vfe_state->vfe1.children_present = 0;
 692     vfe_state->vfe2.interface_descriptor_base =
 693         pp_context->idrt.bo->offset >> 4; /* reloc */
 694     dri_bo_emit_reloc(bo,
 695                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 696                       0,
 697                       offsetof(struct i965_vfe_state, vfe2),
 698                       pp_context->idrt.bo);
 699     dri_bo_unmap(bo);
 700 }
 701
 702 static void
 703 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 704 {
 705     unsigned char *constant_buffer;
 706     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 707
 708     assert(sizeof(*pp_static_parameter) == 128);
 709     dri_bo_map(pp_context->curbe.bo, 1);
 710     assert(pp_context->curbe.bo->virtual);
 711     constant_buffer = pp_context->curbe.bo->virtual;
 712     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 713     dri_bo_unmap(pp_context->curbe.bo);
 714 }
 715
 716 static void
 717 ironlake_pp_states_setup(VADriverContextP ctx,
 718                          struct i965_post_processing_context *pp_context)
 719 {
 720     ironlake_pp_interface_descriptor_table(pp_context);
 721     ironlake_pp_vfe_state(pp_context);
 722     ironlake_pp_upload_constants(pp_context);
 723 }
 724
 725 static void
 726 ironlake_pp_pipeline_select(VADriverContextP ctx,
 727                             struct i965_post_processing_context *pp_context)
 728 {
 729     struct intel_batchbuffer *batch = pp_context->batch;
 730
 731     BEGIN_BATCH(batch, 1);
 732     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 733     ADVANCE_BATCH(batch);
 734 }
 735
 736 static void
 737 ironlake_pp_urb_layout(VADriverContextP ctx,
 738                        struct i965_post_processing_context *pp_context)
 739 {
 740     struct intel_batchbuffer *batch = pp_context->batch;
 741     unsigned int vfe_fence, cs_fence;
 742
 743     vfe_fence = pp_context->urb.cs_start;
 744     cs_fence = pp_context->urb.size;
 745
 746     BEGIN_BATCH(batch, 3);
 747     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 748     OUT_BATCH(batch, 0);
 749     OUT_BATCH(batch,
 750               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 751               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 752     ADVANCE_BATCH(batch);
 753 }
 754
 755 static void
 756 ironlake_pp_state_base_address(VADriverContextP ctx,
 757                                struct i965_post_processing_context *pp_context)
 758 {
 759     struct intel_batchbuffer *batch = pp_context->batch;
 760
 761     BEGIN_BATCH(batch, 8);
 762     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 763     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 764     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 765     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 766     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 767     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 768     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 769     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 770     ADVANCE_BATCH(batch);
 771 }
 772
 773 static void
 774 ironlake_pp_state_pointers(VADriverContextP ctx,
 775                            struct i965_post_processing_context *pp_context)
 776 {
 777     struct intel_batchbuffer *batch = pp_context->batch;
 778
 779     BEGIN_BATCH(batch, 3);
 780     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 781     OUT_BATCH(batch, 0);
 782     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 783     ADVANCE_BATCH(batch);
 784 }
 785
 786 static void
 787 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 788                           struct i965_post_processing_context *pp_context)
 789 {
 790     struct intel_batchbuffer *batch = pp_context->batch;
 791
 792     BEGIN_BATCH(batch, 2);
 793     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 794     OUT_BATCH(batch,
 795               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 796               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 797     ADVANCE_BATCH(batch);
 798 }
 799
 800 static void
 801 ironlake_pp_constant_buffer(VADriverContextP ctx,
 802                             struct i965_post_processing_context *pp_context)
 803 {
 804     struct intel_batchbuffer *batch = pp_context->batch;
 805
 806     BEGIN_BATCH(batch, 2);
 807     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 808     OUT_RELOC(batch, pp_context->curbe.bo,
 809               I915_GEM_DOMAIN_INSTRUCTION, 0,
 810               pp_context->urb.size_cs_entry - 1);
 811     ADVANCE_BATCH(batch);
 812 }
 813
 814 static void
 815 ironlake_pp_object_walker(VADriverContextP ctx,
 816                           struct i965_post_processing_context *pp_context)
 817 {
 818     struct intel_batchbuffer *batch = pp_context->batch;
 819     int x, x_steps, y, y_steps;
 820     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
 821
 822     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
 823     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
 824
 825     for (y = 0; y < y_steps; y++) {
 826         for (x = 0; x < x_steps; x++) {
 827             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
 828                 BEGIN_BATCH(batch, 20);
 829                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
 830                 OUT_BATCH(batch, 0);
 831                 OUT_BATCH(batch, 0); /* no indirect data */
 832                 OUT_BATCH(batch, 0);
 833
 834                 /* inline data grf 5-6 */
 835                 assert(sizeof(*pp_inline_parameter) == 64);
 836                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
 837
 838                 ADVANCE_BATCH(batch);
 839             }
 840         }
 841     }
 842 }
 843
 844 static void
 845 ironlake_pp_pipeline_setup(VADriverContextP ctx,
 846                            struct i965_post_processing_context *pp_context)
 847 {
 848     struct intel_batchbuffer *batch = pp_context->batch;
 849
 850     intel_batchbuffer_start_atomic(batch, 0x1000);
 851     intel_batchbuffer_emit_mi_flush(batch);
 852     ironlake_pp_pipeline_select(ctx, pp_context);
 853     ironlake_pp_state_base_address(ctx, pp_context);
 854     ironlake_pp_state_pointers(ctx, pp_context);
 855     ironlake_pp_urb_layout(ctx, pp_context);
 856     ironlake_pp_cs_urb_layout(ctx, pp_context);
 857     ironlake_pp_constant_buffer(ctx, pp_context);
 858     ironlake_pp_object_walker(ctx, pp_context);
 859     intel_batchbuffer_end_atomic(batch);
 860 }
 861
 862 static void
 863 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 864                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 865                           int width, int height, int pitch, int format,
 866                           int index, int is_target)
 867 {
 868     struct i965_surface_state *ss;
 869     dri_bo *ss_bo;
 870     unsigned int tiling;
 871     unsigned int swizzle;
 872
 873     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 874     ss_bo = pp_context->surface_state_binding_table.bo;
 875     assert(ss_bo);
 876
 877     dri_bo_map(ss_bo, True);
 878     assert(ss_bo->virtual);
 879     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 880     memset(ss, 0, sizeof(*ss));
 881     ss->ss0.surface_type = I965_SURFACE_2D;
 882     ss->ss0.surface_format = format;
 883     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 884     ss->ss2.width = width - 1;
 885     ss->ss2.height = height - 1;
 886     ss->ss3.pitch = pitch - 1;
 887     pp_set_surface_tiling(ss, tiling);
 888     dri_bo_emit_reloc(ss_bo,
 889                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 890                       surf_bo_offset,
 891                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 892                       surf_bo);
 893     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 894     dri_bo_unmap(ss_bo);
 895 }
 896
 897 static void
 898 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 899                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 900                            int width, int height, int wpitch,
 901                            int xoffset, int yoffset,
 902                            int format, int interleave_chroma,
 903                            int index)
 904 {
 905     struct i965_surface_state2 *ss2;
 906     dri_bo *ss2_bo;
 907     unsigned int tiling;
 908     unsigned int swizzle;
 909
 910     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 911     ss2_bo = pp_context->surface_state_binding_table.bo;
 912     assert(ss2_bo);
 913
 914     dri_bo_map(ss2_bo, True);
 915     assert(ss2_bo->virtual);
 916     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 917     memset(ss2, 0, sizeof(*ss2));
 918     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 919     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 920     ss2->ss1.width = width - 1;
 921     ss2->ss1.height = height - 1;
 922     ss2->ss2.pitch = wpitch - 1;
 923     ss2->ss2.interleave_chroma = interleave_chroma;
 924     ss2->ss2.surface_format = format;
 925     ss2->ss3.x_offset_for_cb = xoffset;
 926     ss2->ss3.y_offset_for_cb = yoffset;
 927     pp_set_surface2_tiling(ss2, tiling);
 928     dri_bo_emit_reloc(ss2_bo,
 929                       I915_GEM_DOMAIN_RENDER, 0,
 930                       surf_bo_offset,
 931                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
 932                       surf_bo);
 933     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 934     dri_bo_unmap(ss2_bo);
 935 }
 936
 937 static void
 938 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 939                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 940                           int width, int height, int pitch, int format,
 941                           int index, int is_target)
 942 {
 943     struct gen7_surface_state *ss;
 944     dri_bo *ss_bo;
 945     unsigned int tiling;
 946     unsigned int swizzle;
 947
 948     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 949     ss_bo = pp_context->surface_state_binding_table.bo;
 950     assert(ss_bo);
 951
 952     dri_bo_map(ss_bo, True);
 953     assert(ss_bo->virtual);
 954     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 955     memset(ss, 0, sizeof(*ss));
 956     ss->ss0.surface_type = I965_SURFACE_2D;
 957     ss->ss0.surface_format = format;
 958     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 959     ss->ss2.width = width - 1;
 960     ss->ss2.height = height - 1;
 961     ss->ss3.pitch = pitch - 1;
 962     gen7_pp_set_surface_tiling(ss, tiling);
 963     dri_bo_emit_reloc(ss_bo,
 964                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 965                       surf_bo_offset,
 966                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 967                       surf_bo);
 968     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 969     dri_bo_unmap(ss_bo);
 970 }
 971
 972 static void
 973 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 974                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 975                            int width, int height, int wpitch,
 976                            int xoffset, int yoffset,
 977                            int format, int interleave_chroma,
 978                            int index)
 979 {
 980     struct gen7_surface_state2 *ss2;
 981     dri_bo *ss2_bo;
 982     unsigned int tiling;
 983     unsigned int swizzle;
 984
 985     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 986     ss2_bo = pp_context->surface_state_binding_table.bo;
 987     assert(ss2_bo);
 988
 989     dri_bo_map(ss2_bo, True);
 990     assert(ss2_bo->virtual);
 991     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 992     memset(ss2, 0, sizeof(*ss2));
 993     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 994     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 995     ss2->ss1.width = width - 1;
 996     ss2->ss1.height = height - 1;
 997     ss2->ss2.pitch = wpitch - 1;
 998     ss2->ss2.interleave_chroma = interleave_chroma;
 999     ss2->ss2.surface_format = format;
1000     ss2->ss3.x_offset_for_cb = xoffset;
1001     ss2->ss3.y_offset_for_cb = yoffset;
1002     gen7_pp_set_surface2_tiling(ss2, tiling);
1003     dri_bo_emit_reloc(ss2_bo,
1004                       I915_GEM_DOMAIN_RENDER, 0,
1005                       surf_bo_offset,
1006                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1007                       surf_bo);
1008     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1009     dri_bo_unmap(ss2_bo);
1010 }
1011
1012 static void
1013 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1014                                 const struct i965_surface *surface,
1015                                 int base_index, int is_target,
1016                                 int *width, int *height, int *pitch, int *offset)
1017 {
1018     struct i965_driver_data *i965 = i965_driver_data(ctx);
1019     struct object_surface *obj_surface;
1020     struct object_image *obj_image;
1021     dri_bo *bo;
1022     int fourcc = pp_get_surface_fourcc(ctx, surface);
1023     const int Y = 0;
1024     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1025     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1026     const int UV = 1;
1027     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1028
1029     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1030         obj_surface = SURFACE(surface->id);
1031         bo = obj_surface->bo;
1032         width[0] = obj_surface->orig_width;
1033         height[0] = obj_surface->orig_height;
1034         pitch[0] = obj_surface->width;
1035         offset[0] = 0;
1036
1037         if (interleaved_uv) {
1038             width[1] = obj_surface->orig_width;
1039             height[1] = obj_surface->orig_height / 2;
1040             pitch[1] = obj_surface->width;
1041             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1042         } else {
1043             width[1] = obj_surface->orig_width / 2;
1044             height[1] = obj_surface->orig_height / 2;
1045             pitch[1] = obj_surface->width / 2;
1046             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1047             width[2] = obj_surface->orig_width / 2;
1048             height[2] = obj_surface->orig_height / 2;
1049             pitch[2] = obj_surface->width / 2;
1050             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1051         }
1052     } else {
1053         obj_image = IMAGE(surface->id);
1054         bo = obj_image->bo;
1055         width[0] = obj_image->image.width;
1056         height[0] = obj_image->image.height;
1057         pitch[0] = obj_image->image.pitches[0];
1058         offset[0] = obj_image->image.offsets[0];
1059
1060         if (interleaved_uv) {
1061             width[1] = obj_image->image.width;
1062             height[1] = obj_image->image.height / 2;
1063             pitch[1] = obj_image->image.pitches[1];
1064             offset[1] = obj_image->image.offsets[1];
1065         } else {
1066             width[1] = obj_image->image.width / 2;
1067             height[1] = obj_image->image.height / 2;
1068             pitch[1] = obj_image->image.pitches[1];
1069             offset[1] = obj_image->image.offsets[1];
1070             width[2] = obj_image->image.width / 2;
1071             height[2] = obj_image->image.height / 2;
1072             pitch[2] = obj_image->image.pitches[2];
1073             offset[2] = obj_image->image.offsets[2];
1074         }
1075     }
1076
1077     /* Y surface */
1078     i965_pp_set_surface_state(ctx, pp_context,
1079                               bo, offset[Y],
1080                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1081                               base_index, is_target);
1082
1083     if (interleaved_uv) {
1084         i965_pp_set_surface_state(ctx, pp_context,
1085                                   bo, offset[UV],
1086                                   width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1087                                   base_index + 1, is_target);
1088     } else {
1089         /* U surface */
1090         i965_pp_set_surface_state(ctx, pp_context,
1091                                   bo, offset[U],
1092                                   width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1093                                   base_index + 1, is_target);
1094
1095         /* V surface */
1096         i965_pp_set_surface_state(ctx, pp_context,
1097                                   bo, offset[V],
1098                                   width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1099                                   base_index + 2, is_target);
1100     }
1101
1102 }
1103
1104 static void
1105 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1106                                      const struct i965_surface *surface,
1107                                      int base_index, int is_target,
1108                                      int *width, int *height, int *pitch, int *offset)
1109 {
1110     struct i965_driver_data *i965 = i965_driver_data(ctx);
1111     struct object_surface *obj_surface;
1112     struct object_image *obj_image;
1113     dri_bo *bo;
1114     int fourcc = pp_get_surface_fourcc(ctx, surface);
1115     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1116                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1117     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1118                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1119     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1120
1121     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1122         obj_surface = SURFACE(surface->id);
1123         bo = obj_surface->bo;
1124         width[0] = obj_surface->orig_width;
1125         height[0] = obj_surface->orig_height;
1126         pitch[0] = obj_surface->width;
1127         offset[0] = 0;
1128
1129         width[1] = obj_surface->cb_cr_width;
1130         height[1] = obj_surface->cb_cr_height;
1131         pitch[1] = obj_surface->cb_cr_pitch;
1132         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1133
1134         width[2] = obj_surface->cb_cr_width;
1135         height[2] = obj_surface->cb_cr_height;
1136         pitch[2] = obj_surface->cb_cr_pitch;
1137         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1138     } else {
1139         obj_image = IMAGE(surface->id);
1140         bo = obj_image->bo;
1141         width[0] = obj_image->image.width;
1142         height[0] = obj_image->image.height;
1143         pitch[0] = obj_image->image.pitches[0];
1144         offset[0] = obj_image->image.offsets[0];
1145
1146         if (interleaved_uv) {
1147             width[1] = obj_image->image.width;
1148             height[1] = obj_image->image.height / 2;
1149             pitch[1] = obj_image->image.pitches[1];
1150             offset[1] = obj_image->image.offsets[1];
1151         } else {
1152             width[1] = obj_image->image.width / 2;
1153             height[1] = obj_image->image.height / 2;
1154             pitch[1] = obj_image->image.pitches[U];
1155             offset[1] = obj_image->image.offsets[U];
1156             width[2] = obj_image->image.width / 2;
1157             height[2] = obj_image->image.height / 2;
1158             pitch[2] = obj_image->image.pitches[V];
1159             offset[2] = obj_image->image.offsets[V];
1160         }
1161     }
1162
1163     if (is_target) {
1164         gen7_pp_set_surface_state(ctx, pp_context,
1165                                   bo, 0,
1166                                   width[0] / 4, height[0], pitch[0],
1167                                   I965_SURFACEFORMAT_R8_SINT,
1168                                   base_index, 1);
1169
1170         if (interleaved_uv) {
1171             gen7_pp_set_surface_state(ctx, pp_context,
1172                                       bo, offset[1],
1173                                       width[1] / 2, height[1], pitch[1],
1174                                       I965_SURFACEFORMAT_R8G8_SINT,
1175                                       base_index + 1, 1);
1176         } else {
1177             gen7_pp_set_surface_state(ctx, pp_context,
1178                                       bo, offset[1],
1179                                       width[1] / 4, height[1], pitch[1],
1180                                       I965_SURFACEFORMAT_R8_SINT,
1181                                       base_index + 1, 1);
1182             gen7_pp_set_surface_state(ctx, pp_context,
1183                                       bo, offset[2],
1184                                       width[2] / 4, height[2], pitch[2],
1185                                       I965_SURFACEFORMAT_R8_SINT,
1186                                       base_index + 2, 1);
1187         }
1188     } else {
1189         gen7_pp_set_surface2_state(ctx, pp_context,
1190                                    bo, offset[0],
1191                                    width[0], height[0], pitch[0],
1192                                    0, 0,
1193                                    SURFACE_FORMAT_Y8_UNORM, 0,
1194                                    base_index);
1195
1196         if (interleaved_uv) {
1197             gen7_pp_set_surface2_state(ctx, pp_context,
1198                                        bo, offset[1],
1199                                        width[1], height[1], pitch[1],
1200                                        0, 0,
1201                                        SURFACE_FORMAT_R8B8_UNORM, 0,
1202                                        base_index + 1);
1203         } else {
1204             gen7_pp_set_surface2_state(ctx, pp_context,
1205                                        bo, offset[1],
1206                                        width[1], height[1], pitch[1],
1207                                        0, 0,
1208                                        SURFACE_FORMAT_R8_UNORM, 0,
1209                                        base_index + 1);
1210             gen7_pp_set_surface2_state(ctx, pp_context,
1211                                        bo, offset[1],
1212                                        width[2], height[2], pitch[2],
1213                                        0, 0,
1214                                        SURFACE_FORMAT_R8_UNORM, 0,
1215                                        base_index + 2);
1216         }
1217     }
1218 }
1219
1220 static int
1221 pp_null_x_steps(void *private_context)
1222 {
1223     return 1;
1224 }
1225
1226 static int
1227 pp_null_y_steps(void *private_context)
1228 {
1229     return 1;
1230 }
1231
1232 static int
1233 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1234 {
1235     return 0;
1236 }
1237
1238 static VAStatus
1239 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1240                    const struct i965_surface *src_surface,
1241                    const VARectangle *src_rect,
1242                    struct i965_surface *dst_surface,
1243                    const VARectangle *dst_rect,
1244                    void *filter_param)
1245 {
1246     /* private function & data */
1247     pp_context->pp_x_steps = pp_null_x_steps;
1248     pp_context->pp_y_steps = pp_null_y_steps;
1249     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1250
1251     dst_surface->flags = src_surface->flags;
1252
1253     return VA_STATUS_SUCCESS;
1254 }
1255
1256 static int
1257 pp_load_save_x_steps(void *private_context)
1258 {
1259     return 1;
1260 }
1261
1262 static int
1263 pp_load_save_y_steps(void *private_context)
1264 {
1265     struct pp_load_save_context *pp_load_save_context = private_context;
1266
1267     return pp_load_save_context->dest_h / 8;
1268 }
1269
1270 static int
1271 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1272 {
1273     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1274
1275     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1276     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1277     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1278     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1279
1280     return 0;
1281 }
1282
1283 static VAStatus
1284 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1285                                 const struct i965_surface *src_surface,
1286                                 const VARectangle *src_rect,
1287                                 struct i965_surface *dst_surface,
1288                                 const VARectangle *dst_rect,
1289                                 void *filter_param)
1290 {
1291     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1292     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1293     int width[3], height[3], pitch[3], offset[3];
1294     const int Y = 0;
1295
1296     /* source surface */
1297     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1298                                     width, height, pitch, offset);
1299
1300     /* destination surface */
1301     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1302                                     width, height, pitch, offset);
1303
1304     /* private function & data */
1305     pp_context->pp_x_steps = pp_load_save_x_steps;
1306     pp_context->pp_y_steps = pp_load_save_y_steps;
1307     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1308     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1309     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1310
1311     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1312     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1313
1314     dst_surface->flags = src_surface->flags;
1315
1316     return VA_STATUS_SUCCESS;
1317 }
1318
1319 static int
1320 pp_scaling_x_steps(void *private_context)
1321 {
1322     return 1;
1323 }
1324
1325 static int
1326 pp_scaling_y_steps(void *private_context)
1327 {
1328     struct pp_scaling_context *pp_scaling_context = private_context;
1329
1330     return pp_scaling_context->dest_h / 8;
1331 }
1332
1333 static int
1334 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1335 {
1336     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1337     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1338     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1339     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1340     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1341
1342     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1343     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1344     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1345     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1346
1347     return 0;
1348 }
1349
1350 static VAStatus
1351 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1352                            const struct i965_surface *src_surface,
1353                            const VARectangle *src_rect,
1354                            struct i965_surface *dst_surface,
1355                            const VARectangle *dst_rect,
1356                            void *filter_param)
1357 {
1358     struct i965_driver_data *i965 = i965_driver_data(ctx);
1359     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1360     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1361     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1362     struct object_surface *obj_surface;
1363     struct i965_sampler_state *sampler_state;
1364     int in_w, in_h, in_wpitch, in_hpitch;
1365     int out_w, out_h, out_wpitch, out_hpitch;
1366
1367     /* source surface */
1368     obj_surface = SURFACE(src_surface->id);
1369     in_w = obj_surface->orig_width;
1370     in_h = obj_surface->orig_height;
1371     in_wpitch = obj_surface->width;
1372     in_hpitch = obj_surface->height;
1373
1374     /* source Y surface index 1 */
1375     i965_pp_set_surface_state(ctx, pp_context,
1376                               obj_surface->bo, 0,
1377                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1378                               1, 0);
1379
1380     /* source UV surface index 2 */
1381     i965_pp_set_surface_state(ctx, pp_context,
1382                               obj_surface->bo, in_wpitch * in_hpitch,
1383                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1384                               2, 0);
1385
1386     /* destination surface */
1387     obj_surface = SURFACE(dst_surface->id);
1388     out_w = obj_surface->orig_width;
1389     out_h = obj_surface->orig_height;
1390     out_wpitch = obj_surface->width;
1391     out_hpitch = obj_surface->height;
1392
1393     /* destination Y surface index 7 */
1394     i965_pp_set_surface_state(ctx, pp_context,
1395                               obj_surface->bo, 0,
1396                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1397                               7, 1);
1398
1399     /* destination UV surface index 8 */
1400     i965_pp_set_surface_state(ctx, pp_context,
1401                               obj_surface->bo, out_wpitch * out_hpitch,
1402                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1403                               8, 1);
1404
1405     /* sampler state */
1406     dri_bo_map(pp_context->sampler_state_table.bo, True);
1407     assert(pp_context->sampler_state_table.bo->virtual);
1408     sampler_state = pp_context->sampler_state_table.bo->virtual;
1409
1410     /* SIMD16 Y index 1 */
1411     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1412     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1413     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1414     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1415     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1416
1417     /* SIMD16 UV index 2 */
1418     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1419     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1420     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1421     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1422     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1423
1424     dri_bo_unmap(pp_context->sampler_state_table.bo);
1425
1426     /* private function & data */
1427     pp_context->pp_x_steps = pp_scaling_x_steps;
1428     pp_context->pp_y_steps = pp_scaling_y_steps;
1429     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1430
1431     pp_scaling_context->dest_x = dst_rect->x;
1432     pp_scaling_context->dest_y = dst_rect->y;
1433     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1434     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1435     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1436     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1437
1438     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1439
1440     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1441     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1442     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1443     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1444     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1445
1446     dst_surface->flags = src_surface->flags;
1447
1448     return VA_STATUS_SUCCESS;
1449 }
1450
1451 static int
1452 pp_avs_x_steps(void *private_context)
1453 {
1454     struct pp_avs_context *pp_avs_context = private_context;
1455
1456     return pp_avs_context->dest_w / 16;
1457 }
1458
1459 static int
1460 pp_avs_y_steps(void *private_context)
1461 {
1462     return 1;
1463 }
1464
1465 static int
1466 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1467 {
1468     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1469     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1470     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1471     float src_x_steping, src_y_steping, video_step_delta;
1472     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1473
1474     if (tmp_w >= pp_avs_context->dest_w) {
1475         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1476         pp_inline_parameter->grf6.video_step_delta = 0;
1477
1478         if (x == 0) {
1479             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1480                 pp_avs_context->src_normalized_x;
1481         } else {
1482             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1483             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1484             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1485                 16 * 15 * video_step_delta / 2;
1486         }
1487     } else {
1488         int n0, n1, n2, nls_left, nls_right;
1489         int factor_a = 5, factor_b = 4;
1490         float f;
1491
1492         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1493         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1494         n2 = tmp_w / (16 * factor_a);
1495         nls_left = n0 + n2;
1496         nls_right = n1 + n2;
1497         f = (float) n2 * 16 / tmp_w;
1498
1499         if (n0 < 5) {
1500             pp_inline_parameter->grf6.video_step_delta = 0.0;
1501
1502             if (x == 0) {
1503                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1504                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1505             } else {
1506                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1507                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1508                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1509                     16 * 15 * video_step_delta / 2;
1510             }
1511         } else {
1512             if (x < nls_left) {
1513                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1514                 float a = f / (nls_left * 16 * factor_b);
1515                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1516
1517                 pp_inline_parameter->grf6.video_step_delta = b;
1518
1519                 if (x == 0) {
1520                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1521                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1522                 } else {
1523                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1524                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1525                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1526                         16 * 15 * video_step_delta / 2;
1527                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1528                 }
1529             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1530                 /* scale the center linearly */
1531                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1532                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1533                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1534                     16 * 15 * video_step_delta / 2;
1535                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1536                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1537             } else {
1538                 float a = f / (nls_right * 16 * factor_b);
1539                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1540
1541                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1542                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1543                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1544                     16 * 15 * video_step_delta / 2;
1545                 pp_inline_parameter->grf6.video_step_delta = -b;
1546
1547                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1548                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1549                 else
1550                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1551             }
1552         }
1553     }
1554
1555     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1556     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1557     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1558     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1559
1560     return 0;
1561 }
1562
1563 static VAStatus
1564 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1565                        const struct i965_surface *src_surface,
1566                        const VARectangle *src_rect,
1567                        struct i965_surface *dst_surface,
1568                        const VARectangle *dst_rect,
1569                        void *filter_param)
1570 {
1571     struct i965_driver_data *i965 = i965_driver_data(ctx);
1572     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1573     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1574     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1575     struct object_surface *obj_surface;
1576     struct i965_sampler_8x8 *sampler_8x8;
1577     struct i965_sampler_8x8_state *sampler_8x8_state;
1578     int index;
1579     int in_w, in_h, in_wpitch, in_hpitch;
1580     int out_w, out_h, out_wpitch, out_hpitch;
1581     int i;
1582
1583     /* surface */
1584     obj_surface = SURFACE(src_surface->id);
1585     in_w = obj_surface->orig_width;
1586     in_h = obj_surface->orig_height;
1587     in_wpitch = obj_surface->width;
1588     in_hpitch = obj_surface->height;
1589
1590     /* source Y surface index 1 */
1591     i965_pp_set_surface2_state(ctx, pp_context,
1592                                obj_surface->bo, 0,
1593                                in_w, in_h, in_wpitch,
1594                                0, 0,
1595                                SURFACE_FORMAT_Y8_UNORM, 0,
1596                                1);
1597
1598     /* source UV surface index 2 */
1599     i965_pp_set_surface2_state(ctx, pp_context,
1600                                obj_surface->bo, in_wpitch * in_hpitch,
1601                                in_w / 2, in_h / 2, in_wpitch,
1602                                0, 0,
1603                                SURFACE_FORMAT_R8B8_UNORM, 0,
1604                                2);
1605
1606     /* destination surface */
1607     obj_surface = SURFACE(dst_surface->id);
1608     out_w = obj_surface->orig_width;
1609     out_h = obj_surface->orig_height;
1610     out_wpitch = obj_surface->width;
1611     out_hpitch = obj_surface->height;
1612     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1613
1614     /* destination Y surface index 7 */
1615     i965_pp_set_surface_state(ctx, pp_context,
1616                               obj_surface->bo, 0,
1617                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1618                               7, 1);
1619
1620     /* destination UV surface index 8 */
1621     i965_pp_set_surface_state(ctx, pp_context,
1622                               obj_surface->bo, out_wpitch * out_hpitch,
1623                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1624                               8, 1);
1625
1626     /* sampler 8x8 state */
1627     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1628     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1629     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1630     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1631     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1632
1633     for (i = 0; i < 17; i++) {
1634         /* for Y channel, currently ignore */
1635         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1636         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1637         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1638         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1639         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1640         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1641         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1642         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1643         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1644         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1645         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1646         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1647         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1648         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1649         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1650         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1651         /* for U/V channel, 0.25 */
1652         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1653         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1654         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1655         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1656         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1657         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1658         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1659         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1660         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1661         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1662         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1663         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1664         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1665         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1666         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1667         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1668     }
1669
1670     sampler_8x8_state->dw136.default_sharpness_level = 0;
1671     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1672     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1673     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1674     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1675
1676     /* sampler 8x8 */
1677     dri_bo_map(pp_context->sampler_state_table.bo, True);
1678     assert(pp_context->sampler_state_table.bo->virtual);
1679     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1680     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1681
1682     /* sample_8x8 Y index 1 */
1683     index = 1;
1684     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1685     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1686     sampler_8x8[index].dw0.ief_bypass = 1;
1687     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1688     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1689     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1690     sampler_8x8[index].dw2.global_noise_estimation = 22;
1691     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1692     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1693     sampler_8x8[index].dw3.strong_edge_weight = 7;
1694     sampler_8x8[index].dw3.regular_weight = 2;
1695     sampler_8x8[index].dw3.non_edge_weight = 0;
1696     sampler_8x8[index].dw3.gain_factor = 40;
1697     sampler_8x8[index].dw4.steepness_boost = 0;
1698     sampler_8x8[index].dw4.steepness_threshold = 0;
1699     sampler_8x8[index].dw4.mr_boost = 0;
1700     sampler_8x8[index].dw4.mr_threshold = 5;
1701     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1702     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1703     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1704     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1705     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1706     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1707     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1708     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1709     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1710     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1711     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1712     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1713     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1714     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1715     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1716     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1717     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1718     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1719     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1720     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1721     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1722     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1723     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1724     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1725     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1726     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1727     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1728     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1729     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1730     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1731     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1732     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1733     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1734     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1735     sampler_8x8[index].dw13.limiter_boost = 0;
1736     sampler_8x8[index].dw13.minimum_limiter = 10;
1737     sampler_8x8[index].dw13.maximum_limiter = 11;
1738     sampler_8x8[index].dw14.clip_limiter = 130;
1739     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1740                       I915_GEM_DOMAIN_RENDER,
1741                       0,
1742                       0,
1743                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1744                       pp_context->sampler_state_table.bo_8x8);
1745
1746     /* sample_8x8 UV index 2 */
1747     index = 2;
1748     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1749     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1750     sampler_8x8[index].dw0.ief_bypass = 1;
1751     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1752     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1753     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1754     sampler_8x8[index].dw2.global_noise_estimation = 22;
1755     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1756     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1757     sampler_8x8[index].dw3.strong_edge_weight = 7;
1758     sampler_8x8[index].dw3.regular_weight = 2;
1759     sampler_8x8[index].dw3.non_edge_weight = 0;
1760     sampler_8x8[index].dw3.gain_factor = 40;
1761     sampler_8x8[index].dw4.steepness_boost = 0;
1762     sampler_8x8[index].dw4.steepness_threshold = 0;
1763     sampler_8x8[index].dw4.mr_boost = 0;
1764     sampler_8x8[index].dw4.mr_threshold = 5;
1765     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1766     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1767     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1768     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1769     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1770     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1771     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1772     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1773     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1774     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1775     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1776     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1777     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1778     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1779     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1780     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1781     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1782     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1783     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1784     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1785     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1786     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1787     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1788     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1789     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1790     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1791     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1792     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1793     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1794     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1795     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1796     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1797     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1798     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1799     sampler_8x8[index].dw13.limiter_boost = 0;
1800     sampler_8x8[index].dw13.minimum_limiter = 10;
1801     sampler_8x8[index].dw13.maximum_limiter = 11;
1802     sampler_8x8[index].dw14.clip_limiter = 130;
1803     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1804                       I915_GEM_DOMAIN_RENDER,
1805                       0,
1806                       0,
1807                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1808                       pp_context->sampler_state_table.bo_8x8);
1809
1810     dri_bo_unmap(pp_context->sampler_state_table.bo);
1811
1812     /* private function & data */
1813     pp_context->pp_x_steps = pp_avs_x_steps;
1814     pp_context->pp_y_steps = pp_avs_y_steps;
1815     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
1816
1817     pp_avs_context->dest_x = dst_rect->x;
1818     pp_avs_context->dest_y = dst_rect->y;
1819     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
1820     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1821     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
1822     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
1823     pp_avs_context->src_w = src_rect->width;
1824     pp_avs_context->src_h = src_rect->height;
1825
1826     pp_static_parameter->grf4.r4_2.avs.nlas = 1;
1827     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1828
1829     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1830     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
1831     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
1832     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1833     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1834     pp_inline_parameter->grf6.video_step_delta = 0.0;
1835
1836     dst_surface->flags = src_surface->flags;
1837
1838     return VA_STATUS_SUCCESS;
1839 }
1840
1841 static int
1842 gen7_pp_avs_x_steps(void *private_context)
1843 {
1844     struct pp_avs_context *pp_avs_context = private_context;
1845
1846     return pp_avs_context->dest_w / 16;
1847 }
1848
1849 static int
1850 gen7_pp_avs_y_steps(void *private_context)
1851 {
1852     struct pp_avs_context *pp_avs_context = private_context;
1853
1854     return pp_avs_context->dest_h / 16;
1855 }
1856
1857 static int
1858 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1859 {
1860     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1861     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1862
1863     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1864     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
1865     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
1866     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
1867
1868     return 0;
1869 }
1870
1871 static VAStatus
1872 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1873                            const struct i965_surface *src_surface,
1874                            const VARectangle *src_rect,
1875                            struct i965_surface *dst_surface,
1876                            const VARectangle *dst_rect,
1877                            void *filter_param)
1878 {
1879     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1880     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1881     struct gen7_sampler_8x8 *sampler_8x8;
1882     struct i965_sampler_8x8_state *sampler_8x8_state;
1883     int index, i;
1884     int width[3], height[3], pitch[3], offset[3];
1885
1886     /* source surface */
1887     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
1888                                          width, height, pitch, offset);
1889
1890     /* destination surface */
1891     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
1892                                          width, height, pitch, offset);
1893
1894     /* sampler 8x8 state */
1895     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1896     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1897     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1898     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1899     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1900
1901     for (i = 0; i < 17; i++) {
1902         /* for Y channel, currently ignore */
1903         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
1904         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
1905         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
1906         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
1907         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
1908         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
1909         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
1910         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
1911         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
1912         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
1913         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
1914         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
1915         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
1916         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
1917         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
1918         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
1919         /* for U/V channel, 0.25 */
1920         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1921         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1922         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1923         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1924         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1925         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1926         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1927         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1928         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1929         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1930         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1931         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1932         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1933         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1934         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1935         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1936     }
1937
1938     sampler_8x8_state->dw136.default_sharpness_level = 0;
1939     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1940     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1941     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1942     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1943
1944     /* sampler 8x8 */
1945     dri_bo_map(pp_context->sampler_state_table.bo, True);
1946     assert(pp_context->sampler_state_table.bo->virtual);
1947     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
1948     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1949
1950     /* sample_8x8 Y index 4 */
1951     index = 4;
1952     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1953     sampler_8x8[index].dw0.global_noise_estimation = 255;
1954     sampler_8x8[index].dw0.ief_bypass = 1;
1955
1956     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1957
1958     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1959     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1960     sampler_8x8[index].dw2.r5x_coefficient = 9;
1961     sampler_8x8[index].dw2.r5cx_coefficient = 8;
1962     sampler_8x8[index].dw2.r5c_coefficient = 3;
1963
1964     sampler_8x8[index].dw3.r3x_coefficient = 27;
1965     sampler_8x8[index].dw3.r3c_coefficient = 5;
1966     sampler_8x8[index].dw3.gain_factor = 40;
1967     sampler_8x8[index].dw3.non_edge_weight = 1;
1968     sampler_8x8[index].dw3.regular_weight = 2;
1969     sampler_8x8[index].dw3.strong_edge_weight = 7;
1970     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
1971
1972     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1973                       I915_GEM_DOMAIN_RENDER,
1974                       0,
1975                       0,
1976                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1977                       pp_context->sampler_state_table.bo_8x8);
1978
1979     /* sample_8x8 UV index 8 */
1980     index = 8;
1981     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1982     sampler_8x8[index].dw0.disable_8x8_filter = 0;
1983     sampler_8x8[index].dw0.global_noise_estimation = 255;
1984     sampler_8x8[index].dw0.ief_bypass = 1;
1985     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1986     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1987     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1988     sampler_8x8[index].dw2.r5x_coefficient = 9;
1989     sampler_8x8[index].dw2.r5cx_coefficient = 8;
1990     sampler_8x8[index].dw2.r5c_coefficient = 3;
1991     sampler_8x8[index].dw3.r3x_coefficient = 27;
1992     sampler_8x8[index].dw3.r3c_coefficient = 5;
1993     sampler_8x8[index].dw3.gain_factor = 40;
1994     sampler_8x8[index].dw3.non_edge_weight = 1;
1995     sampler_8x8[index].dw3.regular_weight = 2;
1996     sampler_8x8[index].dw3.strong_edge_weight = 7;
1997     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
1998
1999     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2000                       I915_GEM_DOMAIN_RENDER,
2001                       0,
2002                       0,
2003                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2004                       pp_context->sampler_state_table.bo_8x8);
2005
2006     dri_bo_unmap(pp_context->sampler_state_table.bo);
2007
2008     /* sampler_8x8 V, index 12 */
2009     index = 12;
2010     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2011     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2012     sampler_8x8[index].dw0.global_noise_estimation = 255;
2013     sampler_8x8[index].dw0.ief_bypass = 1;
2014     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2015     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2016     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2017     sampler_8x8[index].dw2.r5x_coefficient = 9;
2018     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2019     sampler_8x8[index].dw2.r5c_coefficient = 3;
2020     sampler_8x8[index].dw3.r3x_coefficient = 27;
2021     sampler_8x8[index].dw3.r3c_coefficient = 5;
2022     sampler_8x8[index].dw3.gain_factor = 40;
2023     sampler_8x8[index].dw3.non_edge_weight = 1;
2024     sampler_8x8[index].dw3.regular_weight = 2;
2025     sampler_8x8[index].dw3.strong_edge_weight = 7;
2026     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2027
2028     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2029                       I915_GEM_DOMAIN_RENDER,
2030                       0,
2031                       0,
2032                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2033                       pp_context->sampler_state_table.bo_8x8);
2034
2035     dri_bo_unmap(pp_context->sampler_state_table.bo);
2036
2037     /* private function & data */
2038     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2039     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2040     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2041
2042     pp_avs_context->dest_x = dst_rect->x;
2043     pp_avs_context->dest_y = dst_rect->y;
2044     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2045     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2046     pp_avs_context->src_w = src_rect->width;
2047     pp_avs_context->src_h = src_rect->height;
2048
2049     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2050     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / pp_avs_context->dest_w;
2051     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2052     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2053     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / pp_avs_context->dest_w;
2054
2055     dst_surface->flags = src_surface->flags;
2056
2057     return VA_STATUS_SUCCESS;
2058 }
2059
2060 static int
2061 pp_dndi_x_steps(void *private_context)
2062 {
2063     return 1;
2064 }
2065
2066 static int
2067 pp_dndi_y_steps(void *private_context)
2068 {
2069     struct pp_dndi_context *pp_dndi_context = private_context;
2070
2071     return pp_dndi_context->dest_h / 4;
2072 }
2073
2074 static int
2075 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2076 {
2077     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2078
2079     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2080     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2081
2082     return 0;
2083 }
2084
2085 static VAStatus
2086 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2087                         const struct i965_surface *src_surface,
2088                         const VARectangle *src_rect,
2089                         struct i965_surface *dst_surface,
2090                         const VARectangle *dst_rect,
2091                         void *filter_param)
2092 {
2093     struct i965_driver_data *i965 = i965_driver_data(ctx);
2094     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2095     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2096     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2097     struct object_surface *obj_surface;
2098     struct i965_sampler_dndi *sampler_dndi;
2099     int index;
2100     int w, h;
2101     int orig_w, orig_h;
2102     int dndi_top_first = 1;
2103
2104     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2105         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2106
2107     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2108         dndi_top_first = 1;
2109     else
2110         dndi_top_first = 0;
2111
2112     /* surface */
2113     obj_surface = SURFACE(src_surface->id);
2114     orig_w = obj_surface->orig_width;
2115     orig_h = obj_surface->orig_height;
2116     w = obj_surface->width;
2117     h = obj_surface->height;
2118
2119     if (pp_context->stmm.bo == NULL) {
2120         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2121                                            "STMM surface",
2122                                            w * h,
2123                                            4096);
2124         assert(pp_context->stmm.bo);
2125     }
2126
2127     /* source UV surface index 2 */
2128     i965_pp_set_surface_state(ctx, pp_context,
2129                               obj_surface->bo, w * h,
2130                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2131                               2, 0);
2132
2133     /* source YUV surface index 4 */
2134     i965_pp_set_surface2_state(ctx, pp_context,
2135                                obj_surface->bo, 0,
2136                                orig_w, orig_h, w,
2137                                0, h,
2138                                SURFACE_FORMAT_PLANAR_420_8, 1,
2139                                4);
2140
2141     /* source STMM surface index 20 */
2142     i965_pp_set_surface_state(ctx, pp_context,
2143                               pp_context->stmm.bo, 0,
2144                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2145                               20, 1);
2146
2147     /* destination surface */
2148     obj_surface = SURFACE(dst_surface->id);
2149     orig_w = obj_surface->orig_width;
2150     orig_h = obj_surface->orig_height;
2151     w = obj_surface->width;
2152     h = obj_surface->height;
2153
2154     /* destination Y surface index 7 */
2155     i965_pp_set_surface_state(ctx, pp_context,
2156                               obj_surface->bo, 0,
2157                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2158                               7, 1);
2159
2160     /* destination UV surface index 8 */
2161     i965_pp_set_surface_state(ctx, pp_context,
2162                               obj_surface->bo, w * h,
2163                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2164                               8, 1);
2165     /* sampler dndi */
2166     dri_bo_map(pp_context->sampler_state_table.bo, True);
2167     assert(pp_context->sampler_state_table.bo->virtual);
2168     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2169     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2170
2171     /* sample dndi index 1 */
2172     index = 0;
2173     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2174     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2175     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2176     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2177
2178     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2179     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2180     sampler_dndi[index].dw1.stmm_c2 = 1;
2181     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2182     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2183
2184     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2185     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2186     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2187     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2188
2189     sampler_dndi[index].dw3.maximum_stmm = 128;
2190     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2191     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2192     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2193     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2194
2195     sampler_dndi[index].dw4.sdi_delta = 8;
2196     sampler_dndi[index].dw4.sdi_threshold = 128;
2197     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2198     sampler_dndi[index].dw4.stmm_shift_up = 0;
2199     sampler_dndi[index].dw4.stmm_shift_down = 0;
2200     sampler_dndi[index].dw4.minimum_stmm = 0;
2201
2202     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2203     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2204     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2205     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2206
2207     sampler_dndi[index].dw6.dn_enable = 1;
2208     sampler_dndi[index].dw6.di_enable = 1;
2209     sampler_dndi[index].dw6.di_partial = 0;
2210     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2211     sampler_dndi[index].dw6.dndi_stream_id = 0;
2212     sampler_dndi[index].dw6.dndi_first_frame = 1;
2213     sampler_dndi[index].dw6.progressive_dn = 0;
2214     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2215     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2216     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2217
2218     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2219     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2220     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2221     sampler_dndi[index].dw7.column_width_minus1 = 0;
2222
2223     dri_bo_unmap(pp_context->sampler_state_table.bo);
2224
2225     /* private function & data */
2226     pp_context->pp_x_steps = pp_dndi_x_steps;
2227     pp_context->pp_y_steps = pp_dndi_y_steps;
2228     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2229
2230     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2231     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2232     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2233     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2234
2235     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2236     pp_inline_parameter->grf5.number_blocks = w / 16;
2237     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2238     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2239
2240     pp_dndi_context->dest_w = w;
2241     pp_dndi_context->dest_h = h;
2242
2243     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2244
2245     return VA_STATUS_SUCCESS;
2246 }
2247
2248 static int
2249 pp_dn_x_steps(void *private_context)
2250 {
2251     return 1;
2252 }
2253
2254 static int
2255 pp_dn_y_steps(void *private_context)
2256 {
2257     struct pp_dn_context *pp_dn_context = private_context;
2258
2259     return pp_dn_context->dest_h / 8;
2260 }
2261
2262 static int
2263 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2264 {
2265     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2266
2267     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2268     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2269
2270     return 0;
2271 }
2272
2273 static VAStatus
2274 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2275                       const struct i965_surface *src_surface,
2276                       const VARectangle *src_rect,
2277                       struct i965_surface *dst_surface,
2278                       const VARectangle *dst_rect,
2279                       void *filter_param)
2280 {
2281     struct i965_driver_data *i965 = i965_driver_data(ctx);
2282     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2283     struct object_surface *obj_surface;
2284     struct i965_sampler_dndi *sampler_dndi;
2285     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2286     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2287     VAProcFilterBaseParameterBuffer *dn_filter_param = filter_param;
2288     int index;
2289     int w, h;
2290     int orig_w, orig_h;
2291     int dn_strength = 15;
2292     int dndi_top_first = 1;
2293     int dn_progressive = 0;
2294
2295     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2296         dndi_top_first = 1;
2297         dn_progressive = 1;
2298     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2299         dndi_top_first = 1;
2300         dn_progressive = 0;
2301     } else {
2302         dndi_top_first = 0;
2303         dn_progressive = 0;
2304     }
2305
2306     if (dn_filter_param) {
2307         int value = dn_filter_param->value;
2308
2309         if (value > 1.0)
2310             value = 1.0;
2311
2312         if (value < 0.0)
2313             value = 0.0;
2314
2315         dn_strength = (int)(value * 31.0F);
2316     }
2317
2318     /* surface */
2319     obj_surface = SURFACE(src_surface->id);
2320     orig_w = obj_surface->orig_width;
2321     orig_h = obj_surface->orig_height;
2322     w = obj_surface->width;
2323     h = obj_surface->height;
2324
2325     if (pp_context->stmm.bo == NULL) {
2326         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2327                                            "STMM surface",
2328                                            w * h,
2329                                            4096);
2330         assert(pp_context->stmm.bo);
2331     }
2332
2333     /* source UV surface index 2 */
2334     i965_pp_set_surface_state(ctx, pp_context,
2335                               obj_surface->bo, w * h,
2336                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2337                               2, 0);
2338
2339     /* source YUV surface index 4 */
2340     i965_pp_set_surface2_state(ctx, pp_context,
2341                                obj_surface->bo, 0,
2342                                orig_w, orig_h, w,
2343                                0, h,
2344                                SURFACE_FORMAT_PLANAR_420_8, 1,
2345                                4);
2346
2347     /* source STMM surface index 20 */
2348     i965_pp_set_surface_state(ctx, pp_context,
2349                               pp_context->stmm.bo, 0,
2350                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2351                               20, 1);
2352
2353     /* destination surface */
2354     obj_surface = SURFACE(dst_surface->id);
2355     orig_w = obj_surface->orig_width;
2356     orig_h = obj_surface->orig_height;
2357     w = obj_surface->width;
2358     h = obj_surface->height;
2359
2360     /* destination Y surface index 7 */
2361     i965_pp_set_surface_state(ctx, pp_context,
2362                               obj_surface->bo, 0,
2363                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2364                               7, 1);
2365
2366     /* destination UV surface index 8 */
2367     i965_pp_set_surface_state(ctx, pp_context,
2368                               obj_surface->bo, w * h,
2369                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2370                               8, 1);
2371     /* sampler dn */
2372     dri_bo_map(pp_context->sampler_state_table.bo, True);
2373     assert(pp_context->sampler_state_table.bo->virtual);
2374     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2375     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2376
2377     /* sample dndi index 1 */
2378     index = 0;
2379     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2380     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2381     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2382     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2383
2384     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2385     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2386     sampler_dndi[index].dw1.stmm_c2 = 0;
2387     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2388     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2389
2390     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2391     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2392     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2393     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2394
2395     sampler_dndi[index].dw3.maximum_stmm = 128;
2396     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2397     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2398     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2399     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2400
2401     sampler_dndi[index].dw4.sdi_delta = 8;
2402     sampler_dndi[index].dw4.sdi_threshold = 128;
2403     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2404     sampler_dndi[index].dw4.stmm_shift_up = 0;
2405     sampler_dndi[index].dw4.stmm_shift_down = 0;
2406     sampler_dndi[index].dw4.minimum_stmm = 0;
2407
2408     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2409     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2410     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2411     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2412
2413     sampler_dndi[index].dw6.dn_enable = 1;
2414     sampler_dndi[index].dw6.di_enable = 0;
2415     sampler_dndi[index].dw6.di_partial = 0;
2416     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2417     sampler_dndi[index].dw6.dndi_stream_id = 1;
2418     sampler_dndi[index].dw6.dndi_first_frame = 1;
2419     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2420     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2421     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2422     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2423
2424     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2425     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2426     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2427     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2428
2429     dri_bo_unmap(pp_context->sampler_state_table.bo);
2430
2431     /* private function & data */
2432     pp_context->pp_x_steps = pp_dn_x_steps;
2433     pp_context->pp_y_steps = pp_dn_y_steps;
2434     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2435
2436     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2437     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2438     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2439     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2440
2441     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2442     pp_inline_parameter->grf5.number_blocks = w / 16;
2443     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2444     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2445
2446     pp_dn_context->dest_w = w;
2447     pp_dn_context->dest_h = h;
2448
2449     dst_surface->flags = src_surface->flags;
2450
2451     return VA_STATUS_SUCCESS;
2452 }
2453
2454 static int
2455 gen7_pp_dndi_x_steps(void *private_context)
2456 {
2457     struct pp_dndi_context *pp_dndi_context = private_context;
2458
2459     return pp_dndi_context->dest_w / 16;
2460 }
2461
2462 static int
2463 gen7_pp_dndi_y_steps(void *private_context)
2464 {
2465     struct pp_dndi_context *pp_dndi_context = private_context;
2466
2467     return pp_dndi_context->dest_h / 4;
2468 }
2469
2470 static int
2471 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2472 {
2473     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2474
2475     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2476     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2477
2478     return 0;
2479 }
2480
2481 static VAStatus
2482 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2483                              const struct i965_surface *src_surface,
2484                              const VARectangle *src_rect,
2485                              struct i965_surface *dst_surface,
2486                              const VARectangle *dst_rect,
2487                              void *filter_param)
2488 {
2489     struct i965_driver_data *i965 = i965_driver_data(ctx);
2490     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2491     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2492     struct object_surface *obj_surface;
2493     struct gen7_sampler_dndi *sampler_dndi;
2494     int index;
2495     int w, h;
2496     int orig_w, orig_h;
2497     int dndi_top_first = 1;
2498
2499     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2500         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2501
2502     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2503         dndi_top_first = 1;
2504     else
2505         dndi_top_first = 0;
2506
2507     /* surface */
2508     obj_surface = SURFACE(src_surface->id);
2509     orig_w = obj_surface->orig_width;
2510     orig_h = obj_surface->orig_height;
2511     w = obj_surface->width;
2512     h = obj_surface->height;
2513
2514     if (pp_context->stmm.bo == NULL) {
2515         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2516                                            "STMM surface",
2517                                            w * h,
2518                                            4096);
2519         assert(pp_context->stmm.bo);
2520     }
2521
2522     /* source UV surface index 1 */
2523     gen7_pp_set_surface_state(ctx, pp_context,
2524                               obj_surface->bo, w * h,
2525                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2526                               1, 0);
2527
2528     /* source YUV surface index 3 */
2529     gen7_pp_set_surface2_state(ctx, pp_context,
2530                                obj_surface->bo, 0,
2531                                orig_w, orig_h, w,
2532                                0, h,
2533                                SURFACE_FORMAT_PLANAR_420_8, 1,
2534                                3);
2535
2536     /* source (temporal reference) YUV surface index 4 */
2537     gen7_pp_set_surface2_state(ctx, pp_context,
2538                                obj_surface->bo, 0,
2539                                orig_w, orig_h, w,
2540                                0, h,
2541                                SURFACE_FORMAT_PLANAR_420_8, 1,
2542                                4);
2543
2544     /* STMM / History Statistics input surface, index 5 */
2545     gen7_pp_set_surface_state(ctx, pp_context,
2546                               pp_context->stmm.bo, 0,
2547                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2548                               5, 1);
2549
2550     /* destination surface */
2551     obj_surface = SURFACE(dst_surface->id);
2552     orig_w = obj_surface->orig_width;
2553     orig_h = obj_surface->orig_height;
2554     w = obj_surface->width;
2555     h = obj_surface->height;
2556
2557     /* destination(Previous frame) Y surface index 27 */
2558     gen7_pp_set_surface_state(ctx, pp_context,
2559                               obj_surface->bo, 0,
2560                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2561                               27, 1);
2562
2563     /* destination(Previous frame) UV surface index 28 */
2564     gen7_pp_set_surface_state(ctx, pp_context,
2565                               obj_surface->bo, w * h,
2566                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2567                               28, 1);
2568
2569     /* destination(Current frame) Y surface index 30 */
2570     gen7_pp_set_surface_state(ctx, pp_context,
2571                               obj_surface->bo, 0,
2572                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2573                               30, 1);
2574
2575     /* destination(Current frame) UV surface index 31 */
2576     gen7_pp_set_surface_state(ctx, pp_context,
2577                               obj_surface->bo, w * h,
2578                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2579                               31, 1);
2580
2581     /* STMM output surface, index 33 */
2582     gen7_pp_set_surface_state(ctx, pp_context,
2583                               pp_context->stmm.bo, 0,
2584                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2585                               33, 1);
2586
2587
2588     /* sampler dndi */
2589     dri_bo_map(pp_context->sampler_state_table.bo, True);
2590     assert(pp_context->sampler_state_table.bo->virtual);
2591     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2592     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2593
2594     /* sample dndi index 0 */
2595     index = 0;
2596     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2597     sampler_dndi[index].dw0.dnmh_delt = 8;
2598     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2599     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2600     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2601     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2602
2603     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2604     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2605     sampler_dndi[index].dw1.stmm_c2 = 0;
2606     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2607     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2608
2609     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2610     sampler_dndi[index].dw2.bne_edge_th = 1;
2611     sampler_dndi[index].dw2.smooth_mv_th = 0;
2612     sampler_dndi[index].dw2.sad_tight_th = 5;
2613     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2614     sampler_dndi[index].dw2.good_neighbor_th = 4;
2615
2616     sampler_dndi[index].dw3.maximum_stmm = 128;
2617     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2618     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2619     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2620     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2621
2622     sampler_dndi[index].dw4.sdi_delta = 8;
2623     sampler_dndi[index].dw4.sdi_threshold = 128;
2624     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2625     sampler_dndi[index].dw4.stmm_shift_up = 0;
2626     sampler_dndi[index].dw4.stmm_shift_down = 0;
2627     sampler_dndi[index].dw4.minimum_stmm = 0;
2628
2629     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2630     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2631     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2632     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2633
2634     sampler_dndi[index].dw6.dn_enable = 0;
2635     sampler_dndi[index].dw6.di_enable = 1;
2636     sampler_dndi[index].dw6.di_partial = 0;
2637     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2638     sampler_dndi[index].dw6.dndi_stream_id = 1;
2639     sampler_dndi[index].dw6.dndi_first_frame = 1;
2640     sampler_dndi[index].dw6.progressive_dn = 0;
2641     sampler_dndi[index].dw6.mcdi_enable = 0;
2642     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2643     sampler_dndi[index].dw6.cat_th1 = 0;
2644     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2645     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2646
2647     sampler_dndi[index].dw7.sad_tha = 5;
2648     sampler_dndi[index].dw7.sad_thb = 10;
2649     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2650     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2651     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2652     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2653     sampler_dndi[index].dw7.neighborpixel_th = 10;
2654     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2655
2656     dri_bo_unmap(pp_context->sampler_state_table.bo);
2657
2658     /* private function & data */
2659     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2660     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2661     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2662
2663     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2664     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2665     pp_static_parameter->grf1.di_top_field_first = 0;
2666     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2667
2668     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2669     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2670     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2671
2672     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2673     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2674
2675     pp_dndi_context->dest_w = w;
2676     pp_dndi_context->dest_h = h;
2677
2678     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2679
2680     return VA_STATUS_SUCCESS;
2681 }
2682
2683 static int
2684 gen7_pp_dn_x_steps(void *private_context)
2685 {
2686     return 1;
2687 }
2688
2689 static int
2690 gen7_pp_dn_y_steps(void *private_context)
2691 {
2692     struct pp_dn_context *pp_dn_context = private_context;
2693
2694     return pp_dn_context->dest_h / 4;
2695 }
2696
2697 static int
2698 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2699 {
2700     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2701
2702     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2703     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2704
2705     return 0;
2706 }
2707
2708 static VAStatus
2709 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2710                            const struct i965_surface *src_surface,
2711                            const VARectangle *src_rect,
2712                            struct i965_surface *dst_surface,
2713                            const VARectangle *dst_rect,
2714                            void *filter_param)
2715 {
2716     struct i965_driver_data *i965 = i965_driver_data(ctx);
2717     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2718     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2719     struct object_surface *obj_surface;
2720     struct gen7_sampler_dndi *sampler_dn;
2721     VAProcFilterBaseParameterBuffer *dn_filter_param = filter_param;
2722     int index;
2723     int w, h;
2724     int orig_w, orig_h;
2725     int dn_strength = 15;
2726     int dndi_top_first = 1;
2727     int dn_progressive = 0;
2728
2729     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2730         dndi_top_first = 1;
2731         dn_progressive = 1;
2732     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2733         dndi_top_first = 1;
2734         dn_progressive = 0;
2735     } else {
2736         dndi_top_first = 0;
2737         dn_progressive = 0;
2738     }
2739
2740     if (dn_filter_param) {
2741         int value = dn_filter_param->value;
2742
2743         if (value > 1.0)
2744             value = 1.0;
2745
2746         if (value < 0.0)
2747             value = 0.0;
2748
2749         dn_strength = (int)(value * 31.0F);
2750     }
2751
2752     /* surface */
2753     obj_surface = SURFACE(src_surface->id);
2754     orig_w = obj_surface->orig_width;
2755     orig_h = obj_surface->orig_height;
2756     w = obj_surface->width;
2757     h = obj_surface->height;
2758
2759     if (pp_context->stmm.bo == NULL) {
2760         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2761                                            "STMM surface",
2762                                            w * h,
2763                                            4096);
2764         assert(pp_context->stmm.bo);
2765     }
2766
2767     /* source UV surface index 1 */
2768     gen7_pp_set_surface_state(ctx, pp_context,
2769                               obj_surface->bo, w * h,
2770                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2771                               1, 0);
2772
2773     /* source YUV surface index 3 */
2774     gen7_pp_set_surface2_state(ctx, pp_context,
2775                                obj_surface->bo, 0,
2776                                orig_w, orig_h, w,
2777                                0, h,
2778                                SURFACE_FORMAT_PLANAR_420_8, 1,
2779                                3);
2780
2781     /* source STMM surface index 5 */
2782     gen7_pp_set_surface_state(ctx, pp_context,
2783                               pp_context->stmm.bo, 0,
2784                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2785                               5, 1);
2786
2787     /* destination surface */
2788     obj_surface = SURFACE(dst_surface->id);
2789     orig_w = obj_surface->orig_width;
2790     orig_h = obj_surface->orig_height;
2791     w = obj_surface->width;
2792     h = obj_surface->height;
2793
2794     /* destination Y surface index 7 */
2795     gen7_pp_set_surface_state(ctx, pp_context,
2796                               obj_surface->bo, 0,
2797                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2798                               7, 1);
2799
2800     /* destination UV surface index 8 */
2801     gen7_pp_set_surface_state(ctx, pp_context,
2802                               obj_surface->bo, w * h,
2803                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2804                               8, 1);
2805     /* sampler dn */
2806     dri_bo_map(pp_context->sampler_state_table.bo, True);
2807     assert(pp_context->sampler_state_table.bo->virtual);
2808     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
2809     sampler_dn = pp_context->sampler_state_table.bo->virtual;
2810
2811     /* sample dn index 1 */
2812     index = 0;
2813     sampler_dn[index].dw0.denoise_asd_threshold = 0;
2814     sampler_dn[index].dw0.dnmh_delt = 8;
2815     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
2816     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
2817     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
2818     sampler_dn[index].dw0.denoise_stad_threshold = 0;
2819
2820     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2821     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
2822     sampler_dn[index].dw1.stmm_c2 = 0;
2823     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
2824     sampler_dn[index].dw1.temporal_difference_threshold = 16;
2825
2826     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2827     sampler_dn[index].dw2.bne_edge_th = 1;
2828     sampler_dn[index].dw2.smooth_mv_th = 0;
2829     sampler_dn[index].dw2.sad_tight_th = 5;
2830     sampler_dn[index].dw2.cat_slope_minus1 = 9;
2831     sampler_dn[index].dw2.good_neighbor_th = 4;
2832
2833     sampler_dn[index].dw3.maximum_stmm = 128;
2834     sampler_dn[index].dw3.multipler_for_vecm = 2;
2835     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2836     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2837     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
2838
2839     sampler_dn[index].dw4.sdi_delta = 8;
2840     sampler_dn[index].dw4.sdi_threshold = 128;
2841     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2842     sampler_dn[index].dw4.stmm_shift_up = 0;
2843     sampler_dn[index].dw4.stmm_shift_down = 0;
2844     sampler_dn[index].dw4.minimum_stmm = 0;
2845
2846     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
2847     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
2848     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2849     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2850
2851     sampler_dn[index].dw6.dn_enable = 1;
2852     sampler_dn[index].dw6.di_enable = 0;
2853     sampler_dn[index].dw6.di_partial = 0;
2854     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
2855     sampler_dn[index].dw6.dndi_stream_id = 1;
2856     sampler_dn[index].dw6.dndi_first_frame = 1;
2857     sampler_dn[index].dw6.progressive_dn = dn_progressive;
2858     sampler_dn[index].dw6.mcdi_enable = 0;
2859     sampler_dn[index].dw6.fmd_tear_threshold = 32;
2860     sampler_dn[index].dw6.cat_th1 = 0;
2861     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
2862     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
2863
2864     sampler_dn[index].dw7.sad_tha = 5;
2865     sampler_dn[index].dw7.sad_thb = 10;
2866     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2867     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
2868     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2869     sampler_dn[index].dw7.vdi_walker_enable = 0;
2870     sampler_dn[index].dw7.neighborpixel_th = 10;
2871     sampler_dn[index].dw7.column_width_minus1 = w / 16;
2872
2873     dri_bo_unmap(pp_context->sampler_state_table.bo);
2874
2875     /* private function & data */
2876     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
2877     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
2878     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
2879
2880     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2881     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2882     pp_static_parameter->grf1.di_top_field_first = 0;
2883     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2884
2885     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2886     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2887     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2888
2889     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2890     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2891
2892     pp_dn_context->dest_w = w;
2893     pp_dn_context->dest_h = h;
2894
2895     dst_surface->flags = src_surface->flags;
2896
2897     return VA_STATUS_SUCCESS;
2898 }
2899
2900 static VAStatus
2901 ironlake_pp_initialize(
2902     VADriverContextP   ctx,
2903     struct i965_post_processing_context *pp_context,
2904     const struct i965_surface *src_surface,
2905     const VARectangle *src_rect,
2906     struct i965_surface *dst_surface,
2907     const VARectangle *dst_rect,
2908     int                pp_index,
2909     void *filter_param
2910 )
2911 {
2912     VAStatus va_status;
2913     struct i965_driver_data *i965 = i965_driver_data(ctx);
2914     struct pp_module *pp_module;
2915     dri_bo *bo;
2916     int static_param_size, inline_param_size;
2917
2918     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
2919     bo = dri_bo_alloc(i965->intel.bufmgr,
2920                       "surface state & binding table",
2921                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
2922                       4096);
2923     assert(bo);
2924     pp_context->surface_state_binding_table.bo = bo;
2925
2926     dri_bo_unreference(pp_context->curbe.bo);
2927     bo = dri_bo_alloc(i965->intel.bufmgr,
2928                       "constant buffer",
2929                       4096,
2930                       4096);
2931     assert(bo);
2932     pp_context->curbe.bo = bo;
2933
2934     dri_bo_unreference(pp_context->idrt.bo);
2935     bo = dri_bo_alloc(i965->intel.bufmgr,
2936                       "interface discriptor",
2937                       sizeof(struct i965_interface_descriptor),
2938                       4096);
2939     assert(bo);
2940     pp_context->idrt.bo = bo;
2941     pp_context->idrt.num_interface_descriptors = 0;
2942
2943     dri_bo_unreference(pp_context->sampler_state_table.bo);
2944     bo = dri_bo_alloc(i965->intel.bufmgr,
2945                       "sampler state table",
2946                       4096,
2947                       4096);
2948     assert(bo);
2949     dri_bo_map(bo, True);
2950     memset(bo->virtual, 0, bo->size);
2951     dri_bo_unmap(bo);
2952     pp_context->sampler_state_table.bo = bo;
2953
2954     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
2955     bo = dri_bo_alloc(i965->intel.bufmgr,
2956                       "sampler 8x8 state ",
2957                       4096,
2958                       4096);
2959     assert(bo);
2960     pp_context->sampler_state_table.bo_8x8 = bo;
2961
2962     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
2963     bo = dri_bo_alloc(i965->intel.bufmgr,
2964                       "sampler 8x8 state ",
2965                       4096,
2966                       4096);
2967     assert(bo);
2968     pp_context->sampler_state_table.bo_8x8_uv = bo;
2969
2970     dri_bo_unreference(pp_context->vfe_state.bo);
2971     bo = dri_bo_alloc(i965->intel.bufmgr,
2972                       "vfe state",
2973                       sizeof(struct i965_vfe_state),
2974                       4096);
2975     assert(bo);
2976     pp_context->vfe_state.bo = bo;
2977
2978     if (IS_GEN7(i965->intel.device_id)) {
2979         static_param_size = sizeof(struct gen7_pp_static_parameter);
2980         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
2981     } else {
2982         static_param_size = sizeof(struct pp_static_parameter);
2983         inline_param_size = sizeof(struct pp_inline_parameter);
2984     }
2985
2986     memset(pp_context->pp_static_parameter, 0, static_param_size);
2987     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
2988     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
2989     pp_context->current_pp = pp_index;
2990     pp_module = &pp_context->pp_modules[pp_index];
2991
2992     if (pp_module->initialize)
2993         va_status = pp_module->initialize(ctx, pp_context,
2994                                           src_surface,
2995                                           src_rect,
2996                                           dst_surface,
2997                                           dst_rect,
2998                                           filter_param);
2999     else
3000         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3001
3002     return va_status;
3003 }
3004
3005 static VAStatus
3006 ironlake_post_processing(
3007     VADriverContextP   ctx,
3008     struct i965_post_processing_context *pp_context,
3009     const struct i965_surface *src_surface,
3010     const VARectangle *src_rect,
3011     struct i965_surface *dst_surface,
3012     const VARectangle *dst_rect,
3013     int                pp_index,
3014     void *filter_param
3015 )
3016 {
3017     VAStatus va_status;
3018
3019     va_status = ironlake_pp_initialize(ctx, pp_context,
3020                                        src_surface,
3021                                        src_rect,
3022                                        dst_surface,
3023                                        dst_rect,
3024                                        pp_index,
3025                                        filter_param);
3026
3027     if (va_status == VA_STATUS_SUCCESS) {
3028         ironlake_pp_states_setup(ctx, pp_context);
3029         ironlake_pp_pipeline_setup(ctx, pp_context);
3030     }
3031
3032     return va_status;
3033 }
3034
3035 static VAStatus
3036 gen6_pp_initialize(
3037     VADriverContextP   ctx,
3038     struct i965_post_processing_context *pp_context,
3039     const struct i965_surface *src_surface,
3040     const VARectangle *src_rect,
3041     struct i965_surface *dst_surface,
3042     const VARectangle *dst_rect,
3043     int                pp_index,
3044     void *filter_param
3045 )
3046 {
3047     VAStatus va_status;
3048     struct i965_driver_data *i965 = i965_driver_data(ctx);
3049     struct pp_module *pp_module;
3050     dri_bo *bo;
3051     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3052     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3053
3054     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3055     bo = dri_bo_alloc(i965->intel.bufmgr,
3056                       "surface state & binding table",
3057                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3058                       4096);
3059     assert(bo);
3060     pp_context->surface_state_binding_table.bo = bo;
3061
3062     dri_bo_unreference(pp_context->curbe.bo);
3063     bo = dri_bo_alloc(i965->intel.bufmgr,
3064                       "constant buffer",
3065                       4096,
3066                       4096);
3067     assert(bo);
3068     pp_context->curbe.bo = bo;
3069
3070     dri_bo_unreference(pp_context->idrt.bo);
3071     bo = dri_bo_alloc(i965->intel.bufmgr,
3072                       "interface discriptor",
3073                       sizeof(struct gen6_interface_descriptor_data),
3074                       4096);
3075     assert(bo);
3076     pp_context->idrt.bo = bo;
3077     pp_context->idrt.num_interface_descriptors = 0;
3078
3079     dri_bo_unreference(pp_context->sampler_state_table.bo);
3080     bo = dri_bo_alloc(i965->intel.bufmgr,
3081                       "sampler state table",
3082                       4096,
3083                       4096);
3084     assert(bo);
3085     dri_bo_map(bo, True);
3086     memset(bo->virtual, 0, bo->size);
3087     dri_bo_unmap(bo);
3088     pp_context->sampler_state_table.bo = bo;
3089
3090     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3091     bo = dri_bo_alloc(i965->intel.bufmgr,
3092                       "sampler 8x8 state ",
3093                       4096,
3094                       4096);
3095     assert(bo);
3096     pp_context->sampler_state_table.bo_8x8 = bo;
3097
3098     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3099     bo = dri_bo_alloc(i965->intel.bufmgr,
3100                       "sampler 8x8 state ",
3101                       4096,
3102                       4096);
3103     assert(bo);
3104     pp_context->sampler_state_table.bo_8x8_uv = bo;
3105
3106     dri_bo_unreference(pp_context->vfe_state.bo);
3107     bo = dri_bo_alloc(i965->intel.bufmgr,
3108                       "vfe state",
3109                       sizeof(struct i965_vfe_state),
3110                       4096);
3111     assert(bo);
3112     pp_context->vfe_state.bo = bo;
3113
3114     memset(pp_static_parameter, 0, sizeof(*pp_static_parameter));
3115     memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter));
3116     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3117     pp_context->current_pp = pp_index;
3118     pp_module = &pp_context->pp_modules[pp_index];
3119
3120     if (pp_module->initialize)
3121         va_status = pp_module->initialize(ctx, pp_context,
3122                                           src_surface,
3123                                           src_rect,
3124                                           dst_surface,
3125                                           dst_rect,
3126                                           filter_param);
3127     else
3128         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3129
3130     return va_status;
3131 }
3132
3133 static void
3134 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3135                                    struct i965_post_processing_context *pp_context)
3136 {
3137     struct i965_driver_data *i965 = i965_driver_data(ctx);
3138     struct gen6_interface_descriptor_data *desc;
3139     dri_bo *bo;
3140     int pp_index = pp_context->current_pp;
3141
3142     bo = pp_context->idrt.bo;
3143     dri_bo_map(bo, True);
3144     assert(bo->virtual);
3145     desc = bo->virtual;
3146     memset(desc, 0, sizeof(*desc));
3147     desc->desc0.kernel_start_pointer =
3148         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3149     desc->desc1.single_program_flow = 1;
3150     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3151     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3152     desc->desc2.sampler_state_pointer =
3153         pp_context->sampler_state_table.bo->offset >> 5;
3154     desc->desc3.binding_table_entry_count = 0;
3155     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3156     desc->desc4.constant_urb_entry_read_offset = 0;
3157
3158     if (IS_GEN7(i965->intel.device_id))
3159         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3160     else
3161         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3162
3163     dri_bo_emit_reloc(bo,
3164                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3165                       0,
3166                       offsetof(struct gen6_interface_descriptor_data, desc0),
3167                       pp_context->pp_modules[pp_index].kernel.bo);
3168
3169     dri_bo_emit_reloc(bo,
3170                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3171                       desc->desc2.sampler_count << 2,
3172                       offsetof(struct gen6_interface_descriptor_data, desc2),
3173                       pp_context->sampler_state_table.bo);
3174
3175     dri_bo_unmap(bo);
3176     pp_context->idrt.num_interface_descriptors++;
3177 }
3178
3179 static void
3180 gen6_pp_upload_constants(VADriverContextP ctx,
3181                          struct i965_post_processing_context *pp_context)
3182 {
3183     struct i965_driver_data *i965 = i965_driver_data(ctx);
3184     unsigned char *constant_buffer;
3185     int param_size;
3186
3187     assert(sizeof(struct pp_static_parameter) == 128);
3188     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3189
3190     if (IS_GEN7(i965->intel.device_id))
3191         param_size = sizeof(struct gen7_pp_static_parameter);
3192     else
3193         param_size = sizeof(struct pp_static_parameter);
3194
3195     dri_bo_map(pp_context->curbe.bo, 1);
3196     assert(pp_context->curbe.bo->virtual);
3197     constant_buffer = pp_context->curbe.bo->virtual;
3198     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3199     dri_bo_unmap(pp_context->curbe.bo);
3200 }
3201
3202 static void
3203 gen6_pp_states_setup(VADriverContextP ctx,
3204                      struct i965_post_processing_context *pp_context)
3205 {
3206     gen6_pp_interface_descriptor_table(ctx, pp_context);
3207     gen6_pp_upload_constants(ctx, pp_context);
3208 }
3209
3210 static void
3211 gen6_pp_pipeline_select(VADriverContextP ctx,
3212                         struct i965_post_processing_context *pp_context)
3213 {
3214     struct intel_batchbuffer *batch = pp_context->batch;
3215
3216     BEGIN_BATCH(batch, 1);
3217     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3218     ADVANCE_BATCH(batch);
3219 }
3220
3221 static void
3222 gen6_pp_state_base_address(VADriverContextP ctx,
3223                            struct i965_post_processing_context *pp_context)
3224 {
3225     struct intel_batchbuffer *batch = pp_context->batch;
3226
3227     BEGIN_BATCH(batch, 10);
3228     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3229     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3230     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3231     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3232     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3233     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3234     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3235     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3236     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3237     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3238     ADVANCE_BATCH(batch);
3239 }
3240
3241 static void
3242 gen6_pp_vfe_state(VADriverContextP ctx,
3243                   struct i965_post_processing_context *pp_context)
3244 {
3245     struct intel_batchbuffer *batch = pp_context->batch;
3246
3247     BEGIN_BATCH(batch, 8);
3248     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3249     OUT_BATCH(batch, 0);
3250     OUT_BATCH(batch,
3251               (pp_context->urb.num_vfe_entries - 1) << 16 |
3252               pp_context->urb.num_vfe_entries << 8);
3253     OUT_BATCH(batch, 0);
3254     OUT_BATCH(batch,
3255               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3256               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3257     OUT_BATCH(batch, 0);
3258     OUT_BATCH(batch, 0);
3259     OUT_BATCH(batch, 0);
3260     ADVANCE_BATCH(batch);
3261 }
3262
3263 static void
3264 gen6_pp_curbe_load(VADriverContextP ctx,
3265                    struct i965_post_processing_context *pp_context)
3266 {
3267     struct intel_batchbuffer *batch = pp_context->batch;
3268
3269     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3270
3271     BEGIN_BATCH(batch, 4);
3272     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3273     OUT_BATCH(batch, 0);
3274     OUT_BATCH(batch,
3275               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3276     OUT_RELOC(batch,
3277               pp_context->curbe.bo,
3278               I915_GEM_DOMAIN_INSTRUCTION, 0,
3279               0);
3280     ADVANCE_BATCH(batch);
3281 }
3282
3283 static void
3284 gen6_interface_descriptor_load(VADriverContextP ctx,
3285                                struct i965_post_processing_context *pp_context)
3286 {
3287     struct intel_batchbuffer *batch = pp_context->batch;
3288
3289     BEGIN_BATCH(batch, 4);
3290     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3291     OUT_BATCH(batch, 0);
3292     OUT_BATCH(batch,
3293               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3294     OUT_RELOC(batch,
3295               pp_context->idrt.bo,
3296               I915_GEM_DOMAIN_INSTRUCTION, 0,
3297               0);
3298     ADVANCE_BATCH(batch);
3299 }
3300
3301 static void
3302 gen6_pp_object_walker(VADriverContextP ctx,
3303                       struct i965_post_processing_context *pp_context)
3304 {
3305     struct i965_driver_data *i965 = i965_driver_data(ctx);
3306     struct intel_batchbuffer *batch = pp_context->batch;
3307     int x, x_steps, y, y_steps;
3308     int param_size, command_length_in_dws;
3309     dri_bo *command_buffer;
3310     unsigned int *command_ptr;
3311
3312     if (IS_GEN7(i965->intel.device_id))
3313         param_size = sizeof(struct gen7_pp_inline_parameter);
3314     else
3315         param_size = sizeof(struct pp_inline_parameter);
3316
3317     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3318     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3319     command_length_in_dws = 6 + (param_size >> 2);
3320     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3321                                   "command objects buffer",
3322                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3323                                   4096);
3324
3325     dri_bo_map(command_buffer, 1);
3326     command_ptr = command_buffer->virtual;
3327
3328     for (y = 0; y < y_steps; y++) {
3329         for (x = 0; x < x_steps; x++) {
3330             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3331                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3332                 *command_ptr++ = 0;
3333                 *command_ptr++ = 0;
3334                 *command_ptr++ = 0;
3335                 *command_ptr++ = 0;
3336                 *command_ptr++ = 0;
3337                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3338                 command_ptr += (param_size >> 2);
3339             }
3340         }
3341     }
3342
3343     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3344         *command_ptr++ = 0;
3345
3346     *command_ptr = MI_BATCH_BUFFER_END;
3347
3348     dri_bo_unmap(command_buffer);
3349
3350     BEGIN_BATCH(batch, 2);
3351     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3352     OUT_RELOC(batch, command_buffer,
3353               I915_GEM_DOMAIN_COMMAND, 0,
3354               0);
3355     ADVANCE_BATCH(batch);
3356
3357     dri_bo_unreference(command_buffer);
3358
3359     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3360      * will cause control to pass back to ring buffer
3361      */
3362     intel_batchbuffer_end_atomic(batch);
3363     intel_batchbuffer_flush(batch);
3364     intel_batchbuffer_start_atomic(batch, 0x1000);
3365 }
3366
3367 static void
3368 gen6_pp_pipeline_setup(VADriverContextP ctx,
3369                        struct i965_post_processing_context *pp_context)
3370 {
3371     struct intel_batchbuffer *batch = pp_context->batch;
3372
3373     intel_batchbuffer_start_atomic(batch, 0x1000);
3374     intel_batchbuffer_emit_mi_flush(batch);
3375     gen6_pp_pipeline_select(ctx, pp_context);
3376     gen6_pp_state_base_address(ctx, pp_context);
3377     gen6_pp_vfe_state(ctx, pp_context);
3378     gen6_pp_curbe_load(ctx, pp_context);
3379     gen6_interface_descriptor_load(ctx, pp_context);
3380     gen6_pp_object_walker(ctx, pp_context);
3381     intel_batchbuffer_end_atomic(batch);
3382 }
3383
3384 static VAStatus
3385 gen6_post_processing(
3386     VADriverContextP   ctx,
3387     struct i965_post_processing_context *pp_context,
3388     const struct i965_surface *src_surface,
3389     const VARectangle *src_rect,
3390     struct i965_surface *dst_surface,
3391     const VARectangle *dst_rect,
3392     int                pp_index,
3393     void * filter_param
3394 )
3395 {
3396     VAStatus va_status;
3397
3398     va_status = gen6_pp_initialize(ctx, pp_context,
3399                                    src_surface,
3400                                    src_rect,
3401                                    dst_surface,
3402                                    dst_rect,
3403                                    pp_index,
3404                                    filter_param);
3405
3406     if (va_status == VA_STATUS_SUCCESS) {
3407         gen6_pp_states_setup(ctx, pp_context);
3408         gen6_pp_pipeline_setup(ctx, pp_context);
3409     }
3410
3411     return va_status;
3412 }
3413
3414 static VAStatus
3415 i965_post_processing_internal(
3416     VADriverContextP   ctx,
3417     struct i965_post_processing_context *pp_context,
3418     const struct i965_surface *src_surface,
3419     const VARectangle *src_rect,
3420     struct i965_surface *dst_surface,
3421     const VARectangle *dst_rect,
3422     int                pp_index,
3423     void *filter_param
3424 )
3425 {
3426     struct i965_driver_data *i965 = i965_driver_data(ctx);
3427     VAStatus va_status;
3428
3429     if (IS_GEN6(i965->intel.device_id) ||
3430         IS_GEN7(i965->intel.device_id))
3431         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3432     else
3433         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3434
3435     return va_status;
3436 }
3437
3438 VAStatus
3439 i965_DestroySurfaces(VADriverContextP ctx,
3440                      VASurfaceID *surface_list,
3441                      int num_surfaces);
3442 VAStatus
3443 i965_CreateSurfaces(VADriverContextP ctx,
3444                     int width,
3445                     int height,
3446                     int format,
3447                     int num_surfaces,
3448                     VASurfaceID *surfaces);
3449
3450 static void
3451 i965_vpp_clear_surface(VADriverContextP ctx,
3452                        struct i965_post_processing_context *pp_context,
3453                        VASurfaceID surface,
3454                        unsigned int color)
3455 {
3456     struct i965_driver_data *i965 = i965_driver_data(ctx);
3457     struct intel_batchbuffer *batch = pp_context->batch;
3458     struct object_surface *obj_surface = SURFACE(surface);
3459     unsigned int blt_cmd, br13;
3460     unsigned int tiling = 0, swizzle = 0;
3461     int pitch;
3462
3463     /* Currently only support NV12 surface */
3464     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3465         return;
3466
3467     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3468     blt_cmd = XY_COLOR_BLT_CMD;
3469     pitch = obj_surface->width;
3470
3471     if (tiling != I915_TILING_NONE) {
3472         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3473         pitch >>= 2;
3474     }
3475
3476     br13 = 0xf0 << 16;
3477     br13 |= BR13_8;
3478     br13 |= pitch;
3479
3480     if (IS_GEN6(i965->intel.device_id) ||
3481         IS_GEN7(i965->intel.device_id)) {
3482         intel_batchbuffer_start_atomic_blt(batch, 48);
3483         BEGIN_BLT_BATCH(batch, 12);
3484     } else {
3485         intel_batchbuffer_start_atomic(batch, 48);
3486         BEGIN_BATCH(batch, 12);
3487     }
3488
3489     OUT_BATCH(batch, blt_cmd);
3490     OUT_BATCH(batch, br13);
3491     OUT_BATCH(batch,
3492               0 << 16 |
3493               0);
3494     OUT_BATCH(batch,
3495               obj_surface->height << 16 |
3496               obj_surface->width);
3497     OUT_RELOC(batch, obj_surface->bo,
3498               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3499               0);
3500     OUT_BATCH(batch, 0x10);
3501
3502     OUT_BATCH(batch, blt_cmd);
3503     OUT_BATCH(batch, br13);
3504     OUT_BATCH(batch,
3505               0 << 16 |
3506               0);
3507     OUT_BATCH(batch,
3508               obj_surface->height / 2 << 16 |
3509               obj_surface->width);
3510     OUT_RELOC(batch, obj_surface->bo,
3511               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3512               obj_surface->width * obj_surface->y_cb_offset);
3513     OUT_BATCH(batch, 0x80);
3514
3515     ADVANCE_BATCH(batch);
3516     intel_batchbuffer_end_atomic(batch);
3517 }
3518
3519 VASurfaceID
3520 i965_post_processing(
3521     VADriverContextP   ctx,
3522     VASurfaceID        surface,
3523     const VARectangle *src_rect,
3524     const VARectangle *dst_rect,
3525     unsigned int       flags,
3526     int               *has_done_scaling
3527 )
3528 {
3529     struct i965_driver_data *i965 = i965_driver_data(ctx);
3530     VASurfaceID in_surface_id = surface;
3531     VASurfaceID out_surface_id = VA_INVALID_ID;
3532
3533     *has_done_scaling = 0;
3534
3535     if (HAS_PP(i965)) {
3536         struct object_surface *obj_surface;
3537         VAStatus status;
3538         struct i965_surface src_surface;
3539         struct i965_surface dst_surface;
3540
3541         obj_surface = SURFACE(in_surface_id);
3542
3543         /* Currently only support post processing for NV12 surface */
3544         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3545             return out_surface_id;
3546
3547         if (flags & I965_PP_FLAG_DEINTERLACING) {
3548             status = i965_CreateSurfaces(ctx,
3549                                          obj_surface->orig_width,
3550                                          obj_surface->orig_height,
3551                                          VA_RT_FORMAT_YUV420,
3552                                          1,
3553                                          &out_surface_id);
3554             assert(status == VA_STATUS_SUCCESS);
3555             obj_surface = SURFACE(out_surface_id);
3556             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3557             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3558             src_surface.id = in_surface_id;
3559             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3560             src_surface.flags = (flags & I965_PP_FLAG_DEINTERLACING_TOP_FISRT) ?
3561                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3562             dst_surface.id = out_surface_id;
3563             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3564             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3565
3566             i965_post_processing_internal(ctx, i965->pp_context,
3567                                           &src_surface,
3568                                           src_rect,
3569                                           &dst_surface,
3570                                           dst_rect,
3571                                           PP_NV12_DNDI,
3572                                           NULL);
3573         }
3574
3575         if (flags & I965_PP_FLAG_AVS) {
3576             struct i965_render_state *render_state = &i965->render_state;
3577             struct intel_region *dest_region = render_state->draw_region;
3578
3579             if (out_surface_id != VA_INVALID_ID)
3580                 in_surface_id = out_surface_id;
3581
3582             status = i965_CreateSurfaces(ctx,
3583                                          dest_region->width,
3584                                          dest_region->height,
3585                                          VA_RT_FORMAT_YUV420,
3586                                          1,
3587                                          &out_surface_id);
3588             assert(status == VA_STATUS_SUCCESS);
3589             obj_surface = SURFACE(out_surface_id);
3590             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3591             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3592             src_surface.id = in_surface_id;
3593             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3594             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3595             dst_surface.id = out_surface_id;
3596             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3597             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3598
3599             i965_post_processing_internal(ctx, i965->pp_context,
3600                                           &src_surface,
3601                                           src_rect,
3602                                           &dst_surface,
3603                                           dst_rect,
3604                                           PP_NV12_AVS,
3605                                           NULL);
3606
3607             if (in_surface_id != surface)
3608                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3609
3610             *has_done_scaling = 1;
3611         }
3612     }
3613
3614     return out_surface_id;
3615 }
3616
3617 static VAStatus
3618 i965_image_i420_processing(VADriverContextP ctx,
3619                            const struct i965_surface *src_surface,
3620                            const VARectangle *src_rect,
3621                            struct i965_surface *dst_surface,
3622                            const VARectangle *dst_rect)
3623 {
3624     struct i965_driver_data *i965 = i965_driver_data(ctx);
3625     struct i965_post_processing_context *pp_context = i965->pp_context;
3626     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3627
3628     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3629         i965_post_processing_internal(ctx, i965->pp_context,
3630                                       src_surface,
3631                                       src_rect,
3632                                       dst_surface,
3633                                       dst_rect,
3634                                       PP_PL3_LOAD_SAVE_N12,
3635                                       NULL);
3636     } else {
3637         i965_post_processing_internal(ctx, i965->pp_context,
3638                                       src_surface,
3639                                       src_rect,
3640                                       dst_surface,
3641                                       dst_rect,
3642                                       PP_PL3_LOAD_SAVE_PL3,
3643                                       NULL);
3644     }
3645
3646     intel_batchbuffer_flush(pp_context->batch);
3647
3648     return VA_STATUS_SUCCESS;
3649 }
3650
3651 static VAStatus
3652 i965_image_nv12_processing(VADriverContextP ctx,
3653                            const struct i965_surface *src_surface,
3654                            const VARectangle *src_rect,
3655                            struct i965_surface *dst_surface,
3656                            const VARectangle *dst_rect)
3657 {
3658     struct i965_driver_data *i965 = i965_driver_data(ctx);
3659     struct i965_post_processing_context *pp_context = i965->pp_context;
3660     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3661
3662     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3663         i965_post_processing_internal(ctx, i965->pp_context,
3664                                       src_surface,
3665                                       src_rect,
3666                                       dst_surface,
3667                                       dst_rect,
3668                                       PP_NV12_LOAD_SAVE_N12,
3669                                       NULL);
3670     } else {
3671         i965_post_processing_internal(ctx, i965->pp_context,
3672                                       src_surface,
3673                                       src_rect,
3674                                       dst_surface,
3675                                       dst_rect,
3676                                       PP_NV12_LOAD_SAVE_PL3,
3677                                       NULL);
3678     }
3679
3680     intel_batchbuffer_flush(pp_context->batch);
3681
3682     return VA_STATUS_SUCCESS;
3683 }
3684
3685 VAStatus
3686 i965_image_processing(VADriverContextP ctx,
3687                       const struct i965_surface *src_surface,
3688                       const VARectangle *src_rect,
3689                       struct i965_surface *dst_surface,
3690                       const VARectangle *dst_rect)
3691 {
3692     struct i965_driver_data *i965 = i965_driver_data(ctx);
3693     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
3694
3695     if (HAS_PP(i965)) {
3696         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
3697
3698         switch (fourcc) {
3699         case VA_FOURCC('Y', 'V', '1', '2'):
3700         case VA_FOURCC('I', '4', '2', '0'):
3701             status = i965_image_i420_processing(ctx,
3702                                                 src_surface,
3703                                                 src_rect,
3704                                                 dst_surface,
3705                                                 dst_rect);
3706             break;
3707
3708         case  VA_FOURCC('N', 'V', '1', '2'):
3709             status = i965_image_nv12_processing(ctx,
3710                                                 src_surface,
3711                                                 src_rect,
3712                                                 dst_surface,
3713                                                 dst_rect);
3714             break;
3715
3716         default:
3717             status = VA_STATUS_ERROR_UNIMPLEMENTED;
3718             break;
3719         }
3720     }
3721
3722     return status;
3723 }
3724
3725 static void
3726 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
3727 {
3728     int i;
3729
3730     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3731     pp_context->surface_state_binding_table.bo = NULL;
3732
3733     dri_bo_unreference(pp_context->curbe.bo);
3734     pp_context->curbe.bo = NULL;
3735
3736     dri_bo_unreference(pp_context->sampler_state_table.bo);
3737     pp_context->sampler_state_table.bo = NULL;
3738
3739     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3740     pp_context->sampler_state_table.bo_8x8 = NULL;
3741
3742     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3743     pp_context->sampler_state_table.bo_8x8_uv = NULL;
3744
3745     dri_bo_unreference(pp_context->idrt.bo);
3746     pp_context->idrt.bo = NULL;
3747     pp_context->idrt.num_interface_descriptors = 0;
3748
3749     dri_bo_unreference(pp_context->vfe_state.bo);
3750     pp_context->vfe_state.bo = NULL;
3751
3752     dri_bo_unreference(pp_context->stmm.bo);
3753     pp_context->stmm.bo = NULL;
3754
3755     for (i = 0; i < NUM_PP_MODULES; i++) {
3756         struct pp_module *pp_module = &pp_context->pp_modules[i];
3757
3758         dri_bo_unreference(pp_module->kernel.bo);
3759         pp_module->kernel.bo = NULL;
3760     }
3761
3762     free(pp_context->pp_static_parameter);
3763     free(pp_context->pp_inline_parameter);
3764     pp_context->pp_static_parameter = NULL;
3765     pp_context->pp_inline_parameter = NULL;
3766 }
3767
3768 Bool
3769 i965_post_processing_terminate(VADriverContextP ctx)
3770 {
3771     struct i965_driver_data *i965 = i965_driver_data(ctx);
3772     struct i965_post_processing_context *pp_context = i965->pp_context;
3773
3774     if (pp_context) {
3775         i965_post_processing_context_finalize(pp_context);
3776         free(pp_context);
3777     }
3778
3779     i965->pp_context = NULL;
3780
3781     return True;
3782 }
3783
3784 static void
3785 i965_post_processing_context_init(VADriverContextP ctx,
3786                                   struct i965_post_processing_context *pp_context,
3787                                   struct intel_batchbuffer *batch)
3788 {
3789     struct i965_driver_data *i965 = i965_driver_data(ctx);
3790     int i;
3791
3792     pp_context->urb.size = URB_SIZE((&i965->intel));
3793     pp_context->urb.num_vfe_entries = 32;
3794     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
3795     pp_context->urb.num_cs_entries = 1;
3796
3797     if (IS_GEN7(i965->intel.device_id))
3798         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
3799     else
3800         pp_context->urb.size_cs_entry = 2;
3801
3802     pp_context->urb.vfe_start = 0;
3803     pp_context->urb.cs_start = pp_context->urb.vfe_start +
3804         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
3805     assert(pp_context->urb.cs_start +
3806            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
3807
3808     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
3809     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
3810     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
3811
3812     if (IS_GEN7(i965->intel.device_id))
3813         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
3814     else if (IS_GEN6(i965->intel.device_id))
3815         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
3816     else if (IS_IRONLAKE(i965->intel.device_id))
3817         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
3818
3819     for (i = 0; i < NUM_PP_MODULES; i++) {
3820         struct pp_module *pp_module = &pp_context->pp_modules[i];
3821         dri_bo_unreference(pp_module->kernel.bo);
3822         if (pp_module->kernel.bin && pp_module->kernel.size) {
3823             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
3824                                                 pp_module->kernel.name,
3825                                                 pp_module->kernel.size,
3826                                                 4096);
3827             assert(pp_module->kernel.bo);
3828             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
3829         } else {
3830             pp_module->kernel.bo = NULL;
3831         }
3832     }
3833
3834     /* static & inline parameters */
3835     if (IS_GEN7(i965->intel.device_id)) {
3836         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
3837         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
3838     } else {
3839         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
3840         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
3841     }
3842
3843     pp_context->batch = batch;
3844 }
3845
3846 Bool
3847 i965_post_processing_init(VADriverContextP ctx)
3848 {
3849     struct i965_driver_data *i965 = i965_driver_data(ctx);
3850     struct i965_post_processing_context *pp_context = i965->pp_context;
3851
3852     if (HAS_PP(i965)) {
3853         if (pp_context == NULL) {
3854             pp_context = calloc(1, sizeof(*pp_context));
3855             i965_post_processing_context_init(ctx, pp_context, i965->batch);
3856             i965->pp_context = pp_context;
3857         }
3858     }
3859
3860     return True;
3861 }
3862
3863 static const int procfilter_to_pp_flag[10] = {
3864     PP_NULL,    /* VAProcFilterNone */
3865     PP_NULL,    /* VAProcFilterDering */
3866     PP_NULL,    /* VAProcFilterDeblocking */
3867     PP_NV12_DN, /* VAProcFilterNoiseReduction */
3868     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
3869     PP_NULL,    /* VAProcFilterSharpening */
3870     PP_NULL,    /* VAProcFilterColorEnhancement */
3871     PP_NULL,    /* VAProcFilterProcAmp */
3872     PP_NULL,    /* VAProcFilterComposition */
3873     PP_NULL,    /* VAProcFilterFrameRateConversion */
3874 };
3875
3876 static const int proc_frame_to_pp_frame[3] = {
3877     I965_SURFACE_FLAG_FRAME,
3878     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
3879     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
3880 };
3881
3882 static void
3883 i965_proc_picture(VADriverContextP ctx,
3884                   VAProfile profile,
3885                   union codec_state *codec_state,
3886                   struct hw_context *hw_context)
3887 {
3888     struct i965_driver_data *i965 = i965_driver_data(ctx);
3889     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
3890     struct proc_state *proc_state = &codec_state->proc;
3891     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
3892     VAProcInputParameterBuffer *input_param = (VAProcInputParameterBuffer *)proc_state->input_param->buffer;
3893     struct object_surface *obj_surface;
3894     struct i965_surface src_surface, dst_surface;
3895     VAStatus status;
3896     int i;
3897     VASurfaceID tmp_surfaces[VA_PROC_PIPELINE_MAX_NUM_FILTERS + 4];
3898     int num_tmp_surfaces = 0;
3899     unsigned int tiling = 0, swizzle = 0;
3900     int in_width, in_height;
3901
3902     assert(input_param->surface != VA_INVALID_ID);
3903     assert(proc_state->current_render_target != VA_INVALID_ID);
3904
3905     obj_surface = SURFACE(input_param->surface);
3906     in_width = obj_surface->orig_width;
3907     in_height = obj_surface->orig_height;
3908     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3909
3910     src_surface.id = input_param->surface;
3911     src_surface.type = I965_SURFACE_TYPE_SURFACE;
3912     src_surface.flags = proc_frame_to_pp_frame[input_param->flags];
3913
3914     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
3915         struct i965_surface src_surface, dst_surface;
3916         VARectangle src_rect, dst_rect;
3917         VASurfaceID out_surface_id = VA_INVALID_ID;
3918
3919         src_surface.id = input_param->surface;
3920         src_surface.type = I965_SURFACE_TYPE_SURFACE;
3921         src_surface.flags = I965_SURFACE_FLAG_FRAME;
3922         src_rect.x = 0;
3923         src_rect.y = 0;
3924         src_rect.width = in_width;
3925         src_rect.height = in_height;
3926
3927         status = i965_CreateSurfaces(ctx,
3928                                      in_width,
3929                                      in_height,
3930                                      VA_RT_FORMAT_YUV420,
3931                                      1,
3932                                      &out_surface_id);
3933         assert(status == VA_STATUS_SUCCESS);
3934         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
3935         obj_surface = SURFACE(out_surface_id);
3936         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
3937
3938         dst_surface.id = out_surface_id;
3939         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3940         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3941         dst_rect.x = 0;
3942         dst_rect.y = 0;
3943         dst_rect.width = in_width;
3944         dst_rect.height = in_height;
3945
3946         status = i965_image_processing(ctx,
3947                                        &src_surface,
3948                                        &src_rect,
3949                                        &dst_surface,
3950                                        &dst_rect);
3951         assert(status == VA_STATUS_SUCCESS);
3952
3953         src_surface.id = out_surface_id;
3954         src_surface.type = I965_SURFACE_TYPE_SURFACE;
3955         src_surface.flags = proc_frame_to_pp_frame[input_param->flags];
3956     }
3957
3958     obj_surface = SURFACE(proc_state->current_render_target);
3959     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3960
3961     for (i = 0; i < VA_PROC_PIPELINE_MAX_NUM_FILTERS; i++) {
3962         VAProcFilterType filter_type = pipeline_param->filter_pipeline[i];
3963         VASurfaceID out_surface_id = VA_INVALID_ID;
3964         void *filter_param = NULL;
3965
3966         if (procfilter_to_pp_flag[filter_type] != PP_NULL) {
3967             if (proc_state->filter_param[filter_type])
3968                 filter_param = proc_state->filter_param[filter_type]->buffer;
3969
3970             status = i965_CreateSurfaces(ctx,
3971                                          in_width,
3972                                          in_height,
3973                                          VA_RT_FORMAT_YUV420,
3974                                          1,
3975                                          &out_surface_id);
3976             assert(status == VA_STATUS_SUCCESS);
3977             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
3978             obj_surface = SURFACE(out_surface_id);
3979             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3980             dst_surface.id = out_surface_id;
3981             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3982             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
3983                                                    &src_surface,
3984                                                    &input_param->region,
3985                                                    &dst_surface,
3986                                                    &input_param->region,
3987                                                    procfilter_to_pp_flag[filter_type],
3988                                                    filter_param);
3989
3990             if (status == VA_STATUS_SUCCESS) {
3991                 src_surface.id = dst_surface.id;
3992                 src_surface.type = dst_surface.type;
3993                 src_surface.flags = dst_surface.flags;
3994             }
3995         }
3996     }
3997
3998     dst_surface.id = proc_state->current_render_target;
3999     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4000     i965_post_processing_internal(ctx, &proc_context->pp_context,
4001                                   &src_surface,
4002                                   &input_param->region,
4003                                   &dst_surface,
4004                                   &pipeline_param->output_region,
4005                                   (pipeline_param->flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4006                                   PP_NV12_AVS : PP_NV12_SCALING,
4007                                   NULL);
4008
4009     if (num_tmp_surfaces)
4010         i965_DestroySurfaces(ctx,
4011                              tmp_surfaces,
4012                              num_tmp_surfaces);
4013
4014     intel_batchbuffer_flush(hw_context->batch);
4015 }
4016
4017 static void
4018 i965_proc_context_destroy(void *hw_context)
4019 {
4020     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4021
4022     i965_post_processing_context_finalize(&proc_context->pp_context);
4023     intel_batchbuffer_free(proc_context->base.batch);
4024     free(proc_context);
4025 }
4026
4027 struct hw_context *
4028 i965_proc_context_init(VADriverContextP ctx, VAProfile profile)
4029 {
4030     struct intel_driver_data *intel = intel_driver_data(ctx);
4031     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4032
4033     proc_context->base.destroy = i965_proc_context_destroy;
4034     proc_context->base.run = i965_proc_picture;
4035     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4036     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4037
4038     return (struct hw_context *)proc_context;
4039 }