2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_post_processing.h"
40 #include "i965_render.h"
42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) || \
43 IS_GEN6((ctx)->intel.device_id) || \
44 IS_GEN7((ctx)->intel.device_id))
46 #define SURFACE_STATE_PADDED_SIZE_0_I965 ALIGN(sizeof(struct i965_surface_state), 32)
47 #define SURFACE_STATE_PADDED_SIZE_1_I965 ALIGN(sizeof(struct i965_surface_state2), 32)
48 #define SURFACE_STATE_PADDED_SIZE_I965 MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
52 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
54 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
55 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
56 #define BINDING_TABLE_OFFSET SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
58 static const uint32_t pp_null_gen5[][4] = {
59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
82 static const uint32_t pp_nv12_avs_gen5[][4] = {
83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
90 static const uint32_t pp_nv12_dn_gen5[][4] = {
91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
111 const struct i965_surface *src_surface,
112 const VARectangle *src_rect,
113 struct i965_surface *dst_surface,
114 const VARectangle *dst_rect,
116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
117 const struct i965_surface *src_surface,
118 const VARectangle *src_rect,
119 struct i965_surface *dst_surface,
120 const VARectangle *dst_rect,
122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
123 const struct i965_surface *src_surface,
124 const VARectangle *src_rect,
125 struct i965_surface *dst_surface,
126 const VARectangle *dst_rect,
128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
129 const struct i965_surface *src_surface,
130 const VARectangle *src_rect,
131 struct i965_surface *dst_surface,
132 const VARectangle *dst_rect,
134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
135 const struct i965_surface *src_surface,
136 const VARectangle *src_rect,
137 struct i965_surface *dst_surface,
138 const VARectangle *dst_rect,
140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
141 const struct i965_surface *src_surface,
142 const VARectangle *src_rect,
143 struct i965_surface *dst_surface,
144 const VARectangle *dst_rect,
146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
147 const struct i965_surface *src_surface,
148 const VARectangle *src_rect,
149 struct i965_surface *dst_surface,
150 const VARectangle *dst_rect,
153 static struct pp_module pp_modules_gen5[] = {
156 "NULL module (for testing)",
159 sizeof(pp_null_gen5),
169 PP_NV12_LOAD_SAVE_N12,
170 pp_nv12_load_save_nv12_gen5,
171 sizeof(pp_nv12_load_save_nv12_gen5),
175 pp_plx_load_save_plx_initialize,
181 PP_NV12_LOAD_SAVE_PL3,
182 pp_nv12_load_save_pl3_gen5,
183 sizeof(pp_nv12_load_save_pl3_gen5),
187 pp_plx_load_save_plx_initialize,
193 PP_PL3_LOAD_SAVE_N12,
194 pp_pl3_load_save_nv12_gen5,
195 sizeof(pp_pl3_load_save_nv12_gen5),
199 pp_plx_load_save_plx_initialize,
205 PP_PL3_LOAD_SAVE_N12,
206 pp_pl3_load_save_pl3_gen5,
207 sizeof(pp_pl3_load_save_pl3_gen5),
211 pp_plx_load_save_plx_initialize
216 "NV12 Scaling module",
218 pp_nv12_scaling_gen5,
219 sizeof(pp_nv12_scaling_gen5),
223 pp_nv12_scaling_initialize,
231 sizeof(pp_nv12_avs_gen5),
235 pp_nv12_avs_initialize_nlas,
243 sizeof(pp_nv12_dndi_gen5),
247 pp_nv12_dndi_initialize,
255 sizeof(pp_nv12_dn_gen5),
259 pp_nv12_dn_initialize,
265 PP_NV12_LOAD_SAVE_PA,
266 pp_nv12_load_save_pa_gen5,
267 sizeof(pp_nv12_load_save_pa_gen5),
271 pp_plx_load_save_plx_initialize,
278 pp_pl3_load_save_pa_gen5,
279 sizeof(pp_pl3_load_save_pa_gen5),
283 pp_plx_load_save_plx_initialize,
289 PP_PA_LOAD_SAVE_NV12,
290 pp_pa_load_save_nv12_gen5,
291 sizeof(pp_pa_load_save_nv12_gen5),
295 pp_plx_load_save_plx_initialize,
302 pp_pa_load_save_pl3_gen5,
303 sizeof(pp_pa_load_save_pl3_gen5),
307 pp_plx_load_save_plx_initialize,
312 static const uint32_t pp_null_gen6[][4] = {
313 #include "shaders/post_processing/gen5_6/null.g6b"
316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
336 static const uint32_t pp_nv12_avs_gen6[][4] = {
337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
344 static const uint32_t pp_nv12_dn_gen6[][4] = {
345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
364 static struct pp_module pp_modules_gen6[] = {
367 "NULL module (for testing)",
370 sizeof(pp_null_gen6),
380 PP_NV12_LOAD_SAVE_N12,
381 pp_nv12_load_save_nv12_gen6,
382 sizeof(pp_nv12_load_save_nv12_gen6),
386 pp_plx_load_save_plx_initialize,
392 PP_NV12_LOAD_SAVE_PL3,
393 pp_nv12_load_save_pl3_gen6,
394 sizeof(pp_nv12_load_save_pl3_gen6),
398 pp_plx_load_save_plx_initialize,
404 PP_PL3_LOAD_SAVE_N12,
405 pp_pl3_load_save_nv12_gen6,
406 sizeof(pp_pl3_load_save_nv12_gen6),
410 pp_plx_load_save_plx_initialize,
416 PP_PL3_LOAD_SAVE_N12,
417 pp_pl3_load_save_pl3_gen6,
418 sizeof(pp_pl3_load_save_pl3_gen6),
422 pp_plx_load_save_plx_initialize,
427 "NV12 Scaling module",
429 pp_nv12_scaling_gen6,
430 sizeof(pp_nv12_scaling_gen6),
434 gen6_nv12_scaling_initialize,
442 sizeof(pp_nv12_avs_gen6),
446 pp_nv12_avs_initialize_nlas,
454 sizeof(pp_nv12_dndi_gen6),
458 pp_nv12_dndi_initialize,
466 sizeof(pp_nv12_dn_gen6),
470 pp_nv12_dn_initialize,
475 PP_NV12_LOAD_SAVE_PA,
476 pp_nv12_load_save_pa_gen6,
477 sizeof(pp_nv12_load_save_pa_gen6),
481 pp_plx_load_save_plx_initialize,
488 pp_pl3_load_save_pa_gen6,
489 sizeof(pp_pl3_load_save_pa_gen6),
493 pp_plx_load_save_plx_initialize,
499 PP_PA_LOAD_SAVE_NV12,
500 pp_pa_load_save_nv12_gen6,
501 sizeof(pp_pa_load_save_nv12_gen6),
505 pp_plx_load_save_plx_initialize,
512 pp_pa_load_save_pl3_gen6,
513 sizeof(pp_pa_load_save_pl3_gen6),
517 pp_plx_load_save_plx_initialize,
522 static const uint32_t pp_null_gen7[][4] = {
525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
542 #include "shaders/post_processing/gen7/avs.g7b"
545 static const uint32_t pp_nv12_avs_gen7[][4] = {
546 #include "shaders/post_processing/gen7/avs.g7b"
549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
550 // #include "shaders/post_processing/gen7/dndi.g7b"
553 static const uint32_t pp_nv12_dn_gen7[][4] = {
555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
557 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
559 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
561 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
564 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
565 const struct i965_surface *src_surface,
566 const VARectangle *src_rect,
567 struct i965_surface *dst_surface,
568 const VARectangle *dst_rect,
570 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
571 const struct i965_surface *src_surface,
572 const VARectangle *src_rect,
573 struct i965_surface *dst_surface,
574 const VARectangle *dst_rect,
576 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
577 const struct i965_surface *src_surface,
578 const VARectangle *src_rect,
579 struct i965_surface *dst_surface,
580 const VARectangle *dst_rect,
583 static struct pp_module pp_modules_gen7[] = {
586 "NULL module (for testing)",
589 sizeof(pp_null_gen7),
599 PP_NV12_LOAD_SAVE_N12,
600 pp_nv12_load_save_nv12_gen7,
601 sizeof(pp_nv12_load_save_nv12_gen7),
605 gen7_pp_plx_avs_initialize,
611 PP_NV12_LOAD_SAVE_PL3,
612 pp_nv12_load_save_pl3_gen7,
613 sizeof(pp_nv12_load_save_pl3_gen7),
617 gen7_pp_plx_avs_initialize,
623 PP_PL3_LOAD_SAVE_N12,
624 pp_pl3_load_save_nv12_gen7,
625 sizeof(pp_pl3_load_save_nv12_gen7),
629 gen7_pp_plx_avs_initialize,
635 PP_PL3_LOAD_SAVE_N12,
636 pp_pl3_load_save_pl3_gen7,
637 sizeof(pp_pl3_load_save_pl3_gen7),
641 gen7_pp_plx_avs_initialize,
646 "NV12 Scaling module",
648 pp_nv12_scaling_gen7,
649 sizeof(pp_nv12_scaling_gen7),
653 gen7_pp_plx_avs_initialize,
661 sizeof(pp_nv12_avs_gen7),
665 gen7_pp_plx_avs_initialize,
673 sizeof(pp_nv12_dndi_gen7),
677 gen7_pp_nv12_dndi_initialize,
685 sizeof(pp_nv12_dn_gen7),
689 gen7_pp_nv12_dn_initialize,
694 PP_NV12_LOAD_SAVE_PA,
695 pp_nv12_load_save_pa_gen7,
696 sizeof(pp_nv12_load_save_pa_gen7),
700 pp_plx_load_save_plx_initialize,
707 pp_pl3_load_save_pa_gen7,
708 sizeof(pp_pl3_load_save_pa_gen7),
712 pp_plx_load_save_plx_initialize,
718 PP_PA_LOAD_SAVE_NV12,
719 pp_pa_load_save_nv12_gen7,
720 sizeof(pp_pa_load_save_nv12_gen7),
724 pp_plx_load_save_plx_initialize,
731 pp_pa_load_save_pl3_gen7,
732 sizeof(pp_pa_load_save_pl3_gen7),
736 pp_plx_load_save_plx_initialize,
742 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
744 struct i965_driver_data *i965 = i965_driver_data(ctx);
747 if (surface->type == I965_SURFACE_TYPE_IMAGE) {
748 struct object_image *obj_image = IMAGE(surface->id);
749 fourcc = obj_image->image.format.fourcc;
751 struct object_surface *obj_surface = SURFACE(surface->id);
752 fourcc = obj_surface->fourcc;
759 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
762 case I915_TILING_NONE:
763 ss->ss3.tiled_surface = 0;
764 ss->ss3.tile_walk = 0;
767 ss->ss3.tiled_surface = 1;
768 ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
771 ss->ss3.tiled_surface = 1;
772 ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
778 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
781 case I915_TILING_NONE:
782 ss->ss2.tiled_surface = 0;
783 ss->ss2.tile_walk = 0;
786 ss->ss2.tiled_surface = 1;
787 ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
790 ss->ss2.tiled_surface = 1;
791 ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
797 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
800 case I915_TILING_NONE:
801 ss->ss0.tiled_surface = 0;
802 ss->ss0.tile_walk = 0;
805 ss->ss0.tiled_surface = 1;
806 ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
809 ss->ss0.tiled_surface = 1;
810 ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
816 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
819 case I915_TILING_NONE:
820 ss->ss2.tiled_surface = 0;
821 ss->ss2.tile_walk = 0;
824 ss->ss2.tiled_surface = 1;
825 ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
828 ss->ss2.tiled_surface = 1;
829 ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
835 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
837 struct i965_interface_descriptor *desc;
839 int pp_index = pp_context->current_pp;
841 bo = pp_context->idrt.bo;
845 memset(desc, 0, sizeof(*desc));
846 desc->desc0.grf_reg_blocks = 10;
847 desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
848 desc->desc1.const_urb_entry_read_offset = 0;
849 desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
850 desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
851 desc->desc2.sampler_count = 0;
852 desc->desc3.binding_table_entry_count = 0;
853 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
855 dri_bo_emit_reloc(bo,
856 I915_GEM_DOMAIN_INSTRUCTION, 0,
857 desc->desc0.grf_reg_blocks,
858 offsetof(struct i965_interface_descriptor, desc0),
859 pp_context->pp_modules[pp_index].kernel.bo);
861 dri_bo_emit_reloc(bo,
862 I915_GEM_DOMAIN_INSTRUCTION, 0,
863 desc->desc2.sampler_count << 2,
864 offsetof(struct i965_interface_descriptor, desc2),
865 pp_context->sampler_state_table.bo);
868 pp_context->idrt.num_interface_descriptors++;
872 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
874 struct i965_vfe_state *vfe_state;
877 bo = pp_context->vfe_state.bo;
880 vfe_state = bo->virtual;
881 memset(vfe_state, 0, sizeof(*vfe_state));
882 vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
883 vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
884 vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
885 vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
886 vfe_state->vfe1.children_present = 0;
887 vfe_state->vfe2.interface_descriptor_base =
888 pp_context->idrt.bo->offset >> 4; /* reloc */
889 dri_bo_emit_reloc(bo,
890 I915_GEM_DOMAIN_INSTRUCTION, 0,
892 offsetof(struct i965_vfe_state, vfe2),
893 pp_context->idrt.bo);
898 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
900 unsigned char *constant_buffer;
901 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
903 assert(sizeof(*pp_static_parameter) == 128);
904 dri_bo_map(pp_context->curbe.bo, 1);
905 assert(pp_context->curbe.bo->virtual);
906 constant_buffer = pp_context->curbe.bo->virtual;
907 memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
908 dri_bo_unmap(pp_context->curbe.bo);
912 ironlake_pp_states_setup(VADriverContextP ctx,
913 struct i965_post_processing_context *pp_context)
915 ironlake_pp_interface_descriptor_table(pp_context);
916 ironlake_pp_vfe_state(pp_context);
917 ironlake_pp_upload_constants(pp_context);
921 ironlake_pp_pipeline_select(VADriverContextP ctx,
922 struct i965_post_processing_context *pp_context)
924 struct intel_batchbuffer *batch = pp_context->batch;
926 BEGIN_BATCH(batch, 1);
927 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
928 ADVANCE_BATCH(batch);
932 ironlake_pp_urb_layout(VADriverContextP ctx,
933 struct i965_post_processing_context *pp_context)
935 struct intel_batchbuffer *batch = pp_context->batch;
936 unsigned int vfe_fence, cs_fence;
938 vfe_fence = pp_context->urb.cs_start;
939 cs_fence = pp_context->urb.size;
941 BEGIN_BATCH(batch, 3);
942 OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
945 (vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */
946 (cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */
947 ADVANCE_BATCH(batch);
951 ironlake_pp_state_base_address(VADriverContextP ctx,
952 struct i965_post_processing_context *pp_context)
954 struct intel_batchbuffer *batch = pp_context->batch;
956 BEGIN_BATCH(batch, 8);
957 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
958 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
959 OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
960 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
961 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
962 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
963 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
964 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
965 ADVANCE_BATCH(batch);
969 ironlake_pp_state_pointers(VADriverContextP ctx,
970 struct i965_post_processing_context *pp_context)
972 struct intel_batchbuffer *batch = pp_context->batch;
974 BEGIN_BATCH(batch, 3);
975 OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
977 OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
978 ADVANCE_BATCH(batch);
982 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
983 struct i965_post_processing_context *pp_context)
985 struct intel_batchbuffer *batch = pp_context->batch;
987 BEGIN_BATCH(batch, 2);
988 OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
990 ((pp_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */
991 (pp_context->urb.num_cs_entries << 0)); /* Number of URB Entries */
992 ADVANCE_BATCH(batch);
996 ironlake_pp_constant_buffer(VADriverContextP ctx,
997 struct i965_post_processing_context *pp_context)
999 struct intel_batchbuffer *batch = pp_context->batch;
1001 BEGIN_BATCH(batch, 2);
1002 OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1003 OUT_RELOC(batch, pp_context->curbe.bo,
1004 I915_GEM_DOMAIN_INSTRUCTION, 0,
1005 pp_context->urb.size_cs_entry - 1);
1006 ADVANCE_BATCH(batch);
1010 ironlake_pp_object_walker(VADriverContextP ctx,
1011 struct i965_post_processing_context *pp_context)
1013 struct intel_batchbuffer *batch = pp_context->batch;
1014 int x, x_steps, y, y_steps;
1015 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1017 x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1018 y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1020 for (y = 0; y < y_steps; y++) {
1021 for (x = 0; x < x_steps; x++) {
1022 if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1023 BEGIN_BATCH(batch, 20);
1024 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1025 OUT_BATCH(batch, 0);
1026 OUT_BATCH(batch, 0); /* no indirect data */
1027 OUT_BATCH(batch, 0);
1029 /* inline data grf 5-6 */
1030 assert(sizeof(*pp_inline_parameter) == 64);
1031 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1033 ADVANCE_BATCH(batch);
1040 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1041 struct i965_post_processing_context *pp_context)
1043 struct intel_batchbuffer *batch = pp_context->batch;
1045 intel_batchbuffer_start_atomic(batch, 0x1000);
1046 intel_batchbuffer_emit_mi_flush(batch);
1047 ironlake_pp_pipeline_select(ctx, pp_context);
1048 ironlake_pp_state_base_address(ctx, pp_context);
1049 ironlake_pp_state_pointers(ctx, pp_context);
1050 ironlake_pp_urb_layout(ctx, pp_context);
1051 ironlake_pp_cs_urb_layout(ctx, pp_context);
1052 ironlake_pp_constant_buffer(ctx, pp_context);
1053 ironlake_pp_object_walker(ctx, pp_context);
1054 intel_batchbuffer_end_atomic(batch);
1058 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1059 dri_bo *surf_bo, unsigned long surf_bo_offset,
1060 int width, int height, int pitch, int format,
1061 int index, int is_target)
1063 struct i965_surface_state *ss;
1065 unsigned int tiling;
1066 unsigned int swizzle;
1068 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1069 ss_bo = pp_context->surface_state_binding_table.bo;
1072 dri_bo_map(ss_bo, True);
1073 assert(ss_bo->virtual);
1074 ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1075 memset(ss, 0, sizeof(*ss));
1076 ss->ss0.surface_type = I965_SURFACE_2D;
1077 ss->ss0.surface_format = format;
1078 ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1079 ss->ss2.width = width - 1;
1080 ss->ss2.height = height - 1;
1081 ss->ss3.pitch = pitch - 1;
1082 pp_set_surface_tiling(ss, tiling);
1083 dri_bo_emit_reloc(ss_bo,
1084 I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1086 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1088 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1089 dri_bo_unmap(ss_bo);
1093 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1094 dri_bo *surf_bo, unsigned long surf_bo_offset,
1095 int width, int height, int wpitch,
1096 int xoffset, int yoffset,
1097 int format, int interleave_chroma,
1100 struct i965_surface_state2 *ss2;
1102 unsigned int tiling;
1103 unsigned int swizzle;
1105 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1106 ss2_bo = pp_context->surface_state_binding_table.bo;
1109 dri_bo_map(ss2_bo, True);
1110 assert(ss2_bo->virtual);
1111 ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1112 memset(ss2, 0, sizeof(*ss2));
1113 ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1114 ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1115 ss2->ss1.width = width - 1;
1116 ss2->ss1.height = height - 1;
1117 ss2->ss2.pitch = wpitch - 1;
1118 ss2->ss2.interleave_chroma = interleave_chroma;
1119 ss2->ss2.surface_format = format;
1120 ss2->ss3.x_offset_for_cb = xoffset;
1121 ss2->ss3.y_offset_for_cb = yoffset;
1122 pp_set_surface2_tiling(ss2, tiling);
1123 dri_bo_emit_reloc(ss2_bo,
1124 I915_GEM_DOMAIN_RENDER, 0,
1126 SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1128 ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1129 dri_bo_unmap(ss2_bo);
1133 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1134 dri_bo *surf_bo, unsigned long surf_bo_offset,
1135 int width, int height, int pitch, int format,
1136 int index, int is_target)
1138 struct gen7_surface_state *ss;
1140 unsigned int tiling;
1141 unsigned int swizzle;
1143 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1144 ss_bo = pp_context->surface_state_binding_table.bo;
1147 dri_bo_map(ss_bo, True);
1148 assert(ss_bo->virtual);
1149 ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1150 memset(ss, 0, sizeof(*ss));
1151 ss->ss0.surface_type = I965_SURFACE_2D;
1152 ss->ss0.surface_format = format;
1153 ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1154 ss->ss2.width = width - 1;
1155 ss->ss2.height = height - 1;
1156 ss->ss3.pitch = pitch - 1;
1157 gen7_pp_set_surface_tiling(ss, tiling);
1158 dri_bo_emit_reloc(ss_bo,
1159 I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1161 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1163 ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1164 dri_bo_unmap(ss_bo);
1168 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1169 dri_bo *surf_bo, unsigned long surf_bo_offset,
1170 int width, int height, int wpitch,
1171 int xoffset, int yoffset,
1172 int format, int interleave_chroma,
1175 struct gen7_surface_state2 *ss2;
1177 unsigned int tiling;
1178 unsigned int swizzle;
1180 dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1181 ss2_bo = pp_context->surface_state_binding_table.bo;
1184 dri_bo_map(ss2_bo, True);
1185 assert(ss2_bo->virtual);
1186 ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1187 memset(ss2, 0, sizeof(*ss2));
1188 ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1189 ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1190 ss2->ss1.width = width - 1;
1191 ss2->ss1.height = height - 1;
1192 ss2->ss2.pitch = wpitch - 1;
1193 ss2->ss2.interleave_chroma = interleave_chroma;
1194 ss2->ss2.surface_format = format;
1195 ss2->ss3.x_offset_for_cb = xoffset;
1196 ss2->ss3.y_offset_for_cb = yoffset;
1197 gen7_pp_set_surface2_tiling(ss2, tiling);
1198 dri_bo_emit_reloc(ss2_bo,
1199 I915_GEM_DOMAIN_RENDER, 0,
1201 SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1203 ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1204 dri_bo_unmap(ss2_bo);
1208 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1209 const struct i965_surface *surface,
1210 int base_index, int is_target,
1211 int *width, int *height, int *pitch, int *offset)
1213 struct i965_driver_data *i965 = i965_driver_data(ctx);
1214 struct object_surface *obj_surface;
1215 struct object_image *obj_image;
1217 int fourcc = pp_get_surface_fourcc(ctx, surface);
1219 const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1220 const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1222 int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1223 int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1225 if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1226 obj_surface = SURFACE(surface->id);
1227 bo = obj_surface->bo;
1228 width[0] = obj_surface->orig_width;
1229 height[0] = obj_surface->orig_height;
1230 pitch[0] = obj_surface->width;
1234 width[0] = obj_surface->orig_width * 2;
1235 pitch[0] = obj_surface->width * 2;
1237 else if (interleaved_uv) {
1238 width[1] = obj_surface->orig_width;
1239 height[1] = obj_surface->orig_height / 2;
1240 pitch[1] = obj_surface->width;
1241 offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1243 width[1] = obj_surface->orig_width / 2;
1244 height[1] = obj_surface->orig_height / 2;
1245 pitch[1] = obj_surface->width / 2;
1246 offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1247 width[2] = obj_surface->orig_width / 2;
1248 height[2] = obj_surface->orig_height / 2;
1249 pitch[2] = obj_surface->width / 2;
1250 offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1253 obj_image = IMAGE(surface->id);
1255 width[0] = obj_image->image.width;
1256 height[0] = obj_image->image.height;
1257 pitch[0] = obj_image->image.pitches[0];
1258 offset[0] = obj_image->image.offsets[0];
1261 width[0] = obj_image->image.width * 2;
1263 else if (interleaved_uv) {
1264 width[1] = obj_image->image.width;
1265 height[1] = obj_image->image.height / 2;
1266 pitch[1] = obj_image->image.pitches[1];
1267 offset[1] = obj_image->image.offsets[1];
1269 width[1] = obj_image->image.width / 2;
1270 height[1] = obj_image->image.height / 2;
1271 pitch[1] = obj_image->image.pitches[1];
1272 offset[1] = obj_image->image.offsets[1];
1273 width[2] = obj_image->image.width / 2;
1274 height[2] = obj_image->image.height / 2;
1275 pitch[2] = obj_image->image.pitches[2];
1276 offset[2] = obj_image->image.offsets[2];
1281 i965_pp_set_surface_state(ctx, pp_context,
1283 width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1284 base_index, is_target);
1287 if (interleaved_uv) {
1288 i965_pp_set_surface_state(ctx, pp_context,
1290 width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1291 base_index + 1, is_target);
1294 i965_pp_set_surface_state(ctx, pp_context,
1296 width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1297 base_index + 1, is_target);
1300 i965_pp_set_surface_state(ctx, pp_context,
1302 width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1303 base_index + 2, is_target);
1310 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1311 const struct i965_surface *surface,
1312 int base_index, int is_target,
1313 int *width, int *height, int *pitch, int *offset)
1315 struct i965_driver_data *i965 = i965_driver_data(ctx);
1316 struct object_surface *obj_surface;
1317 struct object_image *obj_image;
1319 int fourcc = pp_get_surface_fourcc(ctx, surface);
1320 const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1321 fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1322 const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1323 fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1324 int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1326 if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1327 obj_surface = SURFACE(surface->id);
1328 bo = obj_surface->bo;
1329 width[0] = obj_surface->orig_width;
1330 height[0] = obj_surface->orig_height;
1331 pitch[0] = obj_surface->width;
1334 width[1] = obj_surface->cb_cr_width;
1335 height[1] = obj_surface->cb_cr_height;
1336 pitch[1] = obj_surface->cb_cr_pitch;
1337 offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1339 width[2] = obj_surface->cb_cr_width;
1340 height[2] = obj_surface->cb_cr_height;
1341 pitch[2] = obj_surface->cb_cr_pitch;
1342 offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1344 obj_image = IMAGE(surface->id);
1346 width[0] = obj_image->image.width;
1347 height[0] = obj_image->image.height;
1348 pitch[0] = obj_image->image.pitches[0];
1349 offset[0] = obj_image->image.offsets[0];
1351 if (interleaved_uv) {
1352 width[1] = obj_image->image.width;
1353 height[1] = obj_image->image.height / 2;
1354 pitch[1] = obj_image->image.pitches[1];
1355 offset[1] = obj_image->image.offsets[1];
1357 width[1] = obj_image->image.width / 2;
1358 height[1] = obj_image->image.height / 2;
1359 pitch[1] = obj_image->image.pitches[U];
1360 offset[1] = obj_image->image.offsets[U];
1361 width[2] = obj_image->image.width / 2;
1362 height[2] = obj_image->image.height / 2;
1363 pitch[2] = obj_image->image.pitches[V];
1364 offset[2] = obj_image->image.offsets[V];
1369 gen7_pp_set_surface_state(ctx, pp_context,
1371 width[0] / 4, height[0], pitch[0],
1372 I965_SURFACEFORMAT_R8_SINT,
1375 if (interleaved_uv) {
1376 gen7_pp_set_surface_state(ctx, pp_context,
1378 width[1] / 2, height[1], pitch[1],
1379 I965_SURFACEFORMAT_R8G8_SINT,
1382 gen7_pp_set_surface_state(ctx, pp_context,
1384 width[1] / 4, height[1], pitch[1],
1385 I965_SURFACEFORMAT_R8_SINT,
1387 gen7_pp_set_surface_state(ctx, pp_context,
1389 width[2] / 4, height[2], pitch[2],
1390 I965_SURFACEFORMAT_R8_SINT,
1394 gen7_pp_set_surface2_state(ctx, pp_context,
1396 width[0], height[0], pitch[0],
1398 SURFACE_FORMAT_Y8_UNORM, 0,
1401 if (interleaved_uv) {
1402 gen7_pp_set_surface2_state(ctx, pp_context,
1404 width[1], height[1], pitch[1],
1406 SURFACE_FORMAT_R8B8_UNORM, 0,
1409 gen7_pp_set_surface2_state(ctx, pp_context,
1411 width[1], height[1], pitch[1],
1413 SURFACE_FORMAT_R8_UNORM, 0,
1415 gen7_pp_set_surface2_state(ctx, pp_context,
1417 width[2], height[2], pitch[2],
1419 SURFACE_FORMAT_R8_UNORM, 0,
1426 pp_null_x_steps(void *private_context)
1432 pp_null_y_steps(void *private_context)
1438 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1444 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1445 const struct i965_surface *src_surface,
1446 const VARectangle *src_rect,
1447 struct i965_surface *dst_surface,
1448 const VARectangle *dst_rect,
1451 /* private function & data */
1452 pp_context->pp_x_steps = pp_null_x_steps;
1453 pp_context->pp_y_steps = pp_null_y_steps;
1454 pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1456 dst_surface->flags = src_surface->flags;
1458 return VA_STATUS_SUCCESS;
1462 pp_load_save_x_steps(void *private_context)
1468 pp_load_save_y_steps(void *private_context)
1470 struct pp_load_save_context *pp_load_save_context = private_context;
1472 return pp_load_save_context->dest_h / 8;
1476 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1478 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1480 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1481 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1482 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1483 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1489 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1490 const struct i965_surface *src_surface,
1491 const VARectangle *src_rect,
1492 struct i965_surface *dst_surface,
1493 const VARectangle *dst_rect,
1496 struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1497 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1498 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1499 int width[3], height[3], pitch[3], offset[3];
1502 /* source surface */
1503 pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1504 width, height, pitch, offset);
1506 /* destination surface */
1507 pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1508 width, height, pitch, offset);
1510 /* private function & data */
1511 pp_context->pp_x_steps = pp_load_save_x_steps;
1512 pp_context->pp_y_steps = pp_load_save_y_steps;
1513 pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1514 pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1515 pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1517 pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16; /* 1 x N */
1518 pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1520 pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1521 pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1523 dst_surface->flags = src_surface->flags;
1525 return VA_STATUS_SUCCESS;
1529 pp_scaling_x_steps(void *private_context)
1535 pp_scaling_y_steps(void *private_context)
1537 struct pp_scaling_context *pp_scaling_context = private_context;
1539 return pp_scaling_context->dest_h / 8;
1543 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1545 struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1546 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1547 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1548 float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1549 float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1551 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1552 pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1553 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1554 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1560 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1561 const struct i965_surface *src_surface,
1562 const VARectangle *src_rect,
1563 struct i965_surface *dst_surface,
1564 const VARectangle *dst_rect,
1567 struct i965_driver_data *i965 = i965_driver_data(ctx);
1568 struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1569 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1570 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1571 struct object_surface *obj_surface;
1572 struct i965_sampler_state *sampler_state;
1573 int in_w, in_h, in_wpitch, in_hpitch;
1574 int out_w, out_h, out_wpitch, out_hpitch;
1576 /* source surface */
1577 obj_surface = SURFACE(src_surface->id);
1578 in_w = obj_surface->orig_width;
1579 in_h = obj_surface->orig_height;
1580 in_wpitch = obj_surface->width;
1581 in_hpitch = obj_surface->height;
1583 /* source Y surface index 1 */
1584 i965_pp_set_surface_state(ctx, pp_context,
1586 in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1589 /* source UV surface index 2 */
1590 i965_pp_set_surface_state(ctx, pp_context,
1591 obj_surface->bo, in_wpitch * in_hpitch,
1592 in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1595 /* destination surface */
1596 obj_surface = SURFACE(dst_surface->id);
1597 out_w = obj_surface->orig_width;
1598 out_h = obj_surface->orig_height;
1599 out_wpitch = obj_surface->width;
1600 out_hpitch = obj_surface->height;
1602 /* destination Y surface index 7 */
1603 i965_pp_set_surface_state(ctx, pp_context,
1605 out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1608 /* destination UV surface index 8 */
1609 i965_pp_set_surface_state(ctx, pp_context,
1610 obj_surface->bo, out_wpitch * out_hpitch,
1611 out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1615 dri_bo_map(pp_context->sampler_state_table.bo, True);
1616 assert(pp_context->sampler_state_table.bo->virtual);
1617 sampler_state = pp_context->sampler_state_table.bo->virtual;
1619 /* SIMD16 Y index 1 */
1620 sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1621 sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1622 sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1623 sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1624 sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1626 /* SIMD16 UV index 2 */
1627 sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1628 sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1629 sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1630 sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1631 sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1633 dri_bo_unmap(pp_context->sampler_state_table.bo);
1635 /* private function & data */
1636 pp_context->pp_x_steps = pp_scaling_x_steps;
1637 pp_context->pp_y_steps = pp_scaling_y_steps;
1638 pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1640 pp_scaling_context->dest_x = dst_rect->x;
1641 pp_scaling_context->dest_y = dst_rect->y;
1642 pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1643 pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1644 pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1645 pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1647 pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1649 pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1650 pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16; /* 1 x N */
1651 pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1652 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1653 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1655 dst_surface->flags = src_surface->flags;
1657 return VA_STATUS_SUCCESS;
1661 pp_avs_x_steps(void *private_context)
1663 struct pp_avs_context *pp_avs_context = private_context;
1665 return pp_avs_context->dest_w / 16;
1669 pp_avs_y_steps(void *private_context)
1675 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1677 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1678 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1679 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1680 float src_x_steping, src_y_steping, video_step_delta;
1681 int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1683 if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1684 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1685 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1686 } else if (tmp_w >= pp_avs_context->dest_w) {
1687 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1688 pp_inline_parameter->grf6.video_step_delta = 0;
1691 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1692 pp_avs_context->src_normalized_x;
1694 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1695 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1696 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1697 16 * 15 * video_step_delta / 2;
1700 int n0, n1, n2, nls_left, nls_right;
1701 int factor_a = 5, factor_b = 4;
1704 n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1705 n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1706 n2 = tmp_w / (16 * factor_a);
1708 nls_right = n1 + n2;
1709 f = (float) n2 * 16 / tmp_w;
1712 pp_inline_parameter->grf6.video_step_delta = 0.0;
1715 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1716 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1718 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1719 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1720 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1721 16 * 15 * video_step_delta / 2;
1725 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1726 float a = f / (nls_left * 16 * factor_b);
1727 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1729 pp_inline_parameter->grf6.video_step_delta = b;
1732 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1733 pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1735 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1736 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1737 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1738 16 * 15 * video_step_delta / 2;
1739 pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1741 } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1742 /* scale the center linearly */
1743 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1744 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1745 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1746 16 * 15 * video_step_delta / 2;
1747 pp_inline_parameter->grf6.video_step_delta = 0.0;
1748 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1750 float a = f / (nls_right * 16 * factor_b);
1751 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1753 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1754 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1755 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1756 16 * 15 * video_step_delta / 2;
1757 pp_inline_parameter->grf6.video_step_delta = -b;
1759 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1760 pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16 - 1) * b;
1762 pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1767 src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1768 pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1769 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1770 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1776 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1777 const struct i965_surface *src_surface,
1778 const VARectangle *src_rect,
1779 struct i965_surface *dst_surface,
1780 const VARectangle *dst_rect,
1784 struct i965_driver_data *i965 = i965_driver_data(ctx);
1785 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1786 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1787 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1788 struct object_surface *obj_surface;
1789 struct i965_sampler_8x8 *sampler_8x8;
1790 struct i965_sampler_8x8_state *sampler_8x8_state;
1792 int in_w, in_h, in_wpitch, in_hpitch;
1793 int out_w, out_h, out_wpitch, out_hpitch;
1797 obj_surface = SURFACE(src_surface->id);
1798 in_w = obj_surface->orig_width;
1799 in_h = obj_surface->orig_height;
1800 in_wpitch = obj_surface->width;
1801 in_hpitch = obj_surface->height;
1803 /* source Y surface index 1 */
1804 i965_pp_set_surface2_state(ctx, pp_context,
1806 in_w, in_h, in_wpitch,
1808 SURFACE_FORMAT_Y8_UNORM, 0,
1811 /* source UV surface index 2 */
1812 i965_pp_set_surface2_state(ctx, pp_context,
1813 obj_surface->bo, in_wpitch * in_hpitch,
1814 in_w / 2, in_h / 2, in_wpitch,
1816 SURFACE_FORMAT_R8B8_UNORM, 0,
1819 /* destination surface */
1820 obj_surface = SURFACE(dst_surface->id);
1821 out_w = obj_surface->orig_width;
1822 out_h = obj_surface->orig_height;
1823 out_wpitch = obj_surface->width;
1824 out_hpitch = obj_surface->height;
1825 assert(out_w <= out_wpitch && out_h <= out_hpitch);
1827 /* destination Y surface index 7 */
1828 i965_pp_set_surface_state(ctx, pp_context,
1830 out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1833 /* destination UV surface index 8 */
1834 i965_pp_set_surface_state(ctx, pp_context,
1835 obj_surface->bo, out_wpitch * out_hpitch,
1836 out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1839 /* sampler 8x8 state */
1840 dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1841 assert(pp_context->sampler_state_table.bo_8x8->virtual);
1842 assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1843 sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1844 memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1846 for (i = 0; i < 17; i++) {
1847 /* for Y channel, currently ignore */
1848 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1849 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1850 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1851 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1852 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1853 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1854 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1855 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1856 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1857 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1858 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1859 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1860 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1861 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1862 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1863 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1864 /* for U/V channel, 0.25 */
1865 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1866 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1867 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1868 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1869 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1870 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1871 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1872 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1873 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1874 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1875 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1876 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1877 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1878 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1879 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1880 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1883 sampler_8x8_state->dw136.default_sharpness_level = 0;
1884 sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1885 sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1886 sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1887 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1890 dri_bo_map(pp_context->sampler_state_table.bo, True);
1891 assert(pp_context->sampler_state_table.bo->virtual);
1892 assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1893 sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1895 /* sample_8x8 Y index 1 */
1897 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1898 sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1899 sampler_8x8[index].dw0.ief_bypass = 1;
1900 sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1901 sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1902 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1903 sampler_8x8[index].dw2.global_noise_estimation = 22;
1904 sampler_8x8[index].dw2.strong_edge_threshold = 8;
1905 sampler_8x8[index].dw2.weak_edge_threshold = 1;
1906 sampler_8x8[index].dw3.strong_edge_weight = 7;
1907 sampler_8x8[index].dw3.regular_weight = 2;
1908 sampler_8x8[index].dw3.non_edge_weight = 0;
1909 sampler_8x8[index].dw3.gain_factor = 40;
1910 sampler_8x8[index].dw4.steepness_boost = 0;
1911 sampler_8x8[index].dw4.steepness_threshold = 0;
1912 sampler_8x8[index].dw4.mr_boost = 0;
1913 sampler_8x8[index].dw4.mr_threshold = 5;
1914 sampler_8x8[index].dw5.pwl1_point_1 = 4;
1915 sampler_8x8[index].dw5.pwl1_point_2 = 12;
1916 sampler_8x8[index].dw5.pwl1_point_3 = 16;
1917 sampler_8x8[index].dw5.pwl1_point_4 = 26;
1918 sampler_8x8[index].dw6.pwl1_point_5 = 40;
1919 sampler_8x8[index].dw6.pwl1_point_6 = 160;
1920 sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1921 sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1922 sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1923 sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1924 sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1925 sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1926 sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1927 sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1928 sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1929 sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1930 sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1931 sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1932 sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1933 sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1934 sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1935 sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1936 sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1937 sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1938 sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1939 sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1940 sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1941 sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1942 sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1943 sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1944 sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1945 sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1946 sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1947 sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1948 sampler_8x8[index].dw13.limiter_boost = 0;
1949 sampler_8x8[index].dw13.minimum_limiter = 10;
1950 sampler_8x8[index].dw13.maximum_limiter = 11;
1951 sampler_8x8[index].dw14.clip_limiter = 130;
1952 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1953 I915_GEM_DOMAIN_RENDER,
1956 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1957 pp_context->sampler_state_table.bo_8x8);
1959 /* sample_8x8 UV index 2 */
1961 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1962 sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1963 sampler_8x8[index].dw0.ief_bypass = 1;
1964 sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1965 sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1966 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1967 sampler_8x8[index].dw2.global_noise_estimation = 22;
1968 sampler_8x8[index].dw2.strong_edge_threshold = 8;
1969 sampler_8x8[index].dw2.weak_edge_threshold = 1;
1970 sampler_8x8[index].dw3.strong_edge_weight = 7;
1971 sampler_8x8[index].dw3.regular_weight = 2;
1972 sampler_8x8[index].dw3.non_edge_weight = 0;
1973 sampler_8x8[index].dw3.gain_factor = 40;
1974 sampler_8x8[index].dw4.steepness_boost = 0;
1975 sampler_8x8[index].dw4.steepness_threshold = 0;
1976 sampler_8x8[index].dw4.mr_boost = 0;
1977 sampler_8x8[index].dw4.mr_threshold = 5;
1978 sampler_8x8[index].dw5.pwl1_point_1 = 4;
1979 sampler_8x8[index].dw5.pwl1_point_2 = 12;
1980 sampler_8x8[index].dw5.pwl1_point_3 = 16;
1981 sampler_8x8[index].dw5.pwl1_point_4 = 26;
1982 sampler_8x8[index].dw6.pwl1_point_5 = 40;
1983 sampler_8x8[index].dw6.pwl1_point_6 = 160;
1984 sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1985 sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1986 sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1987 sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1988 sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1989 sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1990 sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1991 sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1992 sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1993 sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1994 sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1995 sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1996 sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1997 sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1998 sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1999 sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2000 sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2001 sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2002 sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2003 sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2004 sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2005 sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2006 sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2007 sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2008 sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2009 sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2010 sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2011 sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2012 sampler_8x8[index].dw13.limiter_boost = 0;
2013 sampler_8x8[index].dw13.minimum_limiter = 10;
2014 sampler_8x8[index].dw13.maximum_limiter = 11;
2015 sampler_8x8[index].dw14.clip_limiter = 130;
2016 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2017 I915_GEM_DOMAIN_RENDER,
2020 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2021 pp_context->sampler_state_table.bo_8x8);
2023 dri_bo_unmap(pp_context->sampler_state_table.bo);
2025 /* private function & data */
2026 pp_context->pp_x_steps = pp_avs_x_steps;
2027 pp_context->pp_y_steps = pp_avs_y_steps;
2028 pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2030 pp_avs_context->dest_x = dst_rect->x;
2031 pp_avs_context->dest_y = dst_rect->y;
2032 pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2033 pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2034 pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2035 pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2036 pp_avs_context->src_w = src_rect->width;
2037 pp_avs_context->src_h = src_rect->height;
2039 pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2040 pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2042 pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2043 pp_inline_parameter->grf5.block_count_x = 1; /* M x 1 */
2044 pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2045 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2046 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2047 pp_inline_parameter->grf6.video_step_delta = 0.0;
2049 dst_surface->flags = src_surface->flags;
2051 return VA_STATUS_SUCCESS;
2055 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2056 const struct i965_surface *src_surface,
2057 const VARectangle *src_rect,
2058 struct i965_surface *dst_surface,
2059 const VARectangle *dst_rect,
2062 return pp_nv12_avs_initialize(ctx, pp_context,
2072 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2073 const struct i965_surface *src_surface,
2074 const VARectangle *src_rect,
2075 struct i965_surface *dst_surface,
2076 const VARectangle *dst_rect,
2079 return pp_nv12_avs_initialize(ctx, pp_context,
2089 gen7_pp_avs_x_steps(void *private_context)
2091 struct pp_avs_context *pp_avs_context = private_context;
2093 return pp_avs_context->dest_w / 16;
2097 gen7_pp_avs_y_steps(void *private_context)
2099 struct pp_avs_context *pp_avs_context = private_context;
2101 return pp_avs_context->dest_h / 16;
2105 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2107 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2108 struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2110 pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2111 pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2112 pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2113 pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2119 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2120 const struct i965_surface *src_surface,
2121 const VARectangle *src_rect,
2122 struct i965_surface *dst_surface,
2123 const VARectangle *dst_rect,
2126 struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2127 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2128 struct gen7_sampler_8x8 *sampler_8x8;
2129 struct i965_sampler_8x8_state *sampler_8x8_state;
2131 int width[3], height[3], pitch[3], offset[3];
2133 /* source surface */
2134 gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2135 width, height, pitch, offset);
2137 /* destination surface */
2138 gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2139 width, height, pitch, offset);
2141 /* sampler 8x8 state */
2142 dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2143 assert(pp_context->sampler_state_table.bo_8x8->virtual);
2144 assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2145 sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2146 memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2148 for (i = 0; i < 17; i++) {
2149 /* for Y channel, currently ignore */
2150 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2151 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2152 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2153 sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2154 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2155 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2156 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2157 sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2158 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2159 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2160 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2161 sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2162 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2163 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2164 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2165 sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2166 /* for U/V channel, 0.25 */
2167 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2168 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2169 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2170 sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2171 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2172 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2173 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2174 sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2175 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2176 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2177 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2178 sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2179 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2180 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2181 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2182 sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2185 sampler_8x8_state->dw136.default_sharpness_level = 0;
2186 sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2187 sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2188 sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2189 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2192 dri_bo_map(pp_context->sampler_state_table.bo, True);
2193 assert(pp_context->sampler_state_table.bo->virtual);
2194 assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2195 sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2197 /* sample_8x8 Y index 4 */
2199 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2200 sampler_8x8[index].dw0.global_noise_estimation = 255;
2201 sampler_8x8[index].dw0.ief_bypass = 1;
2203 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2205 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2206 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2207 sampler_8x8[index].dw2.r5x_coefficient = 9;
2208 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2209 sampler_8x8[index].dw2.r5c_coefficient = 3;
2211 sampler_8x8[index].dw3.r3x_coefficient = 27;
2212 sampler_8x8[index].dw3.r3c_coefficient = 5;
2213 sampler_8x8[index].dw3.gain_factor = 40;
2214 sampler_8x8[index].dw3.non_edge_weight = 1;
2215 sampler_8x8[index].dw3.regular_weight = 2;
2216 sampler_8x8[index].dw3.strong_edge_weight = 7;
2217 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2219 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2220 I915_GEM_DOMAIN_RENDER,
2223 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2224 pp_context->sampler_state_table.bo_8x8);
2226 /* sample_8x8 UV index 8 */
2228 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2229 sampler_8x8[index].dw0.disable_8x8_filter = 0;
2230 sampler_8x8[index].dw0.global_noise_estimation = 255;
2231 sampler_8x8[index].dw0.ief_bypass = 1;
2232 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2233 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2234 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2235 sampler_8x8[index].dw2.r5x_coefficient = 9;
2236 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2237 sampler_8x8[index].dw2.r5c_coefficient = 3;
2238 sampler_8x8[index].dw3.r3x_coefficient = 27;
2239 sampler_8x8[index].dw3.r3c_coefficient = 5;
2240 sampler_8x8[index].dw3.gain_factor = 40;
2241 sampler_8x8[index].dw3.non_edge_weight = 1;
2242 sampler_8x8[index].dw3.regular_weight = 2;
2243 sampler_8x8[index].dw3.strong_edge_weight = 7;
2244 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2246 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2247 I915_GEM_DOMAIN_RENDER,
2250 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2251 pp_context->sampler_state_table.bo_8x8);
2253 /* sampler_8x8 V, index 12 */
2255 memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2256 sampler_8x8[index].dw0.disable_8x8_filter = 0;
2257 sampler_8x8[index].dw0.global_noise_estimation = 255;
2258 sampler_8x8[index].dw0.ief_bypass = 1;
2259 sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2260 sampler_8x8[index].dw2.weak_edge_threshold = 1;
2261 sampler_8x8[index].dw2.strong_edge_threshold = 8;
2262 sampler_8x8[index].dw2.r5x_coefficient = 9;
2263 sampler_8x8[index].dw2.r5cx_coefficient = 8;
2264 sampler_8x8[index].dw2.r5c_coefficient = 3;
2265 sampler_8x8[index].dw3.r3x_coefficient = 27;
2266 sampler_8x8[index].dw3.r3c_coefficient = 5;
2267 sampler_8x8[index].dw3.gain_factor = 40;
2268 sampler_8x8[index].dw3.non_edge_weight = 1;
2269 sampler_8x8[index].dw3.regular_weight = 2;
2270 sampler_8x8[index].dw3.strong_edge_weight = 7;
2271 sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2273 dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2274 I915_GEM_DOMAIN_RENDER,
2277 sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2278 pp_context->sampler_state_table.bo_8x8);
2280 dri_bo_unmap(pp_context->sampler_state_table.bo);
2282 /* private function & data */
2283 pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2284 pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2285 pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2287 pp_avs_context->dest_x = dst_rect->x;
2288 pp_avs_context->dest_y = dst_rect->y;
2289 pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2290 pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2291 pp_avs_context->src_w = src_rect->width;
2292 pp_avs_context->src_h = src_rect->height;
2294 int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2295 dw = MAX(dw, pp_avs_context->dest_w);
2297 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2298 pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2299 pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2300 pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2301 pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2303 dst_surface->flags = src_surface->flags;
2305 return VA_STATUS_SUCCESS;
2309 pp_dndi_x_steps(void *private_context)
2315 pp_dndi_y_steps(void *private_context)
2317 struct pp_dndi_context *pp_dndi_context = private_context;
2319 return pp_dndi_context->dest_h / 4;
2323 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2325 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2327 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2328 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2334 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2335 const struct i965_surface *src_surface,
2336 const VARectangle *src_rect,
2337 struct i965_surface *dst_surface,
2338 const VARectangle *dst_rect,
2341 struct i965_driver_data *i965 = i965_driver_data(ctx);
2342 struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2343 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2344 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2345 struct object_surface *obj_surface;
2346 struct i965_sampler_dndi *sampler_dndi;
2350 int dndi_top_first = 1;
2352 if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2353 return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2355 if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2361 obj_surface = SURFACE(src_surface->id);
2362 orig_w = obj_surface->orig_width;
2363 orig_h = obj_surface->orig_height;
2364 w = obj_surface->width;
2365 h = obj_surface->height;
2367 if (pp_context->stmm.bo == NULL) {
2368 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2372 assert(pp_context->stmm.bo);
2375 /* source UV surface index 2 */
2376 i965_pp_set_surface_state(ctx, pp_context,
2377 obj_surface->bo, w * h,
2378 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2381 /* source YUV surface index 4 */
2382 i965_pp_set_surface2_state(ctx, pp_context,
2386 SURFACE_FORMAT_PLANAR_420_8, 1,
2389 /* source STMM surface index 20 */
2390 i965_pp_set_surface_state(ctx, pp_context,
2391 pp_context->stmm.bo, 0,
2392 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2395 /* destination surface */
2396 obj_surface = SURFACE(dst_surface->id);
2397 orig_w = obj_surface->orig_width;
2398 orig_h = obj_surface->orig_height;
2399 w = obj_surface->width;
2400 h = obj_surface->height;
2402 /* destination Y surface index 7 */
2403 i965_pp_set_surface_state(ctx, pp_context,
2405 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2408 /* destination UV surface index 8 */
2409 i965_pp_set_surface_state(ctx, pp_context,
2410 obj_surface->bo, w * h,
2411 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2414 dri_bo_map(pp_context->sampler_state_table.bo, True);
2415 assert(pp_context->sampler_state_table.bo->virtual);
2416 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2417 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2419 /* sample dndi index 1 */
2421 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2422 sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8
2423 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2424 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2426 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2427 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2428 sampler_dndi[index].dw1.stmm_c2 = 1;
2429 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2430 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2432 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15; // 0-31
2433 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15
2434 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15
2435 sampler_dndi[index].dw2.good_neighbor_threshold = 4; // 0-63
2437 sampler_dndi[index].dw3.maximum_stmm = 128;
2438 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2439 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2440 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2441 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2443 sampler_dndi[index].dw4.sdi_delta = 8;
2444 sampler_dndi[index].dw4.sdi_threshold = 128;
2445 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2446 sampler_dndi[index].dw4.stmm_shift_up = 0;
2447 sampler_dndi[index].dw4.stmm_shift_down = 0;
2448 sampler_dndi[index].dw4.minimum_stmm = 0;
2450 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2451 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2452 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2453 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2455 sampler_dndi[index].dw6.dn_enable = 1;
2456 sampler_dndi[index].dw6.di_enable = 1;
2457 sampler_dndi[index].dw6.di_partial = 0;
2458 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2459 sampler_dndi[index].dw6.dndi_stream_id = 0;
2460 sampler_dndi[index].dw6.dndi_first_frame = 1;
2461 sampler_dndi[index].dw6.progressive_dn = 0;
2462 sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2463 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2464 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2466 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2467 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2468 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2469 sampler_dndi[index].dw7.column_width_minus1 = 0;
2471 dri_bo_unmap(pp_context->sampler_state_table.bo);
2473 /* private function & data */
2474 pp_context->pp_x_steps = pp_dndi_x_steps;
2475 pp_context->pp_y_steps = pp_dndi_y_steps;
2476 pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2478 pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2479 pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2480 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2481 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2483 pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */
2484 pp_inline_parameter->grf5.number_blocks = w / 16;
2485 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2486 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2488 pp_dndi_context->dest_w = w;
2489 pp_dndi_context->dest_h = h;
2491 dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2493 return VA_STATUS_SUCCESS;
2497 pp_dn_x_steps(void *private_context)
2503 pp_dn_y_steps(void *private_context)
2505 struct pp_dn_context *pp_dn_context = private_context;
2507 return pp_dn_context->dest_h / 8;
2511 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2513 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2515 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2516 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2522 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2523 const struct i965_surface *src_surface,
2524 const VARectangle *src_rect,
2525 struct i965_surface *dst_surface,
2526 const VARectangle *dst_rect,
2529 struct i965_driver_data *i965 = i965_driver_data(ctx);
2530 struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2531 struct object_surface *obj_surface;
2532 struct i965_sampler_dndi *sampler_dndi;
2533 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2534 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2535 VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2539 int dn_strength = 15;
2540 int dndi_top_first = 1;
2541 int dn_progressive = 0;
2543 if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2546 } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2554 if (dn_filter_param) {
2555 float value = dn_filter_param->value;
2563 dn_strength = (int)(value * 31.0F);
2567 obj_surface = SURFACE(src_surface->id);
2568 orig_w = obj_surface->orig_width;
2569 orig_h = obj_surface->orig_height;
2570 w = obj_surface->width;
2571 h = obj_surface->height;
2573 if (pp_context->stmm.bo == NULL) {
2574 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2578 assert(pp_context->stmm.bo);
2581 /* source UV surface index 2 */
2582 i965_pp_set_surface_state(ctx, pp_context,
2583 obj_surface->bo, w * h,
2584 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2587 /* source YUV surface index 4 */
2588 i965_pp_set_surface2_state(ctx, pp_context,
2592 SURFACE_FORMAT_PLANAR_420_8, 1,
2595 /* source STMM surface index 20 */
2596 i965_pp_set_surface_state(ctx, pp_context,
2597 pp_context->stmm.bo, 0,
2598 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2601 /* destination surface */
2602 obj_surface = SURFACE(dst_surface->id);
2603 orig_w = obj_surface->orig_width;
2604 orig_h = obj_surface->orig_height;
2605 w = obj_surface->width;
2606 h = obj_surface->height;
2608 /* destination Y surface index 7 */
2609 i965_pp_set_surface_state(ctx, pp_context,
2611 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2614 /* destination UV surface index 8 */
2615 i965_pp_set_surface_state(ctx, pp_context,
2616 obj_surface->bo, w * h,
2617 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2620 dri_bo_map(pp_context->sampler_state_table.bo, True);
2621 assert(pp_context->sampler_state_table.bo->virtual);
2622 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2623 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2625 /* sample dndi index 1 */
2627 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2628 sampler_dndi[index].dw0.denoise_history_delta = 8; // 0-15, default is 8
2629 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2630 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2632 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2633 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2634 sampler_dndi[index].dw1.stmm_c2 = 0;
2635 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2636 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2638 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31
2639 sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7; // 0-15
2640 sampler_dndi[index].dw2.denoise_edge_threshold = 7; // 0-15
2641 sampler_dndi[index].dw2.good_neighbor_threshold = 7; // 0-63
2643 sampler_dndi[index].dw3.maximum_stmm = 128;
2644 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2645 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2646 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2647 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2649 sampler_dndi[index].dw4.sdi_delta = 8;
2650 sampler_dndi[index].dw4.sdi_threshold = 128;
2651 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2652 sampler_dndi[index].dw4.stmm_shift_up = 0;
2653 sampler_dndi[index].dw4.stmm_shift_down = 0;
2654 sampler_dndi[index].dw4.minimum_stmm = 0;
2656 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2657 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2658 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2659 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2661 sampler_dndi[index].dw6.dn_enable = 1;
2662 sampler_dndi[index].dw6.di_enable = 0;
2663 sampler_dndi[index].dw6.di_partial = 0;
2664 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2665 sampler_dndi[index].dw6.dndi_stream_id = 1;
2666 sampler_dndi[index].dw6.dndi_first_frame = 1;
2667 sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2668 sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2669 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2670 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2672 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2673 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2674 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2675 sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2677 dri_bo_unmap(pp_context->sampler_state_table.bo);
2679 /* private function & data */
2680 pp_context->pp_x_steps = pp_dn_x_steps;
2681 pp_context->pp_y_steps = pp_dn_y_steps;
2682 pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2684 pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2685 pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2686 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2687 pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2689 pp_inline_parameter->grf5.block_count_x = w / 16; /* 1 x N */
2690 pp_inline_parameter->grf5.number_blocks = w / 16;
2691 pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2692 pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2694 pp_dn_context->dest_w = w;
2695 pp_dn_context->dest_h = h;
2697 dst_surface->flags = src_surface->flags;
2699 return VA_STATUS_SUCCESS;
2703 gen7_pp_dndi_x_steps(void *private_context)
2705 struct pp_dndi_context *pp_dndi_context = private_context;
2707 return pp_dndi_context->dest_w / 16;
2711 gen7_pp_dndi_y_steps(void *private_context)
2713 struct pp_dndi_context *pp_dndi_context = private_context;
2715 return pp_dndi_context->dest_h / 4;
2719 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2721 struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2723 pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2724 pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2730 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2731 const struct i965_surface *src_surface,
2732 const VARectangle *src_rect,
2733 struct i965_surface *dst_surface,
2734 const VARectangle *dst_rect,
2737 struct i965_driver_data *i965 = i965_driver_data(ctx);
2738 struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2739 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2740 struct object_surface *obj_surface;
2741 struct gen7_sampler_dndi *sampler_dndi;
2745 int dndi_top_first = 1;
2747 if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2748 return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2750 if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2756 obj_surface = SURFACE(src_surface->id);
2757 orig_w = obj_surface->orig_width;
2758 orig_h = obj_surface->orig_height;
2759 w = obj_surface->width;
2760 h = obj_surface->height;
2762 if (pp_context->stmm.bo == NULL) {
2763 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2767 assert(pp_context->stmm.bo);
2770 /* source UV surface index 1 */
2771 gen7_pp_set_surface_state(ctx, pp_context,
2772 obj_surface->bo, w * h,
2773 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2776 /* source YUV surface index 3 */
2777 gen7_pp_set_surface2_state(ctx, pp_context,
2781 SURFACE_FORMAT_PLANAR_420_8, 1,
2784 /* source (temporal reference) YUV surface index 4 */
2785 gen7_pp_set_surface2_state(ctx, pp_context,
2789 SURFACE_FORMAT_PLANAR_420_8, 1,
2792 /* STMM / History Statistics input surface, index 5 */
2793 gen7_pp_set_surface_state(ctx, pp_context,
2794 pp_context->stmm.bo, 0,
2795 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2798 /* destination surface */
2799 obj_surface = SURFACE(dst_surface->id);
2800 orig_w = obj_surface->orig_width;
2801 orig_h = obj_surface->orig_height;
2802 w = obj_surface->width;
2803 h = obj_surface->height;
2805 /* destination(Previous frame) Y surface index 27 */
2806 gen7_pp_set_surface_state(ctx, pp_context,
2808 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2811 /* destination(Previous frame) UV surface index 28 */
2812 gen7_pp_set_surface_state(ctx, pp_context,
2813 obj_surface->bo, w * h,
2814 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2817 /* destination(Current frame) Y surface index 30 */
2818 gen7_pp_set_surface_state(ctx, pp_context,
2820 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2823 /* destination(Current frame) UV surface index 31 */
2824 gen7_pp_set_surface_state(ctx, pp_context,
2825 obj_surface->bo, w * h,
2826 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2829 /* STMM output surface, index 33 */
2830 gen7_pp_set_surface_state(ctx, pp_context,
2831 pp_context->stmm.bo, 0,
2832 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2837 dri_bo_map(pp_context->sampler_state_table.bo, True);
2838 assert(pp_context->sampler_state_table.bo->virtual);
2839 assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2840 sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2842 /* sample dndi index 0 */
2844 sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2845 sampler_dndi[index].dw0.dnmh_delt = 8;
2846 sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2847 sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2848 sampler_dndi[index].dw0.denoise_maximum_history = 128; // 128-240
2849 sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2851 sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2852 sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2853 sampler_dndi[index].dw1.stmm_c2 = 0;
2854 sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2855 sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2857 sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15; // 0-31
2858 sampler_dndi[index].dw2.bne_edge_th = 1;
2859 sampler_dndi[index].dw2.smooth_mv_th = 0;
2860 sampler_dndi[index].dw2.sad_tight_th = 5;
2861 sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2862 sampler_dndi[index].dw2.good_neighbor_th = 4;
2864 sampler_dndi[index].dw3.maximum_stmm = 128;
2865 sampler_dndi[index].dw3.multipler_for_vecm = 2;
2866 sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2867 sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2868 sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2870 sampler_dndi[index].dw4.sdi_delta = 8;
2871 sampler_dndi[index].dw4.sdi_threshold = 128;
2872 sampler_dndi[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
2873 sampler_dndi[index].dw4.stmm_shift_up = 0;
2874 sampler_dndi[index].dw4.stmm_shift_down = 0;
2875 sampler_dndi[index].dw4.minimum_stmm = 0;
2877 sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2878 sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2879 sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2880 sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2882 sampler_dndi[index].dw6.dn_enable = 0;
2883 sampler_dndi[index].dw6.di_enable = 1;
2884 sampler_dndi[index].dw6.di_partial = 0;
2885 sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2886 sampler_dndi[index].dw6.dndi_stream_id = 1;
2887 sampler_dndi[index].dw6.dndi_first_frame = 1;
2888 sampler_dndi[index].dw6.progressive_dn = 0;
2889 sampler_dndi[index].dw6.mcdi_enable = 0;
2890 sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2891 sampler_dndi[index].dw6.cat_th1 = 0;
2892 sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2893 sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2895 sampler_dndi[index].dw7.sad_tha = 5;
2896 sampler_dndi[index].dw7.sad_thb = 10;
2897 sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2898 sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2899 sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2900 sampler_dndi[index].dw7.vdi_walker_enable = 0;
2901 sampler_dndi[index].dw7.neighborpixel_th = 10;
2902 sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2904 dri_bo_unmap(pp_context->sampler_state_table.bo);
2906 /* private function & data */
2907 pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2908 pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2909 pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2911 pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2912 pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2913 pp_static_parameter->grf1.di_top_field_first = 0;
2914 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2916 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2917 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2918 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2920 pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2921 pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2923 pp_dndi_context->dest_w = w;
2924 pp_dndi_context->dest_h = h;
2926 dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2928 return VA_STATUS_SUCCESS;
2932 gen7_pp_dn_x_steps(void *private_context)
2938 gen7_pp_dn_y_steps(void *private_context)
2940 struct pp_dn_context *pp_dn_context = private_context;
2942 return pp_dn_context->dest_h / 4;
2946 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2948 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2950 pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2951 pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2957 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2958 const struct i965_surface *src_surface,
2959 const VARectangle *src_rect,
2960 struct i965_surface *dst_surface,
2961 const VARectangle *dst_rect,
2964 struct i965_driver_data *i965 = i965_driver_data(ctx);
2965 struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2966 struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2967 struct object_surface *obj_surface;
2968 struct gen7_sampler_dndi *sampler_dn;
2969 VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2973 int dn_strength = 15;
2974 int dndi_top_first = 1;
2975 int dn_progressive = 0;
2977 if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2980 } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2988 if (dn_filter_param) {
2989 float value = dn_filter_param->value;
2997 dn_strength = (int)(value * 31.0F);
3001 obj_surface = SURFACE(src_surface->id);
3002 orig_w = obj_surface->orig_width;
3003 orig_h = obj_surface->orig_height;
3004 w = obj_surface->width;
3005 h = obj_surface->height;
3007 if (pp_context->stmm.bo == NULL) {
3008 pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3012 assert(pp_context->stmm.bo);
3015 /* source UV surface index 1 */
3016 gen7_pp_set_surface_state(ctx, pp_context,
3017 obj_surface->bo, w * h,
3018 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3021 /* source YUV surface index 3 */
3022 gen7_pp_set_surface2_state(ctx, pp_context,
3026 SURFACE_FORMAT_PLANAR_420_8, 1,
3029 /* source STMM surface index 5 */
3030 gen7_pp_set_surface_state(ctx, pp_context,
3031 pp_context->stmm.bo, 0,
3032 orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3035 /* destination surface */
3036 obj_surface = SURFACE(dst_surface->id);
3037 orig_w = obj_surface->orig_width;
3038 orig_h = obj_surface->orig_height;
3039 w = obj_surface->width;
3040 h = obj_surface->height;
3042 /* destination Y surface index 7 */
3043 gen7_pp_set_surface_state(ctx, pp_context,
3045 orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3048 /* destination UV surface index 8 */
3049 gen7_pp_set_surface_state(ctx, pp_context,
3050 obj_surface->bo, w * h,
3051 orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3054 dri_bo_map(pp_context->sampler_state_table.bo, True);
3055 assert(pp_context->sampler_state_table.bo->virtual);
3056 assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3057 sampler_dn = pp_context->sampler_state_table.bo->virtual;
3059 /* sample dn index 1 */
3061 sampler_dn[index].dw0.denoise_asd_threshold = 0;
3062 sampler_dn[index].dw0.dnmh_delt = 8;
3063 sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3064 sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3065 sampler_dn[index].dw0.denoise_maximum_history = 128; // 128-240
3066 sampler_dn[index].dw0.denoise_stad_threshold = 0;
3068 sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3069 sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3070 sampler_dn[index].dw1.stmm_c2 = 0;
3071 sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3072 sampler_dn[index].dw1.temporal_difference_threshold = 16;
3074 sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength; // 0-31
3075 sampler_dn[index].dw2.bne_edge_th = 1;
3076 sampler_dn[index].dw2.smooth_mv_th = 0;
3077 sampler_dn[index].dw2.sad_tight_th = 5;
3078 sampler_dn[index].dw2.cat_slope_minus1 = 9;
3079 sampler_dn[index].dw2.good_neighbor_th = 4;
3081 sampler_dn[index].dw3.maximum_stmm = 128;
3082 sampler_dn[index].dw3.multipler_for_vecm = 2;
3083 sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3084 sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3085 sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3087 sampler_dn[index].dw4.sdi_delta = 8;
3088 sampler_dn[index].dw4.sdi_threshold = 128;
3089 sampler_dn[index].dw4.stmm_output_shift = 7; // stmm_max - stmm_min = 2 ^ stmm_output_shift
3090 sampler_dn[index].dw4.stmm_shift_up = 0;
3091 sampler_dn[index].dw4.stmm_shift_down = 0;
3092 sampler_dn[index].dw4.minimum_stmm = 0;
3094 sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3095 sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3096 sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3097 sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3099 sampler_dn[index].dw6.dn_enable = 1;
3100 sampler_dn[index].dw6.di_enable = 0;
3101 sampler_dn[index].dw6.di_partial = 0;
3102 sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3103 sampler_dn[index].dw6.dndi_stream_id = 1;
3104 sampler_dn[index].dw6.dndi_first_frame = 1;
3105 sampler_dn[index].dw6.progressive_dn = dn_progressive;
3106 sampler_dn[index].dw6.mcdi_enable = 0;
3107 sampler_dn[index].dw6.fmd_tear_threshold = 32;
3108 sampler_dn[index].dw6.cat_th1 = 0;
3109 sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3110 sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3112 sampler_dn[index].dw7.sad_tha = 5;
3113 sampler_dn[index].dw7.sad_thb = 10;
3114 sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3115 sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3116 sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3117 sampler_dn[index].dw7.vdi_walker_enable = 0;
3118 sampler_dn[index].dw7.neighborpixel_th = 10;
3119 sampler_dn[index].dw7.column_width_minus1 = w / 16;
3121 dri_bo_unmap(pp_context->sampler_state_table.bo);
3123 /* private function & data */
3124 pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3125 pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3126 pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3128 pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3129 pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3130 pp_static_parameter->grf1.di_top_field_first = 0;
3131 pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3133 pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3134 pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3135 pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3137 pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3138 pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3140 pp_dn_context->dest_w = w;
3141 pp_dn_context->dest_h = h;
3143 dst_surface->flags = src_surface->flags;
3145 return VA_STATUS_SUCCESS;
3148 // update u/v offset when the surface format are packed yuv
3149 static void i965_update_src_surface_uv_offset(
3150 VADriverContextP ctx,
3151 struct i965_post_processing_context *pp_context,
3152 const struct i965_surface *surface)
3154 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3155 int fourcc = pp_get_surface_fourcc(ctx, surface);
3157 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3158 pp_static_parameter->grf1.source_packed_u_offset = 1;
3159 pp_static_parameter->grf1.source_packed_v_offset = 3;
3161 else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3162 pp_static_parameter->grf1.source_packed_y_offset = 1;
3163 pp_static_parameter->grf1.source_packed_v_offset = 2;
3168 static void i965_update_dst_surface_uv_offset(
3169 VADriverContextP ctx,
3170 struct i965_post_processing_context *pp_context,
3171 const struct i965_surface *surface)
3173 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3174 int fourcc = pp_get_surface_fourcc(ctx, surface);
3176 if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3177 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
3178 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
3180 else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3181 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
3182 pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
3188 ironlake_pp_initialize(
3189 VADriverContextP ctx,
3190 struct i965_post_processing_context *pp_context,
3191 const struct i965_surface *src_surface,
3192 const VARectangle *src_rect,
3193 struct i965_surface *dst_surface,
3194 const VARectangle *dst_rect,
3200 struct i965_driver_data *i965 = i965_driver_data(ctx);
3201 struct pp_module *pp_module;
3203 int static_param_size, inline_param_size;
3205 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3206 bo = dri_bo_alloc(i965->intel.bufmgr,
3207 "surface state & binding table",
3208 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3211 pp_context->surface_state_binding_table.bo = bo;
3213 dri_bo_unreference(pp_context->curbe.bo);
3214 bo = dri_bo_alloc(i965->intel.bufmgr,
3219 pp_context->curbe.bo = bo;
3221 dri_bo_unreference(pp_context->idrt.bo);
3222 bo = dri_bo_alloc(i965->intel.bufmgr,
3223 "interface discriptor",
3224 sizeof(struct i965_interface_descriptor),
3227 pp_context->idrt.bo = bo;
3228 pp_context->idrt.num_interface_descriptors = 0;
3230 dri_bo_unreference(pp_context->sampler_state_table.bo);
3231 bo = dri_bo_alloc(i965->intel.bufmgr,
3232 "sampler state table",
3236 dri_bo_map(bo, True);
3237 memset(bo->virtual, 0, bo->size);
3239 pp_context->sampler_state_table.bo = bo;
3241 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3242 bo = dri_bo_alloc(i965->intel.bufmgr,
3243 "sampler 8x8 state ",
3247 pp_context->sampler_state_table.bo_8x8 = bo;
3249 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3250 bo = dri_bo_alloc(i965->intel.bufmgr,
3251 "sampler 8x8 state ",
3255 pp_context->sampler_state_table.bo_8x8_uv = bo;
3257 dri_bo_unreference(pp_context->vfe_state.bo);
3258 bo = dri_bo_alloc(i965->intel.bufmgr,
3260 sizeof(struct i965_vfe_state),
3263 pp_context->vfe_state.bo = bo;
3265 if (IS_GEN7(i965->intel.device_id)) {
3266 static_param_size = sizeof(struct gen7_pp_static_parameter);
3267 inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3269 static_param_size = sizeof(struct pp_static_parameter);
3270 inline_param_size = sizeof(struct pp_inline_parameter);
3273 memset(pp_context->pp_static_parameter, 0, static_param_size);
3274 memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3276 // update u/v offset for packed yuv
3277 i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3278 i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3280 assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3281 pp_context->current_pp = pp_index;
3282 pp_module = &pp_context->pp_modules[pp_index];
3284 if (pp_module->initialize)
3285 va_status = pp_module->initialize(ctx, pp_context,
3292 va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3298 ironlake_post_processing(
3299 VADriverContextP ctx,
3300 struct i965_post_processing_context *pp_context,
3301 const struct i965_surface *src_surface,
3302 const VARectangle *src_rect,
3303 struct i965_surface *dst_surface,
3304 const VARectangle *dst_rect,
3311 va_status = ironlake_pp_initialize(ctx, pp_context,
3319 if (va_status == VA_STATUS_SUCCESS) {
3320 ironlake_pp_states_setup(ctx, pp_context);
3321 ironlake_pp_pipeline_setup(ctx, pp_context);
3329 VADriverContextP ctx,
3330 struct i965_post_processing_context *pp_context,
3331 const struct i965_surface *src_surface,
3332 const VARectangle *src_rect,
3333 struct i965_surface *dst_surface,
3334 const VARectangle *dst_rect,
3340 struct i965_driver_data *i965 = i965_driver_data(ctx);
3341 struct pp_module *pp_module;
3343 struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3344 struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3346 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3347 bo = dri_bo_alloc(i965->intel.bufmgr,
3348 "surface state & binding table",
3349 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3352 pp_context->surface_state_binding_table.bo = bo;
3354 dri_bo_unreference(pp_context->curbe.bo);
3355 bo = dri_bo_alloc(i965->intel.bufmgr,
3360 pp_context->curbe.bo = bo;
3362 dri_bo_unreference(pp_context->idrt.bo);
3363 bo = dri_bo_alloc(i965->intel.bufmgr,
3364 "interface discriptor",
3365 sizeof(struct gen6_interface_descriptor_data),
3368 pp_context->idrt.bo = bo;
3369 pp_context->idrt.num_interface_descriptors = 0;
3371 dri_bo_unreference(pp_context->sampler_state_table.bo);
3372 bo = dri_bo_alloc(i965->intel.bufmgr,
3373 "sampler state table",
3377 dri_bo_map(bo, True);
3378 memset(bo->virtual, 0, bo->size);
3380 pp_context->sampler_state_table.bo = bo;
3382 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3383 bo = dri_bo_alloc(i965->intel.bufmgr,
3384 "sampler 8x8 state ",
3388 pp_context->sampler_state_table.bo_8x8 = bo;
3390 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3391 bo = dri_bo_alloc(i965->intel.bufmgr,
3392 "sampler 8x8 state ",
3396 pp_context->sampler_state_table.bo_8x8_uv = bo;
3398 dri_bo_unreference(pp_context->vfe_state.bo);
3399 bo = dri_bo_alloc(i965->intel.bufmgr,
3401 sizeof(struct i965_vfe_state),
3404 pp_context->vfe_state.bo = bo;
3406 memset(pp_static_parameter, 0, sizeof(*pp_static_parameter));
3407 memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter));
3409 // update u/v offset for packed yuv
3410 i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3411 i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3413 assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3414 pp_context->current_pp = pp_index;
3415 pp_module = &pp_context->pp_modules[pp_index];
3417 if (pp_module->initialize)
3418 va_status = pp_module->initialize(ctx, pp_context,
3425 va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3431 gen6_pp_interface_descriptor_table(VADriverContextP ctx,
3432 struct i965_post_processing_context *pp_context)
3434 struct i965_driver_data *i965 = i965_driver_data(ctx);
3435 struct gen6_interface_descriptor_data *desc;
3437 int pp_index = pp_context->current_pp;
3439 bo = pp_context->idrt.bo;
3440 dri_bo_map(bo, True);
3441 assert(bo->virtual);
3443 memset(desc, 0, sizeof(*desc));
3444 desc->desc0.kernel_start_pointer =
3445 pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3446 desc->desc1.single_program_flow = 1;
3447 desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3448 desc->desc2.sampler_count = 1; /* 1 - 4 samplers used */
3449 desc->desc2.sampler_state_pointer =
3450 pp_context->sampler_state_table.bo->offset >> 5;
3451 desc->desc3.binding_table_entry_count = 0;
3452 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3453 desc->desc4.constant_urb_entry_read_offset = 0;
3455 if (IS_GEN7(i965->intel.device_id))
3456 desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3458 desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3460 dri_bo_emit_reloc(bo,
3461 I915_GEM_DOMAIN_INSTRUCTION, 0,
3463 offsetof(struct gen6_interface_descriptor_data, desc0),
3464 pp_context->pp_modules[pp_index].kernel.bo);
3466 dri_bo_emit_reloc(bo,
3467 I915_GEM_DOMAIN_INSTRUCTION, 0,
3468 desc->desc2.sampler_count << 2,
3469 offsetof(struct gen6_interface_descriptor_data, desc2),
3470 pp_context->sampler_state_table.bo);
3473 pp_context->idrt.num_interface_descriptors++;
3477 gen6_pp_upload_constants(VADriverContextP ctx,
3478 struct i965_post_processing_context *pp_context)
3480 struct i965_driver_data *i965 = i965_driver_data(ctx);
3481 unsigned char *constant_buffer;
3484 assert(sizeof(struct pp_static_parameter) == 128);
3485 assert(sizeof(struct gen7_pp_static_parameter) == 192);
3487 if (IS_GEN7(i965->intel.device_id))
3488 param_size = sizeof(struct gen7_pp_static_parameter);
3490 param_size = sizeof(struct pp_static_parameter);
3492 dri_bo_map(pp_context->curbe.bo, 1);
3493 assert(pp_context->curbe.bo->virtual);
3494 constant_buffer = pp_context->curbe.bo->virtual;
3495 memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3496 dri_bo_unmap(pp_context->curbe.bo);
3500 gen6_pp_states_setup(VADriverContextP ctx,
3501 struct i965_post_processing_context *pp_context)
3503 gen6_pp_interface_descriptor_table(ctx, pp_context);
3504 gen6_pp_upload_constants(ctx, pp_context);
3508 gen6_pp_pipeline_select(VADriverContextP ctx,
3509 struct i965_post_processing_context *pp_context)
3511 struct intel_batchbuffer *batch = pp_context->batch;
3513 BEGIN_BATCH(batch, 1);
3514 OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3515 ADVANCE_BATCH(batch);
3519 gen6_pp_state_base_address(VADriverContextP ctx,
3520 struct i965_post_processing_context *pp_context)
3522 struct intel_batchbuffer *batch = pp_context->batch;
3524 BEGIN_BATCH(batch, 10);
3525 OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3526 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3527 OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3528 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3529 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3530 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3531 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3532 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3533 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3534 OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3535 ADVANCE_BATCH(batch);
3539 gen6_pp_vfe_state(VADriverContextP ctx,
3540 struct i965_post_processing_context *pp_context)
3542 struct intel_batchbuffer *batch = pp_context->batch;
3544 BEGIN_BATCH(batch, 8);
3545 OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3546 OUT_BATCH(batch, 0);
3548 (pp_context->urb.num_vfe_entries - 1) << 16 |
3549 pp_context->urb.num_vfe_entries << 8);
3550 OUT_BATCH(batch, 0);
3552 (pp_context->urb.size_vfe_entry * 2) << 16 | /* URB Entry Allocation Size, in 256 bits unit */
3553 (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3554 OUT_BATCH(batch, 0);
3555 OUT_BATCH(batch, 0);
3556 OUT_BATCH(batch, 0);
3557 ADVANCE_BATCH(batch);
3561 gen6_pp_curbe_load(VADriverContextP ctx,
3562 struct i965_post_processing_context *pp_context)
3564 struct intel_batchbuffer *batch = pp_context->batch;
3566 assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3568 BEGIN_BATCH(batch, 4);
3569 OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3570 OUT_BATCH(batch, 0);
3572 pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3574 pp_context->curbe.bo,
3575 I915_GEM_DOMAIN_INSTRUCTION, 0,
3577 ADVANCE_BATCH(batch);
3581 gen6_interface_descriptor_load(VADriverContextP ctx,
3582 struct i965_post_processing_context *pp_context)
3584 struct intel_batchbuffer *batch = pp_context->batch;
3586 BEGIN_BATCH(batch, 4);
3587 OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3588 OUT_BATCH(batch, 0);
3590 pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3592 pp_context->idrt.bo,
3593 I915_GEM_DOMAIN_INSTRUCTION, 0,
3595 ADVANCE_BATCH(batch);
3599 gen6_pp_object_walker(VADriverContextP ctx,
3600 struct i965_post_processing_context *pp_context)
3602 struct i965_driver_data *i965 = i965_driver_data(ctx);
3603 struct intel_batchbuffer *batch = pp_context->batch;
3604 int x, x_steps, y, y_steps;
3605 int param_size, command_length_in_dws;
3606 dri_bo *command_buffer;
3607 unsigned int *command_ptr;
3609 if (IS_GEN7(i965->intel.device_id))
3610 param_size = sizeof(struct gen7_pp_inline_parameter);
3612 param_size = sizeof(struct pp_inline_parameter);
3614 x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3615 y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3616 command_length_in_dws = 6 + (param_size >> 2);
3617 command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3618 "command objects buffer",
3619 command_length_in_dws * 4 * x_steps * y_steps + 8,
3622 dri_bo_map(command_buffer, 1);
3623 command_ptr = command_buffer->virtual;
3625 for (y = 0; y < y_steps; y++) {
3626 for (x = 0; x < x_steps; x++) {
3627 if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3628 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3634 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3635 command_ptr += (param_size >> 2);
3640 if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3643 *command_ptr = MI_BATCH_BUFFER_END;
3645 dri_bo_unmap(command_buffer);
3647 BEGIN_BATCH(batch, 2);
3648 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3649 OUT_RELOC(batch, command_buffer,
3650 I915_GEM_DOMAIN_COMMAND, 0,
3652 ADVANCE_BATCH(batch);
3654 dri_bo_unreference(command_buffer);
3656 /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3657 * will cause control to pass back to ring buffer
3659 intel_batchbuffer_end_atomic(batch);
3660 intel_batchbuffer_flush(batch);
3661 intel_batchbuffer_start_atomic(batch, 0x1000);
3665 gen6_pp_pipeline_setup(VADriverContextP ctx,
3666 struct i965_post_processing_context *pp_context)
3668 struct intel_batchbuffer *batch = pp_context->batch;
3670 intel_batchbuffer_start_atomic(batch, 0x1000);
3671 intel_batchbuffer_emit_mi_flush(batch);
3672 gen6_pp_pipeline_select(ctx, pp_context);
3673 gen6_pp_state_base_address(ctx, pp_context);
3674 gen6_pp_vfe_state(ctx, pp_context);
3675 gen6_pp_curbe_load(ctx, pp_context);
3676 gen6_interface_descriptor_load(ctx, pp_context);
3677 gen6_pp_object_walker(ctx, pp_context);
3678 intel_batchbuffer_end_atomic(batch);
3682 gen6_post_processing(
3683 VADriverContextP ctx,
3684 struct i965_post_processing_context *pp_context,
3685 const struct i965_surface *src_surface,
3686 const VARectangle *src_rect,
3687 struct i965_surface *dst_surface,
3688 const VARectangle *dst_rect,
3695 va_status = gen6_pp_initialize(ctx, pp_context,
3703 if (va_status == VA_STATUS_SUCCESS) {
3704 gen6_pp_states_setup(ctx, pp_context);
3705 gen6_pp_pipeline_setup(ctx, pp_context);
3712 i965_post_processing_internal(
3713 VADriverContextP ctx,
3714 struct i965_post_processing_context *pp_context,
3715 const struct i965_surface *src_surface,
3716 const VARectangle *src_rect,
3717 struct i965_surface *dst_surface,
3718 const VARectangle *dst_rect,
3723 struct i965_driver_data *i965 = i965_driver_data(ctx);
3726 if (IS_GEN6(i965->intel.device_id) ||
3727 IS_GEN7(i965->intel.device_id))
3728 va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3730 va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3736 i965_DestroySurfaces(VADriverContextP ctx,
3737 VASurfaceID *surface_list,
3740 i965_CreateSurfaces(VADriverContextP ctx,
3745 VASurfaceID *surfaces);
3748 rgb_to_yuv(unsigned int argb,
3754 int r = ((argb >> 16) & 0xff);
3755 int g = ((argb >> 8) & 0xff);
3756 int b = ((argb >> 0) & 0xff);
3758 *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3759 *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3760 *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3761 *a = ((argb >> 24) & 0xff);
3765 i965_vpp_clear_surface(VADriverContextP ctx,
3766 struct i965_post_processing_context *pp_context,
3767 VASurfaceID surface,
3770 struct i965_driver_data *i965 = i965_driver_data(ctx);
3771 struct intel_batchbuffer *batch = pp_context->batch;
3772 struct object_surface *obj_surface = SURFACE(surface);
3773 unsigned int blt_cmd, br13;
3774 unsigned int tiling = 0, swizzle = 0;
3776 unsigned char y, u, v, a = 0;
3778 /* Currently only support NV12 surface */
3779 if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3782 rgb_to_yuv(color, &y, &u, &v, &a);
3787 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3788 blt_cmd = XY_COLOR_BLT_CMD;
3789 pitch = obj_surface->width;
3791 if (tiling != I915_TILING_NONE) {
3792 blt_cmd |= XY_COLOR_BLT_DST_TILED;
3800 if (IS_GEN6(i965->intel.device_id) ||
3801 IS_GEN7(i965->intel.device_id)) {
3802 intel_batchbuffer_start_atomic_blt(batch, 48);
3803 BEGIN_BLT_BATCH(batch, 12);
3805 intel_batchbuffer_start_atomic(batch, 48);
3806 BEGIN_BATCH(batch, 12);
3809 OUT_BATCH(batch, blt_cmd);
3810 OUT_BATCH(batch, br13);
3815 obj_surface->height << 16 |
3816 obj_surface->width);
3817 OUT_RELOC(batch, obj_surface->bo,
3818 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3820 OUT_BATCH(batch, y);
3826 OUT_BATCH(batch, blt_cmd);
3827 OUT_BATCH(batch, br13);
3832 obj_surface->height / 2 << 16 |
3833 obj_surface->width / 2);
3834 OUT_RELOC(batch, obj_surface->bo,
3835 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3836 obj_surface->width * obj_surface->y_cb_offset);
3837 OUT_BATCH(batch, v << 8 | u);
3839 ADVANCE_BATCH(batch);
3840 intel_batchbuffer_end_atomic(batch);
3844 i965_post_processing(
3845 VADriverContextP ctx,
3846 VASurfaceID surface,
3847 const VARectangle *src_rect,
3848 const VARectangle *dst_rect,
3850 int *has_done_scaling
3853 struct i965_driver_data *i965 = i965_driver_data(ctx);
3854 VASurfaceID in_surface_id = surface;
3855 VASurfaceID out_surface_id = VA_INVALID_ID;
3857 *has_done_scaling = 0;
3860 struct object_surface *obj_surface;
3862 struct i965_surface src_surface;
3863 struct i965_surface dst_surface;
3865 obj_surface = SURFACE(in_surface_id);
3867 /* Currently only support post processing for NV12 surface */
3868 if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3869 return out_surface_id;
3871 _i965LockMutex(&i965->pp_mutex);
3873 if (flags & I965_PP_FLAG_MCDI) {
3874 status = i965_CreateSurfaces(ctx,
3875 obj_surface->orig_width,
3876 obj_surface->orig_height,
3877 VA_RT_FORMAT_YUV420,
3880 assert(status == VA_STATUS_SUCCESS);
3881 obj_surface = SURFACE(out_surface_id);
3882 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3883 i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3884 src_surface.id = in_surface_id;
3885 src_surface.type = I965_SURFACE_TYPE_SURFACE;
3886 src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3887 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3888 dst_surface.id = out_surface_id;
3889 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3890 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3892 i965_post_processing_internal(ctx, i965->pp_context,
3901 if (flags & I965_PP_FLAG_AVS) {
3902 struct i965_render_state *render_state = &i965->render_state;
3903 struct intel_region *dest_region = render_state->draw_region;
3905 if (out_surface_id != VA_INVALID_ID)
3906 in_surface_id = out_surface_id;
3908 status = i965_CreateSurfaces(ctx,
3910 dest_region->height,
3911 VA_RT_FORMAT_YUV420,
3914 assert(status == VA_STATUS_SUCCESS);
3915 obj_surface = SURFACE(out_surface_id);
3916 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3917 i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3918 src_surface.id = in_surface_id;
3919 src_surface.type = I965_SURFACE_TYPE_SURFACE;
3920 src_surface.flags = I965_SURFACE_FLAG_FRAME;
3921 dst_surface.id = out_surface_id;
3922 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3923 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3925 i965_post_processing_internal(ctx, i965->pp_context,
3933 if (in_surface_id != surface)
3934 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3936 *has_done_scaling = 1;
3939 _i965UnlockMutex(&i965->pp_mutex);
3942 return out_surface_id;
3946 i965_image_pl3_processing(VADriverContextP ctx,
3947 const struct i965_surface *src_surface,
3948 const VARectangle *src_rect,
3949 struct i965_surface *dst_surface,
3950 const VARectangle *dst_rect)
3952 struct i965_driver_data *i965 = i965_driver_data(ctx);
3953 struct i965_post_processing_context *pp_context = i965->pp_context;
3954 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3955 VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
3957 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3958 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3963 PP_PL3_LOAD_SAVE_N12,
3965 } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
3966 fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
3967 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3972 PP_PL3_LOAD_SAVE_PL3,
3974 } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3975 if (IS_GEN6(i965->intel.device_id))
3976 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3981 PP_PL3_LOAD_SAVE_PA,
3988 intel_batchbuffer_flush(pp_context->batch);
3994 i965_image_pl2_processing(VADriverContextP ctx,
3995 const struct i965_surface *src_surface,
3996 const VARectangle *src_rect,
3997 struct i965_surface *dst_surface,
3998 const VARectangle *dst_rect)
4000 struct i965_driver_data *i965 = i965_driver_data(ctx);
4001 struct i965_post_processing_context *pp_context = i965->pp_context;
4002 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4003 VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4005 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4006 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4011 PP_NV12_LOAD_SAVE_N12,
4013 } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4014 fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
4015 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4020 PP_NV12_LOAD_SAVE_PL3,
4022 } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
4023 if (IS_GEN6(i965->intel.device_id))
4024 vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4029 PP_NV12_LOAD_SAVE_PA,
4033 intel_batchbuffer_flush(pp_context->batch);
4039 i965_image_pl1_processing(VADriverContextP ctx,
4040 const struct i965_surface *src_surface,
4041 const VARectangle *src_rect,
4042 struct i965_surface *dst_surface,
4043 const VARectangle *dst_rect)
4045 struct i965_driver_data *i965 = i965_driver_data(ctx);
4046 struct i965_post_processing_context *pp_context = i965->pp_context;
4047 int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4049 if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4050 i965_post_processing_internal(ctx, i965->pp_context,
4055 PP_PA_LOAD_SAVE_NV12,
4058 else if (fourcc == VA_FOURCC_YV12) {
4059 i965_post_processing_internal(ctx, i965->pp_context,
4064 PP_PA_LOAD_SAVE_PL3,
4069 return VA_STATUS_ERROR_UNKNOWN;
4072 intel_batchbuffer_flush(pp_context->batch);
4074 return VA_STATUS_SUCCESS;
4078 i965_image_processing(VADriverContextP ctx,
4079 const struct i965_surface *src_surface,
4080 const VARectangle *src_rect,
4081 struct i965_surface *dst_surface,
4082 const VARectangle *dst_rect)
4084 struct i965_driver_data *i965 = i965_driver_data(ctx);
4085 VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4088 int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4090 _i965LockMutex(&i965->pp_mutex);
4093 case VA_FOURCC('Y', 'V', '1', '2'):
4094 case VA_FOURCC('I', '4', '2', '0'):
4095 case VA_FOURCC('I', 'M', 'C', '1'):
4096 case VA_FOURCC('I', 'M', 'C', '3'):
4097 status = i965_image_pl3_processing(ctx,
4104 case VA_FOURCC('N', 'V', '1', '2'):
4105 status = i965_image_pl2_processing(ctx,
4111 case VA_FOURCC('Y', 'U', 'Y', '2'):
4112 if (IS_GEN6(i965->intel.device_id))
4113 status = i965_image_pl1_processing(ctx,
4121 status = VA_STATUS_ERROR_UNIMPLEMENTED;
4125 _i965UnlockMutex(&i965->pp_mutex);
4132 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4136 dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4137 pp_context->surface_state_binding_table.bo = NULL;
4139 dri_bo_unreference(pp_context->curbe.bo);
4140 pp_context->curbe.bo = NULL;
4142 dri_bo_unreference(pp_context->sampler_state_table.bo);
4143 pp_context->sampler_state_table.bo = NULL;
4145 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4146 pp_context->sampler_state_table.bo_8x8 = NULL;
4148 dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4149 pp_context->sampler_state_table.bo_8x8_uv = NULL;
4151 dri_bo_unreference(pp_context->idrt.bo);
4152 pp_context->idrt.bo = NULL;
4153 pp_context->idrt.num_interface_descriptors = 0;
4155 dri_bo_unreference(pp_context->vfe_state.bo);
4156 pp_context->vfe_state.bo = NULL;
4158 dri_bo_unreference(pp_context->stmm.bo);
4159 pp_context->stmm.bo = NULL;
4161 for (i = 0; i < NUM_PP_MODULES; i++) {
4162 struct pp_module *pp_module = &pp_context->pp_modules[i];
4164 dri_bo_unreference(pp_module->kernel.bo);
4165 pp_module->kernel.bo = NULL;
4168 free(pp_context->pp_static_parameter);
4169 free(pp_context->pp_inline_parameter);
4170 pp_context->pp_static_parameter = NULL;
4171 pp_context->pp_inline_parameter = NULL;
4175 i965_post_processing_terminate(VADriverContextP ctx)
4177 struct i965_driver_data *i965 = i965_driver_data(ctx);
4178 struct i965_post_processing_context *pp_context = i965->pp_context;
4181 i965_post_processing_context_finalize(pp_context);
4185 i965->pp_context = NULL;
4191 i965_post_processing_context_init(VADriverContextP ctx,
4192 struct i965_post_processing_context *pp_context,
4193 struct intel_batchbuffer *batch)
4195 struct i965_driver_data *i965 = i965_driver_data(ctx);
4198 pp_context->urb.size = URB_SIZE((&i965->intel));
4199 pp_context->urb.num_vfe_entries = 32;
4200 pp_context->urb.size_vfe_entry = 1; /* in 512 bits unit */
4201 pp_context->urb.num_cs_entries = 1;
4203 if (IS_GEN7(i965->intel.device_id))
4204 pp_context->urb.size_cs_entry = 4; /* in 512 bits unit */
4206 pp_context->urb.size_cs_entry = 2;
4208 pp_context->urb.vfe_start = 0;
4209 pp_context->urb.cs_start = pp_context->urb.vfe_start +
4210 pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4211 assert(pp_context->urb.cs_start +
4212 pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4214 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4215 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4216 assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4218 if (IS_GEN7(i965->intel.device_id))
4219 memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4220 else if (IS_GEN6(i965->intel.device_id))
4221 memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4222 else if (IS_IRONLAKE(i965->intel.device_id))
4223 memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4225 for (i = 0; i < NUM_PP_MODULES; i++) {
4226 struct pp_module *pp_module = &pp_context->pp_modules[i];
4227 dri_bo_unreference(pp_module->kernel.bo);
4228 if (pp_module->kernel.bin && pp_module->kernel.size) {
4229 pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4230 pp_module->kernel.name,
4231 pp_module->kernel.size,
4233 assert(pp_module->kernel.bo);
4234 dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4236 pp_module->kernel.bo = NULL;
4240 /* static & inline parameters */
4241 if (IS_GEN7(i965->intel.device_id)) {
4242 pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4243 pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4245 pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4246 pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4249 pp_context->batch = batch;
4253 i965_post_processing_init(VADriverContextP ctx)
4255 struct i965_driver_data *i965 = i965_driver_data(ctx);
4256 struct i965_post_processing_context *pp_context = i965->pp_context;
4259 if (pp_context == NULL) {
4260 pp_context = calloc(1, sizeof(*pp_context));
4261 i965_post_processing_context_init(ctx, pp_context, i965->batch);
4262 i965->pp_context = pp_context;
4269 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4270 PP_NULL, /* VAProcFilterNone */
4271 PP_NV12_DN, /* VAProcFilterNoiseReduction */
4272 PP_NULL, /* VAProcFilterDeblocking */
4273 PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4274 PP_NULL, /* VAProcFilterSharpening */
4275 PP_NULL, /* VAProcFilterColorBalance */
4276 PP_NULL, /* VAProcFilterColorStandard */
4277 PP_NULL, /* VAProcFilterFrameRateConversion */
4280 static const int proc_frame_to_pp_frame[3] = {
4281 I965_SURFACE_FLAG_FRAME,
4282 I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4283 I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4287 i965_proc_picture(VADriverContextP ctx,
4289 union codec_state *codec_state,
4290 struct hw_context *hw_context)
4292 struct i965_driver_data *i965 = i965_driver_data(ctx);
4293 struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4294 struct proc_state *proc_state = &codec_state->proc;
4295 VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4296 struct object_surface *obj_surface;
4297 struct i965_surface src_surface, dst_surface;
4298 VARectangle src_rect, dst_rect;
4301 VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4302 int num_tmp_surfaces = 0;
4303 unsigned int tiling = 0, swizzle = 0;
4304 int in_width, in_height;
4306 assert(pipeline_param->surface != VA_INVALID_ID);
4307 assert(proc_state->current_render_target != VA_INVALID_ID);
4309 obj_surface = SURFACE(pipeline_param->surface);
4310 in_width = obj_surface->orig_width;
4311 in_height = obj_surface->orig_height;
4312 dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4314 src_surface.id = pipeline_param->surface;
4315 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4316 src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4318 if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4319 VASurfaceID out_surface_id = VA_INVALID_ID;
4321 src_surface.id = pipeline_param->surface;
4322 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4323 src_surface.flags = I965_SURFACE_FLAG_FRAME;
4326 src_rect.width = in_width;
4327 src_rect.height = in_height;
4329 status = i965_CreateSurfaces(ctx,
4332 VA_RT_FORMAT_YUV420,
4335 assert(status == VA_STATUS_SUCCESS);
4336 tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4337 obj_surface = SURFACE(out_surface_id);
4338 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4340 dst_surface.id = out_surface_id;
4341 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4342 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4345 dst_rect.width = in_width;
4346 dst_rect.height = in_height;
4348 status = i965_image_processing(ctx,
4353 assert(status == VA_STATUS_SUCCESS);
4355 src_surface.id = out_surface_id;
4356 src_surface.type = I965_SURFACE_TYPE_SURFACE;
4357 src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4360 if (pipeline_param->surface_region) {
4361 src_rect.x = pipeline_param->surface_region->x;
4362 src_rect.y = pipeline_param->surface_region->y;
4363 src_rect.width = pipeline_param->surface_region->width;
4364 src_rect.height = pipeline_param->surface_region->height;
4368 src_rect.width = in_width;
4369 src_rect.height = in_height;
4372 if (pipeline_param->output_region) {
4373 dst_rect.x = pipeline_param->output_region->x;
4374 dst_rect.y = pipeline_param->output_region->y;
4375 dst_rect.width = pipeline_param->output_region->width;
4376 dst_rect.height = pipeline_param->output_region->height;
4380 dst_rect.width = in_width;
4381 dst_rect.height = in_height;
4384 obj_surface = SURFACE(proc_state->current_render_target);
4385 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4386 i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4388 for (i = 0; i < pipeline_param->num_filters; i++) {
4389 struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4390 VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4391 VAProcFilterType filter_type = filter_param->type;
4392 VASurfaceID out_surface_id = VA_INVALID_ID;
4393 int kernel_index = procfilter_to_pp_flag[filter_type];
4395 if (kernel_index != PP_NULL &&
4396 proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4397 status = i965_CreateSurfaces(ctx,
4400 VA_RT_FORMAT_YUV420,
4403 assert(status == VA_STATUS_SUCCESS);
4404 tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4405 obj_surface = SURFACE(out_surface_id);
4406 i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4407 dst_surface.id = out_surface_id;
4408 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4409 status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4417 if (status == VA_STATUS_SUCCESS) {
4418 src_surface.id = dst_surface.id;
4419 src_surface.type = dst_surface.type;
4420 src_surface.flags = dst_surface.flags;
4425 dst_surface.id = proc_state->current_render_target;
4426 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4428 if (src_rect.width == dst_rect.width &&
4429 src_rect.height == dst_rect.height) {
4430 i965_post_processing_internal(ctx, &proc_context->pp_context,
4435 PP_NV12_LOAD_SAVE_N12,
4439 i965_post_processing_internal(ctx, &proc_context->pp_context,
4444 (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4445 PP_NV12_AVS : PP_NV12_SCALING,
4449 if (num_tmp_surfaces)
4450 i965_DestroySurfaces(ctx,
4454 intel_batchbuffer_flush(hw_context->batch);
4458 i965_proc_context_destroy(void *hw_context)
4460 struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4462 i965_post_processing_context_finalize(&proc_context->pp_context);
4463 intel_batchbuffer_free(proc_context->base.batch);
4468 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4470 struct intel_driver_data *intel = intel_driver_data(ctx);
4471 struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4473 proc_context->base.destroy = i965_proc_context_destroy;
4474 proc_context->base.run = i965_proc_picture;
4475 proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4476 i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4478 return (struct hw_context *)proc_context;