src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = {
 111 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5"
 112 };
 113
 114 static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = {
 115 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5"
 116 };
 117
 118 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                    const struct i965_surface *src_surface,
 120                                    const VARectangle *src_rect,
 121                                    struct i965_surface *dst_surface,
 122                                    const VARectangle *dst_rect,
 123                                    void *filter_param);
 124 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                             const struct i965_surface *src_surface,
 126                                             const VARectangle *src_rect,
 127                                             struct i965_surface *dst_surface,
 128                                             const VARectangle *dst_rect,
 129                                             void *filter_param);
 130 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 131                                            const struct i965_surface *src_surface,
 132                                            const VARectangle *src_rect,
 133                                            struct i965_surface *dst_surface,
 134                                            const VARectangle *dst_rect,
 135                                            void *filter_param);
 136 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 137                                              const struct i965_surface *src_surface,
 138                                              const VARectangle *src_rect,
 139                                              struct i965_surface *dst_surface,
 140                                              const VARectangle *dst_rect,
 141                                              void *filter_param);
 142 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 143                                                 const struct i965_surface *src_surface,
 144                                                 const VARectangle *src_rect,
 145                                                 struct i965_surface *dst_surface,
 146                                                 const VARectangle *dst_rect,
 147                                                 void *filter_param);
 148 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 149                                         const struct i965_surface *src_surface,
 150                                         const VARectangle *src_rect,
 151                                         struct i965_surface *dst_surface,
 152                                         const VARectangle *dst_rect,
 153                                         void *filter_param);
 154 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 155                                       const struct i965_surface *src_surface,
 156                                       const VARectangle *src_rect,
 157                                       struct i965_surface *dst_surface,
 158                                       const VARectangle *dst_rect,
 159                                       void *filter_param);
 160
 161 static struct pp_module pp_modules_gen5[] = {
 162     {
 163         {
 164             "NULL module (for testing)",
 165             PP_NULL,
 166             pp_null_gen5,
 167             sizeof(pp_null_gen5),
 168             NULL,
 169         },
 170
 171         pp_null_initialize,
 172     },
 173
 174     {
 175         {
 176             "NV12_NV12",
 177             PP_NV12_LOAD_SAVE_N12,
 178             pp_nv12_load_save_nv12_gen5,
 179             sizeof(pp_nv12_load_save_nv12_gen5),
 180             NULL,
 181         },
 182
 183         pp_plx_load_save_plx_initialize,
 184     },
 185
 186     {
 187         {
 188             "NV12_PL3",
 189             PP_NV12_LOAD_SAVE_PL3,
 190             pp_nv12_load_save_pl3_gen5,
 191             sizeof(pp_nv12_load_save_pl3_gen5),
 192             NULL,
 193         },
 194
 195         pp_plx_load_save_plx_initialize,
 196     },
 197
 198     {
 199         {
 200             "PL3_NV12",
 201             PP_PL3_LOAD_SAVE_N12,
 202             pp_pl3_load_save_nv12_gen5,
 203             sizeof(pp_pl3_load_save_nv12_gen5),
 204             NULL,
 205         },
 206
 207         pp_plx_load_save_plx_initialize,
 208     },
 209
 210     {
 211         {
 212             "PL3_PL3",
 213             PP_PL3_LOAD_SAVE_N12,
 214             pp_pl3_load_save_pl3_gen5,
 215             sizeof(pp_pl3_load_save_pl3_gen5),
 216             NULL,
 217         },
 218
 219         pp_plx_load_save_plx_initialize
 220     },
 221
 222     {
 223         {
 224             "NV12 Scaling module",
 225             PP_NV12_SCALING,
 226             pp_nv12_scaling_gen5,
 227             sizeof(pp_nv12_scaling_gen5),
 228             NULL,
 229         },
 230
 231         pp_nv12_scaling_initialize,
 232     },
 233
 234     {
 235         {
 236             "NV12 AVS module",
 237             PP_NV12_AVS,
 238             pp_nv12_avs_gen5,
 239             sizeof(pp_nv12_avs_gen5),
 240             NULL,
 241         },
 242
 243         pp_nv12_avs_initialize_nlas,
 244     },
 245
 246     {
 247         {
 248             "NV12 DNDI module",
 249             PP_NV12_DNDI,
 250             pp_nv12_dndi_gen5,
 251             sizeof(pp_nv12_dndi_gen5),
 252             NULL,
 253         },
 254
 255         pp_nv12_dndi_initialize,
 256     },
 257
 258     {
 259         {
 260             "NV12 DN module",
 261             PP_NV12_DN,
 262             pp_nv12_dn_gen5,
 263             sizeof(pp_nv12_dn_gen5),
 264             NULL,
 265         },
 266
 267         pp_nv12_dn_initialize,
 268     },
 269
 270     {
 271         {
 272             "NV12_PA module",
 273             PP_NV12_LOAD_SAVE_PA,
 274             pp_nv12_load_save_pa_gen5,
 275             sizeof(pp_nv12_load_save_pa_gen5),
 276             NULL,
 277         },
 278
 279         pp_plx_load_save_plx_initialize,
 280     },
 281
 282     {
 283         {
 284             "PL3_PA module",
 285             PP_PL3_LOAD_SAVE_PA,
 286             pp_pl3_load_save_pa_gen5,
 287             sizeof(pp_pl3_load_save_pa_gen5),
 288             NULL,
 289         },
 290
 291         pp_plx_load_save_plx_initialize,
 292     },
 293
 294     {
 295         {
 296             "PA_NV12 module",
 297             PP_PA_LOAD_SAVE_NV12,
 298             pp_pa_load_save_nv12_gen5,
 299             sizeof(pp_pa_load_save_nv12_gen5),
 300             NULL,
 301         },
 302
 303         pp_plx_load_save_plx_initialize,
 304     },
 305
 306     {
 307         {
 308             "PA_PL3 module",
 309             PP_PA_LOAD_SAVE_PL3,
 310             pp_pa_load_save_pl3_gen5,
 311             sizeof(pp_pa_load_save_pl3_gen5),
 312             NULL,
 313         },
 314
 315         pp_plx_load_save_plx_initialize,
 316     },
 317
 318     {
 319         {
 320             "RGBX_NV12 module",
 321             PP_RGBX_LOAD_SAVE_NV12,
 322             pp_rgbx_load_save_nv12_gen5,
 323             sizeof(pp_rgbx_load_save_nv12_gen5),
 324             NULL,
 325         },
 326
 327         pp_plx_load_save_plx_initialize,
 328     },
 329
 330     {
 331         {
 332             "NV12_RGBX module",
 333             PP_NV12_LOAD_SAVE_RGBX,
 334             pp_nv12_load_save_rgbx_gen5,
 335             sizeof(pp_nv12_load_save_rgbx_gen5),
 336             NULL,
 337         },
 338
 339         pp_plx_load_save_plx_initialize,
 340     },
 341
 342 };
 343
 344 static const uint32_t pp_null_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/null.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 350 };
 351
 352 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 354 };
 355
 356 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 362 };
 363
 364 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 365 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 366 };
 367
 368 static const uint32_t pp_nv12_avs_gen6[][4] = {
 369 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 370 };
 371
 372 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 373 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 374 };
 375
 376 static const uint32_t pp_nv12_dn_gen6[][4] = {
 377 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 378 };
 379
 380 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 381 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 382 };
 383
 384 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 385 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 386 };
 387
 388 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 389 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 390 };
 391
 392 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 393 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 394 };
 395
 396 static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = {
 397 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b"
 398 };
 399
 400 static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = {
 401 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b"
 402 };
 403
 404 static struct pp_module pp_modules_gen6[] = {
 405     {
 406         {
 407             "NULL module (for testing)",
 408             PP_NULL,
 409             pp_null_gen6,
 410             sizeof(pp_null_gen6),
 411             NULL,
 412         },
 413
 414         pp_null_initialize,
 415     },
 416
 417     {
 418         {
 419             "NV12_NV12",
 420             PP_NV12_LOAD_SAVE_N12,
 421             pp_nv12_load_save_nv12_gen6,
 422             sizeof(pp_nv12_load_save_nv12_gen6),
 423             NULL,
 424         },
 425
 426         pp_plx_load_save_plx_initialize,
 427     },
 428
 429     {
 430         {
 431             "NV12_PL3",
 432             PP_NV12_LOAD_SAVE_PL3,
 433             pp_nv12_load_save_pl3_gen6,
 434             sizeof(pp_nv12_load_save_pl3_gen6),
 435             NULL,
 436         },
 437
 438         pp_plx_load_save_plx_initialize,
 439     },
 440
 441     {
 442         {
 443             "PL3_NV12",
 444             PP_PL3_LOAD_SAVE_N12,
 445             pp_pl3_load_save_nv12_gen6,
 446             sizeof(pp_pl3_load_save_nv12_gen6),
 447             NULL,
 448         },
 449
 450         pp_plx_load_save_plx_initialize,
 451     },
 452
 453     {
 454         {
 455             "PL3_PL3",
 456             PP_PL3_LOAD_SAVE_N12,
 457             pp_pl3_load_save_pl3_gen6,
 458             sizeof(pp_pl3_load_save_pl3_gen6),
 459             NULL,
 460         },
 461
 462         pp_plx_load_save_plx_initialize,
 463     },
 464
 465     {
 466         {
 467             "NV12 Scaling module",
 468             PP_NV12_SCALING,
 469             pp_nv12_scaling_gen6,
 470             sizeof(pp_nv12_scaling_gen6),
 471             NULL,
 472         },
 473
 474         gen6_nv12_scaling_initialize,
 475     },
 476
 477     {
 478         {
 479             "NV12 AVS module",
 480             PP_NV12_AVS,
 481             pp_nv12_avs_gen6,
 482             sizeof(pp_nv12_avs_gen6),
 483             NULL,
 484         },
 485
 486         pp_nv12_avs_initialize_nlas,
 487     },
 488
 489     {
 490         {
 491             "NV12 DNDI module",
 492             PP_NV12_DNDI,
 493             pp_nv12_dndi_gen6,
 494             sizeof(pp_nv12_dndi_gen6),
 495             NULL,
 496         },
 497
 498         pp_nv12_dndi_initialize,
 499     },
 500
 501     {
 502         {
 503             "NV12 DN module",
 504             PP_NV12_DN,
 505             pp_nv12_dn_gen6,
 506             sizeof(pp_nv12_dn_gen6),
 507             NULL,
 508         },
 509
 510         pp_nv12_dn_initialize,
 511     },
 512     {
 513         {
 514             "NV12_PA module",
 515             PP_NV12_LOAD_SAVE_PA,
 516             pp_nv12_load_save_pa_gen6,
 517             sizeof(pp_nv12_load_save_pa_gen6),
 518             NULL,
 519         },
 520
 521         pp_plx_load_save_plx_initialize,
 522     },
 523
 524     {
 525         {
 526             "PL3_PA module",
 527             PP_PL3_LOAD_SAVE_PA,
 528             pp_pl3_load_save_pa_gen6,
 529             sizeof(pp_pl3_load_save_pa_gen6),
 530             NULL,
 531         },
 532
 533         pp_plx_load_save_plx_initialize,
 534     },
 535
 536     {
 537         {
 538             "PA_NV12 module",
 539             PP_PA_LOAD_SAVE_NV12,
 540             pp_pa_load_save_nv12_gen6,
 541             sizeof(pp_pa_load_save_nv12_gen6),
 542             NULL,
 543         },
 544
 545         pp_plx_load_save_plx_initialize,
 546     },
 547
 548     {
 549         {
 550             "PA_PL3 module",
 551             PP_PA_LOAD_SAVE_PL3,
 552             pp_pa_load_save_pl3_gen6,
 553             sizeof(pp_pa_load_save_pl3_gen6),
 554             NULL,
 555         },
 556
 557         pp_plx_load_save_plx_initialize,
 558     },
 559
 560     {
 561         {
 562             "RGBX_NV12 module",
 563             PP_RGBX_LOAD_SAVE_NV12,
 564             pp_rgbx_load_save_nv12_gen6,
 565             sizeof(pp_rgbx_load_save_nv12_gen6),
 566             NULL,
 567         },
 568
 569         pp_plx_load_save_plx_initialize,
 570     },
 571
 572     {
 573         {
 574             "NV12_RGBX module",
 575             PP_NV12_LOAD_SAVE_RGBX,
 576             pp_nv12_load_save_rgbx_gen6,
 577             sizeof(pp_nv12_load_save_rgbx_gen6),
 578             NULL,
 579         },
 580
 581         pp_plx_load_save_plx_initialize,
 582     },
 583 };
 584
 585 static const uint32_t pp_null_gen7[][4] = {
 586 };
 587
 588 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 589 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 590 };
 591
 592 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 593 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 594 };
 595
 596 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 597 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 598 };
 599
 600 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 601 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 602 };
 603
 604 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 605 #include "shaders/post_processing/gen7/avs.g7b"
 606 };
 607
 608 static const uint32_t pp_nv12_avs_gen7[][4] = {
 609 #include "shaders/post_processing/gen7/avs.g7b"
 610 };
 611
 612 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 613 // #include "shaders/post_processing/gen7/dndi.g7b"
 614 };
 615
 616 static const uint32_t pp_nv12_dn_gen7[][4] = {
 617 };
 618 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 619 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 620 };
 621 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 622 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 623 };
 624 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 625 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 626 };
 627 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 628 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 629 };
 630 static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = {
 631 };
 632 static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = {
 633 };
 634
 635 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 636                                            const struct i965_surface *src_surface,
 637                                            const VARectangle *src_rect,
 638                                            struct i965_surface *dst_surface,
 639                                            const VARectangle *dst_rect,
 640                                            void *filter_param);
 641 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 642                                              const struct i965_surface *src_surface,
 643                                              const VARectangle *src_rect,
 644                                              struct i965_surface *dst_surface,
 645                                              const VARectangle *dst_rect,
 646                                              void *filter_param);
 647 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 648                                            const struct i965_surface *src_surface,
 649                                            const VARectangle *src_rect,
 650                                            struct i965_surface *dst_surface,
 651                                            const VARectangle *dst_rect,
 652                                            void *filter_param);
 653
 654 static struct pp_module pp_modules_gen7[] = {
 655     {
 656         {
 657             "NULL module (for testing)",
 658             PP_NULL,
 659             pp_null_gen7,
 660             sizeof(pp_null_gen7),
 661             NULL,
 662         },
 663
 664         pp_null_initialize,
 665     },
 666
 667     {
 668         {
 669             "NV12_NV12",
 670             PP_NV12_LOAD_SAVE_N12,
 671             pp_nv12_load_save_nv12_gen7,
 672             sizeof(pp_nv12_load_save_nv12_gen7),
 673             NULL,
 674         },
 675
 676         gen7_pp_plx_avs_initialize,
 677     },
 678
 679     {
 680         {
 681             "NV12_PL3",
 682             PP_NV12_LOAD_SAVE_PL3,
 683             pp_nv12_load_save_pl3_gen7,
 684             sizeof(pp_nv12_load_save_pl3_gen7),
 685             NULL,
 686         },
 687
 688         gen7_pp_plx_avs_initialize,
 689     },
 690
 691     {
 692         {
 693             "PL3_NV12",
 694             PP_PL3_LOAD_SAVE_N12,
 695             pp_pl3_load_save_nv12_gen7,
 696             sizeof(pp_pl3_load_save_nv12_gen7),
 697             NULL,
 698         },
 699
 700         gen7_pp_plx_avs_initialize,
 701     },
 702
 703     {
 704         {
 705             "PL3_PL3",
 706             PP_PL3_LOAD_SAVE_N12,
 707             pp_pl3_load_save_pl3_gen7,
 708             sizeof(pp_pl3_load_save_pl3_gen7),
 709             NULL,
 710         },
 711
 712         gen7_pp_plx_avs_initialize,
 713     },
 714
 715     {
 716         {
 717             "NV12 Scaling module",
 718             PP_NV12_SCALING,
 719             pp_nv12_scaling_gen7,
 720             sizeof(pp_nv12_scaling_gen7),
 721             NULL,
 722         },
 723
 724         gen7_pp_plx_avs_initialize,
 725     },
 726
 727     {
 728         {
 729             "NV12 AVS module",
 730             PP_NV12_AVS,
 731             pp_nv12_avs_gen7,
 732             sizeof(pp_nv12_avs_gen7),
 733             NULL,
 734         },
 735
 736         gen7_pp_plx_avs_initialize,
 737     },
 738
 739     {
 740         {
 741             "NV12 DNDI module",
 742             PP_NV12_DNDI,
 743             pp_nv12_dndi_gen7,
 744             sizeof(pp_nv12_dndi_gen7),
 745             NULL,
 746         },
 747
 748         gen7_pp_nv12_dndi_initialize,
 749     },
 750
 751     {
 752         {
 753             "NV12 DN module",
 754             PP_NV12_DN,
 755             pp_nv12_dn_gen7,
 756             sizeof(pp_nv12_dn_gen7),
 757             NULL,
 758         },
 759
 760         gen7_pp_nv12_dn_initialize,
 761     },
 762     {
 763         {
 764             "NV12_PA module",
 765             PP_NV12_LOAD_SAVE_PA,
 766             pp_nv12_load_save_pa_gen7,
 767             sizeof(pp_nv12_load_save_pa_gen7),
 768             NULL,
 769         },
 770
 771         gen7_pp_plx_avs_initialize,
 772     },
 773
 774     {
 775         {
 776             "PL3_PA module",
 777             PP_PL3_LOAD_SAVE_PA,
 778             pp_pl3_load_save_pa_gen7,
 779             sizeof(pp_pl3_load_save_pa_gen7),
 780             NULL,
 781         },
 782
 783         gen7_pp_plx_avs_initialize,
 784     },
 785
 786     {
 787         {
 788             "PA_NV12 module",
 789             PP_PA_LOAD_SAVE_NV12,
 790             pp_pa_load_save_nv12_gen7,
 791             sizeof(pp_pa_load_save_nv12_gen7),
 792             NULL,
 793         },
 794
 795         gen7_pp_plx_avs_initialize,
 796     },
 797
 798     {
 799         {
 800             "PA_PL3 module",
 801             PP_PA_LOAD_SAVE_PL3,
 802             pp_pa_load_save_pl3_gen7,
 803             sizeof(pp_pa_load_save_pl3_gen7),
 804             NULL,
 805         },
 806
 807         gen7_pp_plx_avs_initialize,
 808     },
 809
 810     {
 811         {
 812             "RGBX_NV12 module",
 813             PP_RGBX_LOAD_SAVE_NV12,
 814             pp_rgbx_load_save_nv12_gen7,
 815             sizeof(pp_rgbx_load_save_nv12_gen7),
 816             NULL,
 817         },
 818
 819         pp_plx_load_save_plx_initialize,
 820     },
 821
 822     {
 823         {
 824             "NV12_RGBX module",
 825             PP_NV12_LOAD_SAVE_RGBX,
 826             pp_nv12_load_save_rgbx_gen7,
 827             sizeof(pp_nv12_load_save_rgbx_gen7),
 828             NULL,
 829         },
 830
 831         pp_plx_load_save_plx_initialize,
 832     },
 833
 834 };
 835
 836 static int
 837 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 838 {
 839     struct i965_driver_data *i965 = i965_driver_data(ctx);
 840     int fourcc;
 841
 842     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 843         struct object_image *obj_image = IMAGE(surface->id);
 844         fourcc = obj_image->image.format.fourcc;
 845     } else {
 846         struct object_surface *obj_surface = SURFACE(surface->id);
 847         fourcc = obj_surface->fourcc;
 848     }
 849
 850     return fourcc;
 851 }
 852
 853 static void
 854 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 855 {
 856     switch (tiling) {
 857     case I915_TILING_NONE:
 858         ss->ss3.tiled_surface = 0;
 859         ss->ss3.tile_walk = 0;
 860         break;
 861     case I915_TILING_X:
 862         ss->ss3.tiled_surface = 1;
 863         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 864         break;
 865     case I915_TILING_Y:
 866         ss->ss3.tiled_surface = 1;
 867         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 868         break;
 869     }
 870 }
 871
 872 static void
 873 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 874 {
 875     switch (tiling) {
 876     case I915_TILING_NONE:
 877         ss->ss2.tiled_surface = 0;
 878         ss->ss2.tile_walk = 0;
 879         break;
 880     case I915_TILING_X:
 881         ss->ss2.tiled_surface = 1;
 882         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 883         break;
 884     case I915_TILING_Y:
 885         ss->ss2.tiled_surface = 1;
 886         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 887         break;
 888     }
 889 }
 890
 891 static void
 892 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 893 {
 894     switch (tiling) {
 895     case I915_TILING_NONE:
 896         ss->ss0.tiled_surface = 0;
 897         ss->ss0.tile_walk = 0;
 898         break;
 899     case I915_TILING_X:
 900         ss->ss0.tiled_surface = 1;
 901         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 902         break;
 903     case I915_TILING_Y:
 904         ss->ss0.tiled_surface = 1;
 905         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 906         break;
 907     }
 908 }
 909
 910 static void
 911 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 912 {
 913     switch (tiling) {
 914     case I915_TILING_NONE:
 915         ss->ss2.tiled_surface = 0;
 916         ss->ss2.tile_walk = 0;
 917         break;
 918     case I915_TILING_X:
 919         ss->ss2.tiled_surface = 1;
 920         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 921         break;
 922     case I915_TILING_Y:
 923         ss->ss2.tiled_surface = 1;
 924         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 925         break;
 926     }
 927 }
 928
 929 static void
 930 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 931 {
 932     struct i965_interface_descriptor *desc;
 933     dri_bo *bo;
 934     int pp_index = pp_context->current_pp;
 935
 936     bo = pp_context->idrt.bo;
 937     dri_bo_map(bo, 1);
 938     assert(bo->virtual);
 939     desc = bo->virtual;
 940     memset(desc, 0, sizeof(*desc));
 941     desc->desc0.grf_reg_blocks = 10;
 942     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 943     desc->desc1.const_urb_entry_read_offset = 0;
 944     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 945     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 946     desc->desc2.sampler_count = 0;
 947     desc->desc3.binding_table_entry_count = 0;
 948     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 949
 950     dri_bo_emit_reloc(bo,
 951                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 952                       desc->desc0.grf_reg_blocks,
 953                       offsetof(struct i965_interface_descriptor, desc0),
 954                       pp_context->pp_modules[pp_index].kernel.bo);
 955
 956     dri_bo_emit_reloc(bo,
 957                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 958                       desc->desc2.sampler_count << 2,
 959                       offsetof(struct i965_interface_descriptor, desc2),
 960                       pp_context->sampler_state_table.bo);
 961
 962     dri_bo_unmap(bo);
 963     pp_context->idrt.num_interface_descriptors++;
 964 }
 965
 966 static void
 967 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 968 {
 969     struct i965_vfe_state *vfe_state;
 970     dri_bo *bo;
 971
 972     bo = pp_context->vfe_state.bo;
 973     dri_bo_map(bo, 1);
 974     assert(bo->virtual);
 975     vfe_state = bo->virtual;
 976     memset(vfe_state, 0, sizeof(*vfe_state));
 977     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 978     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 979     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 980     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 981     vfe_state->vfe1.children_present = 0;
 982     vfe_state->vfe2.interface_descriptor_base =
 983         pp_context->idrt.bo->offset >> 4; /* reloc */
 984     dri_bo_emit_reloc(bo,
 985                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 986                       0,
 987                       offsetof(struct i965_vfe_state, vfe2),
 988                       pp_context->idrt.bo);
 989     dri_bo_unmap(bo);
 990 }
 991
 992 static void
 993 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 994 {
 995     unsigned char *constant_buffer;
 996     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 997
 998     assert(sizeof(*pp_static_parameter) == 128);
 999     dri_bo_map(pp_context->curbe.bo, 1);
1000     assert(pp_context->curbe.bo->virtual);
1001     constant_buffer = pp_context->curbe.bo->virtual;
1002     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
1003     dri_bo_unmap(pp_context->curbe.bo);
1004 }
1005
1006 static void
1007 ironlake_pp_states_setup(VADriverContextP ctx,
1008                          struct i965_post_processing_context *pp_context)
1009 {
1010     ironlake_pp_interface_descriptor_table(pp_context);
1011     ironlake_pp_vfe_state(pp_context);
1012     ironlake_pp_upload_constants(pp_context);
1013 }
1014
1015 static void
1016 ironlake_pp_pipeline_select(VADriverContextP ctx,
1017                             struct i965_post_processing_context *pp_context)
1018 {
1019     struct intel_batchbuffer *batch = pp_context->batch;
1020
1021     BEGIN_BATCH(batch, 1);
1022     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
1023     ADVANCE_BATCH(batch);
1024 }
1025
1026 static void
1027 ironlake_pp_urb_layout(VADriverContextP ctx,
1028                        struct i965_post_processing_context *pp_context)
1029 {
1030     struct intel_batchbuffer *batch = pp_context->batch;
1031     unsigned int vfe_fence, cs_fence;
1032
1033     vfe_fence = pp_context->urb.cs_start;
1034     cs_fence = pp_context->urb.size;
1035
1036     BEGIN_BATCH(batch, 3);
1037     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
1038     OUT_BATCH(batch, 0);
1039     OUT_BATCH(batch,
1040               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
1041               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
1042     ADVANCE_BATCH(batch);
1043 }
1044
1045 static void
1046 ironlake_pp_state_base_address(VADriverContextP ctx,
1047                                struct i965_post_processing_context *pp_context)
1048 {
1049     struct intel_batchbuffer *batch = pp_context->batch;
1050
1051     BEGIN_BATCH(batch, 8);
1052     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1053     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1054     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1055     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1056     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1057     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1058     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1059     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1060     ADVANCE_BATCH(batch);
1061 }
1062
1063 static void
1064 ironlake_pp_state_pointers(VADriverContextP ctx,
1065                            struct i965_post_processing_context *pp_context)
1066 {
1067     struct intel_batchbuffer *batch = pp_context->batch;
1068
1069     BEGIN_BATCH(batch, 3);
1070     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
1071     OUT_BATCH(batch, 0);
1072     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1073     ADVANCE_BATCH(batch);
1074 }
1075
1076 static void
1077 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
1078                           struct i965_post_processing_context *pp_context)
1079 {
1080     struct intel_batchbuffer *batch = pp_context->batch;
1081
1082     BEGIN_BATCH(batch, 2);
1083     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1084     OUT_BATCH(batch,
1085               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
1086               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
1087     ADVANCE_BATCH(batch);
1088 }
1089
1090 static void
1091 ironlake_pp_constant_buffer(VADriverContextP ctx,
1092                             struct i965_post_processing_context *pp_context)
1093 {
1094     struct intel_batchbuffer *batch = pp_context->batch;
1095
1096     BEGIN_BATCH(batch, 2);
1097     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1098     OUT_RELOC(batch, pp_context->curbe.bo,
1099               I915_GEM_DOMAIN_INSTRUCTION, 0,
1100               pp_context->urb.size_cs_entry - 1);
1101     ADVANCE_BATCH(batch);
1102 }
1103
1104 static void
1105 ironlake_pp_object_walker(VADriverContextP ctx,
1106                           struct i965_post_processing_context *pp_context)
1107 {
1108     struct intel_batchbuffer *batch = pp_context->batch;
1109     int x, x_steps, y, y_steps;
1110     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1111
1112     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1113     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1114
1115     for (y = 0; y < y_steps; y++) {
1116         for (x = 0; x < x_steps; x++) {
1117             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1118                 BEGIN_BATCH(batch, 20);
1119                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1120                 OUT_BATCH(batch, 0);
1121                 OUT_BATCH(batch, 0); /* no indirect data */
1122                 OUT_BATCH(batch, 0);
1123
1124                 /* inline data grf 5-6 */
1125                 assert(sizeof(*pp_inline_parameter) == 64);
1126                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1127
1128                 ADVANCE_BATCH(batch);
1129             }
1130         }
1131     }
1132 }
1133
1134 static void
1135 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1136                            struct i965_post_processing_context *pp_context)
1137 {
1138     struct intel_batchbuffer *batch = pp_context->batch;
1139
1140     intel_batchbuffer_start_atomic(batch, 0x1000);
1141     intel_batchbuffer_emit_mi_flush(batch);
1142     ironlake_pp_pipeline_select(ctx, pp_context);
1143     ironlake_pp_state_base_address(ctx, pp_context);
1144     ironlake_pp_state_pointers(ctx, pp_context);
1145     ironlake_pp_urb_layout(ctx, pp_context);
1146     ironlake_pp_cs_urb_layout(ctx, pp_context);
1147     ironlake_pp_constant_buffer(ctx, pp_context);
1148     ironlake_pp_object_walker(ctx, pp_context);
1149     intel_batchbuffer_end_atomic(batch);
1150 }
1151
1152 // update u/v offset when the surface format are packed yuv
1153 static void i965_update_src_surface_static_parameter(
1154     VADriverContextP    ctx,
1155     struct i965_post_processing_context *pp_context,
1156     const struct i965_surface *surface)
1157 {
1158     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1159     int fourcc = pp_get_surface_fourcc(ctx, surface);
1160
1161     switch (fourcc) {
1162     case VA_FOURCC('Y', 'U', 'Y', '2'):
1163         pp_static_parameter->grf1.source_packed_u_offset = 1;
1164         pp_static_parameter->grf1.source_packed_v_offset = 3;
1165         break;
1166     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1167         pp_static_parameter->grf1.source_packed_y_offset = 1;
1168         pp_static_parameter->grf1.source_packed_v_offset = 2;
1169         break;
1170     case VA_FOURCC('B', 'G', 'R', 'X'):
1171     case VA_FOURCC('B', 'G', 'R', 'A'):
1172         pp_static_parameter->grf1.source_rgb_layout = 0;
1173         break;
1174     case VA_FOURCC('R', 'G', 'B', 'X'):
1175     case VA_FOURCC('R', 'G', 'B', 'A'):
1176         pp_static_parameter->grf1.source_rgb_layout = 1;
1177         break;
1178     default:
1179         break;
1180     }
1181
1182 }
1183
1184 static void i965_update_dst_surface_static_parameter(
1185     VADriverContextP    ctx,
1186     struct i965_post_processing_context *pp_context,
1187     const struct i965_surface *surface)
1188 {
1189     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1190     int fourcc = pp_get_surface_fourcc(ctx, surface);
1191
1192     switch (fourcc) {
1193     case VA_FOURCC('Y', 'U', 'Y', '2'):
1194         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1195         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1196         break;
1197     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1198         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1199         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1200         break;
1201     case VA_FOURCC('B', 'G', 'R', 'X'):
1202     case VA_FOURCC('B', 'G', 'R', 'A'):
1203         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0;
1204         break;
1205     case VA_FOURCC('R', 'G', 'B', 'X'):
1206     case VA_FOURCC('R', 'G', 'B', 'A'):
1207         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1;
1208         break;
1209     default:
1210         break;
1211     }
1212
1213 }
1214
1215 static void
1216 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1217                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1218                           int width, int height, int pitch, int format,
1219                           int index, int is_target)
1220 {
1221     struct i965_surface_state *ss;
1222     dri_bo *ss_bo;
1223     unsigned int tiling;
1224     unsigned int swizzle;
1225
1226     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1227     ss_bo = pp_context->surface_state_binding_table.bo;
1228     assert(ss_bo);
1229
1230     dri_bo_map(ss_bo, True);
1231     assert(ss_bo->virtual);
1232     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1233     memset(ss, 0, sizeof(*ss));
1234     ss->ss0.surface_type = I965_SURFACE_2D;
1235     ss->ss0.surface_format = format;
1236     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1237     ss->ss2.width = width - 1;
1238     ss->ss2.height = height - 1;
1239     ss->ss3.pitch = pitch - 1;
1240     pp_set_surface_tiling(ss, tiling);
1241     dri_bo_emit_reloc(ss_bo,
1242                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1243                       surf_bo_offset,
1244                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1245                       surf_bo);
1246     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1247     dri_bo_unmap(ss_bo);
1248 }
1249
1250 static void
1251 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1252                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1253                            int width, int height, int wpitch,
1254                            int xoffset, int yoffset,
1255                            int format, int interleave_chroma,
1256                            int index)
1257 {
1258     struct i965_surface_state2 *ss2;
1259     dri_bo *ss2_bo;
1260     unsigned int tiling;
1261     unsigned int swizzle;
1262
1263     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1264     ss2_bo = pp_context->surface_state_binding_table.bo;
1265     assert(ss2_bo);
1266
1267     dri_bo_map(ss2_bo, True);
1268     assert(ss2_bo->virtual);
1269     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1270     memset(ss2, 0, sizeof(*ss2));
1271     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1272     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1273     ss2->ss1.width = width - 1;
1274     ss2->ss1.height = height - 1;
1275     ss2->ss2.pitch = wpitch - 1;
1276     ss2->ss2.interleave_chroma = interleave_chroma;
1277     ss2->ss2.surface_format = format;
1278     ss2->ss3.x_offset_for_cb = xoffset;
1279     ss2->ss3.y_offset_for_cb = yoffset;
1280     pp_set_surface2_tiling(ss2, tiling);
1281     dri_bo_emit_reloc(ss2_bo,
1282                       I915_GEM_DOMAIN_RENDER, 0,
1283                       surf_bo_offset,
1284                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1285                       surf_bo);
1286     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1287     dri_bo_unmap(ss2_bo);
1288 }
1289
1290 static void
1291 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1292                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1293                           int width, int height, int pitch, int format,
1294                           int index, int is_target)
1295 {
1296     struct gen7_surface_state *ss;
1297     dri_bo *ss_bo;
1298     unsigned int tiling;
1299     unsigned int swizzle;
1300
1301     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1302     ss_bo = pp_context->surface_state_binding_table.bo;
1303     assert(ss_bo);
1304
1305     dri_bo_map(ss_bo, True);
1306     assert(ss_bo->virtual);
1307     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1308     memset(ss, 0, sizeof(*ss));
1309     ss->ss0.surface_type = I965_SURFACE_2D;
1310     ss->ss0.surface_format = format;
1311     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1312     ss->ss2.width = width - 1;
1313     ss->ss2.height = height - 1;
1314     ss->ss3.pitch = pitch - 1;
1315     gen7_pp_set_surface_tiling(ss, tiling);
1316     dri_bo_emit_reloc(ss_bo,
1317                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1318                       surf_bo_offset,
1319                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1320                       surf_bo);
1321     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1322     dri_bo_unmap(ss_bo);
1323 }
1324
1325 static void
1326 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1327                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1328                            int width, int height, int wpitch,
1329                            int xoffset, int yoffset,
1330                            int format, int interleave_chroma,
1331                            int index)
1332 {
1333     struct gen7_surface_state2 *ss2;
1334     dri_bo *ss2_bo;
1335     unsigned int tiling;
1336     unsigned int swizzle;
1337
1338     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1339     ss2_bo = pp_context->surface_state_binding_table.bo;
1340     assert(ss2_bo);
1341
1342     dri_bo_map(ss2_bo, True);
1343     assert(ss2_bo->virtual);
1344     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1345     memset(ss2, 0, sizeof(*ss2));
1346     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1347     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1348     ss2->ss1.width = width - 1;
1349     ss2->ss1.height = height - 1;
1350     ss2->ss2.pitch = wpitch - 1;
1351     ss2->ss2.interleave_chroma = interleave_chroma;
1352     ss2->ss2.surface_format = format;
1353     ss2->ss3.x_offset_for_cb = xoffset;
1354     ss2->ss3.y_offset_for_cb = yoffset;
1355     gen7_pp_set_surface2_tiling(ss2, tiling);
1356     dri_bo_emit_reloc(ss2_bo,
1357                       I915_GEM_DOMAIN_RENDER, 0,
1358                       surf_bo_offset,
1359                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1360                       surf_bo);
1361     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1362     dri_bo_unmap(ss2_bo);
1363 }
1364
1365 static void
1366 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1367                                 const struct i965_surface *surface,
1368                                 int base_index, int is_target,
1369                                 int *width, int *height, int *pitch, int *offset)
1370 {
1371     struct i965_driver_data *i965 = i965_driver_data(ctx);
1372     struct object_surface *obj_surface;
1373     struct object_image *obj_image;
1374     dri_bo *bo;
1375     int fourcc = pp_get_surface_fourcc(ctx, surface);
1376     const int Y = 0;
1377     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1378     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1379     const int UV = 1;
1380     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1381     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1382     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1383                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1384                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1385                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1386     int scale_factor_of_1st_plane_width_in_byte = 1;
1387
1388     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1389         obj_surface = SURFACE(surface->id);
1390         bo = obj_surface->bo;
1391         width[0] = obj_surface->orig_width;
1392         height[0] = obj_surface->orig_height;
1393         pitch[0] = obj_surface->width;
1394         offset[0] = 0;
1395
1396         if (full_packed_format) {
1397             scale_factor_of_1st_plane_width_in_byte = 4;
1398             pitch[0] = obj_surface->width * 4;
1399         }
1400         else if (packed_yuv ) {
1401             scale_factor_of_1st_plane_width_in_byte =  2;
1402             pitch[0] = obj_surface->width * 2;
1403         }
1404         else if (interleaved_uv) {
1405             width[1] = obj_surface->orig_width;
1406             height[1] = obj_surface->orig_height / 2;
1407             pitch[1] = obj_surface->width;
1408             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1409         } else {
1410             width[1] = obj_surface->orig_width / 2;
1411             height[1] = obj_surface->orig_height / 2;
1412             pitch[1] = obj_surface->width / 2;
1413             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1414             width[2] = obj_surface->orig_width / 2;
1415             height[2] = obj_surface->orig_height / 2;
1416             pitch[2] = obj_surface->width / 2;
1417             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1418         }
1419     } else {
1420         obj_image = IMAGE(surface->id);
1421         bo = obj_image->bo;
1422         width[0] = obj_image->image.width;
1423         height[0] = obj_image->image.height;
1424         pitch[0] = obj_image->image.pitches[0];
1425         offset[0] = obj_image->image.offsets[0];
1426
1427         if (full_packed_format) {
1428             scale_factor_of_1st_plane_width_in_byte = 4;
1429         }
1430         else if (packed_yuv ) {
1431             scale_factor_of_1st_plane_width_in_byte = 2;
1432         }
1433         else if (interleaved_uv) {
1434             width[1] = obj_image->image.width;
1435             height[1] = obj_image->image.height / 2;
1436             pitch[1] = obj_image->image.pitches[1];
1437             offset[1] = obj_image->image.offsets[1];
1438         } else {
1439             width[1] = obj_image->image.width / 2;
1440             height[1] = obj_image->image.height / 2;
1441             pitch[1] = obj_image->image.pitches[1];
1442             offset[1] = obj_image->image.offsets[1];
1443             width[2] = obj_image->image.width / 2;
1444             height[2] = obj_image->image.height / 2;
1445             pitch[2] = obj_image->image.pitches[2];
1446             offset[2] = obj_image->image.offsets[2];
1447         }
1448     }
1449
1450     /* Y surface */
1451     i965_pp_set_surface_state(ctx, pp_context,
1452                               bo, offset[Y],
1453                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1454                               base_index, is_target);
1455
1456     if (!packed_yuv && !full_packed_format) {
1457         if (interleaved_uv) {
1458             i965_pp_set_surface_state(ctx, pp_context,
1459                                       bo, offset[UV],
1460                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1461                                       base_index + 1, is_target);
1462         } else {
1463             /* U surface */
1464             i965_pp_set_surface_state(ctx, pp_context,
1465                                       bo, offset[U],
1466                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1467                                       base_index + 1, is_target);
1468
1469             /* V surface */
1470             i965_pp_set_surface_state(ctx, pp_context,
1471                                       bo, offset[V],
1472                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1473                                       base_index + 2, is_target);
1474         }
1475     }
1476
1477 }
1478
1479 static void
1480 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1481                                      const struct i965_surface *surface,
1482                                      int base_index, int is_target,
1483                                      int *width, int *height, int *pitch, int *offset)
1484 {
1485     struct i965_driver_data *i965 = i965_driver_data(ctx);
1486     struct object_surface *obj_surface;
1487     struct object_image *obj_image;
1488     dri_bo *bo;
1489     int fourcc = pp_get_surface_fourcc(ctx, surface);
1490     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1491                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1492     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1493                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1494     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1495     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1496
1497     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1498         obj_surface = SURFACE(surface->id);
1499         bo = obj_surface->bo;
1500         width[0] = obj_surface->orig_width;
1501         height[0] = obj_surface->orig_height;
1502         pitch[0] = obj_surface->width;
1503         offset[0] = 0;
1504
1505         if (packed_yuv) {
1506             if (is_target)
1507                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1508             else
1509                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1510
1511             pitch[0] = obj_surface->width * 2;
1512         }
1513
1514         width[1] = obj_surface->cb_cr_width;
1515         height[1] = obj_surface->cb_cr_height;
1516         pitch[1] = obj_surface->cb_cr_pitch;
1517         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1518
1519         width[2] = obj_surface->cb_cr_width;
1520         height[2] = obj_surface->cb_cr_height;
1521         pitch[2] = obj_surface->cb_cr_pitch;
1522         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1523     } else {
1524         obj_image = IMAGE(surface->id);
1525         bo = obj_image->bo;
1526         width[0] = obj_image->image.width;
1527         height[0] = obj_image->image.height;
1528         pitch[0] = obj_image->image.pitches[0];
1529         offset[0] = obj_image->image.offsets[0];
1530
1531         if (packed_yuv) {
1532             if (is_target)
1533                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1534             else
1535                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1536         } else if (interleaved_uv) {
1537             width[1] = obj_image->image.width / 2;
1538             height[1] = obj_image->image.height / 2;
1539             pitch[1] = obj_image->image.pitches[1];
1540             offset[1] = obj_image->image.offsets[1];
1541         } else {
1542             width[1] = obj_image->image.width / 2;
1543             height[1] = obj_image->image.height / 2;
1544             pitch[1] = obj_image->image.pitches[U];
1545             offset[1] = obj_image->image.offsets[U];
1546             width[2] = obj_image->image.width / 2;
1547             height[2] = obj_image->image.height / 2;
1548             pitch[2] = obj_image->image.pitches[V];
1549             offset[2] = obj_image->image.offsets[V];
1550         }
1551     }
1552
1553     if (is_target) {
1554         gen7_pp_set_surface_state(ctx, pp_context,
1555                                   bo, 0,
1556                                   width[0] / 4, height[0], pitch[0],
1557                                   I965_SURFACEFORMAT_R8_SINT,
1558                                   base_index, 1);
1559
1560         if (!packed_yuv) {
1561             if (interleaved_uv) {
1562                 gen7_pp_set_surface_state(ctx, pp_context,
1563                                           bo, offset[1],
1564                                           width[1] / 2, height[1], pitch[1],
1565                                           I965_SURFACEFORMAT_R8G8_SINT,
1566                                           base_index + 1, 1);
1567             } else {
1568                 gen7_pp_set_surface_state(ctx, pp_context,
1569                                           bo, offset[1],
1570                                           width[1] / 4, height[1], pitch[1],
1571                                           I965_SURFACEFORMAT_R8_SINT,
1572                                           base_index + 1, 1);
1573                 gen7_pp_set_surface_state(ctx, pp_context,
1574                                           bo, offset[2],
1575                                           width[2] / 4, height[2], pitch[2],
1576                                           I965_SURFACEFORMAT_R8_SINT,
1577                                           base_index + 2, 1);
1578             }
1579         }
1580     } else {
1581         int format0 = SURFACE_FORMAT_Y8_UNORM;
1582
1583         switch (fourcc) {
1584         case VA_FOURCC('Y', 'U', 'Y', '2'):
1585             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1586             break;
1587
1588         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1589             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1590             break;
1591
1592         default:
1593             break;
1594         }
1595
1596         gen7_pp_set_surface2_state(ctx, pp_context,
1597                                    bo, offset[0],
1598                                    width[0], height[0], pitch[0],
1599                                    0, 0,
1600                                    format0, 0,
1601                                    base_index);
1602
1603         if (!packed_yuv) {
1604             if (interleaved_uv) {
1605                 gen7_pp_set_surface2_state(ctx, pp_context,
1606                                            bo, offset[1],
1607                                            width[1], height[1], pitch[1],
1608                                            0, 0,
1609                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1610                                            base_index + 1);
1611             } else {
1612                 gen7_pp_set_surface2_state(ctx, pp_context,
1613                                            bo, offset[1],
1614                                            width[1], height[1], pitch[1],
1615                                            0, 0,
1616                                            SURFACE_FORMAT_R8_UNORM, 0,
1617                                            base_index + 1);
1618                 gen7_pp_set_surface2_state(ctx, pp_context,
1619                                            bo, offset[2],
1620                                            width[2], height[2], pitch[2],
1621                                            0, 0,
1622                                            SURFACE_FORMAT_R8_UNORM, 0,
1623                                            base_index + 2);
1624             }
1625         }
1626     }
1627 }
1628
1629 static int
1630 pp_null_x_steps(void *private_context)
1631 {
1632     return 1;
1633 }
1634
1635 static int
1636 pp_null_y_steps(void *private_context)
1637 {
1638     return 1;
1639 }
1640
1641 static int
1642 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1643 {
1644     return 0;
1645 }
1646
1647 static VAStatus
1648 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1649                    const struct i965_surface *src_surface,
1650                    const VARectangle *src_rect,
1651                    struct i965_surface *dst_surface,
1652                    const VARectangle *dst_rect,
1653                    void *filter_param)
1654 {
1655     /* private function & data */
1656     pp_context->pp_x_steps = pp_null_x_steps;
1657     pp_context->pp_y_steps = pp_null_y_steps;
1658     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1659
1660     dst_surface->flags = src_surface->flags;
1661
1662     return VA_STATUS_SUCCESS;
1663 }
1664
1665 static int
1666 pp_load_save_x_steps(void *private_context)
1667 {
1668     return 1;
1669 }
1670
1671 static int
1672 pp_load_save_y_steps(void *private_context)
1673 {
1674     struct pp_load_save_context *pp_load_save_context = private_context;
1675
1676     return pp_load_save_context->dest_h / 8;
1677 }
1678
1679 static int
1680 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1681 {
1682     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1683
1684     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1685     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1686     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1687     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1688
1689     return 0;
1690 }
1691
1692 static VAStatus
1693 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1694                                 const struct i965_surface *src_surface,
1695                                 const VARectangle *src_rect,
1696                                 struct i965_surface *dst_surface,
1697                                 const VARectangle *dst_rect,
1698                                 void *filter_param)
1699 {
1700     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1701     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1702     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1703     int width[3], height[3], pitch[3], offset[3];
1704     const int Y = 0;
1705
1706     /* source surface */
1707     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1708                                     width, height, pitch, offset);
1709
1710     /* destination surface */
1711     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1712                                     width, height, pitch, offset);
1713
1714     /* private function & data */
1715     pp_context->pp_x_steps = pp_load_save_x_steps;
1716     pp_context->pp_y_steps = pp_load_save_y_steps;
1717     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1718     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1719     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1720
1721     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1722     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1723
1724     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1725     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1726
1727     // update u/v offset for packed yuv
1728     i965_update_src_surface_static_parameter (ctx, pp_context, src_surface);
1729     i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface);
1730
1731     dst_surface->flags = src_surface->flags;
1732
1733     return VA_STATUS_SUCCESS;
1734 }
1735
1736 static int
1737 pp_scaling_x_steps(void *private_context)
1738 {
1739     return 1;
1740 }
1741
1742 static int
1743 pp_scaling_y_steps(void *private_context)
1744 {
1745     struct pp_scaling_context *pp_scaling_context = private_context;
1746
1747     return pp_scaling_context->dest_h / 8;
1748 }
1749
1750 static int
1751 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1752 {
1753     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1754     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1755     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1756     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1757     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1758
1759     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1760     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1761     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1762     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1763
1764     return 0;
1765 }
1766
1767 static VAStatus
1768 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1769                            const struct i965_surface *src_surface,
1770                            const VARectangle *src_rect,
1771                            struct i965_surface *dst_surface,
1772                            const VARectangle *dst_rect,
1773                            void *filter_param)
1774 {
1775     struct i965_driver_data *i965 = i965_driver_data(ctx);
1776     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1777     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1778     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1779     struct object_surface *obj_surface;
1780     struct i965_sampler_state *sampler_state;
1781     int in_w, in_h, in_wpitch, in_hpitch;
1782     int out_w, out_h, out_wpitch, out_hpitch;
1783
1784     /* source surface */
1785     obj_surface = SURFACE(src_surface->id);
1786     in_w = obj_surface->orig_width;
1787     in_h = obj_surface->orig_height;
1788     in_wpitch = obj_surface->width;
1789     in_hpitch = obj_surface->height;
1790
1791     /* source Y surface index 1 */
1792     i965_pp_set_surface_state(ctx, pp_context,
1793                               obj_surface->bo, 0,
1794                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1795                               1, 0);
1796
1797     /* source UV surface index 2 */
1798     i965_pp_set_surface_state(ctx, pp_context,
1799                               obj_surface->bo, in_wpitch * in_hpitch,
1800                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1801                               2, 0);
1802
1803     /* destination surface */
1804     obj_surface = SURFACE(dst_surface->id);
1805     out_w = obj_surface->orig_width;
1806     out_h = obj_surface->orig_height;
1807     out_wpitch = obj_surface->width;
1808     out_hpitch = obj_surface->height;
1809
1810     /* destination Y surface index 7 */
1811     i965_pp_set_surface_state(ctx, pp_context,
1812                               obj_surface->bo, 0,
1813                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1814                               7, 1);
1815
1816     /* destination UV surface index 8 */
1817     i965_pp_set_surface_state(ctx, pp_context,
1818                               obj_surface->bo, out_wpitch * out_hpitch,
1819                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1820                               8, 1);
1821
1822     /* sampler state */
1823     dri_bo_map(pp_context->sampler_state_table.bo, True);
1824     assert(pp_context->sampler_state_table.bo->virtual);
1825     sampler_state = pp_context->sampler_state_table.bo->virtual;
1826
1827     /* SIMD16 Y index 1 */
1828     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1829     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1830     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1831     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1832     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1833
1834     /* SIMD16 UV index 2 */
1835     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1836     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1837     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1838     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1839     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1840
1841     dri_bo_unmap(pp_context->sampler_state_table.bo);
1842
1843     /* private function & data */
1844     pp_context->pp_x_steps = pp_scaling_x_steps;
1845     pp_context->pp_y_steps = pp_scaling_y_steps;
1846     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1847
1848     pp_scaling_context->dest_x = dst_rect->x;
1849     pp_scaling_context->dest_y = dst_rect->y;
1850     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1851     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1852     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1853     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1854
1855     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1856
1857     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1858     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1859     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1860     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1861     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1862
1863     dst_surface->flags = src_surface->flags;
1864
1865     return VA_STATUS_SUCCESS;
1866 }
1867
1868 static int
1869 pp_avs_x_steps(void *private_context)
1870 {
1871     struct pp_avs_context *pp_avs_context = private_context;
1872
1873     return pp_avs_context->dest_w / 16;
1874 }
1875
1876 static int
1877 pp_avs_y_steps(void *private_context)
1878 {
1879     return 1;
1880 }
1881
1882 static int
1883 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1884 {
1885     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1886     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1887     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1888     float src_x_steping, src_y_steping, video_step_delta;
1889     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1890
1891     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1892         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1893         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1894     } else if (tmp_w >= pp_avs_context->dest_w) {
1895         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1896         pp_inline_parameter->grf6.video_step_delta = 0;
1897
1898         if (x == 0) {
1899             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1900                 pp_avs_context->src_normalized_x;
1901         } else {
1902             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1903             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1904             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1905                 16 * 15 * video_step_delta / 2;
1906         }
1907     } else {
1908         int n0, n1, n2, nls_left, nls_right;
1909         int factor_a = 5, factor_b = 4;
1910         float f;
1911
1912         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1913         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1914         n2 = tmp_w / (16 * factor_a);
1915         nls_left = n0 + n2;
1916         nls_right = n1 + n2;
1917         f = (float) n2 * 16 / tmp_w;
1918
1919         if (n0 < 5) {
1920             pp_inline_parameter->grf6.video_step_delta = 0.0;
1921
1922             if (x == 0) {
1923                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1924                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1925             } else {
1926                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1927                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1928                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1929                     16 * 15 * video_step_delta / 2;
1930             }
1931         } else {
1932             if (x < nls_left) {
1933                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1934                 float a = f / (nls_left * 16 * factor_b);
1935                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1936
1937                 pp_inline_parameter->grf6.video_step_delta = b;
1938
1939                 if (x == 0) {
1940                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1941                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1942                 } else {
1943                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1944                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1945                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1946                         16 * 15 * video_step_delta / 2;
1947                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1948                 }
1949             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1950                 /* scale the center linearly */
1951                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1952                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1953                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1954                     16 * 15 * video_step_delta / 2;
1955                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1956                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1957             } else {
1958                 float a = f / (nls_right * 16 * factor_b);
1959                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1960
1961                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1962                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1963                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1964                     16 * 15 * video_step_delta / 2;
1965                 pp_inline_parameter->grf6.video_step_delta = -b;
1966
1967                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1968                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1969                 else
1970                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1971             }
1972         }
1973     }
1974
1975     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1976     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1977     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1978     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1979
1980     return 0;
1981 }
1982
1983 static VAStatus
1984 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1985                        const struct i965_surface *src_surface,
1986                        const VARectangle *src_rect,
1987                        struct i965_surface *dst_surface,
1988                        const VARectangle *dst_rect,
1989                        void *filter_param,
1990                        int nlas)
1991 {
1992     struct i965_driver_data *i965 = i965_driver_data(ctx);
1993     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1994     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1995     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1996     struct object_surface *obj_surface;
1997     struct i965_sampler_8x8 *sampler_8x8;
1998     struct i965_sampler_8x8_state *sampler_8x8_state;
1999     int index;
2000     int in_w, in_h, in_wpitch, in_hpitch;
2001     int out_w, out_h, out_wpitch, out_hpitch;
2002     int i;
2003
2004     /* surface */
2005     obj_surface = SURFACE(src_surface->id);
2006     in_w = obj_surface->orig_width;
2007     in_h = obj_surface->orig_height;
2008     in_wpitch = obj_surface->width;
2009     in_hpitch = obj_surface->height;
2010
2011     /* source Y surface index 1 */
2012     i965_pp_set_surface2_state(ctx, pp_context,
2013                                obj_surface->bo, 0,
2014                                in_w, in_h, in_wpitch,
2015                                0, 0,
2016                                SURFACE_FORMAT_Y8_UNORM, 0,
2017                                1);
2018
2019     /* source UV surface index 2 */
2020     i965_pp_set_surface2_state(ctx, pp_context,
2021                                obj_surface->bo, in_wpitch * in_hpitch,
2022                                in_w / 2, in_h / 2, in_wpitch,
2023                                0, 0,
2024                                SURFACE_FORMAT_R8B8_UNORM, 0,
2025                                2);
2026
2027     /* destination surface */
2028     obj_surface = SURFACE(dst_surface->id);
2029     out_w = obj_surface->orig_width;
2030     out_h = obj_surface->orig_height;
2031     out_wpitch = obj_surface->width;
2032     out_hpitch = obj_surface->height;
2033     assert(out_w <= out_wpitch && out_h <= out_hpitch);
2034
2035     /* destination Y surface index 7 */
2036     i965_pp_set_surface_state(ctx, pp_context,
2037                               obj_surface->bo, 0,
2038                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2039                               7, 1);
2040
2041     /* destination UV surface index 8 */
2042     i965_pp_set_surface_state(ctx, pp_context,
2043                               obj_surface->bo, out_wpitch * out_hpitch,
2044                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2045                               8, 1);
2046
2047     /* sampler 8x8 state */
2048     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2049     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2050     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2051     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2052     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2053
2054     for (i = 0; i < 17; i++) {
2055         /* for Y channel, currently ignore */
2056         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
2057         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
2058         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
2059         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
2060         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
2061         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
2062         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
2063         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
2064         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
2065         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
2066         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
2067         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
2068         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
2069         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
2070         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
2071         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
2072         /* for U/V channel, 0.25 */
2073         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2074         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2075         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2076         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2077         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2078         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2079         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2080         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2081         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2082         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2083         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2084         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2085         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2086         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2087         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2088         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2089     }
2090
2091     sampler_8x8_state->dw136.default_sharpness_level = 0;
2092     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2093     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2094     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2095     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2096
2097     /* sampler 8x8 */
2098     dri_bo_map(pp_context->sampler_state_table.bo, True);
2099     assert(pp_context->sampler_state_table.bo->virtual);
2100     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
2101     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2102
2103     /* sample_8x8 Y index 1 */
2104     index = 1;
2105     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2106     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2107     sampler_8x8[index].dw0.ief_bypass = 1;
2108     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2109     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2110     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2111     sampler_8x8[index].dw2.global_noise_estimation = 22;
2112     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2113     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2114     sampler_8x8[index].dw3.strong_edge_weight = 7;
2115     sampler_8x8[index].dw3.regular_weight = 2;
2116     sampler_8x8[index].dw3.non_edge_weight = 0;
2117     sampler_8x8[index].dw3.gain_factor = 40;
2118     sampler_8x8[index].dw4.steepness_boost = 0;
2119     sampler_8x8[index].dw4.steepness_threshold = 0;
2120     sampler_8x8[index].dw4.mr_boost = 0;
2121     sampler_8x8[index].dw4.mr_threshold = 5;
2122     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2123     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2124     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2125     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2126     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2127     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2128     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2129     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2130     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2131     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2132     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2133     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2134     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2135     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2136     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2137     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2138     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2139     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2140     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2141     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2142     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2143     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2144     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2145     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2146     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2147     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2148     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2149     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2150     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2151     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2152     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2153     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2154     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2155     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2156     sampler_8x8[index].dw13.limiter_boost = 0;
2157     sampler_8x8[index].dw13.minimum_limiter = 10;
2158     sampler_8x8[index].dw13.maximum_limiter = 11;
2159     sampler_8x8[index].dw14.clip_limiter = 130;
2160     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2161                       I915_GEM_DOMAIN_RENDER,
2162                       0,
2163                       0,
2164                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2165                       pp_context->sampler_state_table.bo_8x8);
2166
2167     /* sample_8x8 UV index 2 */
2168     index = 2;
2169     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2170     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2171     sampler_8x8[index].dw0.ief_bypass = 1;
2172     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2173     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2174     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2175     sampler_8x8[index].dw2.global_noise_estimation = 22;
2176     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2177     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2178     sampler_8x8[index].dw3.strong_edge_weight = 7;
2179     sampler_8x8[index].dw3.regular_weight = 2;
2180     sampler_8x8[index].dw3.non_edge_weight = 0;
2181     sampler_8x8[index].dw3.gain_factor = 40;
2182     sampler_8x8[index].dw4.steepness_boost = 0;
2183     sampler_8x8[index].dw4.steepness_threshold = 0;
2184     sampler_8x8[index].dw4.mr_boost = 0;
2185     sampler_8x8[index].dw4.mr_threshold = 5;
2186     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2187     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2188     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2189     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2190     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2191     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2192     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2193     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2194     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2195     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2196     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2197     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2198     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2199     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2200     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2201     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2202     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2203     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2204     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2205     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2206     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2207     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2208     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2209     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2210     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2211     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2212     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2213     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2214     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2215     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2216     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2217     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2218     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2219     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2220     sampler_8x8[index].dw13.limiter_boost = 0;
2221     sampler_8x8[index].dw13.minimum_limiter = 10;
2222     sampler_8x8[index].dw13.maximum_limiter = 11;
2223     sampler_8x8[index].dw14.clip_limiter = 130;
2224     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2225                       I915_GEM_DOMAIN_RENDER,
2226                       0,
2227                       0,
2228                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2229                       pp_context->sampler_state_table.bo_8x8);
2230
2231     dri_bo_unmap(pp_context->sampler_state_table.bo);
2232
2233     /* private function & data */
2234     pp_context->pp_x_steps = pp_avs_x_steps;
2235     pp_context->pp_y_steps = pp_avs_y_steps;
2236     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2237
2238     pp_avs_context->dest_x = dst_rect->x;
2239     pp_avs_context->dest_y = dst_rect->y;
2240     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2241     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2242     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2243     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2244     pp_avs_context->src_w = src_rect->width;
2245     pp_avs_context->src_h = src_rect->height;
2246
2247     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2248     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2249
2250     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2251     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2252     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2253     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2254     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2255     pp_inline_parameter->grf6.video_step_delta = 0.0;
2256
2257     dst_surface->flags = src_surface->flags;
2258
2259     return VA_STATUS_SUCCESS;
2260 }
2261
2262 static VAStatus
2263 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2264                             const struct i965_surface *src_surface,
2265                             const VARectangle *src_rect,
2266                             struct i965_surface *dst_surface,
2267                             const VARectangle *dst_rect,
2268                             void *filter_param)
2269 {
2270     return pp_nv12_avs_initialize(ctx, pp_context,
2271                                   src_surface,
2272                                   src_rect,
2273                                   dst_surface,
2274                                   dst_rect,
2275                                   filter_param,
2276                                   1);
2277 }
2278
2279 static VAStatus
2280 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2281                              const struct i965_surface *src_surface,
2282                              const VARectangle *src_rect,
2283                              struct i965_surface *dst_surface,
2284                              const VARectangle *dst_rect,
2285                              void *filter_param)
2286 {
2287     return pp_nv12_avs_initialize(ctx, pp_context,
2288                                   src_surface,
2289                                   src_rect,
2290                                   dst_surface,
2291                                   dst_rect,
2292                                   filter_param,
2293                                   0);
2294 }
2295
2296 static int
2297 gen7_pp_avs_x_steps(void *private_context)
2298 {
2299     struct pp_avs_context *pp_avs_context = private_context;
2300
2301     return pp_avs_context->dest_w / 16;
2302 }
2303
2304 static int
2305 gen7_pp_avs_y_steps(void *private_context)
2306 {
2307     struct pp_avs_context *pp_avs_context = private_context;
2308
2309     return pp_avs_context->dest_h / 16;
2310 }
2311
2312 static int
2313 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2314 {
2315     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2316     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2317
2318     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2319     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2320     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2321     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2322
2323     return 0;
2324 }
2325
2326 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2327                                               struct i965_post_processing_context *pp_context,
2328                                               const struct i965_surface *surface)
2329 {
2330     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2331     int fourcc = pp_get_surface_fourcc(ctx, surface);
2332
2333     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2334         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2335         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2336         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2337     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2338         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2339         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2340         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2341     }
2342 }
2343
2344 static VAStatus
2345 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2346                            const struct i965_surface *src_surface,
2347                            const VARectangle *src_rect,
2348                            struct i965_surface *dst_surface,
2349                            const VARectangle *dst_rect,
2350                            void *filter_param)
2351 {
2352     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2353     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2354     struct gen7_sampler_8x8 *sampler_8x8;
2355     struct i965_sampler_8x8_state *sampler_8x8_state;
2356     int index, i;
2357     int width[3], height[3], pitch[3], offset[3];
2358
2359     /* source surface */
2360     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2361                                          width, height, pitch, offset);
2362
2363     /* destination surface */
2364     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2365                                          width, height, pitch, offset);
2366
2367     /* sampler 8x8 state */
2368     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2369     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2370     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2371     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2372     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2373
2374     for (i = 0; i < 17; i++) {
2375         /* for Y channel, currently ignore */
2376         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2377         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2378         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2379         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2380         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2381         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2382         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2383         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2384         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2385         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2386         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2387         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2388         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2389         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2390         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2391         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2392         /* for U/V channel, 0.25 */
2393         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2394         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2395         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2396         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2397         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2398         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2399         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2400         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2401         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2402         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2403         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2404         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2405         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2406         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2407         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2408         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2409     }
2410
2411     sampler_8x8_state->dw136.default_sharpness_level = 0;
2412     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2413     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2414     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2415     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2416
2417     /* sampler 8x8 */
2418     dri_bo_map(pp_context->sampler_state_table.bo, True);
2419     assert(pp_context->sampler_state_table.bo->virtual);
2420     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2421     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2422
2423     /* sample_8x8 Y index 4 */
2424     index = 4;
2425     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2426     sampler_8x8[index].dw0.global_noise_estimation = 255;
2427     sampler_8x8[index].dw0.ief_bypass = 1;
2428
2429     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2430
2431     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2432     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2433     sampler_8x8[index].dw2.r5x_coefficient = 9;
2434     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2435     sampler_8x8[index].dw2.r5c_coefficient = 3;
2436
2437     sampler_8x8[index].dw3.r3x_coefficient = 27;
2438     sampler_8x8[index].dw3.r3c_coefficient = 5;
2439     sampler_8x8[index].dw3.gain_factor = 40;
2440     sampler_8x8[index].dw3.non_edge_weight = 1;
2441     sampler_8x8[index].dw3.regular_weight = 2;
2442     sampler_8x8[index].dw3.strong_edge_weight = 7;
2443     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2444
2445     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2446                       I915_GEM_DOMAIN_RENDER,
2447                       0,
2448                       0,
2449                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2450                       pp_context->sampler_state_table.bo_8x8);
2451
2452     /* sample_8x8 UV index 8 */
2453     index = 8;
2454     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2455     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2456     sampler_8x8[index].dw0.global_noise_estimation = 255;
2457     sampler_8x8[index].dw0.ief_bypass = 1;
2458     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2459     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2460     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2461     sampler_8x8[index].dw2.r5x_coefficient = 9;
2462     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2463     sampler_8x8[index].dw2.r5c_coefficient = 3;
2464     sampler_8x8[index].dw3.r3x_coefficient = 27;
2465     sampler_8x8[index].dw3.r3c_coefficient = 5;
2466     sampler_8x8[index].dw3.gain_factor = 40;
2467     sampler_8x8[index].dw3.non_edge_weight = 1;
2468     sampler_8x8[index].dw3.regular_weight = 2;
2469     sampler_8x8[index].dw3.strong_edge_weight = 7;
2470     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2471
2472     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2473                       I915_GEM_DOMAIN_RENDER,
2474                       0,
2475                       0,
2476                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2477                       pp_context->sampler_state_table.bo_8x8);
2478
2479     /* sampler_8x8 V, index 12 */
2480     index = 12;
2481     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2482     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2483     sampler_8x8[index].dw0.global_noise_estimation = 255;
2484     sampler_8x8[index].dw0.ief_bypass = 1;
2485     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2486     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2487     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2488     sampler_8x8[index].dw2.r5x_coefficient = 9;
2489     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2490     sampler_8x8[index].dw2.r5c_coefficient = 3;
2491     sampler_8x8[index].dw3.r3x_coefficient = 27;
2492     sampler_8x8[index].dw3.r3c_coefficient = 5;
2493     sampler_8x8[index].dw3.gain_factor = 40;
2494     sampler_8x8[index].dw3.non_edge_weight = 1;
2495     sampler_8x8[index].dw3.regular_weight = 2;
2496     sampler_8x8[index].dw3.strong_edge_weight = 7;
2497     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2498
2499     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2500                       I915_GEM_DOMAIN_RENDER,
2501                       0,
2502                       0,
2503                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2504                       pp_context->sampler_state_table.bo_8x8);
2505
2506     dri_bo_unmap(pp_context->sampler_state_table.bo);
2507
2508     /* private function & data */
2509     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2510     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2511     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2512
2513     pp_avs_context->dest_x = dst_rect->x;
2514     pp_avs_context->dest_y = dst_rect->y;
2515     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2516     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2517     pp_avs_context->src_w = src_rect->width;
2518     pp_avs_context->src_h = src_rect->height;
2519
2520     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2521     dw = MAX(dw, pp_avs_context->dest_w);
2522
2523     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2524     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2525     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2526     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2527     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2528
2529     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2530
2531     dst_surface->flags = src_surface->flags;
2532
2533     return VA_STATUS_SUCCESS;
2534 }
2535
2536 static int
2537 pp_dndi_x_steps(void *private_context)
2538 {
2539     return 1;
2540 }
2541
2542 static int
2543 pp_dndi_y_steps(void *private_context)
2544 {
2545     struct pp_dndi_context *pp_dndi_context = private_context;
2546
2547     return pp_dndi_context->dest_h / 4;
2548 }
2549
2550 static int
2551 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2552 {
2553     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2554
2555     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2556     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2557
2558     return 0;
2559 }
2560
2561 static VAStatus
2562 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2563                         const struct i965_surface *src_surface,
2564                         const VARectangle *src_rect,
2565                         struct i965_surface *dst_surface,
2566                         const VARectangle *dst_rect,
2567                         void *filter_param)
2568 {
2569     struct i965_driver_data *i965 = i965_driver_data(ctx);
2570     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2571     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2572     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2573     struct object_surface *obj_surface;
2574     struct i965_sampler_dndi *sampler_dndi;
2575     int index;
2576     int w, h;
2577     int orig_w, orig_h;
2578     int dndi_top_first = 1;
2579
2580     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2581         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2582
2583     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2584         dndi_top_first = 1;
2585     else
2586         dndi_top_first = 0;
2587
2588     /* surface */
2589     obj_surface = SURFACE(src_surface->id);
2590     orig_w = obj_surface->orig_width;
2591     orig_h = obj_surface->orig_height;
2592     w = obj_surface->width;
2593     h = obj_surface->height;
2594
2595     if (pp_context->stmm.bo == NULL) {
2596         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2597                                            "STMM surface",
2598                                            w * h,
2599                                            4096);
2600         assert(pp_context->stmm.bo);
2601     }
2602
2603     /* source UV surface index 2 */
2604     i965_pp_set_surface_state(ctx, pp_context,
2605                               obj_surface->bo, w * h,
2606                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2607                               2, 0);
2608
2609     /* source YUV surface index 4 */
2610     i965_pp_set_surface2_state(ctx, pp_context,
2611                                obj_surface->bo, 0,
2612                                orig_w, orig_h, w,
2613                                0, h,
2614                                SURFACE_FORMAT_PLANAR_420_8, 1,
2615                                4);
2616
2617     /* source STMM surface index 20 */
2618     i965_pp_set_surface_state(ctx, pp_context,
2619                               pp_context->stmm.bo, 0,
2620                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2621                               20, 1);
2622
2623     /* destination surface */
2624     obj_surface = SURFACE(dst_surface->id);
2625     orig_w = obj_surface->orig_width;
2626     orig_h = obj_surface->orig_height;
2627     w = obj_surface->width;
2628     h = obj_surface->height;
2629
2630     /* destination Y surface index 7 */
2631     i965_pp_set_surface_state(ctx, pp_context,
2632                               obj_surface->bo, 0,
2633                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2634                               7, 1);
2635
2636     /* destination UV surface index 8 */
2637     i965_pp_set_surface_state(ctx, pp_context,
2638                               obj_surface->bo, w * h,
2639                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2640                               8, 1);
2641     /* sampler dndi */
2642     dri_bo_map(pp_context->sampler_state_table.bo, True);
2643     assert(pp_context->sampler_state_table.bo->virtual);
2644     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2645     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2646
2647     /* sample dndi index 1 */
2648     index = 0;
2649     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2650     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2651     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2652     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2653
2654     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2655     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2656     sampler_dndi[index].dw1.stmm_c2 = 1;
2657     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2658     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2659
2660     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2661     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2662     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2663     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2664
2665     sampler_dndi[index].dw3.maximum_stmm = 128;
2666     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2667     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2668     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2669     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2670
2671     sampler_dndi[index].dw4.sdi_delta = 8;
2672     sampler_dndi[index].dw4.sdi_threshold = 128;
2673     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2674     sampler_dndi[index].dw4.stmm_shift_up = 0;
2675     sampler_dndi[index].dw4.stmm_shift_down = 0;
2676     sampler_dndi[index].dw4.minimum_stmm = 0;
2677
2678     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2679     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2680     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2681     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2682
2683     sampler_dndi[index].dw6.dn_enable = 1;
2684     sampler_dndi[index].dw6.di_enable = 1;
2685     sampler_dndi[index].dw6.di_partial = 0;
2686     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2687     sampler_dndi[index].dw6.dndi_stream_id = 0;
2688     sampler_dndi[index].dw6.dndi_first_frame = 1;
2689     sampler_dndi[index].dw6.progressive_dn = 0;
2690     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2691     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2692     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2693
2694     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2695     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2696     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2697     sampler_dndi[index].dw7.column_width_minus1 = 0;
2698
2699     dri_bo_unmap(pp_context->sampler_state_table.bo);
2700
2701     /* private function & data */
2702     pp_context->pp_x_steps = pp_dndi_x_steps;
2703     pp_context->pp_y_steps = pp_dndi_y_steps;
2704     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2705
2706     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2707     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2708     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2709     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2710
2711     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2712     pp_inline_parameter->grf5.number_blocks = w / 16;
2713     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2714     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2715
2716     pp_dndi_context->dest_w = w;
2717     pp_dndi_context->dest_h = h;
2718
2719     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2720
2721     return VA_STATUS_SUCCESS;
2722 }
2723
2724 static int
2725 pp_dn_x_steps(void *private_context)
2726 {
2727     return 1;
2728 }
2729
2730 static int
2731 pp_dn_y_steps(void *private_context)
2732 {
2733     struct pp_dn_context *pp_dn_context = private_context;
2734
2735     return pp_dn_context->dest_h / 8;
2736 }
2737
2738 static int
2739 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2740 {
2741     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2742
2743     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2744     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2745
2746     return 0;
2747 }
2748
2749 static VAStatus
2750 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2751                       const struct i965_surface *src_surface,
2752                       const VARectangle *src_rect,
2753                       struct i965_surface *dst_surface,
2754                       const VARectangle *dst_rect,
2755                       void *filter_param)
2756 {
2757     struct i965_driver_data *i965 = i965_driver_data(ctx);
2758     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2759     struct object_surface *obj_surface;
2760     struct i965_sampler_dndi *sampler_dndi;
2761     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2762     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2763     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2764     int index;
2765     int w, h;
2766     int orig_w, orig_h;
2767     int dn_strength = 15;
2768     int dndi_top_first = 1;
2769     int dn_progressive = 0;
2770
2771     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2772         dndi_top_first = 1;
2773         dn_progressive = 1;
2774     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2775         dndi_top_first = 1;
2776         dn_progressive = 0;
2777     } else {
2778         dndi_top_first = 0;
2779         dn_progressive = 0;
2780     }
2781
2782     if (dn_filter_param) {
2783         float value = dn_filter_param->value;
2784
2785         if (value > 1.0)
2786             value = 1.0;
2787
2788         if (value < 0.0)
2789             value = 0.0;
2790
2791         dn_strength = (int)(value * 31.0F);
2792     }
2793
2794     /* surface */
2795     obj_surface = SURFACE(src_surface->id);
2796     orig_w = obj_surface->orig_width;
2797     orig_h = obj_surface->orig_height;
2798     w = obj_surface->width;
2799     h = obj_surface->height;
2800
2801     if (pp_context->stmm.bo == NULL) {
2802         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2803                                            "STMM surface",
2804                                            w * h,
2805                                            4096);
2806         assert(pp_context->stmm.bo);
2807     }
2808
2809     /* source UV surface index 2 */
2810     i965_pp_set_surface_state(ctx, pp_context,
2811                               obj_surface->bo, w * h,
2812                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2813                               2, 0);
2814
2815     /* source YUV surface index 4 */
2816     i965_pp_set_surface2_state(ctx, pp_context,
2817                                obj_surface->bo, 0,
2818                                orig_w, orig_h, w,
2819                                0, h,
2820                                SURFACE_FORMAT_PLANAR_420_8, 1,
2821                                4);
2822
2823     /* source STMM surface index 20 */
2824     i965_pp_set_surface_state(ctx, pp_context,
2825                               pp_context->stmm.bo, 0,
2826                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2827                               20, 1);
2828
2829     /* destination surface */
2830     obj_surface = SURFACE(dst_surface->id);
2831     orig_w = obj_surface->orig_width;
2832     orig_h = obj_surface->orig_height;
2833     w = obj_surface->width;
2834     h = obj_surface->height;
2835
2836     /* destination Y surface index 7 */
2837     i965_pp_set_surface_state(ctx, pp_context,
2838                               obj_surface->bo, 0,
2839                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2840                               7, 1);
2841
2842     /* destination UV surface index 8 */
2843     i965_pp_set_surface_state(ctx, pp_context,
2844                               obj_surface->bo, w * h,
2845                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2846                               8, 1);
2847     /* sampler dn */
2848     dri_bo_map(pp_context->sampler_state_table.bo, True);
2849     assert(pp_context->sampler_state_table.bo->virtual);
2850     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2851     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2852
2853     /* sample dndi index 1 */
2854     index = 0;
2855     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2856     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2857     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2858     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2859
2860     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2861     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2862     sampler_dndi[index].dw1.stmm_c2 = 0;
2863     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2864     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2865
2866     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2867     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2868     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2869     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2870
2871     sampler_dndi[index].dw3.maximum_stmm = 128;
2872     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2873     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2874     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2875     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2876
2877     sampler_dndi[index].dw4.sdi_delta = 8;
2878     sampler_dndi[index].dw4.sdi_threshold = 128;
2879     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2880     sampler_dndi[index].dw4.stmm_shift_up = 0;
2881     sampler_dndi[index].dw4.stmm_shift_down = 0;
2882     sampler_dndi[index].dw4.minimum_stmm = 0;
2883
2884     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2885     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2886     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2887     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2888
2889     sampler_dndi[index].dw6.dn_enable = 1;
2890     sampler_dndi[index].dw6.di_enable = 0;
2891     sampler_dndi[index].dw6.di_partial = 0;
2892     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2893     sampler_dndi[index].dw6.dndi_stream_id = 1;
2894     sampler_dndi[index].dw6.dndi_first_frame = 1;
2895     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2896     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2897     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2898     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2899
2900     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2901     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2902     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2903     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2904
2905     dri_bo_unmap(pp_context->sampler_state_table.bo);
2906
2907     /* private function & data */
2908     pp_context->pp_x_steps = pp_dn_x_steps;
2909     pp_context->pp_y_steps = pp_dn_y_steps;
2910     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2911
2912     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2913     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2914     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2915     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2916
2917     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2918     pp_inline_parameter->grf5.number_blocks = w / 16;
2919     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2920     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2921
2922     pp_dn_context->dest_w = w;
2923     pp_dn_context->dest_h = h;
2924
2925     dst_surface->flags = src_surface->flags;
2926
2927     return VA_STATUS_SUCCESS;
2928 }
2929
2930 static int
2931 gen7_pp_dndi_x_steps(void *private_context)
2932 {
2933     struct pp_dndi_context *pp_dndi_context = private_context;
2934
2935     return pp_dndi_context->dest_w / 16;
2936 }
2937
2938 static int
2939 gen7_pp_dndi_y_steps(void *private_context)
2940 {
2941     struct pp_dndi_context *pp_dndi_context = private_context;
2942
2943     return pp_dndi_context->dest_h / 4;
2944 }
2945
2946 static int
2947 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2948 {
2949     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2950
2951     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2952     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2953
2954     return 0;
2955 }
2956
2957 static VAStatus
2958 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2959                              const struct i965_surface *src_surface,
2960                              const VARectangle *src_rect,
2961                              struct i965_surface *dst_surface,
2962                              const VARectangle *dst_rect,
2963                              void *filter_param)
2964 {
2965     struct i965_driver_data *i965 = i965_driver_data(ctx);
2966     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2967     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2968     struct object_surface *obj_surface;
2969     struct gen7_sampler_dndi *sampler_dndi;
2970     int index;
2971     int w, h;
2972     int orig_w, orig_h;
2973     int dndi_top_first = 1;
2974
2975     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2976         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2977
2978     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2979         dndi_top_first = 1;
2980     else
2981         dndi_top_first = 0;
2982
2983     /* surface */
2984     obj_surface = SURFACE(src_surface->id);
2985     orig_w = obj_surface->orig_width;
2986     orig_h = obj_surface->orig_height;
2987     w = obj_surface->width;
2988     h = obj_surface->height;
2989
2990     if (pp_context->stmm.bo == NULL) {
2991         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2992                                            "STMM surface",
2993                                            w * h,
2994                                            4096);
2995         assert(pp_context->stmm.bo);
2996     }
2997
2998     /* source UV surface index 1 */
2999     gen7_pp_set_surface_state(ctx, pp_context,
3000                               obj_surface->bo, w * h,
3001                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3002                               1, 0);
3003
3004     /* source YUV surface index 3 */
3005     gen7_pp_set_surface2_state(ctx, pp_context,
3006                                obj_surface->bo, 0,
3007                                orig_w, orig_h, w,
3008                                0, h,
3009                                SURFACE_FORMAT_PLANAR_420_8, 1,
3010                                3);
3011
3012     /* source (temporal reference) YUV surface index 4 */
3013     gen7_pp_set_surface2_state(ctx, pp_context,
3014                                obj_surface->bo, 0,
3015                                orig_w, orig_h, w,
3016                                0, h,
3017                                SURFACE_FORMAT_PLANAR_420_8, 1,
3018                                4);
3019
3020     /* STMM / History Statistics input surface, index 5 */
3021     gen7_pp_set_surface_state(ctx, pp_context,
3022                               pp_context->stmm.bo, 0,
3023                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3024                               5, 1);
3025
3026     /* destination surface */
3027     obj_surface = SURFACE(dst_surface->id);
3028     orig_w = obj_surface->orig_width;
3029     orig_h = obj_surface->orig_height;
3030     w = obj_surface->width;
3031     h = obj_surface->height;
3032
3033     /* destination(Previous frame) Y surface index 27 */
3034     gen7_pp_set_surface_state(ctx, pp_context,
3035                               obj_surface->bo, 0,
3036                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3037                               27, 1);
3038
3039     /* destination(Previous frame) UV surface index 28 */
3040     gen7_pp_set_surface_state(ctx, pp_context,
3041                               obj_surface->bo, w * h,
3042                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3043                               28, 1);
3044
3045     /* destination(Current frame) Y surface index 30 */
3046     gen7_pp_set_surface_state(ctx, pp_context,
3047                               obj_surface->bo, 0,
3048                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3049                               30, 1);
3050
3051     /* destination(Current frame) UV surface index 31 */
3052     gen7_pp_set_surface_state(ctx, pp_context,
3053                               obj_surface->bo, w * h,
3054                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3055                               31, 1);
3056
3057     /* STMM output surface, index 33 */
3058     gen7_pp_set_surface_state(ctx, pp_context,
3059                               pp_context->stmm.bo, 0,
3060                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3061                               33, 1);
3062
3063
3064     /* sampler dndi */
3065     dri_bo_map(pp_context->sampler_state_table.bo, True);
3066     assert(pp_context->sampler_state_table.bo->virtual);
3067     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
3068     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
3069
3070     /* sample dndi index 0 */
3071     index = 0;
3072     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
3073     sampler_dndi[index].dw0.dnmh_delt = 8;
3074     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
3075     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
3076     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
3077     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
3078
3079     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3080     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
3081     sampler_dndi[index].dw1.stmm_c2 = 0;
3082     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
3083     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
3084
3085     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
3086     sampler_dndi[index].dw2.bne_edge_th = 1;
3087     sampler_dndi[index].dw2.smooth_mv_th = 0;
3088     sampler_dndi[index].dw2.sad_tight_th = 5;
3089     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
3090     sampler_dndi[index].dw2.good_neighbor_th = 4;
3091
3092     sampler_dndi[index].dw3.maximum_stmm = 128;
3093     sampler_dndi[index].dw3.multipler_for_vecm = 2;
3094     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3095     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3096     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
3097
3098     sampler_dndi[index].dw4.sdi_delta = 8;
3099     sampler_dndi[index].dw4.sdi_threshold = 128;
3100     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3101     sampler_dndi[index].dw4.stmm_shift_up = 0;
3102     sampler_dndi[index].dw4.stmm_shift_down = 0;
3103     sampler_dndi[index].dw4.minimum_stmm = 0;
3104
3105     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
3106     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
3107     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3108     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3109
3110     sampler_dndi[index].dw6.dn_enable = 0;
3111     sampler_dndi[index].dw6.di_enable = 1;
3112     sampler_dndi[index].dw6.di_partial = 0;
3113     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
3114     sampler_dndi[index].dw6.dndi_stream_id = 1;
3115     sampler_dndi[index].dw6.dndi_first_frame = 1;
3116     sampler_dndi[index].dw6.progressive_dn = 0;
3117     sampler_dndi[index].dw6.mcdi_enable = 0;
3118     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3119     sampler_dndi[index].dw6.cat_th1 = 0;
3120     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3121     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3122
3123     sampler_dndi[index].dw7.sad_tha = 5;
3124     sampler_dndi[index].dw7.sad_thb = 10;
3125     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3126     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3127     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3128     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3129     sampler_dndi[index].dw7.neighborpixel_th = 10;
3130     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3131
3132     dri_bo_unmap(pp_context->sampler_state_table.bo);
3133
3134     /* private function & data */
3135     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3136     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3137     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3138
3139     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3140     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3141     pp_static_parameter->grf1.di_top_field_first = 0;
3142     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3143
3144     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3145     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3146     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3147
3148     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3149     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3150
3151     pp_dndi_context->dest_w = w;
3152     pp_dndi_context->dest_h = h;
3153
3154     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3155
3156     return VA_STATUS_SUCCESS;
3157 }
3158
3159 static int
3160 gen7_pp_dn_x_steps(void *private_context)
3161 {
3162     return 1;
3163 }
3164
3165 static int
3166 gen7_pp_dn_y_steps(void *private_context)
3167 {
3168     struct pp_dn_context *pp_dn_context = private_context;
3169
3170     return pp_dn_context->dest_h / 4;
3171 }
3172
3173 static int
3174 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3175 {
3176     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3177
3178     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3179     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3180
3181     return 0;
3182 }
3183
3184 static VAStatus
3185 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3186                            const struct i965_surface *src_surface,
3187                            const VARectangle *src_rect,
3188                            struct i965_surface *dst_surface,
3189                            const VARectangle *dst_rect,
3190                            void *filter_param)
3191 {
3192     struct i965_driver_data *i965 = i965_driver_data(ctx);
3193     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3194     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3195     struct object_surface *obj_surface;
3196     struct gen7_sampler_dndi *sampler_dn;
3197     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3198     int index;
3199     int w, h;
3200     int orig_w, orig_h;
3201     int dn_strength = 15;
3202     int dndi_top_first = 1;
3203     int dn_progressive = 0;
3204
3205     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3206         dndi_top_first = 1;
3207         dn_progressive = 1;
3208     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3209         dndi_top_first = 1;
3210         dn_progressive = 0;
3211     } else {
3212         dndi_top_first = 0;
3213         dn_progressive = 0;
3214     }
3215
3216     if (dn_filter_param) {
3217         float value = dn_filter_param->value;
3218
3219         if (value > 1.0)
3220             value = 1.0;
3221
3222         if (value < 0.0)
3223             value = 0.0;
3224
3225         dn_strength = (int)(value * 31.0F);
3226     }
3227
3228     /* surface */
3229     obj_surface = SURFACE(src_surface->id);
3230     orig_w = obj_surface->orig_width;
3231     orig_h = obj_surface->orig_height;
3232     w = obj_surface->width;
3233     h = obj_surface->height;
3234
3235     if (pp_context->stmm.bo == NULL) {
3236         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3237                                            "STMM surface",
3238                                            w * h,
3239                                            4096);
3240         assert(pp_context->stmm.bo);
3241     }
3242
3243     /* source UV surface index 1 */
3244     gen7_pp_set_surface_state(ctx, pp_context,
3245                               obj_surface->bo, w * h,
3246                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3247                               1, 0);
3248
3249     /* source YUV surface index 3 */
3250     gen7_pp_set_surface2_state(ctx, pp_context,
3251                                obj_surface->bo, 0,
3252                                orig_w, orig_h, w,
3253                                0, h,
3254                                SURFACE_FORMAT_PLANAR_420_8, 1,
3255                                3);
3256
3257     /* source STMM surface index 5 */
3258     gen7_pp_set_surface_state(ctx, pp_context,
3259                               pp_context->stmm.bo, 0,
3260                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3261                               5, 1);
3262
3263     /* destination surface */
3264     obj_surface = SURFACE(dst_surface->id);
3265     orig_w = obj_surface->orig_width;
3266     orig_h = obj_surface->orig_height;
3267     w = obj_surface->width;
3268     h = obj_surface->height;
3269
3270     /* destination Y surface index 7 */
3271     gen7_pp_set_surface_state(ctx, pp_context,
3272                               obj_surface->bo, 0,
3273                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3274                               7, 1);
3275
3276     /* destination UV surface index 8 */
3277     gen7_pp_set_surface_state(ctx, pp_context,
3278                               obj_surface->bo, w * h,
3279                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3280                               8, 1);
3281     /* sampler dn */
3282     dri_bo_map(pp_context->sampler_state_table.bo, True);
3283     assert(pp_context->sampler_state_table.bo->virtual);
3284     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3285     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3286
3287     /* sample dn index 1 */
3288     index = 0;
3289     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3290     sampler_dn[index].dw0.dnmh_delt = 8;
3291     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3292     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3293     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3294     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3295
3296     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3297     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3298     sampler_dn[index].dw1.stmm_c2 = 0;
3299     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3300     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3301
3302     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3303     sampler_dn[index].dw2.bne_edge_th = 1;
3304     sampler_dn[index].dw2.smooth_mv_th = 0;
3305     sampler_dn[index].dw2.sad_tight_th = 5;
3306     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3307     sampler_dn[index].dw2.good_neighbor_th = 4;
3308
3309     sampler_dn[index].dw3.maximum_stmm = 128;
3310     sampler_dn[index].dw3.multipler_for_vecm = 2;
3311     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3312     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3313     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3314
3315     sampler_dn[index].dw4.sdi_delta = 8;
3316     sampler_dn[index].dw4.sdi_threshold = 128;
3317     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3318     sampler_dn[index].dw4.stmm_shift_up = 0;
3319     sampler_dn[index].dw4.stmm_shift_down = 0;
3320     sampler_dn[index].dw4.minimum_stmm = 0;
3321
3322     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3323     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3324     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3325     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3326
3327     sampler_dn[index].dw6.dn_enable = 1;
3328     sampler_dn[index].dw6.di_enable = 0;
3329     sampler_dn[index].dw6.di_partial = 0;
3330     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3331     sampler_dn[index].dw6.dndi_stream_id = 1;
3332     sampler_dn[index].dw6.dndi_first_frame = 1;
3333     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3334     sampler_dn[index].dw6.mcdi_enable = 0;
3335     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3336     sampler_dn[index].dw6.cat_th1 = 0;
3337     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3338     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3339
3340     sampler_dn[index].dw7.sad_tha = 5;
3341     sampler_dn[index].dw7.sad_thb = 10;
3342     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3343     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3344     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3345     sampler_dn[index].dw7.vdi_walker_enable = 0;
3346     sampler_dn[index].dw7.neighborpixel_th = 10;
3347     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3348
3349     dri_bo_unmap(pp_context->sampler_state_table.bo);
3350
3351     /* private function & data */
3352     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3353     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3354     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3355
3356     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3357     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3358     pp_static_parameter->grf1.di_top_field_first = 0;
3359     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3360
3361     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3362     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3363     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3364
3365     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3366     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3367
3368     pp_dn_context->dest_w = w;
3369     pp_dn_context->dest_h = h;
3370
3371     dst_surface->flags = src_surface->flags;
3372
3373     return VA_STATUS_SUCCESS;
3374 }
3375
3376 static VAStatus
3377 ironlake_pp_initialize(
3378     VADriverContextP   ctx,
3379     struct i965_post_processing_context *pp_context,
3380     const struct i965_surface *src_surface,
3381     const VARectangle *src_rect,
3382     struct i965_surface *dst_surface,
3383     const VARectangle *dst_rect,
3384     int                pp_index,
3385     void *filter_param
3386 )
3387 {
3388     VAStatus va_status;
3389     struct i965_driver_data *i965 = i965_driver_data(ctx);
3390     struct pp_module *pp_module;
3391     dri_bo *bo;
3392     int static_param_size, inline_param_size;
3393
3394     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3395     bo = dri_bo_alloc(i965->intel.bufmgr,
3396                       "surface state & binding table",
3397                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3398                       4096);
3399     assert(bo);
3400     pp_context->surface_state_binding_table.bo = bo;
3401
3402     dri_bo_unreference(pp_context->curbe.bo);
3403     bo = dri_bo_alloc(i965->intel.bufmgr,
3404                       "constant buffer",
3405                       4096,
3406                       4096);
3407     assert(bo);
3408     pp_context->curbe.bo = bo;
3409
3410     dri_bo_unreference(pp_context->idrt.bo);
3411     bo = dri_bo_alloc(i965->intel.bufmgr,
3412                       "interface discriptor",
3413                       sizeof(struct i965_interface_descriptor),
3414                       4096);
3415     assert(bo);
3416     pp_context->idrt.bo = bo;
3417     pp_context->idrt.num_interface_descriptors = 0;
3418
3419     dri_bo_unreference(pp_context->sampler_state_table.bo);
3420     bo = dri_bo_alloc(i965->intel.bufmgr,
3421                       "sampler state table",
3422                       4096,
3423                       4096);
3424     assert(bo);
3425     dri_bo_map(bo, True);
3426     memset(bo->virtual, 0, bo->size);
3427     dri_bo_unmap(bo);
3428     pp_context->sampler_state_table.bo = bo;
3429
3430     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3431     bo = dri_bo_alloc(i965->intel.bufmgr,
3432                       "sampler 8x8 state ",
3433                       4096,
3434                       4096);
3435     assert(bo);
3436     pp_context->sampler_state_table.bo_8x8 = bo;
3437
3438     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3439     bo = dri_bo_alloc(i965->intel.bufmgr,
3440                       "sampler 8x8 state ",
3441                       4096,
3442                       4096);
3443     assert(bo);
3444     pp_context->sampler_state_table.bo_8x8_uv = bo;
3445
3446     dri_bo_unreference(pp_context->vfe_state.bo);
3447     bo = dri_bo_alloc(i965->intel.bufmgr,
3448                       "vfe state",
3449                       sizeof(struct i965_vfe_state),
3450                       4096);
3451     assert(bo);
3452     pp_context->vfe_state.bo = bo;
3453
3454     static_param_size = sizeof(struct pp_static_parameter);
3455     inline_param_size = sizeof(struct pp_inline_parameter);
3456
3457     memset(pp_context->pp_static_parameter, 0, static_param_size);
3458     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3459
3460     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3461     pp_context->current_pp = pp_index;
3462     pp_module = &pp_context->pp_modules[pp_index];
3463
3464     if (pp_module->initialize)
3465         va_status = pp_module->initialize(ctx, pp_context,
3466                                           src_surface,
3467                                           src_rect,
3468                                           dst_surface,
3469                                           dst_rect,
3470                                           filter_param);
3471     else
3472         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3473
3474     return va_status;
3475 }
3476
3477 static VAStatus
3478 ironlake_post_processing(
3479     VADriverContextP   ctx,
3480     struct i965_post_processing_context *pp_context,
3481     const struct i965_surface *src_surface,
3482     const VARectangle *src_rect,
3483     struct i965_surface *dst_surface,
3484     const VARectangle *dst_rect,
3485     int                pp_index,
3486     void *filter_param
3487 )
3488 {
3489     VAStatus va_status;
3490
3491     va_status = ironlake_pp_initialize(ctx, pp_context,
3492                                        src_surface,
3493                                        src_rect,
3494                                        dst_surface,
3495                                        dst_rect,
3496                                        pp_index,
3497                                        filter_param);
3498
3499     if (va_status == VA_STATUS_SUCCESS) {
3500         ironlake_pp_states_setup(ctx, pp_context);
3501         ironlake_pp_pipeline_setup(ctx, pp_context);
3502     }
3503
3504     return va_status;
3505 }
3506
3507 static VAStatus
3508 gen6_pp_initialize(
3509     VADriverContextP   ctx,
3510     struct i965_post_processing_context *pp_context,
3511     const struct i965_surface *src_surface,
3512     const VARectangle *src_rect,
3513     struct i965_surface *dst_surface,
3514     const VARectangle *dst_rect,
3515     int                pp_index,
3516     void *filter_param
3517 )
3518 {
3519     VAStatus va_status;
3520     struct i965_driver_data *i965 = i965_driver_data(ctx);
3521     struct pp_module *pp_module;
3522     dri_bo *bo;
3523     int static_param_size, inline_param_size;
3524
3525     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3526     bo = dri_bo_alloc(i965->intel.bufmgr,
3527                       "surface state & binding table",
3528                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3529                       4096);
3530     assert(bo);
3531     pp_context->surface_state_binding_table.bo = bo;
3532
3533     dri_bo_unreference(pp_context->curbe.bo);
3534     bo = dri_bo_alloc(i965->intel.bufmgr,
3535                       "constant buffer",
3536                       4096,
3537                       4096);
3538     assert(bo);
3539     pp_context->curbe.bo = bo;
3540
3541     dri_bo_unreference(pp_context->idrt.bo);
3542     bo = dri_bo_alloc(i965->intel.bufmgr,
3543                       "interface discriptor",
3544                       sizeof(struct gen6_interface_descriptor_data),
3545                       4096);
3546     assert(bo);
3547     pp_context->idrt.bo = bo;
3548     pp_context->idrt.num_interface_descriptors = 0;
3549
3550     dri_bo_unreference(pp_context->sampler_state_table.bo);
3551     bo = dri_bo_alloc(i965->intel.bufmgr,
3552                       "sampler state table",
3553                       4096,
3554                       4096);
3555     assert(bo);
3556     dri_bo_map(bo, True);
3557     memset(bo->virtual, 0, bo->size);
3558     dri_bo_unmap(bo);
3559     pp_context->sampler_state_table.bo = bo;
3560
3561     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3562     bo = dri_bo_alloc(i965->intel.bufmgr,
3563                       "sampler 8x8 state ",
3564                       4096,
3565                       4096);
3566     assert(bo);
3567     pp_context->sampler_state_table.bo_8x8 = bo;
3568
3569     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3570     bo = dri_bo_alloc(i965->intel.bufmgr,
3571                       "sampler 8x8 state ",
3572                       4096,
3573                       4096);
3574     assert(bo);
3575     pp_context->sampler_state_table.bo_8x8_uv = bo;
3576
3577     dri_bo_unreference(pp_context->vfe_state.bo);
3578     bo = dri_bo_alloc(i965->intel.bufmgr,
3579                       "vfe state",
3580                       sizeof(struct i965_vfe_state),
3581                       4096);
3582     assert(bo);
3583     pp_context->vfe_state.bo = bo;
3584
3585     if (IS_GEN7(i965->intel.device_id)) {
3586         static_param_size = sizeof(struct gen7_pp_static_parameter);
3587         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3588     } else {
3589         static_param_size = sizeof(struct pp_static_parameter);
3590         inline_param_size = sizeof(struct pp_inline_parameter);
3591     }
3592
3593     memset(pp_context->pp_static_parameter, 0, static_param_size);
3594     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3595
3596     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3597     pp_context->current_pp = pp_index;
3598     pp_module = &pp_context->pp_modules[pp_index];
3599
3600     if (pp_module->initialize)
3601         va_status = pp_module->initialize(ctx, pp_context,
3602                                           src_surface,
3603                                           src_rect,
3604                                           dst_surface,
3605                                           dst_rect,
3606                                           filter_param);
3607     else
3608         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3609
3610     return va_status;
3611 }
3612
3613 static void
3614 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3615                                    struct i965_post_processing_context *pp_context)
3616 {
3617     struct i965_driver_data *i965 = i965_driver_data(ctx);
3618     struct gen6_interface_descriptor_data *desc;
3619     dri_bo *bo;
3620     int pp_index = pp_context->current_pp;
3621
3622     bo = pp_context->idrt.bo;
3623     dri_bo_map(bo, True);
3624     assert(bo->virtual);
3625     desc = bo->virtual;
3626     memset(desc, 0, sizeof(*desc));
3627     desc->desc0.kernel_start_pointer =
3628         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3629     desc->desc1.single_program_flow = 1;
3630     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3631     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3632     desc->desc2.sampler_state_pointer =
3633         pp_context->sampler_state_table.bo->offset >> 5;
3634     desc->desc3.binding_table_entry_count = 0;
3635     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3636     desc->desc4.constant_urb_entry_read_offset = 0;
3637
3638     if (IS_GEN7(i965->intel.device_id))
3639         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3640     else
3641         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3642
3643     dri_bo_emit_reloc(bo,
3644                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3645                       0,
3646                       offsetof(struct gen6_interface_descriptor_data, desc0),
3647                       pp_context->pp_modules[pp_index].kernel.bo);
3648
3649     dri_bo_emit_reloc(bo,
3650                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3651                       desc->desc2.sampler_count << 2,
3652                       offsetof(struct gen6_interface_descriptor_data, desc2),
3653                       pp_context->sampler_state_table.bo);
3654
3655     dri_bo_unmap(bo);
3656     pp_context->idrt.num_interface_descriptors++;
3657 }
3658
3659 static void
3660 gen6_pp_upload_constants(VADriverContextP ctx,
3661                          struct i965_post_processing_context *pp_context)
3662 {
3663     struct i965_driver_data *i965 = i965_driver_data(ctx);
3664     unsigned char *constant_buffer;
3665     int param_size;
3666
3667     assert(sizeof(struct pp_static_parameter) == 128);
3668     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3669
3670     if (IS_GEN7(i965->intel.device_id))
3671         param_size = sizeof(struct gen7_pp_static_parameter);
3672     else
3673         param_size = sizeof(struct pp_static_parameter);
3674
3675     dri_bo_map(pp_context->curbe.bo, 1);
3676     assert(pp_context->curbe.bo->virtual);
3677     constant_buffer = pp_context->curbe.bo->virtual;
3678     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3679     dri_bo_unmap(pp_context->curbe.bo);
3680 }
3681
3682 static void
3683 gen6_pp_states_setup(VADriverContextP ctx,
3684                      struct i965_post_processing_context *pp_context)
3685 {
3686     gen6_pp_interface_descriptor_table(ctx, pp_context);
3687     gen6_pp_upload_constants(ctx, pp_context);
3688 }
3689
3690 static void
3691 gen6_pp_pipeline_select(VADriverContextP ctx,
3692                         struct i965_post_processing_context *pp_context)
3693 {
3694     struct intel_batchbuffer *batch = pp_context->batch;
3695
3696     BEGIN_BATCH(batch, 1);
3697     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3698     ADVANCE_BATCH(batch);
3699 }
3700
3701 static void
3702 gen6_pp_state_base_address(VADriverContextP ctx,
3703                            struct i965_post_processing_context *pp_context)
3704 {
3705     struct intel_batchbuffer *batch = pp_context->batch;
3706
3707     BEGIN_BATCH(batch, 10);
3708     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3709     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3710     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3711     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3712     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3713     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3714     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3715     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3716     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3717     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3718     ADVANCE_BATCH(batch);
3719 }
3720
3721 static void
3722 gen6_pp_vfe_state(VADriverContextP ctx,
3723                   struct i965_post_processing_context *pp_context)
3724 {
3725     struct intel_batchbuffer *batch = pp_context->batch;
3726
3727     BEGIN_BATCH(batch, 8);
3728     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3729     OUT_BATCH(batch, 0);
3730     OUT_BATCH(batch,
3731               (pp_context->urb.num_vfe_entries - 1) << 16 |
3732               pp_context->urb.num_vfe_entries << 8);
3733     OUT_BATCH(batch, 0);
3734     OUT_BATCH(batch,
3735               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3736               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3737     OUT_BATCH(batch, 0);
3738     OUT_BATCH(batch, 0);
3739     OUT_BATCH(batch, 0);
3740     ADVANCE_BATCH(batch);
3741 }
3742
3743 static void
3744 gen6_pp_curbe_load(VADriverContextP ctx,
3745                    struct i965_post_processing_context *pp_context)
3746 {
3747     struct intel_batchbuffer *batch = pp_context->batch;
3748
3749     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3750
3751     BEGIN_BATCH(batch, 4);
3752     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3753     OUT_BATCH(batch, 0);
3754     OUT_BATCH(batch,
3755               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3756     OUT_RELOC(batch,
3757               pp_context->curbe.bo,
3758               I915_GEM_DOMAIN_INSTRUCTION, 0,
3759               0);
3760     ADVANCE_BATCH(batch);
3761 }
3762
3763 static void
3764 gen6_interface_descriptor_load(VADriverContextP ctx,
3765                                struct i965_post_processing_context *pp_context)
3766 {
3767     struct intel_batchbuffer *batch = pp_context->batch;
3768
3769     BEGIN_BATCH(batch, 4);
3770     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3771     OUT_BATCH(batch, 0);
3772     OUT_BATCH(batch,
3773               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3774     OUT_RELOC(batch,
3775               pp_context->idrt.bo,
3776               I915_GEM_DOMAIN_INSTRUCTION, 0,
3777               0);
3778     ADVANCE_BATCH(batch);
3779 }
3780
3781 static void
3782 gen6_pp_object_walker(VADriverContextP ctx,
3783                       struct i965_post_processing_context *pp_context)
3784 {
3785     struct i965_driver_data *i965 = i965_driver_data(ctx);
3786     struct intel_batchbuffer *batch = pp_context->batch;
3787     int x, x_steps, y, y_steps;
3788     int param_size, command_length_in_dws;
3789     dri_bo *command_buffer;
3790     unsigned int *command_ptr;
3791
3792     if (IS_GEN7(i965->intel.device_id))
3793         param_size = sizeof(struct gen7_pp_inline_parameter);
3794     else
3795         param_size = sizeof(struct pp_inline_parameter);
3796
3797     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3798     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3799     command_length_in_dws = 6 + (param_size >> 2);
3800     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3801                                   "command objects buffer",
3802                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3803                                   4096);
3804
3805     dri_bo_map(command_buffer, 1);
3806     command_ptr = command_buffer->virtual;
3807
3808     for (y = 0; y < y_steps; y++) {
3809         for (x = 0; x < x_steps; x++) {
3810             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3811                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3812                 *command_ptr++ = 0;
3813                 *command_ptr++ = 0;
3814                 *command_ptr++ = 0;
3815                 *command_ptr++ = 0;
3816                 *command_ptr++ = 0;
3817                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3818                 command_ptr += (param_size >> 2);
3819             }
3820         }
3821     }
3822
3823     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3824         *command_ptr++ = 0;
3825
3826     *command_ptr = MI_BATCH_BUFFER_END;
3827
3828     dri_bo_unmap(command_buffer);
3829
3830     BEGIN_BATCH(batch, 2);
3831     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3832     OUT_RELOC(batch, command_buffer,
3833               I915_GEM_DOMAIN_COMMAND, 0,
3834               0);
3835     ADVANCE_BATCH(batch);
3836
3837     dri_bo_unreference(command_buffer);
3838
3839     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3840      * will cause control to pass back to ring buffer
3841      */
3842     intel_batchbuffer_end_atomic(batch);
3843     intel_batchbuffer_flush(batch);
3844     intel_batchbuffer_start_atomic(batch, 0x1000);
3845 }
3846
3847 static void
3848 gen6_pp_pipeline_setup(VADriverContextP ctx,
3849                        struct i965_post_processing_context *pp_context)
3850 {
3851     struct intel_batchbuffer *batch = pp_context->batch;
3852
3853     intel_batchbuffer_start_atomic(batch, 0x1000);
3854     intel_batchbuffer_emit_mi_flush(batch);
3855     gen6_pp_pipeline_select(ctx, pp_context);
3856     gen6_pp_state_base_address(ctx, pp_context);
3857     gen6_pp_vfe_state(ctx, pp_context);
3858     gen6_pp_curbe_load(ctx, pp_context);
3859     gen6_interface_descriptor_load(ctx, pp_context);
3860     gen6_pp_object_walker(ctx, pp_context);
3861     intel_batchbuffer_end_atomic(batch);
3862 }
3863
3864 static VAStatus
3865 gen6_post_processing(
3866     VADriverContextP   ctx,
3867     struct i965_post_processing_context *pp_context,
3868     const struct i965_surface *src_surface,
3869     const VARectangle *src_rect,
3870     struct i965_surface *dst_surface,
3871     const VARectangle *dst_rect,
3872     int                pp_index,
3873     void * filter_param
3874 )
3875 {
3876     VAStatus va_status;
3877
3878     va_status = gen6_pp_initialize(ctx, pp_context,
3879                                    src_surface,
3880                                    src_rect,
3881                                    dst_surface,
3882                                    dst_rect,
3883                                    pp_index,
3884                                    filter_param);
3885
3886     if (va_status == VA_STATUS_SUCCESS) {
3887         gen6_pp_states_setup(ctx, pp_context);
3888         gen6_pp_pipeline_setup(ctx, pp_context);
3889     }
3890
3891     return va_status;
3892 }
3893
3894 static VAStatus
3895 i965_post_processing_internal(
3896     VADriverContextP   ctx,
3897     struct i965_post_processing_context *pp_context,
3898     const struct i965_surface *src_surface,
3899     const VARectangle *src_rect,
3900     struct i965_surface *dst_surface,
3901     const VARectangle *dst_rect,
3902     int                pp_index,
3903     void *filter_param
3904 )
3905 {
3906     struct i965_driver_data *i965 = i965_driver_data(ctx);
3907     VAStatus va_status;
3908
3909     if (IS_GEN6(i965->intel.device_id) ||
3910         IS_GEN7(i965->intel.device_id))
3911         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3912     else
3913         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3914
3915     return va_status;
3916 }
3917
3918 VAStatus
3919 i965_DestroySurfaces(VADriverContextP ctx,
3920                      VASurfaceID *surface_list,
3921                      int num_surfaces);
3922 VAStatus
3923 i965_CreateSurfaces(VADriverContextP ctx,
3924                     int width,
3925                     int height,
3926                     int format,
3927                     int num_surfaces,
3928                     VASurfaceID *surfaces);
3929
3930 static void
3931 rgb_to_yuv(unsigned int argb,
3932            unsigned char *y,
3933            unsigned char *u,
3934            unsigned char *v,
3935            unsigned char *a)
3936 {
3937     int r = ((argb >> 16) & 0xff);
3938     int g = ((argb >> 8) & 0xff);
3939     int b = ((argb >> 0) & 0xff);
3940
3941     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3942     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3943     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3944     *a = ((argb >> 24) & 0xff);
3945 }
3946
3947 static void
3948 i965_vpp_clear_surface(VADriverContextP ctx,
3949                        struct i965_post_processing_context *pp_context,
3950                        VASurfaceID surface,
3951                        unsigned int color)
3952 {
3953     struct i965_driver_data *i965 = i965_driver_data(ctx);
3954     struct intel_batchbuffer *batch = pp_context->batch;
3955     struct object_surface *obj_surface = SURFACE(surface);
3956     unsigned int blt_cmd, br13;
3957     unsigned int tiling = 0, swizzle = 0;
3958     int pitch;
3959     unsigned char y, u, v, a = 0;
3960
3961     /* Currently only support NV12 surface */
3962     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3963         return;
3964
3965     rgb_to_yuv(color, &y, &u, &v, &a);
3966
3967     if (a == 0)
3968         return;
3969
3970     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3971     blt_cmd = XY_COLOR_BLT_CMD;
3972     pitch = obj_surface->width;
3973
3974     if (tiling != I915_TILING_NONE) {
3975         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3976         pitch >>= 2;
3977     }
3978
3979     br13 = 0xf0 << 16;
3980     br13 |= BR13_8;
3981     br13 |= pitch;
3982
3983     if (IS_GEN6(i965->intel.device_id) ||
3984         IS_GEN7(i965->intel.device_id)) {
3985         intel_batchbuffer_start_atomic_blt(batch, 48);
3986         BEGIN_BLT_BATCH(batch, 12);
3987     } else {
3988         intel_batchbuffer_start_atomic(batch, 48);
3989         BEGIN_BATCH(batch, 12);
3990     }
3991
3992     OUT_BATCH(batch, blt_cmd);
3993     OUT_BATCH(batch, br13);
3994     OUT_BATCH(batch,
3995               0 << 16 |
3996               0);
3997     OUT_BATCH(batch,
3998               obj_surface->height << 16 |
3999               obj_surface->width);
4000     OUT_RELOC(batch, obj_surface->bo,
4001               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4002               0);
4003     OUT_BATCH(batch, y);
4004
4005     br13 = 0xf0 << 16;
4006     br13 |= BR13_565;
4007     br13 |= pitch;
4008
4009     OUT_BATCH(batch, blt_cmd);
4010     OUT_BATCH(batch, br13);
4011     OUT_BATCH(batch,
4012               0 << 16 |
4013               0);
4014     OUT_BATCH(batch,
4015               obj_surface->height / 2 << 16 |
4016               obj_surface->width / 2);
4017     OUT_RELOC(batch, obj_surface->bo,
4018               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4019               obj_surface->width * obj_surface->y_cb_offset);
4020     OUT_BATCH(batch, v << 8 | u);
4021
4022     ADVANCE_BATCH(batch);
4023     intel_batchbuffer_end_atomic(batch);
4024 }
4025
4026 VASurfaceID
4027 i965_post_processing(
4028     VADriverContextP   ctx,
4029     VASurfaceID        surface,
4030     const VARectangle *src_rect,
4031     const VARectangle *dst_rect,
4032     unsigned int       flags,
4033     int               *has_done_scaling
4034 )
4035 {
4036     struct i965_driver_data *i965 = i965_driver_data(ctx);
4037     VASurfaceID in_surface_id = surface;
4038     VASurfaceID out_surface_id = VA_INVALID_ID;
4039
4040     *has_done_scaling = 0;
4041
4042     if (HAS_PP(i965)) {
4043         struct object_surface *obj_surface;
4044         VAStatus status;
4045         struct i965_surface src_surface;
4046         struct i965_surface dst_surface;
4047
4048         obj_surface = SURFACE(in_surface_id);
4049
4050         /* Currently only support post processing for NV12 surface */
4051         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
4052             return out_surface_id;
4053
4054         _i965LockMutex(&i965->pp_mutex);
4055
4056         if (flags & I965_PP_FLAG_MCDI) {
4057             status = i965_CreateSurfaces(ctx,
4058                                          obj_surface->orig_width,
4059                                          obj_surface->orig_height,
4060                                          VA_RT_FORMAT_YUV420,
4061                                          1,
4062                                          &out_surface_id);
4063             assert(status == VA_STATUS_SUCCESS);
4064             obj_surface = SURFACE(out_surface_id);
4065             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4066             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4067             src_surface.id = in_surface_id;
4068             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4069             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
4070                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
4071             dst_surface.id = out_surface_id;
4072             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4073             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4074
4075             i965_post_processing_internal(ctx, i965->pp_context,
4076                                           &src_surface,
4077                                           src_rect,
4078                                           &dst_surface,
4079                                           dst_rect,
4080                                           PP_NV12_DNDI,
4081                                           NULL);
4082         }
4083
4084         if (flags & I965_PP_FLAG_AVS) {
4085             struct i965_render_state *render_state = &i965->render_state;
4086             struct intel_region *dest_region = render_state->draw_region;
4087
4088             if (out_surface_id != VA_INVALID_ID)
4089                 in_surface_id = out_surface_id;
4090
4091             status = i965_CreateSurfaces(ctx,
4092                                          dest_region->width,
4093                                          dest_region->height,
4094                                          VA_RT_FORMAT_YUV420,
4095                                          1,
4096                                          &out_surface_id);
4097             assert(status == VA_STATUS_SUCCESS);
4098             obj_surface = SURFACE(out_surface_id);
4099             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4100             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4101             src_surface.id = in_surface_id;
4102             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4103             src_surface.flags = I965_SURFACE_FLAG_FRAME;
4104             dst_surface.id = out_surface_id;
4105             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4106             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4107
4108             i965_post_processing_internal(ctx, i965->pp_context,
4109                                           &src_surface,
4110                                           src_rect,
4111                                           &dst_surface,
4112                                           dst_rect,
4113                                           PP_NV12_AVS,
4114                                           NULL);
4115
4116             if (in_surface_id != surface)
4117                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4118
4119             *has_done_scaling = 1;
4120         }
4121
4122         _i965UnlockMutex(&i965->pp_mutex);
4123     }
4124
4125     return out_surface_id;
4126 }
4127
4128 static VAStatus
4129 i965_image_pl1_rgbx_processing(VADriverContextP ctx,
4130                           const struct i965_surface *src_surface,
4131                           const VARectangle *src_rect,
4132                           struct i965_surface *dst_surface,
4133                           const VARectangle *dst_rect)
4134 {
4135     struct i965_driver_data *i965 = i965_driver_data(ctx);
4136     struct i965_post_processing_context *pp_context = i965->pp_context;
4137     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4138
4139     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4140         i965_post_processing_internal(ctx, i965->pp_context,
4141                                       src_surface,
4142                                       src_rect,
4143                                       dst_surface,
4144                                       dst_rect,
4145                                       PP_RGBX_LOAD_SAVE_NV12,
4146                                       NULL);
4147     } else {
4148         assert(0);
4149         return VA_STATUS_ERROR_UNKNOWN;
4150     }
4151
4152     intel_batchbuffer_flush(pp_context->batch);
4153
4154     return VA_STATUS_SUCCESS;
4155 }
4156
4157 static VAStatus
4158 i965_image_pl3_processing(VADriverContextP ctx,
4159                           const struct i965_surface *src_surface,
4160                           const VARectangle *src_rect,
4161                           struct i965_surface *dst_surface,
4162                           const VARectangle *dst_rect)
4163 {
4164     struct i965_driver_data *i965 = i965_driver_data(ctx);
4165     struct i965_post_processing_context *pp_context = i965->pp_context;
4166     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4167     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4168
4169     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4170         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4171                                                  src_surface,
4172                                                  src_rect,
4173                                                  dst_surface,
4174                                                  dst_rect,
4175                                                  PP_PL3_LOAD_SAVE_N12,
4176                                                  NULL);
4177     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4178                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4179                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4180                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4181         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4182                                                  src_surface,
4183                                                  src_rect,
4184                                                  dst_surface,
4185                                                  dst_rect,
4186                                                  PP_PL3_LOAD_SAVE_PL3,
4187                                                  NULL);
4188     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4189                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4190         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4191                                                  src_surface,
4192                                                  src_rect,
4193                                                  dst_surface,
4194                                                  dst_rect,
4195                                                  PP_PL3_LOAD_SAVE_PA,
4196                                                  NULL);
4197     }
4198     else {
4199         assert(0);
4200     }
4201
4202     intel_batchbuffer_flush(pp_context->batch);
4203
4204     return vaStatus;
4205 }
4206
4207 static VAStatus
4208 i965_image_pl2_processing(VADriverContextP ctx,
4209                           const struct i965_surface *src_surface,
4210                           const VARectangle *src_rect,
4211                           struct i965_surface *dst_surface,
4212                           const VARectangle *dst_rect)
4213 {
4214     struct i965_driver_data *i965 = i965_driver_data(ctx);
4215     struct i965_post_processing_context *pp_context = i965->pp_context;
4216     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4217     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4218
4219     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4220         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4221                                                  src_surface,
4222                                                  src_rect,
4223                                                  dst_surface,
4224                                                  dst_rect,
4225                                                  PP_NV12_LOAD_SAVE_N12,
4226                                                  NULL);
4227     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4228                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4229                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4230                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4231         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4232                                                  src_surface,
4233                                                  src_rect,
4234                                                  dst_surface,
4235                                                  dst_rect,
4236                                                  PP_NV12_LOAD_SAVE_PL3,
4237                                                  NULL);
4238     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4239                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4240         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4241                                                  src_surface,
4242                                                  src_rect,
4243                                                  dst_surface,
4244                                                  dst_rect,
4245                                                  PP_NV12_LOAD_SAVE_PA,
4246                                                      NULL);
4247     } else if (fourcc == VA_FOURCC('B', 'G', 'R', 'X') ||
4248                fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
4249                fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
4250                fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) {
4251         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4252                                       src_surface,
4253                                       src_rect,
4254                                       dst_surface,
4255                                       dst_rect,
4256                                       PP_NV12_LOAD_SAVE_RGBX,
4257                                       NULL);
4258     } else {
4259         assert(0);
4260         return VA_STATUS_ERROR_UNKNOWN;
4261     }
4262
4263     intel_batchbuffer_flush(pp_context->batch);
4264
4265     return vaStatus;
4266 }
4267
4268 static VAStatus
4269 i965_image_pl1_processing(VADriverContextP ctx,
4270                           const struct i965_surface *src_surface,
4271                           const VARectangle *src_rect,
4272                           struct i965_surface *dst_surface,
4273                           const VARectangle *dst_rect)
4274 {
4275     struct i965_driver_data *i965 = i965_driver_data(ctx);
4276     struct i965_post_processing_context *pp_context = i965->pp_context;
4277     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4278
4279     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4280         i965_post_processing_internal(ctx, i965->pp_context,
4281                                       src_surface,
4282                                       src_rect,
4283                                       dst_surface,
4284                                       dst_rect,
4285                                       PP_PA_LOAD_SAVE_NV12,
4286                                       NULL);
4287     }
4288     else if (fourcc == VA_FOURCC_YV12) {
4289         i965_post_processing_internal(ctx, i965->pp_context,
4290                                       src_surface,
4291                                       src_rect,
4292                                       dst_surface,
4293                                       dst_rect,
4294                                       PP_PA_LOAD_SAVE_PL3,
4295                                       NULL);
4296
4297     }
4298     else {
4299         return VA_STATUS_ERROR_UNKNOWN;
4300     }
4301
4302     intel_batchbuffer_flush(pp_context->batch);
4303
4304     return VA_STATUS_SUCCESS;
4305 }
4306
4307 VAStatus
4308 i965_image_processing(VADriverContextP ctx,
4309                       const struct i965_surface *src_surface,
4310                       const VARectangle *src_rect,
4311                       struct i965_surface *dst_surface,
4312                       const VARectangle *dst_rect)
4313 {
4314     struct i965_driver_data *i965 = i965_driver_data(ctx);
4315     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4316
4317     if (HAS_PP(i965)) {
4318         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4319
4320         _i965LockMutex(&i965->pp_mutex);
4321
4322         switch (fourcc) {
4323         case VA_FOURCC('Y', 'V', '1', '2'):
4324         case VA_FOURCC('I', '4', '2', '0'):
4325         case VA_FOURCC('I', 'M', 'C', '1'):
4326         case VA_FOURCC('I', 'M', 'C', '3'):
4327             status = i965_image_pl3_processing(ctx,
4328                                                src_surface,
4329                                                src_rect,
4330                                                dst_surface,
4331                                                dst_rect);
4332             break;
4333
4334         case  VA_FOURCC('N', 'V', '1', '2'):
4335             status = i965_image_pl2_processing(ctx,
4336                                                src_surface,
4337                                                src_rect,
4338                                                dst_surface,
4339                                                dst_rect);
4340             break;
4341         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4342         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4343             status = i965_image_pl1_processing(ctx,
4344                                                src_surface,
4345                                                src_rect,
4346                                                dst_surface,
4347                                                dst_rect);
4348             break;
4349         case VA_FOURCC('B', 'G', 'R', 'A'):
4350         case VA_FOURCC('B', 'G', 'R', 'X'):
4351         case VA_FOURCC('R', 'G', 'B', 'A'):
4352         case VA_FOURCC('R', 'G', 'B', 'X'):
4353             status = i965_image_pl1_rgbx_processing(ctx,
4354                                                src_surface,
4355                                                src_rect,
4356                                                dst_surface,
4357                                                dst_rect);
4358             break;
4359         default:
4360             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4361             break;
4362         }
4363
4364         _i965UnlockMutex(&i965->pp_mutex);
4365     }
4366
4367     return status;
4368 }
4369
4370 static void
4371 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4372 {
4373     int i;
4374
4375     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4376     pp_context->surface_state_binding_table.bo = NULL;
4377
4378     dri_bo_unreference(pp_context->curbe.bo);
4379     pp_context->curbe.bo = NULL;
4380
4381     dri_bo_unreference(pp_context->sampler_state_table.bo);
4382     pp_context->sampler_state_table.bo = NULL;
4383
4384     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4385     pp_context->sampler_state_table.bo_8x8 = NULL;
4386
4387     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4388     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4389
4390     dri_bo_unreference(pp_context->idrt.bo);
4391     pp_context->idrt.bo = NULL;
4392     pp_context->idrt.num_interface_descriptors = 0;
4393
4394     dri_bo_unreference(pp_context->vfe_state.bo);
4395     pp_context->vfe_state.bo = NULL;
4396
4397     dri_bo_unreference(pp_context->stmm.bo);
4398     pp_context->stmm.bo = NULL;
4399
4400     for (i = 0; i < NUM_PP_MODULES; i++) {
4401         struct pp_module *pp_module = &pp_context->pp_modules[i];
4402
4403         dri_bo_unreference(pp_module->kernel.bo);
4404         pp_module->kernel.bo = NULL;
4405     }
4406
4407     free(pp_context->pp_static_parameter);
4408     free(pp_context->pp_inline_parameter);
4409     pp_context->pp_static_parameter = NULL;
4410     pp_context->pp_inline_parameter = NULL;
4411 }
4412
4413 Bool
4414 i965_post_processing_terminate(VADriverContextP ctx)
4415 {
4416     struct i965_driver_data *i965 = i965_driver_data(ctx);
4417     struct i965_post_processing_context *pp_context = i965->pp_context;
4418
4419     if (pp_context) {
4420         i965_post_processing_context_finalize(pp_context);
4421         free(pp_context);
4422     }
4423
4424     i965->pp_context = NULL;
4425
4426     return True;
4427 }
4428
4429 static void
4430 i965_post_processing_context_init(VADriverContextP ctx,
4431                                   struct i965_post_processing_context *pp_context,
4432                                   struct intel_batchbuffer *batch)
4433 {
4434     struct i965_driver_data *i965 = i965_driver_data(ctx);
4435     int i;
4436
4437     pp_context->urb.size = URB_SIZE((&i965->intel));
4438     pp_context->urb.num_vfe_entries = 32;
4439     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4440     pp_context->urb.num_cs_entries = 1;
4441
4442     if (IS_GEN7(i965->intel.device_id))
4443         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4444     else
4445         pp_context->urb.size_cs_entry = 2;
4446
4447     pp_context->urb.vfe_start = 0;
4448     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4449         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4450     assert(pp_context->urb.cs_start +
4451            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4452
4453     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4454     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4455     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4456
4457     if (IS_GEN7(i965->intel.device_id))
4458         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4459     else if (IS_GEN6(i965->intel.device_id))
4460         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4461     else if (IS_IRONLAKE(i965->intel.device_id))
4462         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4463
4464     for (i = 0; i < NUM_PP_MODULES; i++) {
4465         struct pp_module *pp_module = &pp_context->pp_modules[i];
4466         dri_bo_unreference(pp_module->kernel.bo);
4467         if (pp_module->kernel.bin && pp_module->kernel.size) {
4468             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4469                                                 pp_module->kernel.name,
4470                                                 pp_module->kernel.size,
4471                                                 4096);
4472             assert(pp_module->kernel.bo);
4473             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4474         } else {
4475             pp_module->kernel.bo = NULL;
4476         }
4477     }
4478
4479     /* static & inline parameters */
4480     if (IS_GEN7(i965->intel.device_id)) {
4481         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4482         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4483     } else {
4484         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4485         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4486     }
4487
4488     pp_context->batch = batch;
4489 }
4490
4491 Bool
4492 i965_post_processing_init(VADriverContextP ctx)
4493 {
4494     struct i965_driver_data *i965 = i965_driver_data(ctx);
4495     struct i965_post_processing_context *pp_context = i965->pp_context;
4496
4497     if (HAS_PP(i965)) {
4498         if (pp_context == NULL) {
4499             pp_context = calloc(1, sizeof(*pp_context));
4500             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4501             i965->pp_context = pp_context;
4502         }
4503     }
4504
4505     return True;
4506 }
4507
4508 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4509     PP_NULL,    /* VAProcFilterNone */
4510     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4511     PP_NULL,    /* VAProcFilterDeblocking */
4512     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4513     PP_NULL,    /* VAProcFilterSharpening */
4514     PP_NULL,    /* VAProcFilterColorBalance */
4515     PP_NULL,    /* VAProcFilterColorStandard */
4516     PP_NULL,    /* VAProcFilterFrameRateConversion */
4517 };
4518
4519 static const int proc_frame_to_pp_frame[3] = {
4520     I965_SURFACE_FLAG_FRAME,
4521     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4522     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4523 };
4524
4525 static void
4526 i965_proc_picture(VADriverContextP ctx,
4527                   VAProfile profile,
4528                   union codec_state *codec_state,
4529                   struct hw_context *hw_context)
4530 {
4531     struct i965_driver_data *i965 = i965_driver_data(ctx);
4532     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4533     struct proc_state *proc_state = &codec_state->proc;
4534     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4535     struct object_surface *obj_surface;
4536     struct i965_surface src_surface, dst_surface;
4537     VARectangle src_rect, dst_rect;
4538     VAStatus status;
4539     int i;
4540     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4541     int num_tmp_surfaces = 0;
4542     unsigned int tiling = 0, swizzle = 0;
4543     int in_width, in_height;
4544
4545     assert(pipeline_param->surface != VA_INVALID_ID);
4546     assert(proc_state->current_render_target != VA_INVALID_ID);
4547
4548     obj_surface = SURFACE(pipeline_param->surface);
4549     in_width = obj_surface->orig_width;
4550     in_height = obj_surface->orig_height;
4551     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4552
4553     src_surface.id = pipeline_param->surface;
4554     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4555     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4556
4557     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4558         VASurfaceID out_surface_id = VA_INVALID_ID;
4559
4560         src_surface.id = pipeline_param->surface;
4561         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4562         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4563         src_rect.x = 0;
4564         src_rect.y = 0;
4565         src_rect.width = in_width;
4566         src_rect.height = in_height;
4567
4568         status = i965_CreateSurfaces(ctx,
4569                                      in_width,
4570                                      in_height,
4571                                      VA_RT_FORMAT_YUV420,
4572                                      1,
4573                                      &out_surface_id);
4574         assert(status == VA_STATUS_SUCCESS);
4575         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4576         obj_surface = SURFACE(out_surface_id);
4577         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4578
4579         dst_surface.id = out_surface_id;
4580         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4581         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4582         dst_rect.x = 0;
4583         dst_rect.y = 0;
4584         dst_rect.width = in_width;
4585         dst_rect.height = in_height;
4586
4587         status = i965_image_processing(ctx,
4588                                        &src_surface,
4589                                        &src_rect,
4590                                        &dst_surface,
4591                                        &dst_rect);
4592         assert(status == VA_STATUS_SUCCESS);
4593
4594         src_surface.id = out_surface_id;
4595         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4596         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4597     }
4598
4599     if (pipeline_param->surface_region) {
4600         src_rect.x = pipeline_param->surface_region->x;
4601         src_rect.y = pipeline_param->surface_region->y;
4602         src_rect.width = pipeline_param->surface_region->width;
4603         src_rect.height = pipeline_param->surface_region->height;
4604     } else {
4605         src_rect.x = 0;
4606         src_rect.y = 0;
4607         src_rect.width = in_width;
4608         src_rect.height = in_height;
4609     }
4610
4611     if (pipeline_param->output_region) {
4612         dst_rect.x = pipeline_param->output_region->x;
4613         dst_rect.y = pipeline_param->output_region->y;
4614         dst_rect.width = pipeline_param->output_region->width;
4615         dst_rect.height = pipeline_param->output_region->height;
4616     } else {
4617         dst_rect.x = 0;
4618         dst_rect.y = 0;
4619         dst_rect.width = in_width;
4620         dst_rect.height = in_height;
4621     }
4622
4623     obj_surface = SURFACE(proc_state->current_render_target);
4624     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4625     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4626
4627     for (i = 0; i < pipeline_param->num_filters; i++) {
4628         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4629         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4630         VAProcFilterType filter_type = filter_param->type;
4631         VASurfaceID out_surface_id = VA_INVALID_ID;
4632         int kernel_index = procfilter_to_pp_flag[filter_type];
4633
4634         if (kernel_index != PP_NULL &&
4635             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4636             status = i965_CreateSurfaces(ctx,
4637                                          in_width,
4638                                          in_height,
4639                                          VA_RT_FORMAT_YUV420,
4640                                          1,
4641                                          &out_surface_id);
4642             assert(status == VA_STATUS_SUCCESS);
4643             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4644             obj_surface = SURFACE(out_surface_id);
4645             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4646             dst_surface.id = out_surface_id;
4647             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4648             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4649                                                    &src_surface,
4650                                                    &src_rect,
4651                                                    &dst_surface,
4652                                                    &src_rect,
4653                                                    kernel_index,
4654                                                    filter_param);
4655
4656             if (status == VA_STATUS_SUCCESS) {
4657                 src_surface.id = dst_surface.id;
4658                 src_surface.type = dst_surface.type;
4659                 src_surface.flags = dst_surface.flags;
4660             }
4661         }
4662     }
4663
4664     dst_surface.id = proc_state->current_render_target;
4665     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4666
4667     if (src_rect.width == dst_rect.width &&
4668         src_rect.height == dst_rect.height) {
4669         i965_post_processing_internal(ctx, &proc_context->pp_context,
4670                                       &src_surface,
4671                                       &src_rect,
4672                                       &dst_surface,
4673                                       &dst_rect,
4674                                       PP_NV12_LOAD_SAVE_N12,
4675                                       NULL);
4676     } else {
4677
4678         i965_post_processing_internal(ctx, &proc_context->pp_context,
4679                                       &src_surface,
4680                                       &src_rect,
4681                                       &dst_surface,
4682                                       &dst_rect,
4683                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4684                                       PP_NV12_AVS : PP_NV12_SCALING,
4685                                       NULL);
4686     }
4687
4688     if (num_tmp_surfaces)
4689         i965_DestroySurfaces(ctx,
4690                              tmp_surfaces,
4691                              num_tmp_surfaces);
4692
4693     intel_batchbuffer_flush(hw_context->batch);
4694 }
4695
4696 static void
4697 i965_proc_context_destroy(void *hw_context)
4698 {
4699     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4700
4701     i965_post_processing_context_finalize(&proc_context->pp_context);
4702     intel_batchbuffer_free(proc_context->base.batch);
4703     free(proc_context);
4704 }
4705
4706 struct hw_context *
4707 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4708 {
4709     struct intel_driver_data *intel = intel_driver_data(ctx);
4710     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4711
4712     proc_context->base.destroy = i965_proc_context_destroy;
4713     proc_context->base.run = i965_proc_picture;
4714     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4715     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4716
4717     return (struct hw_context *)proc_context;
4718 }