src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = {
 111 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5"
 112 };
 113
 114 static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = {
 115 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5"
 116 };
 117
 118 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                    const struct i965_surface *src_surface,
 120                                    const VARectangle *src_rect,
 121                                    struct i965_surface *dst_surface,
 122                                    const VARectangle *dst_rect,
 123                                    void *filter_param);
 124 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                             const struct i965_surface *src_surface,
 126                                             const VARectangle *src_rect,
 127                                             struct i965_surface *dst_surface,
 128                                             const VARectangle *dst_rect,
 129                                             void *filter_param);
 130 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 131                                            const struct i965_surface *src_surface,
 132                                            const VARectangle *src_rect,
 133                                            struct i965_surface *dst_surface,
 134                                            const VARectangle *dst_rect,
 135                                            void *filter_param);
 136 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 137                                              const struct i965_surface *src_surface,
 138                                              const VARectangle *src_rect,
 139                                              struct i965_surface *dst_surface,
 140                                              const VARectangle *dst_rect,
 141                                              void *filter_param);
 142 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 143                                                 const struct i965_surface *src_surface,
 144                                                 const VARectangle *src_rect,
 145                                                 struct i965_surface *dst_surface,
 146                                                 const VARectangle *dst_rect,
 147                                                 void *filter_param);
 148 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 149                                         const struct i965_surface *src_surface,
 150                                         const VARectangle *src_rect,
 151                                         struct i965_surface *dst_surface,
 152                                         const VARectangle *dst_rect,
 153                                         void *filter_param);
 154 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 155                                       const struct i965_surface *src_surface,
 156                                       const VARectangle *src_rect,
 157                                       struct i965_surface *dst_surface,
 158                                       const VARectangle *dst_rect,
 159                                       void *filter_param);
 160
 161 static struct pp_module pp_modules_gen5[] = {
 162     {
 163         {
 164             "NULL module (for testing)",
 165             PP_NULL,
 166             pp_null_gen5,
 167             sizeof(pp_null_gen5),
 168             NULL,
 169         },
 170
 171         pp_null_initialize,
 172     },
 173
 174     {
 175         {
 176             "NV12_NV12",
 177             PP_NV12_LOAD_SAVE_N12,
 178             pp_nv12_load_save_nv12_gen5,
 179             sizeof(pp_nv12_load_save_nv12_gen5),
 180             NULL,
 181         },
 182
 183         pp_plx_load_save_plx_initialize,
 184     },
 185
 186     {
 187         {
 188             "NV12_PL3",
 189             PP_NV12_LOAD_SAVE_PL3,
 190             pp_nv12_load_save_pl3_gen5,
 191             sizeof(pp_nv12_load_save_pl3_gen5),
 192             NULL,
 193         },
 194
 195         pp_plx_load_save_plx_initialize,
 196     },
 197
 198     {
 199         {
 200             "PL3_NV12",
 201             PP_PL3_LOAD_SAVE_N12,
 202             pp_pl3_load_save_nv12_gen5,
 203             sizeof(pp_pl3_load_save_nv12_gen5),
 204             NULL,
 205         },
 206
 207         pp_plx_load_save_plx_initialize,
 208     },
 209
 210     {
 211         {
 212             "PL3_PL3",
 213             PP_PL3_LOAD_SAVE_N12,
 214             pp_pl3_load_save_pl3_gen5,
 215             sizeof(pp_pl3_load_save_pl3_gen5),
 216             NULL,
 217         },
 218
 219         pp_plx_load_save_plx_initialize
 220     },
 221
 222     {
 223         {
 224             "NV12 Scaling module",
 225             PP_NV12_SCALING,
 226             pp_nv12_scaling_gen5,
 227             sizeof(pp_nv12_scaling_gen5),
 228             NULL,
 229         },
 230
 231         pp_nv12_scaling_initialize,
 232     },
 233
 234     {
 235         {
 236             "NV12 AVS module",
 237             PP_NV12_AVS,
 238             pp_nv12_avs_gen5,
 239             sizeof(pp_nv12_avs_gen5),
 240             NULL,
 241         },
 242
 243         pp_nv12_avs_initialize_nlas,
 244     },
 245
 246     {
 247         {
 248             "NV12 DNDI module",
 249             PP_NV12_DNDI,
 250             pp_nv12_dndi_gen5,
 251             sizeof(pp_nv12_dndi_gen5),
 252             NULL,
 253         },
 254
 255         pp_nv12_dndi_initialize,
 256     },
 257
 258     {
 259         {
 260             "NV12 DN module",
 261             PP_NV12_DN,
 262             pp_nv12_dn_gen5,
 263             sizeof(pp_nv12_dn_gen5),
 264             NULL,
 265         },
 266
 267         pp_nv12_dn_initialize,
 268     },
 269
 270     {
 271         {
 272             "NV12_PA module",
 273             PP_NV12_LOAD_SAVE_PA,
 274             pp_nv12_load_save_pa_gen5,
 275             sizeof(pp_nv12_load_save_pa_gen5),
 276             NULL,
 277         },
 278
 279         pp_plx_load_save_plx_initialize,
 280     },
 281
 282     {
 283         {
 284             "PL3_PA module",
 285             PP_PL3_LOAD_SAVE_PA,
 286             pp_pl3_load_save_pa_gen5,
 287             sizeof(pp_pl3_load_save_pa_gen5),
 288             NULL,
 289         },
 290
 291         pp_plx_load_save_plx_initialize,
 292     },
 293
 294     {
 295         {
 296             "PA_NV12 module",
 297             PP_PA_LOAD_SAVE_NV12,
 298             pp_pa_load_save_nv12_gen5,
 299             sizeof(pp_pa_load_save_nv12_gen5),
 300             NULL,
 301         },
 302
 303         pp_plx_load_save_plx_initialize,
 304     },
 305
 306     {
 307         {
 308             "PA_PL3 module",
 309             PP_PA_LOAD_SAVE_PL3,
 310             pp_pa_load_save_pl3_gen5,
 311             sizeof(pp_pa_load_save_pl3_gen5),
 312             NULL,
 313         },
 314
 315         pp_plx_load_save_plx_initialize,
 316     },
 317
 318     {
 319         {
 320             "RGBX_NV12 module",
 321             PP_RGBX_LOAD_SAVE_NV12,
 322             pp_rgbx_load_save_nv12_gen5,
 323             sizeof(pp_rgbx_load_save_nv12_gen5),
 324             NULL,
 325         },
 326
 327         pp_plx_load_save_plx_initialize,
 328     },
 329
 330     {
 331         {
 332             "NV12_RGBX module",
 333             PP_NV12_LOAD_SAVE_RGBX,
 334             pp_nv12_load_save_rgbx_gen5,
 335             sizeof(pp_nv12_load_save_rgbx_gen5),
 336             NULL,
 337         },
 338
 339         pp_plx_load_save_plx_initialize,
 340     },
 341
 342 };
 343
 344 static const uint32_t pp_null_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/null.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 350 };
 351
 352 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 354 };
 355
 356 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 362 };
 363
 364 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 365 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 366 };
 367
 368 static const uint32_t pp_nv12_avs_gen6[][4] = {
 369 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 370 };
 371
 372 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 373 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 374 };
 375
 376 static const uint32_t pp_nv12_dn_gen6[][4] = {
 377 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 378 };
 379
 380 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 381 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 382 };
 383
 384 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 385 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 386 };
 387
 388 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 389 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 390 };
 391
 392 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 393 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 394 };
 395
 396 static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = {
 397 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b"
 398 };
 399
 400 static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = {
 401 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b"
 402 };
 403
 404 static struct pp_module pp_modules_gen6[] = {
 405     {
 406         {
 407             "NULL module (for testing)",
 408             PP_NULL,
 409             pp_null_gen6,
 410             sizeof(pp_null_gen6),
 411             NULL,
 412         },
 413
 414         pp_null_initialize,
 415     },
 416
 417     {
 418         {
 419             "NV12_NV12",
 420             PP_NV12_LOAD_SAVE_N12,
 421             pp_nv12_load_save_nv12_gen6,
 422             sizeof(pp_nv12_load_save_nv12_gen6),
 423             NULL,
 424         },
 425
 426         pp_plx_load_save_plx_initialize,
 427     },
 428
 429     {
 430         {
 431             "NV12_PL3",
 432             PP_NV12_LOAD_SAVE_PL3,
 433             pp_nv12_load_save_pl3_gen6,
 434             sizeof(pp_nv12_load_save_pl3_gen6),
 435             NULL,
 436         },
 437
 438         pp_plx_load_save_plx_initialize,
 439     },
 440
 441     {
 442         {
 443             "PL3_NV12",
 444             PP_PL3_LOAD_SAVE_N12,
 445             pp_pl3_load_save_nv12_gen6,
 446             sizeof(pp_pl3_load_save_nv12_gen6),
 447             NULL,
 448         },
 449
 450         pp_plx_load_save_plx_initialize,
 451     },
 452
 453     {
 454         {
 455             "PL3_PL3",
 456             PP_PL3_LOAD_SAVE_N12,
 457             pp_pl3_load_save_pl3_gen6,
 458             sizeof(pp_pl3_load_save_pl3_gen6),
 459             NULL,
 460         },
 461
 462         pp_plx_load_save_plx_initialize,
 463     },
 464
 465     {
 466         {
 467             "NV12 Scaling module",
 468             PP_NV12_SCALING,
 469             pp_nv12_scaling_gen6,
 470             sizeof(pp_nv12_scaling_gen6),
 471             NULL,
 472         },
 473
 474         gen6_nv12_scaling_initialize,
 475     },
 476
 477     {
 478         {
 479             "NV12 AVS module",
 480             PP_NV12_AVS,
 481             pp_nv12_avs_gen6,
 482             sizeof(pp_nv12_avs_gen6),
 483             NULL,
 484         },
 485
 486         pp_nv12_avs_initialize_nlas,
 487     },
 488
 489     {
 490         {
 491             "NV12 DNDI module",
 492             PP_NV12_DNDI,
 493             pp_nv12_dndi_gen6,
 494             sizeof(pp_nv12_dndi_gen6),
 495             NULL,
 496         },
 497
 498         pp_nv12_dndi_initialize,
 499     },
 500
 501     {
 502         {
 503             "NV12 DN module",
 504             PP_NV12_DN,
 505             pp_nv12_dn_gen6,
 506             sizeof(pp_nv12_dn_gen6),
 507             NULL,
 508         },
 509
 510         pp_nv12_dn_initialize,
 511     },
 512     {
 513         {
 514             "NV12_PA module",
 515             PP_NV12_LOAD_SAVE_PA,
 516             pp_nv12_load_save_pa_gen6,
 517             sizeof(pp_nv12_load_save_pa_gen6),
 518             NULL,
 519         },
 520
 521         pp_plx_load_save_plx_initialize,
 522     },
 523
 524     {
 525         {
 526             "PL3_PA module",
 527             PP_PL3_LOAD_SAVE_PA,
 528             pp_pl3_load_save_pa_gen6,
 529             sizeof(pp_pl3_load_save_pa_gen6),
 530             NULL,
 531         },
 532
 533         pp_plx_load_save_plx_initialize,
 534     },
 535
 536     {
 537         {
 538             "PA_NV12 module",
 539             PP_PA_LOAD_SAVE_NV12,
 540             pp_pa_load_save_nv12_gen6,
 541             sizeof(pp_pa_load_save_nv12_gen6),
 542             NULL,
 543         },
 544
 545         pp_plx_load_save_plx_initialize,
 546     },
 547
 548     {
 549         {
 550             "PA_PL3 module",
 551             PP_PA_LOAD_SAVE_PL3,
 552             pp_pa_load_save_pl3_gen6,
 553             sizeof(pp_pa_load_save_pl3_gen6),
 554             NULL,
 555         },
 556
 557         pp_plx_load_save_plx_initialize,
 558     },
 559
 560     {
 561         {
 562             "RGBX_NV12 module",
 563             PP_RGBX_LOAD_SAVE_NV12,
 564             pp_rgbx_load_save_nv12_gen6,
 565             sizeof(pp_rgbx_load_save_nv12_gen6),
 566             NULL,
 567         },
 568
 569         pp_plx_load_save_plx_initialize,
 570     },
 571
 572     {
 573         {
 574             "NV12_RGBX module",
 575             PP_NV12_LOAD_SAVE_RGBX,
 576             pp_nv12_load_save_rgbx_gen6,
 577             sizeof(pp_nv12_load_save_rgbx_gen6),
 578             NULL,
 579         },
 580
 581         pp_plx_load_save_plx_initialize,
 582     },
 583 };
 584
 585 static const uint32_t pp_null_gen7[][4] = {
 586 };
 587
 588 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 589 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 590 };
 591
 592 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 593 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 594 };
 595
 596 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 597 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 598 };
 599
 600 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 601 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 602 };
 603
 604 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 605 #include "shaders/post_processing/gen7/avs.g7b"
 606 };
 607
 608 static const uint32_t pp_nv12_avs_gen7[][4] = {
 609 #include "shaders/post_processing/gen7/avs.g7b"
 610 };
 611
 612 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 613 #include "shaders/post_processing/gen7/dndi.g7b"
 614 };
 615
 616 static const uint32_t pp_nv12_dn_gen7[][4] = {
 617 #include "shaders/post_processing/gen7/nv12_dn_nv12.g7b"
 618 };
 619 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 620 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 621 };
 622 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 623 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 624 };
 625 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 626 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 627 };
 628 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 629 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 630 };
 631 static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = {
 632 };
 633 static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = {
 634 };
 635
 636 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 637                                            const struct i965_surface *src_surface,
 638                                            const VARectangle *src_rect,
 639                                            struct i965_surface *dst_surface,
 640                                            const VARectangle *dst_rect,
 641                                            void *filter_param);
 642 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 643                                              const struct i965_surface *src_surface,
 644                                              const VARectangle *src_rect,
 645                                              struct i965_surface *dst_surface,
 646                                              const VARectangle *dst_rect,
 647                                              void *filter_param);
 648 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 649                                            const struct i965_surface *src_surface,
 650                                            const VARectangle *src_rect,
 651                                            struct i965_surface *dst_surface,
 652                                            const VARectangle *dst_rect,
 653                                            void *filter_param);
 654
 655 static struct pp_module pp_modules_gen7[] = {
 656     {
 657         {
 658             "NULL module (for testing)",
 659             PP_NULL,
 660             pp_null_gen7,
 661             sizeof(pp_null_gen7),
 662             NULL,
 663         },
 664
 665         pp_null_initialize,
 666     },
 667
 668     {
 669         {
 670             "NV12_NV12",
 671             PP_NV12_LOAD_SAVE_N12,
 672             pp_nv12_load_save_nv12_gen7,
 673             sizeof(pp_nv12_load_save_nv12_gen7),
 674             NULL,
 675         },
 676
 677         gen7_pp_plx_avs_initialize,
 678     },
 679
 680     {
 681         {
 682             "NV12_PL3",
 683             PP_NV12_LOAD_SAVE_PL3,
 684             pp_nv12_load_save_pl3_gen7,
 685             sizeof(pp_nv12_load_save_pl3_gen7),
 686             NULL,
 687         },
 688
 689         gen7_pp_plx_avs_initialize,
 690     },
 691
 692     {
 693         {
 694             "PL3_NV12",
 695             PP_PL3_LOAD_SAVE_N12,
 696             pp_pl3_load_save_nv12_gen7,
 697             sizeof(pp_pl3_load_save_nv12_gen7),
 698             NULL,
 699         },
 700
 701         gen7_pp_plx_avs_initialize,
 702     },
 703
 704     {
 705         {
 706             "PL3_PL3",
 707             PP_PL3_LOAD_SAVE_N12,
 708             pp_pl3_load_save_pl3_gen7,
 709             sizeof(pp_pl3_load_save_pl3_gen7),
 710             NULL,
 711         },
 712
 713         gen7_pp_plx_avs_initialize,
 714     },
 715
 716     {
 717         {
 718             "NV12 Scaling module",
 719             PP_NV12_SCALING,
 720             pp_nv12_scaling_gen7,
 721             sizeof(pp_nv12_scaling_gen7),
 722             NULL,
 723         },
 724
 725         gen7_pp_plx_avs_initialize,
 726     },
 727
 728     {
 729         {
 730             "NV12 AVS module",
 731             PP_NV12_AVS,
 732             pp_nv12_avs_gen7,
 733             sizeof(pp_nv12_avs_gen7),
 734             NULL,
 735         },
 736
 737         gen7_pp_plx_avs_initialize,
 738     },
 739
 740     {
 741         {
 742             "NV12 DNDI module",
 743             PP_NV12_DNDI,
 744             pp_nv12_dndi_gen7,
 745             sizeof(pp_nv12_dndi_gen7),
 746             NULL,
 747         },
 748
 749         gen7_pp_nv12_dndi_initialize,
 750     },
 751
 752     {
 753         {
 754             "NV12 DN module",
 755             PP_NV12_DN,
 756             pp_nv12_dn_gen7,
 757             sizeof(pp_nv12_dn_gen7),
 758             NULL,
 759         },
 760
 761         gen7_pp_nv12_dn_initialize,
 762     },
 763     {
 764         {
 765             "NV12_PA module",
 766             PP_NV12_LOAD_SAVE_PA,
 767             pp_nv12_load_save_pa_gen7,
 768             sizeof(pp_nv12_load_save_pa_gen7),
 769             NULL,
 770         },
 771
 772         gen7_pp_plx_avs_initialize,
 773     },
 774
 775     {
 776         {
 777             "PL3_PA module",
 778             PP_PL3_LOAD_SAVE_PA,
 779             pp_pl3_load_save_pa_gen7,
 780             sizeof(pp_pl3_load_save_pa_gen7),
 781             NULL,
 782         },
 783
 784         gen7_pp_plx_avs_initialize,
 785     },
 786
 787     {
 788         {
 789             "PA_NV12 module",
 790             PP_PA_LOAD_SAVE_NV12,
 791             pp_pa_load_save_nv12_gen7,
 792             sizeof(pp_pa_load_save_nv12_gen7),
 793             NULL,
 794         },
 795
 796         gen7_pp_plx_avs_initialize,
 797     },
 798
 799     {
 800         {
 801             "PA_PL3 module",
 802             PP_PA_LOAD_SAVE_PL3,
 803             pp_pa_load_save_pl3_gen7,
 804             sizeof(pp_pa_load_save_pl3_gen7),
 805             NULL,
 806         },
 807
 808         gen7_pp_plx_avs_initialize,
 809     },
 810
 811     {
 812         {
 813             "RGBX_NV12 module",
 814             PP_RGBX_LOAD_SAVE_NV12,
 815             pp_rgbx_load_save_nv12_gen7,
 816             sizeof(pp_rgbx_load_save_nv12_gen7),
 817             NULL,
 818         },
 819
 820         pp_plx_load_save_plx_initialize,
 821     },
 822
 823     {
 824         {
 825             "NV12_RGBX module",
 826             PP_NV12_LOAD_SAVE_RGBX,
 827             pp_nv12_load_save_rgbx_gen7,
 828             sizeof(pp_nv12_load_save_rgbx_gen7),
 829             NULL,
 830         },
 831
 832         pp_plx_load_save_plx_initialize,
 833     },
 834
 835 };
 836
 837 static int
 838 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 839 {
 840     struct i965_driver_data *i965 = i965_driver_data(ctx);
 841     int fourcc;
 842
 843     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 844         struct object_image *obj_image = IMAGE(surface->id);
 845         fourcc = obj_image->image.format.fourcc;
 846     } else {
 847         struct object_surface *obj_surface = SURFACE(surface->id);
 848         fourcc = obj_surface->fourcc;
 849     }
 850
 851     return fourcc;
 852 }
 853
 854 static void
 855 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 856 {
 857     switch (tiling) {
 858     case I915_TILING_NONE:
 859         ss->ss3.tiled_surface = 0;
 860         ss->ss3.tile_walk = 0;
 861         break;
 862     case I915_TILING_X:
 863         ss->ss3.tiled_surface = 1;
 864         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 865         break;
 866     case I915_TILING_Y:
 867         ss->ss3.tiled_surface = 1;
 868         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 869         break;
 870     }
 871 }
 872
 873 static void
 874 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 875 {
 876     switch (tiling) {
 877     case I915_TILING_NONE:
 878         ss->ss2.tiled_surface = 0;
 879         ss->ss2.tile_walk = 0;
 880         break;
 881     case I915_TILING_X:
 882         ss->ss2.tiled_surface = 1;
 883         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 884         break;
 885     case I915_TILING_Y:
 886         ss->ss2.tiled_surface = 1;
 887         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 888         break;
 889     }
 890 }
 891
 892 static void
 893 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 894 {
 895     switch (tiling) {
 896     case I915_TILING_NONE:
 897         ss->ss0.tiled_surface = 0;
 898         ss->ss0.tile_walk = 0;
 899         break;
 900     case I915_TILING_X:
 901         ss->ss0.tiled_surface = 1;
 902         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 903         break;
 904     case I915_TILING_Y:
 905         ss->ss0.tiled_surface = 1;
 906         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 907         break;
 908     }
 909 }
 910
 911 static void
 912 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 913 {
 914     switch (tiling) {
 915     case I915_TILING_NONE:
 916         ss->ss2.tiled_surface = 0;
 917         ss->ss2.tile_walk = 0;
 918         break;
 919     case I915_TILING_X:
 920         ss->ss2.tiled_surface = 1;
 921         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 922         break;
 923     case I915_TILING_Y:
 924         ss->ss2.tiled_surface = 1;
 925         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 926         break;
 927     }
 928 }
 929
 930 static void
 931 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 932 {
 933     struct i965_interface_descriptor *desc;
 934     dri_bo *bo;
 935     int pp_index = pp_context->current_pp;
 936
 937     bo = pp_context->idrt.bo;
 938     dri_bo_map(bo, 1);
 939     assert(bo->virtual);
 940     desc = bo->virtual;
 941     memset(desc, 0, sizeof(*desc));
 942     desc->desc0.grf_reg_blocks = 10;
 943     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 944     desc->desc1.const_urb_entry_read_offset = 0;
 945     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 946     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 947     desc->desc2.sampler_count = 0;
 948     desc->desc3.binding_table_entry_count = 0;
 949     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 950
 951     dri_bo_emit_reloc(bo,
 952                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 953                       desc->desc0.grf_reg_blocks,
 954                       offsetof(struct i965_interface_descriptor, desc0),
 955                       pp_context->pp_modules[pp_index].kernel.bo);
 956
 957     dri_bo_emit_reloc(bo,
 958                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 959                       desc->desc2.sampler_count << 2,
 960                       offsetof(struct i965_interface_descriptor, desc2),
 961                       pp_context->sampler_state_table.bo);
 962
 963     dri_bo_unmap(bo);
 964     pp_context->idrt.num_interface_descriptors++;
 965 }
 966
 967 static void
 968 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 969 {
 970     struct i965_vfe_state *vfe_state;
 971     dri_bo *bo;
 972
 973     bo = pp_context->vfe_state.bo;
 974     dri_bo_map(bo, 1);
 975     assert(bo->virtual);
 976     vfe_state = bo->virtual;
 977     memset(vfe_state, 0, sizeof(*vfe_state));
 978     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 979     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 980     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 981     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 982     vfe_state->vfe1.children_present = 0;
 983     vfe_state->vfe2.interface_descriptor_base =
 984         pp_context->idrt.bo->offset >> 4; /* reloc */
 985     dri_bo_emit_reloc(bo,
 986                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 987                       0,
 988                       offsetof(struct i965_vfe_state, vfe2),
 989                       pp_context->idrt.bo);
 990     dri_bo_unmap(bo);
 991 }
 992
 993 static void
 994 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 995 {
 996     unsigned char *constant_buffer;
 997     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 998
 999     assert(sizeof(*pp_static_parameter) == 128);
1000     dri_bo_map(pp_context->curbe.bo, 1);
1001     assert(pp_context->curbe.bo->virtual);
1002     constant_buffer = pp_context->curbe.bo->virtual;
1003     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
1004     dri_bo_unmap(pp_context->curbe.bo);
1005 }
1006
1007 static void
1008 ironlake_pp_states_setup(VADriverContextP ctx,
1009                          struct i965_post_processing_context *pp_context)
1010 {
1011     ironlake_pp_interface_descriptor_table(pp_context);
1012     ironlake_pp_vfe_state(pp_context);
1013     ironlake_pp_upload_constants(pp_context);
1014 }
1015
1016 static void
1017 ironlake_pp_pipeline_select(VADriverContextP ctx,
1018                             struct i965_post_processing_context *pp_context)
1019 {
1020     struct intel_batchbuffer *batch = pp_context->batch;
1021
1022     BEGIN_BATCH(batch, 1);
1023     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
1024     ADVANCE_BATCH(batch);
1025 }
1026
1027 static void
1028 ironlake_pp_urb_layout(VADriverContextP ctx,
1029                        struct i965_post_processing_context *pp_context)
1030 {
1031     struct intel_batchbuffer *batch = pp_context->batch;
1032     unsigned int vfe_fence, cs_fence;
1033
1034     vfe_fence = pp_context->urb.cs_start;
1035     cs_fence = pp_context->urb.size;
1036
1037     BEGIN_BATCH(batch, 3);
1038     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
1039     OUT_BATCH(batch, 0);
1040     OUT_BATCH(batch,
1041               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
1042               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
1043     ADVANCE_BATCH(batch);
1044 }
1045
1046 static void
1047 ironlake_pp_state_base_address(VADriverContextP ctx,
1048                                struct i965_post_processing_context *pp_context)
1049 {
1050     struct intel_batchbuffer *batch = pp_context->batch;
1051
1052     BEGIN_BATCH(batch, 8);
1053     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1054     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1055     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1056     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1057     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1058     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1059     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1060     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1061     ADVANCE_BATCH(batch);
1062 }
1063
1064 static void
1065 ironlake_pp_state_pointers(VADriverContextP ctx,
1066                            struct i965_post_processing_context *pp_context)
1067 {
1068     struct intel_batchbuffer *batch = pp_context->batch;
1069
1070     BEGIN_BATCH(batch, 3);
1071     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
1072     OUT_BATCH(batch, 0);
1073     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1074     ADVANCE_BATCH(batch);
1075 }
1076
1077 static void
1078 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
1079                           struct i965_post_processing_context *pp_context)
1080 {
1081     struct intel_batchbuffer *batch = pp_context->batch;
1082
1083     BEGIN_BATCH(batch, 2);
1084     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1085     OUT_BATCH(batch,
1086               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
1087               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
1088     ADVANCE_BATCH(batch);
1089 }
1090
1091 static void
1092 ironlake_pp_constant_buffer(VADriverContextP ctx,
1093                             struct i965_post_processing_context *pp_context)
1094 {
1095     struct intel_batchbuffer *batch = pp_context->batch;
1096
1097     BEGIN_BATCH(batch, 2);
1098     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1099     OUT_RELOC(batch, pp_context->curbe.bo,
1100               I915_GEM_DOMAIN_INSTRUCTION, 0,
1101               pp_context->urb.size_cs_entry - 1);
1102     ADVANCE_BATCH(batch);
1103 }
1104
1105 static void
1106 ironlake_pp_object_walker(VADriverContextP ctx,
1107                           struct i965_post_processing_context *pp_context)
1108 {
1109     struct intel_batchbuffer *batch = pp_context->batch;
1110     int x, x_steps, y, y_steps;
1111     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1112
1113     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1114     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1115
1116     for (y = 0; y < y_steps; y++) {
1117         for (x = 0; x < x_steps; x++) {
1118             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1119                 BEGIN_BATCH(batch, 20);
1120                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1121                 OUT_BATCH(batch, 0);
1122                 OUT_BATCH(batch, 0); /* no indirect data */
1123                 OUT_BATCH(batch, 0);
1124
1125                 /* inline data grf 5-6 */
1126                 assert(sizeof(*pp_inline_parameter) == 64);
1127                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1128
1129                 ADVANCE_BATCH(batch);
1130             }
1131         }
1132     }
1133 }
1134
1135 static void
1136 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1137                            struct i965_post_processing_context *pp_context)
1138 {
1139     struct intel_batchbuffer *batch = pp_context->batch;
1140
1141     intel_batchbuffer_start_atomic(batch, 0x1000);
1142     intel_batchbuffer_emit_mi_flush(batch);
1143     ironlake_pp_pipeline_select(ctx, pp_context);
1144     ironlake_pp_state_base_address(ctx, pp_context);
1145     ironlake_pp_state_pointers(ctx, pp_context);
1146     ironlake_pp_urb_layout(ctx, pp_context);
1147     ironlake_pp_cs_urb_layout(ctx, pp_context);
1148     ironlake_pp_constant_buffer(ctx, pp_context);
1149     ironlake_pp_object_walker(ctx, pp_context);
1150     intel_batchbuffer_end_atomic(batch);
1151 }
1152
1153 // update u/v offset when the surface format are packed yuv
1154 static void i965_update_src_surface_static_parameter(
1155     VADriverContextP    ctx,
1156     struct i965_post_processing_context *pp_context,
1157     const struct i965_surface *surface)
1158 {
1159     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1160     int fourcc = pp_get_surface_fourcc(ctx, surface);
1161
1162     switch (fourcc) {
1163     case VA_FOURCC('Y', 'U', 'Y', '2'):
1164         pp_static_parameter->grf1.source_packed_u_offset = 1;
1165         pp_static_parameter->grf1.source_packed_v_offset = 3;
1166         break;
1167     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1168         pp_static_parameter->grf1.source_packed_y_offset = 1;
1169         pp_static_parameter->grf1.source_packed_v_offset = 2;
1170         break;
1171     case VA_FOURCC('B', 'G', 'R', 'X'):
1172     case VA_FOURCC('B', 'G', 'R', 'A'):
1173         pp_static_parameter->grf1.source_rgb_layout = 0;
1174         break;
1175     case VA_FOURCC('R', 'G', 'B', 'X'):
1176     case VA_FOURCC('R', 'G', 'B', 'A'):
1177         pp_static_parameter->grf1.source_rgb_layout = 1;
1178         break;
1179     default:
1180         break;
1181     }
1182
1183 }
1184
1185 static void i965_update_dst_surface_static_parameter(
1186     VADriverContextP    ctx,
1187     struct i965_post_processing_context *pp_context,
1188     const struct i965_surface *surface)
1189 {
1190     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1191     int fourcc = pp_get_surface_fourcc(ctx, surface);
1192
1193     switch (fourcc) {
1194     case VA_FOURCC('Y', 'U', 'Y', '2'):
1195         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1196         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1197         break;
1198     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1199         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1200         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1201         break;
1202     case VA_FOURCC('B', 'G', 'R', 'X'):
1203     case VA_FOURCC('B', 'G', 'R', 'A'):
1204         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0;
1205         break;
1206     case VA_FOURCC('R', 'G', 'B', 'X'):
1207     case VA_FOURCC('R', 'G', 'B', 'A'):
1208         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1;
1209         break;
1210     default:
1211         break;
1212     }
1213
1214 }
1215
1216 static void
1217 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1218                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1219                           int width, int height, int pitch, int format,
1220                           int index, int is_target)
1221 {
1222     struct i965_surface_state *ss;
1223     dri_bo *ss_bo;
1224     unsigned int tiling;
1225     unsigned int swizzle;
1226
1227     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1228     ss_bo = pp_context->surface_state_binding_table.bo;
1229     assert(ss_bo);
1230
1231     dri_bo_map(ss_bo, True);
1232     assert(ss_bo->virtual);
1233     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1234     memset(ss, 0, sizeof(*ss));
1235     ss->ss0.surface_type = I965_SURFACE_2D;
1236     ss->ss0.surface_format = format;
1237     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1238     ss->ss2.width = width - 1;
1239     ss->ss2.height = height - 1;
1240     ss->ss3.pitch = pitch - 1;
1241     pp_set_surface_tiling(ss, tiling);
1242     dri_bo_emit_reloc(ss_bo,
1243                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1244                       surf_bo_offset,
1245                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1246                       surf_bo);
1247     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1248     dri_bo_unmap(ss_bo);
1249 }
1250
1251 static void
1252 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1253                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1254                            int width, int height, int wpitch,
1255                            int xoffset, int yoffset,
1256                            int format, int interleave_chroma,
1257                            int index)
1258 {
1259     struct i965_surface_state2 *ss2;
1260     dri_bo *ss2_bo;
1261     unsigned int tiling;
1262     unsigned int swizzle;
1263
1264     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1265     ss2_bo = pp_context->surface_state_binding_table.bo;
1266     assert(ss2_bo);
1267
1268     dri_bo_map(ss2_bo, True);
1269     assert(ss2_bo->virtual);
1270     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1271     memset(ss2, 0, sizeof(*ss2));
1272     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1273     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1274     ss2->ss1.width = width - 1;
1275     ss2->ss1.height = height - 1;
1276     ss2->ss2.pitch = wpitch - 1;
1277     ss2->ss2.interleave_chroma = interleave_chroma;
1278     ss2->ss2.surface_format = format;
1279     ss2->ss3.x_offset_for_cb = xoffset;
1280     ss2->ss3.y_offset_for_cb = yoffset;
1281     pp_set_surface2_tiling(ss2, tiling);
1282     dri_bo_emit_reloc(ss2_bo,
1283                       I915_GEM_DOMAIN_RENDER, 0,
1284                       surf_bo_offset,
1285                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1286                       surf_bo);
1287     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1288     dri_bo_unmap(ss2_bo);
1289 }
1290
1291 static void
1292 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1293                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1294                           int width, int height, int pitch, int format,
1295                           int index, int is_target)
1296 {
1297     struct gen7_surface_state *ss;
1298     dri_bo *ss_bo;
1299     unsigned int tiling;
1300     unsigned int swizzle;
1301
1302     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1303     ss_bo = pp_context->surface_state_binding_table.bo;
1304     assert(ss_bo);
1305
1306     dri_bo_map(ss_bo, True);
1307     assert(ss_bo->virtual);
1308     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1309     memset(ss, 0, sizeof(*ss));
1310     ss->ss0.surface_type = I965_SURFACE_2D;
1311     ss->ss0.surface_format = format;
1312     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1313     ss->ss2.width = width - 1;
1314     ss->ss2.height = height - 1;
1315     ss->ss3.pitch = pitch - 1;
1316     gen7_pp_set_surface_tiling(ss, tiling);
1317     dri_bo_emit_reloc(ss_bo,
1318                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1319                       surf_bo_offset,
1320                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1321                       surf_bo);
1322     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1323     dri_bo_unmap(ss_bo);
1324 }
1325
1326 static void
1327 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1328                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1329                            int width, int height, int wpitch,
1330                            int xoffset, int yoffset,
1331                            int format, int interleave_chroma,
1332                            int index)
1333 {
1334     struct gen7_surface_state2 *ss2;
1335     dri_bo *ss2_bo;
1336     unsigned int tiling;
1337     unsigned int swizzle;
1338
1339     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1340     ss2_bo = pp_context->surface_state_binding_table.bo;
1341     assert(ss2_bo);
1342
1343     dri_bo_map(ss2_bo, True);
1344     assert(ss2_bo->virtual);
1345     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1346     memset(ss2, 0, sizeof(*ss2));
1347     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1348     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1349     ss2->ss1.width = width - 1;
1350     ss2->ss1.height = height - 1;
1351     ss2->ss2.pitch = wpitch - 1;
1352     ss2->ss2.interleave_chroma = interleave_chroma;
1353     ss2->ss2.surface_format = format;
1354     ss2->ss3.x_offset_for_cb = xoffset;
1355     ss2->ss3.y_offset_for_cb = yoffset;
1356     gen7_pp_set_surface2_tiling(ss2, tiling);
1357     dri_bo_emit_reloc(ss2_bo,
1358                       I915_GEM_DOMAIN_RENDER, 0,
1359                       surf_bo_offset,
1360                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1361                       surf_bo);
1362     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1363     dri_bo_unmap(ss2_bo);
1364 }
1365
1366 static void
1367 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1368                                 const struct i965_surface *surface,
1369                                 int base_index, int is_target,
1370                                 int *width, int *height, int *pitch, int *offset)
1371 {
1372     struct i965_driver_data *i965 = i965_driver_data(ctx);
1373     struct object_surface *obj_surface;
1374     struct object_image *obj_image;
1375     dri_bo *bo;
1376     int fourcc = pp_get_surface_fourcc(ctx, surface);
1377     const int Y = 0;
1378     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1379     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1380     const int UV = 1;
1381     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1382     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1383     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1384                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1385                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1386                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1387     int scale_factor_of_1st_plane_width_in_byte = 1;
1388
1389     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1390         obj_surface = SURFACE(surface->id);
1391         bo = obj_surface->bo;
1392         width[0] = obj_surface->orig_width;
1393         height[0] = obj_surface->orig_height;
1394         pitch[0] = obj_surface->width;
1395         offset[0] = 0;
1396
1397         if (full_packed_format) {
1398             scale_factor_of_1st_plane_width_in_byte = 4;
1399             pitch[0] = obj_surface->width * 4;
1400         }
1401         else if (packed_yuv ) {
1402             scale_factor_of_1st_plane_width_in_byte =  2;
1403             pitch[0] = obj_surface->width * 2;
1404         }
1405         else if (interleaved_uv) {
1406             width[1] = obj_surface->orig_width;
1407             height[1] = obj_surface->orig_height / 2;
1408             pitch[1] = obj_surface->width;
1409             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1410         } else {
1411             width[1] = obj_surface->orig_width / 2;
1412             height[1] = obj_surface->orig_height / 2;
1413             pitch[1] = obj_surface->width / 2;
1414             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1415             width[2] = obj_surface->orig_width / 2;
1416             height[2] = obj_surface->orig_height / 2;
1417             pitch[2] = obj_surface->width / 2;
1418             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1419         }
1420     } else {
1421         obj_image = IMAGE(surface->id);
1422         bo = obj_image->bo;
1423         width[0] = obj_image->image.width;
1424         height[0] = obj_image->image.height;
1425         pitch[0] = obj_image->image.pitches[0];
1426         offset[0] = obj_image->image.offsets[0];
1427
1428         if (full_packed_format) {
1429             scale_factor_of_1st_plane_width_in_byte = 4;
1430         }
1431         else if (packed_yuv ) {
1432             scale_factor_of_1st_plane_width_in_byte = 2;
1433         }
1434         else if (interleaved_uv) {
1435             width[1] = obj_image->image.width;
1436             height[1] = obj_image->image.height / 2;
1437             pitch[1] = obj_image->image.pitches[1];
1438             offset[1] = obj_image->image.offsets[1];
1439         } else {
1440             width[1] = obj_image->image.width / 2;
1441             height[1] = obj_image->image.height / 2;
1442             pitch[1] = obj_image->image.pitches[1];
1443             offset[1] = obj_image->image.offsets[1];
1444             width[2] = obj_image->image.width / 2;
1445             height[2] = obj_image->image.height / 2;
1446             pitch[2] = obj_image->image.pitches[2];
1447             offset[2] = obj_image->image.offsets[2];
1448         }
1449     }
1450
1451     /* Y surface */
1452     i965_pp_set_surface_state(ctx, pp_context,
1453                               bo, offset[Y],
1454                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1455                               base_index, is_target);
1456
1457     if (!packed_yuv && !full_packed_format) {
1458         if (interleaved_uv) {
1459             i965_pp_set_surface_state(ctx, pp_context,
1460                                       bo, offset[UV],
1461                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1462                                       base_index + 1, is_target);
1463         } else {
1464             /* U surface */
1465             i965_pp_set_surface_state(ctx, pp_context,
1466                                       bo, offset[U],
1467                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1468                                       base_index + 1, is_target);
1469
1470             /* V surface */
1471             i965_pp_set_surface_state(ctx, pp_context,
1472                                       bo, offset[V],
1473                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1474                                       base_index + 2, is_target);
1475         }
1476     }
1477
1478 }
1479
1480 static void
1481 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1482                                      const struct i965_surface *surface,
1483                                      int base_index, int is_target,
1484                                      int *width, int *height, int *pitch, int *offset)
1485 {
1486     struct i965_driver_data *i965 = i965_driver_data(ctx);
1487     struct object_surface *obj_surface;
1488     struct object_image *obj_image;
1489     dri_bo *bo;
1490     int fourcc = pp_get_surface_fourcc(ctx, surface);
1491     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1492                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1493     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1494                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1495     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1496     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1497
1498     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1499         obj_surface = SURFACE(surface->id);
1500         bo = obj_surface->bo;
1501         width[0] = obj_surface->orig_width;
1502         height[0] = obj_surface->orig_height;
1503         pitch[0] = obj_surface->width;
1504         offset[0] = 0;
1505
1506         if (packed_yuv) {
1507             if (is_target)
1508                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1509             else
1510                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1511
1512             pitch[0] = obj_surface->width * 2;
1513         }
1514
1515         width[1] = obj_surface->cb_cr_width;
1516         height[1] = obj_surface->cb_cr_height;
1517         pitch[1] = obj_surface->cb_cr_pitch;
1518         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1519
1520         width[2] = obj_surface->cb_cr_width;
1521         height[2] = obj_surface->cb_cr_height;
1522         pitch[2] = obj_surface->cb_cr_pitch;
1523         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1524     } else {
1525         obj_image = IMAGE(surface->id);
1526         bo = obj_image->bo;
1527         width[0] = obj_image->image.width;
1528         height[0] = obj_image->image.height;
1529         pitch[0] = obj_image->image.pitches[0];
1530         offset[0] = obj_image->image.offsets[0];
1531
1532         if (packed_yuv) {
1533             if (is_target)
1534                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1535             else
1536                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1537         } else if (interleaved_uv) {
1538             width[1] = obj_image->image.width / 2;
1539             height[1] = obj_image->image.height / 2;
1540             pitch[1] = obj_image->image.pitches[1];
1541             offset[1] = obj_image->image.offsets[1];
1542         } else {
1543             width[1] = obj_image->image.width / 2;
1544             height[1] = obj_image->image.height / 2;
1545             pitch[1] = obj_image->image.pitches[U];
1546             offset[1] = obj_image->image.offsets[U];
1547             width[2] = obj_image->image.width / 2;
1548             height[2] = obj_image->image.height / 2;
1549             pitch[2] = obj_image->image.pitches[V];
1550             offset[2] = obj_image->image.offsets[V];
1551         }
1552     }
1553
1554     if (is_target) {
1555         gen7_pp_set_surface_state(ctx, pp_context,
1556                                   bo, 0,
1557                                   width[0] / 4, height[0], pitch[0],
1558                                   I965_SURFACEFORMAT_R8_SINT,
1559                                   base_index, 1);
1560
1561         if (!packed_yuv) {
1562             if (interleaved_uv) {
1563                 gen7_pp_set_surface_state(ctx, pp_context,
1564                                           bo, offset[1],
1565                                           width[1] / 2, height[1], pitch[1],
1566                                           I965_SURFACEFORMAT_R8G8_SINT,
1567                                           base_index + 1, 1);
1568             } else {
1569                 gen7_pp_set_surface_state(ctx, pp_context,
1570                                           bo, offset[1],
1571                                           width[1] / 4, height[1], pitch[1],
1572                                           I965_SURFACEFORMAT_R8_SINT,
1573                                           base_index + 1, 1);
1574                 gen7_pp_set_surface_state(ctx, pp_context,
1575                                           bo, offset[2],
1576                                           width[2] / 4, height[2], pitch[2],
1577                                           I965_SURFACEFORMAT_R8_SINT,
1578                                           base_index + 2, 1);
1579             }
1580         }
1581     } else {
1582         int format0 = SURFACE_FORMAT_Y8_UNORM;
1583
1584         switch (fourcc) {
1585         case VA_FOURCC('Y', 'U', 'Y', '2'):
1586             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1587             break;
1588
1589         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1590             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1591             break;
1592
1593         default:
1594             break;
1595         }
1596
1597         gen7_pp_set_surface2_state(ctx, pp_context,
1598                                    bo, offset[0],
1599                                    width[0], height[0], pitch[0],
1600                                    0, 0,
1601                                    format0, 0,
1602                                    base_index);
1603
1604         if (!packed_yuv) {
1605             if (interleaved_uv) {
1606                 gen7_pp_set_surface2_state(ctx, pp_context,
1607                                            bo, offset[1],
1608                                            width[1], height[1], pitch[1],
1609                                            0, 0,
1610                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1611                                            base_index + 1);
1612             } else {
1613                 gen7_pp_set_surface2_state(ctx, pp_context,
1614                                            bo, offset[1],
1615                                            width[1], height[1], pitch[1],
1616                                            0, 0,
1617                                            SURFACE_FORMAT_R8_UNORM, 0,
1618                                            base_index + 1);
1619                 gen7_pp_set_surface2_state(ctx, pp_context,
1620                                            bo, offset[2],
1621                                            width[2], height[2], pitch[2],
1622                                            0, 0,
1623                                            SURFACE_FORMAT_R8_UNORM, 0,
1624                                            base_index + 2);
1625             }
1626         }
1627     }
1628 }
1629
1630 static int
1631 pp_null_x_steps(void *private_context)
1632 {
1633     return 1;
1634 }
1635
1636 static int
1637 pp_null_y_steps(void *private_context)
1638 {
1639     return 1;
1640 }
1641
1642 static int
1643 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1644 {
1645     return 0;
1646 }
1647
1648 static VAStatus
1649 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1650                    const struct i965_surface *src_surface,
1651                    const VARectangle *src_rect,
1652                    struct i965_surface *dst_surface,
1653                    const VARectangle *dst_rect,
1654                    void *filter_param)
1655 {
1656     /* private function & data */
1657     pp_context->pp_x_steps = pp_null_x_steps;
1658     pp_context->pp_y_steps = pp_null_y_steps;
1659     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1660
1661     dst_surface->flags = src_surface->flags;
1662
1663     return VA_STATUS_SUCCESS;
1664 }
1665
1666 static int
1667 pp_load_save_x_steps(void *private_context)
1668 {
1669     return 1;
1670 }
1671
1672 static int
1673 pp_load_save_y_steps(void *private_context)
1674 {
1675     struct pp_load_save_context *pp_load_save_context = private_context;
1676
1677     return pp_load_save_context->dest_h / 8;
1678 }
1679
1680 static int
1681 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1682 {
1683     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1684
1685     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1686     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1687     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1688     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1689
1690     return 0;
1691 }
1692
1693 static VAStatus
1694 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1695                                 const struct i965_surface *src_surface,
1696                                 const VARectangle *src_rect,
1697                                 struct i965_surface *dst_surface,
1698                                 const VARectangle *dst_rect,
1699                                 void *filter_param)
1700 {
1701     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1702     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1703     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1704     int width[3], height[3], pitch[3], offset[3];
1705     const int Y = 0;
1706
1707     /* source surface */
1708     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1709                                     width, height, pitch, offset);
1710
1711     /* destination surface */
1712     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1713                                     width, height, pitch, offset);
1714
1715     /* private function & data */
1716     pp_context->pp_x_steps = pp_load_save_x_steps;
1717     pp_context->pp_y_steps = pp_load_save_y_steps;
1718     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1719     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1720     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1721
1722     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1723     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1724
1725     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1726     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1727
1728     // update u/v offset for packed yuv
1729     i965_update_src_surface_static_parameter (ctx, pp_context, src_surface);
1730     i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface);
1731
1732     dst_surface->flags = src_surface->flags;
1733
1734     return VA_STATUS_SUCCESS;
1735 }
1736
1737 static int
1738 pp_scaling_x_steps(void *private_context)
1739 {
1740     return 1;
1741 }
1742
1743 static int
1744 pp_scaling_y_steps(void *private_context)
1745 {
1746     struct pp_scaling_context *pp_scaling_context = private_context;
1747
1748     return pp_scaling_context->dest_h / 8;
1749 }
1750
1751 static int
1752 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1753 {
1754     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1755     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1756     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1757     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1758     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1759
1760     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1761     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1762     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1763     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1764
1765     return 0;
1766 }
1767
1768 static VAStatus
1769 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1770                            const struct i965_surface *src_surface,
1771                            const VARectangle *src_rect,
1772                            struct i965_surface *dst_surface,
1773                            const VARectangle *dst_rect,
1774                            void *filter_param)
1775 {
1776     struct i965_driver_data *i965 = i965_driver_data(ctx);
1777     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1778     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1779     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1780     struct object_surface *obj_surface;
1781     struct i965_sampler_state *sampler_state;
1782     int in_w, in_h, in_wpitch, in_hpitch;
1783     int out_w, out_h, out_wpitch, out_hpitch;
1784
1785     /* source surface */
1786     obj_surface = SURFACE(src_surface->id);
1787     in_w = obj_surface->orig_width;
1788     in_h = obj_surface->orig_height;
1789     in_wpitch = obj_surface->width;
1790     in_hpitch = obj_surface->height;
1791
1792     /* source Y surface index 1 */
1793     i965_pp_set_surface_state(ctx, pp_context,
1794                               obj_surface->bo, 0,
1795                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1796                               1, 0);
1797
1798     /* source UV surface index 2 */
1799     i965_pp_set_surface_state(ctx, pp_context,
1800                               obj_surface->bo, in_wpitch * in_hpitch,
1801                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1802                               2, 0);
1803
1804     /* destination surface */
1805     obj_surface = SURFACE(dst_surface->id);
1806     out_w = obj_surface->orig_width;
1807     out_h = obj_surface->orig_height;
1808     out_wpitch = obj_surface->width;
1809     out_hpitch = obj_surface->height;
1810
1811     /* destination Y surface index 7 */
1812     i965_pp_set_surface_state(ctx, pp_context,
1813                               obj_surface->bo, 0,
1814                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1815                               7, 1);
1816
1817     /* destination UV surface index 8 */
1818     i965_pp_set_surface_state(ctx, pp_context,
1819                               obj_surface->bo, out_wpitch * out_hpitch,
1820                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1821                               8, 1);
1822
1823     /* sampler state */
1824     dri_bo_map(pp_context->sampler_state_table.bo, True);
1825     assert(pp_context->sampler_state_table.bo->virtual);
1826     sampler_state = pp_context->sampler_state_table.bo->virtual;
1827
1828     /* SIMD16 Y index 1 */
1829     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1830     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1831     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1832     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1833     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1834
1835     /* SIMD16 UV index 2 */
1836     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1837     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1838     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1839     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1840     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1841
1842     dri_bo_unmap(pp_context->sampler_state_table.bo);
1843
1844     /* private function & data */
1845     pp_context->pp_x_steps = pp_scaling_x_steps;
1846     pp_context->pp_y_steps = pp_scaling_y_steps;
1847     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1848
1849     pp_scaling_context->dest_x = dst_rect->x;
1850     pp_scaling_context->dest_y = dst_rect->y;
1851     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1852     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1853     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1854     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1855
1856     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1857
1858     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1859     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1860     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1861     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1862     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1863
1864     dst_surface->flags = src_surface->flags;
1865
1866     return VA_STATUS_SUCCESS;
1867 }
1868
1869 static int
1870 pp_avs_x_steps(void *private_context)
1871 {
1872     struct pp_avs_context *pp_avs_context = private_context;
1873
1874     return pp_avs_context->dest_w / 16;
1875 }
1876
1877 static int
1878 pp_avs_y_steps(void *private_context)
1879 {
1880     return 1;
1881 }
1882
1883 static int
1884 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1885 {
1886     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1887     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1888     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1889     float src_x_steping, src_y_steping, video_step_delta;
1890     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1891
1892     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1893         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1894         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1895     } else if (tmp_w >= pp_avs_context->dest_w) {
1896         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1897         pp_inline_parameter->grf6.video_step_delta = 0;
1898
1899         if (x == 0) {
1900             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1901                 pp_avs_context->src_normalized_x;
1902         } else {
1903             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1904             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1905             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1906                 16 * 15 * video_step_delta / 2;
1907         }
1908     } else {
1909         int n0, n1, n2, nls_left, nls_right;
1910         int factor_a = 5, factor_b = 4;
1911         float f;
1912
1913         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1914         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1915         n2 = tmp_w / (16 * factor_a);
1916         nls_left = n0 + n2;
1917         nls_right = n1 + n2;
1918         f = (float) n2 * 16 / tmp_w;
1919
1920         if (n0 < 5) {
1921             pp_inline_parameter->grf6.video_step_delta = 0.0;
1922
1923             if (x == 0) {
1924                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1925                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1926             } else {
1927                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1928                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1929                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1930                     16 * 15 * video_step_delta / 2;
1931             }
1932         } else {
1933             if (x < nls_left) {
1934                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1935                 float a = f / (nls_left * 16 * factor_b);
1936                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1937
1938                 pp_inline_parameter->grf6.video_step_delta = b;
1939
1940                 if (x == 0) {
1941                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1942                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1943                 } else {
1944                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1945                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1946                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1947                         16 * 15 * video_step_delta / 2;
1948                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1949                 }
1950             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1951                 /* scale the center linearly */
1952                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1953                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1954                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1955                     16 * 15 * video_step_delta / 2;
1956                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1957                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1958             } else {
1959                 float a = f / (nls_right * 16 * factor_b);
1960                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1961
1962                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1963                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1964                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1965                     16 * 15 * video_step_delta / 2;
1966                 pp_inline_parameter->grf6.video_step_delta = -b;
1967
1968                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1969                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1970                 else
1971                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1972             }
1973         }
1974     }
1975
1976     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1977     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1978     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1979     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1980
1981     return 0;
1982 }
1983
1984 static VAStatus
1985 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1986                        const struct i965_surface *src_surface,
1987                        const VARectangle *src_rect,
1988                        struct i965_surface *dst_surface,
1989                        const VARectangle *dst_rect,
1990                        void *filter_param,
1991                        int nlas)
1992 {
1993     struct i965_driver_data *i965 = i965_driver_data(ctx);
1994     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1995     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1996     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1997     struct object_surface *obj_surface;
1998     struct i965_sampler_8x8 *sampler_8x8;
1999     struct i965_sampler_8x8_state *sampler_8x8_state;
2000     int index;
2001     int in_w, in_h, in_wpitch, in_hpitch;
2002     int out_w, out_h, out_wpitch, out_hpitch;
2003     int i;
2004
2005     /* surface */
2006     obj_surface = SURFACE(src_surface->id);
2007     in_w = obj_surface->orig_width;
2008     in_h = obj_surface->orig_height;
2009     in_wpitch = obj_surface->width;
2010     in_hpitch = obj_surface->height;
2011
2012     /* source Y surface index 1 */
2013     i965_pp_set_surface2_state(ctx, pp_context,
2014                                obj_surface->bo, 0,
2015                                in_w, in_h, in_wpitch,
2016                                0, 0,
2017                                SURFACE_FORMAT_Y8_UNORM, 0,
2018                                1);
2019
2020     /* source UV surface index 2 */
2021     i965_pp_set_surface2_state(ctx, pp_context,
2022                                obj_surface->bo, in_wpitch * in_hpitch,
2023                                in_w / 2, in_h / 2, in_wpitch,
2024                                0, 0,
2025                                SURFACE_FORMAT_R8B8_UNORM, 0,
2026                                2);
2027
2028     /* destination surface */
2029     obj_surface = SURFACE(dst_surface->id);
2030     out_w = obj_surface->orig_width;
2031     out_h = obj_surface->orig_height;
2032     out_wpitch = obj_surface->width;
2033     out_hpitch = obj_surface->height;
2034     assert(out_w <= out_wpitch && out_h <= out_hpitch);
2035
2036     /* destination Y surface index 7 */
2037     i965_pp_set_surface_state(ctx, pp_context,
2038                               obj_surface->bo, 0,
2039                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2040                               7, 1);
2041
2042     /* destination UV surface index 8 */
2043     i965_pp_set_surface_state(ctx, pp_context,
2044                               obj_surface->bo, out_wpitch * out_hpitch,
2045                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2046                               8, 1);
2047
2048     /* sampler 8x8 state */
2049     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2050     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2051     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2052     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2053     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2054
2055     for (i = 0; i < 17; i++) {
2056         /* for Y channel, currently ignore */
2057         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
2058         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
2059         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
2060         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
2061         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
2062         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
2063         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
2064         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
2065         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
2066         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
2067         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
2068         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
2069         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
2070         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
2071         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
2072         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
2073         /* for U/V channel, 0.25 */
2074         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2075         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2076         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2077         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2078         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2079         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2080         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2081         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2082         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2083         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2084         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2085         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2086         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2087         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2088         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2089         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2090     }
2091
2092     sampler_8x8_state->dw136.default_sharpness_level = 0;
2093     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2094     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2095     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2096     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2097
2098     /* sampler 8x8 */
2099     dri_bo_map(pp_context->sampler_state_table.bo, True);
2100     assert(pp_context->sampler_state_table.bo->virtual);
2101     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
2102     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2103
2104     /* sample_8x8 Y index 1 */
2105     index = 1;
2106     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2107     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2108     sampler_8x8[index].dw0.ief_bypass = 1;
2109     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2110     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2111     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2112     sampler_8x8[index].dw2.global_noise_estimation = 22;
2113     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2114     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2115     sampler_8x8[index].dw3.strong_edge_weight = 7;
2116     sampler_8x8[index].dw3.regular_weight = 2;
2117     sampler_8x8[index].dw3.non_edge_weight = 0;
2118     sampler_8x8[index].dw3.gain_factor = 40;
2119     sampler_8x8[index].dw4.steepness_boost = 0;
2120     sampler_8x8[index].dw4.steepness_threshold = 0;
2121     sampler_8x8[index].dw4.mr_boost = 0;
2122     sampler_8x8[index].dw4.mr_threshold = 5;
2123     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2124     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2125     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2126     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2127     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2128     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2129     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2130     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2131     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2132     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2133     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2134     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2135     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2136     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2137     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2138     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2139     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2140     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2141     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2142     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2143     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2144     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2145     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2146     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2147     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2148     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2149     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2150     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2151     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2152     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2153     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2154     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2155     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2156     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2157     sampler_8x8[index].dw13.limiter_boost = 0;
2158     sampler_8x8[index].dw13.minimum_limiter = 10;
2159     sampler_8x8[index].dw13.maximum_limiter = 11;
2160     sampler_8x8[index].dw14.clip_limiter = 130;
2161     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2162                       I915_GEM_DOMAIN_RENDER,
2163                       0,
2164                       0,
2165                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2166                       pp_context->sampler_state_table.bo_8x8);
2167
2168     /* sample_8x8 UV index 2 */
2169     index = 2;
2170     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2171     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2172     sampler_8x8[index].dw0.ief_bypass = 1;
2173     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2174     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2175     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2176     sampler_8x8[index].dw2.global_noise_estimation = 22;
2177     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2178     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2179     sampler_8x8[index].dw3.strong_edge_weight = 7;
2180     sampler_8x8[index].dw3.regular_weight = 2;
2181     sampler_8x8[index].dw3.non_edge_weight = 0;
2182     sampler_8x8[index].dw3.gain_factor = 40;
2183     sampler_8x8[index].dw4.steepness_boost = 0;
2184     sampler_8x8[index].dw4.steepness_threshold = 0;
2185     sampler_8x8[index].dw4.mr_boost = 0;
2186     sampler_8x8[index].dw4.mr_threshold = 5;
2187     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2188     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2189     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2190     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2191     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2192     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2193     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2194     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2195     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2196     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2197     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2198     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2199     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2200     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2201     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2202     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2203     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2204     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2205     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2206     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2207     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2208     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2209     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2210     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2211     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2212     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2213     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2214     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2215     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2216     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2217     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2218     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2219     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2220     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2221     sampler_8x8[index].dw13.limiter_boost = 0;
2222     sampler_8x8[index].dw13.minimum_limiter = 10;
2223     sampler_8x8[index].dw13.maximum_limiter = 11;
2224     sampler_8x8[index].dw14.clip_limiter = 130;
2225     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2226                       I915_GEM_DOMAIN_RENDER,
2227                       0,
2228                       0,
2229                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2230                       pp_context->sampler_state_table.bo_8x8);
2231
2232     dri_bo_unmap(pp_context->sampler_state_table.bo);
2233
2234     /* private function & data */
2235     pp_context->pp_x_steps = pp_avs_x_steps;
2236     pp_context->pp_y_steps = pp_avs_y_steps;
2237     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2238
2239     pp_avs_context->dest_x = dst_rect->x;
2240     pp_avs_context->dest_y = dst_rect->y;
2241     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2242     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2243     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2244     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2245     pp_avs_context->src_w = src_rect->width;
2246     pp_avs_context->src_h = src_rect->height;
2247
2248     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2249     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2250
2251     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2252     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2253     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2254     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2255     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2256     pp_inline_parameter->grf6.video_step_delta = 0.0;
2257
2258     dst_surface->flags = src_surface->flags;
2259
2260     return VA_STATUS_SUCCESS;
2261 }
2262
2263 static VAStatus
2264 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2265                             const struct i965_surface *src_surface,
2266                             const VARectangle *src_rect,
2267                             struct i965_surface *dst_surface,
2268                             const VARectangle *dst_rect,
2269                             void *filter_param)
2270 {
2271     return pp_nv12_avs_initialize(ctx, pp_context,
2272                                   src_surface,
2273                                   src_rect,
2274                                   dst_surface,
2275                                   dst_rect,
2276                                   filter_param,
2277                                   1);
2278 }
2279
2280 static VAStatus
2281 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2282                              const struct i965_surface *src_surface,
2283                              const VARectangle *src_rect,
2284                              struct i965_surface *dst_surface,
2285                              const VARectangle *dst_rect,
2286                              void *filter_param)
2287 {
2288     return pp_nv12_avs_initialize(ctx, pp_context,
2289                                   src_surface,
2290                                   src_rect,
2291                                   dst_surface,
2292                                   dst_rect,
2293                                   filter_param,
2294                                   0);
2295 }
2296
2297 static int
2298 gen7_pp_avs_x_steps(void *private_context)
2299 {
2300     struct pp_avs_context *pp_avs_context = private_context;
2301
2302     return pp_avs_context->dest_w / 16;
2303 }
2304
2305 static int
2306 gen7_pp_avs_y_steps(void *private_context)
2307 {
2308     struct pp_avs_context *pp_avs_context = private_context;
2309
2310     return pp_avs_context->dest_h / 16;
2311 }
2312
2313 static int
2314 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2315 {
2316     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2317     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2318
2319     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2320     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2321     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2322     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2323
2324     return 0;
2325 }
2326
2327 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2328                                               struct i965_post_processing_context *pp_context,
2329                                               const struct i965_surface *surface)
2330 {
2331     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2332     int fourcc = pp_get_surface_fourcc(ctx, surface);
2333
2334     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2335         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2336         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2337         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2338     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2339         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2340         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2341         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2342     }
2343 }
2344
2345 static VAStatus
2346 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2347                            const struct i965_surface *src_surface,
2348                            const VARectangle *src_rect,
2349                            struct i965_surface *dst_surface,
2350                            const VARectangle *dst_rect,
2351                            void *filter_param)
2352 {
2353     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2354     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2355     struct gen7_sampler_8x8 *sampler_8x8;
2356     struct i965_sampler_8x8_state *sampler_8x8_state;
2357     int index, i;
2358     int width[3], height[3], pitch[3], offset[3];
2359
2360     /* source surface */
2361     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2362                                          width, height, pitch, offset);
2363
2364     /* destination surface */
2365     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2366                                          width, height, pitch, offset);
2367
2368     /* sampler 8x8 state */
2369     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2370     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2371     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2372     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2373     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2374
2375     for (i = 0; i < 17; i++) {
2376         /* for Y channel, currently ignore */
2377         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2378         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2379         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2380         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2381         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2382         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2383         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2384         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2385         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2386         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2387         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2388         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2389         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2390         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2391         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2392         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2393         /* for U/V channel, 0.25 */
2394         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2395         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2396         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2397         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2398         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2399         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2400         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2401         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2402         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2403         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2404         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2405         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2406         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2407         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2408         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2409         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2410     }
2411
2412     sampler_8x8_state->dw136.default_sharpness_level = 0;
2413     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2414     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2415     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2416     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2417
2418     /* sampler 8x8 */
2419     dri_bo_map(pp_context->sampler_state_table.bo, True);
2420     assert(pp_context->sampler_state_table.bo->virtual);
2421     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2422     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2423
2424     /* sample_8x8 Y index 4 */
2425     index = 4;
2426     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2427     sampler_8x8[index].dw0.global_noise_estimation = 255;
2428     sampler_8x8[index].dw0.ief_bypass = 1;
2429
2430     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2431
2432     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2433     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2434     sampler_8x8[index].dw2.r5x_coefficient = 9;
2435     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2436     sampler_8x8[index].dw2.r5c_coefficient = 3;
2437
2438     sampler_8x8[index].dw3.r3x_coefficient = 27;
2439     sampler_8x8[index].dw3.r3c_coefficient = 5;
2440     sampler_8x8[index].dw3.gain_factor = 40;
2441     sampler_8x8[index].dw3.non_edge_weight = 1;
2442     sampler_8x8[index].dw3.regular_weight = 2;
2443     sampler_8x8[index].dw3.strong_edge_weight = 7;
2444     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2445
2446     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2447                       I915_GEM_DOMAIN_RENDER,
2448                       0,
2449                       0,
2450                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2451                       pp_context->sampler_state_table.bo_8x8);
2452
2453     /* sample_8x8 UV index 8 */
2454     index = 8;
2455     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2456     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2457     sampler_8x8[index].dw0.global_noise_estimation = 255;
2458     sampler_8x8[index].dw0.ief_bypass = 1;
2459     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2460     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2461     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2462     sampler_8x8[index].dw2.r5x_coefficient = 9;
2463     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2464     sampler_8x8[index].dw2.r5c_coefficient = 3;
2465     sampler_8x8[index].dw3.r3x_coefficient = 27;
2466     sampler_8x8[index].dw3.r3c_coefficient = 5;
2467     sampler_8x8[index].dw3.gain_factor = 40;
2468     sampler_8x8[index].dw3.non_edge_weight = 1;
2469     sampler_8x8[index].dw3.regular_weight = 2;
2470     sampler_8x8[index].dw3.strong_edge_weight = 7;
2471     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2472
2473     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2474                       I915_GEM_DOMAIN_RENDER,
2475                       0,
2476                       0,
2477                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2478                       pp_context->sampler_state_table.bo_8x8);
2479
2480     /* sampler_8x8 V, index 12 */
2481     index = 12;
2482     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2483     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2484     sampler_8x8[index].dw0.global_noise_estimation = 255;
2485     sampler_8x8[index].dw0.ief_bypass = 1;
2486     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2487     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2488     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2489     sampler_8x8[index].dw2.r5x_coefficient = 9;
2490     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2491     sampler_8x8[index].dw2.r5c_coefficient = 3;
2492     sampler_8x8[index].dw3.r3x_coefficient = 27;
2493     sampler_8x8[index].dw3.r3c_coefficient = 5;
2494     sampler_8x8[index].dw3.gain_factor = 40;
2495     sampler_8x8[index].dw3.non_edge_weight = 1;
2496     sampler_8x8[index].dw3.regular_weight = 2;
2497     sampler_8x8[index].dw3.strong_edge_weight = 7;
2498     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2499
2500     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2501                       I915_GEM_DOMAIN_RENDER,
2502                       0,
2503                       0,
2504                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2505                       pp_context->sampler_state_table.bo_8x8);
2506
2507     dri_bo_unmap(pp_context->sampler_state_table.bo);
2508
2509     /* private function & data */
2510     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2511     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2512     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2513
2514     pp_avs_context->dest_x = dst_rect->x;
2515     pp_avs_context->dest_y = dst_rect->y;
2516     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2517     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2518     pp_avs_context->src_w = src_rect->width;
2519     pp_avs_context->src_h = src_rect->height;
2520
2521     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2522     dw = MAX(dw, pp_avs_context->dest_w);
2523
2524     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2525     pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */
2526     pp_static_parameter->grf2.avs_wa_width = dw;
2527     pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw);
2528     pp_static_parameter->grf2.avs_wa_five_div_256_width = (float) 5.0 / (256 * dw);
2529
2530     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2531     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2532     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2533     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2534
2535     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2536
2537     dst_surface->flags = src_surface->flags;
2538
2539     return VA_STATUS_SUCCESS;
2540 }
2541
2542 static int
2543 pp_dndi_x_steps(void *private_context)
2544 {
2545     return 1;
2546 }
2547
2548 static int
2549 pp_dndi_y_steps(void *private_context)
2550 {
2551     struct pp_dndi_context *pp_dndi_context = private_context;
2552
2553     return pp_dndi_context->dest_h / 4;
2554 }
2555
2556 static int
2557 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2558 {
2559     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2560
2561     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2562     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2563
2564     return 0;
2565 }
2566
2567 static VAStatus
2568 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2569                         const struct i965_surface *src_surface,
2570                         const VARectangle *src_rect,
2571                         struct i965_surface *dst_surface,
2572                         const VARectangle *dst_rect,
2573                         void *filter_param)
2574 {
2575     struct i965_driver_data *i965 = i965_driver_data(ctx);
2576     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2577     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2578     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2579     struct object_surface *obj_surface;
2580     struct i965_sampler_dndi *sampler_dndi;
2581     int index;
2582     int w, h;
2583     int orig_w, orig_h;
2584     int dndi_top_first = 1;
2585
2586     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2587         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2588
2589     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2590         dndi_top_first = 1;
2591     else
2592         dndi_top_first = 0;
2593
2594     /* surface */
2595     obj_surface = SURFACE(src_surface->id);
2596     orig_w = obj_surface->orig_width;
2597     orig_h = obj_surface->orig_height;
2598     w = obj_surface->width;
2599     h = obj_surface->height;
2600
2601     if (pp_context->stmm.bo == NULL) {
2602         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2603                                            "STMM surface",
2604                                            w * h,
2605                                            4096);
2606         assert(pp_context->stmm.bo);
2607     }
2608
2609     /* source UV surface index 2 */
2610     i965_pp_set_surface_state(ctx, pp_context,
2611                               obj_surface->bo, w * h,
2612                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2613                               2, 0);
2614
2615     /* source YUV surface index 4 */
2616     i965_pp_set_surface2_state(ctx, pp_context,
2617                                obj_surface->bo, 0,
2618                                orig_w, orig_h, w,
2619                                0, h,
2620                                SURFACE_FORMAT_PLANAR_420_8, 1,
2621                                4);
2622
2623     /* source STMM surface index 20 */
2624     i965_pp_set_surface_state(ctx, pp_context,
2625                               pp_context->stmm.bo, 0,
2626                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2627                               20, 1);
2628
2629     /* destination surface */
2630     obj_surface = SURFACE(dst_surface->id);
2631     orig_w = obj_surface->orig_width;
2632     orig_h = obj_surface->orig_height;
2633     w = obj_surface->width;
2634     h = obj_surface->height;
2635
2636     /* destination Y surface index 7 */
2637     i965_pp_set_surface_state(ctx, pp_context,
2638                               obj_surface->bo, 0,
2639                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2640                               7, 1);
2641
2642     /* destination UV surface index 8 */
2643     i965_pp_set_surface_state(ctx, pp_context,
2644                               obj_surface->bo, w * h,
2645                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2646                               8, 1);
2647     /* sampler dndi */
2648     dri_bo_map(pp_context->sampler_state_table.bo, True);
2649     assert(pp_context->sampler_state_table.bo->virtual);
2650     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2651     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2652
2653     /* sample dndi index 1 */
2654     index = 0;
2655     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2656     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2657     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2658     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2659
2660     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2661     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2662     sampler_dndi[index].dw1.stmm_c2 = 1;
2663     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2664     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2665
2666     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2667     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2668     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2669     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2670
2671     sampler_dndi[index].dw3.maximum_stmm = 128;
2672     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2673     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2674     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2675     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2676
2677     sampler_dndi[index].dw4.sdi_delta = 8;
2678     sampler_dndi[index].dw4.sdi_threshold = 128;
2679     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2680     sampler_dndi[index].dw4.stmm_shift_up = 0;
2681     sampler_dndi[index].dw4.stmm_shift_down = 0;
2682     sampler_dndi[index].dw4.minimum_stmm = 0;
2683
2684     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2685     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2686     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2687     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2688
2689     sampler_dndi[index].dw6.dn_enable = 1;
2690     sampler_dndi[index].dw6.di_enable = 1;
2691     sampler_dndi[index].dw6.di_partial = 0;
2692     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2693     sampler_dndi[index].dw6.dndi_stream_id = 0;
2694     sampler_dndi[index].dw6.dndi_first_frame = 1;
2695     sampler_dndi[index].dw6.progressive_dn = 0;
2696     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2697     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2698     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2699
2700     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2701     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2702     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2703     sampler_dndi[index].dw7.column_width_minus1 = 0;
2704
2705     dri_bo_unmap(pp_context->sampler_state_table.bo);
2706
2707     /* private function & data */
2708     pp_context->pp_x_steps = pp_dndi_x_steps;
2709     pp_context->pp_y_steps = pp_dndi_y_steps;
2710     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2711
2712     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2713     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2714     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2715     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2716
2717     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2718     pp_inline_parameter->grf5.number_blocks = w / 16;
2719     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2720     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2721
2722     pp_dndi_context->dest_w = w;
2723     pp_dndi_context->dest_h = h;
2724
2725     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2726
2727     return VA_STATUS_SUCCESS;
2728 }
2729
2730 static int
2731 pp_dn_x_steps(void *private_context)
2732 {
2733     return 1;
2734 }
2735
2736 static int
2737 pp_dn_y_steps(void *private_context)
2738 {
2739     struct pp_dn_context *pp_dn_context = private_context;
2740
2741     return pp_dn_context->dest_h / 8;
2742 }
2743
2744 static int
2745 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2746 {
2747     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2748
2749     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2750     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2751
2752     return 0;
2753 }
2754
2755 static VAStatus
2756 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2757                       const struct i965_surface *src_surface,
2758                       const VARectangle *src_rect,
2759                       struct i965_surface *dst_surface,
2760                       const VARectangle *dst_rect,
2761                       void *filter_param)
2762 {
2763     struct i965_driver_data *i965 = i965_driver_data(ctx);
2764     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2765     struct object_surface *obj_surface;
2766     struct i965_sampler_dndi *sampler_dndi;
2767     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2768     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2769     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2770     int index;
2771     int w, h;
2772     int orig_w, orig_h;
2773     int dn_strength = 15;
2774     int dndi_top_first = 1;
2775     int dn_progressive = 0;
2776
2777     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2778         dndi_top_first = 1;
2779         dn_progressive = 1;
2780     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2781         dndi_top_first = 1;
2782         dn_progressive = 0;
2783     } else {
2784         dndi_top_first = 0;
2785         dn_progressive = 0;
2786     }
2787
2788     if (dn_filter_param) {
2789         float value = dn_filter_param->value;
2790
2791         if (value > 1.0)
2792             value = 1.0;
2793
2794         if (value < 0.0)
2795             value = 0.0;
2796
2797         dn_strength = (int)(value * 31.0F);
2798     }
2799
2800     /* surface */
2801     obj_surface = SURFACE(src_surface->id);
2802     orig_w = obj_surface->orig_width;
2803     orig_h = obj_surface->orig_height;
2804     w = obj_surface->width;
2805     h = obj_surface->height;
2806
2807     if (pp_context->stmm.bo == NULL) {
2808         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2809                                            "STMM surface",
2810                                            w * h,
2811                                            4096);
2812         assert(pp_context->stmm.bo);
2813     }
2814
2815     /* source UV surface index 2 */
2816     i965_pp_set_surface_state(ctx, pp_context,
2817                               obj_surface->bo, w * h,
2818                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2819                               2, 0);
2820
2821     /* source YUV surface index 4 */
2822     i965_pp_set_surface2_state(ctx, pp_context,
2823                                obj_surface->bo, 0,
2824                                orig_w, orig_h, w,
2825                                0, h,
2826                                SURFACE_FORMAT_PLANAR_420_8, 1,
2827                                4);
2828
2829     /* source STMM surface index 20 */
2830     i965_pp_set_surface_state(ctx, pp_context,
2831                               pp_context->stmm.bo, 0,
2832                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2833                               20, 1);
2834
2835     /* destination surface */
2836     obj_surface = SURFACE(dst_surface->id);
2837     orig_w = obj_surface->orig_width;
2838     orig_h = obj_surface->orig_height;
2839     w = obj_surface->width;
2840     h = obj_surface->height;
2841
2842     /* destination Y surface index 7 */
2843     i965_pp_set_surface_state(ctx, pp_context,
2844                               obj_surface->bo, 0,
2845                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2846                               7, 1);
2847
2848     /* destination UV surface index 8 */
2849     i965_pp_set_surface_state(ctx, pp_context,
2850                               obj_surface->bo, w * h,
2851                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2852                               8, 1);
2853     /* sampler dn */
2854     dri_bo_map(pp_context->sampler_state_table.bo, True);
2855     assert(pp_context->sampler_state_table.bo->virtual);
2856     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2857     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2858
2859     /* sample dndi index 1 */
2860     index = 0;
2861     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2862     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2863     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2864     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2865
2866     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2867     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2868     sampler_dndi[index].dw1.stmm_c2 = 0;
2869     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2870     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2871
2872     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2873     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2874     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2875     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2876
2877     sampler_dndi[index].dw3.maximum_stmm = 128;
2878     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2879     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2880     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2881     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2882
2883     sampler_dndi[index].dw4.sdi_delta = 8;
2884     sampler_dndi[index].dw4.sdi_threshold = 128;
2885     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2886     sampler_dndi[index].dw4.stmm_shift_up = 0;
2887     sampler_dndi[index].dw4.stmm_shift_down = 0;
2888     sampler_dndi[index].dw4.minimum_stmm = 0;
2889
2890     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2891     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2892     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2893     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2894
2895     sampler_dndi[index].dw6.dn_enable = 1;
2896     sampler_dndi[index].dw6.di_enable = 0;
2897     sampler_dndi[index].dw6.di_partial = 0;
2898     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2899     sampler_dndi[index].dw6.dndi_stream_id = 1;
2900     sampler_dndi[index].dw6.dndi_first_frame = 1;
2901     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2902     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2903     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2904     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2905
2906     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2907     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2908     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2909     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2910
2911     dri_bo_unmap(pp_context->sampler_state_table.bo);
2912
2913     /* private function & data */
2914     pp_context->pp_x_steps = pp_dn_x_steps;
2915     pp_context->pp_y_steps = pp_dn_y_steps;
2916     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2917
2918     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2919     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2920     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2921     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2922
2923     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2924     pp_inline_parameter->grf5.number_blocks = w / 16;
2925     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2926     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2927
2928     pp_dn_context->dest_w = w;
2929     pp_dn_context->dest_h = h;
2930
2931     dst_surface->flags = src_surface->flags;
2932
2933     return VA_STATUS_SUCCESS;
2934 }
2935
2936 static int
2937 gen7_pp_dndi_x_steps(void *private_context)
2938 {
2939     struct pp_dndi_context *pp_dndi_context = private_context;
2940
2941     return pp_dndi_context->dest_w / 16;
2942 }
2943
2944 static int
2945 gen7_pp_dndi_y_steps(void *private_context)
2946 {
2947     struct pp_dndi_context *pp_dndi_context = private_context;
2948
2949     return pp_dndi_context->dest_h / 4;
2950 }
2951
2952 static int
2953 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2954 {
2955     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2956
2957     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2958     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2959
2960     return 0;
2961 }
2962
2963 static VAStatus
2964 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2965                              const struct i965_surface *src_surface,
2966                              const VARectangle *src_rect,
2967                              struct i965_surface *dst_surface,
2968                              const VARectangle *dst_rect,
2969                              void *filter_param)
2970 {
2971     struct i965_driver_data *i965 = i965_driver_data(ctx);
2972     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2973     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2974     struct object_surface *obj_surface;
2975     struct gen7_sampler_dndi *sampler_dndi;
2976     int index;
2977     int w, h;
2978     int orig_w, orig_h;
2979     int dndi_top_first = 1;
2980
2981     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2982         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2983
2984     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2985         dndi_top_first = 1;
2986     else
2987         dndi_top_first = 0;
2988
2989     /* surface */
2990     obj_surface = SURFACE(src_surface->id);
2991     orig_w = obj_surface->orig_width;
2992     orig_h = obj_surface->orig_height;
2993     w = obj_surface->width;
2994     h = obj_surface->height;
2995
2996     if (pp_context->stmm.bo == NULL) {
2997         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2998                                            "STMM surface",
2999                                            w * h,
3000                                            4096);
3001         assert(pp_context->stmm.bo);
3002     }
3003
3004     /* source UV surface index 1 */
3005     gen7_pp_set_surface_state(ctx, pp_context,
3006                               obj_surface->bo, w * h,
3007                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3008                               1, 0);
3009
3010     /* source YUV surface index 3 */
3011     gen7_pp_set_surface2_state(ctx, pp_context,
3012                                obj_surface->bo, 0,
3013                                orig_w, orig_h, w,
3014                                0, h,
3015                                SURFACE_FORMAT_PLANAR_420_8, 1,
3016                                3);
3017
3018     /* source (temporal reference) YUV surface index 4 */
3019     gen7_pp_set_surface2_state(ctx, pp_context,
3020                                obj_surface->bo, 0,
3021                                orig_w, orig_h, w,
3022                                0, h,
3023                                SURFACE_FORMAT_PLANAR_420_8, 1,
3024                                4);
3025
3026     /* STMM / History Statistics input surface, index 5 */
3027     gen7_pp_set_surface_state(ctx, pp_context,
3028                               pp_context->stmm.bo, 0,
3029                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3030                               5, 1);
3031
3032     /* destination surface */
3033     obj_surface = SURFACE(dst_surface->id);
3034     orig_w = obj_surface->orig_width;
3035     orig_h = obj_surface->orig_height;
3036     w = obj_surface->width;
3037     h = obj_surface->height;
3038
3039     /* destination(Previous frame) Y surface index 27 */
3040     gen7_pp_set_surface_state(ctx, pp_context,
3041                               obj_surface->bo, 0,
3042                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3043                               27, 1);
3044
3045     /* destination(Previous frame) UV surface index 28 */
3046     gen7_pp_set_surface_state(ctx, pp_context,
3047                               obj_surface->bo, w * h,
3048                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3049                               28, 1);
3050
3051     /* destination(Current frame) Y surface index 30 */
3052     gen7_pp_set_surface_state(ctx, pp_context,
3053                               obj_surface->bo, 0,
3054                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3055                               30, 1);
3056
3057     /* destination(Current frame) UV surface index 31 */
3058     gen7_pp_set_surface_state(ctx, pp_context,
3059                               obj_surface->bo, w * h,
3060                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3061                               31, 1);
3062
3063     /* STMM output surface, index 33 */
3064     gen7_pp_set_surface_state(ctx, pp_context,
3065                               pp_context->stmm.bo, 0,
3066                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3067                               33, 1);
3068
3069
3070     /* sampler dndi */
3071     dri_bo_map(pp_context->sampler_state_table.bo, True);
3072     assert(pp_context->sampler_state_table.bo->virtual);
3073     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
3074     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
3075
3076     /* sample dndi index 0 */
3077     index = 0;
3078     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
3079     sampler_dndi[index].dw0.dnmh_delt = 8;
3080     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
3081     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
3082     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
3083     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
3084
3085     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3086     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
3087     sampler_dndi[index].dw1.stmm_c2 = 0;
3088     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
3089     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
3090
3091     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
3092     sampler_dndi[index].dw2.bne_edge_th = 1;
3093     sampler_dndi[index].dw2.smooth_mv_th = 0;
3094     sampler_dndi[index].dw2.sad_tight_th = 5;
3095     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
3096     sampler_dndi[index].dw2.good_neighbor_th = 4;
3097
3098     sampler_dndi[index].dw3.maximum_stmm = 128;
3099     sampler_dndi[index].dw3.multipler_for_vecm = 2;
3100     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3101     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3102     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
3103
3104     sampler_dndi[index].dw4.sdi_delta = 8;
3105     sampler_dndi[index].dw4.sdi_threshold = 128;
3106     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3107     sampler_dndi[index].dw4.stmm_shift_up = 0;
3108     sampler_dndi[index].dw4.stmm_shift_down = 0;
3109     sampler_dndi[index].dw4.minimum_stmm = 0;
3110
3111     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
3112     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
3113     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3114     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3115
3116     sampler_dndi[index].dw6.dn_enable = 0;
3117     sampler_dndi[index].dw6.di_enable = 1;
3118     sampler_dndi[index].dw6.di_partial = 0;
3119     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
3120     sampler_dndi[index].dw6.dndi_stream_id = 1;
3121     sampler_dndi[index].dw6.dndi_first_frame = 1;
3122     sampler_dndi[index].dw6.progressive_dn = 0;
3123     sampler_dndi[index].dw6.mcdi_enable = 0;
3124     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3125     sampler_dndi[index].dw6.cat_th1 = 0;
3126     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3127     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3128
3129     sampler_dndi[index].dw7.sad_tha = 5;
3130     sampler_dndi[index].dw7.sad_thb = 10;
3131     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3132     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3133     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3134     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3135     sampler_dndi[index].dw7.neighborpixel_th = 10;
3136     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3137
3138     dri_bo_unmap(pp_context->sampler_state_table.bo);
3139
3140     /* private function & data */
3141     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3142     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3143     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3144
3145     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3146     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3147     pp_static_parameter->grf1.di_top_field_first = 0;
3148     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3149
3150     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3151     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3152     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3153
3154     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3155     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3156
3157     pp_dndi_context->dest_w = w;
3158     pp_dndi_context->dest_h = h;
3159
3160     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3161
3162     return VA_STATUS_SUCCESS;
3163 }
3164
3165 static int
3166 gen7_pp_dn_x_steps(void *private_context)
3167 {
3168     struct pp_dn_context *pp_dn_context = private_context;
3169
3170     return pp_dn_context->dest_w / 16;
3171 }
3172
3173 static int
3174 gen7_pp_dn_y_steps(void *private_context)
3175 {
3176     struct pp_dn_context *pp_dn_context = private_context;
3177
3178     return pp_dn_context->dest_h / 4;
3179 }
3180
3181 static int
3182 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3183 {
3184     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3185
3186     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3187     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3188
3189     return 0;
3190 }
3191
3192 static VAStatus
3193 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3194                            const struct i965_surface *src_surface,
3195                            const VARectangle *src_rect,
3196                            struct i965_surface *dst_surface,
3197                            const VARectangle *dst_rect,
3198                            void *filter_param)
3199 {
3200     struct i965_driver_data *i965 = i965_driver_data(ctx);
3201     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3202     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3203     struct object_surface *obj_surface;
3204     struct gen7_sampler_dndi *sampler_dn;
3205     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3206     int index;
3207     int w, h;
3208     int orig_w, orig_h;
3209     int dn_strength = 15;
3210     int dndi_top_first = 1;
3211     int dn_progressive = 0;
3212
3213     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3214         dndi_top_first = 1;
3215         dn_progressive = 1;
3216     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3217         dndi_top_first = 1;
3218         dn_progressive = 0;
3219     } else {
3220         dndi_top_first = 0;
3221         dn_progressive = 0;
3222     }
3223
3224     if (dn_filter_param) {
3225         float value = dn_filter_param->value;
3226
3227         if (value > 1.0)
3228             value = 1.0;
3229
3230         if (value < 0.0)
3231             value = 0.0;
3232
3233         dn_strength = (int)(value * 31.0F);
3234     }
3235
3236     /* surface */
3237     obj_surface = SURFACE(src_surface->id);
3238     orig_w = obj_surface->orig_width;
3239     orig_h = obj_surface->orig_height;
3240     w = obj_surface->width;
3241     h = obj_surface->height;
3242
3243     if (pp_context->stmm.bo == NULL) {
3244         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3245                                            "STMM surface",
3246                                            w * h,
3247                                            4096);
3248         assert(pp_context->stmm.bo);
3249     }
3250
3251     /* source UV surface index 1 */
3252     gen7_pp_set_surface_state(ctx, pp_context,
3253                               obj_surface->bo, w * h,
3254                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3255                               1, 0);
3256
3257     /* source YUV surface index 3 */
3258     gen7_pp_set_surface2_state(ctx, pp_context,
3259                                obj_surface->bo, 0,
3260                                orig_w, orig_h, w,
3261                                0, h,
3262                                SURFACE_FORMAT_PLANAR_420_8, 1,
3263                                3);
3264
3265     /* source (temporal reference) YUV surface index 4 */
3266     gen7_pp_set_surface2_state(ctx, pp_context,
3267                                obj_surface->bo, 0,
3268                                orig_w, orig_h, w,
3269                                0, h,
3270                                SURFACE_FORMAT_PLANAR_420_8, 1,
3271                                4);
3272
3273     /* STMM / History Statistics input surface, index 5 */
3274     gen7_pp_set_surface_state(ctx, pp_context,
3275                               pp_context->stmm.bo, 0,
3276                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3277                               5, 1);
3278
3279     /* destination surface */
3280     obj_surface = SURFACE(dst_surface->id);
3281     orig_w = obj_surface->orig_width;
3282     orig_h = obj_surface->orig_height;
3283     w = obj_surface->width;
3284     h = obj_surface->height;
3285
3286     /* destination Y surface index 24 */
3287     gen7_pp_set_surface_state(ctx, pp_context,
3288                               obj_surface->bo, 0,
3289                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3290                               24, 1);
3291
3292     /* destination UV surface index 25 */
3293     gen7_pp_set_surface_state(ctx, pp_context,
3294                               obj_surface->bo, w * h,
3295                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3296                               25, 1);
3297
3298     /* sampler dn */
3299     dri_bo_map(pp_context->sampler_state_table.bo, True);
3300     assert(pp_context->sampler_state_table.bo->virtual);
3301     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3302     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3303
3304     /* sample dn index 1 */
3305     index = 0;
3306     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3307     sampler_dn[index].dw0.dnmh_delt = 8;
3308     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3309     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3310     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3311     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3312
3313     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3314     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3315     sampler_dn[index].dw1.stmm_c2 = 0;
3316     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3317     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3318
3319     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3320     sampler_dn[index].dw2.bne_edge_th = 1;
3321     sampler_dn[index].dw2.smooth_mv_th = 0;
3322     sampler_dn[index].dw2.sad_tight_th = 5;
3323     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3324     sampler_dn[index].dw2.good_neighbor_th = 4;
3325
3326     sampler_dn[index].dw3.maximum_stmm = 128;
3327     sampler_dn[index].dw3.multipler_for_vecm = 2;
3328     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3329     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3330     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3331
3332     sampler_dn[index].dw4.sdi_delta = 8;
3333     sampler_dn[index].dw4.sdi_threshold = 128;
3334     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3335     sampler_dn[index].dw4.stmm_shift_up = 0;
3336     sampler_dn[index].dw4.stmm_shift_down = 0;
3337     sampler_dn[index].dw4.minimum_stmm = 0;
3338
3339     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3340     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3341     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3342     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3343
3344     sampler_dn[index].dw6.dn_enable = 1;
3345     sampler_dn[index].dw6.di_enable = 0;
3346     sampler_dn[index].dw6.di_partial = 0;
3347     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3348     sampler_dn[index].dw6.dndi_stream_id = 1;
3349     sampler_dn[index].dw6.dndi_first_frame = 1;
3350     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3351     sampler_dn[index].dw6.mcdi_enable = 0;
3352     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3353     sampler_dn[index].dw6.cat_th1 = 0;
3354     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3355     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3356
3357     sampler_dn[index].dw7.sad_tha = 5;
3358     sampler_dn[index].dw7.sad_thb = 10;
3359     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3360     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3361     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3362     sampler_dn[index].dw7.vdi_walker_enable = 0;
3363     sampler_dn[index].dw7.neighborpixel_th = 10;
3364     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3365
3366     dri_bo_unmap(pp_context->sampler_state_table.bo);
3367
3368     /* private function & data */
3369     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3370     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3371     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3372
3373     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3374     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3375     pp_static_parameter->grf1.di_top_field_first = 0;
3376     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3377
3378     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3379     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3380     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3381
3382     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3383     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3384
3385     pp_dn_context->dest_w = w;
3386     pp_dn_context->dest_h = h;
3387
3388     dst_surface->flags = src_surface->flags;
3389
3390     return VA_STATUS_SUCCESS;
3391 }
3392
3393 static VAStatus
3394 ironlake_pp_initialize(
3395     VADriverContextP   ctx,
3396     struct i965_post_processing_context *pp_context,
3397     const struct i965_surface *src_surface,
3398     const VARectangle *src_rect,
3399     struct i965_surface *dst_surface,
3400     const VARectangle *dst_rect,
3401     int                pp_index,
3402     void *filter_param
3403 )
3404 {
3405     VAStatus va_status;
3406     struct i965_driver_data *i965 = i965_driver_data(ctx);
3407     struct pp_module *pp_module;
3408     dri_bo *bo;
3409     int static_param_size, inline_param_size;
3410
3411     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3412     bo = dri_bo_alloc(i965->intel.bufmgr,
3413                       "surface state & binding table",
3414                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3415                       4096);
3416     assert(bo);
3417     pp_context->surface_state_binding_table.bo = bo;
3418
3419     dri_bo_unreference(pp_context->curbe.bo);
3420     bo = dri_bo_alloc(i965->intel.bufmgr,
3421                       "constant buffer",
3422                       4096,
3423                       4096);
3424     assert(bo);
3425     pp_context->curbe.bo = bo;
3426
3427     dri_bo_unreference(pp_context->idrt.bo);
3428     bo = dri_bo_alloc(i965->intel.bufmgr,
3429                       "interface discriptor",
3430                       sizeof(struct i965_interface_descriptor),
3431                       4096);
3432     assert(bo);
3433     pp_context->idrt.bo = bo;
3434     pp_context->idrt.num_interface_descriptors = 0;
3435
3436     dri_bo_unreference(pp_context->sampler_state_table.bo);
3437     bo = dri_bo_alloc(i965->intel.bufmgr,
3438                       "sampler state table",
3439                       4096,
3440                       4096);
3441     assert(bo);
3442     dri_bo_map(bo, True);
3443     memset(bo->virtual, 0, bo->size);
3444     dri_bo_unmap(bo);
3445     pp_context->sampler_state_table.bo = bo;
3446
3447     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3448     bo = dri_bo_alloc(i965->intel.bufmgr,
3449                       "sampler 8x8 state ",
3450                       4096,
3451                       4096);
3452     assert(bo);
3453     pp_context->sampler_state_table.bo_8x8 = bo;
3454
3455     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3456     bo = dri_bo_alloc(i965->intel.bufmgr,
3457                       "sampler 8x8 state ",
3458                       4096,
3459                       4096);
3460     assert(bo);
3461     pp_context->sampler_state_table.bo_8x8_uv = bo;
3462
3463     dri_bo_unreference(pp_context->vfe_state.bo);
3464     bo = dri_bo_alloc(i965->intel.bufmgr,
3465                       "vfe state",
3466                       sizeof(struct i965_vfe_state),
3467                       4096);
3468     assert(bo);
3469     pp_context->vfe_state.bo = bo;
3470
3471     static_param_size = sizeof(struct pp_static_parameter);
3472     inline_param_size = sizeof(struct pp_inline_parameter);
3473
3474     memset(pp_context->pp_static_parameter, 0, static_param_size);
3475     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3476
3477     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3478     pp_context->current_pp = pp_index;
3479     pp_module = &pp_context->pp_modules[pp_index];
3480
3481     if (pp_module->initialize)
3482         va_status = pp_module->initialize(ctx, pp_context,
3483                                           src_surface,
3484                                           src_rect,
3485                                           dst_surface,
3486                                           dst_rect,
3487                                           filter_param);
3488     else
3489         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3490
3491     return va_status;
3492 }
3493
3494 static VAStatus
3495 ironlake_post_processing(
3496     VADriverContextP   ctx,
3497     struct i965_post_processing_context *pp_context,
3498     const struct i965_surface *src_surface,
3499     const VARectangle *src_rect,
3500     struct i965_surface *dst_surface,
3501     const VARectangle *dst_rect,
3502     int                pp_index,
3503     void *filter_param
3504 )
3505 {
3506     VAStatus va_status;
3507
3508     va_status = ironlake_pp_initialize(ctx, pp_context,
3509                                        src_surface,
3510                                        src_rect,
3511                                        dst_surface,
3512                                        dst_rect,
3513                                        pp_index,
3514                                        filter_param);
3515
3516     if (va_status == VA_STATUS_SUCCESS) {
3517         ironlake_pp_states_setup(ctx, pp_context);
3518         ironlake_pp_pipeline_setup(ctx, pp_context);
3519     }
3520
3521     return va_status;
3522 }
3523
3524 static VAStatus
3525 gen6_pp_initialize(
3526     VADriverContextP   ctx,
3527     struct i965_post_processing_context *pp_context,
3528     const struct i965_surface *src_surface,
3529     const VARectangle *src_rect,
3530     struct i965_surface *dst_surface,
3531     const VARectangle *dst_rect,
3532     int                pp_index,
3533     void *filter_param
3534 )
3535 {
3536     VAStatus va_status;
3537     struct i965_driver_data *i965 = i965_driver_data(ctx);
3538     struct pp_module *pp_module;
3539     dri_bo *bo;
3540     int static_param_size, inline_param_size;
3541
3542     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3543     bo = dri_bo_alloc(i965->intel.bufmgr,
3544                       "surface state & binding table",
3545                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3546                       4096);
3547     assert(bo);
3548     pp_context->surface_state_binding_table.bo = bo;
3549
3550     dri_bo_unreference(pp_context->curbe.bo);
3551     bo = dri_bo_alloc(i965->intel.bufmgr,
3552                       "constant buffer",
3553                       4096,
3554                       4096);
3555     assert(bo);
3556     pp_context->curbe.bo = bo;
3557
3558     dri_bo_unreference(pp_context->idrt.bo);
3559     bo = dri_bo_alloc(i965->intel.bufmgr,
3560                       "interface discriptor",
3561                       sizeof(struct gen6_interface_descriptor_data),
3562                       4096);
3563     assert(bo);
3564     pp_context->idrt.bo = bo;
3565     pp_context->idrt.num_interface_descriptors = 0;
3566
3567     dri_bo_unreference(pp_context->sampler_state_table.bo);
3568     bo = dri_bo_alloc(i965->intel.bufmgr,
3569                       "sampler state table",
3570                       4096,
3571                       4096);
3572     assert(bo);
3573     dri_bo_map(bo, True);
3574     memset(bo->virtual, 0, bo->size);
3575     dri_bo_unmap(bo);
3576     pp_context->sampler_state_table.bo = bo;
3577
3578     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3579     bo = dri_bo_alloc(i965->intel.bufmgr,
3580                       "sampler 8x8 state ",
3581                       4096,
3582                       4096);
3583     assert(bo);
3584     pp_context->sampler_state_table.bo_8x8 = bo;
3585
3586     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3587     bo = dri_bo_alloc(i965->intel.bufmgr,
3588                       "sampler 8x8 state ",
3589                       4096,
3590                       4096);
3591     assert(bo);
3592     pp_context->sampler_state_table.bo_8x8_uv = bo;
3593
3594     dri_bo_unreference(pp_context->vfe_state.bo);
3595     bo = dri_bo_alloc(i965->intel.bufmgr,
3596                       "vfe state",
3597                       sizeof(struct i965_vfe_state),
3598                       4096);
3599     assert(bo);
3600     pp_context->vfe_state.bo = bo;
3601
3602     if (IS_GEN7(i965->intel.device_id)) {
3603         static_param_size = sizeof(struct gen7_pp_static_parameter);
3604         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3605     } else {
3606         static_param_size = sizeof(struct pp_static_parameter);
3607         inline_param_size = sizeof(struct pp_inline_parameter);
3608     }
3609
3610     memset(pp_context->pp_static_parameter, 0, static_param_size);
3611     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3612
3613     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3614     pp_context->current_pp = pp_index;
3615     pp_module = &pp_context->pp_modules[pp_index];
3616
3617     if (pp_module->initialize)
3618         va_status = pp_module->initialize(ctx, pp_context,
3619                                           src_surface,
3620                                           src_rect,
3621                                           dst_surface,
3622                                           dst_rect,
3623                                           filter_param);
3624     else
3625         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3626
3627     return va_status;
3628 }
3629
3630 static void
3631 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3632                                    struct i965_post_processing_context *pp_context)
3633 {
3634     struct i965_driver_data *i965 = i965_driver_data(ctx);
3635     struct gen6_interface_descriptor_data *desc;
3636     dri_bo *bo;
3637     int pp_index = pp_context->current_pp;
3638
3639     bo = pp_context->idrt.bo;
3640     dri_bo_map(bo, True);
3641     assert(bo->virtual);
3642     desc = bo->virtual;
3643     memset(desc, 0, sizeof(*desc));
3644     desc->desc0.kernel_start_pointer =
3645         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3646     desc->desc1.single_program_flow = 1;
3647     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3648     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3649     desc->desc2.sampler_state_pointer =
3650         pp_context->sampler_state_table.bo->offset >> 5;
3651     desc->desc3.binding_table_entry_count = 0;
3652     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3653     desc->desc4.constant_urb_entry_read_offset = 0;
3654
3655     if (IS_GEN7(i965->intel.device_id))
3656         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3657     else
3658         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3659
3660     dri_bo_emit_reloc(bo,
3661                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3662                       0,
3663                       offsetof(struct gen6_interface_descriptor_data, desc0),
3664                       pp_context->pp_modules[pp_index].kernel.bo);
3665
3666     dri_bo_emit_reloc(bo,
3667                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3668                       desc->desc2.sampler_count << 2,
3669                       offsetof(struct gen6_interface_descriptor_data, desc2),
3670                       pp_context->sampler_state_table.bo);
3671
3672     dri_bo_unmap(bo);
3673     pp_context->idrt.num_interface_descriptors++;
3674 }
3675
3676 static void
3677 gen6_pp_upload_constants(VADriverContextP ctx,
3678                          struct i965_post_processing_context *pp_context)
3679 {
3680     struct i965_driver_data *i965 = i965_driver_data(ctx);
3681     unsigned char *constant_buffer;
3682     int param_size;
3683
3684     assert(sizeof(struct pp_static_parameter) == 128);
3685     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3686
3687     if (IS_GEN7(i965->intel.device_id))
3688         param_size = sizeof(struct gen7_pp_static_parameter);
3689     else
3690         param_size = sizeof(struct pp_static_parameter);
3691
3692     dri_bo_map(pp_context->curbe.bo, 1);
3693     assert(pp_context->curbe.bo->virtual);
3694     constant_buffer = pp_context->curbe.bo->virtual;
3695     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3696     dri_bo_unmap(pp_context->curbe.bo);
3697 }
3698
3699 static void
3700 gen6_pp_states_setup(VADriverContextP ctx,
3701                      struct i965_post_processing_context *pp_context)
3702 {
3703     gen6_pp_interface_descriptor_table(ctx, pp_context);
3704     gen6_pp_upload_constants(ctx, pp_context);
3705 }
3706
3707 static void
3708 gen6_pp_pipeline_select(VADriverContextP ctx,
3709                         struct i965_post_processing_context *pp_context)
3710 {
3711     struct intel_batchbuffer *batch = pp_context->batch;
3712
3713     BEGIN_BATCH(batch, 1);
3714     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3715     ADVANCE_BATCH(batch);
3716 }
3717
3718 static void
3719 gen6_pp_state_base_address(VADriverContextP ctx,
3720                            struct i965_post_processing_context *pp_context)
3721 {
3722     struct intel_batchbuffer *batch = pp_context->batch;
3723
3724     BEGIN_BATCH(batch, 10);
3725     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3726     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3727     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3728     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3729     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3730     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3731     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3732     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3733     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3734     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3735     ADVANCE_BATCH(batch);
3736 }
3737
3738 static void
3739 gen6_pp_vfe_state(VADriverContextP ctx,
3740                   struct i965_post_processing_context *pp_context)
3741 {
3742     struct intel_batchbuffer *batch = pp_context->batch;
3743
3744     BEGIN_BATCH(batch, 8);
3745     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3746     OUT_BATCH(batch, 0);
3747     OUT_BATCH(batch,
3748               (pp_context->urb.num_vfe_entries - 1) << 16 |
3749               pp_context->urb.num_vfe_entries << 8);
3750     OUT_BATCH(batch, 0);
3751     OUT_BATCH(batch,
3752               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3753               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3754     OUT_BATCH(batch, 0);
3755     OUT_BATCH(batch, 0);
3756     OUT_BATCH(batch, 0);
3757     ADVANCE_BATCH(batch);
3758 }
3759
3760 static void
3761 gen6_pp_curbe_load(VADriverContextP ctx,
3762                    struct i965_post_processing_context *pp_context)
3763 {
3764     struct intel_batchbuffer *batch = pp_context->batch;
3765
3766     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3767
3768     BEGIN_BATCH(batch, 4);
3769     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3770     OUT_BATCH(batch, 0);
3771     OUT_BATCH(batch,
3772               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3773     OUT_RELOC(batch,
3774               pp_context->curbe.bo,
3775               I915_GEM_DOMAIN_INSTRUCTION, 0,
3776               0);
3777     ADVANCE_BATCH(batch);
3778 }
3779
3780 static void
3781 gen6_interface_descriptor_load(VADriverContextP ctx,
3782                                struct i965_post_processing_context *pp_context)
3783 {
3784     struct intel_batchbuffer *batch = pp_context->batch;
3785
3786     BEGIN_BATCH(batch, 4);
3787     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3788     OUT_BATCH(batch, 0);
3789     OUT_BATCH(batch,
3790               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3791     OUT_RELOC(batch,
3792               pp_context->idrt.bo,
3793               I915_GEM_DOMAIN_INSTRUCTION, 0,
3794               0);
3795     ADVANCE_BATCH(batch);
3796 }
3797
3798 static void
3799 gen6_pp_object_walker(VADriverContextP ctx,
3800                       struct i965_post_processing_context *pp_context)
3801 {
3802     struct i965_driver_data *i965 = i965_driver_data(ctx);
3803     struct intel_batchbuffer *batch = pp_context->batch;
3804     int x, x_steps, y, y_steps;
3805     int param_size, command_length_in_dws;
3806     dri_bo *command_buffer;
3807     unsigned int *command_ptr;
3808
3809     if (IS_GEN7(i965->intel.device_id))
3810         param_size = sizeof(struct gen7_pp_inline_parameter);
3811     else
3812         param_size = sizeof(struct pp_inline_parameter);
3813
3814     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3815     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3816     command_length_in_dws = 6 + (param_size >> 2);
3817     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3818                                   "command objects buffer",
3819                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3820                                   4096);
3821
3822     dri_bo_map(command_buffer, 1);
3823     command_ptr = command_buffer->virtual;
3824
3825     for (y = 0; y < y_steps; y++) {
3826         for (x = 0; x < x_steps; x++) {
3827             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3828                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3829                 *command_ptr++ = 0;
3830                 *command_ptr++ = 0;
3831                 *command_ptr++ = 0;
3832                 *command_ptr++ = 0;
3833                 *command_ptr++ = 0;
3834                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3835                 command_ptr += (param_size >> 2);
3836             }
3837         }
3838     }
3839
3840     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3841         *command_ptr++ = 0;
3842
3843     *command_ptr = MI_BATCH_BUFFER_END;
3844
3845     dri_bo_unmap(command_buffer);
3846
3847     BEGIN_BATCH(batch, 2);
3848     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3849     OUT_RELOC(batch, command_buffer,
3850               I915_GEM_DOMAIN_COMMAND, 0,
3851               0);
3852     ADVANCE_BATCH(batch);
3853
3854     dri_bo_unreference(command_buffer);
3855
3856     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3857      * will cause control to pass back to ring buffer
3858      */
3859     intel_batchbuffer_end_atomic(batch);
3860     intel_batchbuffer_flush(batch);
3861     intel_batchbuffer_start_atomic(batch, 0x1000);
3862 }
3863
3864 static void
3865 gen6_pp_pipeline_setup(VADriverContextP ctx,
3866                        struct i965_post_processing_context *pp_context)
3867 {
3868     struct intel_batchbuffer *batch = pp_context->batch;
3869
3870     intel_batchbuffer_start_atomic(batch, 0x1000);
3871     intel_batchbuffer_emit_mi_flush(batch);
3872     gen6_pp_pipeline_select(ctx, pp_context);
3873     gen6_pp_state_base_address(ctx, pp_context);
3874     gen6_pp_vfe_state(ctx, pp_context);
3875     gen6_pp_curbe_load(ctx, pp_context);
3876     gen6_interface_descriptor_load(ctx, pp_context);
3877     gen6_pp_object_walker(ctx, pp_context);
3878     intel_batchbuffer_end_atomic(batch);
3879 }
3880
3881 static VAStatus
3882 gen6_post_processing(
3883     VADriverContextP   ctx,
3884     struct i965_post_processing_context *pp_context,
3885     const struct i965_surface *src_surface,
3886     const VARectangle *src_rect,
3887     struct i965_surface *dst_surface,
3888     const VARectangle *dst_rect,
3889     int                pp_index,
3890     void * filter_param
3891 )
3892 {
3893     VAStatus va_status;
3894
3895     va_status = gen6_pp_initialize(ctx, pp_context,
3896                                    src_surface,
3897                                    src_rect,
3898                                    dst_surface,
3899                                    dst_rect,
3900                                    pp_index,
3901                                    filter_param);
3902
3903     if (va_status == VA_STATUS_SUCCESS) {
3904         gen6_pp_states_setup(ctx, pp_context);
3905         gen6_pp_pipeline_setup(ctx, pp_context);
3906     }
3907
3908     return va_status;
3909 }
3910
3911 static VAStatus
3912 i965_post_processing_internal(
3913     VADriverContextP   ctx,
3914     struct i965_post_processing_context *pp_context,
3915     const struct i965_surface *src_surface,
3916     const VARectangle *src_rect,
3917     struct i965_surface *dst_surface,
3918     const VARectangle *dst_rect,
3919     int                pp_index,
3920     void *filter_param
3921 )
3922 {
3923     struct i965_driver_data *i965 = i965_driver_data(ctx);
3924     VAStatus va_status;
3925
3926     if (IS_GEN6(i965->intel.device_id) ||
3927         IS_GEN7(i965->intel.device_id))
3928         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3929     else
3930         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3931
3932     return va_status;
3933 }
3934
3935 VAStatus
3936 i965_DestroySurfaces(VADriverContextP ctx,
3937                      VASurfaceID *surface_list,
3938                      int num_surfaces);
3939 VAStatus
3940 i965_CreateSurfaces(VADriverContextP ctx,
3941                     int width,
3942                     int height,
3943                     int format,
3944                     int num_surfaces,
3945                     VASurfaceID *surfaces);
3946
3947 static void
3948 rgb_to_yuv(unsigned int argb,
3949            unsigned char *y,
3950            unsigned char *u,
3951            unsigned char *v,
3952            unsigned char *a)
3953 {
3954     int r = ((argb >> 16) & 0xff);
3955     int g = ((argb >> 8) & 0xff);
3956     int b = ((argb >> 0) & 0xff);
3957
3958     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3959     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3960     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3961     *a = ((argb >> 24) & 0xff);
3962 }
3963
3964 static void
3965 i965_vpp_clear_surface(VADriverContextP ctx,
3966                        struct i965_post_processing_context *pp_context,
3967                        VASurfaceID surface,
3968                        unsigned int color)
3969 {
3970     struct i965_driver_data *i965 = i965_driver_data(ctx);
3971     struct intel_batchbuffer *batch = pp_context->batch;
3972     struct object_surface *obj_surface = SURFACE(surface);
3973     unsigned int blt_cmd, br13;
3974     unsigned int tiling = 0, swizzle = 0;
3975     int pitch;
3976     unsigned char y, u, v, a = 0;
3977
3978     /* Currently only support NV12 surface */
3979     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3980         return;
3981
3982     rgb_to_yuv(color, &y, &u, &v, &a);
3983
3984     if (a == 0)
3985         return;
3986
3987     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3988     blt_cmd = XY_COLOR_BLT_CMD;
3989     pitch = obj_surface->width;
3990
3991     if (tiling != I915_TILING_NONE) {
3992         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3993         pitch >>= 2;
3994     }
3995
3996     br13 = 0xf0 << 16;
3997     br13 |= BR13_8;
3998     br13 |= pitch;
3999
4000     if (IS_GEN6(i965->intel.device_id) ||
4001         IS_GEN7(i965->intel.device_id)) {
4002         intel_batchbuffer_start_atomic_blt(batch, 48);
4003         BEGIN_BLT_BATCH(batch, 12);
4004     } else {
4005         intel_batchbuffer_start_atomic(batch, 48);
4006         BEGIN_BATCH(batch, 12);
4007     }
4008
4009     OUT_BATCH(batch, blt_cmd);
4010     OUT_BATCH(batch, br13);
4011     OUT_BATCH(batch,
4012               0 << 16 |
4013               0);
4014     OUT_BATCH(batch,
4015               obj_surface->height << 16 |
4016               obj_surface->width);
4017     OUT_RELOC(batch, obj_surface->bo,
4018               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4019               0);
4020     OUT_BATCH(batch, y);
4021
4022     br13 = 0xf0 << 16;
4023     br13 |= BR13_565;
4024     br13 |= pitch;
4025
4026     OUT_BATCH(batch, blt_cmd);
4027     OUT_BATCH(batch, br13);
4028     OUT_BATCH(batch,
4029               0 << 16 |
4030               0);
4031     OUT_BATCH(batch,
4032               obj_surface->height / 2 << 16 |
4033               obj_surface->width / 2);
4034     OUT_RELOC(batch, obj_surface->bo,
4035               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4036               obj_surface->width * obj_surface->y_cb_offset);
4037     OUT_BATCH(batch, v << 8 | u);
4038
4039     ADVANCE_BATCH(batch);
4040     intel_batchbuffer_end_atomic(batch);
4041 }
4042
4043 VASurfaceID
4044 i965_post_processing(
4045     VADriverContextP   ctx,
4046     VASurfaceID        surface,
4047     const VARectangle *src_rect,
4048     const VARectangle *dst_rect,
4049     unsigned int       flags,
4050     int               *has_done_scaling
4051 )
4052 {
4053     struct i965_driver_data *i965 = i965_driver_data(ctx);
4054     VASurfaceID in_surface_id = surface;
4055     VASurfaceID out_surface_id = VA_INVALID_ID;
4056
4057     *has_done_scaling = 0;
4058
4059     if (HAS_PP(i965)) {
4060         struct object_surface *obj_surface;
4061         VAStatus status;
4062         struct i965_surface src_surface;
4063         struct i965_surface dst_surface;
4064
4065         obj_surface = SURFACE(in_surface_id);
4066
4067         /* Currently only support post processing for NV12 surface */
4068         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
4069             return out_surface_id;
4070
4071         _i965LockMutex(&i965->pp_mutex);
4072
4073         if (flags & I965_PP_FLAG_MCDI) {
4074             status = i965_CreateSurfaces(ctx,
4075                                          obj_surface->orig_width,
4076                                          obj_surface->orig_height,
4077                                          VA_RT_FORMAT_YUV420,
4078                                          1,
4079                                          &out_surface_id);
4080             assert(status == VA_STATUS_SUCCESS);
4081             obj_surface = SURFACE(out_surface_id);
4082             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4083             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4084             src_surface.id = in_surface_id;
4085             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4086             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
4087                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
4088             dst_surface.id = out_surface_id;
4089             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4090             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4091
4092             i965_post_processing_internal(ctx, i965->pp_context,
4093                                           &src_surface,
4094                                           src_rect,
4095                                           &dst_surface,
4096                                           dst_rect,
4097                                           PP_NV12_DNDI,
4098                                           NULL);
4099         }
4100
4101         if (flags & I965_PP_FLAG_AVS) {
4102             struct i965_render_state *render_state = &i965->render_state;
4103             struct intel_region *dest_region = render_state->draw_region;
4104
4105             if (out_surface_id != VA_INVALID_ID)
4106                 in_surface_id = out_surface_id;
4107
4108             status = i965_CreateSurfaces(ctx,
4109                                          dest_region->width,
4110                                          dest_region->height,
4111                                          VA_RT_FORMAT_YUV420,
4112                                          1,
4113                                          &out_surface_id);
4114             assert(status == VA_STATUS_SUCCESS);
4115             obj_surface = SURFACE(out_surface_id);
4116             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4117             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4118             src_surface.id = in_surface_id;
4119             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4120             src_surface.flags = I965_SURFACE_FLAG_FRAME;
4121             dst_surface.id = out_surface_id;
4122             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4123             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4124
4125             i965_post_processing_internal(ctx, i965->pp_context,
4126                                           &src_surface,
4127                                           src_rect,
4128                                           &dst_surface,
4129                                           dst_rect,
4130                                           PP_NV12_AVS,
4131                                           NULL);
4132
4133             if (in_surface_id != surface)
4134                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4135
4136             *has_done_scaling = 1;
4137         }
4138
4139         _i965UnlockMutex(&i965->pp_mutex);
4140     }
4141
4142     return out_surface_id;
4143 }
4144
4145 static VAStatus
4146 i965_image_pl1_rgbx_processing(VADriverContextP ctx,
4147                           const struct i965_surface *src_surface,
4148                           const VARectangle *src_rect,
4149                           struct i965_surface *dst_surface,
4150                           const VARectangle *dst_rect)
4151 {
4152     struct i965_driver_data *i965 = i965_driver_data(ctx);
4153     struct i965_post_processing_context *pp_context = i965->pp_context;
4154     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4155
4156     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4157         i965_post_processing_internal(ctx, i965->pp_context,
4158                                       src_surface,
4159                                       src_rect,
4160                                       dst_surface,
4161                                       dst_rect,
4162                                       PP_RGBX_LOAD_SAVE_NV12,
4163                                       NULL);
4164     } else {
4165         assert(0);
4166         return VA_STATUS_ERROR_UNKNOWN;
4167     }
4168
4169     intel_batchbuffer_flush(pp_context->batch);
4170
4171     return VA_STATUS_SUCCESS;
4172 }
4173
4174 static VAStatus
4175 i965_image_pl3_processing(VADriverContextP ctx,
4176                           const struct i965_surface *src_surface,
4177                           const VARectangle *src_rect,
4178                           struct i965_surface *dst_surface,
4179                           const VARectangle *dst_rect)
4180 {
4181     struct i965_driver_data *i965 = i965_driver_data(ctx);
4182     struct i965_post_processing_context *pp_context = i965->pp_context;
4183     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4184     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4185
4186     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4187         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4188                                                  src_surface,
4189                                                  src_rect,
4190                                                  dst_surface,
4191                                                  dst_rect,
4192                                                  PP_PL3_LOAD_SAVE_N12,
4193                                                  NULL);
4194     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4195                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4196                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4197                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4198         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4199                                                  src_surface,
4200                                                  src_rect,
4201                                                  dst_surface,
4202                                                  dst_rect,
4203                                                  PP_PL3_LOAD_SAVE_PL3,
4204                                                  NULL);
4205     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4206                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4207         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4208                                                  src_surface,
4209                                                  src_rect,
4210                                                  dst_surface,
4211                                                  dst_rect,
4212                                                  PP_PL3_LOAD_SAVE_PA,
4213                                                  NULL);
4214     }
4215     else {
4216         assert(0);
4217     }
4218
4219     intel_batchbuffer_flush(pp_context->batch);
4220
4221     return vaStatus;
4222 }
4223
4224 static VAStatus
4225 i965_image_pl2_processing(VADriverContextP ctx,
4226                           const struct i965_surface *src_surface,
4227                           const VARectangle *src_rect,
4228                           struct i965_surface *dst_surface,
4229                           const VARectangle *dst_rect)
4230 {
4231     struct i965_driver_data *i965 = i965_driver_data(ctx);
4232     struct i965_post_processing_context *pp_context = i965->pp_context;
4233     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4234     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4235
4236     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4237         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4238                                                  src_surface,
4239                                                  src_rect,
4240                                                  dst_surface,
4241                                                  dst_rect,
4242                                                  PP_NV12_LOAD_SAVE_N12,
4243                                                  NULL);
4244     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4245                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4246                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4247                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4248         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4249                                                  src_surface,
4250                                                  src_rect,
4251                                                  dst_surface,
4252                                                  dst_rect,
4253                                                  PP_NV12_LOAD_SAVE_PL3,
4254                                                  NULL);
4255     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4256                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4257         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4258                                                  src_surface,
4259                                                  src_rect,
4260                                                  dst_surface,
4261                                                  dst_rect,
4262                                                  PP_NV12_LOAD_SAVE_PA,
4263                                                      NULL);
4264     } else if (fourcc == VA_FOURCC('B', 'G', 'R', 'X') ||
4265                fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
4266                fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
4267                fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) {
4268         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4269                                       src_surface,
4270                                       src_rect,
4271                                       dst_surface,
4272                                       dst_rect,
4273                                       PP_NV12_LOAD_SAVE_RGBX,
4274                                       NULL);
4275     } else {
4276         assert(0);
4277         return VA_STATUS_ERROR_UNKNOWN;
4278     }
4279
4280     intel_batchbuffer_flush(pp_context->batch);
4281
4282     return vaStatus;
4283 }
4284
4285 static VAStatus
4286 i965_image_pl1_processing(VADriverContextP ctx,
4287                           const struct i965_surface *src_surface,
4288                           const VARectangle *src_rect,
4289                           struct i965_surface *dst_surface,
4290                           const VARectangle *dst_rect)
4291 {
4292     struct i965_driver_data *i965 = i965_driver_data(ctx);
4293     struct i965_post_processing_context *pp_context = i965->pp_context;
4294     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4295
4296     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4297         i965_post_processing_internal(ctx, i965->pp_context,
4298                                       src_surface,
4299                                       src_rect,
4300                                       dst_surface,
4301                                       dst_rect,
4302                                       PP_PA_LOAD_SAVE_NV12,
4303                                       NULL);
4304     }
4305     else if (fourcc == VA_FOURCC_YV12) {
4306         i965_post_processing_internal(ctx, i965->pp_context,
4307                                       src_surface,
4308                                       src_rect,
4309                                       dst_surface,
4310                                       dst_rect,
4311                                       PP_PA_LOAD_SAVE_PL3,
4312                                       NULL);
4313
4314     }
4315     else {
4316         return VA_STATUS_ERROR_UNKNOWN;
4317     }
4318
4319     intel_batchbuffer_flush(pp_context->batch);
4320
4321     return VA_STATUS_SUCCESS;
4322 }
4323
4324 VAStatus
4325 i965_image_processing(VADriverContextP ctx,
4326                       const struct i965_surface *src_surface,
4327                       const VARectangle *src_rect,
4328                       struct i965_surface *dst_surface,
4329                       const VARectangle *dst_rect)
4330 {
4331     struct i965_driver_data *i965 = i965_driver_data(ctx);
4332     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4333
4334     if (HAS_PP(i965)) {
4335         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4336
4337         _i965LockMutex(&i965->pp_mutex);
4338
4339         switch (fourcc) {
4340         case VA_FOURCC('Y', 'V', '1', '2'):
4341         case VA_FOURCC('I', '4', '2', '0'):
4342         case VA_FOURCC('I', 'M', 'C', '1'):
4343         case VA_FOURCC('I', 'M', 'C', '3'):
4344             status = i965_image_pl3_processing(ctx,
4345                                                src_surface,
4346                                                src_rect,
4347                                                dst_surface,
4348                                                dst_rect);
4349             break;
4350
4351         case  VA_FOURCC('N', 'V', '1', '2'):
4352             status = i965_image_pl2_processing(ctx,
4353                                                src_surface,
4354                                                src_rect,
4355                                                dst_surface,
4356                                                dst_rect);
4357             break;
4358         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4359         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4360             status = i965_image_pl1_processing(ctx,
4361                                                src_surface,
4362                                                src_rect,
4363                                                dst_surface,
4364                                                dst_rect);
4365             break;
4366         case VA_FOURCC('B', 'G', 'R', 'A'):
4367         case VA_FOURCC('B', 'G', 'R', 'X'):
4368         case VA_FOURCC('R', 'G', 'B', 'A'):
4369         case VA_FOURCC('R', 'G', 'B', 'X'):
4370             status = i965_image_pl1_rgbx_processing(ctx,
4371                                                src_surface,
4372                                                src_rect,
4373                                                dst_surface,
4374                                                dst_rect);
4375             break;
4376         default:
4377             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4378             break;
4379         }
4380
4381         _i965UnlockMutex(&i965->pp_mutex);
4382     }
4383
4384     return status;
4385 }
4386
4387 static void
4388 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4389 {
4390     int i;
4391
4392     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4393     pp_context->surface_state_binding_table.bo = NULL;
4394
4395     dri_bo_unreference(pp_context->curbe.bo);
4396     pp_context->curbe.bo = NULL;
4397
4398     dri_bo_unreference(pp_context->sampler_state_table.bo);
4399     pp_context->sampler_state_table.bo = NULL;
4400
4401     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4402     pp_context->sampler_state_table.bo_8x8 = NULL;
4403
4404     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4405     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4406
4407     dri_bo_unreference(pp_context->idrt.bo);
4408     pp_context->idrt.bo = NULL;
4409     pp_context->idrt.num_interface_descriptors = 0;
4410
4411     dri_bo_unreference(pp_context->vfe_state.bo);
4412     pp_context->vfe_state.bo = NULL;
4413
4414     dri_bo_unreference(pp_context->stmm.bo);
4415     pp_context->stmm.bo = NULL;
4416
4417     for (i = 0; i < NUM_PP_MODULES; i++) {
4418         struct pp_module *pp_module = &pp_context->pp_modules[i];
4419
4420         dri_bo_unreference(pp_module->kernel.bo);
4421         pp_module->kernel.bo = NULL;
4422     }
4423
4424     free(pp_context->pp_static_parameter);
4425     free(pp_context->pp_inline_parameter);
4426     pp_context->pp_static_parameter = NULL;
4427     pp_context->pp_inline_parameter = NULL;
4428 }
4429
4430 Bool
4431 i965_post_processing_terminate(VADriverContextP ctx)
4432 {
4433     struct i965_driver_data *i965 = i965_driver_data(ctx);
4434     struct i965_post_processing_context *pp_context = i965->pp_context;
4435
4436     if (pp_context) {
4437         i965_post_processing_context_finalize(pp_context);
4438         free(pp_context);
4439     }
4440
4441     i965->pp_context = NULL;
4442
4443     return True;
4444 }
4445
4446 static void
4447 i965_post_processing_context_init(VADriverContextP ctx,
4448                                   struct i965_post_processing_context *pp_context,
4449                                   struct intel_batchbuffer *batch)
4450 {
4451     struct i965_driver_data *i965 = i965_driver_data(ctx);
4452     int i;
4453
4454     pp_context->urb.size = URB_SIZE((&i965->intel));
4455     pp_context->urb.num_vfe_entries = 32;
4456     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4457     pp_context->urb.num_cs_entries = 1;
4458
4459     if (IS_GEN7(i965->intel.device_id))
4460         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4461     else
4462         pp_context->urb.size_cs_entry = 2;
4463
4464     pp_context->urb.vfe_start = 0;
4465     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4466         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4467     assert(pp_context->urb.cs_start +
4468            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4469
4470     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4471     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4472     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4473
4474     if (IS_GEN7(i965->intel.device_id))
4475         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4476     else if (IS_GEN6(i965->intel.device_id))
4477         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4478     else if (IS_IRONLAKE(i965->intel.device_id))
4479         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4480
4481     for (i = 0; i < NUM_PP_MODULES; i++) {
4482         struct pp_module *pp_module = &pp_context->pp_modules[i];
4483         dri_bo_unreference(pp_module->kernel.bo);
4484         if (pp_module->kernel.bin && pp_module->kernel.size) {
4485             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4486                                                 pp_module->kernel.name,
4487                                                 pp_module->kernel.size,
4488                                                 4096);
4489             assert(pp_module->kernel.bo);
4490             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4491         } else {
4492             pp_module->kernel.bo = NULL;
4493         }
4494     }
4495
4496     /* static & inline parameters */
4497     if (IS_GEN7(i965->intel.device_id)) {
4498         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4499         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4500     } else {
4501         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4502         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4503     }
4504
4505     pp_context->batch = batch;
4506 }
4507
4508 Bool
4509 i965_post_processing_init(VADriverContextP ctx)
4510 {
4511     struct i965_driver_data *i965 = i965_driver_data(ctx);
4512     struct i965_post_processing_context *pp_context = i965->pp_context;
4513
4514     if (HAS_PP(i965)) {
4515         if (pp_context == NULL) {
4516             pp_context = calloc(1, sizeof(*pp_context));
4517             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4518             i965->pp_context = pp_context;
4519         }
4520     }
4521
4522     return True;
4523 }
4524
4525 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4526     PP_NULL,    /* VAProcFilterNone */
4527     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4528     PP_NULL,    /* VAProcFilterDeblocking */
4529     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4530     PP_NULL,    /* VAProcFilterSharpening */
4531     PP_NULL,    /* VAProcFilterColorBalance */
4532     PP_NULL,    /* VAProcFilterColorStandard */
4533     PP_NULL,    /* VAProcFilterFrameRateConversion */
4534 };
4535
4536 static const int proc_frame_to_pp_frame[3] = {
4537     I965_SURFACE_FLAG_FRAME,
4538     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4539     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4540 };
4541
4542 static void
4543 i965_proc_picture(VADriverContextP ctx,
4544                   VAProfile profile,
4545                   union codec_state *codec_state,
4546                   struct hw_context *hw_context)
4547 {
4548     struct i965_driver_data *i965 = i965_driver_data(ctx);
4549     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4550     struct proc_state *proc_state = &codec_state->proc;
4551     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4552     struct object_surface *obj_surface;
4553     struct i965_surface src_surface, dst_surface;
4554     VARectangle src_rect, dst_rect;
4555     VAStatus status;
4556     int i;
4557     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4558     int num_tmp_surfaces = 0;
4559     unsigned int tiling = 0, swizzle = 0;
4560     int in_width, in_height;
4561
4562     assert(pipeline_param->surface != VA_INVALID_ID);
4563     assert(proc_state->current_render_target != VA_INVALID_ID);
4564
4565     obj_surface = SURFACE(pipeline_param->surface);
4566     in_width = obj_surface->orig_width;
4567     in_height = obj_surface->orig_height;
4568     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4569
4570     src_surface.id = pipeline_param->surface;
4571     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4572     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4573
4574     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4575         VASurfaceID out_surface_id = VA_INVALID_ID;
4576
4577         src_surface.id = pipeline_param->surface;
4578         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4579         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4580         src_rect.x = 0;
4581         src_rect.y = 0;
4582         src_rect.width = in_width;
4583         src_rect.height = in_height;
4584
4585         status = i965_CreateSurfaces(ctx,
4586                                      in_width,
4587                                      in_height,
4588                                      VA_RT_FORMAT_YUV420,
4589                                      1,
4590                                      &out_surface_id);
4591         assert(status == VA_STATUS_SUCCESS);
4592         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4593         obj_surface = SURFACE(out_surface_id);
4594         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4595
4596         dst_surface.id = out_surface_id;
4597         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4598         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4599         dst_rect.x = 0;
4600         dst_rect.y = 0;
4601         dst_rect.width = in_width;
4602         dst_rect.height = in_height;
4603
4604         status = i965_image_processing(ctx,
4605                                        &src_surface,
4606                                        &src_rect,
4607                                        &dst_surface,
4608                                        &dst_rect);
4609         assert(status == VA_STATUS_SUCCESS);
4610
4611         src_surface.id = out_surface_id;
4612         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4613         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4614     }
4615
4616     if (pipeline_param->surface_region) {
4617         src_rect.x = pipeline_param->surface_region->x;
4618         src_rect.y = pipeline_param->surface_region->y;
4619         src_rect.width = pipeline_param->surface_region->width;
4620         src_rect.height = pipeline_param->surface_region->height;
4621     } else {
4622         src_rect.x = 0;
4623         src_rect.y = 0;
4624         src_rect.width = in_width;
4625         src_rect.height = in_height;
4626     }
4627
4628     if (pipeline_param->output_region) {
4629         dst_rect.x = pipeline_param->output_region->x;
4630         dst_rect.y = pipeline_param->output_region->y;
4631         dst_rect.width = pipeline_param->output_region->width;
4632         dst_rect.height = pipeline_param->output_region->height;
4633     } else {
4634         dst_rect.x = 0;
4635         dst_rect.y = 0;
4636         dst_rect.width = in_width;
4637         dst_rect.height = in_height;
4638     }
4639
4640     obj_surface = SURFACE(proc_state->current_render_target);
4641     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4642     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4643
4644     for (i = 0; i < pipeline_param->num_filters; i++) {
4645         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4646         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4647         VAProcFilterType filter_type = filter_param->type;
4648         VASurfaceID out_surface_id = VA_INVALID_ID;
4649         int kernel_index = procfilter_to_pp_flag[filter_type];
4650
4651         if (kernel_index != PP_NULL &&
4652             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4653             status = i965_CreateSurfaces(ctx,
4654                                          in_width,
4655                                          in_height,
4656                                          VA_RT_FORMAT_YUV420,
4657                                          1,
4658                                          &out_surface_id);
4659             assert(status == VA_STATUS_SUCCESS);
4660             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4661             obj_surface = SURFACE(out_surface_id);
4662             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4663             dst_surface.id = out_surface_id;
4664             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4665             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4666                                                    &src_surface,
4667                                                    &src_rect,
4668                                                    &dst_surface,
4669                                                    &src_rect,
4670                                                    kernel_index,
4671                                                    filter_param);
4672
4673             if (status == VA_STATUS_SUCCESS) {
4674                 src_surface.id = dst_surface.id;
4675                 src_surface.type = dst_surface.type;
4676                 src_surface.flags = dst_surface.flags;
4677             }
4678         }
4679     }
4680
4681     dst_surface.id = proc_state->current_render_target;
4682     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4683
4684     if (src_rect.width == dst_rect.width &&
4685         src_rect.height == dst_rect.height) {
4686         i965_post_processing_internal(ctx, &proc_context->pp_context,
4687                                       &src_surface,
4688                                       &src_rect,
4689                                       &dst_surface,
4690                                       &dst_rect,
4691                                       PP_NV12_LOAD_SAVE_N12,
4692                                       NULL);
4693     } else {
4694
4695         i965_post_processing_internal(ctx, &proc_context->pp_context,
4696                                       &src_surface,
4697                                       &src_rect,
4698                                       &dst_surface,
4699                                       &dst_rect,
4700                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4701                                       PP_NV12_AVS : PP_NV12_SCALING,
4702                                       NULL);
4703     }
4704
4705     if (num_tmp_surfaces)
4706         i965_DestroySurfaces(ctx,
4707                              tmp_surfaces,
4708                              num_tmp_surfaces);
4709
4710     intel_batchbuffer_flush(hw_context->batch);
4711 }
4712
4713 static void
4714 i965_proc_context_destroy(void *hw_context)
4715 {
4716     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4717
4718     i965_post_processing_context_finalize(&proc_context->pp_context);
4719     intel_batchbuffer_free(proc_context->base.batch);
4720     free(proc_context);
4721 }
4722
4723 struct hw_context *
4724 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4725 {
4726     struct intel_driver_data *intel = intel_driver_data(ctx);
4727     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4728
4729     proc_context->base.destroy = i965_proc_context_destroy;
4730     proc_context->base.run = i965_proc_picture;
4731     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4732     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4733
4734     return (struct hw_context *)proc_context;
4735 }