src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 111                                    const struct i965_surface *src_surface,
 112                                    const VARectangle *src_rect,
 113                                    struct i965_surface *dst_surface,
 114                                    const VARectangle *dst_rect,
 115                                    void *filter_param);
 116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 117                                             const struct i965_surface *src_surface,
 118                                             const VARectangle *src_rect,
 119                                             struct i965_surface *dst_surface,
 120                                             const VARectangle *dst_rect,
 121                                             void *filter_param);
 122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 123                                            const struct i965_surface *src_surface,
 124                                            const VARectangle *src_rect,
 125                                            struct i965_surface *dst_surface,
 126                                            const VARectangle *dst_rect,
 127                                            void *filter_param);
 128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 129                                              const struct i965_surface *src_surface,
 130                                              const VARectangle *src_rect,
 131                                              struct i965_surface *dst_surface,
 132                                              const VARectangle *dst_rect,
 133                                              void *filter_param);
 134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 135                                                 const struct i965_surface *src_surface,
 136                                                 const VARectangle *src_rect,
 137                                                 struct i965_surface *dst_surface,
 138                                                 const VARectangle *dst_rect,
 139                                                 void *filter_param);
 140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 141                                         const struct i965_surface *src_surface,
 142                                         const VARectangle *src_rect,
 143                                         struct i965_surface *dst_surface,
 144                                         const VARectangle *dst_rect,
 145                                         void *filter_param);
 146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 147                                       const struct i965_surface *src_surface,
 148                                       const VARectangle *src_rect,
 149                                       struct i965_surface *dst_surface,
 150                                       const VARectangle *dst_rect,
 151                                       void *filter_param);
 152
 153 static struct pp_module pp_modules_gen5[] = {
 154     {
 155         {
 156             "NULL module (for testing)",
 157             PP_NULL,
 158             pp_null_gen5,
 159             sizeof(pp_null_gen5),
 160             NULL,
 161         },
 162
 163         pp_null_initialize,
 164     },
 165
 166     {
 167         {
 168             "NV12_NV12",
 169             PP_NV12_LOAD_SAVE_N12,
 170             pp_nv12_load_save_nv12_gen5,
 171             sizeof(pp_nv12_load_save_nv12_gen5),
 172             NULL,
 173         },
 174
 175         pp_plx_load_save_plx_initialize,
 176     },
 177
 178     {
 179         {
 180             "NV12_PL3",
 181             PP_NV12_LOAD_SAVE_PL3,
 182             pp_nv12_load_save_pl3_gen5,
 183             sizeof(pp_nv12_load_save_pl3_gen5),
 184             NULL,
 185         },
 186
 187         pp_plx_load_save_plx_initialize,
 188     },
 189
 190     {
 191         {
 192             "PL3_NV12",
 193             PP_PL3_LOAD_SAVE_N12,
 194             pp_pl3_load_save_nv12_gen5,
 195             sizeof(pp_pl3_load_save_nv12_gen5),
 196             NULL,
 197         },
 198
 199         pp_plx_load_save_plx_initialize,
 200     },
 201
 202     {
 203         {
 204             "PL3_PL3",
 205             PP_PL3_LOAD_SAVE_N12,
 206             pp_pl3_load_save_pl3_gen5,
 207             sizeof(pp_pl3_load_save_pl3_gen5),
 208             NULL,
 209         },
 210
 211         pp_plx_load_save_plx_initialize
 212     },
 213
 214     {
 215         {
 216             "NV12 Scaling module",
 217             PP_NV12_SCALING,
 218             pp_nv12_scaling_gen5,
 219             sizeof(pp_nv12_scaling_gen5),
 220             NULL,
 221         },
 222
 223         pp_nv12_scaling_initialize,
 224     },
 225
 226     {
 227         {
 228             "NV12 AVS module",
 229             PP_NV12_AVS,
 230             pp_nv12_avs_gen5,
 231             sizeof(pp_nv12_avs_gen5),
 232             NULL,
 233         },
 234
 235         pp_nv12_avs_initialize_nlas,
 236     },
 237
 238     {
 239         {
 240             "NV12 DNDI module",
 241             PP_NV12_DNDI,
 242             pp_nv12_dndi_gen5,
 243             sizeof(pp_nv12_dndi_gen5),
 244             NULL,
 245         },
 246
 247         pp_nv12_dndi_initialize,
 248     },
 249
 250     {
 251         {
 252             "NV12 DN module",
 253             PP_NV12_DN,
 254             pp_nv12_dn_gen5,
 255             sizeof(pp_nv12_dn_gen5),
 256             NULL,
 257         },
 258
 259         pp_nv12_dn_initialize,
 260     },
 261
 262     {
 263         {
 264             "NV12_PA module",
 265             PP_NV12_LOAD_SAVE_PA,
 266             pp_nv12_load_save_pa_gen5,
 267             sizeof(pp_nv12_load_save_pa_gen5),
 268             NULL,
 269         },
 270
 271         pp_plx_load_save_plx_initialize,
 272     },
 273
 274     {
 275         {
 276             "PL3_PA module",
 277             PP_PL3_LOAD_SAVE_PA,
 278             pp_pl3_load_save_pa_gen5,
 279             sizeof(pp_pl3_load_save_pa_gen5),
 280             NULL,
 281         },
 282
 283         pp_plx_load_save_plx_initialize,
 284     },
 285
 286     {
 287         {
 288             "PA_NV12 module",
 289             PP_PA_LOAD_SAVE_NV12,
 290             pp_pa_load_save_nv12_gen5,
 291             sizeof(pp_pa_load_save_nv12_gen5),
 292             NULL,
 293         },
 294
 295         pp_plx_load_save_plx_initialize,
 296     },
 297
 298     {
 299         {
 300             "PA_PL3 module",
 301             PP_PA_LOAD_SAVE_PL3,
 302             pp_pa_load_save_pl3_gen5,
 303             sizeof(pp_pa_load_save_pl3_gen5),
 304             NULL,
 305         },
 306
 307         pp_plx_load_save_plx_initialize,
 308     },
 309
 310 };
 311
 312 static const uint32_t pp_null_gen6[][4] = {
 313 #include "shaders/post_processing/gen5_6/null.g6b"
 314 };
 315
 316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 318 };
 319
 320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 322 };
 323
 324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 326 };
 327
 328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 330 };
 331
 332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 334 };
 335
 336 static const uint32_t pp_nv12_avs_gen6[][4] = {
 337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 338 };
 339
 340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 342 };
 343
 344 static const uint32_t pp_nv12_dn_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 350 };
 351
 352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 354 };
 355
 356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 362 };
 363
 364 static struct pp_module pp_modules_gen6[] = {
 365     {
 366         {
 367             "NULL module (for testing)",
 368             PP_NULL,
 369             pp_null_gen6,
 370             sizeof(pp_null_gen6),
 371             NULL,
 372         },
 373
 374         pp_null_initialize,
 375     },
 376
 377     {
 378         {
 379             "NV12_NV12",
 380             PP_NV12_LOAD_SAVE_N12,
 381             pp_nv12_load_save_nv12_gen6,
 382             sizeof(pp_nv12_load_save_nv12_gen6),
 383             NULL,
 384         },
 385
 386         pp_plx_load_save_plx_initialize,
 387     },
 388
 389     {
 390         {
 391             "NV12_PL3",
 392             PP_NV12_LOAD_SAVE_PL3,
 393             pp_nv12_load_save_pl3_gen6,
 394             sizeof(pp_nv12_load_save_pl3_gen6),
 395             NULL,
 396         },
 397
 398         pp_plx_load_save_plx_initialize,
 399     },
 400
 401     {
 402         {
 403             "PL3_NV12",
 404             PP_PL3_LOAD_SAVE_N12,
 405             pp_pl3_load_save_nv12_gen6,
 406             sizeof(pp_pl3_load_save_nv12_gen6),
 407             NULL,
 408         },
 409
 410         pp_plx_load_save_plx_initialize,
 411     },
 412
 413     {
 414         {
 415             "PL3_PL3",
 416             PP_PL3_LOAD_SAVE_N12,
 417             pp_pl3_load_save_pl3_gen6,
 418             sizeof(pp_pl3_load_save_pl3_gen6),
 419             NULL,
 420         },
 421
 422         pp_plx_load_save_plx_initialize,
 423     },
 424
 425     {
 426         {
 427             "NV12 Scaling module",
 428             PP_NV12_SCALING,
 429             pp_nv12_scaling_gen6,
 430             sizeof(pp_nv12_scaling_gen6),
 431             NULL,
 432         },
 433
 434         gen6_nv12_scaling_initialize,
 435     },
 436
 437     {
 438         {
 439             "NV12 AVS module",
 440             PP_NV12_AVS,
 441             pp_nv12_avs_gen6,
 442             sizeof(pp_nv12_avs_gen6),
 443             NULL,
 444         },
 445
 446         pp_nv12_avs_initialize_nlas,
 447     },
 448
 449     {
 450         {
 451             "NV12 DNDI module",
 452             PP_NV12_DNDI,
 453             pp_nv12_dndi_gen6,
 454             sizeof(pp_nv12_dndi_gen6),
 455             NULL,
 456         },
 457
 458         pp_nv12_dndi_initialize,
 459     },
 460
 461     {
 462         {
 463             "NV12 DN module",
 464             PP_NV12_DN,
 465             pp_nv12_dn_gen6,
 466             sizeof(pp_nv12_dn_gen6),
 467             NULL,
 468         },
 469
 470         pp_nv12_dn_initialize,
 471     },
 472     {
 473         {
 474             "NV12_PA module",
 475             PP_NV12_LOAD_SAVE_PA,
 476             pp_nv12_load_save_pa_gen6,
 477             sizeof(pp_nv12_load_save_pa_gen6),
 478             NULL,
 479         },
 480
 481         pp_plx_load_save_plx_initialize,
 482     },
 483
 484     {
 485         {
 486             "PL3_PA module",
 487             PP_PL3_LOAD_SAVE_PA,
 488             pp_pl3_load_save_pa_gen6,
 489             sizeof(pp_pl3_load_save_pa_gen6),
 490             NULL,
 491         },
 492
 493         pp_plx_load_save_plx_initialize,
 494     },
 495
 496     {
 497         {
 498             "PA_NV12 module",
 499             PP_PA_LOAD_SAVE_NV12,
 500             pp_pa_load_save_nv12_gen6,
 501             sizeof(pp_pa_load_save_nv12_gen6),
 502             NULL,
 503         },
 504
 505         pp_plx_load_save_plx_initialize,
 506     },
 507
 508     {
 509         {
 510             "PA_PL3 module",
 511             PP_PA_LOAD_SAVE_PL3,
 512             pp_pa_load_save_pl3_gen6,
 513             sizeof(pp_pa_load_save_pl3_gen6),
 514             NULL,
 515         },
 516
 517         pp_plx_load_save_plx_initialize,
 518     },
 519
 520 };
 521
 522 static const uint32_t pp_null_gen7[][4] = {
 523 };
 524
 525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 527 };
 528
 529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 531 };
 532
 533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 535 };
 536
 537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 539 };
 540
 541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 542 #include "shaders/post_processing/gen7/avs.g7b"
 543 };
 544
 545 static const uint32_t pp_nv12_avs_gen7[][4] = {
 546 #include "shaders/post_processing/gen7/avs.g7b"
 547 };
 548
 549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 550 // #include "shaders/post_processing/gen7/dndi.g7b"
 551 };
 552
 553 static const uint32_t pp_nv12_dn_gen7[][4] = {
 554 };
 555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 556 };
 557 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 558 };
 559 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 560 };
 561 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 562 };
 563
 564 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 565                                            const struct i965_surface *src_surface,
 566                                            const VARectangle *src_rect,
 567                                            struct i965_surface *dst_surface,
 568                                            const VARectangle *dst_rect,
 569                                            void *filter_param);
 570 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 571                                              const struct i965_surface *src_surface,
 572                                              const VARectangle *src_rect,
 573                                              struct i965_surface *dst_surface,
 574                                              const VARectangle *dst_rect,
 575                                              void *filter_param);
 576 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 577                                            const struct i965_surface *src_surface,
 578                                            const VARectangle *src_rect,
 579                                            struct i965_surface *dst_surface,
 580                                            const VARectangle *dst_rect,
 581                                            void *filter_param);
 582
 583 static struct pp_module pp_modules_gen7[] = {
 584     {
 585         {
 586             "NULL module (for testing)",
 587             PP_NULL,
 588             pp_null_gen7,
 589             sizeof(pp_null_gen7),
 590             NULL,
 591         },
 592
 593         pp_null_initialize,
 594     },
 595
 596     {
 597         {
 598             "NV12_NV12",
 599             PP_NV12_LOAD_SAVE_N12,
 600             pp_nv12_load_save_nv12_gen7,
 601             sizeof(pp_nv12_load_save_nv12_gen7),
 602             NULL,
 603         },
 604
 605         gen7_pp_plx_avs_initialize,
 606     },
 607
 608     {
 609         {
 610             "NV12_PL3",
 611             PP_NV12_LOAD_SAVE_PL3,
 612             pp_nv12_load_save_pl3_gen7,
 613             sizeof(pp_nv12_load_save_pl3_gen7),
 614             NULL,
 615         },
 616
 617         gen7_pp_plx_avs_initialize,
 618     },
 619
 620     {
 621         {
 622             "PL3_NV12",
 623             PP_PL3_LOAD_SAVE_N12,
 624             pp_pl3_load_save_nv12_gen7,
 625             sizeof(pp_pl3_load_save_nv12_gen7),
 626             NULL,
 627         },
 628
 629         gen7_pp_plx_avs_initialize,
 630     },
 631
 632     {
 633         {
 634             "PL3_PL3",
 635             PP_PL3_LOAD_SAVE_N12,
 636             pp_pl3_load_save_pl3_gen7,
 637             sizeof(pp_pl3_load_save_pl3_gen7),
 638             NULL,
 639         },
 640
 641         gen7_pp_plx_avs_initialize,
 642     },
 643
 644     {
 645         {
 646             "NV12 Scaling module",
 647             PP_NV12_SCALING,
 648             pp_nv12_scaling_gen7,
 649             sizeof(pp_nv12_scaling_gen7),
 650             NULL,
 651         },
 652
 653         gen7_pp_plx_avs_initialize,
 654     },
 655
 656     {
 657         {
 658             "NV12 AVS module",
 659             PP_NV12_AVS,
 660             pp_nv12_avs_gen7,
 661             sizeof(pp_nv12_avs_gen7),
 662             NULL,
 663         },
 664
 665         gen7_pp_plx_avs_initialize,
 666     },
 667
 668     {
 669         {
 670             "NV12 DNDI module",
 671             PP_NV12_DNDI,
 672             pp_nv12_dndi_gen7,
 673             sizeof(pp_nv12_dndi_gen7),
 674             NULL,
 675         },
 676
 677         gen7_pp_nv12_dndi_initialize,
 678     },
 679
 680     {
 681         {
 682             "NV12 DN module",
 683             PP_NV12_DN,
 684             pp_nv12_dn_gen7,
 685             sizeof(pp_nv12_dn_gen7),
 686             NULL,
 687         },
 688
 689         gen7_pp_nv12_dn_initialize,
 690     },
 691     {
 692         {
 693             "NV12_PA module",
 694             PP_NV12_LOAD_SAVE_PA,
 695             pp_nv12_load_save_pa_gen7,
 696             sizeof(pp_nv12_load_save_pa_gen7),
 697             NULL,
 698         },
 699
 700         pp_plx_load_save_plx_initialize,
 701     },
 702
 703     {
 704         {
 705             "PL3_PA module",
 706             PP_PL3_LOAD_SAVE_PA,
 707             pp_pl3_load_save_pa_gen7,
 708             sizeof(pp_pl3_load_save_pa_gen7),
 709             NULL,
 710         },
 711
 712         pp_plx_load_save_plx_initialize,
 713     },
 714
 715     {
 716         {
 717             "PA_NV12 module",
 718             PP_PA_LOAD_SAVE_NV12,
 719             pp_pa_load_save_nv12_gen7,
 720             sizeof(pp_pa_load_save_nv12_gen7),
 721             NULL,
 722         },
 723
 724         pp_plx_load_save_plx_initialize,
 725     },
 726
 727     {
 728         {
 729             "PA_PL3 module",
 730             PP_PA_LOAD_SAVE_PL3,
 731             pp_pa_load_save_pl3_gen7,
 732             sizeof(pp_pa_load_save_pl3_gen7),
 733             NULL,
 734         },
 735
 736         pp_plx_load_save_plx_initialize,
 737     },
 738
 739 };
 740
 741 static int
 742 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 743 {
 744     struct i965_driver_data *i965 = i965_driver_data(ctx);
 745     int fourcc;
 746
 747     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 748         struct object_image *obj_image = IMAGE(surface->id);
 749         fourcc = obj_image->image.format.fourcc;
 750     } else {
 751         struct object_surface *obj_surface = SURFACE(surface->id);
 752         fourcc = obj_surface->fourcc;
 753     }
 754
 755     return fourcc;
 756 }
 757
 758 static void
 759 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 760 {
 761     switch (tiling) {
 762     case I915_TILING_NONE:
 763         ss->ss3.tiled_surface = 0;
 764         ss->ss3.tile_walk = 0;
 765         break;
 766     case I915_TILING_X:
 767         ss->ss3.tiled_surface = 1;
 768         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 769         break;
 770     case I915_TILING_Y:
 771         ss->ss3.tiled_surface = 1;
 772         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 773         break;
 774     }
 775 }
 776
 777 static void
 778 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 779 {
 780     switch (tiling) {
 781     case I915_TILING_NONE:
 782         ss->ss2.tiled_surface = 0;
 783         ss->ss2.tile_walk = 0;
 784         break;
 785     case I915_TILING_X:
 786         ss->ss2.tiled_surface = 1;
 787         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 788         break;
 789     case I915_TILING_Y:
 790         ss->ss2.tiled_surface = 1;
 791         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 792         break;
 793     }
 794 }
 795
 796 static void
 797 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 798 {
 799     switch (tiling) {
 800     case I915_TILING_NONE:
 801         ss->ss0.tiled_surface = 0;
 802         ss->ss0.tile_walk = 0;
 803         break;
 804     case I915_TILING_X:
 805         ss->ss0.tiled_surface = 1;
 806         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 807         break;
 808     case I915_TILING_Y:
 809         ss->ss0.tiled_surface = 1;
 810         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 811         break;
 812     }
 813 }
 814
 815 static void
 816 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 817 {
 818     switch (tiling) {
 819     case I915_TILING_NONE:
 820         ss->ss2.tiled_surface = 0;
 821         ss->ss2.tile_walk = 0;
 822         break;
 823     case I915_TILING_X:
 824         ss->ss2.tiled_surface = 1;
 825         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 826         break;
 827     case I915_TILING_Y:
 828         ss->ss2.tiled_surface = 1;
 829         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 830         break;
 831     }
 832 }
 833
 834 static void
 835 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 836 {
 837     struct i965_interface_descriptor *desc;
 838     dri_bo *bo;
 839     int pp_index = pp_context->current_pp;
 840
 841     bo = pp_context->idrt.bo;
 842     dri_bo_map(bo, 1);
 843     assert(bo->virtual);
 844     desc = bo->virtual;
 845     memset(desc, 0, sizeof(*desc));
 846     desc->desc0.grf_reg_blocks = 10;
 847     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 848     desc->desc1.const_urb_entry_read_offset = 0;
 849     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 850     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 851     desc->desc2.sampler_count = 0;
 852     desc->desc3.binding_table_entry_count = 0;
 853     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 854
 855     dri_bo_emit_reloc(bo,
 856                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 857                       desc->desc0.grf_reg_blocks,
 858                       offsetof(struct i965_interface_descriptor, desc0),
 859                       pp_context->pp_modules[pp_index].kernel.bo);
 860
 861     dri_bo_emit_reloc(bo,
 862                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 863                       desc->desc2.sampler_count << 2,
 864                       offsetof(struct i965_interface_descriptor, desc2),
 865                       pp_context->sampler_state_table.bo);
 866
 867     dri_bo_unmap(bo);
 868     pp_context->idrt.num_interface_descriptors++;
 869 }
 870
 871 static void
 872 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 873 {
 874     struct i965_vfe_state *vfe_state;
 875     dri_bo *bo;
 876
 877     bo = pp_context->vfe_state.bo;
 878     dri_bo_map(bo, 1);
 879     assert(bo->virtual);
 880     vfe_state = bo->virtual;
 881     memset(vfe_state, 0, sizeof(*vfe_state));
 882     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 883     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 884     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 885     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 886     vfe_state->vfe1.children_present = 0;
 887     vfe_state->vfe2.interface_descriptor_base =
 888         pp_context->idrt.bo->offset >> 4; /* reloc */
 889     dri_bo_emit_reloc(bo,
 890                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 891                       0,
 892                       offsetof(struct i965_vfe_state, vfe2),
 893                       pp_context->idrt.bo);
 894     dri_bo_unmap(bo);
 895 }
 896
 897 static void
 898 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 899 {
 900     unsigned char *constant_buffer;
 901     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 902
 903     assert(sizeof(*pp_static_parameter) == 128);
 904     dri_bo_map(pp_context->curbe.bo, 1);
 905     assert(pp_context->curbe.bo->virtual);
 906     constant_buffer = pp_context->curbe.bo->virtual;
 907     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 908     dri_bo_unmap(pp_context->curbe.bo);
 909 }
 910
 911 static void
 912 ironlake_pp_states_setup(VADriverContextP ctx,
 913                          struct i965_post_processing_context *pp_context)
 914 {
 915     ironlake_pp_interface_descriptor_table(pp_context);
 916     ironlake_pp_vfe_state(pp_context);
 917     ironlake_pp_upload_constants(pp_context);
 918 }
 919
 920 static void
 921 ironlake_pp_pipeline_select(VADriverContextP ctx,
 922                             struct i965_post_processing_context *pp_context)
 923 {
 924     struct intel_batchbuffer *batch = pp_context->batch;
 925
 926     BEGIN_BATCH(batch, 1);
 927     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 928     ADVANCE_BATCH(batch);
 929 }
 930
 931 static void
 932 ironlake_pp_urb_layout(VADriverContextP ctx,
 933                        struct i965_post_processing_context *pp_context)
 934 {
 935     struct intel_batchbuffer *batch = pp_context->batch;
 936     unsigned int vfe_fence, cs_fence;
 937
 938     vfe_fence = pp_context->urb.cs_start;
 939     cs_fence = pp_context->urb.size;
 940
 941     BEGIN_BATCH(batch, 3);
 942     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 943     OUT_BATCH(batch, 0);
 944     OUT_BATCH(batch,
 945               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 946               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 947     ADVANCE_BATCH(batch);
 948 }
 949
 950 static void
 951 ironlake_pp_state_base_address(VADriverContextP ctx,
 952                                struct i965_post_processing_context *pp_context)
 953 {
 954     struct intel_batchbuffer *batch = pp_context->batch;
 955
 956     BEGIN_BATCH(batch, 8);
 957     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 958     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 959     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 960     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 961     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 962     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 963     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 964     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 965     ADVANCE_BATCH(batch);
 966 }
 967
 968 static void
 969 ironlake_pp_state_pointers(VADriverContextP ctx,
 970                            struct i965_post_processing_context *pp_context)
 971 {
 972     struct intel_batchbuffer *batch = pp_context->batch;
 973
 974     BEGIN_BATCH(batch, 3);
 975     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 976     OUT_BATCH(batch, 0);
 977     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 978     ADVANCE_BATCH(batch);
 979 }
 980
 981 static void
 982 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 983                           struct i965_post_processing_context *pp_context)
 984 {
 985     struct intel_batchbuffer *batch = pp_context->batch;
 986
 987     BEGIN_BATCH(batch, 2);
 988     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 989     OUT_BATCH(batch,
 990               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 991               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 992     ADVANCE_BATCH(batch);
 993 }
 994
 995 static void
 996 ironlake_pp_constant_buffer(VADriverContextP ctx,
 997                             struct i965_post_processing_context *pp_context)
 998 {
 999     struct intel_batchbuffer *batch = pp_context->batch;
1000
1001     BEGIN_BATCH(batch, 2);
1002     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1003     OUT_RELOC(batch, pp_context->curbe.bo,
1004               I915_GEM_DOMAIN_INSTRUCTION, 0,
1005               pp_context->urb.size_cs_entry - 1);
1006     ADVANCE_BATCH(batch);
1007 }
1008
1009 static void
1010 ironlake_pp_object_walker(VADriverContextP ctx,
1011                           struct i965_post_processing_context *pp_context)
1012 {
1013     struct intel_batchbuffer *batch = pp_context->batch;
1014     int x, x_steps, y, y_steps;
1015     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1016
1017     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1018     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1019
1020     for (y = 0; y < y_steps; y++) {
1021         for (x = 0; x < x_steps; x++) {
1022             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1023                 BEGIN_BATCH(batch, 20);
1024                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1025                 OUT_BATCH(batch, 0);
1026                 OUT_BATCH(batch, 0); /* no indirect data */
1027                 OUT_BATCH(batch, 0);
1028
1029                 /* inline data grf 5-6 */
1030                 assert(sizeof(*pp_inline_parameter) == 64);
1031                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1032
1033                 ADVANCE_BATCH(batch);
1034             }
1035         }
1036     }
1037 }
1038
1039 static void
1040 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1041                            struct i965_post_processing_context *pp_context)
1042 {
1043     struct intel_batchbuffer *batch = pp_context->batch;
1044
1045     intel_batchbuffer_start_atomic(batch, 0x1000);
1046     intel_batchbuffer_emit_mi_flush(batch);
1047     ironlake_pp_pipeline_select(ctx, pp_context);
1048     ironlake_pp_state_base_address(ctx, pp_context);
1049     ironlake_pp_state_pointers(ctx, pp_context);
1050     ironlake_pp_urb_layout(ctx, pp_context);
1051     ironlake_pp_cs_urb_layout(ctx, pp_context);
1052     ironlake_pp_constant_buffer(ctx, pp_context);
1053     ironlake_pp_object_walker(ctx, pp_context);
1054     intel_batchbuffer_end_atomic(batch);
1055 }
1056
1057 static void
1058 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1059                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1060                           int width, int height, int pitch, int format,
1061                           int index, int is_target)
1062 {
1063     struct i965_surface_state *ss;
1064     dri_bo *ss_bo;
1065     unsigned int tiling;
1066     unsigned int swizzle;
1067
1068     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1069     ss_bo = pp_context->surface_state_binding_table.bo;
1070     assert(ss_bo);
1071
1072     dri_bo_map(ss_bo, True);
1073     assert(ss_bo->virtual);
1074     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1075     memset(ss, 0, sizeof(*ss));
1076     ss->ss0.surface_type = I965_SURFACE_2D;
1077     ss->ss0.surface_format = format;
1078     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1079     ss->ss2.width = width - 1;
1080     ss->ss2.height = height - 1;
1081     ss->ss3.pitch = pitch - 1;
1082     pp_set_surface_tiling(ss, tiling);
1083     dri_bo_emit_reloc(ss_bo,
1084                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1085                       surf_bo_offset,
1086                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1087                       surf_bo);
1088     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1089     dri_bo_unmap(ss_bo);
1090 }
1091
1092 static void
1093 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1094                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1095                            int width, int height, int wpitch,
1096                            int xoffset, int yoffset,
1097                            int format, int interleave_chroma,
1098                            int index)
1099 {
1100     struct i965_surface_state2 *ss2;
1101     dri_bo *ss2_bo;
1102     unsigned int tiling;
1103     unsigned int swizzle;
1104
1105     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1106     ss2_bo = pp_context->surface_state_binding_table.bo;
1107     assert(ss2_bo);
1108
1109     dri_bo_map(ss2_bo, True);
1110     assert(ss2_bo->virtual);
1111     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1112     memset(ss2, 0, sizeof(*ss2));
1113     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1114     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1115     ss2->ss1.width = width - 1;
1116     ss2->ss1.height = height - 1;
1117     ss2->ss2.pitch = wpitch - 1;
1118     ss2->ss2.interleave_chroma = interleave_chroma;
1119     ss2->ss2.surface_format = format;
1120     ss2->ss3.x_offset_for_cb = xoffset;
1121     ss2->ss3.y_offset_for_cb = yoffset;
1122     pp_set_surface2_tiling(ss2, tiling);
1123     dri_bo_emit_reloc(ss2_bo,
1124                       I915_GEM_DOMAIN_RENDER, 0,
1125                       surf_bo_offset,
1126                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1127                       surf_bo);
1128     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1129     dri_bo_unmap(ss2_bo);
1130 }
1131
1132 static void
1133 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1134                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1135                           int width, int height, int pitch, int format,
1136                           int index, int is_target)
1137 {
1138     struct gen7_surface_state *ss;
1139     dri_bo *ss_bo;
1140     unsigned int tiling;
1141     unsigned int swizzle;
1142
1143     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1144     ss_bo = pp_context->surface_state_binding_table.bo;
1145     assert(ss_bo);
1146
1147     dri_bo_map(ss_bo, True);
1148     assert(ss_bo->virtual);
1149     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1150     memset(ss, 0, sizeof(*ss));
1151     ss->ss0.surface_type = I965_SURFACE_2D;
1152     ss->ss0.surface_format = format;
1153     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1154     ss->ss2.width = width - 1;
1155     ss->ss2.height = height - 1;
1156     ss->ss3.pitch = pitch - 1;
1157     gen7_pp_set_surface_tiling(ss, tiling);
1158     dri_bo_emit_reloc(ss_bo,
1159                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1160                       surf_bo_offset,
1161                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1162                       surf_bo);
1163     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1164     dri_bo_unmap(ss_bo);
1165 }
1166
1167 static void
1168 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1169                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1170                            int width, int height, int wpitch,
1171                            int xoffset, int yoffset,
1172                            int format, int interleave_chroma,
1173                            int index)
1174 {
1175     struct gen7_surface_state2 *ss2;
1176     dri_bo *ss2_bo;
1177     unsigned int tiling;
1178     unsigned int swizzle;
1179
1180     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1181     ss2_bo = pp_context->surface_state_binding_table.bo;
1182     assert(ss2_bo);
1183
1184     dri_bo_map(ss2_bo, True);
1185     assert(ss2_bo->virtual);
1186     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1187     memset(ss2, 0, sizeof(*ss2));
1188     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1189     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1190     ss2->ss1.width = width - 1;
1191     ss2->ss1.height = height - 1;
1192     ss2->ss2.pitch = wpitch - 1;
1193     ss2->ss2.interleave_chroma = interleave_chroma;
1194     ss2->ss2.surface_format = format;
1195     ss2->ss3.x_offset_for_cb = xoffset;
1196     ss2->ss3.y_offset_for_cb = yoffset;
1197     gen7_pp_set_surface2_tiling(ss2, tiling);
1198     dri_bo_emit_reloc(ss2_bo,
1199                       I915_GEM_DOMAIN_RENDER, 0,
1200                       surf_bo_offset,
1201                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1202                       surf_bo);
1203     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1204     dri_bo_unmap(ss2_bo);
1205 }
1206
1207 static void
1208 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1209                                 const struct i965_surface *surface,
1210                                 int base_index, int is_target,
1211                                 int *width, int *height, int *pitch, int *offset)
1212 {
1213     struct i965_driver_data *i965 = i965_driver_data(ctx);
1214     struct object_surface *obj_surface;
1215     struct object_image *obj_image;
1216     dri_bo *bo;
1217     int fourcc = pp_get_surface_fourcc(ctx, surface);
1218     const int Y = 0;
1219     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1220     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1221     const int UV = 1;
1222     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1223     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1224
1225     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1226         obj_surface = SURFACE(surface->id);
1227         bo = obj_surface->bo;
1228         width[0] = obj_surface->orig_width;
1229         height[0] = obj_surface->orig_height;
1230         pitch[0] = obj_surface->width;
1231         offset[0] = 0;
1232
1233         if (packed_yuv ) {
1234             width[0] = obj_surface->orig_width * 2;
1235             pitch[0] = obj_surface->width * 2;
1236         }
1237         else if (interleaved_uv) {
1238             width[1] = obj_surface->orig_width;
1239             height[1] = obj_surface->orig_height / 2;
1240             pitch[1] = obj_surface->width;
1241             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1242         } else {
1243             width[1] = obj_surface->orig_width / 2;
1244             height[1] = obj_surface->orig_height / 2;
1245             pitch[1] = obj_surface->width / 2;
1246             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1247             width[2] = obj_surface->orig_width / 2;
1248             height[2] = obj_surface->orig_height / 2;
1249             pitch[2] = obj_surface->width / 2;
1250             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1251         }
1252     } else {
1253         obj_image = IMAGE(surface->id);
1254         bo = obj_image->bo;
1255         width[0] = obj_image->image.width;
1256         height[0] = obj_image->image.height;
1257         pitch[0] = obj_image->image.pitches[0];
1258         offset[0] = obj_image->image.offsets[0];
1259
1260         if (packed_yuv ) {
1261             width[0] = obj_image->image.width * 2;
1262         }
1263         else if (interleaved_uv) {
1264             width[1] = obj_image->image.width;
1265             height[1] = obj_image->image.height / 2;
1266             pitch[1] = obj_image->image.pitches[1];
1267             offset[1] = obj_image->image.offsets[1];
1268         } else {
1269             width[1] = obj_image->image.width / 2;
1270             height[1] = obj_image->image.height / 2;
1271             pitch[1] = obj_image->image.pitches[1];
1272             offset[1] = obj_image->image.offsets[1];
1273             width[2] = obj_image->image.width / 2;
1274             height[2] = obj_image->image.height / 2;
1275             pitch[2] = obj_image->image.pitches[2];
1276             offset[2] = obj_image->image.offsets[2];
1277         }
1278     }
1279
1280     /* Y surface */
1281     i965_pp_set_surface_state(ctx, pp_context,
1282                               bo, offset[Y],
1283                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1284                               base_index, is_target);
1285
1286     if (!packed_yuv) {
1287         if (interleaved_uv) {
1288             i965_pp_set_surface_state(ctx, pp_context,
1289                                       bo, offset[UV],
1290                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1291                                       base_index + 1, is_target);
1292         } else {
1293             /* U surface */
1294             i965_pp_set_surface_state(ctx, pp_context,
1295                                       bo, offset[U],
1296                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1297                                       base_index + 1, is_target);
1298
1299             /* V surface */
1300             i965_pp_set_surface_state(ctx, pp_context,
1301                                       bo, offset[V],
1302                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1303                                       base_index + 2, is_target);
1304         }
1305     }
1306
1307 }
1308
1309 static void
1310 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1311                                      const struct i965_surface *surface,
1312                                      int base_index, int is_target,
1313                                      int *width, int *height, int *pitch, int *offset)
1314 {
1315     struct i965_driver_data *i965 = i965_driver_data(ctx);
1316     struct object_surface *obj_surface;
1317     struct object_image *obj_image;
1318     dri_bo *bo;
1319     int fourcc = pp_get_surface_fourcc(ctx, surface);
1320     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1321                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1322     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1323                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1324     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1325
1326     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1327         obj_surface = SURFACE(surface->id);
1328         bo = obj_surface->bo;
1329         width[0] = obj_surface->orig_width;
1330         height[0] = obj_surface->orig_height;
1331         pitch[0] = obj_surface->width;
1332         offset[0] = 0;
1333
1334         width[1] = obj_surface->cb_cr_width;
1335         height[1] = obj_surface->cb_cr_height;
1336         pitch[1] = obj_surface->cb_cr_pitch;
1337         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1338
1339         width[2] = obj_surface->cb_cr_width;
1340         height[2] = obj_surface->cb_cr_height;
1341         pitch[2] = obj_surface->cb_cr_pitch;
1342         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1343     } else {
1344         obj_image = IMAGE(surface->id);
1345         bo = obj_image->bo;
1346         width[0] = obj_image->image.width;
1347         height[0] = obj_image->image.height;
1348         pitch[0] = obj_image->image.pitches[0];
1349         offset[0] = obj_image->image.offsets[0];
1350
1351         if (interleaved_uv) {
1352             width[1] = obj_image->image.width;
1353             height[1] = obj_image->image.height / 2;
1354             pitch[1] = obj_image->image.pitches[1];
1355             offset[1] = obj_image->image.offsets[1];
1356         } else {
1357             width[1] = obj_image->image.width / 2;
1358             height[1] = obj_image->image.height / 2;
1359             pitch[1] = obj_image->image.pitches[U];
1360             offset[1] = obj_image->image.offsets[U];
1361             width[2] = obj_image->image.width / 2;
1362             height[2] = obj_image->image.height / 2;
1363             pitch[2] = obj_image->image.pitches[V];
1364             offset[2] = obj_image->image.offsets[V];
1365         }
1366     }
1367
1368     if (is_target) {
1369         gen7_pp_set_surface_state(ctx, pp_context,
1370                                   bo, 0,
1371                                   width[0] / 4, height[0], pitch[0],
1372                                   I965_SURFACEFORMAT_R8_SINT,
1373                                   base_index, 1);
1374
1375         if (interleaved_uv) {
1376             gen7_pp_set_surface_state(ctx, pp_context,
1377                                       bo, offset[1],
1378                                       width[1] / 2, height[1], pitch[1],
1379                                       I965_SURFACEFORMAT_R8G8_SINT,
1380                                       base_index + 1, 1);
1381         } else {
1382             gen7_pp_set_surface_state(ctx, pp_context,
1383                                       bo, offset[1],
1384                                       width[1] / 4, height[1], pitch[1],
1385                                       I965_SURFACEFORMAT_R8_SINT,
1386                                       base_index + 1, 1);
1387             gen7_pp_set_surface_state(ctx, pp_context,
1388                                       bo, offset[2],
1389                                       width[2] / 4, height[2], pitch[2],
1390                                       I965_SURFACEFORMAT_R8_SINT,
1391                                       base_index + 2, 1);
1392         }
1393     } else {
1394         gen7_pp_set_surface2_state(ctx, pp_context,
1395                                    bo, offset[0],
1396                                    width[0], height[0], pitch[0],
1397                                    0, 0,
1398                                    SURFACE_FORMAT_Y8_UNORM, 0,
1399                                    base_index);
1400
1401         if (interleaved_uv) {
1402             gen7_pp_set_surface2_state(ctx, pp_context,
1403                                        bo, offset[1],
1404                                        width[1], height[1], pitch[1],
1405                                        0, 0,
1406                                        SURFACE_FORMAT_R8B8_UNORM, 0,
1407                                        base_index + 1);
1408         } else {
1409             gen7_pp_set_surface2_state(ctx, pp_context,
1410                                        bo, offset[1],
1411                                        width[1], height[1], pitch[1],
1412                                        0, 0,
1413                                        SURFACE_FORMAT_R8_UNORM, 0,
1414                                        base_index + 1);
1415             gen7_pp_set_surface2_state(ctx, pp_context,
1416                                        bo, offset[2],
1417                                        width[2], height[2], pitch[2],
1418                                        0, 0,
1419                                        SURFACE_FORMAT_R8_UNORM, 0,
1420                                        base_index + 2);
1421         }
1422     }
1423 }
1424
1425 static int
1426 pp_null_x_steps(void *private_context)
1427 {
1428     return 1;
1429 }
1430
1431 static int
1432 pp_null_y_steps(void *private_context)
1433 {
1434     return 1;
1435 }
1436
1437 static int
1438 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1439 {
1440     return 0;
1441 }
1442
1443 static VAStatus
1444 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1445                    const struct i965_surface *src_surface,
1446                    const VARectangle *src_rect,
1447                    struct i965_surface *dst_surface,
1448                    const VARectangle *dst_rect,
1449                    void *filter_param)
1450 {
1451     /* private function & data */
1452     pp_context->pp_x_steps = pp_null_x_steps;
1453     pp_context->pp_y_steps = pp_null_y_steps;
1454     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1455
1456     dst_surface->flags = src_surface->flags;
1457
1458     return VA_STATUS_SUCCESS;
1459 }
1460
1461 static int
1462 pp_load_save_x_steps(void *private_context)
1463 {
1464     return 1;
1465 }
1466
1467 static int
1468 pp_load_save_y_steps(void *private_context)
1469 {
1470     struct pp_load_save_context *pp_load_save_context = private_context;
1471
1472     return pp_load_save_context->dest_h / 8;
1473 }
1474
1475 static int
1476 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1477 {
1478     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1479
1480     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1481     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1482     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1483     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1484
1485     return 0;
1486 }
1487
1488 static VAStatus
1489 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1490                                 const struct i965_surface *src_surface,
1491                                 const VARectangle *src_rect,
1492                                 struct i965_surface *dst_surface,
1493                                 const VARectangle *dst_rect,
1494                                 void *filter_param)
1495 {
1496     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1497     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1498     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1499     int width[3], height[3], pitch[3], offset[3];
1500     const int Y = 0;
1501
1502     /* source surface */
1503     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1504                                     width, height, pitch, offset);
1505
1506     /* destination surface */
1507     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1508                                     width, height, pitch, offset);
1509
1510     /* private function & data */
1511     pp_context->pp_x_steps = pp_load_save_x_steps;
1512     pp_context->pp_y_steps = pp_load_save_y_steps;
1513     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1514     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1515     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1516
1517     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1518     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1519
1520     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1521     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1522
1523     dst_surface->flags = src_surface->flags;
1524
1525     return VA_STATUS_SUCCESS;
1526 }
1527
1528 static int
1529 pp_scaling_x_steps(void *private_context)
1530 {
1531     return 1;
1532 }
1533
1534 static int
1535 pp_scaling_y_steps(void *private_context)
1536 {
1537     struct pp_scaling_context *pp_scaling_context = private_context;
1538
1539     return pp_scaling_context->dest_h / 8;
1540 }
1541
1542 static int
1543 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1544 {
1545     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1546     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1547     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1548     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1549     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1550
1551     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1552     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1553     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1554     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1555
1556     return 0;
1557 }
1558
1559 static VAStatus
1560 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1561                            const struct i965_surface *src_surface,
1562                            const VARectangle *src_rect,
1563                            struct i965_surface *dst_surface,
1564                            const VARectangle *dst_rect,
1565                            void *filter_param)
1566 {
1567     struct i965_driver_data *i965 = i965_driver_data(ctx);
1568     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1569     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1570     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1571     struct object_surface *obj_surface;
1572     struct i965_sampler_state *sampler_state;
1573     int in_w, in_h, in_wpitch, in_hpitch;
1574     int out_w, out_h, out_wpitch, out_hpitch;
1575
1576     /* source surface */
1577     obj_surface = SURFACE(src_surface->id);
1578     in_w = obj_surface->orig_width;
1579     in_h = obj_surface->orig_height;
1580     in_wpitch = obj_surface->width;
1581     in_hpitch = obj_surface->height;
1582
1583     /* source Y surface index 1 */
1584     i965_pp_set_surface_state(ctx, pp_context,
1585                               obj_surface->bo, 0,
1586                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1587                               1, 0);
1588
1589     /* source UV surface index 2 */
1590     i965_pp_set_surface_state(ctx, pp_context,
1591                               obj_surface->bo, in_wpitch * in_hpitch,
1592                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1593                               2, 0);
1594
1595     /* destination surface */
1596     obj_surface = SURFACE(dst_surface->id);
1597     out_w = obj_surface->orig_width;
1598     out_h = obj_surface->orig_height;
1599     out_wpitch = obj_surface->width;
1600     out_hpitch = obj_surface->height;
1601
1602     /* destination Y surface index 7 */
1603     i965_pp_set_surface_state(ctx, pp_context,
1604                               obj_surface->bo, 0,
1605                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1606                               7, 1);
1607
1608     /* destination UV surface index 8 */
1609     i965_pp_set_surface_state(ctx, pp_context,
1610                               obj_surface->bo, out_wpitch * out_hpitch,
1611                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1612                               8, 1);
1613
1614     /* sampler state */
1615     dri_bo_map(pp_context->sampler_state_table.bo, True);
1616     assert(pp_context->sampler_state_table.bo->virtual);
1617     sampler_state = pp_context->sampler_state_table.bo->virtual;
1618
1619     /* SIMD16 Y index 1 */
1620     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1621     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1622     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1623     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1624     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1625
1626     /* SIMD16 UV index 2 */
1627     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1628     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1629     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1630     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1631     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1632
1633     dri_bo_unmap(pp_context->sampler_state_table.bo);
1634
1635     /* private function & data */
1636     pp_context->pp_x_steps = pp_scaling_x_steps;
1637     pp_context->pp_y_steps = pp_scaling_y_steps;
1638     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1639
1640     pp_scaling_context->dest_x = dst_rect->x;
1641     pp_scaling_context->dest_y = dst_rect->y;
1642     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1643     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1644     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1645     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1646
1647     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1648
1649     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1650     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1651     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1652     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1653     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1654
1655     dst_surface->flags = src_surface->flags;
1656
1657     return VA_STATUS_SUCCESS;
1658 }
1659
1660 static int
1661 pp_avs_x_steps(void *private_context)
1662 {
1663     struct pp_avs_context *pp_avs_context = private_context;
1664
1665     return pp_avs_context->dest_w / 16;
1666 }
1667
1668 static int
1669 pp_avs_y_steps(void *private_context)
1670 {
1671     return 1;
1672 }
1673
1674 static int
1675 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1676 {
1677     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1678     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1679     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1680     float src_x_steping, src_y_steping, video_step_delta;
1681     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1682
1683     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1684         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1685         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1686     } else if (tmp_w >= pp_avs_context->dest_w) {
1687         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1688         pp_inline_parameter->grf6.video_step_delta = 0;
1689
1690         if (x == 0) {
1691             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1692                 pp_avs_context->src_normalized_x;
1693         } else {
1694             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1695             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1696             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1697                 16 * 15 * video_step_delta / 2;
1698         }
1699     } else {
1700         int n0, n1, n2, nls_left, nls_right;
1701         int factor_a = 5, factor_b = 4;
1702         float f;
1703
1704         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1705         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1706         n2 = tmp_w / (16 * factor_a);
1707         nls_left = n0 + n2;
1708         nls_right = n1 + n2;
1709         f = (float) n2 * 16 / tmp_w;
1710
1711         if (n0 < 5) {
1712             pp_inline_parameter->grf6.video_step_delta = 0.0;
1713
1714             if (x == 0) {
1715                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1716                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1717             } else {
1718                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1719                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1720                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1721                     16 * 15 * video_step_delta / 2;
1722             }
1723         } else {
1724             if (x < nls_left) {
1725                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1726                 float a = f / (nls_left * 16 * factor_b);
1727                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1728
1729                 pp_inline_parameter->grf6.video_step_delta = b;
1730
1731                 if (x == 0) {
1732                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1733                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1734                 } else {
1735                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1736                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1737                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1738                         16 * 15 * video_step_delta / 2;
1739                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1740                 }
1741             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1742                 /* scale the center linearly */
1743                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1744                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1745                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1746                     16 * 15 * video_step_delta / 2;
1747                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1748                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1749             } else {
1750                 float a = f / (nls_right * 16 * factor_b);
1751                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1752
1753                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1754                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1755                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1756                     16 * 15 * video_step_delta / 2;
1757                 pp_inline_parameter->grf6.video_step_delta = -b;
1758
1759                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1760                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1761                 else
1762                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1763             }
1764         }
1765     }
1766
1767     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1768     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1769     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1770     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1771
1772     return 0;
1773 }
1774
1775 static VAStatus
1776 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1777                        const struct i965_surface *src_surface,
1778                        const VARectangle *src_rect,
1779                        struct i965_surface *dst_surface,
1780                        const VARectangle *dst_rect,
1781                        void *filter_param,
1782                        int nlas)
1783 {
1784     struct i965_driver_data *i965 = i965_driver_data(ctx);
1785     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1786     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1787     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1788     struct object_surface *obj_surface;
1789     struct i965_sampler_8x8 *sampler_8x8;
1790     struct i965_sampler_8x8_state *sampler_8x8_state;
1791     int index;
1792     int in_w, in_h, in_wpitch, in_hpitch;
1793     int out_w, out_h, out_wpitch, out_hpitch;
1794     int i;
1795
1796     /* surface */
1797     obj_surface = SURFACE(src_surface->id);
1798     in_w = obj_surface->orig_width;
1799     in_h = obj_surface->orig_height;
1800     in_wpitch = obj_surface->width;
1801     in_hpitch = obj_surface->height;
1802
1803     /* source Y surface index 1 */
1804     i965_pp_set_surface2_state(ctx, pp_context,
1805                                obj_surface->bo, 0,
1806                                in_w, in_h, in_wpitch,
1807                                0, 0,
1808                                SURFACE_FORMAT_Y8_UNORM, 0,
1809                                1);
1810
1811     /* source UV surface index 2 */
1812     i965_pp_set_surface2_state(ctx, pp_context,
1813                                obj_surface->bo, in_wpitch * in_hpitch,
1814                                in_w / 2, in_h / 2, in_wpitch,
1815                                0, 0,
1816                                SURFACE_FORMAT_R8B8_UNORM, 0,
1817                                2);
1818
1819     /* destination surface */
1820     obj_surface = SURFACE(dst_surface->id);
1821     out_w = obj_surface->orig_width;
1822     out_h = obj_surface->orig_height;
1823     out_wpitch = obj_surface->width;
1824     out_hpitch = obj_surface->height;
1825     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1826
1827     /* destination Y surface index 7 */
1828     i965_pp_set_surface_state(ctx, pp_context,
1829                               obj_surface->bo, 0,
1830                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1831                               7, 1);
1832
1833     /* destination UV surface index 8 */
1834     i965_pp_set_surface_state(ctx, pp_context,
1835                               obj_surface->bo, out_wpitch * out_hpitch,
1836                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1837                               8, 1);
1838
1839     /* sampler 8x8 state */
1840     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1841     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1842     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1843     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1844     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1845
1846     for (i = 0; i < 17; i++) {
1847         /* for Y channel, currently ignore */
1848         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1849         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1850         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1851         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1852         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1853         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1854         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1855         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1856         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1857         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1858         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1859         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1860         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1861         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1862         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1863         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1864         /* for U/V channel, 0.25 */
1865         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1866         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1867         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1868         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1869         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1870         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1871         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1872         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1873         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1874         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1875         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1876         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1877         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1878         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1879         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1880         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1881     }
1882
1883     sampler_8x8_state->dw136.default_sharpness_level = 0;
1884     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1885     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1886     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1887     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1888
1889     /* sampler 8x8 */
1890     dri_bo_map(pp_context->sampler_state_table.bo, True);
1891     assert(pp_context->sampler_state_table.bo->virtual);
1892     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1893     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1894
1895     /* sample_8x8 Y index 1 */
1896     index = 1;
1897     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1898     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1899     sampler_8x8[index].dw0.ief_bypass = 1;
1900     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1901     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1902     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1903     sampler_8x8[index].dw2.global_noise_estimation = 22;
1904     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1905     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1906     sampler_8x8[index].dw3.strong_edge_weight = 7;
1907     sampler_8x8[index].dw3.regular_weight = 2;
1908     sampler_8x8[index].dw3.non_edge_weight = 0;
1909     sampler_8x8[index].dw3.gain_factor = 40;
1910     sampler_8x8[index].dw4.steepness_boost = 0;
1911     sampler_8x8[index].dw4.steepness_threshold = 0;
1912     sampler_8x8[index].dw4.mr_boost = 0;
1913     sampler_8x8[index].dw4.mr_threshold = 5;
1914     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1915     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1916     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1917     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1918     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1919     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1920     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1921     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1922     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1923     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1924     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1925     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1926     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1927     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1928     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1929     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1930     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1931     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1932     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1933     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1934     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1935     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1936     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1937     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1938     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1939     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1940     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1941     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1942     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1943     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1944     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1945     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1946     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1947     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1948     sampler_8x8[index].dw13.limiter_boost = 0;
1949     sampler_8x8[index].dw13.minimum_limiter = 10;
1950     sampler_8x8[index].dw13.maximum_limiter = 11;
1951     sampler_8x8[index].dw14.clip_limiter = 130;
1952     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1953                       I915_GEM_DOMAIN_RENDER,
1954                       0,
1955                       0,
1956                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1957                       pp_context->sampler_state_table.bo_8x8);
1958
1959     /* sample_8x8 UV index 2 */
1960     index = 2;
1961     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1962     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1963     sampler_8x8[index].dw0.ief_bypass = 1;
1964     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1965     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1966     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1967     sampler_8x8[index].dw2.global_noise_estimation = 22;
1968     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1969     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1970     sampler_8x8[index].dw3.strong_edge_weight = 7;
1971     sampler_8x8[index].dw3.regular_weight = 2;
1972     sampler_8x8[index].dw3.non_edge_weight = 0;
1973     sampler_8x8[index].dw3.gain_factor = 40;
1974     sampler_8x8[index].dw4.steepness_boost = 0;
1975     sampler_8x8[index].dw4.steepness_threshold = 0;
1976     sampler_8x8[index].dw4.mr_boost = 0;
1977     sampler_8x8[index].dw4.mr_threshold = 5;
1978     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1979     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1980     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1981     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1982     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1983     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1984     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1985     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1986     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1987     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1988     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1989     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1990     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1991     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1992     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1993     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1994     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1995     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1996     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1997     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1998     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1999     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2000     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2001     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2002     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2003     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2004     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2005     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2006     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2007     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2008     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2009     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2010     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2011     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2012     sampler_8x8[index].dw13.limiter_boost = 0;
2013     sampler_8x8[index].dw13.minimum_limiter = 10;
2014     sampler_8x8[index].dw13.maximum_limiter = 11;
2015     sampler_8x8[index].dw14.clip_limiter = 130;
2016     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2017                       I915_GEM_DOMAIN_RENDER,
2018                       0,
2019                       0,
2020                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2021                       pp_context->sampler_state_table.bo_8x8);
2022
2023     dri_bo_unmap(pp_context->sampler_state_table.bo);
2024
2025     /* private function & data */
2026     pp_context->pp_x_steps = pp_avs_x_steps;
2027     pp_context->pp_y_steps = pp_avs_y_steps;
2028     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2029
2030     pp_avs_context->dest_x = dst_rect->x;
2031     pp_avs_context->dest_y = dst_rect->y;
2032     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2033     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2034     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2035     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2036     pp_avs_context->src_w = src_rect->width;
2037     pp_avs_context->src_h = src_rect->height;
2038
2039     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2040     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2041
2042     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2043     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2044     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2045     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2046     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2047     pp_inline_parameter->grf6.video_step_delta = 0.0;
2048
2049     dst_surface->flags = src_surface->flags;
2050
2051     return VA_STATUS_SUCCESS;
2052 }
2053
2054 static VAStatus
2055 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2056                             const struct i965_surface *src_surface,
2057                             const VARectangle *src_rect,
2058                             struct i965_surface *dst_surface,
2059                             const VARectangle *dst_rect,
2060                             void *filter_param)
2061 {
2062     return pp_nv12_avs_initialize(ctx, pp_context,
2063                                   src_surface,
2064                                   src_rect,
2065                                   dst_surface,
2066                                   dst_rect,
2067                                   filter_param,
2068                                   1);
2069 }
2070
2071 static VAStatus
2072 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2073                              const struct i965_surface *src_surface,
2074                              const VARectangle *src_rect,
2075                              struct i965_surface *dst_surface,
2076                              const VARectangle *dst_rect,
2077                              void *filter_param)
2078 {
2079     return pp_nv12_avs_initialize(ctx, pp_context,
2080                                   src_surface,
2081                                   src_rect,
2082                                   dst_surface,
2083                                   dst_rect,
2084                                   filter_param,
2085                                   0);
2086 }
2087
2088 static int
2089 gen7_pp_avs_x_steps(void *private_context)
2090 {
2091     struct pp_avs_context *pp_avs_context = private_context;
2092
2093     return pp_avs_context->dest_w / 16;
2094 }
2095
2096 static int
2097 gen7_pp_avs_y_steps(void *private_context)
2098 {
2099     struct pp_avs_context *pp_avs_context = private_context;
2100
2101     return pp_avs_context->dest_h / 16;
2102 }
2103
2104 static int
2105 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2106 {
2107     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2108     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2109
2110     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2111     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2112     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2113     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2114
2115     return 0;
2116 }
2117
2118 static VAStatus
2119 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2120                            const struct i965_surface *src_surface,
2121                            const VARectangle *src_rect,
2122                            struct i965_surface *dst_surface,
2123                            const VARectangle *dst_rect,
2124                            void *filter_param)
2125 {
2126     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2127     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2128     struct gen7_sampler_8x8 *sampler_8x8;
2129     struct i965_sampler_8x8_state *sampler_8x8_state;
2130     int index, i;
2131     int width[3], height[3], pitch[3], offset[3];
2132
2133     /* source surface */
2134     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2135                                          width, height, pitch, offset);
2136
2137     /* destination surface */
2138     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2139                                          width, height, pitch, offset);
2140
2141     /* sampler 8x8 state */
2142     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2143     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2144     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2145     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2146     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2147
2148     for (i = 0; i < 17; i++) {
2149         /* for Y channel, currently ignore */
2150         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2151         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2152         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2153         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2154         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2155         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2156         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2157         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2158         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2159         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2160         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2161         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2162         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2163         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2164         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2165         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2166         /* for U/V channel, 0.25 */
2167         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2168         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2169         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2170         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2171         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2172         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2173         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2174         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2175         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2176         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2177         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2178         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2179         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2180         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2181         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2182         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2183     }
2184
2185     sampler_8x8_state->dw136.default_sharpness_level = 0;
2186     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2187     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2188     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2189     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2190
2191     /* sampler 8x8 */
2192     dri_bo_map(pp_context->sampler_state_table.bo, True);
2193     assert(pp_context->sampler_state_table.bo->virtual);
2194     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2195     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2196
2197     /* sample_8x8 Y index 4 */
2198     index = 4;
2199     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2200     sampler_8x8[index].dw0.global_noise_estimation = 255;
2201     sampler_8x8[index].dw0.ief_bypass = 1;
2202
2203     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2204
2205     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2206     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2207     sampler_8x8[index].dw2.r5x_coefficient = 9;
2208     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2209     sampler_8x8[index].dw2.r5c_coefficient = 3;
2210
2211     sampler_8x8[index].dw3.r3x_coefficient = 27;
2212     sampler_8x8[index].dw3.r3c_coefficient = 5;
2213     sampler_8x8[index].dw3.gain_factor = 40;
2214     sampler_8x8[index].dw3.non_edge_weight = 1;
2215     sampler_8x8[index].dw3.regular_weight = 2;
2216     sampler_8x8[index].dw3.strong_edge_weight = 7;
2217     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2218
2219     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2220                       I915_GEM_DOMAIN_RENDER,
2221                       0,
2222                       0,
2223                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2224                       pp_context->sampler_state_table.bo_8x8);
2225
2226     /* sample_8x8 UV index 8 */
2227     index = 8;
2228     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2229     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2230     sampler_8x8[index].dw0.global_noise_estimation = 255;
2231     sampler_8x8[index].dw0.ief_bypass = 1;
2232     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2233     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2234     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2235     sampler_8x8[index].dw2.r5x_coefficient = 9;
2236     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2237     sampler_8x8[index].dw2.r5c_coefficient = 3;
2238     sampler_8x8[index].dw3.r3x_coefficient = 27;
2239     sampler_8x8[index].dw3.r3c_coefficient = 5;
2240     sampler_8x8[index].dw3.gain_factor = 40;
2241     sampler_8x8[index].dw3.non_edge_weight = 1;
2242     sampler_8x8[index].dw3.regular_weight = 2;
2243     sampler_8x8[index].dw3.strong_edge_weight = 7;
2244     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2245
2246     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2247                       I915_GEM_DOMAIN_RENDER,
2248                       0,
2249                       0,
2250                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2251                       pp_context->sampler_state_table.bo_8x8);
2252
2253     /* sampler_8x8 V, index 12 */
2254     index = 12;
2255     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2256     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2257     sampler_8x8[index].dw0.global_noise_estimation = 255;
2258     sampler_8x8[index].dw0.ief_bypass = 1;
2259     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2260     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2261     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2262     sampler_8x8[index].dw2.r5x_coefficient = 9;
2263     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2264     sampler_8x8[index].dw2.r5c_coefficient = 3;
2265     sampler_8x8[index].dw3.r3x_coefficient = 27;
2266     sampler_8x8[index].dw3.r3c_coefficient = 5;
2267     sampler_8x8[index].dw3.gain_factor = 40;
2268     sampler_8x8[index].dw3.non_edge_weight = 1;
2269     sampler_8x8[index].dw3.regular_weight = 2;
2270     sampler_8x8[index].dw3.strong_edge_weight = 7;
2271     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2272
2273     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2274                       I915_GEM_DOMAIN_RENDER,
2275                       0,
2276                       0,
2277                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2278                       pp_context->sampler_state_table.bo_8x8);
2279
2280     dri_bo_unmap(pp_context->sampler_state_table.bo);
2281
2282     /* private function & data */
2283     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2284     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2285     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2286
2287     pp_avs_context->dest_x = dst_rect->x;
2288     pp_avs_context->dest_y = dst_rect->y;
2289     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2290     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2291     pp_avs_context->src_w = src_rect->width;
2292     pp_avs_context->src_h = src_rect->height;
2293
2294     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2295     dw = MAX(dw, pp_avs_context->dest_w);
2296
2297     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2298     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2299     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2300     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2301     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2302
2303     dst_surface->flags = src_surface->flags;
2304
2305     return VA_STATUS_SUCCESS;
2306 }
2307
2308 static int
2309 pp_dndi_x_steps(void *private_context)
2310 {
2311     return 1;
2312 }
2313
2314 static int
2315 pp_dndi_y_steps(void *private_context)
2316 {
2317     struct pp_dndi_context *pp_dndi_context = private_context;
2318
2319     return pp_dndi_context->dest_h / 4;
2320 }
2321
2322 static int
2323 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2324 {
2325     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2326
2327     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2328     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2329
2330     return 0;
2331 }
2332
2333 static VAStatus
2334 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2335                         const struct i965_surface *src_surface,
2336                         const VARectangle *src_rect,
2337                         struct i965_surface *dst_surface,
2338                         const VARectangle *dst_rect,
2339                         void *filter_param)
2340 {
2341     struct i965_driver_data *i965 = i965_driver_data(ctx);
2342     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2343     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2344     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2345     struct object_surface *obj_surface;
2346     struct i965_sampler_dndi *sampler_dndi;
2347     int index;
2348     int w, h;
2349     int orig_w, orig_h;
2350     int dndi_top_first = 1;
2351
2352     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2353         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2354
2355     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2356         dndi_top_first = 1;
2357     else
2358         dndi_top_first = 0;
2359
2360     /* surface */
2361     obj_surface = SURFACE(src_surface->id);
2362     orig_w = obj_surface->orig_width;
2363     orig_h = obj_surface->orig_height;
2364     w = obj_surface->width;
2365     h = obj_surface->height;
2366
2367     if (pp_context->stmm.bo == NULL) {
2368         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2369                                            "STMM surface",
2370                                            w * h,
2371                                            4096);
2372         assert(pp_context->stmm.bo);
2373     }
2374
2375     /* source UV surface index 2 */
2376     i965_pp_set_surface_state(ctx, pp_context,
2377                               obj_surface->bo, w * h,
2378                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2379                               2, 0);
2380
2381     /* source YUV surface index 4 */
2382     i965_pp_set_surface2_state(ctx, pp_context,
2383                                obj_surface->bo, 0,
2384                                orig_w, orig_h, w,
2385                                0, h,
2386                                SURFACE_FORMAT_PLANAR_420_8, 1,
2387                                4);
2388
2389     /* source STMM surface index 20 */
2390     i965_pp_set_surface_state(ctx, pp_context,
2391                               pp_context->stmm.bo, 0,
2392                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2393                               20, 1);
2394
2395     /* destination surface */
2396     obj_surface = SURFACE(dst_surface->id);
2397     orig_w = obj_surface->orig_width;
2398     orig_h = obj_surface->orig_height;
2399     w = obj_surface->width;
2400     h = obj_surface->height;
2401
2402     /* destination Y surface index 7 */
2403     i965_pp_set_surface_state(ctx, pp_context,
2404                               obj_surface->bo, 0,
2405                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2406                               7, 1);
2407
2408     /* destination UV surface index 8 */
2409     i965_pp_set_surface_state(ctx, pp_context,
2410                               obj_surface->bo, w * h,
2411                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2412                               8, 1);
2413     /* sampler dndi */
2414     dri_bo_map(pp_context->sampler_state_table.bo, True);
2415     assert(pp_context->sampler_state_table.bo->virtual);
2416     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2417     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2418
2419     /* sample dndi index 1 */
2420     index = 0;
2421     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2422     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2423     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2424     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2425
2426     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2427     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2428     sampler_dndi[index].dw1.stmm_c2 = 1;
2429     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2430     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2431
2432     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2433     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2434     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2435     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2436
2437     sampler_dndi[index].dw3.maximum_stmm = 128;
2438     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2439     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2440     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2441     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2442
2443     sampler_dndi[index].dw4.sdi_delta = 8;
2444     sampler_dndi[index].dw4.sdi_threshold = 128;
2445     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2446     sampler_dndi[index].dw4.stmm_shift_up = 0;
2447     sampler_dndi[index].dw4.stmm_shift_down = 0;
2448     sampler_dndi[index].dw4.minimum_stmm = 0;
2449
2450     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2451     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2452     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2453     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2454
2455     sampler_dndi[index].dw6.dn_enable = 1;
2456     sampler_dndi[index].dw6.di_enable = 1;
2457     sampler_dndi[index].dw6.di_partial = 0;
2458     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2459     sampler_dndi[index].dw6.dndi_stream_id = 0;
2460     sampler_dndi[index].dw6.dndi_first_frame = 1;
2461     sampler_dndi[index].dw6.progressive_dn = 0;
2462     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2463     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2464     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2465
2466     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2467     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2468     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2469     sampler_dndi[index].dw7.column_width_minus1 = 0;
2470
2471     dri_bo_unmap(pp_context->sampler_state_table.bo);
2472
2473     /* private function & data */
2474     pp_context->pp_x_steps = pp_dndi_x_steps;
2475     pp_context->pp_y_steps = pp_dndi_y_steps;
2476     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2477
2478     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2479     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2480     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2481     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2482
2483     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2484     pp_inline_parameter->grf5.number_blocks = w / 16;
2485     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2486     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2487
2488     pp_dndi_context->dest_w = w;
2489     pp_dndi_context->dest_h = h;
2490
2491     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2492
2493     return VA_STATUS_SUCCESS;
2494 }
2495
2496 static int
2497 pp_dn_x_steps(void *private_context)
2498 {
2499     return 1;
2500 }
2501
2502 static int
2503 pp_dn_y_steps(void *private_context)
2504 {
2505     struct pp_dn_context *pp_dn_context = private_context;
2506
2507     return pp_dn_context->dest_h / 8;
2508 }
2509
2510 static int
2511 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2512 {
2513     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2514
2515     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2516     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2517
2518     return 0;
2519 }
2520
2521 static VAStatus
2522 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2523                       const struct i965_surface *src_surface,
2524                       const VARectangle *src_rect,
2525                       struct i965_surface *dst_surface,
2526                       const VARectangle *dst_rect,
2527                       void *filter_param)
2528 {
2529     struct i965_driver_data *i965 = i965_driver_data(ctx);
2530     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2531     struct object_surface *obj_surface;
2532     struct i965_sampler_dndi *sampler_dndi;
2533     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2534     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2535     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2536     int index;
2537     int w, h;
2538     int orig_w, orig_h;
2539     int dn_strength = 15;
2540     int dndi_top_first = 1;
2541     int dn_progressive = 0;
2542
2543     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2544         dndi_top_first = 1;
2545         dn_progressive = 1;
2546     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2547         dndi_top_first = 1;
2548         dn_progressive = 0;
2549     } else {
2550         dndi_top_first = 0;
2551         dn_progressive = 0;
2552     }
2553
2554     if (dn_filter_param) {
2555         float value = dn_filter_param->value;
2556
2557         if (value > 1.0)
2558             value = 1.0;
2559
2560         if (value < 0.0)
2561             value = 0.0;
2562
2563         dn_strength = (int)(value * 31.0F);
2564     }
2565
2566     /* surface */
2567     obj_surface = SURFACE(src_surface->id);
2568     orig_w = obj_surface->orig_width;
2569     orig_h = obj_surface->orig_height;
2570     w = obj_surface->width;
2571     h = obj_surface->height;
2572
2573     if (pp_context->stmm.bo == NULL) {
2574         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2575                                            "STMM surface",
2576                                            w * h,
2577                                            4096);
2578         assert(pp_context->stmm.bo);
2579     }
2580
2581     /* source UV surface index 2 */
2582     i965_pp_set_surface_state(ctx, pp_context,
2583                               obj_surface->bo, w * h,
2584                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2585                               2, 0);
2586
2587     /* source YUV surface index 4 */
2588     i965_pp_set_surface2_state(ctx, pp_context,
2589                                obj_surface->bo, 0,
2590                                orig_w, orig_h, w,
2591                                0, h,
2592                                SURFACE_FORMAT_PLANAR_420_8, 1,
2593                                4);
2594
2595     /* source STMM surface index 20 */
2596     i965_pp_set_surface_state(ctx, pp_context,
2597                               pp_context->stmm.bo, 0,
2598                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2599                               20, 1);
2600
2601     /* destination surface */
2602     obj_surface = SURFACE(dst_surface->id);
2603     orig_w = obj_surface->orig_width;
2604     orig_h = obj_surface->orig_height;
2605     w = obj_surface->width;
2606     h = obj_surface->height;
2607
2608     /* destination Y surface index 7 */
2609     i965_pp_set_surface_state(ctx, pp_context,
2610                               obj_surface->bo, 0,
2611                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2612                               7, 1);
2613
2614     /* destination UV surface index 8 */
2615     i965_pp_set_surface_state(ctx, pp_context,
2616                               obj_surface->bo, w * h,
2617                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2618                               8, 1);
2619     /* sampler dn */
2620     dri_bo_map(pp_context->sampler_state_table.bo, True);
2621     assert(pp_context->sampler_state_table.bo->virtual);
2622     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2623     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2624
2625     /* sample dndi index 1 */
2626     index = 0;
2627     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2628     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2629     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2630     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2631
2632     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2633     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2634     sampler_dndi[index].dw1.stmm_c2 = 0;
2635     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2636     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2637
2638     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2639     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2640     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2641     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2642
2643     sampler_dndi[index].dw3.maximum_stmm = 128;
2644     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2645     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2646     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2647     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2648
2649     sampler_dndi[index].dw4.sdi_delta = 8;
2650     sampler_dndi[index].dw4.sdi_threshold = 128;
2651     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2652     sampler_dndi[index].dw4.stmm_shift_up = 0;
2653     sampler_dndi[index].dw4.stmm_shift_down = 0;
2654     sampler_dndi[index].dw4.minimum_stmm = 0;
2655
2656     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2657     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2658     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2659     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2660
2661     sampler_dndi[index].dw6.dn_enable = 1;
2662     sampler_dndi[index].dw6.di_enable = 0;
2663     sampler_dndi[index].dw6.di_partial = 0;
2664     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2665     sampler_dndi[index].dw6.dndi_stream_id = 1;
2666     sampler_dndi[index].dw6.dndi_first_frame = 1;
2667     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2668     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2669     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2670     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2671
2672     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2673     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2674     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2675     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2676
2677     dri_bo_unmap(pp_context->sampler_state_table.bo);
2678
2679     /* private function & data */
2680     pp_context->pp_x_steps = pp_dn_x_steps;
2681     pp_context->pp_y_steps = pp_dn_y_steps;
2682     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2683
2684     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2685     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2686     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2687     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2688
2689     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2690     pp_inline_parameter->grf5.number_blocks = w / 16;
2691     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2692     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2693
2694     pp_dn_context->dest_w = w;
2695     pp_dn_context->dest_h = h;
2696
2697     dst_surface->flags = src_surface->flags;
2698
2699     return VA_STATUS_SUCCESS;
2700 }
2701
2702 static int
2703 gen7_pp_dndi_x_steps(void *private_context)
2704 {
2705     struct pp_dndi_context *pp_dndi_context = private_context;
2706
2707     return pp_dndi_context->dest_w / 16;
2708 }
2709
2710 static int
2711 gen7_pp_dndi_y_steps(void *private_context)
2712 {
2713     struct pp_dndi_context *pp_dndi_context = private_context;
2714
2715     return pp_dndi_context->dest_h / 4;
2716 }
2717
2718 static int
2719 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2720 {
2721     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2722
2723     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2724     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2725
2726     return 0;
2727 }
2728
2729 static VAStatus
2730 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2731                              const struct i965_surface *src_surface,
2732                              const VARectangle *src_rect,
2733                              struct i965_surface *dst_surface,
2734                              const VARectangle *dst_rect,
2735                              void *filter_param)
2736 {
2737     struct i965_driver_data *i965 = i965_driver_data(ctx);
2738     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2739     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2740     struct object_surface *obj_surface;
2741     struct gen7_sampler_dndi *sampler_dndi;
2742     int index;
2743     int w, h;
2744     int orig_w, orig_h;
2745     int dndi_top_first = 1;
2746
2747     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2748         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2749
2750     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2751         dndi_top_first = 1;
2752     else
2753         dndi_top_first = 0;
2754
2755     /* surface */
2756     obj_surface = SURFACE(src_surface->id);
2757     orig_w = obj_surface->orig_width;
2758     orig_h = obj_surface->orig_height;
2759     w = obj_surface->width;
2760     h = obj_surface->height;
2761
2762     if (pp_context->stmm.bo == NULL) {
2763         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2764                                            "STMM surface",
2765                                            w * h,
2766                                            4096);
2767         assert(pp_context->stmm.bo);
2768     }
2769
2770     /* source UV surface index 1 */
2771     gen7_pp_set_surface_state(ctx, pp_context,
2772                               obj_surface->bo, w * h,
2773                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2774                               1, 0);
2775
2776     /* source YUV surface index 3 */
2777     gen7_pp_set_surface2_state(ctx, pp_context,
2778                                obj_surface->bo, 0,
2779                                orig_w, orig_h, w,
2780                                0, h,
2781                                SURFACE_FORMAT_PLANAR_420_8, 1,
2782                                3);
2783
2784     /* source (temporal reference) YUV surface index 4 */
2785     gen7_pp_set_surface2_state(ctx, pp_context,
2786                                obj_surface->bo, 0,
2787                                orig_w, orig_h, w,
2788                                0, h,
2789                                SURFACE_FORMAT_PLANAR_420_8, 1,
2790                                4);
2791
2792     /* STMM / History Statistics input surface, index 5 */
2793     gen7_pp_set_surface_state(ctx, pp_context,
2794                               pp_context->stmm.bo, 0,
2795                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2796                               5, 1);
2797
2798     /* destination surface */
2799     obj_surface = SURFACE(dst_surface->id);
2800     orig_w = obj_surface->orig_width;
2801     orig_h = obj_surface->orig_height;
2802     w = obj_surface->width;
2803     h = obj_surface->height;
2804
2805     /* destination(Previous frame) Y surface index 27 */
2806     gen7_pp_set_surface_state(ctx, pp_context,
2807                               obj_surface->bo, 0,
2808                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2809                               27, 1);
2810
2811     /* destination(Previous frame) UV surface index 28 */
2812     gen7_pp_set_surface_state(ctx, pp_context,
2813                               obj_surface->bo, w * h,
2814                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2815                               28, 1);
2816
2817     /* destination(Current frame) Y surface index 30 */
2818     gen7_pp_set_surface_state(ctx, pp_context,
2819                               obj_surface->bo, 0,
2820                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2821                               30, 1);
2822
2823     /* destination(Current frame) UV surface index 31 */
2824     gen7_pp_set_surface_state(ctx, pp_context,
2825                               obj_surface->bo, w * h,
2826                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2827                               31, 1);
2828
2829     /* STMM output surface, index 33 */
2830     gen7_pp_set_surface_state(ctx, pp_context,
2831                               pp_context->stmm.bo, 0,
2832                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2833                               33, 1);
2834
2835
2836     /* sampler dndi */
2837     dri_bo_map(pp_context->sampler_state_table.bo, True);
2838     assert(pp_context->sampler_state_table.bo->virtual);
2839     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2840     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2841
2842     /* sample dndi index 0 */
2843     index = 0;
2844     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2845     sampler_dndi[index].dw0.dnmh_delt = 8;
2846     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2847     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2848     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2849     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2850
2851     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2852     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2853     sampler_dndi[index].dw1.stmm_c2 = 0;
2854     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2855     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2856
2857     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2858     sampler_dndi[index].dw2.bne_edge_th = 1;
2859     sampler_dndi[index].dw2.smooth_mv_th = 0;
2860     sampler_dndi[index].dw2.sad_tight_th = 5;
2861     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2862     sampler_dndi[index].dw2.good_neighbor_th = 4;
2863
2864     sampler_dndi[index].dw3.maximum_stmm = 128;
2865     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2866     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2867     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2868     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2869
2870     sampler_dndi[index].dw4.sdi_delta = 8;
2871     sampler_dndi[index].dw4.sdi_threshold = 128;
2872     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2873     sampler_dndi[index].dw4.stmm_shift_up = 0;
2874     sampler_dndi[index].dw4.stmm_shift_down = 0;
2875     sampler_dndi[index].dw4.minimum_stmm = 0;
2876
2877     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2878     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2879     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2880     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2881
2882     sampler_dndi[index].dw6.dn_enable = 0;
2883     sampler_dndi[index].dw6.di_enable = 1;
2884     sampler_dndi[index].dw6.di_partial = 0;
2885     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2886     sampler_dndi[index].dw6.dndi_stream_id = 1;
2887     sampler_dndi[index].dw6.dndi_first_frame = 1;
2888     sampler_dndi[index].dw6.progressive_dn = 0;
2889     sampler_dndi[index].dw6.mcdi_enable = 0;
2890     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2891     sampler_dndi[index].dw6.cat_th1 = 0;
2892     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2893     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2894
2895     sampler_dndi[index].dw7.sad_tha = 5;
2896     sampler_dndi[index].dw7.sad_thb = 10;
2897     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2898     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2899     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2900     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2901     sampler_dndi[index].dw7.neighborpixel_th = 10;
2902     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2903
2904     dri_bo_unmap(pp_context->sampler_state_table.bo);
2905
2906     /* private function & data */
2907     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2908     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2909     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2910
2911     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2912     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2913     pp_static_parameter->grf1.di_top_field_first = 0;
2914     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2915
2916     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2917     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2918     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2919
2920     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2921     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2922
2923     pp_dndi_context->dest_w = w;
2924     pp_dndi_context->dest_h = h;
2925
2926     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2927
2928     return VA_STATUS_SUCCESS;
2929 }
2930
2931 static int
2932 gen7_pp_dn_x_steps(void *private_context)
2933 {
2934     return 1;
2935 }
2936
2937 static int
2938 gen7_pp_dn_y_steps(void *private_context)
2939 {
2940     struct pp_dn_context *pp_dn_context = private_context;
2941
2942     return pp_dn_context->dest_h / 4;
2943 }
2944
2945 static int
2946 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2947 {
2948     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2949
2950     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2951     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2952
2953     return 0;
2954 }
2955
2956 static VAStatus
2957 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2958                            const struct i965_surface *src_surface,
2959                            const VARectangle *src_rect,
2960                            struct i965_surface *dst_surface,
2961                            const VARectangle *dst_rect,
2962                            void *filter_param)
2963 {
2964     struct i965_driver_data *i965 = i965_driver_data(ctx);
2965     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2966     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2967     struct object_surface *obj_surface;
2968     struct gen7_sampler_dndi *sampler_dn;
2969     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2970     int index;
2971     int w, h;
2972     int orig_w, orig_h;
2973     int dn_strength = 15;
2974     int dndi_top_first = 1;
2975     int dn_progressive = 0;
2976
2977     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2978         dndi_top_first = 1;
2979         dn_progressive = 1;
2980     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2981         dndi_top_first = 1;
2982         dn_progressive = 0;
2983     } else {
2984         dndi_top_first = 0;
2985         dn_progressive = 0;
2986     }
2987
2988     if (dn_filter_param) {
2989         float value = dn_filter_param->value;
2990
2991         if (value > 1.0)
2992             value = 1.0;
2993
2994         if (value < 0.0)
2995             value = 0.0;
2996
2997         dn_strength = (int)(value * 31.0F);
2998     }
2999
3000     /* surface */
3001     obj_surface = SURFACE(src_surface->id);
3002     orig_w = obj_surface->orig_width;
3003     orig_h = obj_surface->orig_height;
3004     w = obj_surface->width;
3005     h = obj_surface->height;
3006
3007     if (pp_context->stmm.bo == NULL) {
3008         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3009                                            "STMM surface",
3010                                            w * h,
3011                                            4096);
3012         assert(pp_context->stmm.bo);
3013     }
3014
3015     /* source UV surface index 1 */
3016     gen7_pp_set_surface_state(ctx, pp_context,
3017                               obj_surface->bo, w * h,
3018                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3019                               1, 0);
3020
3021     /* source YUV surface index 3 */
3022     gen7_pp_set_surface2_state(ctx, pp_context,
3023                                obj_surface->bo, 0,
3024                                orig_w, orig_h, w,
3025                                0, h,
3026                                SURFACE_FORMAT_PLANAR_420_8, 1,
3027                                3);
3028
3029     /* source STMM surface index 5 */
3030     gen7_pp_set_surface_state(ctx, pp_context,
3031                               pp_context->stmm.bo, 0,
3032                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3033                               5, 1);
3034
3035     /* destination surface */
3036     obj_surface = SURFACE(dst_surface->id);
3037     orig_w = obj_surface->orig_width;
3038     orig_h = obj_surface->orig_height;
3039     w = obj_surface->width;
3040     h = obj_surface->height;
3041
3042     /* destination Y surface index 7 */
3043     gen7_pp_set_surface_state(ctx, pp_context,
3044                               obj_surface->bo, 0,
3045                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3046                               7, 1);
3047
3048     /* destination UV surface index 8 */
3049     gen7_pp_set_surface_state(ctx, pp_context,
3050                               obj_surface->bo, w * h,
3051                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3052                               8, 1);
3053     /* sampler dn */
3054     dri_bo_map(pp_context->sampler_state_table.bo, True);
3055     assert(pp_context->sampler_state_table.bo->virtual);
3056     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3057     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3058
3059     /* sample dn index 1 */
3060     index = 0;
3061     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3062     sampler_dn[index].dw0.dnmh_delt = 8;
3063     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3064     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3065     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3066     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3067
3068     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3069     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3070     sampler_dn[index].dw1.stmm_c2 = 0;
3071     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3072     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3073
3074     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3075     sampler_dn[index].dw2.bne_edge_th = 1;
3076     sampler_dn[index].dw2.smooth_mv_th = 0;
3077     sampler_dn[index].dw2.sad_tight_th = 5;
3078     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3079     sampler_dn[index].dw2.good_neighbor_th = 4;
3080
3081     sampler_dn[index].dw3.maximum_stmm = 128;
3082     sampler_dn[index].dw3.multipler_for_vecm = 2;
3083     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3084     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3085     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3086
3087     sampler_dn[index].dw4.sdi_delta = 8;
3088     sampler_dn[index].dw4.sdi_threshold = 128;
3089     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3090     sampler_dn[index].dw4.stmm_shift_up = 0;
3091     sampler_dn[index].dw4.stmm_shift_down = 0;
3092     sampler_dn[index].dw4.minimum_stmm = 0;
3093
3094     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3095     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3096     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3097     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3098
3099     sampler_dn[index].dw6.dn_enable = 1;
3100     sampler_dn[index].dw6.di_enable = 0;
3101     sampler_dn[index].dw6.di_partial = 0;
3102     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3103     sampler_dn[index].dw6.dndi_stream_id = 1;
3104     sampler_dn[index].dw6.dndi_first_frame = 1;
3105     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3106     sampler_dn[index].dw6.mcdi_enable = 0;
3107     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3108     sampler_dn[index].dw6.cat_th1 = 0;
3109     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3110     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3111
3112     sampler_dn[index].dw7.sad_tha = 5;
3113     sampler_dn[index].dw7.sad_thb = 10;
3114     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3115     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3116     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3117     sampler_dn[index].dw7.vdi_walker_enable = 0;
3118     sampler_dn[index].dw7.neighborpixel_th = 10;
3119     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3120
3121     dri_bo_unmap(pp_context->sampler_state_table.bo);
3122
3123     /* private function & data */
3124     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3125     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3126     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3127
3128     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3129     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3130     pp_static_parameter->grf1.di_top_field_first = 0;
3131     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3132
3133     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3134     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3135     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3136
3137     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3138     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3139
3140     pp_dn_context->dest_w = w;
3141     pp_dn_context->dest_h = h;
3142
3143     dst_surface->flags = src_surface->flags;
3144
3145     return VA_STATUS_SUCCESS;
3146 }
3147
3148 // update u/v offset when the surface format are packed yuv
3149 static void i965_update_src_surface_uv_offset(
3150     VADriverContextP    ctx,
3151     struct i965_post_processing_context *pp_context,
3152     const struct i965_surface *surface)
3153 {
3154     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3155     int fourcc = pp_get_surface_fourcc(ctx, surface);
3156
3157     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3158         pp_static_parameter->grf1.source_packed_u_offset = 1;
3159         pp_static_parameter->grf1.source_packed_v_offset = 3;
3160     }
3161     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3162         pp_static_parameter->grf1.source_packed_y_offset = 1;
3163         pp_static_parameter->grf1.source_packed_v_offset = 2;
3164     }
3165
3166 }
3167
3168 static void i965_update_dst_surface_uv_offset(
3169     VADriverContextP    ctx,
3170     struct i965_post_processing_context *pp_context,
3171     const struct i965_surface *surface)
3172 {
3173     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3174     int fourcc = pp_get_surface_fourcc(ctx, surface);
3175
3176     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3177         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
3178         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
3179     }
3180     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3181         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
3182         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
3183     }
3184
3185 }
3186
3187 static VAStatus
3188 ironlake_pp_initialize(
3189     VADriverContextP   ctx,
3190     struct i965_post_processing_context *pp_context,
3191     const struct i965_surface *src_surface,
3192     const VARectangle *src_rect,
3193     struct i965_surface *dst_surface,
3194     const VARectangle *dst_rect,
3195     int                pp_index,
3196     void *filter_param
3197 )
3198 {
3199     VAStatus va_status;
3200     struct i965_driver_data *i965 = i965_driver_data(ctx);
3201     struct pp_module *pp_module;
3202     dri_bo *bo;
3203     int static_param_size, inline_param_size;
3204
3205     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3206     bo = dri_bo_alloc(i965->intel.bufmgr,
3207                       "surface state & binding table",
3208                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3209                       4096);
3210     assert(bo);
3211     pp_context->surface_state_binding_table.bo = bo;
3212
3213     dri_bo_unreference(pp_context->curbe.bo);
3214     bo = dri_bo_alloc(i965->intel.bufmgr,
3215                       "constant buffer",
3216                       4096,
3217                       4096);
3218     assert(bo);
3219     pp_context->curbe.bo = bo;
3220
3221     dri_bo_unreference(pp_context->idrt.bo);
3222     bo = dri_bo_alloc(i965->intel.bufmgr,
3223                       "interface discriptor",
3224                       sizeof(struct i965_interface_descriptor),
3225                       4096);
3226     assert(bo);
3227     pp_context->idrt.bo = bo;
3228     pp_context->idrt.num_interface_descriptors = 0;
3229
3230     dri_bo_unreference(pp_context->sampler_state_table.bo);
3231     bo = dri_bo_alloc(i965->intel.bufmgr,
3232                       "sampler state table",
3233                       4096,
3234                       4096);
3235     assert(bo);
3236     dri_bo_map(bo, True);
3237     memset(bo->virtual, 0, bo->size);
3238     dri_bo_unmap(bo);
3239     pp_context->sampler_state_table.bo = bo;
3240
3241     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3242     bo = dri_bo_alloc(i965->intel.bufmgr,
3243                       "sampler 8x8 state ",
3244                       4096,
3245                       4096);
3246     assert(bo);
3247     pp_context->sampler_state_table.bo_8x8 = bo;
3248
3249     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3250     bo = dri_bo_alloc(i965->intel.bufmgr,
3251                       "sampler 8x8 state ",
3252                       4096,
3253                       4096);
3254     assert(bo);
3255     pp_context->sampler_state_table.bo_8x8_uv = bo;
3256
3257     dri_bo_unreference(pp_context->vfe_state.bo);
3258     bo = dri_bo_alloc(i965->intel.bufmgr,
3259                       "vfe state",
3260                       sizeof(struct i965_vfe_state),
3261                       4096);
3262     assert(bo);
3263     pp_context->vfe_state.bo = bo;
3264
3265     static_param_size = sizeof(struct pp_static_parameter);
3266     inline_param_size = sizeof(struct pp_inline_parameter);
3267
3268     memset(pp_context->pp_static_parameter, 0, static_param_size);
3269     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3270
3271     // update u/v offset for packed yuv
3272     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3273     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3274
3275     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3276     pp_context->current_pp = pp_index;
3277     pp_module = &pp_context->pp_modules[pp_index];
3278
3279     if (pp_module->initialize)
3280         va_status = pp_module->initialize(ctx, pp_context,
3281                                           src_surface,
3282                                           src_rect,
3283                                           dst_surface,
3284                                           dst_rect,
3285                                           filter_param);
3286     else
3287         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3288
3289     return va_status;
3290 }
3291
3292 static VAStatus
3293 ironlake_post_processing(
3294     VADriverContextP   ctx,
3295     struct i965_post_processing_context *pp_context,
3296     const struct i965_surface *src_surface,
3297     const VARectangle *src_rect,
3298     struct i965_surface *dst_surface,
3299     const VARectangle *dst_rect,
3300     int                pp_index,
3301     void *filter_param
3302 )
3303 {
3304     VAStatus va_status;
3305
3306     va_status = ironlake_pp_initialize(ctx, pp_context,
3307                                        src_surface,
3308                                        src_rect,
3309                                        dst_surface,
3310                                        dst_rect,
3311                                        pp_index,
3312                                        filter_param);
3313
3314     if (va_status == VA_STATUS_SUCCESS) {
3315         ironlake_pp_states_setup(ctx, pp_context);
3316         ironlake_pp_pipeline_setup(ctx, pp_context);
3317     }
3318
3319     return va_status;
3320 }
3321
3322 static VAStatus
3323 gen6_pp_initialize(
3324     VADriverContextP   ctx,
3325     struct i965_post_processing_context *pp_context,
3326     const struct i965_surface *src_surface,
3327     const VARectangle *src_rect,
3328     struct i965_surface *dst_surface,
3329     const VARectangle *dst_rect,
3330     int                pp_index,
3331     void *filter_param
3332 )
3333 {
3334     VAStatus va_status;
3335     struct i965_driver_data *i965 = i965_driver_data(ctx);
3336     struct pp_module *pp_module;
3337     dri_bo *bo;
3338     int static_param_size, inline_param_size;
3339
3340     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3341     bo = dri_bo_alloc(i965->intel.bufmgr,
3342                       "surface state & binding table",
3343                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3344                       4096);
3345     assert(bo);
3346     pp_context->surface_state_binding_table.bo = bo;
3347
3348     dri_bo_unreference(pp_context->curbe.bo);
3349     bo = dri_bo_alloc(i965->intel.bufmgr,
3350                       "constant buffer",
3351                       4096,
3352                       4096);
3353     assert(bo);
3354     pp_context->curbe.bo = bo;
3355
3356     dri_bo_unreference(pp_context->idrt.bo);
3357     bo = dri_bo_alloc(i965->intel.bufmgr,
3358                       "interface discriptor",
3359                       sizeof(struct gen6_interface_descriptor_data),
3360                       4096);
3361     assert(bo);
3362     pp_context->idrt.bo = bo;
3363     pp_context->idrt.num_interface_descriptors = 0;
3364
3365     dri_bo_unreference(pp_context->sampler_state_table.bo);
3366     bo = dri_bo_alloc(i965->intel.bufmgr,
3367                       "sampler state table",
3368                       4096,
3369                       4096);
3370     assert(bo);
3371     dri_bo_map(bo, True);
3372     memset(bo->virtual, 0, bo->size);
3373     dri_bo_unmap(bo);
3374     pp_context->sampler_state_table.bo = bo;
3375
3376     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3377     bo = dri_bo_alloc(i965->intel.bufmgr,
3378                       "sampler 8x8 state ",
3379                       4096,
3380                       4096);
3381     assert(bo);
3382     pp_context->sampler_state_table.bo_8x8 = bo;
3383
3384     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3385     bo = dri_bo_alloc(i965->intel.bufmgr,
3386                       "sampler 8x8 state ",
3387                       4096,
3388                       4096);
3389     assert(bo);
3390     pp_context->sampler_state_table.bo_8x8_uv = bo;
3391
3392     dri_bo_unreference(pp_context->vfe_state.bo);
3393     bo = dri_bo_alloc(i965->intel.bufmgr,
3394                       "vfe state",
3395                       sizeof(struct i965_vfe_state),
3396                       4096);
3397     assert(bo);
3398     pp_context->vfe_state.bo = bo;
3399
3400     if (IS_GEN7(i965->intel.device_id)) {
3401         static_param_size = sizeof(struct gen7_pp_static_parameter);
3402         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3403     } else {
3404         static_param_size = sizeof(struct pp_static_parameter);
3405         inline_param_size = sizeof(struct pp_inline_parameter);
3406     }
3407
3408     memset(pp_context->pp_static_parameter, 0, static_param_size);
3409     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3410
3411     // update u/v offset for packed yuv
3412     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3413     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3414
3415     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3416     pp_context->current_pp = pp_index;
3417     pp_module = &pp_context->pp_modules[pp_index];
3418
3419     if (pp_module->initialize)
3420         va_status = pp_module->initialize(ctx, pp_context,
3421                                           src_surface,
3422                                           src_rect,
3423                                           dst_surface,
3424                                           dst_rect,
3425                                           filter_param);
3426     else
3427         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3428
3429     return va_status;
3430 }
3431
3432 static void
3433 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3434                                    struct i965_post_processing_context *pp_context)
3435 {
3436     struct i965_driver_data *i965 = i965_driver_data(ctx);
3437     struct gen6_interface_descriptor_data *desc;
3438     dri_bo *bo;
3439     int pp_index = pp_context->current_pp;
3440
3441     bo = pp_context->idrt.bo;
3442     dri_bo_map(bo, True);
3443     assert(bo->virtual);
3444     desc = bo->virtual;
3445     memset(desc, 0, sizeof(*desc));
3446     desc->desc0.kernel_start_pointer =
3447         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3448     desc->desc1.single_program_flow = 1;
3449     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3450     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3451     desc->desc2.sampler_state_pointer =
3452         pp_context->sampler_state_table.bo->offset >> 5;
3453     desc->desc3.binding_table_entry_count = 0;
3454     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3455     desc->desc4.constant_urb_entry_read_offset = 0;
3456
3457     if (IS_GEN7(i965->intel.device_id))
3458         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3459     else
3460         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3461
3462     dri_bo_emit_reloc(bo,
3463                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3464                       0,
3465                       offsetof(struct gen6_interface_descriptor_data, desc0),
3466                       pp_context->pp_modules[pp_index].kernel.bo);
3467
3468     dri_bo_emit_reloc(bo,
3469                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3470                       desc->desc2.sampler_count << 2,
3471                       offsetof(struct gen6_interface_descriptor_data, desc2),
3472                       pp_context->sampler_state_table.bo);
3473
3474     dri_bo_unmap(bo);
3475     pp_context->idrt.num_interface_descriptors++;
3476 }
3477
3478 static void
3479 gen6_pp_upload_constants(VADriverContextP ctx,
3480                          struct i965_post_processing_context *pp_context)
3481 {
3482     struct i965_driver_data *i965 = i965_driver_data(ctx);
3483     unsigned char *constant_buffer;
3484     int param_size;
3485
3486     assert(sizeof(struct pp_static_parameter) == 128);
3487     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3488
3489     if (IS_GEN7(i965->intel.device_id))
3490         param_size = sizeof(struct gen7_pp_static_parameter);
3491     else
3492         param_size = sizeof(struct pp_static_parameter);
3493
3494     dri_bo_map(pp_context->curbe.bo, 1);
3495     assert(pp_context->curbe.bo->virtual);
3496     constant_buffer = pp_context->curbe.bo->virtual;
3497     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3498     dri_bo_unmap(pp_context->curbe.bo);
3499 }
3500
3501 static void
3502 gen6_pp_states_setup(VADriverContextP ctx,
3503                      struct i965_post_processing_context *pp_context)
3504 {
3505     gen6_pp_interface_descriptor_table(ctx, pp_context);
3506     gen6_pp_upload_constants(ctx, pp_context);
3507 }
3508
3509 static void
3510 gen6_pp_pipeline_select(VADriverContextP ctx,
3511                         struct i965_post_processing_context *pp_context)
3512 {
3513     struct intel_batchbuffer *batch = pp_context->batch;
3514
3515     BEGIN_BATCH(batch, 1);
3516     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3517     ADVANCE_BATCH(batch);
3518 }
3519
3520 static void
3521 gen6_pp_state_base_address(VADriverContextP ctx,
3522                            struct i965_post_processing_context *pp_context)
3523 {
3524     struct intel_batchbuffer *batch = pp_context->batch;
3525
3526     BEGIN_BATCH(batch, 10);
3527     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3528     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3529     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3530     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3531     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3532     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3533     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3534     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3535     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3536     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3537     ADVANCE_BATCH(batch);
3538 }
3539
3540 static void
3541 gen6_pp_vfe_state(VADriverContextP ctx,
3542                   struct i965_post_processing_context *pp_context)
3543 {
3544     struct intel_batchbuffer *batch = pp_context->batch;
3545
3546     BEGIN_BATCH(batch, 8);
3547     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3548     OUT_BATCH(batch, 0);
3549     OUT_BATCH(batch,
3550               (pp_context->urb.num_vfe_entries - 1) << 16 |
3551               pp_context->urb.num_vfe_entries << 8);
3552     OUT_BATCH(batch, 0);
3553     OUT_BATCH(batch,
3554               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3555               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3556     OUT_BATCH(batch, 0);
3557     OUT_BATCH(batch, 0);
3558     OUT_BATCH(batch, 0);
3559     ADVANCE_BATCH(batch);
3560 }
3561
3562 static void
3563 gen6_pp_curbe_load(VADriverContextP ctx,
3564                    struct i965_post_processing_context *pp_context)
3565 {
3566     struct intel_batchbuffer *batch = pp_context->batch;
3567
3568     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3569
3570     BEGIN_BATCH(batch, 4);
3571     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3572     OUT_BATCH(batch, 0);
3573     OUT_BATCH(batch,
3574               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3575     OUT_RELOC(batch,
3576               pp_context->curbe.bo,
3577               I915_GEM_DOMAIN_INSTRUCTION, 0,
3578               0);
3579     ADVANCE_BATCH(batch);
3580 }
3581
3582 static void
3583 gen6_interface_descriptor_load(VADriverContextP ctx,
3584                                struct i965_post_processing_context *pp_context)
3585 {
3586     struct intel_batchbuffer *batch = pp_context->batch;
3587
3588     BEGIN_BATCH(batch, 4);
3589     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3590     OUT_BATCH(batch, 0);
3591     OUT_BATCH(batch,
3592               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3593     OUT_RELOC(batch,
3594               pp_context->idrt.bo,
3595               I915_GEM_DOMAIN_INSTRUCTION, 0,
3596               0);
3597     ADVANCE_BATCH(batch);
3598 }
3599
3600 static void
3601 gen6_pp_object_walker(VADriverContextP ctx,
3602                       struct i965_post_processing_context *pp_context)
3603 {
3604     struct i965_driver_data *i965 = i965_driver_data(ctx);
3605     struct intel_batchbuffer *batch = pp_context->batch;
3606     int x, x_steps, y, y_steps;
3607     int param_size, command_length_in_dws;
3608     dri_bo *command_buffer;
3609     unsigned int *command_ptr;
3610
3611     if (IS_GEN7(i965->intel.device_id))
3612         param_size = sizeof(struct gen7_pp_inline_parameter);
3613     else
3614         param_size = sizeof(struct pp_inline_parameter);
3615
3616     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3617     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3618     command_length_in_dws = 6 + (param_size >> 2);
3619     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3620                                   "command objects buffer",
3621                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3622                                   4096);
3623
3624     dri_bo_map(command_buffer, 1);
3625     command_ptr = command_buffer->virtual;
3626
3627     for (y = 0; y < y_steps; y++) {
3628         for (x = 0; x < x_steps; x++) {
3629             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3630                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3631                 *command_ptr++ = 0;
3632                 *command_ptr++ = 0;
3633                 *command_ptr++ = 0;
3634                 *command_ptr++ = 0;
3635                 *command_ptr++ = 0;
3636                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3637                 command_ptr += (param_size >> 2);
3638             }
3639         }
3640     }
3641
3642     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3643         *command_ptr++ = 0;
3644
3645     *command_ptr = MI_BATCH_BUFFER_END;
3646
3647     dri_bo_unmap(command_buffer);
3648
3649     BEGIN_BATCH(batch, 2);
3650     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3651     OUT_RELOC(batch, command_buffer,
3652               I915_GEM_DOMAIN_COMMAND, 0,
3653               0);
3654     ADVANCE_BATCH(batch);
3655
3656     dri_bo_unreference(command_buffer);
3657
3658     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3659      * will cause control to pass back to ring buffer
3660      */
3661     intel_batchbuffer_end_atomic(batch);
3662     intel_batchbuffer_flush(batch);
3663     intel_batchbuffer_start_atomic(batch, 0x1000);
3664 }
3665
3666 static void
3667 gen6_pp_pipeline_setup(VADriverContextP ctx,
3668                        struct i965_post_processing_context *pp_context)
3669 {
3670     struct intel_batchbuffer *batch = pp_context->batch;
3671
3672     intel_batchbuffer_start_atomic(batch, 0x1000);
3673     intel_batchbuffer_emit_mi_flush(batch);
3674     gen6_pp_pipeline_select(ctx, pp_context);
3675     gen6_pp_state_base_address(ctx, pp_context);
3676     gen6_pp_vfe_state(ctx, pp_context);
3677     gen6_pp_curbe_load(ctx, pp_context);
3678     gen6_interface_descriptor_load(ctx, pp_context);
3679     gen6_pp_object_walker(ctx, pp_context);
3680     intel_batchbuffer_end_atomic(batch);
3681 }
3682
3683 static VAStatus
3684 gen6_post_processing(
3685     VADriverContextP   ctx,
3686     struct i965_post_processing_context *pp_context,
3687     const struct i965_surface *src_surface,
3688     const VARectangle *src_rect,
3689     struct i965_surface *dst_surface,
3690     const VARectangle *dst_rect,
3691     int                pp_index,
3692     void * filter_param
3693 )
3694 {
3695     VAStatus va_status;
3696
3697     va_status = gen6_pp_initialize(ctx, pp_context,
3698                                    src_surface,
3699                                    src_rect,
3700                                    dst_surface,
3701                                    dst_rect,
3702                                    pp_index,
3703                                    filter_param);
3704
3705     if (va_status == VA_STATUS_SUCCESS) {
3706         gen6_pp_states_setup(ctx, pp_context);
3707         gen6_pp_pipeline_setup(ctx, pp_context);
3708     }
3709
3710     return va_status;
3711 }
3712
3713 static VAStatus
3714 i965_post_processing_internal(
3715     VADriverContextP   ctx,
3716     struct i965_post_processing_context *pp_context,
3717     const struct i965_surface *src_surface,
3718     const VARectangle *src_rect,
3719     struct i965_surface *dst_surface,
3720     const VARectangle *dst_rect,
3721     int                pp_index,
3722     void *filter_param
3723 )
3724 {
3725     struct i965_driver_data *i965 = i965_driver_data(ctx);
3726     VAStatus va_status;
3727
3728     if (IS_GEN6(i965->intel.device_id) ||
3729         IS_GEN7(i965->intel.device_id))
3730         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3731     else
3732         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3733
3734     return va_status;
3735 }
3736
3737 VAStatus
3738 i965_DestroySurfaces(VADriverContextP ctx,
3739                      VASurfaceID *surface_list,
3740                      int num_surfaces);
3741 VAStatus
3742 i965_CreateSurfaces(VADriverContextP ctx,
3743                     int width,
3744                     int height,
3745                     int format,
3746                     int num_surfaces,
3747                     VASurfaceID *surfaces);
3748
3749 static void
3750 rgb_to_yuv(unsigned int argb,
3751            unsigned char *y,
3752            unsigned char *u,
3753            unsigned char *v,
3754            unsigned char *a)
3755 {
3756     int r = ((argb >> 16) & 0xff);
3757     int g = ((argb >> 8) & 0xff);
3758     int b = ((argb >> 0) & 0xff);
3759
3760     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3761     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3762     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3763     *a = ((argb >> 24) & 0xff);
3764 }
3765
3766 static void
3767 i965_vpp_clear_surface(VADriverContextP ctx,
3768                        struct i965_post_processing_context *pp_context,
3769                        VASurfaceID surface,
3770                        unsigned int color)
3771 {
3772     struct i965_driver_data *i965 = i965_driver_data(ctx);
3773     struct intel_batchbuffer *batch = pp_context->batch;
3774     struct object_surface *obj_surface = SURFACE(surface);
3775     unsigned int blt_cmd, br13;
3776     unsigned int tiling = 0, swizzle = 0;
3777     int pitch;
3778     unsigned char y, u, v, a = 0;
3779
3780     /* Currently only support NV12 surface */
3781     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3782         return;
3783
3784     rgb_to_yuv(color, &y, &u, &v, &a);
3785
3786     if (a == 0)
3787         return;
3788
3789     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3790     blt_cmd = XY_COLOR_BLT_CMD;
3791     pitch = obj_surface->width;
3792
3793     if (tiling != I915_TILING_NONE) {
3794         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3795         pitch >>= 2;
3796     }
3797
3798     br13 = 0xf0 << 16;
3799     br13 |= BR13_8;
3800     br13 |= pitch;
3801
3802     if (IS_GEN6(i965->intel.device_id) ||
3803         IS_GEN7(i965->intel.device_id)) {
3804         intel_batchbuffer_start_atomic_blt(batch, 48);
3805         BEGIN_BLT_BATCH(batch, 12);
3806     } else {
3807         intel_batchbuffer_start_atomic(batch, 48);
3808         BEGIN_BATCH(batch, 12);
3809     }
3810
3811     OUT_BATCH(batch, blt_cmd);
3812     OUT_BATCH(batch, br13);
3813     OUT_BATCH(batch,
3814               0 << 16 |
3815               0);
3816     OUT_BATCH(batch,
3817               obj_surface->height << 16 |
3818               obj_surface->width);
3819     OUT_RELOC(batch, obj_surface->bo,
3820               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3821               0);
3822     OUT_BATCH(batch, y);
3823
3824     br13 = 0xf0 << 16;
3825     br13 |= BR13_565;
3826     br13 |= pitch;
3827
3828     OUT_BATCH(batch, blt_cmd);
3829     OUT_BATCH(batch, br13);
3830     OUT_BATCH(batch,
3831               0 << 16 |
3832               0);
3833     OUT_BATCH(batch,
3834               obj_surface->height / 2 << 16 |
3835               obj_surface->width / 2);
3836     OUT_RELOC(batch, obj_surface->bo,
3837               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3838               obj_surface->width * obj_surface->y_cb_offset);
3839     OUT_BATCH(batch, v << 8 | u);
3840
3841     ADVANCE_BATCH(batch);
3842     intel_batchbuffer_end_atomic(batch);
3843 }
3844
3845 VASurfaceID
3846 i965_post_processing(
3847     VADriverContextP   ctx,
3848     VASurfaceID        surface,
3849     const VARectangle *src_rect,
3850     const VARectangle *dst_rect,
3851     unsigned int       flags,
3852     int               *has_done_scaling
3853 )
3854 {
3855     struct i965_driver_data *i965 = i965_driver_data(ctx);
3856     VASurfaceID in_surface_id = surface;
3857     VASurfaceID out_surface_id = VA_INVALID_ID;
3858
3859     *has_done_scaling = 0;
3860
3861     if (HAS_PP(i965)) {
3862         struct object_surface *obj_surface;
3863         VAStatus status;
3864         struct i965_surface src_surface;
3865         struct i965_surface dst_surface;
3866
3867         obj_surface = SURFACE(in_surface_id);
3868
3869         /* Currently only support post processing for NV12 surface */
3870         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3871             return out_surface_id;
3872
3873         _i965LockMutex(&i965->pp_mutex);
3874
3875         if (flags & I965_PP_FLAG_MCDI) {
3876             status = i965_CreateSurfaces(ctx,
3877                                          obj_surface->orig_width,
3878                                          obj_surface->orig_height,
3879                                          VA_RT_FORMAT_YUV420,
3880                                          1,
3881                                          &out_surface_id);
3882             assert(status == VA_STATUS_SUCCESS);
3883             obj_surface = SURFACE(out_surface_id);
3884             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3885             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3886             src_surface.id = in_surface_id;
3887             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3888             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3889                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3890             dst_surface.id = out_surface_id;
3891             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3892             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3893
3894             i965_post_processing_internal(ctx, i965->pp_context,
3895                                           &src_surface,
3896                                           src_rect,
3897                                           &dst_surface,
3898                                           dst_rect,
3899                                           PP_NV12_DNDI,
3900                                           NULL);
3901         }
3902
3903         if (flags & I965_PP_FLAG_AVS) {
3904             struct i965_render_state *render_state = &i965->render_state;
3905             struct intel_region *dest_region = render_state->draw_region;
3906
3907             if (out_surface_id != VA_INVALID_ID)
3908                 in_surface_id = out_surface_id;
3909
3910             status = i965_CreateSurfaces(ctx,
3911                                          dest_region->width,
3912                                          dest_region->height,
3913                                          VA_RT_FORMAT_YUV420,
3914                                          1,
3915                                          &out_surface_id);
3916             assert(status == VA_STATUS_SUCCESS);
3917             obj_surface = SURFACE(out_surface_id);
3918             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3919             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3920             src_surface.id = in_surface_id;
3921             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3922             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3923             dst_surface.id = out_surface_id;
3924             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3925             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3926
3927             i965_post_processing_internal(ctx, i965->pp_context,
3928                                           &src_surface,
3929                                           src_rect,
3930                                           &dst_surface,
3931                                           dst_rect,
3932                                           PP_NV12_AVS,
3933                                           NULL);
3934
3935             if (in_surface_id != surface)
3936                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3937
3938             *has_done_scaling = 1;
3939         }
3940
3941         _i965UnlockMutex(&i965->pp_mutex);
3942     }
3943
3944     return out_surface_id;
3945 }
3946
3947 static VAStatus
3948 i965_image_pl3_processing(VADriverContextP ctx,
3949                           const struct i965_surface *src_surface,
3950                           const VARectangle *src_rect,
3951                           struct i965_surface *dst_surface,
3952                           const VARectangle *dst_rect)
3953 {
3954     struct i965_driver_data *i965 = i965_driver_data(ctx);
3955     struct i965_post_processing_context *pp_context = i965->pp_context;
3956     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3957     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
3958
3959     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3960         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3961                                                  src_surface,
3962                                                  src_rect,
3963                                                  dst_surface,
3964                                                  dst_rect,
3965                                                  PP_PL3_LOAD_SAVE_N12,
3966                                                  NULL);
3967     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
3968                fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
3969         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3970                                                  src_surface,
3971                                                  src_rect,
3972                                                  dst_surface,
3973                                                  dst_rect,
3974                                                  PP_PL3_LOAD_SAVE_PL3,
3975                                                  NULL);
3976     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3977         if (IS_GEN6(i965->intel.device_id))
3978             vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
3979                                                      src_surface,
3980                                                      src_rect,
3981                                                      dst_surface,
3982                                                      dst_rect,
3983                                                      PP_PL3_LOAD_SAVE_PA,
3984                                                      NULL);
3985     }
3986     else {
3987         assert(0);
3988     }
3989
3990     intel_batchbuffer_flush(pp_context->batch);
3991
3992     return vaStatus;
3993 }
3994
3995 static VAStatus
3996 i965_image_pl2_processing(VADriverContextP ctx,
3997                           const struct i965_surface *src_surface,
3998                           const VARectangle *src_rect,
3999                           struct i965_surface *dst_surface,
4000                           const VARectangle *dst_rect)
4001 {
4002     struct i965_driver_data *i965 = i965_driver_data(ctx);
4003     struct i965_post_processing_context *pp_context = i965->pp_context;
4004     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4005     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4006
4007     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4008         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4009                                                  src_surface,
4010                                                  src_rect,
4011                                                  dst_surface,
4012                                                  dst_rect,
4013                                                  PP_NV12_LOAD_SAVE_N12,
4014                                                  NULL);
4015     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4016                fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
4017         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4018                                                  src_surface,
4019                                                  src_rect,
4020                                                  dst_surface,
4021                                                  dst_rect,
4022                                                  PP_NV12_LOAD_SAVE_PL3,
4023                                                  NULL);
4024     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
4025         if (IS_GEN6(i965->intel.device_id))
4026             vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4027                                                      src_surface,
4028                                                      src_rect,
4029                                                      dst_surface,
4030                                                      dst_rect,
4031                                                      PP_NV12_LOAD_SAVE_PA,
4032                                                      NULL);
4033     }
4034
4035     intel_batchbuffer_flush(pp_context->batch);
4036
4037     return vaStatus;
4038 }
4039
4040 static VAStatus
4041 i965_image_pl1_processing(VADriverContextP ctx,
4042                           const struct i965_surface *src_surface,
4043                           const VARectangle *src_rect,
4044                           struct i965_surface *dst_surface,
4045                           const VARectangle *dst_rect)
4046 {
4047     struct i965_driver_data *i965 = i965_driver_data(ctx);
4048     struct i965_post_processing_context *pp_context = i965->pp_context;
4049     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4050
4051     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4052         i965_post_processing_internal(ctx, i965->pp_context,
4053                                       src_surface,
4054                                       src_rect,
4055                                       dst_surface,
4056                                       dst_rect,
4057                                       PP_PA_LOAD_SAVE_NV12,
4058                                       NULL);
4059     }
4060     else if (fourcc == VA_FOURCC_YV12) {
4061         i965_post_processing_internal(ctx, i965->pp_context,
4062                                       src_surface,
4063                                       src_rect,
4064                                       dst_surface,
4065                                       dst_rect,
4066                                       PP_PA_LOAD_SAVE_PL3,
4067                                       NULL);
4068
4069     }
4070     else {
4071         return VA_STATUS_ERROR_UNKNOWN;
4072     }
4073
4074     intel_batchbuffer_flush(pp_context->batch);
4075
4076     return VA_STATUS_SUCCESS;
4077 }
4078
4079 VAStatus
4080 i965_image_processing(VADriverContextP ctx,
4081                       const struct i965_surface *src_surface,
4082                       const VARectangle *src_rect,
4083                       struct i965_surface *dst_surface,
4084                       const VARectangle *dst_rect)
4085 {
4086     struct i965_driver_data *i965 = i965_driver_data(ctx);
4087     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4088
4089     if (HAS_PP(i965)) {
4090         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4091
4092         _i965LockMutex(&i965->pp_mutex);
4093
4094         switch (fourcc) {
4095         case VA_FOURCC('Y', 'V', '1', '2'):
4096         case VA_FOURCC('I', '4', '2', '0'):
4097         case VA_FOURCC('I', 'M', 'C', '1'):
4098         case VA_FOURCC('I', 'M', 'C', '3'):
4099             status = i965_image_pl3_processing(ctx,
4100                                                src_surface,
4101                                                src_rect,
4102                                                dst_surface,
4103                                                dst_rect);
4104             break;
4105
4106         case  VA_FOURCC('N', 'V', '1', '2'):
4107             status = i965_image_pl2_processing(ctx,
4108                                                src_surface,
4109                                                src_rect,
4110                                                dst_surface,
4111                                                dst_rect);
4112             break;
4113         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4114             if (IS_GEN6(i965->intel.device_id))
4115                 status = i965_image_pl1_processing(ctx,
4116                                                    src_surface,
4117                                                    src_rect,
4118                                                    dst_surface,
4119                                                    dst_rect);
4120             break;
4121
4122         default:
4123             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4124             break;
4125         }
4126
4127         _i965UnlockMutex(&i965->pp_mutex);
4128     }
4129
4130     return status;
4131 }
4132
4133 static void
4134 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4135 {
4136     int i;
4137
4138     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4139     pp_context->surface_state_binding_table.bo = NULL;
4140
4141     dri_bo_unreference(pp_context->curbe.bo);
4142     pp_context->curbe.bo = NULL;
4143
4144     dri_bo_unreference(pp_context->sampler_state_table.bo);
4145     pp_context->sampler_state_table.bo = NULL;
4146
4147     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4148     pp_context->sampler_state_table.bo_8x8 = NULL;
4149
4150     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4151     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4152
4153     dri_bo_unreference(pp_context->idrt.bo);
4154     pp_context->idrt.bo = NULL;
4155     pp_context->idrt.num_interface_descriptors = 0;
4156
4157     dri_bo_unreference(pp_context->vfe_state.bo);
4158     pp_context->vfe_state.bo = NULL;
4159
4160     dri_bo_unreference(pp_context->stmm.bo);
4161     pp_context->stmm.bo = NULL;
4162
4163     for (i = 0; i < NUM_PP_MODULES; i++) {
4164         struct pp_module *pp_module = &pp_context->pp_modules[i];
4165
4166         dri_bo_unreference(pp_module->kernel.bo);
4167         pp_module->kernel.bo = NULL;
4168     }
4169
4170     free(pp_context->pp_static_parameter);
4171     free(pp_context->pp_inline_parameter);
4172     pp_context->pp_static_parameter = NULL;
4173     pp_context->pp_inline_parameter = NULL;
4174 }
4175
4176 Bool
4177 i965_post_processing_terminate(VADriverContextP ctx)
4178 {
4179     struct i965_driver_data *i965 = i965_driver_data(ctx);
4180     struct i965_post_processing_context *pp_context = i965->pp_context;
4181
4182     if (pp_context) {
4183         i965_post_processing_context_finalize(pp_context);
4184         free(pp_context);
4185     }
4186
4187     i965->pp_context = NULL;
4188
4189     return True;
4190 }
4191
4192 static void
4193 i965_post_processing_context_init(VADriverContextP ctx,
4194                                   struct i965_post_processing_context *pp_context,
4195                                   struct intel_batchbuffer *batch)
4196 {
4197     struct i965_driver_data *i965 = i965_driver_data(ctx);
4198     int i;
4199
4200     pp_context->urb.size = URB_SIZE((&i965->intel));
4201     pp_context->urb.num_vfe_entries = 32;
4202     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4203     pp_context->urb.num_cs_entries = 1;
4204
4205     if (IS_GEN7(i965->intel.device_id))
4206         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4207     else
4208         pp_context->urb.size_cs_entry = 2;
4209
4210     pp_context->urb.vfe_start = 0;
4211     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4212         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4213     assert(pp_context->urb.cs_start +
4214            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4215
4216     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4217     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4218     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4219
4220     if (IS_GEN7(i965->intel.device_id))
4221         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4222     else if (IS_GEN6(i965->intel.device_id))
4223         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4224     else if (IS_IRONLAKE(i965->intel.device_id))
4225         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4226
4227     for (i = 0; i < NUM_PP_MODULES; i++) {
4228         struct pp_module *pp_module = &pp_context->pp_modules[i];
4229         dri_bo_unreference(pp_module->kernel.bo);
4230         if (pp_module->kernel.bin && pp_module->kernel.size) {
4231             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4232                                                 pp_module->kernel.name,
4233                                                 pp_module->kernel.size,
4234                                                 4096);
4235             assert(pp_module->kernel.bo);
4236             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4237         } else {
4238             pp_module->kernel.bo = NULL;
4239         }
4240     }
4241
4242     /* static & inline parameters */
4243     if (IS_GEN7(i965->intel.device_id)) {
4244         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4245         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4246     } else {
4247         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4248         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4249     }
4250
4251     pp_context->batch = batch;
4252 }
4253
4254 Bool
4255 i965_post_processing_init(VADriverContextP ctx)
4256 {
4257     struct i965_driver_data *i965 = i965_driver_data(ctx);
4258     struct i965_post_processing_context *pp_context = i965->pp_context;
4259
4260     if (HAS_PP(i965)) {
4261         if (pp_context == NULL) {
4262             pp_context = calloc(1, sizeof(*pp_context));
4263             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4264             i965->pp_context = pp_context;
4265         }
4266     }
4267
4268     return True;
4269 }
4270
4271 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4272     PP_NULL,    /* VAProcFilterNone */
4273     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4274     PP_NULL,    /* VAProcFilterDeblocking */
4275     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4276     PP_NULL,    /* VAProcFilterSharpening */
4277     PP_NULL,    /* VAProcFilterColorBalance */
4278     PP_NULL,    /* VAProcFilterColorStandard */
4279     PP_NULL,    /* VAProcFilterFrameRateConversion */
4280 };
4281
4282 static const int proc_frame_to_pp_frame[3] = {
4283     I965_SURFACE_FLAG_FRAME,
4284     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4285     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4286 };
4287
4288 static void
4289 i965_proc_picture(VADriverContextP ctx,
4290                   VAProfile profile,
4291                   union codec_state *codec_state,
4292                   struct hw_context *hw_context)
4293 {
4294     struct i965_driver_data *i965 = i965_driver_data(ctx);
4295     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4296     struct proc_state *proc_state = &codec_state->proc;
4297     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4298     struct object_surface *obj_surface;
4299     struct i965_surface src_surface, dst_surface;
4300     VARectangle src_rect, dst_rect;
4301     VAStatus status;
4302     int i;
4303     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4304     int num_tmp_surfaces = 0;
4305     unsigned int tiling = 0, swizzle = 0;
4306     int in_width, in_height;
4307
4308     assert(pipeline_param->surface != VA_INVALID_ID);
4309     assert(proc_state->current_render_target != VA_INVALID_ID);
4310
4311     obj_surface = SURFACE(pipeline_param->surface);
4312     in_width = obj_surface->orig_width;
4313     in_height = obj_surface->orig_height;
4314     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4315
4316     src_surface.id = pipeline_param->surface;
4317     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4318     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4319
4320     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4321         VASurfaceID out_surface_id = VA_INVALID_ID;
4322
4323         src_surface.id = pipeline_param->surface;
4324         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4325         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4326         src_rect.x = 0;
4327         src_rect.y = 0;
4328         src_rect.width = in_width;
4329         src_rect.height = in_height;
4330
4331         status = i965_CreateSurfaces(ctx,
4332                                      in_width,
4333                                      in_height,
4334                                      VA_RT_FORMAT_YUV420,
4335                                      1,
4336                                      &out_surface_id);
4337         assert(status == VA_STATUS_SUCCESS);
4338         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4339         obj_surface = SURFACE(out_surface_id);
4340         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4341
4342         dst_surface.id = out_surface_id;
4343         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4344         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4345         dst_rect.x = 0;
4346         dst_rect.y = 0;
4347         dst_rect.width = in_width;
4348         dst_rect.height = in_height;
4349
4350         status = i965_image_processing(ctx,
4351                                        &src_surface,
4352                                        &src_rect,
4353                                        &dst_surface,
4354                                        &dst_rect);
4355         assert(status == VA_STATUS_SUCCESS);
4356
4357         src_surface.id = out_surface_id;
4358         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4359         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4360     }
4361
4362     if (pipeline_param->surface_region) {
4363         src_rect.x = pipeline_param->surface_region->x;
4364         src_rect.y = pipeline_param->surface_region->y;
4365         src_rect.width = pipeline_param->surface_region->width;
4366         src_rect.height = pipeline_param->surface_region->height;
4367     } else {
4368         src_rect.x = 0;
4369         src_rect.y = 0;
4370         src_rect.width = in_width;
4371         src_rect.height = in_height;
4372     }
4373
4374     if (pipeline_param->output_region) {
4375         dst_rect.x = pipeline_param->output_region->x;
4376         dst_rect.y = pipeline_param->output_region->y;
4377         dst_rect.width = pipeline_param->output_region->width;
4378         dst_rect.height = pipeline_param->output_region->height;
4379     } else {
4380         dst_rect.x = 0;
4381         dst_rect.y = 0;
4382         dst_rect.width = in_width;
4383         dst_rect.height = in_height;
4384     }
4385
4386     obj_surface = SURFACE(proc_state->current_render_target);
4387     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4388     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4389
4390     for (i = 0; i < pipeline_param->num_filters; i++) {
4391         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4392         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4393         VAProcFilterType filter_type = filter_param->type;
4394         VASurfaceID out_surface_id = VA_INVALID_ID;
4395         int kernel_index = procfilter_to_pp_flag[filter_type];
4396
4397         if (kernel_index != PP_NULL &&
4398             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4399             status = i965_CreateSurfaces(ctx,
4400                                          in_width,
4401                                          in_height,
4402                                          VA_RT_FORMAT_YUV420,
4403                                          1,
4404                                          &out_surface_id);
4405             assert(status == VA_STATUS_SUCCESS);
4406             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4407             obj_surface = SURFACE(out_surface_id);
4408             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4409             dst_surface.id = out_surface_id;
4410             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4411             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4412                                                    &src_surface,
4413                                                    &src_rect,
4414                                                    &dst_surface,
4415                                                    &src_rect,
4416                                                    kernel_index,
4417                                                    filter_param);
4418
4419             if (status == VA_STATUS_SUCCESS) {
4420                 src_surface.id = dst_surface.id;
4421                 src_surface.type = dst_surface.type;
4422                 src_surface.flags = dst_surface.flags;
4423             }
4424         }
4425     }
4426
4427     dst_surface.id = proc_state->current_render_target;
4428     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4429
4430     if (src_rect.width == dst_rect.width &&
4431         src_rect.height == dst_rect.height) {
4432         i965_post_processing_internal(ctx, &proc_context->pp_context,
4433                                       &src_surface,
4434                                       &src_rect,
4435                                       &dst_surface,
4436                                       &dst_rect,
4437                                       PP_NV12_LOAD_SAVE_N12,
4438                                       NULL);
4439     } else {
4440
4441         i965_post_processing_internal(ctx, &proc_context->pp_context,
4442                                       &src_surface,
4443                                       &src_rect,
4444                                       &dst_surface,
4445                                       &dst_rect,
4446                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4447                                       PP_NV12_AVS : PP_NV12_SCALING,
4448                                       NULL);
4449     }
4450
4451     if (num_tmp_surfaces)
4452         i965_DestroySurfaces(ctx,
4453                              tmp_surfaces,
4454                              num_tmp_surfaces);
4455
4456     intel_batchbuffer_flush(hw_context->batch);
4457 }
4458
4459 static void
4460 i965_proc_context_destroy(void *hw_context)
4461 {
4462     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4463
4464     i965_post_processing_context_finalize(&proc_context->pp_context);
4465     intel_batchbuffer_free(proc_context->base.batch);
4466     free(proc_context);
4467 }
4468
4469 struct hw_context *
4470 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4471 {
4472     struct intel_driver_data *intel = intel_driver_data(ctx);
4473     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4474
4475     proc_context->base.destroy = i965_proc_context_destroy;
4476     proc_context->base.run = i965_proc_picture;
4477     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4478     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4479
4480     return (struct hw_context *)proc_context;
4481 }