src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 103                                    const struct i965_surface *src_surface,
 104                                    const VARectangle *src_rect,
 105                                    struct i965_surface *dst_surface,
 106                                    const VARectangle *dst_rect,
 107                                    void *filter_param);
 108 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 109                                             const struct i965_surface *src_surface,
 110                                             const VARectangle *src_rect,
 111                                             struct i965_surface *dst_surface,
 112                                             const VARectangle *dst_rect,
 113                                             void *filter_param);
 114 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 115                                            const struct i965_surface *src_surface,
 116                                            const VARectangle *src_rect,
 117                                            struct i965_surface *dst_surface,
 118                                            const VARectangle *dst_rect,
 119                                            void *filter_param);
 120 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 121                                              const struct i965_surface *src_surface,
 122                                              const VARectangle *src_rect,
 123                                              struct i965_surface *dst_surface,
 124                                              const VARectangle *dst_rect,
 125                                              void *filter_param);
 126 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 127                                                 const struct i965_surface *src_surface,
 128                                                 const VARectangle *src_rect,
 129                                                 struct i965_surface *dst_surface,
 130                                                 const VARectangle *dst_rect,
 131                                                 void *filter_param);
 132 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 133                                         const struct i965_surface *src_surface,
 134                                         const VARectangle *src_rect,
 135                                         struct i965_surface *dst_surface,
 136                                         const VARectangle *dst_rect,
 137                                         void *filter_param);
 138 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 139                                       const struct i965_surface *src_surface,
 140                                       const VARectangle *src_rect,
 141                                       struct i965_surface *dst_surface,
 142                                       const VARectangle *dst_rect,
 143                                       void *filter_param);
 144
 145 static struct pp_module pp_modules_gen5[] = {
 146     {
 147         {
 148             "NULL module (for testing)",
 149             PP_NULL,
 150             pp_null_gen5,
 151             sizeof(pp_null_gen5),
 152             NULL,
 153         },
 154
 155         pp_null_initialize,
 156     },
 157
 158     {
 159         {
 160             "NV12_NV12",
 161             PP_NV12_LOAD_SAVE_N12,
 162             pp_nv12_load_save_nv12_gen5,
 163             sizeof(pp_nv12_load_save_nv12_gen5),
 164             NULL,
 165         },
 166
 167         pp_plx_load_save_plx_initialize,
 168     },
 169
 170     {
 171         {
 172             "NV12_PL3",
 173             PP_NV12_LOAD_SAVE_PL3,
 174             pp_nv12_load_save_pl3_gen5,
 175             sizeof(pp_nv12_load_save_pl3_gen5),
 176             NULL,
 177         },
 178
 179         pp_plx_load_save_plx_initialize,
 180     },
 181
 182     {
 183         {
 184             "PL3_NV12",
 185             PP_PL3_LOAD_SAVE_N12,
 186             pp_pl3_load_save_nv12_gen5,
 187             sizeof(pp_pl3_load_save_nv12_gen5),
 188             NULL,
 189         },
 190
 191         pp_plx_load_save_plx_initialize,
 192     },
 193
 194     {
 195         {
 196             "PL3_PL3",
 197             PP_PL3_LOAD_SAVE_N12,
 198             pp_pl3_load_save_pl3_gen5,
 199             sizeof(pp_pl3_load_save_pl3_gen5),
 200             NULL,
 201         },
 202
 203         pp_plx_load_save_plx_initialize
 204     },
 205
 206     {
 207         {
 208             "NV12 Scaling module",
 209             PP_NV12_SCALING,
 210             pp_nv12_scaling_gen5,
 211             sizeof(pp_nv12_scaling_gen5),
 212             NULL,
 213         },
 214
 215         pp_nv12_scaling_initialize,
 216     },
 217
 218     {
 219         {
 220             "NV12 AVS module",
 221             PP_NV12_AVS,
 222             pp_nv12_avs_gen5,
 223             sizeof(pp_nv12_avs_gen5),
 224             NULL,
 225         },
 226
 227         pp_nv12_avs_initialize_nlas,
 228     },
 229
 230     {
 231         {
 232             "NV12 DNDI module",
 233             PP_NV12_DNDI,
 234             pp_nv12_dndi_gen5,
 235             sizeof(pp_nv12_dndi_gen5),
 236             NULL,
 237         },
 238
 239         pp_nv12_dndi_initialize,
 240     },
 241
 242     {
 243         {
 244             "NV12 DN module",
 245             PP_NV12_DN,
 246             pp_nv12_dn_gen5,
 247             sizeof(pp_nv12_dn_gen5),
 248             NULL,
 249         },
 250
 251         pp_nv12_dn_initialize,
 252     },
 253
 254     {
 255         {
 256             "NV12_PA module",
 257             PP_NV12_LOAD_SAVE_PA,
 258             pp_nv12_load_save_pa_gen5,
 259             sizeof(pp_nv12_load_save_pa_gen5),
 260             NULL,
 261         },
 262
 263         pp_plx_load_save_plx_initialize,
 264     },
 265
 266     {
 267         {
 268             "PL3_PA module",
 269             PP_PL3_LOAD_SAVE_PA,
 270             pp_pl3_load_save_pa_gen5,
 271             sizeof(pp_pl3_load_save_pa_gen5),
 272             NULL,
 273         },
 274
 275         pp_plx_load_save_plx_initialize,
 276     },
 277
 278 };
 279
 280 static const uint32_t pp_null_gen6[][4] = {
 281 #include "shaders/post_processing/gen5_6/null.g6b"
 282 };
 283
 284 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 285 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 286 };
 287
 288 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 289 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 290 };
 291
 292 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 293 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 294 };
 295
 296 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 297 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 298 };
 299
 300 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 301 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 302 };
 303
 304 static const uint32_t pp_nv12_avs_gen6[][4] = {
 305 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 306 };
 307
 308 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 309 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 310 };
 311
 312 static const uint32_t pp_nv12_dn_gen6[][4] = {
 313 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 314 };
 315
 316 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 317 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 318 };
 319
 320 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 321 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 322 };
 323
 324 static struct pp_module pp_modules_gen6[] = {
 325     {
 326         {
 327             "NULL module (for testing)",
 328             PP_NULL,
 329             pp_null_gen6,
 330             sizeof(pp_null_gen6),
 331             NULL,
 332         },
 333
 334         pp_null_initialize,
 335     },
 336
 337     {
 338         {
 339             "NV12_NV12",
 340             PP_NV12_LOAD_SAVE_N12,
 341             pp_nv12_load_save_nv12_gen6,
 342             sizeof(pp_nv12_load_save_nv12_gen6),
 343             NULL,
 344         },
 345
 346         pp_plx_load_save_plx_initialize,
 347     },
 348
 349     {
 350         {
 351             "NV12_PL3",
 352             PP_NV12_LOAD_SAVE_PL3,
 353             pp_nv12_load_save_pl3_gen6,
 354             sizeof(pp_nv12_load_save_pl3_gen6),
 355             NULL,
 356         },
 357
 358         pp_plx_load_save_plx_initialize,
 359     },
 360
 361     {
 362         {
 363             "PL3_NV12",
 364             PP_PL3_LOAD_SAVE_N12,
 365             pp_pl3_load_save_nv12_gen6,
 366             sizeof(pp_pl3_load_save_nv12_gen6),
 367             NULL,
 368         },
 369
 370         pp_plx_load_save_plx_initialize,
 371     },
 372
 373     {
 374         {
 375             "PL3_PL3",
 376             PP_PL3_LOAD_SAVE_N12,
 377             pp_pl3_load_save_pl3_gen6,
 378             sizeof(pp_pl3_load_save_pl3_gen6),
 379             NULL,
 380         },
 381
 382         pp_plx_load_save_plx_initialize,
 383     },
 384
 385     {
 386         {
 387             "NV12 Scaling module",
 388             PP_NV12_SCALING,
 389             pp_nv12_scaling_gen6,
 390             sizeof(pp_nv12_scaling_gen6),
 391             NULL,
 392         },
 393
 394         gen6_nv12_scaling_initialize,
 395     },
 396
 397     {
 398         {
 399             "NV12 AVS module",
 400             PP_NV12_AVS,
 401             pp_nv12_avs_gen6,
 402             sizeof(pp_nv12_avs_gen6),
 403             NULL,
 404         },
 405
 406         pp_nv12_avs_initialize_nlas,
 407     },
 408
 409     {
 410         {
 411             "NV12 DNDI module",
 412             PP_NV12_DNDI,
 413             pp_nv12_dndi_gen6,
 414             sizeof(pp_nv12_dndi_gen6),
 415             NULL,
 416         },
 417
 418         pp_nv12_dndi_initialize,
 419     },
 420
 421     {
 422         {
 423             "NV12 DN module",
 424             PP_NV12_DN,
 425             pp_nv12_dn_gen6,
 426             sizeof(pp_nv12_dn_gen6),
 427             NULL,
 428         },
 429
 430         pp_nv12_dn_initialize,
 431     },
 432     {
 433         {
 434             "NV12_PA module",
 435             PP_NV12_LOAD_SAVE_PA,
 436             pp_nv12_load_save_pa_gen6,
 437             sizeof(pp_nv12_load_save_pa_gen6),
 438             NULL,
 439         },
 440
 441         pp_plx_load_save_plx_initialize,
 442     },
 443
 444     {
 445         {
 446             "PL3_PA module",
 447             PP_PL3_LOAD_SAVE_PA,
 448             pp_pl3_load_save_pa_gen6,
 449             sizeof(pp_pl3_load_save_pa_gen6),
 450             NULL,
 451         },
 452
 453         pp_plx_load_save_plx_initialize,
 454     },
 455
 456 };
 457
 458 static const uint32_t pp_null_gen7[][4] = {
 459 };
 460
 461 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 462 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 463 };
 464
 465 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 466 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 467 };
 468
 469 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 470 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 471 };
 472
 473 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 474 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 475 };
 476
 477 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 478 #include "shaders/post_processing/gen7/avs.g7b"
 479 };
 480
 481 static const uint32_t pp_nv12_avs_gen7[][4] = {
 482 #include "shaders/post_processing/gen7/avs.g7b"
 483 };
 484
 485 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 486 #include "shaders/post_processing/gen7/dndi.g7b"
 487 };
 488
 489 static const uint32_t pp_nv12_dn_gen7[][4] = {
 490 };
 491 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 492 };
 493 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 494 };
 495
 496 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 497                                            const struct i965_surface *src_surface,
 498                                            const VARectangle *src_rect,
 499                                            struct i965_surface *dst_surface,
 500                                            const VARectangle *dst_rect,
 501                                            void *filter_param);
 502 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 503                                              const struct i965_surface *src_surface,
 504                                              const VARectangle *src_rect,
 505                                              struct i965_surface *dst_surface,
 506                                              const VARectangle *dst_rect,
 507                                              void *filter_param);
 508 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 509                                            const struct i965_surface *src_surface,
 510                                            const VARectangle *src_rect,
 511                                            struct i965_surface *dst_surface,
 512                                            const VARectangle *dst_rect,
 513                                            void *filter_param);
 514
 515 static struct pp_module pp_modules_gen7[] = {
 516     {
 517         {
 518             "NULL module (for testing)",
 519             PP_NULL,
 520             pp_null_gen7,
 521             sizeof(pp_null_gen7),
 522             NULL,
 523         },
 524
 525         pp_null_initialize,
 526     },
 527
 528     {
 529         {
 530             "NV12_NV12",
 531             PP_NV12_LOAD_SAVE_N12,
 532             pp_nv12_load_save_nv12_gen7,
 533             sizeof(pp_nv12_load_save_nv12_gen7),
 534             NULL,
 535         },
 536
 537         gen7_pp_plx_avs_initialize,
 538     },
 539
 540     {
 541         {
 542             "NV12_PL3",
 543             PP_NV12_LOAD_SAVE_PL3,
 544             pp_nv12_load_save_pl3_gen7,
 545             sizeof(pp_nv12_load_save_pl3_gen7),
 546             NULL,
 547         },
 548
 549         gen7_pp_plx_avs_initialize,
 550     },
 551
 552     {
 553         {
 554             "PL3_NV12",
 555             PP_PL3_LOAD_SAVE_N12,
 556             pp_pl3_load_save_nv12_gen7,
 557             sizeof(pp_pl3_load_save_nv12_gen7),
 558             NULL,
 559         },
 560
 561         gen7_pp_plx_avs_initialize,
 562     },
 563
 564     {
 565         {
 566             "PL3_PL3",
 567             PP_PL3_LOAD_SAVE_N12,
 568             pp_pl3_load_save_pl3_gen7,
 569             sizeof(pp_pl3_load_save_pl3_gen7),
 570             NULL,
 571         },
 572
 573         gen7_pp_plx_avs_initialize,
 574     },
 575
 576     {
 577         {
 578             "NV12 Scaling module",
 579             PP_NV12_SCALING,
 580             pp_nv12_scaling_gen7,
 581             sizeof(pp_nv12_scaling_gen7),
 582             NULL,
 583         },
 584
 585         gen7_pp_plx_avs_initialize,
 586     },
 587
 588     {
 589         {
 590             "NV12 AVS module",
 591             PP_NV12_AVS,
 592             pp_nv12_avs_gen7,
 593             sizeof(pp_nv12_avs_gen7),
 594             NULL,
 595         },
 596
 597         gen7_pp_plx_avs_initialize,
 598     },
 599
 600     {
 601         {
 602             "NV12 DNDI module",
 603             PP_NV12_DNDI,
 604             pp_nv12_dndi_gen7,
 605             sizeof(pp_nv12_dndi_gen7),
 606             NULL,
 607         },
 608
 609         gen7_pp_nv12_dndi_initialize,
 610     },
 611
 612     {
 613         {
 614             "NV12 DN module",
 615             PP_NV12_DN,
 616             pp_nv12_dn_gen7,
 617             sizeof(pp_nv12_dn_gen7),
 618             NULL,
 619         },
 620
 621         gen7_pp_nv12_dn_initialize,
 622     },
 623     {
 624         {
 625             "NV12_PA module",
 626             PP_NV12_LOAD_SAVE_PA,
 627             pp_nv12_load_save_pa_gen7,
 628             sizeof(pp_nv12_load_save_pa_gen7),
 629             NULL,
 630         },
 631
 632         pp_plx_load_save_plx_initialize,
 633     },
 634
 635     {
 636         {
 637             "PL3_PA module",
 638             PP_PL3_LOAD_SAVE_PA,
 639             pp_pl3_load_save_pa_gen7,
 640             sizeof(pp_pl3_load_save_pa_gen7),
 641             NULL,
 642         },
 643
 644         pp_plx_load_save_plx_initialize,
 645     },
 646
 647 };
 648
 649 static int
 650 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 651 {
 652     struct i965_driver_data *i965 = i965_driver_data(ctx);
 653     int fourcc;
 654
 655     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 656         struct object_image *obj_image = IMAGE(surface->id);
 657         fourcc = obj_image->image.format.fourcc;
 658     } else {
 659         struct object_surface *obj_surface = SURFACE(surface->id);
 660         fourcc = obj_surface->fourcc;
 661     }
 662
 663     return fourcc;
 664 }
 665
 666 static void
 667 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 668 {
 669     switch (tiling) {
 670     case I915_TILING_NONE:
 671         ss->ss3.tiled_surface = 0;
 672         ss->ss3.tile_walk = 0;
 673         break;
 674     case I915_TILING_X:
 675         ss->ss3.tiled_surface = 1;
 676         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 677         break;
 678     case I915_TILING_Y:
 679         ss->ss3.tiled_surface = 1;
 680         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 681         break;
 682     }
 683 }
 684
 685 static void
 686 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 687 {
 688     switch (tiling) {
 689     case I915_TILING_NONE:
 690         ss->ss2.tiled_surface = 0;
 691         ss->ss2.tile_walk = 0;
 692         break;
 693     case I915_TILING_X:
 694         ss->ss2.tiled_surface = 1;
 695         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 696         break;
 697     case I915_TILING_Y:
 698         ss->ss2.tiled_surface = 1;
 699         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 700         break;
 701     }
 702 }
 703
 704 static void
 705 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 706 {
 707     switch (tiling) {
 708     case I915_TILING_NONE:
 709         ss->ss0.tiled_surface = 0;
 710         ss->ss0.tile_walk = 0;
 711         break;
 712     case I915_TILING_X:
 713         ss->ss0.tiled_surface = 1;
 714         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 715         break;
 716     case I915_TILING_Y:
 717         ss->ss0.tiled_surface = 1;
 718         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 719         break;
 720     }
 721 }
 722
 723 static void
 724 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 725 {
 726     switch (tiling) {
 727     case I915_TILING_NONE:
 728         ss->ss2.tiled_surface = 0;
 729         ss->ss2.tile_walk = 0;
 730         break;
 731     case I915_TILING_X:
 732         ss->ss2.tiled_surface = 1;
 733         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 734         break;
 735     case I915_TILING_Y:
 736         ss->ss2.tiled_surface = 1;
 737         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 738         break;
 739     }
 740 }
 741
 742 static void
 743 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 744 {
 745     struct i965_interface_descriptor *desc;
 746     dri_bo *bo;
 747     int pp_index = pp_context->current_pp;
 748
 749     bo = pp_context->idrt.bo;
 750     dri_bo_map(bo, 1);
 751     assert(bo->virtual);
 752     desc = bo->virtual;
 753     memset(desc, 0, sizeof(*desc));
 754     desc->desc0.grf_reg_blocks = 10;
 755     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 756     desc->desc1.const_urb_entry_read_offset = 0;
 757     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 758     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 759     desc->desc2.sampler_count = 0;
 760     desc->desc3.binding_table_entry_count = 0;
 761     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 762
 763     dri_bo_emit_reloc(bo,
 764                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 765                       desc->desc0.grf_reg_blocks,
 766                       offsetof(struct i965_interface_descriptor, desc0),
 767                       pp_context->pp_modules[pp_index].kernel.bo);
 768
 769     dri_bo_emit_reloc(bo,
 770                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 771                       desc->desc2.sampler_count << 2,
 772                       offsetof(struct i965_interface_descriptor, desc2),
 773                       pp_context->sampler_state_table.bo);
 774
 775     dri_bo_unmap(bo);
 776     pp_context->idrt.num_interface_descriptors++;
 777 }
 778
 779 static void
 780 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 781 {
 782     struct i965_vfe_state *vfe_state;
 783     dri_bo *bo;
 784
 785     bo = pp_context->vfe_state.bo;
 786     dri_bo_map(bo, 1);
 787     assert(bo->virtual);
 788     vfe_state = bo->virtual;
 789     memset(vfe_state, 0, sizeof(*vfe_state));
 790     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 791     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 792     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 793     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 794     vfe_state->vfe1.children_present = 0;
 795     vfe_state->vfe2.interface_descriptor_base =
 796         pp_context->idrt.bo->offset >> 4; /* reloc */
 797     dri_bo_emit_reloc(bo,
 798                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 799                       0,
 800                       offsetof(struct i965_vfe_state, vfe2),
 801                       pp_context->idrt.bo);
 802     dri_bo_unmap(bo);
 803 }
 804
 805 static void
 806 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 807 {
 808     unsigned char *constant_buffer;
 809     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 810
 811     assert(sizeof(*pp_static_parameter) == 128);
 812     dri_bo_map(pp_context->curbe.bo, 1);
 813     assert(pp_context->curbe.bo->virtual);
 814     constant_buffer = pp_context->curbe.bo->virtual;
 815     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 816     dri_bo_unmap(pp_context->curbe.bo);
 817 }
 818
 819 static void
 820 ironlake_pp_states_setup(VADriverContextP ctx,
 821                          struct i965_post_processing_context *pp_context)
 822 {
 823     ironlake_pp_interface_descriptor_table(pp_context);
 824     ironlake_pp_vfe_state(pp_context);
 825     ironlake_pp_upload_constants(pp_context);
 826 }
 827
 828 static void
 829 ironlake_pp_pipeline_select(VADriverContextP ctx,
 830                             struct i965_post_processing_context *pp_context)
 831 {
 832     struct intel_batchbuffer *batch = pp_context->batch;
 833
 834     BEGIN_BATCH(batch, 1);
 835     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 836     ADVANCE_BATCH(batch);
 837 }
 838
 839 static void
 840 ironlake_pp_urb_layout(VADriverContextP ctx,
 841                        struct i965_post_processing_context *pp_context)
 842 {
 843     struct intel_batchbuffer *batch = pp_context->batch;
 844     unsigned int vfe_fence, cs_fence;
 845
 846     vfe_fence = pp_context->urb.cs_start;
 847     cs_fence = pp_context->urb.size;
 848
 849     BEGIN_BATCH(batch, 3);
 850     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 851     OUT_BATCH(batch, 0);
 852     OUT_BATCH(batch,
 853               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 854               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 855     ADVANCE_BATCH(batch);
 856 }
 857
 858 static void
 859 ironlake_pp_state_base_address(VADriverContextP ctx,
 860                                struct i965_post_processing_context *pp_context)
 861 {
 862     struct intel_batchbuffer *batch = pp_context->batch;
 863
 864     BEGIN_BATCH(batch, 8);
 865     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 866     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 867     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 868     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 869     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 870     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 871     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 872     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 873     ADVANCE_BATCH(batch);
 874 }
 875
 876 static void
 877 ironlake_pp_state_pointers(VADriverContextP ctx,
 878                            struct i965_post_processing_context *pp_context)
 879 {
 880     struct intel_batchbuffer *batch = pp_context->batch;
 881
 882     BEGIN_BATCH(batch, 3);
 883     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 884     OUT_BATCH(batch, 0);
 885     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 886     ADVANCE_BATCH(batch);
 887 }
 888
 889 static void
 890 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 891                           struct i965_post_processing_context *pp_context)
 892 {
 893     struct intel_batchbuffer *batch = pp_context->batch;
 894
 895     BEGIN_BATCH(batch, 2);
 896     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 897     OUT_BATCH(batch,
 898               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 899               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 900     ADVANCE_BATCH(batch);
 901 }
 902
 903 static void
 904 ironlake_pp_constant_buffer(VADriverContextP ctx,
 905                             struct i965_post_processing_context *pp_context)
 906 {
 907     struct intel_batchbuffer *batch = pp_context->batch;
 908
 909     BEGIN_BATCH(batch, 2);
 910     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 911     OUT_RELOC(batch, pp_context->curbe.bo,
 912               I915_GEM_DOMAIN_INSTRUCTION, 0,
 913               pp_context->urb.size_cs_entry - 1);
 914     ADVANCE_BATCH(batch);
 915 }
 916
 917 static void
 918 ironlake_pp_object_walker(VADriverContextP ctx,
 919                           struct i965_post_processing_context *pp_context)
 920 {
 921     struct intel_batchbuffer *batch = pp_context->batch;
 922     int x, x_steps, y, y_steps;
 923     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
 924
 925     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
 926     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
 927
 928     for (y = 0; y < y_steps; y++) {
 929         for (x = 0; x < x_steps; x++) {
 930             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
 931                 BEGIN_BATCH(batch, 20);
 932                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
 933                 OUT_BATCH(batch, 0);
 934                 OUT_BATCH(batch, 0); /* no indirect data */
 935                 OUT_BATCH(batch, 0);
 936
 937                 /* inline data grf 5-6 */
 938                 assert(sizeof(*pp_inline_parameter) == 64);
 939                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
 940
 941                 ADVANCE_BATCH(batch);
 942             }
 943         }
 944     }
 945 }
 946
 947 static void
 948 ironlake_pp_pipeline_setup(VADriverContextP ctx,
 949                            struct i965_post_processing_context *pp_context)
 950 {
 951     struct intel_batchbuffer *batch = pp_context->batch;
 952
 953     intel_batchbuffer_start_atomic(batch, 0x1000);
 954     intel_batchbuffer_emit_mi_flush(batch);
 955     ironlake_pp_pipeline_select(ctx, pp_context);
 956     ironlake_pp_state_base_address(ctx, pp_context);
 957     ironlake_pp_state_pointers(ctx, pp_context);
 958     ironlake_pp_urb_layout(ctx, pp_context);
 959     ironlake_pp_cs_urb_layout(ctx, pp_context);
 960     ironlake_pp_constant_buffer(ctx, pp_context);
 961     ironlake_pp_object_walker(ctx, pp_context);
 962     intel_batchbuffer_end_atomic(batch);
 963 }
 964
 965 static void
 966 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 967                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 968                           int width, int height, int pitch, int format,
 969                           int index, int is_target)
 970 {
 971     struct i965_surface_state *ss;
 972     dri_bo *ss_bo;
 973     unsigned int tiling;
 974     unsigned int swizzle;
 975
 976     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 977     ss_bo = pp_context->surface_state_binding_table.bo;
 978     assert(ss_bo);
 979
 980     dri_bo_map(ss_bo, True);
 981     assert(ss_bo->virtual);
 982     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 983     memset(ss, 0, sizeof(*ss));
 984     ss->ss0.surface_type = I965_SURFACE_2D;
 985     ss->ss0.surface_format = format;
 986     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 987     ss->ss2.width = width - 1;
 988     ss->ss2.height = height - 1;
 989     ss->ss3.pitch = pitch - 1;
 990     pp_set_surface_tiling(ss, tiling);
 991     dri_bo_emit_reloc(ss_bo,
 992                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 993                       surf_bo_offset,
 994                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 995                       surf_bo);
 996     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 997     dri_bo_unmap(ss_bo);
 998 }
 999
1000 static void
1001 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1002                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1003                            int width, int height, int wpitch,
1004                            int xoffset, int yoffset,
1005                            int format, int interleave_chroma,
1006                            int index)
1007 {
1008     struct i965_surface_state2 *ss2;
1009     dri_bo *ss2_bo;
1010     unsigned int tiling;
1011     unsigned int swizzle;
1012
1013     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1014     ss2_bo = pp_context->surface_state_binding_table.bo;
1015     assert(ss2_bo);
1016
1017     dri_bo_map(ss2_bo, True);
1018     assert(ss2_bo->virtual);
1019     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1020     memset(ss2, 0, sizeof(*ss2));
1021     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1022     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1023     ss2->ss1.width = width - 1;
1024     ss2->ss1.height = height - 1;
1025     ss2->ss2.pitch = wpitch - 1;
1026     ss2->ss2.interleave_chroma = interleave_chroma;
1027     ss2->ss2.surface_format = format;
1028     ss2->ss3.x_offset_for_cb = xoffset;
1029     ss2->ss3.y_offset_for_cb = yoffset;
1030     pp_set_surface2_tiling(ss2, tiling);
1031     dri_bo_emit_reloc(ss2_bo,
1032                       I915_GEM_DOMAIN_RENDER, 0,
1033                       surf_bo_offset,
1034                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1035                       surf_bo);
1036     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1037     dri_bo_unmap(ss2_bo);
1038 }
1039
1040 static void
1041 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1042                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1043                           int width, int height, int pitch, int format,
1044                           int index, int is_target)
1045 {
1046     struct gen7_surface_state *ss;
1047     dri_bo *ss_bo;
1048     unsigned int tiling;
1049     unsigned int swizzle;
1050
1051     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1052     ss_bo = pp_context->surface_state_binding_table.bo;
1053     assert(ss_bo);
1054
1055     dri_bo_map(ss_bo, True);
1056     assert(ss_bo->virtual);
1057     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1058     memset(ss, 0, sizeof(*ss));
1059     ss->ss0.surface_type = I965_SURFACE_2D;
1060     ss->ss0.surface_format = format;
1061     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1062     ss->ss2.width = width - 1;
1063     ss->ss2.height = height - 1;
1064     ss->ss3.pitch = pitch - 1;
1065     gen7_pp_set_surface_tiling(ss, tiling);
1066     dri_bo_emit_reloc(ss_bo,
1067                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1068                       surf_bo_offset,
1069                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1070                       surf_bo);
1071     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1072     dri_bo_unmap(ss_bo);
1073 }
1074
1075 static void
1076 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1077                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1078                            int width, int height, int wpitch,
1079                            int xoffset, int yoffset,
1080                            int format, int interleave_chroma,
1081                            int index)
1082 {
1083     struct gen7_surface_state2 *ss2;
1084     dri_bo *ss2_bo;
1085     unsigned int tiling;
1086     unsigned int swizzle;
1087
1088     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1089     ss2_bo = pp_context->surface_state_binding_table.bo;
1090     assert(ss2_bo);
1091
1092     dri_bo_map(ss2_bo, True);
1093     assert(ss2_bo->virtual);
1094     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1095     memset(ss2, 0, sizeof(*ss2));
1096     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1097     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1098     ss2->ss1.width = width - 1;
1099     ss2->ss1.height = height - 1;
1100     ss2->ss2.pitch = wpitch - 1;
1101     ss2->ss2.interleave_chroma = interleave_chroma;
1102     ss2->ss2.surface_format = format;
1103     ss2->ss3.x_offset_for_cb = xoffset;
1104     ss2->ss3.y_offset_for_cb = yoffset;
1105     gen7_pp_set_surface2_tiling(ss2, tiling);
1106     dri_bo_emit_reloc(ss2_bo,
1107                       I915_GEM_DOMAIN_RENDER, 0,
1108                       surf_bo_offset,
1109                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1110                       surf_bo);
1111     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1112     dri_bo_unmap(ss2_bo);
1113 }
1114
1115 static void
1116 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1117                                 const struct i965_surface *surface,
1118                                 int base_index, int is_target,
1119                                 int *width, int *height, int *pitch, int *offset)
1120 {
1121     struct i965_driver_data *i965 = i965_driver_data(ctx);
1122     struct object_surface *obj_surface;
1123     struct object_image *obj_image;
1124     dri_bo *bo;
1125     int fourcc = pp_get_surface_fourcc(ctx, surface);
1126     const int Y = 0;
1127     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1128     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1129     const int UV = 1;
1130     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1131     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1132
1133     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1134         obj_surface = SURFACE(surface->id);
1135         bo = obj_surface->bo;
1136         width[0] = obj_surface->orig_width;
1137         height[0] = obj_surface->orig_height;
1138         pitch[0] = obj_surface->width;
1139         offset[0] = 0;
1140
1141         if (packed_yuv ) {
1142             width[0] = obj_surface->orig_width * 2;
1143             pitch[0] = obj_surface->width * 2;
1144         }
1145         else if (interleaved_uv) {
1146             width[1] = obj_surface->orig_width;
1147             height[1] = obj_surface->orig_height / 2;
1148             pitch[1] = obj_surface->width;
1149             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1150         } else {
1151             width[1] = obj_surface->orig_width / 2;
1152             height[1] = obj_surface->orig_height / 2;
1153             pitch[1] = obj_surface->width / 2;
1154             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1155             width[2] = obj_surface->orig_width / 2;
1156             height[2] = obj_surface->orig_height / 2;
1157             pitch[2] = obj_surface->width / 2;
1158             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1159         }
1160     } else {
1161         obj_image = IMAGE(surface->id);
1162         bo = obj_image->bo;
1163         width[0] = obj_image->image.width;
1164         height[0] = obj_image->image.height;
1165         pitch[0] = obj_image->image.pitches[0];
1166         offset[0] = obj_image->image.offsets[0];
1167
1168         if (interleaved_uv) {
1169             width[1] = obj_image->image.width;
1170             height[1] = obj_image->image.height / 2;
1171             pitch[1] = obj_image->image.pitches[1];
1172             offset[1] = obj_image->image.offsets[1];
1173         } else {
1174             width[1] = obj_image->image.width / 2;
1175             height[1] = obj_image->image.height / 2;
1176             pitch[1] = obj_image->image.pitches[1];
1177             offset[1] = obj_image->image.offsets[1];
1178             width[2] = obj_image->image.width / 2;
1179             height[2] = obj_image->image.height / 2;
1180             pitch[2] = obj_image->image.pitches[2];
1181             offset[2] = obj_image->image.offsets[2];
1182         }
1183     }
1184
1185     /* Y surface */
1186     i965_pp_set_surface_state(ctx, pp_context,
1187                               bo, offset[Y],
1188                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1189                               base_index, is_target);
1190
1191     if (!packed_yuv) {
1192         if (interleaved_uv) {
1193             i965_pp_set_surface_state(ctx, pp_context,
1194                                       bo, offset[UV],
1195                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1196                                       base_index + 1, is_target);
1197         } else {
1198             /* U surface */
1199             i965_pp_set_surface_state(ctx, pp_context,
1200                                       bo, offset[U],
1201                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1202                                       base_index + 1, is_target);
1203
1204             /* V surface */
1205             i965_pp_set_surface_state(ctx, pp_context,
1206                                       bo, offset[V],
1207                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1208                                       base_index + 2, is_target);
1209         }
1210     }
1211
1212 }
1213
1214 static void
1215 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1216                                      const struct i965_surface *surface,
1217                                      int base_index, int is_target,
1218                                      int *width, int *height, int *pitch, int *offset)
1219 {
1220     struct i965_driver_data *i965 = i965_driver_data(ctx);
1221     struct object_surface *obj_surface;
1222     struct object_image *obj_image;
1223     dri_bo *bo;
1224     int fourcc = pp_get_surface_fourcc(ctx, surface);
1225     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1226                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1227     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1228                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1229     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1230
1231     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1232         obj_surface = SURFACE(surface->id);
1233         bo = obj_surface->bo;
1234         width[0] = obj_surface->orig_width;
1235         height[0] = obj_surface->orig_height;
1236         pitch[0] = obj_surface->width;
1237         offset[0] = 0;
1238
1239         width[1] = obj_surface->cb_cr_width;
1240         height[1] = obj_surface->cb_cr_height;
1241         pitch[1] = obj_surface->cb_cr_pitch;
1242         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1243
1244         width[2] = obj_surface->cb_cr_width;
1245         height[2] = obj_surface->cb_cr_height;
1246         pitch[2] = obj_surface->cb_cr_pitch;
1247         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1248     } else {
1249         obj_image = IMAGE(surface->id);
1250         bo = obj_image->bo;
1251         width[0] = obj_image->image.width;
1252         height[0] = obj_image->image.height;
1253         pitch[0] = obj_image->image.pitches[0];
1254         offset[0] = obj_image->image.offsets[0];
1255
1256         if (interleaved_uv) {
1257             width[1] = obj_image->image.width;
1258             height[1] = obj_image->image.height / 2;
1259             pitch[1] = obj_image->image.pitches[1];
1260             offset[1] = obj_image->image.offsets[1];
1261         } else {
1262             width[1] = obj_image->image.width / 2;
1263             height[1] = obj_image->image.height / 2;
1264             pitch[1] = obj_image->image.pitches[U];
1265             offset[1] = obj_image->image.offsets[U];
1266             width[2] = obj_image->image.width / 2;
1267             height[2] = obj_image->image.height / 2;
1268             pitch[2] = obj_image->image.pitches[V];
1269             offset[2] = obj_image->image.offsets[V];
1270         }
1271     }
1272
1273     if (is_target) {
1274         gen7_pp_set_surface_state(ctx, pp_context,
1275                                   bo, 0,
1276                                   width[0] / 4, height[0], pitch[0],
1277                                   I965_SURFACEFORMAT_R8_SINT,
1278                                   base_index, 1);
1279
1280         if (interleaved_uv) {
1281             gen7_pp_set_surface_state(ctx, pp_context,
1282                                       bo, offset[1],
1283                                       width[1] / 2, height[1], pitch[1],
1284                                       I965_SURFACEFORMAT_R8G8_SINT,
1285                                       base_index + 1, 1);
1286         } else {
1287             gen7_pp_set_surface_state(ctx, pp_context,
1288                                       bo, offset[1],
1289                                       width[1] / 4, height[1], pitch[1],
1290                                       I965_SURFACEFORMAT_R8_SINT,
1291                                       base_index + 1, 1);
1292             gen7_pp_set_surface_state(ctx, pp_context,
1293                                       bo, offset[2],
1294                                       width[2] / 4, height[2], pitch[2],
1295                                       I965_SURFACEFORMAT_R8_SINT,
1296                                       base_index + 2, 1);
1297         }
1298     } else {
1299         gen7_pp_set_surface2_state(ctx, pp_context,
1300                                    bo, offset[0],
1301                                    width[0], height[0], pitch[0],
1302                                    0, 0,
1303                                    SURFACE_FORMAT_Y8_UNORM, 0,
1304                                    base_index);
1305
1306         if (interleaved_uv) {
1307             gen7_pp_set_surface2_state(ctx, pp_context,
1308                                        bo, offset[1],
1309                                        width[1], height[1], pitch[1],
1310                                        0, 0,
1311                                        SURFACE_FORMAT_R8B8_UNORM, 0,
1312                                        base_index + 1);
1313         } else {
1314             gen7_pp_set_surface2_state(ctx, pp_context,
1315                                        bo, offset[1],
1316                                        width[1], height[1], pitch[1],
1317                                        0, 0,
1318                                        SURFACE_FORMAT_R8_UNORM, 0,
1319                                        base_index + 1);
1320             gen7_pp_set_surface2_state(ctx, pp_context,
1321                                        bo, offset[2],
1322                                        width[2], height[2], pitch[2],
1323                                        0, 0,
1324                                        SURFACE_FORMAT_R8_UNORM, 0,
1325                                        base_index + 2);
1326         }
1327     }
1328 }
1329
1330 static int
1331 pp_null_x_steps(void *private_context)
1332 {
1333     return 1;
1334 }
1335
1336 static int
1337 pp_null_y_steps(void *private_context)
1338 {
1339     return 1;
1340 }
1341
1342 static int
1343 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1344 {
1345     return 0;
1346 }
1347
1348 static VAStatus
1349 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1350                    const struct i965_surface *src_surface,
1351                    const VARectangle *src_rect,
1352                    struct i965_surface *dst_surface,
1353                    const VARectangle *dst_rect,
1354                    void *filter_param)
1355 {
1356     /* private function & data */
1357     pp_context->pp_x_steps = pp_null_x_steps;
1358     pp_context->pp_y_steps = pp_null_y_steps;
1359     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1360
1361     dst_surface->flags = src_surface->flags;
1362
1363     return VA_STATUS_SUCCESS;
1364 }
1365
1366 static int
1367 pp_load_save_x_steps(void *private_context)
1368 {
1369     return 1;
1370 }
1371
1372 static int
1373 pp_load_save_y_steps(void *private_context)
1374 {
1375     struct pp_load_save_context *pp_load_save_context = private_context;
1376
1377     return pp_load_save_context->dest_h / 8;
1378 }
1379
1380 static int
1381 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1382 {
1383     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1384
1385     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1386     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1387     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1388     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1389
1390     return 0;
1391 }
1392
1393 static VAStatus
1394 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1395                                 const struct i965_surface *src_surface,
1396                                 const VARectangle *src_rect,
1397                                 struct i965_surface *dst_surface,
1398                                 const VARectangle *dst_rect,
1399                                 void *filter_param)
1400 {
1401     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1402     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1403     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1404     int width[3], height[3], pitch[3], offset[3];
1405     const int Y = 0;
1406
1407     /* source surface */
1408     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1409                                     width, height, pitch, offset);
1410
1411     /* destination surface */
1412     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1413                                     width, height, pitch, offset);
1414
1415     /* private function & data */
1416     pp_context->pp_x_steps = pp_load_save_x_steps;
1417     pp_context->pp_y_steps = pp_load_save_y_steps;
1418     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1419     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1420     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1421
1422     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1423     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1424
1425     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1426     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1427
1428     dst_surface->flags = src_surface->flags;
1429
1430     return VA_STATUS_SUCCESS;
1431 }
1432
1433 static int
1434 pp_scaling_x_steps(void *private_context)
1435 {
1436     return 1;
1437 }
1438
1439 static int
1440 pp_scaling_y_steps(void *private_context)
1441 {
1442     struct pp_scaling_context *pp_scaling_context = private_context;
1443
1444     return pp_scaling_context->dest_h / 8;
1445 }
1446
1447 static int
1448 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1449 {
1450     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1451     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1452     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1453     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1454     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1455
1456     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1457     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1458     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1459     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1460
1461     return 0;
1462 }
1463
1464 static VAStatus
1465 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1466                            const struct i965_surface *src_surface,
1467                            const VARectangle *src_rect,
1468                            struct i965_surface *dst_surface,
1469                            const VARectangle *dst_rect,
1470                            void *filter_param)
1471 {
1472     struct i965_driver_data *i965 = i965_driver_data(ctx);
1473     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1474     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1475     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1476     struct object_surface *obj_surface;
1477     struct i965_sampler_state *sampler_state;
1478     int in_w, in_h, in_wpitch, in_hpitch;
1479     int out_w, out_h, out_wpitch, out_hpitch;
1480
1481     /* source surface */
1482     obj_surface = SURFACE(src_surface->id);
1483     in_w = obj_surface->orig_width;
1484     in_h = obj_surface->orig_height;
1485     in_wpitch = obj_surface->width;
1486     in_hpitch = obj_surface->height;
1487
1488     /* source Y surface index 1 */
1489     i965_pp_set_surface_state(ctx, pp_context,
1490                               obj_surface->bo, 0,
1491                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1492                               1, 0);
1493
1494     /* source UV surface index 2 */
1495     i965_pp_set_surface_state(ctx, pp_context,
1496                               obj_surface->bo, in_wpitch * in_hpitch,
1497                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1498                               2, 0);
1499
1500     /* destination surface */
1501     obj_surface = SURFACE(dst_surface->id);
1502     out_w = obj_surface->orig_width;
1503     out_h = obj_surface->orig_height;
1504     out_wpitch = obj_surface->width;
1505     out_hpitch = obj_surface->height;
1506
1507     /* destination Y surface index 7 */
1508     i965_pp_set_surface_state(ctx, pp_context,
1509                               obj_surface->bo, 0,
1510                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1511                               7, 1);
1512
1513     /* destination UV surface index 8 */
1514     i965_pp_set_surface_state(ctx, pp_context,
1515                               obj_surface->bo, out_wpitch * out_hpitch,
1516                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1517                               8, 1);
1518
1519     /* sampler state */
1520     dri_bo_map(pp_context->sampler_state_table.bo, True);
1521     assert(pp_context->sampler_state_table.bo->virtual);
1522     sampler_state = pp_context->sampler_state_table.bo->virtual;
1523
1524     /* SIMD16 Y index 1 */
1525     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1526     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1527     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1528     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1529     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1530
1531     /* SIMD16 UV index 2 */
1532     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1533     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1534     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1535     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1536     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1537
1538     dri_bo_unmap(pp_context->sampler_state_table.bo);
1539
1540     /* private function & data */
1541     pp_context->pp_x_steps = pp_scaling_x_steps;
1542     pp_context->pp_y_steps = pp_scaling_y_steps;
1543     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1544
1545     pp_scaling_context->dest_x = dst_rect->x;
1546     pp_scaling_context->dest_y = dst_rect->y;
1547     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1548     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1549     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1550     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1551
1552     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1553
1554     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1555     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1556     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1557     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1558     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1559
1560     dst_surface->flags = src_surface->flags;
1561
1562     return VA_STATUS_SUCCESS;
1563 }
1564
1565 static int
1566 pp_avs_x_steps(void *private_context)
1567 {
1568     struct pp_avs_context *pp_avs_context = private_context;
1569
1570     return pp_avs_context->dest_w / 16;
1571 }
1572
1573 static int
1574 pp_avs_y_steps(void *private_context)
1575 {
1576     return 1;
1577 }
1578
1579 static int
1580 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1581 {
1582     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1583     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1584     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1585     float src_x_steping, src_y_steping, video_step_delta;
1586     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1587
1588     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1589         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1590         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1591     } else if (tmp_w >= pp_avs_context->dest_w) {
1592         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1593         pp_inline_parameter->grf6.video_step_delta = 0;
1594
1595         if (x == 0) {
1596             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1597                 pp_avs_context->src_normalized_x;
1598         } else {
1599             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1600             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1601             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1602                 16 * 15 * video_step_delta / 2;
1603         }
1604     } else {
1605         int n0, n1, n2, nls_left, nls_right;
1606         int factor_a = 5, factor_b = 4;
1607         float f;
1608
1609         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1610         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1611         n2 = tmp_w / (16 * factor_a);
1612         nls_left = n0 + n2;
1613         nls_right = n1 + n2;
1614         f = (float) n2 * 16 / tmp_w;
1615
1616         if (n0 < 5) {
1617             pp_inline_parameter->grf6.video_step_delta = 0.0;
1618
1619             if (x == 0) {
1620                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1621                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1622             } else {
1623                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1624                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1625                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1626                     16 * 15 * video_step_delta / 2;
1627             }
1628         } else {
1629             if (x < nls_left) {
1630                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1631                 float a = f / (nls_left * 16 * factor_b);
1632                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1633
1634                 pp_inline_parameter->grf6.video_step_delta = b;
1635
1636                 if (x == 0) {
1637                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1638                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1639                 } else {
1640                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1641                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1642                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1643                         16 * 15 * video_step_delta / 2;
1644                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1645                 }
1646             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1647                 /* scale the center linearly */
1648                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1649                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1650                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1651                     16 * 15 * video_step_delta / 2;
1652                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1653                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1654             } else {
1655                 float a = f / (nls_right * 16 * factor_b);
1656                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1657
1658                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1659                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1660                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1661                     16 * 15 * video_step_delta / 2;
1662                 pp_inline_parameter->grf6.video_step_delta = -b;
1663
1664                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1665                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1666                 else
1667                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1668             }
1669         }
1670     }
1671
1672     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1673     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1674     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1675     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1676
1677     return 0;
1678 }
1679
1680 static VAStatus
1681 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1682                        const struct i965_surface *src_surface,
1683                        const VARectangle *src_rect,
1684                        struct i965_surface *dst_surface,
1685                        const VARectangle *dst_rect,
1686                        void *filter_param,
1687                        int nlas)
1688 {
1689     struct i965_driver_data *i965 = i965_driver_data(ctx);
1690     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1691     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1692     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1693     struct object_surface *obj_surface;
1694     struct i965_sampler_8x8 *sampler_8x8;
1695     struct i965_sampler_8x8_state *sampler_8x8_state;
1696     int index;
1697     int in_w, in_h, in_wpitch, in_hpitch;
1698     int out_w, out_h, out_wpitch, out_hpitch;
1699     int i;
1700
1701     /* surface */
1702     obj_surface = SURFACE(src_surface->id);
1703     in_w = obj_surface->orig_width;
1704     in_h = obj_surface->orig_height;
1705     in_wpitch = obj_surface->width;
1706     in_hpitch = obj_surface->height;
1707
1708     /* source Y surface index 1 */
1709     i965_pp_set_surface2_state(ctx, pp_context,
1710                                obj_surface->bo, 0,
1711                                in_w, in_h, in_wpitch,
1712                                0, 0,
1713                                SURFACE_FORMAT_Y8_UNORM, 0,
1714                                1);
1715
1716     /* source UV surface index 2 */
1717     i965_pp_set_surface2_state(ctx, pp_context,
1718                                obj_surface->bo, in_wpitch * in_hpitch,
1719                                in_w / 2, in_h / 2, in_wpitch,
1720                                0, 0,
1721                                SURFACE_FORMAT_R8B8_UNORM, 0,
1722                                2);
1723
1724     /* destination surface */
1725     obj_surface = SURFACE(dst_surface->id);
1726     out_w = obj_surface->orig_width;
1727     out_h = obj_surface->orig_height;
1728     out_wpitch = obj_surface->width;
1729     out_hpitch = obj_surface->height;
1730     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1731
1732     /* destination Y surface index 7 */
1733     i965_pp_set_surface_state(ctx, pp_context,
1734                               obj_surface->bo, 0,
1735                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1736                               7, 1);
1737
1738     /* destination UV surface index 8 */
1739     i965_pp_set_surface_state(ctx, pp_context,
1740                               obj_surface->bo, out_wpitch * out_hpitch,
1741                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1742                               8, 1);
1743
1744     /* sampler 8x8 state */
1745     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1746     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1747     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1748     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1749     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1750
1751     for (i = 0; i < 17; i++) {
1752         /* for Y channel, currently ignore */
1753         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1754         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1755         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1756         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1757         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1758         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1759         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1760         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1761         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1762         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1763         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1764         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1765         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1766         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1767         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1768         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1769         /* for U/V channel, 0.25 */
1770         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1771         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1772         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1773         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1774         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1775         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1776         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1777         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1778         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1779         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1780         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1781         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1782         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1783         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1784         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1785         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1786     }
1787
1788     sampler_8x8_state->dw136.default_sharpness_level = 0;
1789     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1790     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1791     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1792     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1793
1794     /* sampler 8x8 */
1795     dri_bo_map(pp_context->sampler_state_table.bo, True);
1796     assert(pp_context->sampler_state_table.bo->virtual);
1797     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1798     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1799
1800     /* sample_8x8 Y index 1 */
1801     index = 1;
1802     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1803     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1804     sampler_8x8[index].dw0.ief_bypass = 1;
1805     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1806     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1807     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1808     sampler_8x8[index].dw2.global_noise_estimation = 22;
1809     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1810     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1811     sampler_8x8[index].dw3.strong_edge_weight = 7;
1812     sampler_8x8[index].dw3.regular_weight = 2;
1813     sampler_8x8[index].dw3.non_edge_weight = 0;
1814     sampler_8x8[index].dw3.gain_factor = 40;
1815     sampler_8x8[index].dw4.steepness_boost = 0;
1816     sampler_8x8[index].dw4.steepness_threshold = 0;
1817     sampler_8x8[index].dw4.mr_boost = 0;
1818     sampler_8x8[index].dw4.mr_threshold = 5;
1819     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1820     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1821     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1822     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1823     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1824     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1825     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1826     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1827     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1828     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1829     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1830     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1831     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1832     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1833     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1834     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1835     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1836     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1837     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1838     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1839     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1840     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1841     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1842     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1843     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1844     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1845     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1846     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1847     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1848     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1849     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1850     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1851     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1852     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1853     sampler_8x8[index].dw13.limiter_boost = 0;
1854     sampler_8x8[index].dw13.minimum_limiter = 10;
1855     sampler_8x8[index].dw13.maximum_limiter = 11;
1856     sampler_8x8[index].dw14.clip_limiter = 130;
1857     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1858                       I915_GEM_DOMAIN_RENDER,
1859                       0,
1860                       0,
1861                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1862                       pp_context->sampler_state_table.bo_8x8);
1863
1864     /* sample_8x8 UV index 2 */
1865     index = 2;
1866     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1867     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1868     sampler_8x8[index].dw0.ief_bypass = 1;
1869     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1870     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1871     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1872     sampler_8x8[index].dw2.global_noise_estimation = 22;
1873     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1874     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1875     sampler_8x8[index].dw3.strong_edge_weight = 7;
1876     sampler_8x8[index].dw3.regular_weight = 2;
1877     sampler_8x8[index].dw3.non_edge_weight = 0;
1878     sampler_8x8[index].dw3.gain_factor = 40;
1879     sampler_8x8[index].dw4.steepness_boost = 0;
1880     sampler_8x8[index].dw4.steepness_threshold = 0;
1881     sampler_8x8[index].dw4.mr_boost = 0;
1882     sampler_8x8[index].dw4.mr_threshold = 5;
1883     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1884     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1885     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1886     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1887     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1888     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1889     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1890     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1891     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1892     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1893     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1894     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1895     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1896     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1897     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1898     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1899     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1900     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1901     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1902     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1903     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1904     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1905     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1906     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1907     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1908     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1909     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1910     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1911     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1912     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1913     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1914     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1915     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1916     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1917     sampler_8x8[index].dw13.limiter_boost = 0;
1918     sampler_8x8[index].dw13.minimum_limiter = 10;
1919     sampler_8x8[index].dw13.maximum_limiter = 11;
1920     sampler_8x8[index].dw14.clip_limiter = 130;
1921     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1922                       I915_GEM_DOMAIN_RENDER,
1923                       0,
1924                       0,
1925                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1926                       pp_context->sampler_state_table.bo_8x8);
1927
1928     dri_bo_unmap(pp_context->sampler_state_table.bo);
1929
1930     /* private function & data */
1931     pp_context->pp_x_steps = pp_avs_x_steps;
1932     pp_context->pp_y_steps = pp_avs_y_steps;
1933     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
1934
1935     pp_avs_context->dest_x = dst_rect->x;
1936     pp_avs_context->dest_y = dst_rect->y;
1937     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
1938     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1939     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
1940     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
1941     pp_avs_context->src_w = src_rect->width;
1942     pp_avs_context->src_h = src_rect->height;
1943
1944     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
1945     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1946
1947     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1948     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
1949     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
1950     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1951     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1952     pp_inline_parameter->grf6.video_step_delta = 0.0;
1953
1954     dst_surface->flags = src_surface->flags;
1955
1956     return VA_STATUS_SUCCESS;
1957 }
1958
1959 static VAStatus
1960 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1961                             const struct i965_surface *src_surface,
1962                             const VARectangle *src_rect,
1963                             struct i965_surface *dst_surface,
1964                             const VARectangle *dst_rect,
1965                             void *filter_param)
1966 {
1967     return pp_nv12_avs_initialize(ctx, pp_context,
1968                                   src_surface,
1969                                   src_rect,
1970                                   dst_surface,
1971                                   dst_rect,
1972                                   filter_param,
1973                                   1);
1974 }
1975
1976 static VAStatus
1977 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1978                              const struct i965_surface *src_surface,
1979                              const VARectangle *src_rect,
1980                              struct i965_surface *dst_surface,
1981                              const VARectangle *dst_rect,
1982                              void *filter_param)
1983 {
1984     return pp_nv12_avs_initialize(ctx, pp_context,
1985                                   src_surface,
1986                                   src_rect,
1987                                   dst_surface,
1988                                   dst_rect,
1989                                   filter_param,
1990                                   0);
1991 }
1992
1993 static int
1994 gen7_pp_avs_x_steps(void *private_context)
1995 {
1996     struct pp_avs_context *pp_avs_context = private_context;
1997
1998     return pp_avs_context->dest_w / 16;
1999 }
2000
2001 static int
2002 gen7_pp_avs_y_steps(void *private_context)
2003 {
2004     struct pp_avs_context *pp_avs_context = private_context;
2005
2006     return pp_avs_context->dest_h / 16;
2007 }
2008
2009 static int
2010 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2011 {
2012     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2013     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2014
2015     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2016     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2017     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2018     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2019
2020     return 0;
2021 }
2022
2023 static VAStatus
2024 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2025                            const struct i965_surface *src_surface,
2026                            const VARectangle *src_rect,
2027                            struct i965_surface *dst_surface,
2028                            const VARectangle *dst_rect,
2029                            void *filter_param)
2030 {
2031     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2032     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2033     struct gen7_sampler_8x8 *sampler_8x8;
2034     struct i965_sampler_8x8_state *sampler_8x8_state;
2035     int index, i;
2036     int width[3], height[3], pitch[3], offset[3];
2037
2038     /* source surface */
2039     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2040                                          width, height, pitch, offset);
2041
2042     /* destination surface */
2043     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2044                                          width, height, pitch, offset);
2045
2046     /* sampler 8x8 state */
2047     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2048     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2049     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2050     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2051     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2052
2053     for (i = 0; i < 17; i++) {
2054         /* for Y channel, currently ignore */
2055         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2056         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2057         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2058         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2059         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2060         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2061         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2062         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2063         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2064         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2065         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2066         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2067         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2068         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2069         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2070         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2071         /* for U/V channel, 0.25 */
2072         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2073         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2074         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2075         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2076         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2077         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2078         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2079         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2080         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2081         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2082         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2083         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2084         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2085         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2086         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2087         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2088     }
2089
2090     sampler_8x8_state->dw136.default_sharpness_level = 0;
2091     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2092     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2093     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2094     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2095
2096     /* sampler 8x8 */
2097     dri_bo_map(pp_context->sampler_state_table.bo, True);
2098     assert(pp_context->sampler_state_table.bo->virtual);
2099     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2100     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2101
2102     /* sample_8x8 Y index 4 */
2103     index = 4;
2104     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2105     sampler_8x8[index].dw0.global_noise_estimation = 255;
2106     sampler_8x8[index].dw0.ief_bypass = 1;
2107
2108     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2109
2110     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2111     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2112     sampler_8x8[index].dw2.r5x_coefficient = 9;
2113     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2114     sampler_8x8[index].dw2.r5c_coefficient = 3;
2115
2116     sampler_8x8[index].dw3.r3x_coefficient = 27;
2117     sampler_8x8[index].dw3.r3c_coefficient = 5;
2118     sampler_8x8[index].dw3.gain_factor = 40;
2119     sampler_8x8[index].dw3.non_edge_weight = 1;
2120     sampler_8x8[index].dw3.regular_weight = 2;
2121     sampler_8x8[index].dw3.strong_edge_weight = 7;
2122     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2123
2124     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2125                       I915_GEM_DOMAIN_RENDER,
2126                       0,
2127                       0,
2128                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2129                       pp_context->sampler_state_table.bo_8x8);
2130
2131     /* sample_8x8 UV index 8 */
2132     index = 8;
2133     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2134     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2135     sampler_8x8[index].dw0.global_noise_estimation = 255;
2136     sampler_8x8[index].dw0.ief_bypass = 1;
2137     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2138     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2139     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2140     sampler_8x8[index].dw2.r5x_coefficient = 9;
2141     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2142     sampler_8x8[index].dw2.r5c_coefficient = 3;
2143     sampler_8x8[index].dw3.r3x_coefficient = 27;
2144     sampler_8x8[index].dw3.r3c_coefficient = 5;
2145     sampler_8x8[index].dw3.gain_factor = 40;
2146     sampler_8x8[index].dw3.non_edge_weight = 1;
2147     sampler_8x8[index].dw3.regular_weight = 2;
2148     sampler_8x8[index].dw3.strong_edge_weight = 7;
2149     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2150
2151     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2152                       I915_GEM_DOMAIN_RENDER,
2153                       0,
2154                       0,
2155                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2156                       pp_context->sampler_state_table.bo_8x8);
2157
2158     /* sampler_8x8 V, index 12 */
2159     index = 12;
2160     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2161     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2162     sampler_8x8[index].dw0.global_noise_estimation = 255;
2163     sampler_8x8[index].dw0.ief_bypass = 1;
2164     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2165     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2166     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2167     sampler_8x8[index].dw2.r5x_coefficient = 9;
2168     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2169     sampler_8x8[index].dw2.r5c_coefficient = 3;
2170     sampler_8x8[index].dw3.r3x_coefficient = 27;
2171     sampler_8x8[index].dw3.r3c_coefficient = 5;
2172     sampler_8x8[index].dw3.gain_factor = 40;
2173     sampler_8x8[index].dw3.non_edge_weight = 1;
2174     sampler_8x8[index].dw3.regular_weight = 2;
2175     sampler_8x8[index].dw3.strong_edge_weight = 7;
2176     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2177
2178     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2179                       I915_GEM_DOMAIN_RENDER,
2180                       0,
2181                       0,
2182                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2183                       pp_context->sampler_state_table.bo_8x8);
2184
2185     dri_bo_unmap(pp_context->sampler_state_table.bo);
2186
2187     /* private function & data */
2188     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2189     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2190     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2191
2192     pp_avs_context->dest_x = dst_rect->x;
2193     pp_avs_context->dest_y = dst_rect->y;
2194     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2195     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2196     pp_avs_context->src_w = src_rect->width;
2197     pp_avs_context->src_h = src_rect->height;
2198
2199     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2200     dw = MAX(dw, pp_avs_context->dest_w);
2201
2202     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2203     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2204     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2205     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2206     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2207
2208     dst_surface->flags = src_surface->flags;
2209
2210     return VA_STATUS_SUCCESS;
2211 }
2212
2213 static int
2214 pp_dndi_x_steps(void *private_context)
2215 {
2216     return 1;
2217 }
2218
2219 static int
2220 pp_dndi_y_steps(void *private_context)
2221 {
2222     struct pp_dndi_context *pp_dndi_context = private_context;
2223
2224     return pp_dndi_context->dest_h / 4;
2225 }
2226
2227 static int
2228 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2229 {
2230     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2231
2232     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2233     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2234
2235     return 0;
2236 }
2237
2238 static VAStatus
2239 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2240                         const struct i965_surface *src_surface,
2241                         const VARectangle *src_rect,
2242                         struct i965_surface *dst_surface,
2243                         const VARectangle *dst_rect,
2244                         void *filter_param)
2245 {
2246     struct i965_driver_data *i965 = i965_driver_data(ctx);
2247     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2248     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2249     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2250     struct object_surface *obj_surface;
2251     struct i965_sampler_dndi *sampler_dndi;
2252     int index;
2253     int w, h;
2254     int orig_w, orig_h;
2255     int dndi_top_first = 1;
2256
2257     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2258         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2259
2260     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2261         dndi_top_first = 1;
2262     else
2263         dndi_top_first = 0;
2264
2265     /* surface */
2266     obj_surface = SURFACE(src_surface->id);
2267     orig_w = obj_surface->orig_width;
2268     orig_h = obj_surface->orig_height;
2269     w = obj_surface->width;
2270     h = obj_surface->height;
2271
2272     if (pp_context->stmm.bo == NULL) {
2273         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2274                                            "STMM surface",
2275                                            w * h,
2276                                            4096);
2277         assert(pp_context->stmm.bo);
2278     }
2279
2280     /* source UV surface index 2 */
2281     i965_pp_set_surface_state(ctx, pp_context,
2282                               obj_surface->bo, w * h,
2283                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2284                               2, 0);
2285
2286     /* source YUV surface index 4 */
2287     i965_pp_set_surface2_state(ctx, pp_context,
2288                                obj_surface->bo, 0,
2289                                orig_w, orig_h, w,
2290                                0, h,
2291                                SURFACE_FORMAT_PLANAR_420_8, 1,
2292                                4);
2293
2294     /* source STMM surface index 20 */
2295     i965_pp_set_surface_state(ctx, pp_context,
2296                               pp_context->stmm.bo, 0,
2297                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2298                               20, 1);
2299
2300     /* destination surface */
2301     obj_surface = SURFACE(dst_surface->id);
2302     orig_w = obj_surface->orig_width;
2303     orig_h = obj_surface->orig_height;
2304     w = obj_surface->width;
2305     h = obj_surface->height;
2306
2307     /* destination Y surface index 7 */
2308     i965_pp_set_surface_state(ctx, pp_context,
2309                               obj_surface->bo, 0,
2310                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2311                               7, 1);
2312
2313     /* destination UV surface index 8 */
2314     i965_pp_set_surface_state(ctx, pp_context,
2315                               obj_surface->bo, w * h,
2316                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2317                               8, 1);
2318     /* sampler dndi */
2319     dri_bo_map(pp_context->sampler_state_table.bo, True);
2320     assert(pp_context->sampler_state_table.bo->virtual);
2321     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2322     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2323
2324     /* sample dndi index 1 */
2325     index = 0;
2326     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2327     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2328     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2329     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2330
2331     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2332     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2333     sampler_dndi[index].dw1.stmm_c2 = 1;
2334     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2335     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2336
2337     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2338     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2339     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2340     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2341
2342     sampler_dndi[index].dw3.maximum_stmm = 128;
2343     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2344     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2345     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2346     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2347
2348     sampler_dndi[index].dw4.sdi_delta = 8;
2349     sampler_dndi[index].dw4.sdi_threshold = 128;
2350     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2351     sampler_dndi[index].dw4.stmm_shift_up = 0;
2352     sampler_dndi[index].dw4.stmm_shift_down = 0;
2353     sampler_dndi[index].dw4.minimum_stmm = 0;
2354
2355     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2356     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2357     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2358     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2359
2360     sampler_dndi[index].dw6.dn_enable = 1;
2361     sampler_dndi[index].dw6.di_enable = 1;
2362     sampler_dndi[index].dw6.di_partial = 0;
2363     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2364     sampler_dndi[index].dw6.dndi_stream_id = 0;
2365     sampler_dndi[index].dw6.dndi_first_frame = 1;
2366     sampler_dndi[index].dw6.progressive_dn = 0;
2367     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2368     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2369     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2370
2371     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2372     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2373     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2374     sampler_dndi[index].dw7.column_width_minus1 = 0;
2375
2376     dri_bo_unmap(pp_context->sampler_state_table.bo);
2377
2378     /* private function & data */
2379     pp_context->pp_x_steps = pp_dndi_x_steps;
2380     pp_context->pp_y_steps = pp_dndi_y_steps;
2381     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2382
2383     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2384     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2385     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2386     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2387
2388     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2389     pp_inline_parameter->grf5.number_blocks = w / 16;
2390     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2391     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2392
2393     pp_dndi_context->dest_w = w;
2394     pp_dndi_context->dest_h = h;
2395
2396     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2397
2398     return VA_STATUS_SUCCESS;
2399 }
2400
2401 static int
2402 pp_dn_x_steps(void *private_context)
2403 {
2404     return 1;
2405 }
2406
2407 static int
2408 pp_dn_y_steps(void *private_context)
2409 {
2410     struct pp_dn_context *pp_dn_context = private_context;
2411
2412     return pp_dn_context->dest_h / 8;
2413 }
2414
2415 static int
2416 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2417 {
2418     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2419
2420     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2421     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2422
2423     return 0;
2424 }
2425
2426 static VAStatus
2427 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2428                       const struct i965_surface *src_surface,
2429                       const VARectangle *src_rect,
2430                       struct i965_surface *dst_surface,
2431                       const VARectangle *dst_rect,
2432                       void *filter_param)
2433 {
2434     struct i965_driver_data *i965 = i965_driver_data(ctx);
2435     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2436     struct object_surface *obj_surface;
2437     struct i965_sampler_dndi *sampler_dndi;
2438     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2439     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2440     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2441     int index;
2442     int w, h;
2443     int orig_w, orig_h;
2444     int dn_strength = 15;
2445     int dndi_top_first = 1;
2446     int dn_progressive = 0;
2447
2448     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2449         dndi_top_first = 1;
2450         dn_progressive = 1;
2451     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2452         dndi_top_first = 1;
2453         dn_progressive = 0;
2454     } else {
2455         dndi_top_first = 0;
2456         dn_progressive = 0;
2457     }
2458
2459     if (dn_filter_param) {
2460         float value = dn_filter_param->value;
2461
2462         if (value > 1.0)
2463             value = 1.0;
2464
2465         if (value < 0.0)
2466             value = 0.0;
2467
2468         dn_strength = (int)(value * 31.0F);
2469     }
2470
2471     /* surface */
2472     obj_surface = SURFACE(src_surface->id);
2473     orig_w = obj_surface->orig_width;
2474     orig_h = obj_surface->orig_height;
2475     w = obj_surface->width;
2476     h = obj_surface->height;
2477
2478     if (pp_context->stmm.bo == NULL) {
2479         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2480                                            "STMM surface",
2481                                            w * h,
2482                                            4096);
2483         assert(pp_context->stmm.bo);
2484     }
2485
2486     /* source UV surface index 2 */
2487     i965_pp_set_surface_state(ctx, pp_context,
2488                               obj_surface->bo, w * h,
2489                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2490                               2, 0);
2491
2492     /* source YUV surface index 4 */
2493     i965_pp_set_surface2_state(ctx, pp_context,
2494                                obj_surface->bo, 0,
2495                                orig_w, orig_h, w,
2496                                0, h,
2497                                SURFACE_FORMAT_PLANAR_420_8, 1,
2498                                4);
2499
2500     /* source STMM surface index 20 */
2501     i965_pp_set_surface_state(ctx, pp_context,
2502                               pp_context->stmm.bo, 0,
2503                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2504                               20, 1);
2505
2506     /* destination surface */
2507     obj_surface = SURFACE(dst_surface->id);
2508     orig_w = obj_surface->orig_width;
2509     orig_h = obj_surface->orig_height;
2510     w = obj_surface->width;
2511     h = obj_surface->height;
2512
2513     /* destination Y surface index 7 */
2514     i965_pp_set_surface_state(ctx, pp_context,
2515                               obj_surface->bo, 0,
2516                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2517                               7, 1);
2518
2519     /* destination UV surface index 8 */
2520     i965_pp_set_surface_state(ctx, pp_context,
2521                               obj_surface->bo, w * h,
2522                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2523                               8, 1);
2524     /* sampler dn */
2525     dri_bo_map(pp_context->sampler_state_table.bo, True);
2526     assert(pp_context->sampler_state_table.bo->virtual);
2527     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2528     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2529
2530     /* sample dndi index 1 */
2531     index = 0;
2532     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2533     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2534     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2535     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2536
2537     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2538     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2539     sampler_dndi[index].dw1.stmm_c2 = 0;
2540     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2541     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2542
2543     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2544     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2545     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2546     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2547
2548     sampler_dndi[index].dw3.maximum_stmm = 128;
2549     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2550     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2551     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2552     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2553
2554     sampler_dndi[index].dw4.sdi_delta = 8;
2555     sampler_dndi[index].dw4.sdi_threshold = 128;
2556     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2557     sampler_dndi[index].dw4.stmm_shift_up = 0;
2558     sampler_dndi[index].dw4.stmm_shift_down = 0;
2559     sampler_dndi[index].dw4.minimum_stmm = 0;
2560
2561     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2562     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2563     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2564     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2565
2566     sampler_dndi[index].dw6.dn_enable = 1;
2567     sampler_dndi[index].dw6.di_enable = 0;
2568     sampler_dndi[index].dw6.di_partial = 0;
2569     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2570     sampler_dndi[index].dw6.dndi_stream_id = 1;
2571     sampler_dndi[index].dw6.dndi_first_frame = 1;
2572     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2573     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2574     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2575     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2576
2577     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2578     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2579     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2580     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2581
2582     dri_bo_unmap(pp_context->sampler_state_table.bo);
2583
2584     /* private function & data */
2585     pp_context->pp_x_steps = pp_dn_x_steps;
2586     pp_context->pp_y_steps = pp_dn_y_steps;
2587     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2588
2589     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2590     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2591     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2592     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2593
2594     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2595     pp_inline_parameter->grf5.number_blocks = w / 16;
2596     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2597     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2598
2599     pp_dn_context->dest_w = w;
2600     pp_dn_context->dest_h = h;
2601
2602     dst_surface->flags = src_surface->flags;
2603
2604     return VA_STATUS_SUCCESS;
2605 }
2606
2607 static int
2608 gen7_pp_dndi_x_steps(void *private_context)
2609 {
2610     struct pp_dndi_context *pp_dndi_context = private_context;
2611
2612     return pp_dndi_context->dest_w / 16;
2613 }
2614
2615 static int
2616 gen7_pp_dndi_y_steps(void *private_context)
2617 {
2618     struct pp_dndi_context *pp_dndi_context = private_context;
2619
2620     return pp_dndi_context->dest_h / 4;
2621 }
2622
2623 static int
2624 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2625 {
2626     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2627
2628     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2629     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2630
2631     return 0;
2632 }
2633
2634 static VAStatus
2635 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2636                              const struct i965_surface *src_surface,
2637                              const VARectangle *src_rect,
2638                              struct i965_surface *dst_surface,
2639                              const VARectangle *dst_rect,
2640                              void *filter_param)
2641 {
2642     struct i965_driver_data *i965 = i965_driver_data(ctx);
2643     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2644     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2645     struct object_surface *obj_surface;
2646     struct gen7_sampler_dndi *sampler_dndi;
2647     int index;
2648     int w, h;
2649     int orig_w, orig_h;
2650     int dndi_top_first = 1;
2651
2652     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2653         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2654
2655     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2656         dndi_top_first = 1;
2657     else
2658         dndi_top_first = 0;
2659
2660     /* surface */
2661     obj_surface = SURFACE(src_surface->id);
2662     orig_w = obj_surface->orig_width;
2663     orig_h = obj_surface->orig_height;
2664     w = obj_surface->width;
2665     h = obj_surface->height;
2666
2667     if (pp_context->stmm.bo == NULL) {
2668         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2669                                            "STMM surface",
2670                                            w * h,
2671                                            4096);
2672         assert(pp_context->stmm.bo);
2673     }
2674
2675     /* source UV surface index 1 */
2676     gen7_pp_set_surface_state(ctx, pp_context,
2677                               obj_surface->bo, w * h,
2678                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2679                               1, 0);
2680
2681     /* source YUV surface index 3 */
2682     gen7_pp_set_surface2_state(ctx, pp_context,
2683                                obj_surface->bo, 0,
2684                                orig_w, orig_h, w,
2685                                0, h,
2686                                SURFACE_FORMAT_PLANAR_420_8, 1,
2687                                3);
2688
2689     /* source (temporal reference) YUV surface index 4 */
2690     gen7_pp_set_surface2_state(ctx, pp_context,
2691                                obj_surface->bo, 0,
2692                                orig_w, orig_h, w,
2693                                0, h,
2694                                SURFACE_FORMAT_PLANAR_420_8, 1,
2695                                4);
2696
2697     /* STMM / History Statistics input surface, index 5 */
2698     gen7_pp_set_surface_state(ctx, pp_context,
2699                               pp_context->stmm.bo, 0,
2700                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2701                               5, 1);
2702
2703     /* destination surface */
2704     obj_surface = SURFACE(dst_surface->id);
2705     orig_w = obj_surface->orig_width;
2706     orig_h = obj_surface->orig_height;
2707     w = obj_surface->width;
2708     h = obj_surface->height;
2709
2710     /* destination(Previous frame) Y surface index 27 */
2711     gen7_pp_set_surface_state(ctx, pp_context,
2712                               obj_surface->bo, 0,
2713                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2714                               27, 1);
2715
2716     /* destination(Previous frame) UV surface index 28 */
2717     gen7_pp_set_surface_state(ctx, pp_context,
2718                               obj_surface->bo, w * h,
2719                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2720                               28, 1);
2721
2722     /* destination(Current frame) Y surface index 30 */
2723     gen7_pp_set_surface_state(ctx, pp_context,
2724                               obj_surface->bo, 0,
2725                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2726                               30, 1);
2727
2728     /* destination(Current frame) UV surface index 31 */
2729     gen7_pp_set_surface_state(ctx, pp_context,
2730                               obj_surface->bo, w * h,
2731                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2732                               31, 1);
2733
2734     /* STMM output surface, index 33 */
2735     gen7_pp_set_surface_state(ctx, pp_context,
2736                               pp_context->stmm.bo, 0,
2737                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2738                               33, 1);
2739
2740
2741     /* sampler dndi */
2742     dri_bo_map(pp_context->sampler_state_table.bo, True);
2743     assert(pp_context->sampler_state_table.bo->virtual);
2744     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2745     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2746
2747     /* sample dndi index 0 */
2748     index = 0;
2749     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2750     sampler_dndi[index].dw0.dnmh_delt = 8;
2751     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2752     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2753     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2754     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2755
2756     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2757     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2758     sampler_dndi[index].dw1.stmm_c2 = 0;
2759     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2760     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2761
2762     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2763     sampler_dndi[index].dw2.bne_edge_th = 1;
2764     sampler_dndi[index].dw2.smooth_mv_th = 0;
2765     sampler_dndi[index].dw2.sad_tight_th = 5;
2766     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2767     sampler_dndi[index].dw2.good_neighbor_th = 4;
2768
2769     sampler_dndi[index].dw3.maximum_stmm = 128;
2770     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2771     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2772     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2773     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2774
2775     sampler_dndi[index].dw4.sdi_delta = 8;
2776     sampler_dndi[index].dw4.sdi_threshold = 128;
2777     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2778     sampler_dndi[index].dw4.stmm_shift_up = 0;
2779     sampler_dndi[index].dw4.stmm_shift_down = 0;
2780     sampler_dndi[index].dw4.minimum_stmm = 0;
2781
2782     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2783     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2784     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2785     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2786
2787     sampler_dndi[index].dw6.dn_enable = 0;
2788     sampler_dndi[index].dw6.di_enable = 1;
2789     sampler_dndi[index].dw6.di_partial = 0;
2790     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2791     sampler_dndi[index].dw6.dndi_stream_id = 1;
2792     sampler_dndi[index].dw6.dndi_first_frame = 1;
2793     sampler_dndi[index].dw6.progressive_dn = 0;
2794     sampler_dndi[index].dw6.mcdi_enable = 0;
2795     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2796     sampler_dndi[index].dw6.cat_th1 = 0;
2797     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2798     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2799
2800     sampler_dndi[index].dw7.sad_tha = 5;
2801     sampler_dndi[index].dw7.sad_thb = 10;
2802     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2803     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2804     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2805     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2806     sampler_dndi[index].dw7.neighborpixel_th = 10;
2807     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2808
2809     dri_bo_unmap(pp_context->sampler_state_table.bo);
2810
2811     /* private function & data */
2812     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2813     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2814     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2815
2816     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2817     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2818     pp_static_parameter->grf1.di_top_field_first = 0;
2819     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2820
2821     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2822     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2823     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2824
2825     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2826     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2827
2828     pp_dndi_context->dest_w = w;
2829     pp_dndi_context->dest_h = h;
2830
2831     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2832
2833     return VA_STATUS_SUCCESS;
2834 }
2835
2836 static int
2837 gen7_pp_dn_x_steps(void *private_context)
2838 {
2839     return 1;
2840 }
2841
2842 static int
2843 gen7_pp_dn_y_steps(void *private_context)
2844 {
2845     struct pp_dn_context *pp_dn_context = private_context;
2846
2847     return pp_dn_context->dest_h / 4;
2848 }
2849
2850 static int
2851 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2852 {
2853     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2854
2855     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2856     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2857
2858     return 0;
2859 }
2860
2861 static VAStatus
2862 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2863                            const struct i965_surface *src_surface,
2864                            const VARectangle *src_rect,
2865                            struct i965_surface *dst_surface,
2866                            const VARectangle *dst_rect,
2867                            void *filter_param)
2868 {
2869     struct i965_driver_data *i965 = i965_driver_data(ctx);
2870     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2871     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2872     struct object_surface *obj_surface;
2873     struct gen7_sampler_dndi *sampler_dn;
2874     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2875     int index;
2876     int w, h;
2877     int orig_w, orig_h;
2878     int dn_strength = 15;
2879     int dndi_top_first = 1;
2880     int dn_progressive = 0;
2881
2882     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2883         dndi_top_first = 1;
2884         dn_progressive = 1;
2885     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2886         dndi_top_first = 1;
2887         dn_progressive = 0;
2888     } else {
2889         dndi_top_first = 0;
2890         dn_progressive = 0;
2891     }
2892
2893     if (dn_filter_param) {
2894         float value = dn_filter_param->value;
2895
2896         if (value > 1.0)
2897             value = 1.0;
2898
2899         if (value < 0.0)
2900             value = 0.0;
2901
2902         dn_strength = (int)(value * 31.0F);
2903     }
2904
2905     /* surface */
2906     obj_surface = SURFACE(src_surface->id);
2907     orig_w = obj_surface->orig_width;
2908     orig_h = obj_surface->orig_height;
2909     w = obj_surface->width;
2910     h = obj_surface->height;
2911
2912     if (pp_context->stmm.bo == NULL) {
2913         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2914                                            "STMM surface",
2915                                            w * h,
2916                                            4096);
2917         assert(pp_context->stmm.bo);
2918     }
2919
2920     /* source UV surface index 1 */
2921     gen7_pp_set_surface_state(ctx, pp_context,
2922                               obj_surface->bo, w * h,
2923                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2924                               1, 0);
2925
2926     /* source YUV surface index 3 */
2927     gen7_pp_set_surface2_state(ctx, pp_context,
2928                                obj_surface->bo, 0,
2929                                orig_w, orig_h, w,
2930                                0, h,
2931                                SURFACE_FORMAT_PLANAR_420_8, 1,
2932                                3);
2933
2934     /* source STMM surface index 5 */
2935     gen7_pp_set_surface_state(ctx, pp_context,
2936                               pp_context->stmm.bo, 0,
2937                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2938                               5, 1);
2939
2940     /* destination surface */
2941     obj_surface = SURFACE(dst_surface->id);
2942     orig_w = obj_surface->orig_width;
2943     orig_h = obj_surface->orig_height;
2944     w = obj_surface->width;
2945     h = obj_surface->height;
2946
2947     /* destination Y surface index 7 */
2948     gen7_pp_set_surface_state(ctx, pp_context,
2949                               obj_surface->bo, 0,
2950                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2951                               7, 1);
2952
2953     /* destination UV surface index 8 */
2954     gen7_pp_set_surface_state(ctx, pp_context,
2955                               obj_surface->bo, w * h,
2956                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2957                               8, 1);
2958     /* sampler dn */
2959     dri_bo_map(pp_context->sampler_state_table.bo, True);
2960     assert(pp_context->sampler_state_table.bo->virtual);
2961     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
2962     sampler_dn = pp_context->sampler_state_table.bo->virtual;
2963
2964     /* sample dn index 1 */
2965     index = 0;
2966     sampler_dn[index].dw0.denoise_asd_threshold = 0;
2967     sampler_dn[index].dw0.dnmh_delt = 8;
2968     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
2969     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
2970     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
2971     sampler_dn[index].dw0.denoise_stad_threshold = 0;
2972
2973     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2974     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
2975     sampler_dn[index].dw1.stmm_c2 = 0;
2976     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
2977     sampler_dn[index].dw1.temporal_difference_threshold = 16;
2978
2979     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2980     sampler_dn[index].dw2.bne_edge_th = 1;
2981     sampler_dn[index].dw2.smooth_mv_th = 0;
2982     sampler_dn[index].dw2.sad_tight_th = 5;
2983     sampler_dn[index].dw2.cat_slope_minus1 = 9;
2984     sampler_dn[index].dw2.good_neighbor_th = 4;
2985
2986     sampler_dn[index].dw3.maximum_stmm = 128;
2987     sampler_dn[index].dw3.multipler_for_vecm = 2;
2988     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2989     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2990     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
2991
2992     sampler_dn[index].dw4.sdi_delta = 8;
2993     sampler_dn[index].dw4.sdi_threshold = 128;
2994     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2995     sampler_dn[index].dw4.stmm_shift_up = 0;
2996     sampler_dn[index].dw4.stmm_shift_down = 0;
2997     sampler_dn[index].dw4.minimum_stmm = 0;
2998
2999     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3000     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3001     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3002     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3003
3004     sampler_dn[index].dw6.dn_enable = 1;
3005     sampler_dn[index].dw6.di_enable = 0;
3006     sampler_dn[index].dw6.di_partial = 0;
3007     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3008     sampler_dn[index].dw6.dndi_stream_id = 1;
3009     sampler_dn[index].dw6.dndi_first_frame = 1;
3010     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3011     sampler_dn[index].dw6.mcdi_enable = 0;
3012     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3013     sampler_dn[index].dw6.cat_th1 = 0;
3014     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3015     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3016
3017     sampler_dn[index].dw7.sad_tha = 5;
3018     sampler_dn[index].dw7.sad_thb = 10;
3019     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3020     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3021     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3022     sampler_dn[index].dw7.vdi_walker_enable = 0;
3023     sampler_dn[index].dw7.neighborpixel_th = 10;
3024     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3025
3026     dri_bo_unmap(pp_context->sampler_state_table.bo);
3027
3028     /* private function & data */
3029     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3030     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3031     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3032
3033     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3034     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3035     pp_static_parameter->grf1.di_top_field_first = 0;
3036     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3037
3038     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3039     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3040     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3041
3042     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3043     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3044
3045     pp_dn_context->dest_w = w;
3046     pp_dn_context->dest_h = h;
3047
3048     dst_surface->flags = src_surface->flags;
3049
3050     return VA_STATUS_SUCCESS;
3051 }
3052
3053 // update u/v offset when the surface format are packed yuv
3054 static void i965_update_src_surface_uv_offset(
3055     VADriverContextP    ctx,
3056     struct i965_post_processing_context *pp_context,
3057     const struct i965_surface *surface)
3058 {
3059     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3060     int fourcc = pp_get_surface_fourcc(ctx, surface);
3061
3062     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3063         pp_static_parameter->grf1.source_packed_u_offset = 1;
3064         pp_static_parameter->grf1.source_packed_v_offset = 3;
3065     }
3066     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3067         pp_static_parameter->grf1.source_packed_y_offset = 1;
3068         pp_static_parameter->grf1.source_packed_v_offset = 2;
3069     }
3070
3071 }
3072
3073 static void i965_update_dst_surface_uv_offset(
3074     VADriverContextP    ctx,
3075     struct i965_post_processing_context *pp_context,
3076     const struct i965_surface *surface)
3077 {
3078     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3079     int fourcc = pp_get_surface_fourcc(ctx, surface);
3080
3081     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3082         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
3083         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
3084     }
3085     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3086         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
3087         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
3088     }
3089
3090 }
3091
3092 static VAStatus
3093 ironlake_pp_initialize(
3094     VADriverContextP   ctx,
3095     struct i965_post_processing_context *pp_context,
3096     const struct i965_surface *src_surface,
3097     const VARectangle *src_rect,
3098     struct i965_surface *dst_surface,
3099     const VARectangle *dst_rect,
3100     int                pp_index,
3101     void *filter_param
3102 )
3103 {
3104     VAStatus va_status;
3105     struct i965_driver_data *i965 = i965_driver_data(ctx);
3106     struct pp_module *pp_module;
3107     dri_bo *bo;
3108     int static_param_size, inline_param_size;
3109
3110     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3111     bo = dri_bo_alloc(i965->intel.bufmgr,
3112                       "surface state & binding table",
3113                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3114                       4096);
3115     assert(bo);
3116     pp_context->surface_state_binding_table.bo = bo;
3117
3118     dri_bo_unreference(pp_context->curbe.bo);
3119     bo = dri_bo_alloc(i965->intel.bufmgr,
3120                       "constant buffer",
3121                       4096,
3122                       4096);
3123     assert(bo);
3124     pp_context->curbe.bo = bo;
3125
3126     dri_bo_unreference(pp_context->idrt.bo);
3127     bo = dri_bo_alloc(i965->intel.bufmgr,
3128                       "interface discriptor",
3129                       sizeof(struct i965_interface_descriptor),
3130                       4096);
3131     assert(bo);
3132     pp_context->idrt.bo = bo;
3133     pp_context->idrt.num_interface_descriptors = 0;
3134
3135     dri_bo_unreference(pp_context->sampler_state_table.bo);
3136     bo = dri_bo_alloc(i965->intel.bufmgr,
3137                       "sampler state table",
3138                       4096,
3139                       4096);
3140     assert(bo);
3141     dri_bo_map(bo, True);
3142     memset(bo->virtual, 0, bo->size);
3143     dri_bo_unmap(bo);
3144     pp_context->sampler_state_table.bo = bo;
3145
3146     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3147     bo = dri_bo_alloc(i965->intel.bufmgr,
3148                       "sampler 8x8 state ",
3149                       4096,
3150                       4096);
3151     assert(bo);
3152     pp_context->sampler_state_table.bo_8x8 = bo;
3153
3154     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3155     bo = dri_bo_alloc(i965->intel.bufmgr,
3156                       "sampler 8x8 state ",
3157                       4096,
3158                       4096);
3159     assert(bo);
3160     pp_context->sampler_state_table.bo_8x8_uv = bo;
3161
3162     dri_bo_unreference(pp_context->vfe_state.bo);
3163     bo = dri_bo_alloc(i965->intel.bufmgr,
3164                       "vfe state",
3165                       sizeof(struct i965_vfe_state),
3166                       4096);
3167     assert(bo);
3168     pp_context->vfe_state.bo = bo;
3169
3170     if (IS_GEN7(i965->intel.device_id)) {
3171         static_param_size = sizeof(struct gen7_pp_static_parameter);
3172         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3173     } else {
3174         static_param_size = sizeof(struct pp_static_parameter);
3175         inline_param_size = sizeof(struct pp_inline_parameter);
3176     }
3177
3178     memset(pp_context->pp_static_parameter, 0, static_param_size);
3179     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3180
3181     // update u/v offset for packed yuv
3182     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3183     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3184
3185     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3186     pp_context->current_pp = pp_index;
3187     pp_module = &pp_context->pp_modules[pp_index];
3188
3189     if (pp_module->initialize)
3190         va_status = pp_module->initialize(ctx, pp_context,
3191                                           src_surface,
3192                                           src_rect,
3193                                           dst_surface,
3194                                           dst_rect,
3195                                           filter_param);
3196     else
3197         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3198
3199     return va_status;
3200 }
3201
3202 static VAStatus
3203 ironlake_post_processing(
3204     VADriverContextP   ctx,
3205     struct i965_post_processing_context *pp_context,
3206     const struct i965_surface *src_surface,
3207     const VARectangle *src_rect,
3208     struct i965_surface *dst_surface,
3209     const VARectangle *dst_rect,
3210     int                pp_index,
3211     void *filter_param
3212 )
3213 {
3214     VAStatus va_status;
3215
3216     va_status = ironlake_pp_initialize(ctx, pp_context,
3217                                        src_surface,
3218                                        src_rect,
3219                                        dst_surface,
3220                                        dst_rect,
3221                                        pp_index,
3222                                        filter_param);
3223
3224     if (va_status == VA_STATUS_SUCCESS) {
3225         ironlake_pp_states_setup(ctx, pp_context);
3226         ironlake_pp_pipeline_setup(ctx, pp_context);
3227     }
3228
3229     return va_status;
3230 }
3231
3232 static VAStatus
3233 gen6_pp_initialize(
3234     VADriverContextP   ctx,
3235     struct i965_post_processing_context *pp_context,
3236     const struct i965_surface *src_surface,
3237     const VARectangle *src_rect,
3238     struct i965_surface *dst_surface,
3239     const VARectangle *dst_rect,
3240     int                pp_index,
3241     void *filter_param
3242 )
3243 {
3244     VAStatus va_status;
3245     struct i965_driver_data *i965 = i965_driver_data(ctx);
3246     struct pp_module *pp_module;
3247     dri_bo *bo;
3248     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3249     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3250
3251     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3252     bo = dri_bo_alloc(i965->intel.bufmgr,
3253                       "surface state & binding table",
3254                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3255                       4096);
3256     assert(bo);
3257     pp_context->surface_state_binding_table.bo = bo;
3258
3259     dri_bo_unreference(pp_context->curbe.bo);
3260     bo = dri_bo_alloc(i965->intel.bufmgr,
3261                       "constant buffer",
3262                       4096,
3263                       4096);
3264     assert(bo);
3265     pp_context->curbe.bo = bo;
3266
3267     dri_bo_unreference(pp_context->idrt.bo);
3268     bo = dri_bo_alloc(i965->intel.bufmgr,
3269                       "interface discriptor",
3270                       sizeof(struct gen6_interface_descriptor_data),
3271                       4096);
3272     assert(bo);
3273     pp_context->idrt.bo = bo;
3274     pp_context->idrt.num_interface_descriptors = 0;
3275
3276     dri_bo_unreference(pp_context->sampler_state_table.bo);
3277     bo = dri_bo_alloc(i965->intel.bufmgr,
3278                       "sampler state table",
3279                       4096,
3280                       4096);
3281     assert(bo);
3282     dri_bo_map(bo, True);
3283     memset(bo->virtual, 0, bo->size);
3284     dri_bo_unmap(bo);
3285     pp_context->sampler_state_table.bo = bo;
3286
3287     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3288     bo = dri_bo_alloc(i965->intel.bufmgr,
3289                       "sampler 8x8 state ",
3290                       4096,
3291                       4096);
3292     assert(bo);
3293     pp_context->sampler_state_table.bo_8x8 = bo;
3294
3295     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3296     bo = dri_bo_alloc(i965->intel.bufmgr,
3297                       "sampler 8x8 state ",
3298                       4096,
3299                       4096);
3300     assert(bo);
3301     pp_context->sampler_state_table.bo_8x8_uv = bo;
3302
3303     dri_bo_unreference(pp_context->vfe_state.bo);
3304     bo = dri_bo_alloc(i965->intel.bufmgr,
3305                       "vfe state",
3306                       sizeof(struct i965_vfe_state),
3307                       4096);
3308     assert(bo);
3309     pp_context->vfe_state.bo = bo;
3310
3311     memset(pp_static_parameter, 0, sizeof(*pp_static_parameter));
3312     memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter));
3313
3314     // update u/v offset for packed yuv
3315     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3316     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3317
3318     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3319     pp_context->current_pp = pp_index;
3320     pp_module = &pp_context->pp_modules[pp_index];
3321
3322     if (pp_module->initialize)
3323         va_status = pp_module->initialize(ctx, pp_context,
3324                                           src_surface,
3325                                           src_rect,
3326                                           dst_surface,
3327                                           dst_rect,
3328                                           filter_param);
3329     else
3330         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3331
3332     return va_status;
3333 }
3334
3335 static void
3336 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3337                                    struct i965_post_processing_context *pp_context)
3338 {
3339     struct i965_driver_data *i965 = i965_driver_data(ctx);
3340     struct gen6_interface_descriptor_data *desc;
3341     dri_bo *bo;
3342     int pp_index = pp_context->current_pp;
3343
3344     bo = pp_context->idrt.bo;
3345     dri_bo_map(bo, True);
3346     assert(bo->virtual);
3347     desc = bo->virtual;
3348     memset(desc, 0, sizeof(*desc));
3349     desc->desc0.kernel_start_pointer =
3350         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3351     desc->desc1.single_program_flow = 1;
3352     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3353     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3354     desc->desc2.sampler_state_pointer =
3355         pp_context->sampler_state_table.bo->offset >> 5;
3356     desc->desc3.binding_table_entry_count = 0;
3357     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3358     desc->desc4.constant_urb_entry_read_offset = 0;
3359
3360     if (IS_GEN7(i965->intel.device_id))
3361         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3362     else
3363         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3364
3365     dri_bo_emit_reloc(bo,
3366                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3367                       0,
3368                       offsetof(struct gen6_interface_descriptor_data, desc0),
3369                       pp_context->pp_modules[pp_index].kernel.bo);
3370
3371     dri_bo_emit_reloc(bo,
3372                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3373                       desc->desc2.sampler_count << 2,
3374                       offsetof(struct gen6_interface_descriptor_data, desc2),
3375                       pp_context->sampler_state_table.bo);
3376
3377     dri_bo_unmap(bo);
3378     pp_context->idrt.num_interface_descriptors++;
3379 }
3380
3381 static void
3382 gen6_pp_upload_constants(VADriverContextP ctx,
3383                          struct i965_post_processing_context *pp_context)
3384 {
3385     struct i965_driver_data *i965 = i965_driver_data(ctx);
3386     unsigned char *constant_buffer;
3387     int param_size;
3388
3389     assert(sizeof(struct pp_static_parameter) == 128);
3390     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3391
3392     if (IS_GEN7(i965->intel.device_id))
3393         param_size = sizeof(struct gen7_pp_static_parameter);
3394     else
3395         param_size = sizeof(struct pp_static_parameter);
3396
3397     dri_bo_map(pp_context->curbe.bo, 1);
3398     assert(pp_context->curbe.bo->virtual);
3399     constant_buffer = pp_context->curbe.bo->virtual;
3400     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3401     dri_bo_unmap(pp_context->curbe.bo);
3402 }
3403
3404 static void
3405 gen6_pp_states_setup(VADriverContextP ctx,
3406                      struct i965_post_processing_context *pp_context)
3407 {
3408     gen6_pp_interface_descriptor_table(ctx, pp_context);
3409     gen6_pp_upload_constants(ctx, pp_context);
3410 }
3411
3412 static void
3413 gen6_pp_pipeline_select(VADriverContextP ctx,
3414                         struct i965_post_processing_context *pp_context)
3415 {
3416     struct intel_batchbuffer *batch = pp_context->batch;
3417
3418     BEGIN_BATCH(batch, 1);
3419     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3420     ADVANCE_BATCH(batch);
3421 }
3422
3423 static void
3424 gen6_pp_state_base_address(VADriverContextP ctx,
3425                            struct i965_post_processing_context *pp_context)
3426 {
3427     struct intel_batchbuffer *batch = pp_context->batch;
3428
3429     BEGIN_BATCH(batch, 10);
3430     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3431     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3432     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3433     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3434     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3435     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3436     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3437     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3438     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3439     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3440     ADVANCE_BATCH(batch);
3441 }
3442
3443 static void
3444 gen6_pp_vfe_state(VADriverContextP ctx,
3445                   struct i965_post_processing_context *pp_context)
3446 {
3447     struct intel_batchbuffer *batch = pp_context->batch;
3448
3449     BEGIN_BATCH(batch, 8);
3450     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3451     OUT_BATCH(batch, 0);
3452     OUT_BATCH(batch,
3453               (pp_context->urb.num_vfe_entries - 1) << 16 |
3454               pp_context->urb.num_vfe_entries << 8);
3455     OUT_BATCH(batch, 0);
3456     OUT_BATCH(batch,
3457               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3458               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3459     OUT_BATCH(batch, 0);
3460     OUT_BATCH(batch, 0);
3461     OUT_BATCH(batch, 0);
3462     ADVANCE_BATCH(batch);
3463 }
3464
3465 static void
3466 gen6_pp_curbe_load(VADriverContextP ctx,
3467                    struct i965_post_processing_context *pp_context)
3468 {
3469     struct intel_batchbuffer *batch = pp_context->batch;
3470
3471     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3472
3473     BEGIN_BATCH(batch, 4);
3474     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3475     OUT_BATCH(batch, 0);
3476     OUT_BATCH(batch,
3477               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3478     OUT_RELOC(batch,
3479               pp_context->curbe.bo,
3480               I915_GEM_DOMAIN_INSTRUCTION, 0,
3481               0);
3482     ADVANCE_BATCH(batch);
3483 }
3484
3485 static void
3486 gen6_interface_descriptor_load(VADriverContextP ctx,
3487                                struct i965_post_processing_context *pp_context)
3488 {
3489     struct intel_batchbuffer *batch = pp_context->batch;
3490
3491     BEGIN_BATCH(batch, 4);
3492     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3493     OUT_BATCH(batch, 0);
3494     OUT_BATCH(batch,
3495               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3496     OUT_RELOC(batch,
3497               pp_context->idrt.bo,
3498               I915_GEM_DOMAIN_INSTRUCTION, 0,
3499               0);
3500     ADVANCE_BATCH(batch);
3501 }
3502
3503 static void
3504 gen6_pp_object_walker(VADriverContextP ctx,
3505                       struct i965_post_processing_context *pp_context)
3506 {
3507     struct i965_driver_data *i965 = i965_driver_data(ctx);
3508     struct intel_batchbuffer *batch = pp_context->batch;
3509     int x, x_steps, y, y_steps;
3510     int param_size, command_length_in_dws;
3511     dri_bo *command_buffer;
3512     unsigned int *command_ptr;
3513
3514     if (IS_GEN7(i965->intel.device_id))
3515         param_size = sizeof(struct gen7_pp_inline_parameter);
3516     else
3517         param_size = sizeof(struct pp_inline_parameter);
3518
3519     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3520     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3521     command_length_in_dws = 6 + (param_size >> 2);
3522     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3523                                   "command objects buffer",
3524                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3525                                   4096);
3526
3527     dri_bo_map(command_buffer, 1);
3528     command_ptr = command_buffer->virtual;
3529
3530     for (y = 0; y < y_steps; y++) {
3531         for (x = 0; x < x_steps; x++) {
3532             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3533                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3534                 *command_ptr++ = 0;
3535                 *command_ptr++ = 0;
3536                 *command_ptr++ = 0;
3537                 *command_ptr++ = 0;
3538                 *command_ptr++ = 0;
3539                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3540                 command_ptr += (param_size >> 2);
3541             }
3542         }
3543     }
3544
3545     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3546         *command_ptr++ = 0;
3547
3548     *command_ptr = MI_BATCH_BUFFER_END;
3549
3550     dri_bo_unmap(command_buffer);
3551
3552     BEGIN_BATCH(batch, 2);
3553     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3554     OUT_RELOC(batch, command_buffer,
3555               I915_GEM_DOMAIN_COMMAND, 0,
3556               0);
3557     ADVANCE_BATCH(batch);
3558
3559     dri_bo_unreference(command_buffer);
3560
3561     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3562      * will cause control to pass back to ring buffer
3563      */
3564     intel_batchbuffer_end_atomic(batch);
3565     intel_batchbuffer_flush(batch);
3566     intel_batchbuffer_start_atomic(batch, 0x1000);
3567 }
3568
3569 static void
3570 gen6_pp_pipeline_setup(VADriverContextP ctx,
3571                        struct i965_post_processing_context *pp_context)
3572 {
3573     struct intel_batchbuffer *batch = pp_context->batch;
3574
3575     intel_batchbuffer_start_atomic(batch, 0x1000);
3576     intel_batchbuffer_emit_mi_flush(batch);
3577     gen6_pp_pipeline_select(ctx, pp_context);
3578     gen6_pp_state_base_address(ctx, pp_context);
3579     gen6_pp_vfe_state(ctx, pp_context);
3580     gen6_pp_curbe_load(ctx, pp_context);
3581     gen6_interface_descriptor_load(ctx, pp_context);
3582     gen6_pp_object_walker(ctx, pp_context);
3583     intel_batchbuffer_end_atomic(batch);
3584 }
3585
3586 static VAStatus
3587 gen6_post_processing(
3588     VADriverContextP   ctx,
3589     struct i965_post_processing_context *pp_context,
3590     const struct i965_surface *src_surface,
3591     const VARectangle *src_rect,
3592     struct i965_surface *dst_surface,
3593     const VARectangle *dst_rect,
3594     int                pp_index,
3595     void * filter_param
3596 )
3597 {
3598     VAStatus va_status;
3599
3600     va_status = gen6_pp_initialize(ctx, pp_context,
3601                                    src_surface,
3602                                    src_rect,
3603                                    dst_surface,
3604                                    dst_rect,
3605                                    pp_index,
3606                                    filter_param);
3607
3608     if (va_status == VA_STATUS_SUCCESS) {
3609         gen6_pp_states_setup(ctx, pp_context);
3610         gen6_pp_pipeline_setup(ctx, pp_context);
3611     }
3612
3613     return va_status;
3614 }
3615
3616 static VAStatus
3617 i965_post_processing_internal(
3618     VADriverContextP   ctx,
3619     struct i965_post_processing_context *pp_context,
3620     const struct i965_surface *src_surface,
3621     const VARectangle *src_rect,
3622     struct i965_surface *dst_surface,
3623     const VARectangle *dst_rect,
3624     int                pp_index,
3625     void *filter_param
3626 )
3627 {
3628     struct i965_driver_data *i965 = i965_driver_data(ctx);
3629     VAStatus va_status;
3630
3631     if (IS_GEN6(i965->intel.device_id) ||
3632         IS_GEN7(i965->intel.device_id))
3633         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3634     else
3635         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3636
3637     return va_status;
3638 }
3639
3640 VAStatus
3641 i965_DestroySurfaces(VADriverContextP ctx,
3642                      VASurfaceID *surface_list,
3643                      int num_surfaces);
3644 VAStatus
3645 i965_CreateSurfaces(VADriverContextP ctx,
3646                     int width,
3647                     int height,
3648                     int format,
3649                     int num_surfaces,
3650                     VASurfaceID *surfaces);
3651
3652 static void
3653 rgb_to_yuv(unsigned int argb,
3654            unsigned char *y,
3655            unsigned char *u,
3656            unsigned char *v,
3657            unsigned char *a)
3658 {
3659     int r = ((argb >> 16) & 0xff);
3660     int g = ((argb >> 8) & 0xff);
3661     int b = ((argb >> 0) & 0xff);
3662
3663     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3664     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3665     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3666     *a = ((argb >> 24) & 0xff);
3667 }
3668
3669 static void
3670 i965_vpp_clear_surface(VADriverContextP ctx,
3671                        struct i965_post_processing_context *pp_context,
3672                        VASurfaceID surface,
3673                        unsigned int color)
3674 {
3675     struct i965_driver_data *i965 = i965_driver_data(ctx);
3676     struct intel_batchbuffer *batch = pp_context->batch;
3677     struct object_surface *obj_surface = SURFACE(surface);
3678     unsigned int blt_cmd, br13;
3679     unsigned int tiling = 0, swizzle = 0;
3680     int pitch;
3681     unsigned char y, u, v, a;
3682
3683     /* Currently only support NV12 surface */
3684     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3685         return;
3686
3687     rgb_to_yuv(color, &y, &u, &v, &a);
3688
3689     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3690     blt_cmd = XY_COLOR_BLT_CMD;
3691     pitch = obj_surface->width;
3692
3693     if (tiling != I915_TILING_NONE) {
3694         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3695         pitch >>= 2;
3696     }
3697
3698     br13 = 0xf0 << 16;
3699     br13 |= BR13_8;
3700     br13 |= pitch;
3701
3702     if (IS_GEN6(i965->intel.device_id) ||
3703         IS_GEN7(i965->intel.device_id)) {
3704         intel_batchbuffer_start_atomic_blt(batch, 48);
3705         BEGIN_BLT_BATCH(batch, 12);
3706     } else {
3707         intel_batchbuffer_start_atomic(batch, 48);
3708         BEGIN_BATCH(batch, 12);
3709     }
3710
3711     OUT_BATCH(batch, blt_cmd);
3712     OUT_BATCH(batch, br13);
3713     OUT_BATCH(batch,
3714               0 << 16 |
3715               0);
3716     OUT_BATCH(batch,
3717               obj_surface->height << 16 |
3718               obj_surface->width);
3719     OUT_RELOC(batch, obj_surface->bo,
3720               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3721               0);
3722     OUT_BATCH(batch, y);
3723
3724     br13 = 0xf0 << 16;
3725     br13 |= BR13_565;
3726     br13 |= pitch;
3727
3728     OUT_BATCH(batch, blt_cmd);
3729     OUT_BATCH(batch, br13);
3730     OUT_BATCH(batch,
3731               0 << 16 |
3732               0);
3733     OUT_BATCH(batch,
3734               obj_surface->height / 2 << 16 |
3735               obj_surface->width / 2);
3736     OUT_RELOC(batch, obj_surface->bo,
3737               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3738               obj_surface->width * obj_surface->y_cb_offset);
3739     OUT_BATCH(batch, v << 8 | u);
3740
3741     ADVANCE_BATCH(batch);
3742     intel_batchbuffer_end_atomic(batch);
3743 }
3744
3745 VASurfaceID
3746 i965_post_processing(
3747     VADriverContextP   ctx,
3748     VASurfaceID        surface,
3749     const VARectangle *src_rect,
3750     const VARectangle *dst_rect,
3751     unsigned int       flags,
3752     int               *has_done_scaling
3753 )
3754 {
3755     struct i965_driver_data *i965 = i965_driver_data(ctx);
3756     VASurfaceID in_surface_id = surface;
3757     VASurfaceID out_surface_id = VA_INVALID_ID;
3758
3759     *has_done_scaling = 0;
3760
3761     if (HAS_PP(i965)) {
3762         struct object_surface *obj_surface;
3763         VAStatus status;
3764         struct i965_surface src_surface;
3765         struct i965_surface dst_surface;
3766
3767         obj_surface = SURFACE(in_surface_id);
3768
3769         /* Currently only support post processing for NV12 surface */
3770         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3771             return out_surface_id;
3772
3773         _i965LockMutex(&i965->pp_mutex);
3774
3775         if (flags & I965_PP_FLAG_MCDI) {
3776             status = i965_CreateSurfaces(ctx,
3777                                          obj_surface->orig_width,
3778                                          obj_surface->orig_height,
3779                                          VA_RT_FORMAT_YUV420,
3780                                          1,
3781                                          &out_surface_id);
3782             assert(status == VA_STATUS_SUCCESS);
3783             obj_surface = SURFACE(out_surface_id);
3784             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3785             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3786             src_surface.id = in_surface_id;
3787             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3788             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3789                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3790             dst_surface.id = out_surface_id;
3791             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3792             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3793
3794             i965_post_processing_internal(ctx, i965->pp_context,
3795                                           &src_surface,
3796                                           src_rect,
3797                                           &dst_surface,
3798                                           dst_rect,
3799                                           PP_NV12_DNDI,
3800                                           NULL);
3801         }
3802
3803         if (flags & I965_PP_FLAG_AVS) {
3804             struct i965_render_state *render_state = &i965->render_state;
3805             struct intel_region *dest_region = render_state->draw_region;
3806
3807             if (out_surface_id != VA_INVALID_ID)
3808                 in_surface_id = out_surface_id;
3809
3810             status = i965_CreateSurfaces(ctx,
3811                                          dest_region->width,
3812                                          dest_region->height,
3813                                          VA_RT_FORMAT_YUV420,
3814                                          1,
3815                                          &out_surface_id);
3816             assert(status == VA_STATUS_SUCCESS);
3817             obj_surface = SURFACE(out_surface_id);
3818             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3819             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3820             src_surface.id = in_surface_id;
3821             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3822             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3823             dst_surface.id = out_surface_id;
3824             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3825             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3826
3827             i965_post_processing_internal(ctx, i965->pp_context,
3828                                           &src_surface,
3829                                           src_rect,
3830                                           &dst_surface,
3831                                           dst_rect,
3832                                           PP_NV12_AVS,
3833                                           NULL);
3834
3835             if (in_surface_id != surface)
3836                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3837
3838             *has_done_scaling = 1;
3839         }
3840
3841         _i965UnlockMutex(&i965->pp_mutex);
3842     }
3843
3844     return out_surface_id;
3845 }
3846
3847 static VAStatus
3848 i965_image_pl3_processing(VADriverContextP ctx,
3849                           const struct i965_surface *src_surface,
3850                           const VARectangle *src_rect,
3851                           struct i965_surface *dst_surface,
3852                           const VARectangle *dst_rect)
3853 {
3854     struct i965_driver_data *i965 = i965_driver_data(ctx);
3855     struct i965_post_processing_context *pp_context = i965->pp_context;
3856     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3857
3858     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3859         i965_post_processing_internal(ctx, i965->pp_context,
3860                                       src_surface,
3861                                       src_rect,
3862                                       dst_surface,
3863                                       dst_rect,
3864                                       PP_PL3_LOAD_SAVE_N12,
3865                                       NULL);
3866     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
3867                fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
3868         i965_post_processing_internal(ctx, i965->pp_context,
3869                                       src_surface,
3870                                       src_rect,
3871                                       dst_surface,
3872                                       dst_rect,
3873                                       PP_PL3_LOAD_SAVE_PL3,
3874                                       NULL);
3875     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3876         i965_post_processing_internal(ctx, i965->pp_context,
3877                                       src_surface,
3878                                       src_rect,
3879                                       dst_surface,
3880                                       dst_rect,
3881                                       PP_PL3_LOAD_SAVE_PA,
3882                                       NULL);
3883
3884     }
3885     else {
3886         assert(0);
3887     }
3888
3889     intel_batchbuffer_flush(pp_context->batch);
3890
3891     return VA_STATUS_SUCCESS;
3892 }
3893
3894 static VAStatus
3895 i965_image_pl2_processing(VADriverContextP ctx,
3896                           const struct i965_surface *src_surface,
3897                           const VARectangle *src_rect,
3898                           struct i965_surface *dst_surface,
3899                           const VARectangle *dst_rect)
3900 {
3901     struct i965_driver_data *i965 = i965_driver_data(ctx);
3902     struct i965_post_processing_context *pp_context = i965->pp_context;
3903     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3904
3905     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3906         i965_post_processing_internal(ctx, i965->pp_context,
3907                                       src_surface,
3908                                       src_rect,
3909                                       dst_surface,
3910                                       dst_rect,
3911                                       PP_NV12_LOAD_SAVE_N12,
3912                                       NULL);
3913     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
3914                fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
3915         i965_post_processing_internal(ctx, i965->pp_context,
3916                                       src_surface,
3917                                       src_rect,
3918                                       dst_surface,
3919                                       dst_rect,
3920                                       PP_NV12_LOAD_SAVE_PL3,
3921                                       NULL);
3922     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3923         i965_post_processing_internal(ctx, i965->pp_context,
3924                                       src_surface,
3925                                       src_rect,
3926                                       dst_surface,
3927                                       dst_rect,
3928                                       PP_NV12_LOAD_SAVE_PA,
3929                                       NULL);
3930     }
3931
3932     intel_batchbuffer_flush(pp_context->batch);
3933
3934     return VA_STATUS_SUCCESS;
3935 }
3936
3937 VAStatus
3938 i965_image_processing(VADriverContextP ctx,
3939                       const struct i965_surface *src_surface,
3940                       const VARectangle *src_rect,
3941                       struct i965_surface *dst_surface,
3942                       const VARectangle *dst_rect)
3943 {
3944     struct i965_driver_data *i965 = i965_driver_data(ctx);
3945     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
3946
3947     if (HAS_PP(i965)) {
3948         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
3949
3950         _i965LockMutex(&i965->pp_mutex);
3951
3952         switch (fourcc) {
3953         case VA_FOURCC('Y', 'V', '1', '2'):
3954         case VA_FOURCC('I', '4', '2', '0'):
3955         case VA_FOURCC('I', 'M', 'C', '1'):
3956         case VA_FOURCC('I', 'M', 'C', '3'):
3957             status = i965_image_pl3_processing(ctx,
3958                                                src_surface,
3959                                                src_rect,
3960                                                dst_surface,
3961                                                dst_rect);
3962             break;
3963
3964         case  VA_FOURCC('N', 'V', '1', '2'):
3965             status = i965_image_pl2_processing(ctx,
3966                                                src_surface,
3967                                                src_rect,
3968                                                dst_surface,
3969                                                dst_rect);
3970             break;
3971
3972         default:
3973             status = VA_STATUS_ERROR_UNIMPLEMENTED;
3974             break;
3975         }
3976
3977         _i965UnlockMutex(&i965->pp_mutex);
3978     }
3979
3980     return status;
3981 }
3982
3983 static void
3984 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
3985 {
3986     int i;
3987
3988     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3989     pp_context->surface_state_binding_table.bo = NULL;
3990
3991     dri_bo_unreference(pp_context->curbe.bo);
3992     pp_context->curbe.bo = NULL;
3993
3994     dri_bo_unreference(pp_context->sampler_state_table.bo);
3995     pp_context->sampler_state_table.bo = NULL;
3996
3997     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3998     pp_context->sampler_state_table.bo_8x8 = NULL;
3999
4000     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4001     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4002
4003     dri_bo_unreference(pp_context->idrt.bo);
4004     pp_context->idrt.bo = NULL;
4005     pp_context->idrt.num_interface_descriptors = 0;
4006
4007     dri_bo_unreference(pp_context->vfe_state.bo);
4008     pp_context->vfe_state.bo = NULL;
4009
4010     dri_bo_unreference(pp_context->stmm.bo);
4011     pp_context->stmm.bo = NULL;
4012
4013     for (i = 0; i < NUM_PP_MODULES; i++) {
4014         struct pp_module *pp_module = &pp_context->pp_modules[i];
4015
4016         dri_bo_unreference(pp_module->kernel.bo);
4017         pp_module->kernel.bo = NULL;
4018     }
4019
4020     free(pp_context->pp_static_parameter);
4021     free(pp_context->pp_inline_parameter);
4022     pp_context->pp_static_parameter = NULL;
4023     pp_context->pp_inline_parameter = NULL;
4024 }
4025
4026 Bool
4027 i965_post_processing_terminate(VADriverContextP ctx)
4028 {
4029     struct i965_driver_data *i965 = i965_driver_data(ctx);
4030     struct i965_post_processing_context *pp_context = i965->pp_context;
4031
4032     if (pp_context) {
4033         i965_post_processing_context_finalize(pp_context);
4034         free(pp_context);
4035     }
4036
4037     i965->pp_context = NULL;
4038
4039     return True;
4040 }
4041
4042 static void
4043 i965_post_processing_context_init(VADriverContextP ctx,
4044                                   struct i965_post_processing_context *pp_context,
4045                                   struct intel_batchbuffer *batch)
4046 {
4047     struct i965_driver_data *i965 = i965_driver_data(ctx);
4048     int i;
4049
4050     pp_context->urb.size = URB_SIZE((&i965->intel));
4051     pp_context->urb.num_vfe_entries = 32;
4052     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4053     pp_context->urb.num_cs_entries = 1;
4054
4055     if (IS_GEN7(i965->intel.device_id))
4056         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4057     else
4058         pp_context->urb.size_cs_entry = 2;
4059
4060     pp_context->urb.vfe_start = 0;
4061     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4062         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4063     assert(pp_context->urb.cs_start +
4064            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4065
4066     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4067     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4068     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4069
4070     if (IS_GEN7(i965->intel.device_id))
4071         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4072     else if (IS_GEN6(i965->intel.device_id))
4073         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4074     else if (IS_IRONLAKE(i965->intel.device_id))
4075         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4076
4077     for (i = 0; i < NUM_PP_MODULES; i++) {
4078         struct pp_module *pp_module = &pp_context->pp_modules[i];
4079         dri_bo_unreference(pp_module->kernel.bo);
4080         if (pp_module->kernel.bin && pp_module->kernel.size) {
4081             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4082                                                 pp_module->kernel.name,
4083                                                 pp_module->kernel.size,
4084                                                 4096);
4085             assert(pp_module->kernel.bo);
4086             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4087         } else {
4088             pp_module->kernel.bo = NULL;
4089         }
4090     }
4091
4092     /* static & inline parameters */
4093     if (IS_GEN7(i965->intel.device_id)) {
4094         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4095         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4096     } else {
4097         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4098         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4099     }
4100
4101     pp_context->batch = batch;
4102 }
4103
4104 Bool
4105 i965_post_processing_init(VADriverContextP ctx)
4106 {
4107     struct i965_driver_data *i965 = i965_driver_data(ctx);
4108     struct i965_post_processing_context *pp_context = i965->pp_context;
4109
4110     if (HAS_PP(i965)) {
4111         if (pp_context == NULL) {
4112             pp_context = calloc(1, sizeof(*pp_context));
4113             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4114             i965->pp_context = pp_context;
4115         }
4116     }
4117
4118     return True;
4119 }
4120
4121 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4122     PP_NULL,    /* VAProcFilterNone */
4123     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4124     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4125     PP_NULL,    /* VAProcFilterSharpening */
4126     PP_NULL,    /* VAProcFilterColorBalance */
4127     PP_NULL,    /* VAProcFilterColorStandard */
4128 };
4129
4130 static const int proc_frame_to_pp_frame[3] = {
4131     I965_SURFACE_FLAG_FRAME,
4132     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4133     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4134 };
4135
4136 static void
4137 i965_proc_picture(VADriverContextP ctx,
4138                   VAProfile profile,
4139                   union codec_state *codec_state,
4140                   struct hw_context *hw_context)
4141 {
4142     struct i965_driver_data *i965 = i965_driver_data(ctx);
4143     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4144     struct proc_state *proc_state = &codec_state->proc;
4145     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4146     struct object_surface *obj_surface;
4147     struct i965_surface src_surface, dst_surface;
4148     VARectangle src_rect, dst_rect;
4149     VAStatus status;
4150     int i;
4151     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4152     int num_tmp_surfaces = 0;
4153     unsigned int tiling = 0, swizzle = 0;
4154     int in_width, in_height;
4155
4156     assert(pipeline_param->surface != VA_INVALID_ID);
4157     assert(proc_state->current_render_target != VA_INVALID_ID);
4158
4159     obj_surface = SURFACE(pipeline_param->surface);
4160     in_width = obj_surface->orig_width;
4161     in_height = obj_surface->orig_height;
4162     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4163
4164     src_surface.id = pipeline_param->surface;
4165     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4166     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4167
4168     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4169         VASurfaceID out_surface_id = VA_INVALID_ID;
4170
4171         src_surface.id = pipeline_param->surface;
4172         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4173         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4174         src_rect.x = 0;
4175         src_rect.y = 0;
4176         src_rect.width = in_width;
4177         src_rect.height = in_height;
4178
4179         status = i965_CreateSurfaces(ctx,
4180                                      in_width,
4181                                      in_height,
4182                                      VA_RT_FORMAT_YUV420,
4183                                      1,
4184                                      &out_surface_id);
4185         assert(status == VA_STATUS_SUCCESS);
4186         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4187         obj_surface = SURFACE(out_surface_id);
4188         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4189
4190         dst_surface.id = out_surface_id;
4191         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4192         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4193         dst_rect.x = 0;
4194         dst_rect.y = 0;
4195         dst_rect.width = in_width;
4196         dst_rect.height = in_height;
4197
4198         status = i965_image_processing(ctx,
4199                                        &src_surface,
4200                                        &src_rect,
4201                                        &dst_surface,
4202                                        &dst_rect);
4203         assert(status == VA_STATUS_SUCCESS);
4204
4205         src_surface.id = out_surface_id;
4206         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4207         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4208     }
4209
4210     if (pipeline_param->surface_region) {
4211         src_rect.x = pipeline_param->surface_region->x;
4212         src_rect.y = pipeline_param->surface_region->y;
4213         src_rect.width = pipeline_param->surface_region->width;
4214         src_rect.height = pipeline_param->surface_region->height;
4215     } else {
4216         src_rect.x = 0;
4217         src_rect.y = 0;
4218         src_rect.width = in_width;
4219         src_rect.height = in_height;
4220     }
4221
4222     if (pipeline_param->output_region) {
4223         dst_rect.x = pipeline_param->output_region->x;
4224         dst_rect.y = pipeline_param->output_region->y;
4225         dst_rect.width = pipeline_param->output_region->width;
4226         dst_rect.height = pipeline_param->output_region->height;
4227     } else {
4228         dst_rect.x = 0;
4229         dst_rect.y = 0;
4230         dst_rect.width = in_width;
4231         dst_rect.height = in_height;
4232     }
4233
4234     obj_surface = SURFACE(proc_state->current_render_target);
4235     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4236     i965_vpp_clear_surface(ctx, i965->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4237
4238     for (i = 0; i < pipeline_param->num_filters; i++) {
4239         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4240         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4241         VAProcFilterType filter_type = filter_param->type;
4242         VASurfaceID out_surface_id = VA_INVALID_ID;
4243         int kernel_index = procfilter_to_pp_flag[filter_type];
4244
4245         if (kernel_index != PP_NULL &&
4246             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4247             status = i965_CreateSurfaces(ctx,
4248                                          in_width,
4249                                          in_height,
4250                                          VA_RT_FORMAT_YUV420,
4251                                          1,
4252                                          &out_surface_id);
4253             assert(status == VA_STATUS_SUCCESS);
4254             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4255             obj_surface = SURFACE(out_surface_id);
4256             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4257             dst_surface.id = out_surface_id;
4258             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4259             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4260                                                    &src_surface,
4261                                                    &src_rect,
4262                                                    &dst_surface,
4263                                                    &src_rect,
4264                                                    kernel_index,
4265                                                    filter_param);
4266
4267             if (status == VA_STATUS_SUCCESS) {
4268                 src_surface.id = dst_surface.id;
4269                 src_surface.type = dst_surface.type;
4270                 src_surface.flags = dst_surface.flags;
4271             }
4272         }
4273     }
4274
4275     dst_surface.id = proc_state->current_render_target;
4276     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4277
4278     if (src_rect.width == dst_rect.width &&
4279         src_rect.height == dst_rect.height) {
4280         i965_post_processing_internal(ctx, &proc_context->pp_context,
4281                                       &src_surface,
4282                                       &src_rect,
4283                                       &dst_surface,
4284                                       &dst_rect,
4285                                       PP_NV12_LOAD_SAVE_N12,
4286                                       NULL);
4287     } else {
4288
4289         i965_post_processing_internal(ctx, &proc_context->pp_context,
4290                                       &src_surface,
4291                                       &src_rect,
4292                                       &dst_surface,
4293                                       &dst_rect,
4294                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4295                                       PP_NV12_AVS : PP_NV12_SCALING,
4296                                       NULL);
4297     }
4298
4299     if (num_tmp_surfaces)
4300         i965_DestroySurfaces(ctx,
4301                              tmp_surfaces,
4302                              num_tmp_surfaces);
4303
4304     intel_batchbuffer_flush(hw_context->batch);
4305 }
4306
4307 static void
4308 i965_proc_context_destroy(void *hw_context)
4309 {
4310     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4311
4312     i965_post_processing_context_finalize(&proc_context->pp_context);
4313     intel_batchbuffer_free(proc_context->base.batch);
4314     free(proc_context);
4315 }
4316
4317 struct hw_context *
4318 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4319 {
4320     struct intel_driver_data *intel = intel_driver_data(ctx);
4321     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4322
4323     proc_context->base.destroy = i965_proc_context_destroy;
4324     proc_context->base.run = i965_proc_picture;
4325     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4326     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4327
4328     return (struct hw_context *)proc_context;
4329 }