src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 111                                    const struct i965_surface *src_surface,
 112                                    const VARectangle *src_rect,
 113                                    struct i965_surface *dst_surface,
 114                                    const VARectangle *dst_rect,
 115                                    void *filter_param);
 116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 117                                             const struct i965_surface *src_surface,
 118                                             const VARectangle *src_rect,
 119                                             struct i965_surface *dst_surface,
 120                                             const VARectangle *dst_rect,
 121                                             void *filter_param);
 122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 123                                            const struct i965_surface *src_surface,
 124                                            const VARectangle *src_rect,
 125                                            struct i965_surface *dst_surface,
 126                                            const VARectangle *dst_rect,
 127                                            void *filter_param);
 128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 129                                              const struct i965_surface *src_surface,
 130                                              const VARectangle *src_rect,
 131                                              struct i965_surface *dst_surface,
 132                                              const VARectangle *dst_rect,
 133                                              void *filter_param);
 134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 135                                                 const struct i965_surface *src_surface,
 136                                                 const VARectangle *src_rect,
 137                                                 struct i965_surface *dst_surface,
 138                                                 const VARectangle *dst_rect,
 139                                                 void *filter_param);
 140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 141                                         const struct i965_surface *src_surface,
 142                                         const VARectangle *src_rect,
 143                                         struct i965_surface *dst_surface,
 144                                         const VARectangle *dst_rect,
 145                                         void *filter_param);
 146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 147                                       const struct i965_surface *src_surface,
 148                                       const VARectangle *src_rect,
 149                                       struct i965_surface *dst_surface,
 150                                       const VARectangle *dst_rect,
 151                                       void *filter_param);
 152
 153 static struct pp_module pp_modules_gen5[] = {
 154     {
 155         {
 156             "NULL module (for testing)",
 157             PP_NULL,
 158             pp_null_gen5,
 159             sizeof(pp_null_gen5),
 160             NULL,
 161         },
 162
 163         pp_null_initialize,
 164     },
 165
 166     {
 167         {
 168             "NV12_NV12",
 169             PP_NV12_LOAD_SAVE_N12,
 170             pp_nv12_load_save_nv12_gen5,
 171             sizeof(pp_nv12_load_save_nv12_gen5),
 172             NULL,
 173         },
 174
 175         pp_plx_load_save_plx_initialize,
 176     },
 177
 178     {
 179         {
 180             "NV12_PL3",
 181             PP_NV12_LOAD_SAVE_PL3,
 182             pp_nv12_load_save_pl3_gen5,
 183             sizeof(pp_nv12_load_save_pl3_gen5),
 184             NULL,
 185         },
 186
 187         pp_plx_load_save_plx_initialize,
 188     },
 189
 190     {
 191         {
 192             "PL3_NV12",
 193             PP_PL3_LOAD_SAVE_N12,
 194             pp_pl3_load_save_nv12_gen5,
 195             sizeof(pp_pl3_load_save_nv12_gen5),
 196             NULL,
 197         },
 198
 199         pp_plx_load_save_plx_initialize,
 200     },
 201
 202     {
 203         {
 204             "PL3_PL3",
 205             PP_PL3_LOAD_SAVE_N12,
 206             pp_pl3_load_save_pl3_gen5,
 207             sizeof(pp_pl3_load_save_pl3_gen5),
 208             NULL,
 209         },
 210
 211         pp_plx_load_save_plx_initialize
 212     },
 213
 214     {
 215         {
 216             "NV12 Scaling module",
 217             PP_NV12_SCALING,
 218             pp_nv12_scaling_gen5,
 219             sizeof(pp_nv12_scaling_gen5),
 220             NULL,
 221         },
 222
 223         pp_nv12_scaling_initialize,
 224     },
 225
 226     {
 227         {
 228             "NV12 AVS module",
 229             PP_NV12_AVS,
 230             pp_nv12_avs_gen5,
 231             sizeof(pp_nv12_avs_gen5),
 232             NULL,
 233         },
 234
 235         pp_nv12_avs_initialize_nlas,
 236     },
 237
 238     {
 239         {
 240             "NV12 DNDI module",
 241             PP_NV12_DNDI,
 242             pp_nv12_dndi_gen5,
 243             sizeof(pp_nv12_dndi_gen5),
 244             NULL,
 245         },
 246
 247         pp_nv12_dndi_initialize,
 248     },
 249
 250     {
 251         {
 252             "NV12 DN module",
 253             PP_NV12_DN,
 254             pp_nv12_dn_gen5,
 255             sizeof(pp_nv12_dn_gen5),
 256             NULL,
 257         },
 258
 259         pp_nv12_dn_initialize,
 260     },
 261
 262     {
 263         {
 264             "NV12_PA module",
 265             PP_NV12_LOAD_SAVE_PA,
 266             pp_nv12_load_save_pa_gen5,
 267             sizeof(pp_nv12_load_save_pa_gen5),
 268             NULL,
 269         },
 270
 271         pp_plx_load_save_plx_initialize,
 272     },
 273
 274     {
 275         {
 276             "PL3_PA module",
 277             PP_PL3_LOAD_SAVE_PA,
 278             pp_pl3_load_save_pa_gen5,
 279             sizeof(pp_pl3_load_save_pa_gen5),
 280             NULL,
 281         },
 282
 283         pp_plx_load_save_plx_initialize,
 284     },
 285
 286     {
 287         {
 288             "PA_NV12 module",
 289             PP_PA_LOAD_SAVE_NV12,
 290             pp_pa_load_save_nv12_gen5,
 291             sizeof(pp_pa_load_save_nv12_gen5),
 292             NULL,
 293         },
 294
 295         pp_plx_load_save_plx_initialize,
 296     },
 297
 298     {
 299         {
 300             "PA_PL3 module",
 301             PP_PA_LOAD_SAVE_PL3,
 302             pp_pa_load_save_pl3_gen5,
 303             sizeof(pp_pa_load_save_pl3_gen5),
 304             NULL,
 305         },
 306
 307         pp_plx_load_save_plx_initialize,
 308     },
 309
 310 };
 311
 312 static const uint32_t pp_null_gen6[][4] = {
 313 #include "shaders/post_processing/gen5_6/null.g6b"
 314 };
 315
 316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 318 };
 319
 320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 322 };
 323
 324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 326 };
 327
 328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 330 };
 331
 332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 334 };
 335
 336 static const uint32_t pp_nv12_avs_gen6[][4] = {
 337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 338 };
 339
 340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 342 };
 343
 344 static const uint32_t pp_nv12_dn_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 350 };
 351
 352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 354 };
 355
 356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 362 };
 363
 364 static struct pp_module pp_modules_gen6[] = {
 365     {
 366         {
 367             "NULL module (for testing)",
 368             PP_NULL,
 369             pp_null_gen6,
 370             sizeof(pp_null_gen6),
 371             NULL,
 372         },
 373
 374         pp_null_initialize,
 375     },
 376
 377     {
 378         {
 379             "NV12_NV12",
 380             PP_NV12_LOAD_SAVE_N12,
 381             pp_nv12_load_save_nv12_gen6,
 382             sizeof(pp_nv12_load_save_nv12_gen6),
 383             NULL,
 384         },
 385
 386         pp_plx_load_save_plx_initialize,
 387     },
 388
 389     {
 390         {
 391             "NV12_PL3",
 392             PP_NV12_LOAD_SAVE_PL3,
 393             pp_nv12_load_save_pl3_gen6,
 394             sizeof(pp_nv12_load_save_pl3_gen6),
 395             NULL,
 396         },
 397
 398         pp_plx_load_save_plx_initialize,
 399     },
 400
 401     {
 402         {
 403             "PL3_NV12",
 404             PP_PL3_LOAD_SAVE_N12,
 405             pp_pl3_load_save_nv12_gen6,
 406             sizeof(pp_pl3_load_save_nv12_gen6),
 407             NULL,
 408         },
 409
 410         pp_plx_load_save_plx_initialize,
 411     },
 412
 413     {
 414         {
 415             "PL3_PL3",
 416             PP_PL3_LOAD_SAVE_N12,
 417             pp_pl3_load_save_pl3_gen6,
 418             sizeof(pp_pl3_load_save_pl3_gen6),
 419             NULL,
 420         },
 421
 422         pp_plx_load_save_plx_initialize,
 423     },
 424
 425     {
 426         {
 427             "NV12 Scaling module",
 428             PP_NV12_SCALING,
 429             pp_nv12_scaling_gen6,
 430             sizeof(pp_nv12_scaling_gen6),
 431             NULL,
 432         },
 433
 434         gen6_nv12_scaling_initialize,
 435     },
 436
 437     {
 438         {
 439             "NV12 AVS module",
 440             PP_NV12_AVS,
 441             pp_nv12_avs_gen6,
 442             sizeof(pp_nv12_avs_gen6),
 443             NULL,
 444         },
 445
 446         pp_nv12_avs_initialize_nlas,
 447     },
 448
 449     {
 450         {
 451             "NV12 DNDI module",
 452             PP_NV12_DNDI,
 453             pp_nv12_dndi_gen6,
 454             sizeof(pp_nv12_dndi_gen6),
 455             NULL,
 456         },
 457
 458         pp_nv12_dndi_initialize,
 459     },
 460
 461     {
 462         {
 463             "NV12 DN module",
 464             PP_NV12_DN,
 465             pp_nv12_dn_gen6,
 466             sizeof(pp_nv12_dn_gen6),
 467             NULL,
 468         },
 469
 470         pp_nv12_dn_initialize,
 471     },
 472     {
 473         {
 474             "NV12_PA module",
 475             PP_NV12_LOAD_SAVE_PA,
 476             pp_nv12_load_save_pa_gen6,
 477             sizeof(pp_nv12_load_save_pa_gen6),
 478             NULL,
 479         },
 480
 481         pp_plx_load_save_plx_initialize,
 482     },
 483
 484     {
 485         {
 486             "PL3_PA module",
 487             PP_PL3_LOAD_SAVE_PA,
 488             pp_pl3_load_save_pa_gen6,
 489             sizeof(pp_pl3_load_save_pa_gen6),
 490             NULL,
 491         },
 492
 493         pp_plx_load_save_plx_initialize,
 494     },
 495
 496     {
 497         {
 498             "PA_NV12 module",
 499             PP_PA_LOAD_SAVE_NV12,
 500             pp_pa_load_save_nv12_gen6,
 501             sizeof(pp_pa_load_save_nv12_gen6),
 502             NULL,
 503         },
 504
 505         pp_plx_load_save_plx_initialize,
 506     },
 507
 508     {
 509         {
 510             "PA_PL3 module",
 511             PP_PA_LOAD_SAVE_PL3,
 512             pp_pa_load_save_pl3_gen6,
 513             sizeof(pp_pa_load_save_pl3_gen6),
 514             NULL,
 515         },
 516
 517         pp_plx_load_save_plx_initialize,
 518     },
 519
 520 };
 521
 522 static const uint32_t pp_null_gen7[][4] = {
 523 };
 524
 525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 527 };
 528
 529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 531 };
 532
 533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 535 };
 536
 537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 539 };
 540
 541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 542 #include "shaders/post_processing/gen7/avs.g7b"
 543 };
 544
 545 static const uint32_t pp_nv12_avs_gen7[][4] = {
 546 #include "shaders/post_processing/gen7/avs.g7b"
 547 };
 548
 549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 550 // #include "shaders/post_processing/gen7/dndi.g7b"
 551 };
 552
 553 static const uint32_t pp_nv12_dn_gen7[][4] = {
 554 };
 555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 556 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 557 };
 558 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 559 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 560 };
 561 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 562 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 563 };
 564 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 565 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 566 };
 567
 568 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 569                                            const struct i965_surface *src_surface,
 570                                            const VARectangle *src_rect,
 571                                            struct i965_surface *dst_surface,
 572                                            const VARectangle *dst_rect,
 573                                            void *filter_param);
 574 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 575                                              const struct i965_surface *src_surface,
 576                                              const VARectangle *src_rect,
 577                                              struct i965_surface *dst_surface,
 578                                              const VARectangle *dst_rect,
 579                                              void *filter_param);
 580 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 581                                            const struct i965_surface *src_surface,
 582                                            const VARectangle *src_rect,
 583                                            struct i965_surface *dst_surface,
 584                                            const VARectangle *dst_rect,
 585                                            void *filter_param);
 586
 587 static struct pp_module pp_modules_gen7[] = {
 588     {
 589         {
 590             "NULL module (for testing)",
 591             PP_NULL,
 592             pp_null_gen7,
 593             sizeof(pp_null_gen7),
 594             NULL,
 595         },
 596
 597         pp_null_initialize,
 598     },
 599
 600     {
 601         {
 602             "NV12_NV12",
 603             PP_NV12_LOAD_SAVE_N12,
 604             pp_nv12_load_save_nv12_gen7,
 605             sizeof(pp_nv12_load_save_nv12_gen7),
 606             NULL,
 607         },
 608
 609         gen7_pp_plx_avs_initialize,
 610     },
 611
 612     {
 613         {
 614             "NV12_PL3",
 615             PP_NV12_LOAD_SAVE_PL3,
 616             pp_nv12_load_save_pl3_gen7,
 617             sizeof(pp_nv12_load_save_pl3_gen7),
 618             NULL,
 619         },
 620
 621         gen7_pp_plx_avs_initialize,
 622     },
 623
 624     {
 625         {
 626             "PL3_NV12",
 627             PP_PL3_LOAD_SAVE_N12,
 628             pp_pl3_load_save_nv12_gen7,
 629             sizeof(pp_pl3_load_save_nv12_gen7),
 630             NULL,
 631         },
 632
 633         gen7_pp_plx_avs_initialize,
 634     },
 635
 636     {
 637         {
 638             "PL3_PL3",
 639             PP_PL3_LOAD_SAVE_N12,
 640             pp_pl3_load_save_pl3_gen7,
 641             sizeof(pp_pl3_load_save_pl3_gen7),
 642             NULL,
 643         },
 644
 645         gen7_pp_plx_avs_initialize,
 646     },
 647
 648     {
 649         {
 650             "NV12 Scaling module",
 651             PP_NV12_SCALING,
 652             pp_nv12_scaling_gen7,
 653             sizeof(pp_nv12_scaling_gen7),
 654             NULL,
 655         },
 656
 657         gen7_pp_plx_avs_initialize,
 658     },
 659
 660     {
 661         {
 662             "NV12 AVS module",
 663             PP_NV12_AVS,
 664             pp_nv12_avs_gen7,
 665             sizeof(pp_nv12_avs_gen7),
 666             NULL,
 667         },
 668
 669         gen7_pp_plx_avs_initialize,
 670     },
 671
 672     {
 673         {
 674             "NV12 DNDI module",
 675             PP_NV12_DNDI,
 676             pp_nv12_dndi_gen7,
 677             sizeof(pp_nv12_dndi_gen7),
 678             NULL,
 679         },
 680
 681         gen7_pp_nv12_dndi_initialize,
 682     },
 683
 684     {
 685         {
 686             "NV12 DN module",
 687             PP_NV12_DN,
 688             pp_nv12_dn_gen7,
 689             sizeof(pp_nv12_dn_gen7),
 690             NULL,
 691         },
 692
 693         gen7_pp_nv12_dn_initialize,
 694     },
 695     {
 696         {
 697             "NV12_PA module",
 698             PP_NV12_LOAD_SAVE_PA,
 699             pp_nv12_load_save_pa_gen7,
 700             sizeof(pp_nv12_load_save_pa_gen7),
 701             NULL,
 702         },
 703
 704         gen7_pp_plx_avs_initialize,
 705     },
 706
 707     {
 708         {
 709             "PL3_PA module",
 710             PP_PL3_LOAD_SAVE_PA,
 711             pp_pl3_load_save_pa_gen7,
 712             sizeof(pp_pl3_load_save_pa_gen7),
 713             NULL,
 714         },
 715
 716         gen7_pp_plx_avs_initialize,
 717     },
 718
 719     {
 720         {
 721             "PA_NV12 module",
 722             PP_PA_LOAD_SAVE_NV12,
 723             pp_pa_load_save_nv12_gen7,
 724             sizeof(pp_pa_load_save_nv12_gen7),
 725             NULL,
 726         },
 727
 728         gen7_pp_plx_avs_initialize,
 729     },
 730
 731     {
 732         {
 733             "PA_PL3 module",
 734             PP_PA_LOAD_SAVE_PL3,
 735             pp_pa_load_save_pl3_gen7,
 736             sizeof(pp_pa_load_save_pl3_gen7),
 737             NULL,
 738         },
 739
 740         gen7_pp_plx_avs_initialize,
 741     },
 742
 743 };
 744
 745 static int
 746 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 747 {
 748     struct i965_driver_data *i965 = i965_driver_data(ctx);
 749     int fourcc;
 750
 751     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 752         struct object_image *obj_image = IMAGE(surface->id);
 753         fourcc = obj_image->image.format.fourcc;
 754     } else {
 755         struct object_surface *obj_surface = SURFACE(surface->id);
 756         fourcc = obj_surface->fourcc;
 757     }
 758
 759     return fourcc;
 760 }
 761
 762 static void
 763 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 764 {
 765     switch (tiling) {
 766     case I915_TILING_NONE:
 767         ss->ss3.tiled_surface = 0;
 768         ss->ss3.tile_walk = 0;
 769         break;
 770     case I915_TILING_X:
 771         ss->ss3.tiled_surface = 1;
 772         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 773         break;
 774     case I915_TILING_Y:
 775         ss->ss3.tiled_surface = 1;
 776         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 777         break;
 778     }
 779 }
 780
 781 static void
 782 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 783 {
 784     switch (tiling) {
 785     case I915_TILING_NONE:
 786         ss->ss2.tiled_surface = 0;
 787         ss->ss2.tile_walk = 0;
 788         break;
 789     case I915_TILING_X:
 790         ss->ss2.tiled_surface = 1;
 791         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 792         break;
 793     case I915_TILING_Y:
 794         ss->ss2.tiled_surface = 1;
 795         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 796         break;
 797     }
 798 }
 799
 800 static void
 801 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 802 {
 803     switch (tiling) {
 804     case I915_TILING_NONE:
 805         ss->ss0.tiled_surface = 0;
 806         ss->ss0.tile_walk = 0;
 807         break;
 808     case I915_TILING_X:
 809         ss->ss0.tiled_surface = 1;
 810         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 811         break;
 812     case I915_TILING_Y:
 813         ss->ss0.tiled_surface = 1;
 814         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 815         break;
 816     }
 817 }
 818
 819 static void
 820 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 821 {
 822     switch (tiling) {
 823     case I915_TILING_NONE:
 824         ss->ss2.tiled_surface = 0;
 825         ss->ss2.tile_walk = 0;
 826         break;
 827     case I915_TILING_X:
 828         ss->ss2.tiled_surface = 1;
 829         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 830         break;
 831     case I915_TILING_Y:
 832         ss->ss2.tiled_surface = 1;
 833         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 834         break;
 835     }
 836 }
 837
 838 static void
 839 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 840 {
 841     struct i965_interface_descriptor *desc;
 842     dri_bo *bo;
 843     int pp_index = pp_context->current_pp;
 844
 845     bo = pp_context->idrt.bo;
 846     dri_bo_map(bo, 1);
 847     assert(bo->virtual);
 848     desc = bo->virtual;
 849     memset(desc, 0, sizeof(*desc));
 850     desc->desc0.grf_reg_blocks = 10;
 851     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 852     desc->desc1.const_urb_entry_read_offset = 0;
 853     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 854     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 855     desc->desc2.sampler_count = 0;
 856     desc->desc3.binding_table_entry_count = 0;
 857     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 858
 859     dri_bo_emit_reloc(bo,
 860                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 861                       desc->desc0.grf_reg_blocks,
 862                       offsetof(struct i965_interface_descriptor, desc0),
 863                       pp_context->pp_modules[pp_index].kernel.bo);
 864
 865     dri_bo_emit_reloc(bo,
 866                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 867                       desc->desc2.sampler_count << 2,
 868                       offsetof(struct i965_interface_descriptor, desc2),
 869                       pp_context->sampler_state_table.bo);
 870
 871     dri_bo_unmap(bo);
 872     pp_context->idrt.num_interface_descriptors++;
 873 }
 874
 875 static void
 876 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 877 {
 878     struct i965_vfe_state *vfe_state;
 879     dri_bo *bo;
 880
 881     bo = pp_context->vfe_state.bo;
 882     dri_bo_map(bo, 1);
 883     assert(bo->virtual);
 884     vfe_state = bo->virtual;
 885     memset(vfe_state, 0, sizeof(*vfe_state));
 886     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 887     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 888     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 889     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 890     vfe_state->vfe1.children_present = 0;
 891     vfe_state->vfe2.interface_descriptor_base =
 892         pp_context->idrt.bo->offset >> 4; /* reloc */
 893     dri_bo_emit_reloc(bo,
 894                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 895                       0,
 896                       offsetof(struct i965_vfe_state, vfe2),
 897                       pp_context->idrt.bo);
 898     dri_bo_unmap(bo);
 899 }
 900
 901 static void
 902 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 903 {
 904     unsigned char *constant_buffer;
 905     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 906
 907     assert(sizeof(*pp_static_parameter) == 128);
 908     dri_bo_map(pp_context->curbe.bo, 1);
 909     assert(pp_context->curbe.bo->virtual);
 910     constant_buffer = pp_context->curbe.bo->virtual;
 911     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 912     dri_bo_unmap(pp_context->curbe.bo);
 913 }
 914
 915 static void
 916 ironlake_pp_states_setup(VADriverContextP ctx,
 917                          struct i965_post_processing_context *pp_context)
 918 {
 919     ironlake_pp_interface_descriptor_table(pp_context);
 920     ironlake_pp_vfe_state(pp_context);
 921     ironlake_pp_upload_constants(pp_context);
 922 }
 923
 924 static void
 925 ironlake_pp_pipeline_select(VADriverContextP ctx,
 926                             struct i965_post_processing_context *pp_context)
 927 {
 928     struct intel_batchbuffer *batch = pp_context->batch;
 929
 930     BEGIN_BATCH(batch, 1);
 931     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 932     ADVANCE_BATCH(batch);
 933 }
 934
 935 static void
 936 ironlake_pp_urb_layout(VADriverContextP ctx,
 937                        struct i965_post_processing_context *pp_context)
 938 {
 939     struct intel_batchbuffer *batch = pp_context->batch;
 940     unsigned int vfe_fence, cs_fence;
 941
 942     vfe_fence = pp_context->urb.cs_start;
 943     cs_fence = pp_context->urb.size;
 944
 945     BEGIN_BATCH(batch, 3);
 946     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 947     OUT_BATCH(batch, 0);
 948     OUT_BATCH(batch,
 949               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 950               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 951     ADVANCE_BATCH(batch);
 952 }
 953
 954 static void
 955 ironlake_pp_state_base_address(VADriverContextP ctx,
 956                                struct i965_post_processing_context *pp_context)
 957 {
 958     struct intel_batchbuffer *batch = pp_context->batch;
 959
 960     BEGIN_BATCH(batch, 8);
 961     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 962     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 963     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 964     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 965     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 966     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 967     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 968     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 969     ADVANCE_BATCH(batch);
 970 }
 971
 972 static void
 973 ironlake_pp_state_pointers(VADriverContextP ctx,
 974                            struct i965_post_processing_context *pp_context)
 975 {
 976     struct intel_batchbuffer *batch = pp_context->batch;
 977
 978     BEGIN_BATCH(batch, 3);
 979     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 980     OUT_BATCH(batch, 0);
 981     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 982     ADVANCE_BATCH(batch);
 983 }
 984
 985 static void
 986 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 987                           struct i965_post_processing_context *pp_context)
 988 {
 989     struct intel_batchbuffer *batch = pp_context->batch;
 990
 991     BEGIN_BATCH(batch, 2);
 992     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 993     OUT_BATCH(batch,
 994               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 995               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 996     ADVANCE_BATCH(batch);
 997 }
 998
 999 static void
1000 ironlake_pp_constant_buffer(VADriverContextP ctx,
1001                             struct i965_post_processing_context *pp_context)
1002 {
1003     struct intel_batchbuffer *batch = pp_context->batch;
1004
1005     BEGIN_BATCH(batch, 2);
1006     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1007     OUT_RELOC(batch, pp_context->curbe.bo,
1008               I915_GEM_DOMAIN_INSTRUCTION, 0,
1009               pp_context->urb.size_cs_entry - 1);
1010     ADVANCE_BATCH(batch);
1011 }
1012
1013 static void
1014 ironlake_pp_object_walker(VADriverContextP ctx,
1015                           struct i965_post_processing_context *pp_context)
1016 {
1017     struct intel_batchbuffer *batch = pp_context->batch;
1018     int x, x_steps, y, y_steps;
1019     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1020
1021     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1022     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1023
1024     for (y = 0; y < y_steps; y++) {
1025         for (x = 0; x < x_steps; x++) {
1026             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1027                 BEGIN_BATCH(batch, 20);
1028                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1029                 OUT_BATCH(batch, 0);
1030                 OUT_BATCH(batch, 0); /* no indirect data */
1031                 OUT_BATCH(batch, 0);
1032
1033                 /* inline data grf 5-6 */
1034                 assert(sizeof(*pp_inline_parameter) == 64);
1035                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1036
1037                 ADVANCE_BATCH(batch);
1038             }
1039         }
1040     }
1041 }
1042
1043 static void
1044 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1045                            struct i965_post_processing_context *pp_context)
1046 {
1047     struct intel_batchbuffer *batch = pp_context->batch;
1048
1049     intel_batchbuffer_start_atomic(batch, 0x1000);
1050     intel_batchbuffer_emit_mi_flush(batch);
1051     ironlake_pp_pipeline_select(ctx, pp_context);
1052     ironlake_pp_state_base_address(ctx, pp_context);
1053     ironlake_pp_state_pointers(ctx, pp_context);
1054     ironlake_pp_urb_layout(ctx, pp_context);
1055     ironlake_pp_cs_urb_layout(ctx, pp_context);
1056     ironlake_pp_constant_buffer(ctx, pp_context);
1057     ironlake_pp_object_walker(ctx, pp_context);
1058     intel_batchbuffer_end_atomic(batch);
1059 }
1060
1061 // update u/v offset when the surface format are packed yuv
1062 static void i965_update_src_surface_uv_offset(
1063     VADriverContextP    ctx,
1064     struct i965_post_processing_context *pp_context,
1065     const struct i965_surface *surface)
1066 {
1067     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1068     int fourcc = pp_get_surface_fourcc(ctx, surface);
1069
1070     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1071         pp_static_parameter->grf1.source_packed_u_offset = 1;
1072         pp_static_parameter->grf1.source_packed_v_offset = 3;
1073     }
1074     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1075         pp_static_parameter->grf1.source_packed_y_offset = 1;
1076         pp_static_parameter->grf1.source_packed_v_offset = 2;
1077     }
1078
1079 }
1080
1081 static void i965_update_dst_surface_uv_offset(
1082     VADriverContextP    ctx,
1083     struct i965_post_processing_context *pp_context,
1084     const struct i965_surface *surface)
1085 {
1086     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1087     int fourcc = pp_get_surface_fourcc(ctx, surface);
1088
1089     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1090         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1091         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1092     }
1093     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1094         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1095         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1096     }
1097
1098 }
1099
1100 static void
1101 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1102                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1103                           int width, int height, int pitch, int format,
1104                           int index, int is_target)
1105 {
1106     struct i965_surface_state *ss;
1107     dri_bo *ss_bo;
1108     unsigned int tiling;
1109     unsigned int swizzle;
1110
1111     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1112     ss_bo = pp_context->surface_state_binding_table.bo;
1113     assert(ss_bo);
1114
1115     dri_bo_map(ss_bo, True);
1116     assert(ss_bo->virtual);
1117     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1118     memset(ss, 0, sizeof(*ss));
1119     ss->ss0.surface_type = I965_SURFACE_2D;
1120     ss->ss0.surface_format = format;
1121     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1122     ss->ss2.width = width - 1;
1123     ss->ss2.height = height - 1;
1124     ss->ss3.pitch = pitch - 1;
1125     pp_set_surface_tiling(ss, tiling);
1126     dri_bo_emit_reloc(ss_bo,
1127                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1128                       surf_bo_offset,
1129                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1130                       surf_bo);
1131     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1132     dri_bo_unmap(ss_bo);
1133 }
1134
1135 static void
1136 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1137                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1138                            int width, int height, int wpitch,
1139                            int xoffset, int yoffset,
1140                            int format, int interleave_chroma,
1141                            int index)
1142 {
1143     struct i965_surface_state2 *ss2;
1144     dri_bo *ss2_bo;
1145     unsigned int tiling;
1146     unsigned int swizzle;
1147
1148     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1149     ss2_bo = pp_context->surface_state_binding_table.bo;
1150     assert(ss2_bo);
1151
1152     dri_bo_map(ss2_bo, True);
1153     assert(ss2_bo->virtual);
1154     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1155     memset(ss2, 0, sizeof(*ss2));
1156     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1157     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1158     ss2->ss1.width = width - 1;
1159     ss2->ss1.height = height - 1;
1160     ss2->ss2.pitch = wpitch - 1;
1161     ss2->ss2.interleave_chroma = interleave_chroma;
1162     ss2->ss2.surface_format = format;
1163     ss2->ss3.x_offset_for_cb = xoffset;
1164     ss2->ss3.y_offset_for_cb = yoffset;
1165     pp_set_surface2_tiling(ss2, tiling);
1166     dri_bo_emit_reloc(ss2_bo,
1167                       I915_GEM_DOMAIN_RENDER, 0,
1168                       surf_bo_offset,
1169                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1170                       surf_bo);
1171     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1172     dri_bo_unmap(ss2_bo);
1173 }
1174
1175 static void
1176 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1177                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1178                           int width, int height, int pitch, int format,
1179                           int index, int is_target)
1180 {
1181     struct gen7_surface_state *ss;
1182     dri_bo *ss_bo;
1183     unsigned int tiling;
1184     unsigned int swizzle;
1185
1186     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1187     ss_bo = pp_context->surface_state_binding_table.bo;
1188     assert(ss_bo);
1189
1190     dri_bo_map(ss_bo, True);
1191     assert(ss_bo->virtual);
1192     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1193     memset(ss, 0, sizeof(*ss));
1194     ss->ss0.surface_type = I965_SURFACE_2D;
1195     ss->ss0.surface_format = format;
1196     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1197     ss->ss2.width = width - 1;
1198     ss->ss2.height = height - 1;
1199     ss->ss3.pitch = pitch - 1;
1200     gen7_pp_set_surface_tiling(ss, tiling);
1201     dri_bo_emit_reloc(ss_bo,
1202                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1203                       surf_bo_offset,
1204                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1205                       surf_bo);
1206     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1207     dri_bo_unmap(ss_bo);
1208 }
1209
1210 static void
1211 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1212                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1213                            int width, int height, int wpitch,
1214                            int xoffset, int yoffset,
1215                            int format, int interleave_chroma,
1216                            int index)
1217 {
1218     struct gen7_surface_state2 *ss2;
1219     dri_bo *ss2_bo;
1220     unsigned int tiling;
1221     unsigned int swizzle;
1222
1223     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1224     ss2_bo = pp_context->surface_state_binding_table.bo;
1225     assert(ss2_bo);
1226
1227     dri_bo_map(ss2_bo, True);
1228     assert(ss2_bo->virtual);
1229     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1230     memset(ss2, 0, sizeof(*ss2));
1231     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1232     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1233     ss2->ss1.width = width - 1;
1234     ss2->ss1.height = height - 1;
1235     ss2->ss2.pitch = wpitch - 1;
1236     ss2->ss2.interleave_chroma = interleave_chroma;
1237     ss2->ss2.surface_format = format;
1238     ss2->ss3.x_offset_for_cb = xoffset;
1239     ss2->ss3.y_offset_for_cb = yoffset;
1240     gen7_pp_set_surface2_tiling(ss2, tiling);
1241     dri_bo_emit_reloc(ss2_bo,
1242                       I915_GEM_DOMAIN_RENDER, 0,
1243                       surf_bo_offset,
1244                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1245                       surf_bo);
1246     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1247     dri_bo_unmap(ss2_bo);
1248 }
1249
1250 static void
1251 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1252                                 const struct i965_surface *surface,
1253                                 int base_index, int is_target,
1254                                 int *width, int *height, int *pitch, int *offset)
1255 {
1256     struct i965_driver_data *i965 = i965_driver_data(ctx);
1257     struct object_surface *obj_surface;
1258     struct object_image *obj_image;
1259     dri_bo *bo;
1260     int fourcc = pp_get_surface_fourcc(ctx, surface);
1261     const int Y = 0;
1262     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1263     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1264     const int UV = 1;
1265     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1266     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1267     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1268                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1269                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1270                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1271     int scale_factor_of_1st_plane_width_in_byte = 1;
1272
1273     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1274         obj_surface = SURFACE(surface->id);
1275         bo = obj_surface->bo;
1276         width[0] = obj_surface->orig_width;
1277         height[0] = obj_surface->orig_height;
1278         pitch[0] = obj_surface->width;
1279         offset[0] = 0;
1280
1281         if (full_packed_format) {
1282             scale_factor_of_1st_plane_width_in_byte = 4;
1283             pitch[0] = obj_surface->width * 4;
1284         }
1285         else if (packed_yuv ) {
1286             scale_factor_of_1st_plane_width_in_byte =  2;
1287             pitch[0] = obj_surface->width * 2;
1288         }
1289         else if (interleaved_uv) {
1290             width[1] = obj_surface->orig_width;
1291             height[1] = obj_surface->orig_height / 2;
1292             pitch[1] = obj_surface->width;
1293             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1294         } else {
1295             width[1] = obj_surface->orig_width / 2;
1296             height[1] = obj_surface->orig_height / 2;
1297             pitch[1] = obj_surface->width / 2;
1298             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1299             width[2] = obj_surface->orig_width / 2;
1300             height[2] = obj_surface->orig_height / 2;
1301             pitch[2] = obj_surface->width / 2;
1302             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1303         }
1304     } else {
1305         obj_image = IMAGE(surface->id);
1306         bo = obj_image->bo;
1307         width[0] = obj_image->image.width;
1308         height[0] = obj_image->image.height;
1309         pitch[0] = obj_image->image.pitches[0];
1310         offset[0] = obj_image->image.offsets[0];
1311
1312         if (full_packed_format) {
1313             scale_factor_of_1st_plane_width_in_byte = 4;
1314         }
1315         else if (packed_yuv ) {
1316             scale_factor_of_1st_plane_width_in_byte = 2;
1317         }
1318         else if (interleaved_uv) {
1319             width[1] = obj_image->image.width;
1320             height[1] = obj_image->image.height / 2;
1321             pitch[1] = obj_image->image.pitches[1];
1322             offset[1] = obj_image->image.offsets[1];
1323         } else {
1324             width[1] = obj_image->image.width / 2;
1325             height[1] = obj_image->image.height / 2;
1326             pitch[1] = obj_image->image.pitches[1];
1327             offset[1] = obj_image->image.offsets[1];
1328             width[2] = obj_image->image.width / 2;
1329             height[2] = obj_image->image.height / 2;
1330             pitch[2] = obj_image->image.pitches[2];
1331             offset[2] = obj_image->image.offsets[2];
1332         }
1333     }
1334
1335     /* Y surface */
1336     i965_pp_set_surface_state(ctx, pp_context,
1337                               bo, offset[Y],
1338                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1339                               base_index, is_target);
1340
1341     if (!packed_yuv && !full_packed_format) {
1342         if (interleaved_uv) {
1343             i965_pp_set_surface_state(ctx, pp_context,
1344                                       bo, offset[UV],
1345                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1346                                       base_index + 1, is_target);
1347         } else {
1348             /* U surface */
1349             i965_pp_set_surface_state(ctx, pp_context,
1350                                       bo, offset[U],
1351                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1352                                       base_index + 1, is_target);
1353
1354             /* V surface */
1355             i965_pp_set_surface_state(ctx, pp_context,
1356                                       bo, offset[V],
1357                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1358                                       base_index + 2, is_target);
1359         }
1360     }
1361
1362 }
1363
1364 static void
1365 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1366                                      const struct i965_surface *surface,
1367                                      int base_index, int is_target,
1368                                      int *width, int *height, int *pitch, int *offset)
1369 {
1370     struct i965_driver_data *i965 = i965_driver_data(ctx);
1371     struct object_surface *obj_surface;
1372     struct object_image *obj_image;
1373     dri_bo *bo;
1374     int fourcc = pp_get_surface_fourcc(ctx, surface);
1375     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1376                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1377     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1378                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1379     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1380     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1381
1382     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1383         obj_surface = SURFACE(surface->id);
1384         bo = obj_surface->bo;
1385         width[0] = obj_surface->orig_width;
1386         height[0] = obj_surface->orig_height;
1387         pitch[0] = obj_surface->width;
1388         offset[0] = 0;
1389
1390         if (packed_yuv) {
1391             if (is_target)
1392                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1393             else
1394                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1395
1396             pitch[0] = obj_surface->width * 2;
1397         }
1398
1399         width[1] = obj_surface->cb_cr_width;
1400         height[1] = obj_surface->cb_cr_height;
1401         pitch[1] = obj_surface->cb_cr_pitch;
1402         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1403
1404         width[2] = obj_surface->cb_cr_width;
1405         height[2] = obj_surface->cb_cr_height;
1406         pitch[2] = obj_surface->cb_cr_pitch;
1407         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1408     } else {
1409         obj_image = IMAGE(surface->id);
1410         bo = obj_image->bo;
1411         width[0] = obj_image->image.width;
1412         height[0] = obj_image->image.height;
1413         pitch[0] = obj_image->image.pitches[0];
1414         offset[0] = obj_image->image.offsets[0];
1415
1416         if (packed_yuv) {
1417             if (is_target)
1418                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1419             else
1420                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1421         } else if (interleaved_uv) {
1422             width[1] = obj_image->image.width / 2;
1423             height[1] = obj_image->image.height / 2;
1424             pitch[1] = obj_image->image.pitches[1];
1425             offset[1] = obj_image->image.offsets[1];
1426         } else {
1427             width[1] = obj_image->image.width / 2;
1428             height[1] = obj_image->image.height / 2;
1429             pitch[1] = obj_image->image.pitches[U];
1430             offset[1] = obj_image->image.offsets[U];
1431             width[2] = obj_image->image.width / 2;
1432             height[2] = obj_image->image.height / 2;
1433             pitch[2] = obj_image->image.pitches[V];
1434             offset[2] = obj_image->image.offsets[V];
1435         }
1436     }
1437
1438     if (is_target) {
1439         gen7_pp_set_surface_state(ctx, pp_context,
1440                                   bo, 0,
1441                                   width[0] / 4, height[0], pitch[0],
1442                                   I965_SURFACEFORMAT_R8_SINT,
1443                                   base_index, 1);
1444
1445         if (!packed_yuv) {
1446             if (interleaved_uv) {
1447                 gen7_pp_set_surface_state(ctx, pp_context,
1448                                           bo, offset[1],
1449                                           width[1] / 2, height[1], pitch[1],
1450                                           I965_SURFACEFORMAT_R8G8_SINT,
1451                                           base_index + 1, 1);
1452             } else {
1453                 gen7_pp_set_surface_state(ctx, pp_context,
1454                                           bo, offset[1],
1455                                           width[1] / 4, height[1], pitch[1],
1456                                           I965_SURFACEFORMAT_R8_SINT,
1457                                           base_index + 1, 1);
1458                 gen7_pp_set_surface_state(ctx, pp_context,
1459                                           bo, offset[2],
1460                                           width[2] / 4, height[2], pitch[2],
1461                                           I965_SURFACEFORMAT_R8_SINT,
1462                                           base_index + 2, 1);
1463             }
1464         }
1465     } else {
1466         int format0 = SURFACE_FORMAT_Y8_UNORM;
1467
1468         switch (fourcc) {
1469         case VA_FOURCC('Y', 'U', 'Y', '2'):
1470             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1471             break;
1472
1473         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1474             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1475             break;
1476
1477         default:
1478             break;
1479         }
1480
1481         gen7_pp_set_surface2_state(ctx, pp_context,
1482                                    bo, offset[0],
1483                                    width[0], height[0], pitch[0],
1484                                    0, 0,
1485                                    format0, 0,
1486                                    base_index);
1487
1488         if (!packed_yuv) {
1489             if (interleaved_uv) {
1490                 gen7_pp_set_surface2_state(ctx, pp_context,
1491                                            bo, offset[1],
1492                                            width[1], height[1], pitch[1],
1493                                            0, 0,
1494                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1495                                            base_index + 1);
1496             } else {
1497                 gen7_pp_set_surface2_state(ctx, pp_context,
1498                                            bo, offset[1],
1499                                            width[1], height[1], pitch[1],
1500                                            0, 0,
1501                                            SURFACE_FORMAT_R8_UNORM, 0,
1502                                            base_index + 1);
1503                 gen7_pp_set_surface2_state(ctx, pp_context,
1504                                            bo, offset[2],
1505                                            width[2], height[2], pitch[2],
1506                                            0, 0,
1507                                            SURFACE_FORMAT_R8_UNORM, 0,
1508                                            base_index + 2);
1509             }
1510         }
1511     }
1512 }
1513
1514 static int
1515 pp_null_x_steps(void *private_context)
1516 {
1517     return 1;
1518 }
1519
1520 static int
1521 pp_null_y_steps(void *private_context)
1522 {
1523     return 1;
1524 }
1525
1526 static int
1527 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1528 {
1529     return 0;
1530 }
1531
1532 static VAStatus
1533 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1534                    const struct i965_surface *src_surface,
1535                    const VARectangle *src_rect,
1536                    struct i965_surface *dst_surface,
1537                    const VARectangle *dst_rect,
1538                    void *filter_param)
1539 {
1540     /* private function & data */
1541     pp_context->pp_x_steps = pp_null_x_steps;
1542     pp_context->pp_y_steps = pp_null_y_steps;
1543     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1544
1545     dst_surface->flags = src_surface->flags;
1546
1547     return VA_STATUS_SUCCESS;
1548 }
1549
1550 static int
1551 pp_load_save_x_steps(void *private_context)
1552 {
1553     return 1;
1554 }
1555
1556 static int
1557 pp_load_save_y_steps(void *private_context)
1558 {
1559     struct pp_load_save_context *pp_load_save_context = private_context;
1560
1561     return pp_load_save_context->dest_h / 8;
1562 }
1563
1564 static int
1565 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1566 {
1567     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1568
1569     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1570     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1571     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1572     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1573
1574     return 0;
1575 }
1576
1577 static VAStatus
1578 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1579                                 const struct i965_surface *src_surface,
1580                                 const VARectangle *src_rect,
1581                                 struct i965_surface *dst_surface,
1582                                 const VARectangle *dst_rect,
1583                                 void *filter_param)
1584 {
1585     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1586     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1587     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1588     int width[3], height[3], pitch[3], offset[3];
1589     const int Y = 0;
1590
1591     /* source surface */
1592     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1593                                     width, height, pitch, offset);
1594
1595     /* destination surface */
1596     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1597                                     width, height, pitch, offset);
1598
1599     /* private function & data */
1600     pp_context->pp_x_steps = pp_load_save_x_steps;
1601     pp_context->pp_y_steps = pp_load_save_y_steps;
1602     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1603     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1604     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1605
1606     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1607     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1608
1609     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1610     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1611
1612     // update u/v offset for packed yuv
1613     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
1614     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
1615
1616     dst_surface->flags = src_surface->flags;
1617
1618     return VA_STATUS_SUCCESS;
1619 }
1620
1621 static int
1622 pp_scaling_x_steps(void *private_context)
1623 {
1624     return 1;
1625 }
1626
1627 static int
1628 pp_scaling_y_steps(void *private_context)
1629 {
1630     struct pp_scaling_context *pp_scaling_context = private_context;
1631
1632     return pp_scaling_context->dest_h / 8;
1633 }
1634
1635 static int
1636 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1637 {
1638     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1639     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1640     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1641     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1642     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1643
1644     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1645     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1646     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1647     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1648
1649     return 0;
1650 }
1651
1652 static VAStatus
1653 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1654                            const struct i965_surface *src_surface,
1655                            const VARectangle *src_rect,
1656                            struct i965_surface *dst_surface,
1657                            const VARectangle *dst_rect,
1658                            void *filter_param)
1659 {
1660     struct i965_driver_data *i965 = i965_driver_data(ctx);
1661     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1662     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1663     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1664     struct object_surface *obj_surface;
1665     struct i965_sampler_state *sampler_state;
1666     int in_w, in_h, in_wpitch, in_hpitch;
1667     int out_w, out_h, out_wpitch, out_hpitch;
1668
1669     /* source surface */
1670     obj_surface = SURFACE(src_surface->id);
1671     in_w = obj_surface->orig_width;
1672     in_h = obj_surface->orig_height;
1673     in_wpitch = obj_surface->width;
1674     in_hpitch = obj_surface->height;
1675
1676     /* source Y surface index 1 */
1677     i965_pp_set_surface_state(ctx, pp_context,
1678                               obj_surface->bo, 0,
1679                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1680                               1, 0);
1681
1682     /* source UV surface index 2 */
1683     i965_pp_set_surface_state(ctx, pp_context,
1684                               obj_surface->bo, in_wpitch * in_hpitch,
1685                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1686                               2, 0);
1687
1688     /* destination surface */
1689     obj_surface = SURFACE(dst_surface->id);
1690     out_w = obj_surface->orig_width;
1691     out_h = obj_surface->orig_height;
1692     out_wpitch = obj_surface->width;
1693     out_hpitch = obj_surface->height;
1694
1695     /* destination Y surface index 7 */
1696     i965_pp_set_surface_state(ctx, pp_context,
1697                               obj_surface->bo, 0,
1698                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1699                               7, 1);
1700
1701     /* destination UV surface index 8 */
1702     i965_pp_set_surface_state(ctx, pp_context,
1703                               obj_surface->bo, out_wpitch * out_hpitch,
1704                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1705                               8, 1);
1706
1707     /* sampler state */
1708     dri_bo_map(pp_context->sampler_state_table.bo, True);
1709     assert(pp_context->sampler_state_table.bo->virtual);
1710     sampler_state = pp_context->sampler_state_table.bo->virtual;
1711
1712     /* SIMD16 Y index 1 */
1713     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1714     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1715     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1716     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1717     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1718
1719     /* SIMD16 UV index 2 */
1720     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1721     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1722     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1723     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1724     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1725
1726     dri_bo_unmap(pp_context->sampler_state_table.bo);
1727
1728     /* private function & data */
1729     pp_context->pp_x_steps = pp_scaling_x_steps;
1730     pp_context->pp_y_steps = pp_scaling_y_steps;
1731     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1732
1733     pp_scaling_context->dest_x = dst_rect->x;
1734     pp_scaling_context->dest_y = dst_rect->y;
1735     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1736     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1737     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1738     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1739
1740     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1741
1742     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1743     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1744     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1745     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1746     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1747
1748     dst_surface->flags = src_surface->flags;
1749
1750     return VA_STATUS_SUCCESS;
1751 }
1752
1753 static int
1754 pp_avs_x_steps(void *private_context)
1755 {
1756     struct pp_avs_context *pp_avs_context = private_context;
1757
1758     return pp_avs_context->dest_w / 16;
1759 }
1760
1761 static int
1762 pp_avs_y_steps(void *private_context)
1763 {
1764     return 1;
1765 }
1766
1767 static int
1768 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1769 {
1770     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1771     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1772     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1773     float src_x_steping, src_y_steping, video_step_delta;
1774     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1775
1776     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1777         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1778         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1779     } else if (tmp_w >= pp_avs_context->dest_w) {
1780         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1781         pp_inline_parameter->grf6.video_step_delta = 0;
1782
1783         if (x == 0) {
1784             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1785                 pp_avs_context->src_normalized_x;
1786         } else {
1787             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1788             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1789             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1790                 16 * 15 * video_step_delta / 2;
1791         }
1792     } else {
1793         int n0, n1, n2, nls_left, nls_right;
1794         int factor_a = 5, factor_b = 4;
1795         float f;
1796
1797         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1798         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1799         n2 = tmp_w / (16 * factor_a);
1800         nls_left = n0 + n2;
1801         nls_right = n1 + n2;
1802         f = (float) n2 * 16 / tmp_w;
1803
1804         if (n0 < 5) {
1805             pp_inline_parameter->grf6.video_step_delta = 0.0;
1806
1807             if (x == 0) {
1808                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1809                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1810             } else {
1811                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1812                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1813                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1814                     16 * 15 * video_step_delta / 2;
1815             }
1816         } else {
1817             if (x < nls_left) {
1818                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1819                 float a = f / (nls_left * 16 * factor_b);
1820                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1821
1822                 pp_inline_parameter->grf6.video_step_delta = b;
1823
1824                 if (x == 0) {
1825                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1826                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1827                 } else {
1828                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1829                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1830                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1831                         16 * 15 * video_step_delta / 2;
1832                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1833                 }
1834             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1835                 /* scale the center linearly */
1836                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1837                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1838                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1839                     16 * 15 * video_step_delta / 2;
1840                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1841                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1842             } else {
1843                 float a = f / (nls_right * 16 * factor_b);
1844                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1845
1846                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1847                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1848                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1849                     16 * 15 * video_step_delta / 2;
1850                 pp_inline_parameter->grf6.video_step_delta = -b;
1851
1852                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1853                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1854                 else
1855                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1856             }
1857         }
1858     }
1859
1860     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1861     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1862     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1863     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1864
1865     return 0;
1866 }
1867
1868 static VAStatus
1869 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1870                        const struct i965_surface *src_surface,
1871                        const VARectangle *src_rect,
1872                        struct i965_surface *dst_surface,
1873                        const VARectangle *dst_rect,
1874                        void *filter_param,
1875                        int nlas)
1876 {
1877     struct i965_driver_data *i965 = i965_driver_data(ctx);
1878     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1879     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1880     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1881     struct object_surface *obj_surface;
1882     struct i965_sampler_8x8 *sampler_8x8;
1883     struct i965_sampler_8x8_state *sampler_8x8_state;
1884     int index;
1885     int in_w, in_h, in_wpitch, in_hpitch;
1886     int out_w, out_h, out_wpitch, out_hpitch;
1887     int i;
1888
1889     /* surface */
1890     obj_surface = SURFACE(src_surface->id);
1891     in_w = obj_surface->orig_width;
1892     in_h = obj_surface->orig_height;
1893     in_wpitch = obj_surface->width;
1894     in_hpitch = obj_surface->height;
1895
1896     /* source Y surface index 1 */
1897     i965_pp_set_surface2_state(ctx, pp_context,
1898                                obj_surface->bo, 0,
1899                                in_w, in_h, in_wpitch,
1900                                0, 0,
1901                                SURFACE_FORMAT_Y8_UNORM, 0,
1902                                1);
1903
1904     /* source UV surface index 2 */
1905     i965_pp_set_surface2_state(ctx, pp_context,
1906                                obj_surface->bo, in_wpitch * in_hpitch,
1907                                in_w / 2, in_h / 2, in_wpitch,
1908                                0, 0,
1909                                SURFACE_FORMAT_R8B8_UNORM, 0,
1910                                2);
1911
1912     /* destination surface */
1913     obj_surface = SURFACE(dst_surface->id);
1914     out_w = obj_surface->orig_width;
1915     out_h = obj_surface->orig_height;
1916     out_wpitch = obj_surface->width;
1917     out_hpitch = obj_surface->height;
1918     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1919
1920     /* destination Y surface index 7 */
1921     i965_pp_set_surface_state(ctx, pp_context,
1922                               obj_surface->bo, 0,
1923                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1924                               7, 1);
1925
1926     /* destination UV surface index 8 */
1927     i965_pp_set_surface_state(ctx, pp_context,
1928                               obj_surface->bo, out_wpitch * out_hpitch,
1929                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1930                               8, 1);
1931
1932     /* sampler 8x8 state */
1933     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1934     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1935     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1936     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1937     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1938
1939     for (i = 0; i < 17; i++) {
1940         /* for Y channel, currently ignore */
1941         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1942         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1943         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1944         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1945         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1946         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1947         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1948         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1949         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1950         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1951         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1952         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1953         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1954         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1955         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1956         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1957         /* for U/V channel, 0.25 */
1958         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1959         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1960         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1961         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1962         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1963         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1964         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1965         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1966         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1967         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1968         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1969         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1970         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1971         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1972         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1973         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1974     }
1975
1976     sampler_8x8_state->dw136.default_sharpness_level = 0;
1977     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1978     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1979     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1980     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1981
1982     /* sampler 8x8 */
1983     dri_bo_map(pp_context->sampler_state_table.bo, True);
1984     assert(pp_context->sampler_state_table.bo->virtual);
1985     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1986     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1987
1988     /* sample_8x8 Y index 1 */
1989     index = 1;
1990     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1991     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1992     sampler_8x8[index].dw0.ief_bypass = 1;
1993     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1994     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1995     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1996     sampler_8x8[index].dw2.global_noise_estimation = 22;
1997     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1998     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1999     sampler_8x8[index].dw3.strong_edge_weight = 7;
2000     sampler_8x8[index].dw3.regular_weight = 2;
2001     sampler_8x8[index].dw3.non_edge_weight = 0;
2002     sampler_8x8[index].dw3.gain_factor = 40;
2003     sampler_8x8[index].dw4.steepness_boost = 0;
2004     sampler_8x8[index].dw4.steepness_threshold = 0;
2005     sampler_8x8[index].dw4.mr_boost = 0;
2006     sampler_8x8[index].dw4.mr_threshold = 5;
2007     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2008     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2009     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2010     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2011     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2012     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2013     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2014     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2015     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2016     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2017     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2018     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2019     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2020     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2021     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2022     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2023     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2024     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2025     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2026     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2027     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2028     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2029     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2030     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2031     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2032     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2033     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2034     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2035     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2036     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2037     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2038     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2039     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2040     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2041     sampler_8x8[index].dw13.limiter_boost = 0;
2042     sampler_8x8[index].dw13.minimum_limiter = 10;
2043     sampler_8x8[index].dw13.maximum_limiter = 11;
2044     sampler_8x8[index].dw14.clip_limiter = 130;
2045     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2046                       I915_GEM_DOMAIN_RENDER,
2047                       0,
2048                       0,
2049                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2050                       pp_context->sampler_state_table.bo_8x8);
2051
2052     /* sample_8x8 UV index 2 */
2053     index = 2;
2054     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2055     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2056     sampler_8x8[index].dw0.ief_bypass = 1;
2057     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2058     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2059     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2060     sampler_8x8[index].dw2.global_noise_estimation = 22;
2061     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2062     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2063     sampler_8x8[index].dw3.strong_edge_weight = 7;
2064     sampler_8x8[index].dw3.regular_weight = 2;
2065     sampler_8x8[index].dw3.non_edge_weight = 0;
2066     sampler_8x8[index].dw3.gain_factor = 40;
2067     sampler_8x8[index].dw4.steepness_boost = 0;
2068     sampler_8x8[index].dw4.steepness_threshold = 0;
2069     sampler_8x8[index].dw4.mr_boost = 0;
2070     sampler_8x8[index].dw4.mr_threshold = 5;
2071     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2072     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2073     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2074     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2075     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2076     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2077     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2078     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2079     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2080     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2081     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2082     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2083     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2084     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2085     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2086     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2087     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2088     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2089     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2090     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2091     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2092     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2093     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2094     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2095     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2096     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2097     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2098     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2099     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2100     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2101     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2102     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2103     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2104     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2105     sampler_8x8[index].dw13.limiter_boost = 0;
2106     sampler_8x8[index].dw13.minimum_limiter = 10;
2107     sampler_8x8[index].dw13.maximum_limiter = 11;
2108     sampler_8x8[index].dw14.clip_limiter = 130;
2109     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2110                       I915_GEM_DOMAIN_RENDER,
2111                       0,
2112                       0,
2113                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2114                       pp_context->sampler_state_table.bo_8x8);
2115
2116     dri_bo_unmap(pp_context->sampler_state_table.bo);
2117
2118     /* private function & data */
2119     pp_context->pp_x_steps = pp_avs_x_steps;
2120     pp_context->pp_y_steps = pp_avs_y_steps;
2121     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2122
2123     pp_avs_context->dest_x = dst_rect->x;
2124     pp_avs_context->dest_y = dst_rect->y;
2125     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2126     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2127     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2128     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2129     pp_avs_context->src_w = src_rect->width;
2130     pp_avs_context->src_h = src_rect->height;
2131
2132     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2133     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2134
2135     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2136     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2137     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2138     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2139     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2140     pp_inline_parameter->grf6.video_step_delta = 0.0;
2141
2142     dst_surface->flags = src_surface->flags;
2143
2144     return VA_STATUS_SUCCESS;
2145 }
2146
2147 static VAStatus
2148 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2149                             const struct i965_surface *src_surface,
2150                             const VARectangle *src_rect,
2151                             struct i965_surface *dst_surface,
2152                             const VARectangle *dst_rect,
2153                             void *filter_param)
2154 {
2155     return pp_nv12_avs_initialize(ctx, pp_context,
2156                                   src_surface,
2157                                   src_rect,
2158                                   dst_surface,
2159                                   dst_rect,
2160                                   filter_param,
2161                                   1);
2162 }
2163
2164 static VAStatus
2165 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2166                              const struct i965_surface *src_surface,
2167                              const VARectangle *src_rect,
2168                              struct i965_surface *dst_surface,
2169                              const VARectangle *dst_rect,
2170                              void *filter_param)
2171 {
2172     return pp_nv12_avs_initialize(ctx, pp_context,
2173                                   src_surface,
2174                                   src_rect,
2175                                   dst_surface,
2176                                   dst_rect,
2177                                   filter_param,
2178                                   0);
2179 }
2180
2181 static int
2182 gen7_pp_avs_x_steps(void *private_context)
2183 {
2184     struct pp_avs_context *pp_avs_context = private_context;
2185
2186     return pp_avs_context->dest_w / 16;
2187 }
2188
2189 static int
2190 gen7_pp_avs_y_steps(void *private_context)
2191 {
2192     struct pp_avs_context *pp_avs_context = private_context;
2193
2194     return pp_avs_context->dest_h / 16;
2195 }
2196
2197 static int
2198 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2199 {
2200     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2201     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2202
2203     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2204     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2205     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2206     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2207
2208     return 0;
2209 }
2210
2211 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2212                                               struct i965_post_processing_context *pp_context,
2213                                               const struct i965_surface *surface)
2214 {
2215     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2216     int fourcc = pp_get_surface_fourcc(ctx, surface);
2217
2218     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2219         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2220         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2221         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2222     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2223         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2224         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2225         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2226     }
2227 }
2228
2229 static VAStatus
2230 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2231                            const struct i965_surface *src_surface,
2232                            const VARectangle *src_rect,
2233                            struct i965_surface *dst_surface,
2234                            const VARectangle *dst_rect,
2235                            void *filter_param)
2236 {
2237     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2238     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2239     struct gen7_sampler_8x8 *sampler_8x8;
2240     struct i965_sampler_8x8_state *sampler_8x8_state;
2241     int index, i;
2242     int width[3], height[3], pitch[3], offset[3];
2243
2244     /* source surface */
2245     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2246                                          width, height, pitch, offset);
2247
2248     /* destination surface */
2249     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2250                                          width, height, pitch, offset);
2251
2252     /* sampler 8x8 state */
2253     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2254     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2255     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2256     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2257     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2258
2259     for (i = 0; i < 17; i++) {
2260         /* for Y channel, currently ignore */
2261         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2262         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2263         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2264         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2265         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2266         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2267         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2268         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2269         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2270         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2271         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2272         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2273         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2274         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2275         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2276         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2277         /* for U/V channel, 0.25 */
2278         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2279         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2280         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2281         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2282         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2283         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2284         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2285         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2286         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2287         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2288         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2289         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2290         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2291         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2292         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2293         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2294     }
2295
2296     sampler_8x8_state->dw136.default_sharpness_level = 0;
2297     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2298     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2299     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2300     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2301
2302     /* sampler 8x8 */
2303     dri_bo_map(pp_context->sampler_state_table.bo, True);
2304     assert(pp_context->sampler_state_table.bo->virtual);
2305     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2306     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2307
2308     /* sample_8x8 Y index 4 */
2309     index = 4;
2310     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2311     sampler_8x8[index].dw0.global_noise_estimation = 255;
2312     sampler_8x8[index].dw0.ief_bypass = 1;
2313
2314     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2315
2316     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2317     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2318     sampler_8x8[index].dw2.r5x_coefficient = 9;
2319     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2320     sampler_8x8[index].dw2.r5c_coefficient = 3;
2321
2322     sampler_8x8[index].dw3.r3x_coefficient = 27;
2323     sampler_8x8[index].dw3.r3c_coefficient = 5;
2324     sampler_8x8[index].dw3.gain_factor = 40;
2325     sampler_8x8[index].dw3.non_edge_weight = 1;
2326     sampler_8x8[index].dw3.regular_weight = 2;
2327     sampler_8x8[index].dw3.strong_edge_weight = 7;
2328     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2329
2330     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2331                       I915_GEM_DOMAIN_RENDER,
2332                       0,
2333                       0,
2334                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2335                       pp_context->sampler_state_table.bo_8x8);
2336
2337     /* sample_8x8 UV index 8 */
2338     index = 8;
2339     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2340     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2341     sampler_8x8[index].dw0.global_noise_estimation = 255;
2342     sampler_8x8[index].dw0.ief_bypass = 1;
2343     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2344     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2345     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2346     sampler_8x8[index].dw2.r5x_coefficient = 9;
2347     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2348     sampler_8x8[index].dw2.r5c_coefficient = 3;
2349     sampler_8x8[index].dw3.r3x_coefficient = 27;
2350     sampler_8x8[index].dw3.r3c_coefficient = 5;
2351     sampler_8x8[index].dw3.gain_factor = 40;
2352     sampler_8x8[index].dw3.non_edge_weight = 1;
2353     sampler_8x8[index].dw3.regular_weight = 2;
2354     sampler_8x8[index].dw3.strong_edge_weight = 7;
2355     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2356
2357     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2358                       I915_GEM_DOMAIN_RENDER,
2359                       0,
2360                       0,
2361                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2362                       pp_context->sampler_state_table.bo_8x8);
2363
2364     /* sampler_8x8 V, index 12 */
2365     index = 12;
2366     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2367     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2368     sampler_8x8[index].dw0.global_noise_estimation = 255;
2369     sampler_8x8[index].dw0.ief_bypass = 1;
2370     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2371     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2372     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2373     sampler_8x8[index].dw2.r5x_coefficient = 9;
2374     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2375     sampler_8x8[index].dw2.r5c_coefficient = 3;
2376     sampler_8x8[index].dw3.r3x_coefficient = 27;
2377     sampler_8x8[index].dw3.r3c_coefficient = 5;
2378     sampler_8x8[index].dw3.gain_factor = 40;
2379     sampler_8x8[index].dw3.non_edge_weight = 1;
2380     sampler_8x8[index].dw3.regular_weight = 2;
2381     sampler_8x8[index].dw3.strong_edge_weight = 7;
2382     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2383
2384     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2385                       I915_GEM_DOMAIN_RENDER,
2386                       0,
2387                       0,
2388                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2389                       pp_context->sampler_state_table.bo_8x8);
2390
2391     dri_bo_unmap(pp_context->sampler_state_table.bo);
2392
2393     /* private function & data */
2394     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2395     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2396     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2397
2398     pp_avs_context->dest_x = dst_rect->x;
2399     pp_avs_context->dest_y = dst_rect->y;
2400     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2401     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2402     pp_avs_context->src_w = src_rect->width;
2403     pp_avs_context->src_h = src_rect->height;
2404
2405     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2406     dw = MAX(dw, pp_avs_context->dest_w);
2407
2408     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2409     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2410     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2411     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2412     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2413
2414     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2415
2416     dst_surface->flags = src_surface->flags;
2417
2418     return VA_STATUS_SUCCESS;
2419 }
2420
2421 static int
2422 pp_dndi_x_steps(void *private_context)
2423 {
2424     return 1;
2425 }
2426
2427 static int
2428 pp_dndi_y_steps(void *private_context)
2429 {
2430     struct pp_dndi_context *pp_dndi_context = private_context;
2431
2432     return pp_dndi_context->dest_h / 4;
2433 }
2434
2435 static int
2436 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2437 {
2438     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2439
2440     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2441     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2442
2443     return 0;
2444 }
2445
2446 static VAStatus
2447 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2448                         const struct i965_surface *src_surface,
2449                         const VARectangle *src_rect,
2450                         struct i965_surface *dst_surface,
2451                         const VARectangle *dst_rect,
2452                         void *filter_param)
2453 {
2454     struct i965_driver_data *i965 = i965_driver_data(ctx);
2455     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2456     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2457     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2458     struct object_surface *obj_surface;
2459     struct i965_sampler_dndi *sampler_dndi;
2460     int index;
2461     int w, h;
2462     int orig_w, orig_h;
2463     int dndi_top_first = 1;
2464
2465     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2466         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2467
2468     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2469         dndi_top_first = 1;
2470     else
2471         dndi_top_first = 0;
2472
2473     /* surface */
2474     obj_surface = SURFACE(src_surface->id);
2475     orig_w = obj_surface->orig_width;
2476     orig_h = obj_surface->orig_height;
2477     w = obj_surface->width;
2478     h = obj_surface->height;
2479
2480     if (pp_context->stmm.bo == NULL) {
2481         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2482                                            "STMM surface",
2483                                            w * h,
2484                                            4096);
2485         assert(pp_context->stmm.bo);
2486     }
2487
2488     /* source UV surface index 2 */
2489     i965_pp_set_surface_state(ctx, pp_context,
2490                               obj_surface->bo, w * h,
2491                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2492                               2, 0);
2493
2494     /* source YUV surface index 4 */
2495     i965_pp_set_surface2_state(ctx, pp_context,
2496                                obj_surface->bo, 0,
2497                                orig_w, orig_h, w,
2498                                0, h,
2499                                SURFACE_FORMAT_PLANAR_420_8, 1,
2500                                4);
2501
2502     /* source STMM surface index 20 */
2503     i965_pp_set_surface_state(ctx, pp_context,
2504                               pp_context->stmm.bo, 0,
2505                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2506                               20, 1);
2507
2508     /* destination surface */
2509     obj_surface = SURFACE(dst_surface->id);
2510     orig_w = obj_surface->orig_width;
2511     orig_h = obj_surface->orig_height;
2512     w = obj_surface->width;
2513     h = obj_surface->height;
2514
2515     /* destination Y surface index 7 */
2516     i965_pp_set_surface_state(ctx, pp_context,
2517                               obj_surface->bo, 0,
2518                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2519                               7, 1);
2520
2521     /* destination UV surface index 8 */
2522     i965_pp_set_surface_state(ctx, pp_context,
2523                               obj_surface->bo, w * h,
2524                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2525                               8, 1);
2526     /* sampler dndi */
2527     dri_bo_map(pp_context->sampler_state_table.bo, True);
2528     assert(pp_context->sampler_state_table.bo->virtual);
2529     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2530     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2531
2532     /* sample dndi index 1 */
2533     index = 0;
2534     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2535     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2536     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2537     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2538
2539     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2540     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2541     sampler_dndi[index].dw1.stmm_c2 = 1;
2542     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2543     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2544
2545     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2546     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2547     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2548     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2549
2550     sampler_dndi[index].dw3.maximum_stmm = 128;
2551     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2552     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2553     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2554     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2555
2556     sampler_dndi[index].dw4.sdi_delta = 8;
2557     sampler_dndi[index].dw4.sdi_threshold = 128;
2558     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2559     sampler_dndi[index].dw4.stmm_shift_up = 0;
2560     sampler_dndi[index].dw4.stmm_shift_down = 0;
2561     sampler_dndi[index].dw4.minimum_stmm = 0;
2562
2563     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2564     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2565     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2566     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2567
2568     sampler_dndi[index].dw6.dn_enable = 1;
2569     sampler_dndi[index].dw6.di_enable = 1;
2570     sampler_dndi[index].dw6.di_partial = 0;
2571     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2572     sampler_dndi[index].dw6.dndi_stream_id = 0;
2573     sampler_dndi[index].dw6.dndi_first_frame = 1;
2574     sampler_dndi[index].dw6.progressive_dn = 0;
2575     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2576     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2577     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2578
2579     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2580     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2581     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2582     sampler_dndi[index].dw7.column_width_minus1 = 0;
2583
2584     dri_bo_unmap(pp_context->sampler_state_table.bo);
2585
2586     /* private function & data */
2587     pp_context->pp_x_steps = pp_dndi_x_steps;
2588     pp_context->pp_y_steps = pp_dndi_y_steps;
2589     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2590
2591     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2592     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2593     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2594     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2595
2596     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2597     pp_inline_parameter->grf5.number_blocks = w / 16;
2598     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2599     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2600
2601     pp_dndi_context->dest_w = w;
2602     pp_dndi_context->dest_h = h;
2603
2604     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2605
2606     return VA_STATUS_SUCCESS;
2607 }
2608
2609 static int
2610 pp_dn_x_steps(void *private_context)
2611 {
2612     return 1;
2613 }
2614
2615 static int
2616 pp_dn_y_steps(void *private_context)
2617 {
2618     struct pp_dn_context *pp_dn_context = private_context;
2619
2620     return pp_dn_context->dest_h / 8;
2621 }
2622
2623 static int
2624 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2625 {
2626     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2627
2628     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2629     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2630
2631     return 0;
2632 }
2633
2634 static VAStatus
2635 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2636                       const struct i965_surface *src_surface,
2637                       const VARectangle *src_rect,
2638                       struct i965_surface *dst_surface,
2639                       const VARectangle *dst_rect,
2640                       void *filter_param)
2641 {
2642     struct i965_driver_data *i965 = i965_driver_data(ctx);
2643     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2644     struct object_surface *obj_surface;
2645     struct i965_sampler_dndi *sampler_dndi;
2646     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2647     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2648     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2649     int index;
2650     int w, h;
2651     int orig_w, orig_h;
2652     int dn_strength = 15;
2653     int dndi_top_first = 1;
2654     int dn_progressive = 0;
2655
2656     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2657         dndi_top_first = 1;
2658         dn_progressive = 1;
2659     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2660         dndi_top_first = 1;
2661         dn_progressive = 0;
2662     } else {
2663         dndi_top_first = 0;
2664         dn_progressive = 0;
2665     }
2666
2667     if (dn_filter_param) {
2668         float value = dn_filter_param->value;
2669
2670         if (value > 1.0)
2671             value = 1.0;
2672
2673         if (value < 0.0)
2674             value = 0.0;
2675
2676         dn_strength = (int)(value * 31.0F);
2677     }
2678
2679     /* surface */
2680     obj_surface = SURFACE(src_surface->id);
2681     orig_w = obj_surface->orig_width;
2682     orig_h = obj_surface->orig_height;
2683     w = obj_surface->width;
2684     h = obj_surface->height;
2685
2686     if (pp_context->stmm.bo == NULL) {
2687         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2688                                            "STMM surface",
2689                                            w * h,
2690                                            4096);
2691         assert(pp_context->stmm.bo);
2692     }
2693
2694     /* source UV surface index 2 */
2695     i965_pp_set_surface_state(ctx, pp_context,
2696                               obj_surface->bo, w * h,
2697                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2698                               2, 0);
2699
2700     /* source YUV surface index 4 */
2701     i965_pp_set_surface2_state(ctx, pp_context,
2702                                obj_surface->bo, 0,
2703                                orig_w, orig_h, w,
2704                                0, h,
2705                                SURFACE_FORMAT_PLANAR_420_8, 1,
2706                                4);
2707
2708     /* source STMM surface index 20 */
2709     i965_pp_set_surface_state(ctx, pp_context,
2710                               pp_context->stmm.bo, 0,
2711                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2712                               20, 1);
2713
2714     /* destination surface */
2715     obj_surface = SURFACE(dst_surface->id);
2716     orig_w = obj_surface->orig_width;
2717     orig_h = obj_surface->orig_height;
2718     w = obj_surface->width;
2719     h = obj_surface->height;
2720
2721     /* destination Y surface index 7 */
2722     i965_pp_set_surface_state(ctx, pp_context,
2723                               obj_surface->bo, 0,
2724                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2725                               7, 1);
2726
2727     /* destination UV surface index 8 */
2728     i965_pp_set_surface_state(ctx, pp_context,
2729                               obj_surface->bo, w * h,
2730                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2731                               8, 1);
2732     /* sampler dn */
2733     dri_bo_map(pp_context->sampler_state_table.bo, True);
2734     assert(pp_context->sampler_state_table.bo->virtual);
2735     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2736     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2737
2738     /* sample dndi index 1 */
2739     index = 0;
2740     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2741     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2742     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2743     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2744
2745     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2746     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2747     sampler_dndi[index].dw1.stmm_c2 = 0;
2748     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2749     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2750
2751     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2752     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2753     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2754     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2755
2756     sampler_dndi[index].dw3.maximum_stmm = 128;
2757     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2758     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2759     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2760     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2761
2762     sampler_dndi[index].dw4.sdi_delta = 8;
2763     sampler_dndi[index].dw4.sdi_threshold = 128;
2764     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2765     sampler_dndi[index].dw4.stmm_shift_up = 0;
2766     sampler_dndi[index].dw4.stmm_shift_down = 0;
2767     sampler_dndi[index].dw4.minimum_stmm = 0;
2768
2769     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2770     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2771     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2772     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2773
2774     sampler_dndi[index].dw6.dn_enable = 1;
2775     sampler_dndi[index].dw6.di_enable = 0;
2776     sampler_dndi[index].dw6.di_partial = 0;
2777     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2778     sampler_dndi[index].dw6.dndi_stream_id = 1;
2779     sampler_dndi[index].dw6.dndi_first_frame = 1;
2780     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2781     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2782     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2783     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2784
2785     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2786     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2787     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2788     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2789
2790     dri_bo_unmap(pp_context->sampler_state_table.bo);
2791
2792     /* private function & data */
2793     pp_context->pp_x_steps = pp_dn_x_steps;
2794     pp_context->pp_y_steps = pp_dn_y_steps;
2795     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2796
2797     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2798     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2799     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2800     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2801
2802     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2803     pp_inline_parameter->grf5.number_blocks = w / 16;
2804     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2805     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2806
2807     pp_dn_context->dest_w = w;
2808     pp_dn_context->dest_h = h;
2809
2810     dst_surface->flags = src_surface->flags;
2811
2812     return VA_STATUS_SUCCESS;
2813 }
2814
2815 static int
2816 gen7_pp_dndi_x_steps(void *private_context)
2817 {
2818     struct pp_dndi_context *pp_dndi_context = private_context;
2819
2820     return pp_dndi_context->dest_w / 16;
2821 }
2822
2823 static int
2824 gen7_pp_dndi_y_steps(void *private_context)
2825 {
2826     struct pp_dndi_context *pp_dndi_context = private_context;
2827
2828     return pp_dndi_context->dest_h / 4;
2829 }
2830
2831 static int
2832 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2833 {
2834     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2835
2836     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2837     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2838
2839     return 0;
2840 }
2841
2842 static VAStatus
2843 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2844                              const struct i965_surface *src_surface,
2845                              const VARectangle *src_rect,
2846                              struct i965_surface *dst_surface,
2847                              const VARectangle *dst_rect,
2848                              void *filter_param)
2849 {
2850     struct i965_driver_data *i965 = i965_driver_data(ctx);
2851     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2852     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2853     struct object_surface *obj_surface;
2854     struct gen7_sampler_dndi *sampler_dndi;
2855     int index;
2856     int w, h;
2857     int orig_w, orig_h;
2858     int dndi_top_first = 1;
2859
2860     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2861         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2862
2863     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2864         dndi_top_first = 1;
2865     else
2866         dndi_top_first = 0;
2867
2868     /* surface */
2869     obj_surface = SURFACE(src_surface->id);
2870     orig_w = obj_surface->orig_width;
2871     orig_h = obj_surface->orig_height;
2872     w = obj_surface->width;
2873     h = obj_surface->height;
2874
2875     if (pp_context->stmm.bo == NULL) {
2876         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2877                                            "STMM surface",
2878                                            w * h,
2879                                            4096);
2880         assert(pp_context->stmm.bo);
2881     }
2882
2883     /* source UV surface index 1 */
2884     gen7_pp_set_surface_state(ctx, pp_context,
2885                               obj_surface->bo, w * h,
2886                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2887                               1, 0);
2888
2889     /* source YUV surface index 3 */
2890     gen7_pp_set_surface2_state(ctx, pp_context,
2891                                obj_surface->bo, 0,
2892                                orig_w, orig_h, w,
2893                                0, h,
2894                                SURFACE_FORMAT_PLANAR_420_8, 1,
2895                                3);
2896
2897     /* source (temporal reference) YUV surface index 4 */
2898     gen7_pp_set_surface2_state(ctx, pp_context,
2899                                obj_surface->bo, 0,
2900                                orig_w, orig_h, w,
2901                                0, h,
2902                                SURFACE_FORMAT_PLANAR_420_8, 1,
2903                                4);
2904
2905     /* STMM / History Statistics input surface, index 5 */
2906     gen7_pp_set_surface_state(ctx, pp_context,
2907                               pp_context->stmm.bo, 0,
2908                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2909                               5, 1);
2910
2911     /* destination surface */
2912     obj_surface = SURFACE(dst_surface->id);
2913     orig_w = obj_surface->orig_width;
2914     orig_h = obj_surface->orig_height;
2915     w = obj_surface->width;
2916     h = obj_surface->height;
2917
2918     /* destination(Previous frame) Y surface index 27 */
2919     gen7_pp_set_surface_state(ctx, pp_context,
2920                               obj_surface->bo, 0,
2921                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2922                               27, 1);
2923
2924     /* destination(Previous frame) UV surface index 28 */
2925     gen7_pp_set_surface_state(ctx, pp_context,
2926                               obj_surface->bo, w * h,
2927                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2928                               28, 1);
2929
2930     /* destination(Current frame) Y surface index 30 */
2931     gen7_pp_set_surface_state(ctx, pp_context,
2932                               obj_surface->bo, 0,
2933                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2934                               30, 1);
2935
2936     /* destination(Current frame) UV surface index 31 */
2937     gen7_pp_set_surface_state(ctx, pp_context,
2938                               obj_surface->bo, w * h,
2939                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2940                               31, 1);
2941
2942     /* STMM output surface, index 33 */
2943     gen7_pp_set_surface_state(ctx, pp_context,
2944                               pp_context->stmm.bo, 0,
2945                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2946                               33, 1);
2947
2948
2949     /* sampler dndi */
2950     dri_bo_map(pp_context->sampler_state_table.bo, True);
2951     assert(pp_context->sampler_state_table.bo->virtual);
2952     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2953     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2954
2955     /* sample dndi index 0 */
2956     index = 0;
2957     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2958     sampler_dndi[index].dw0.dnmh_delt = 8;
2959     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2960     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2961     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2962     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2963
2964     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2965     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2966     sampler_dndi[index].dw1.stmm_c2 = 0;
2967     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2968     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2969
2970     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2971     sampler_dndi[index].dw2.bne_edge_th = 1;
2972     sampler_dndi[index].dw2.smooth_mv_th = 0;
2973     sampler_dndi[index].dw2.sad_tight_th = 5;
2974     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2975     sampler_dndi[index].dw2.good_neighbor_th = 4;
2976
2977     sampler_dndi[index].dw3.maximum_stmm = 128;
2978     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2979     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2980     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2981     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2982
2983     sampler_dndi[index].dw4.sdi_delta = 8;
2984     sampler_dndi[index].dw4.sdi_threshold = 128;
2985     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2986     sampler_dndi[index].dw4.stmm_shift_up = 0;
2987     sampler_dndi[index].dw4.stmm_shift_down = 0;
2988     sampler_dndi[index].dw4.minimum_stmm = 0;
2989
2990     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2991     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2992     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2993     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2994
2995     sampler_dndi[index].dw6.dn_enable = 0;
2996     sampler_dndi[index].dw6.di_enable = 1;
2997     sampler_dndi[index].dw6.di_partial = 0;
2998     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2999     sampler_dndi[index].dw6.dndi_stream_id = 1;
3000     sampler_dndi[index].dw6.dndi_first_frame = 1;
3001     sampler_dndi[index].dw6.progressive_dn = 0;
3002     sampler_dndi[index].dw6.mcdi_enable = 0;
3003     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3004     sampler_dndi[index].dw6.cat_th1 = 0;
3005     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3006     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3007
3008     sampler_dndi[index].dw7.sad_tha = 5;
3009     sampler_dndi[index].dw7.sad_thb = 10;
3010     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3011     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3012     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3013     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3014     sampler_dndi[index].dw7.neighborpixel_th = 10;
3015     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3016
3017     dri_bo_unmap(pp_context->sampler_state_table.bo);
3018
3019     /* private function & data */
3020     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3021     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3022     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3023
3024     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3025     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3026     pp_static_parameter->grf1.di_top_field_first = 0;
3027     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3028
3029     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3030     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3031     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3032
3033     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3034     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3035
3036     pp_dndi_context->dest_w = w;
3037     pp_dndi_context->dest_h = h;
3038
3039     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3040
3041     return VA_STATUS_SUCCESS;
3042 }
3043
3044 static int
3045 gen7_pp_dn_x_steps(void *private_context)
3046 {
3047     return 1;
3048 }
3049
3050 static int
3051 gen7_pp_dn_y_steps(void *private_context)
3052 {
3053     struct pp_dn_context *pp_dn_context = private_context;
3054
3055     return pp_dn_context->dest_h / 4;
3056 }
3057
3058 static int
3059 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3060 {
3061     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3062
3063     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3064     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3065
3066     return 0;
3067 }
3068
3069 static VAStatus
3070 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3071                            const struct i965_surface *src_surface,
3072                            const VARectangle *src_rect,
3073                            struct i965_surface *dst_surface,
3074                            const VARectangle *dst_rect,
3075                            void *filter_param)
3076 {
3077     struct i965_driver_data *i965 = i965_driver_data(ctx);
3078     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3079     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3080     struct object_surface *obj_surface;
3081     struct gen7_sampler_dndi *sampler_dn;
3082     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3083     int index;
3084     int w, h;
3085     int orig_w, orig_h;
3086     int dn_strength = 15;
3087     int dndi_top_first = 1;
3088     int dn_progressive = 0;
3089
3090     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3091         dndi_top_first = 1;
3092         dn_progressive = 1;
3093     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3094         dndi_top_first = 1;
3095         dn_progressive = 0;
3096     } else {
3097         dndi_top_first = 0;
3098         dn_progressive = 0;
3099     }
3100
3101     if (dn_filter_param) {
3102         float value = dn_filter_param->value;
3103
3104         if (value > 1.0)
3105             value = 1.0;
3106
3107         if (value < 0.0)
3108             value = 0.0;
3109
3110         dn_strength = (int)(value * 31.0F);
3111     }
3112
3113     /* surface */
3114     obj_surface = SURFACE(src_surface->id);
3115     orig_w = obj_surface->orig_width;
3116     orig_h = obj_surface->orig_height;
3117     w = obj_surface->width;
3118     h = obj_surface->height;
3119
3120     if (pp_context->stmm.bo == NULL) {
3121         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3122                                            "STMM surface",
3123                                            w * h,
3124                                            4096);
3125         assert(pp_context->stmm.bo);
3126     }
3127
3128     /* source UV surface index 1 */
3129     gen7_pp_set_surface_state(ctx, pp_context,
3130                               obj_surface->bo, w * h,
3131                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3132                               1, 0);
3133
3134     /* source YUV surface index 3 */
3135     gen7_pp_set_surface2_state(ctx, pp_context,
3136                                obj_surface->bo, 0,
3137                                orig_w, orig_h, w,
3138                                0, h,
3139                                SURFACE_FORMAT_PLANAR_420_8, 1,
3140                                3);
3141
3142     /* source STMM surface index 5 */
3143     gen7_pp_set_surface_state(ctx, pp_context,
3144                               pp_context->stmm.bo, 0,
3145                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3146                               5, 1);
3147
3148     /* destination surface */
3149     obj_surface = SURFACE(dst_surface->id);
3150     orig_w = obj_surface->orig_width;
3151     orig_h = obj_surface->orig_height;
3152     w = obj_surface->width;
3153     h = obj_surface->height;
3154
3155     /* destination Y surface index 7 */
3156     gen7_pp_set_surface_state(ctx, pp_context,
3157                               obj_surface->bo, 0,
3158                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3159                               7, 1);
3160
3161     /* destination UV surface index 8 */
3162     gen7_pp_set_surface_state(ctx, pp_context,
3163                               obj_surface->bo, w * h,
3164                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3165                               8, 1);
3166     /* sampler dn */
3167     dri_bo_map(pp_context->sampler_state_table.bo, True);
3168     assert(pp_context->sampler_state_table.bo->virtual);
3169     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3170     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3171
3172     /* sample dn index 1 */
3173     index = 0;
3174     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3175     sampler_dn[index].dw0.dnmh_delt = 8;
3176     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3177     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3178     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3179     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3180
3181     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3182     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3183     sampler_dn[index].dw1.stmm_c2 = 0;
3184     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3185     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3186
3187     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3188     sampler_dn[index].dw2.bne_edge_th = 1;
3189     sampler_dn[index].dw2.smooth_mv_th = 0;
3190     sampler_dn[index].dw2.sad_tight_th = 5;
3191     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3192     sampler_dn[index].dw2.good_neighbor_th = 4;
3193
3194     sampler_dn[index].dw3.maximum_stmm = 128;
3195     sampler_dn[index].dw3.multipler_for_vecm = 2;
3196     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3197     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3198     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3199
3200     sampler_dn[index].dw4.sdi_delta = 8;
3201     sampler_dn[index].dw4.sdi_threshold = 128;
3202     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3203     sampler_dn[index].dw4.stmm_shift_up = 0;
3204     sampler_dn[index].dw4.stmm_shift_down = 0;
3205     sampler_dn[index].dw4.minimum_stmm = 0;
3206
3207     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3208     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3209     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3210     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3211
3212     sampler_dn[index].dw6.dn_enable = 1;
3213     sampler_dn[index].dw6.di_enable = 0;
3214     sampler_dn[index].dw6.di_partial = 0;
3215     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3216     sampler_dn[index].dw6.dndi_stream_id = 1;
3217     sampler_dn[index].dw6.dndi_first_frame = 1;
3218     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3219     sampler_dn[index].dw6.mcdi_enable = 0;
3220     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3221     sampler_dn[index].dw6.cat_th1 = 0;
3222     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3223     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3224
3225     sampler_dn[index].dw7.sad_tha = 5;
3226     sampler_dn[index].dw7.sad_thb = 10;
3227     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3228     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3229     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3230     sampler_dn[index].dw7.vdi_walker_enable = 0;
3231     sampler_dn[index].dw7.neighborpixel_th = 10;
3232     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3233
3234     dri_bo_unmap(pp_context->sampler_state_table.bo);
3235
3236     /* private function & data */
3237     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3238     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3239     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3240
3241     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3242     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3243     pp_static_parameter->grf1.di_top_field_first = 0;
3244     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3245
3246     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3247     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3248     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3249
3250     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3251     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3252
3253     pp_dn_context->dest_w = w;
3254     pp_dn_context->dest_h = h;
3255
3256     dst_surface->flags = src_surface->flags;
3257
3258     return VA_STATUS_SUCCESS;
3259 }
3260
3261 static VAStatus
3262 ironlake_pp_initialize(
3263     VADriverContextP   ctx,
3264     struct i965_post_processing_context *pp_context,
3265     const struct i965_surface *src_surface,
3266     const VARectangle *src_rect,
3267     struct i965_surface *dst_surface,
3268     const VARectangle *dst_rect,
3269     int                pp_index,
3270     void *filter_param
3271 )
3272 {
3273     VAStatus va_status;
3274     struct i965_driver_data *i965 = i965_driver_data(ctx);
3275     struct pp_module *pp_module;
3276     dri_bo *bo;
3277     int static_param_size, inline_param_size;
3278
3279     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3280     bo = dri_bo_alloc(i965->intel.bufmgr,
3281                       "surface state & binding table",
3282                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3283                       4096);
3284     assert(bo);
3285     pp_context->surface_state_binding_table.bo = bo;
3286
3287     dri_bo_unreference(pp_context->curbe.bo);
3288     bo = dri_bo_alloc(i965->intel.bufmgr,
3289                       "constant buffer",
3290                       4096,
3291                       4096);
3292     assert(bo);
3293     pp_context->curbe.bo = bo;
3294
3295     dri_bo_unreference(pp_context->idrt.bo);
3296     bo = dri_bo_alloc(i965->intel.bufmgr,
3297                       "interface discriptor",
3298                       sizeof(struct i965_interface_descriptor),
3299                       4096);
3300     assert(bo);
3301     pp_context->idrt.bo = bo;
3302     pp_context->idrt.num_interface_descriptors = 0;
3303
3304     dri_bo_unreference(pp_context->sampler_state_table.bo);
3305     bo = dri_bo_alloc(i965->intel.bufmgr,
3306                       "sampler state table",
3307                       4096,
3308                       4096);
3309     assert(bo);
3310     dri_bo_map(bo, True);
3311     memset(bo->virtual, 0, bo->size);
3312     dri_bo_unmap(bo);
3313     pp_context->sampler_state_table.bo = bo;
3314
3315     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3316     bo = dri_bo_alloc(i965->intel.bufmgr,
3317                       "sampler 8x8 state ",
3318                       4096,
3319                       4096);
3320     assert(bo);
3321     pp_context->sampler_state_table.bo_8x8 = bo;
3322
3323     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3324     bo = dri_bo_alloc(i965->intel.bufmgr,
3325                       "sampler 8x8 state ",
3326                       4096,
3327                       4096);
3328     assert(bo);
3329     pp_context->sampler_state_table.bo_8x8_uv = bo;
3330
3331     dri_bo_unreference(pp_context->vfe_state.bo);
3332     bo = dri_bo_alloc(i965->intel.bufmgr,
3333                       "vfe state",
3334                       sizeof(struct i965_vfe_state),
3335                       4096);
3336     assert(bo);
3337     pp_context->vfe_state.bo = bo;
3338
3339     static_param_size = sizeof(struct pp_static_parameter);
3340     inline_param_size = sizeof(struct pp_inline_parameter);
3341
3342     memset(pp_context->pp_static_parameter, 0, static_param_size);
3343     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3344
3345     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3346     pp_context->current_pp = pp_index;
3347     pp_module = &pp_context->pp_modules[pp_index];
3348
3349     if (pp_module->initialize)
3350         va_status = pp_module->initialize(ctx, pp_context,
3351                                           src_surface,
3352                                           src_rect,
3353                                           dst_surface,
3354                                           dst_rect,
3355                                           filter_param);
3356     else
3357         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3358
3359     return va_status;
3360 }
3361
3362 static VAStatus
3363 ironlake_post_processing(
3364     VADriverContextP   ctx,
3365     struct i965_post_processing_context *pp_context,
3366     const struct i965_surface *src_surface,
3367     const VARectangle *src_rect,
3368     struct i965_surface *dst_surface,
3369     const VARectangle *dst_rect,
3370     int                pp_index,
3371     void *filter_param
3372 )
3373 {
3374     VAStatus va_status;
3375
3376     va_status = ironlake_pp_initialize(ctx, pp_context,
3377                                        src_surface,
3378                                        src_rect,
3379                                        dst_surface,
3380                                        dst_rect,
3381                                        pp_index,
3382                                        filter_param);
3383
3384     if (va_status == VA_STATUS_SUCCESS) {
3385         ironlake_pp_states_setup(ctx, pp_context);
3386         ironlake_pp_pipeline_setup(ctx, pp_context);
3387     }
3388
3389     return va_status;
3390 }
3391
3392 static VAStatus
3393 gen6_pp_initialize(
3394     VADriverContextP   ctx,
3395     struct i965_post_processing_context *pp_context,
3396     const struct i965_surface *src_surface,
3397     const VARectangle *src_rect,
3398     struct i965_surface *dst_surface,
3399     const VARectangle *dst_rect,
3400     int                pp_index,
3401     void *filter_param
3402 )
3403 {
3404     VAStatus va_status;
3405     struct i965_driver_data *i965 = i965_driver_data(ctx);
3406     struct pp_module *pp_module;
3407     dri_bo *bo;
3408     int static_param_size, inline_param_size;
3409
3410     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3411     bo = dri_bo_alloc(i965->intel.bufmgr,
3412                       "surface state & binding table",
3413                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3414                       4096);
3415     assert(bo);
3416     pp_context->surface_state_binding_table.bo = bo;
3417
3418     dri_bo_unreference(pp_context->curbe.bo);
3419     bo = dri_bo_alloc(i965->intel.bufmgr,
3420                       "constant buffer",
3421                       4096,
3422                       4096);
3423     assert(bo);
3424     pp_context->curbe.bo = bo;
3425
3426     dri_bo_unreference(pp_context->idrt.bo);
3427     bo = dri_bo_alloc(i965->intel.bufmgr,
3428                       "interface discriptor",
3429                       sizeof(struct gen6_interface_descriptor_data),
3430                       4096);
3431     assert(bo);
3432     pp_context->idrt.bo = bo;
3433     pp_context->idrt.num_interface_descriptors = 0;
3434
3435     dri_bo_unreference(pp_context->sampler_state_table.bo);
3436     bo = dri_bo_alloc(i965->intel.bufmgr,
3437                       "sampler state table",
3438                       4096,
3439                       4096);
3440     assert(bo);
3441     dri_bo_map(bo, True);
3442     memset(bo->virtual, 0, bo->size);
3443     dri_bo_unmap(bo);
3444     pp_context->sampler_state_table.bo = bo;
3445
3446     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3447     bo = dri_bo_alloc(i965->intel.bufmgr,
3448                       "sampler 8x8 state ",
3449                       4096,
3450                       4096);
3451     assert(bo);
3452     pp_context->sampler_state_table.bo_8x8 = bo;
3453
3454     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3455     bo = dri_bo_alloc(i965->intel.bufmgr,
3456                       "sampler 8x8 state ",
3457                       4096,
3458                       4096);
3459     assert(bo);
3460     pp_context->sampler_state_table.bo_8x8_uv = bo;
3461
3462     dri_bo_unreference(pp_context->vfe_state.bo);
3463     bo = dri_bo_alloc(i965->intel.bufmgr,
3464                       "vfe state",
3465                       sizeof(struct i965_vfe_state),
3466                       4096);
3467     assert(bo);
3468     pp_context->vfe_state.bo = bo;
3469
3470     if (IS_GEN7(i965->intel.device_id)) {
3471         static_param_size = sizeof(struct gen7_pp_static_parameter);
3472         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3473     } else {
3474         static_param_size = sizeof(struct pp_static_parameter);
3475         inline_param_size = sizeof(struct pp_inline_parameter);
3476     }
3477
3478     memset(pp_context->pp_static_parameter, 0, static_param_size);
3479     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3480
3481     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3482     pp_context->current_pp = pp_index;
3483     pp_module = &pp_context->pp_modules[pp_index];
3484
3485     if (pp_module->initialize)
3486         va_status = pp_module->initialize(ctx, pp_context,
3487                                           src_surface,
3488                                           src_rect,
3489                                           dst_surface,
3490                                           dst_rect,
3491                                           filter_param);
3492     else
3493         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3494
3495     return va_status;
3496 }
3497
3498 static void
3499 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3500                                    struct i965_post_processing_context *pp_context)
3501 {
3502     struct i965_driver_data *i965 = i965_driver_data(ctx);
3503     struct gen6_interface_descriptor_data *desc;
3504     dri_bo *bo;
3505     int pp_index = pp_context->current_pp;
3506
3507     bo = pp_context->idrt.bo;
3508     dri_bo_map(bo, True);
3509     assert(bo->virtual);
3510     desc = bo->virtual;
3511     memset(desc, 0, sizeof(*desc));
3512     desc->desc0.kernel_start_pointer =
3513         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3514     desc->desc1.single_program_flow = 1;
3515     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3516     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3517     desc->desc2.sampler_state_pointer =
3518         pp_context->sampler_state_table.bo->offset >> 5;
3519     desc->desc3.binding_table_entry_count = 0;
3520     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3521     desc->desc4.constant_urb_entry_read_offset = 0;
3522
3523     if (IS_GEN7(i965->intel.device_id))
3524         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3525     else
3526         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3527
3528     dri_bo_emit_reloc(bo,
3529                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3530                       0,
3531                       offsetof(struct gen6_interface_descriptor_data, desc0),
3532                       pp_context->pp_modules[pp_index].kernel.bo);
3533
3534     dri_bo_emit_reloc(bo,
3535                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3536                       desc->desc2.sampler_count << 2,
3537                       offsetof(struct gen6_interface_descriptor_data, desc2),
3538                       pp_context->sampler_state_table.bo);
3539
3540     dri_bo_unmap(bo);
3541     pp_context->idrt.num_interface_descriptors++;
3542 }
3543
3544 static void
3545 gen6_pp_upload_constants(VADriverContextP ctx,
3546                          struct i965_post_processing_context *pp_context)
3547 {
3548     struct i965_driver_data *i965 = i965_driver_data(ctx);
3549     unsigned char *constant_buffer;
3550     int param_size;
3551
3552     assert(sizeof(struct pp_static_parameter) == 128);
3553     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3554
3555     if (IS_GEN7(i965->intel.device_id))
3556         param_size = sizeof(struct gen7_pp_static_parameter);
3557     else
3558         param_size = sizeof(struct pp_static_parameter);
3559
3560     dri_bo_map(pp_context->curbe.bo, 1);
3561     assert(pp_context->curbe.bo->virtual);
3562     constant_buffer = pp_context->curbe.bo->virtual;
3563     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3564     dri_bo_unmap(pp_context->curbe.bo);
3565 }
3566
3567 static void
3568 gen6_pp_states_setup(VADriverContextP ctx,
3569                      struct i965_post_processing_context *pp_context)
3570 {
3571     gen6_pp_interface_descriptor_table(ctx, pp_context);
3572     gen6_pp_upload_constants(ctx, pp_context);
3573 }
3574
3575 static void
3576 gen6_pp_pipeline_select(VADriverContextP ctx,
3577                         struct i965_post_processing_context *pp_context)
3578 {
3579     struct intel_batchbuffer *batch = pp_context->batch;
3580
3581     BEGIN_BATCH(batch, 1);
3582     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3583     ADVANCE_BATCH(batch);
3584 }
3585
3586 static void
3587 gen6_pp_state_base_address(VADriverContextP ctx,
3588                            struct i965_post_processing_context *pp_context)
3589 {
3590     struct intel_batchbuffer *batch = pp_context->batch;
3591
3592     BEGIN_BATCH(batch, 10);
3593     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3594     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3595     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3596     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3597     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3598     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3599     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3600     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3601     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3602     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3603     ADVANCE_BATCH(batch);
3604 }
3605
3606 static void
3607 gen6_pp_vfe_state(VADriverContextP ctx,
3608                   struct i965_post_processing_context *pp_context)
3609 {
3610     struct intel_batchbuffer *batch = pp_context->batch;
3611
3612     BEGIN_BATCH(batch, 8);
3613     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3614     OUT_BATCH(batch, 0);
3615     OUT_BATCH(batch,
3616               (pp_context->urb.num_vfe_entries - 1) << 16 |
3617               pp_context->urb.num_vfe_entries << 8);
3618     OUT_BATCH(batch, 0);
3619     OUT_BATCH(batch,
3620               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3621               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3622     OUT_BATCH(batch, 0);
3623     OUT_BATCH(batch, 0);
3624     OUT_BATCH(batch, 0);
3625     ADVANCE_BATCH(batch);
3626 }
3627
3628 static void
3629 gen6_pp_curbe_load(VADriverContextP ctx,
3630                    struct i965_post_processing_context *pp_context)
3631 {
3632     struct intel_batchbuffer *batch = pp_context->batch;
3633
3634     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3635
3636     BEGIN_BATCH(batch, 4);
3637     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3638     OUT_BATCH(batch, 0);
3639     OUT_BATCH(batch,
3640               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3641     OUT_RELOC(batch,
3642               pp_context->curbe.bo,
3643               I915_GEM_DOMAIN_INSTRUCTION, 0,
3644               0);
3645     ADVANCE_BATCH(batch);
3646 }
3647
3648 static void
3649 gen6_interface_descriptor_load(VADriverContextP ctx,
3650                                struct i965_post_processing_context *pp_context)
3651 {
3652     struct intel_batchbuffer *batch = pp_context->batch;
3653
3654     BEGIN_BATCH(batch, 4);
3655     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3656     OUT_BATCH(batch, 0);
3657     OUT_BATCH(batch,
3658               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3659     OUT_RELOC(batch,
3660               pp_context->idrt.bo,
3661               I915_GEM_DOMAIN_INSTRUCTION, 0,
3662               0);
3663     ADVANCE_BATCH(batch);
3664 }
3665
3666 static void
3667 gen6_pp_object_walker(VADriverContextP ctx,
3668                       struct i965_post_processing_context *pp_context)
3669 {
3670     struct i965_driver_data *i965 = i965_driver_data(ctx);
3671     struct intel_batchbuffer *batch = pp_context->batch;
3672     int x, x_steps, y, y_steps;
3673     int param_size, command_length_in_dws;
3674     dri_bo *command_buffer;
3675     unsigned int *command_ptr;
3676
3677     if (IS_GEN7(i965->intel.device_id))
3678         param_size = sizeof(struct gen7_pp_inline_parameter);
3679     else
3680         param_size = sizeof(struct pp_inline_parameter);
3681
3682     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3683     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3684     command_length_in_dws = 6 + (param_size >> 2);
3685     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3686                                   "command objects buffer",
3687                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3688                                   4096);
3689
3690     dri_bo_map(command_buffer, 1);
3691     command_ptr = command_buffer->virtual;
3692
3693     for (y = 0; y < y_steps; y++) {
3694         for (x = 0; x < x_steps; x++) {
3695             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3696                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3697                 *command_ptr++ = 0;
3698                 *command_ptr++ = 0;
3699                 *command_ptr++ = 0;
3700                 *command_ptr++ = 0;
3701                 *command_ptr++ = 0;
3702                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3703                 command_ptr += (param_size >> 2);
3704             }
3705         }
3706     }
3707
3708     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3709         *command_ptr++ = 0;
3710
3711     *command_ptr = MI_BATCH_BUFFER_END;
3712
3713     dri_bo_unmap(command_buffer);
3714
3715     BEGIN_BATCH(batch, 2);
3716     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3717     OUT_RELOC(batch, command_buffer,
3718               I915_GEM_DOMAIN_COMMAND, 0,
3719               0);
3720     ADVANCE_BATCH(batch);
3721
3722     dri_bo_unreference(command_buffer);
3723
3724     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3725      * will cause control to pass back to ring buffer
3726      */
3727     intel_batchbuffer_end_atomic(batch);
3728     intel_batchbuffer_flush(batch);
3729     intel_batchbuffer_start_atomic(batch, 0x1000);
3730 }
3731
3732 static void
3733 gen6_pp_pipeline_setup(VADriverContextP ctx,
3734                        struct i965_post_processing_context *pp_context)
3735 {
3736     struct intel_batchbuffer *batch = pp_context->batch;
3737
3738     intel_batchbuffer_start_atomic(batch, 0x1000);
3739     intel_batchbuffer_emit_mi_flush(batch);
3740     gen6_pp_pipeline_select(ctx, pp_context);
3741     gen6_pp_state_base_address(ctx, pp_context);
3742     gen6_pp_vfe_state(ctx, pp_context);
3743     gen6_pp_curbe_load(ctx, pp_context);
3744     gen6_interface_descriptor_load(ctx, pp_context);
3745     gen6_pp_object_walker(ctx, pp_context);
3746     intel_batchbuffer_end_atomic(batch);
3747 }
3748
3749 static VAStatus
3750 gen6_post_processing(
3751     VADriverContextP   ctx,
3752     struct i965_post_processing_context *pp_context,
3753     const struct i965_surface *src_surface,
3754     const VARectangle *src_rect,
3755     struct i965_surface *dst_surface,
3756     const VARectangle *dst_rect,
3757     int                pp_index,
3758     void * filter_param
3759 )
3760 {
3761     VAStatus va_status;
3762
3763     va_status = gen6_pp_initialize(ctx, pp_context,
3764                                    src_surface,
3765                                    src_rect,
3766                                    dst_surface,
3767                                    dst_rect,
3768                                    pp_index,
3769                                    filter_param);
3770
3771     if (va_status == VA_STATUS_SUCCESS) {
3772         gen6_pp_states_setup(ctx, pp_context);
3773         gen6_pp_pipeline_setup(ctx, pp_context);
3774     }
3775
3776     return va_status;
3777 }
3778
3779 static VAStatus
3780 i965_post_processing_internal(
3781     VADriverContextP   ctx,
3782     struct i965_post_processing_context *pp_context,
3783     const struct i965_surface *src_surface,
3784     const VARectangle *src_rect,
3785     struct i965_surface *dst_surface,
3786     const VARectangle *dst_rect,
3787     int                pp_index,
3788     void *filter_param
3789 )
3790 {
3791     struct i965_driver_data *i965 = i965_driver_data(ctx);
3792     VAStatus va_status;
3793
3794     if (IS_GEN6(i965->intel.device_id) ||
3795         IS_GEN7(i965->intel.device_id))
3796         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3797     else
3798         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3799
3800     return va_status;
3801 }
3802
3803 VAStatus
3804 i965_DestroySurfaces(VADriverContextP ctx,
3805                      VASurfaceID *surface_list,
3806                      int num_surfaces);
3807 VAStatus
3808 i965_CreateSurfaces(VADriverContextP ctx,
3809                     int width,
3810                     int height,
3811                     int format,
3812                     int num_surfaces,
3813                     VASurfaceID *surfaces);
3814
3815 static void
3816 rgb_to_yuv(unsigned int argb,
3817            unsigned char *y,
3818            unsigned char *u,
3819            unsigned char *v,
3820            unsigned char *a)
3821 {
3822     int r = ((argb >> 16) & 0xff);
3823     int g = ((argb >> 8) & 0xff);
3824     int b = ((argb >> 0) & 0xff);
3825
3826     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3827     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3828     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3829     *a = ((argb >> 24) & 0xff);
3830 }
3831
3832 static void
3833 i965_vpp_clear_surface(VADriverContextP ctx,
3834                        struct i965_post_processing_context *pp_context,
3835                        VASurfaceID surface,
3836                        unsigned int color)
3837 {
3838     struct i965_driver_data *i965 = i965_driver_data(ctx);
3839     struct intel_batchbuffer *batch = pp_context->batch;
3840     struct object_surface *obj_surface = SURFACE(surface);
3841     unsigned int blt_cmd, br13;
3842     unsigned int tiling = 0, swizzle = 0;
3843     int pitch;
3844     unsigned char y, u, v, a = 0;
3845
3846     /* Currently only support NV12 surface */
3847     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3848         return;
3849
3850     rgb_to_yuv(color, &y, &u, &v, &a);
3851
3852     if (a == 0)
3853         return;
3854
3855     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3856     blt_cmd = XY_COLOR_BLT_CMD;
3857     pitch = obj_surface->width;
3858
3859     if (tiling != I915_TILING_NONE) {
3860         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3861         pitch >>= 2;
3862     }
3863
3864     br13 = 0xf0 << 16;
3865     br13 |= BR13_8;
3866     br13 |= pitch;
3867
3868     if (IS_GEN6(i965->intel.device_id) ||
3869         IS_GEN7(i965->intel.device_id)) {
3870         intel_batchbuffer_start_atomic_blt(batch, 48);
3871         BEGIN_BLT_BATCH(batch, 12);
3872     } else {
3873         intel_batchbuffer_start_atomic(batch, 48);
3874         BEGIN_BATCH(batch, 12);
3875     }
3876
3877     OUT_BATCH(batch, blt_cmd);
3878     OUT_BATCH(batch, br13);
3879     OUT_BATCH(batch,
3880               0 << 16 |
3881               0);
3882     OUT_BATCH(batch,
3883               obj_surface->height << 16 |
3884               obj_surface->width);
3885     OUT_RELOC(batch, obj_surface->bo,
3886               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3887               0);
3888     OUT_BATCH(batch, y);
3889
3890     br13 = 0xf0 << 16;
3891     br13 |= BR13_565;
3892     br13 |= pitch;
3893
3894     OUT_BATCH(batch, blt_cmd);
3895     OUT_BATCH(batch, br13);
3896     OUT_BATCH(batch,
3897               0 << 16 |
3898               0);
3899     OUT_BATCH(batch,
3900               obj_surface->height / 2 << 16 |
3901               obj_surface->width / 2);
3902     OUT_RELOC(batch, obj_surface->bo,
3903               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3904               obj_surface->width * obj_surface->y_cb_offset);
3905     OUT_BATCH(batch, v << 8 | u);
3906
3907     ADVANCE_BATCH(batch);
3908     intel_batchbuffer_end_atomic(batch);
3909 }
3910
3911 VASurfaceID
3912 i965_post_processing(
3913     VADriverContextP   ctx,
3914     VASurfaceID        surface,
3915     const VARectangle *src_rect,
3916     const VARectangle *dst_rect,
3917     unsigned int       flags,
3918     int               *has_done_scaling
3919 )
3920 {
3921     struct i965_driver_data *i965 = i965_driver_data(ctx);
3922     VASurfaceID in_surface_id = surface;
3923     VASurfaceID out_surface_id = VA_INVALID_ID;
3924
3925     *has_done_scaling = 0;
3926
3927     if (HAS_PP(i965)) {
3928         struct object_surface *obj_surface;
3929         VAStatus status;
3930         struct i965_surface src_surface;
3931         struct i965_surface dst_surface;
3932
3933         obj_surface = SURFACE(in_surface_id);
3934
3935         /* Currently only support post processing for NV12 surface */
3936         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3937             return out_surface_id;
3938
3939         _i965LockMutex(&i965->pp_mutex);
3940
3941         if (flags & I965_PP_FLAG_MCDI) {
3942             status = i965_CreateSurfaces(ctx,
3943                                          obj_surface->orig_width,
3944                                          obj_surface->orig_height,
3945                                          VA_RT_FORMAT_YUV420,
3946                                          1,
3947                                          &out_surface_id);
3948             assert(status == VA_STATUS_SUCCESS);
3949             obj_surface = SURFACE(out_surface_id);
3950             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3951             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3952             src_surface.id = in_surface_id;
3953             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3954             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3955                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3956             dst_surface.id = out_surface_id;
3957             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3958             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3959
3960             i965_post_processing_internal(ctx, i965->pp_context,
3961                                           &src_surface,
3962                                           src_rect,
3963                                           &dst_surface,
3964                                           dst_rect,
3965                                           PP_NV12_DNDI,
3966                                           NULL);
3967         }
3968
3969         if (flags & I965_PP_FLAG_AVS) {
3970             struct i965_render_state *render_state = &i965->render_state;
3971             struct intel_region *dest_region = render_state->draw_region;
3972
3973             if (out_surface_id != VA_INVALID_ID)
3974                 in_surface_id = out_surface_id;
3975
3976             status = i965_CreateSurfaces(ctx,
3977                                          dest_region->width,
3978                                          dest_region->height,
3979                                          VA_RT_FORMAT_YUV420,
3980                                          1,
3981                                          &out_surface_id);
3982             assert(status == VA_STATUS_SUCCESS);
3983             obj_surface = SURFACE(out_surface_id);
3984             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3985             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3986             src_surface.id = in_surface_id;
3987             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3988             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3989             dst_surface.id = out_surface_id;
3990             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3991             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3992
3993             i965_post_processing_internal(ctx, i965->pp_context,
3994                                           &src_surface,
3995                                           src_rect,
3996                                           &dst_surface,
3997                                           dst_rect,
3998                                           PP_NV12_AVS,
3999                                           NULL);
4000
4001             if (in_surface_id != surface)
4002                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4003
4004             *has_done_scaling = 1;
4005         }
4006
4007         _i965UnlockMutex(&i965->pp_mutex);
4008     }
4009
4010     return out_surface_id;
4011 }
4012
4013 static VAStatus
4014 i965_image_pl3_processing(VADriverContextP ctx,
4015                           const struct i965_surface *src_surface,
4016                           const VARectangle *src_rect,
4017                           struct i965_surface *dst_surface,
4018                           const VARectangle *dst_rect)
4019 {
4020     struct i965_driver_data *i965 = i965_driver_data(ctx);
4021     struct i965_post_processing_context *pp_context = i965->pp_context;
4022     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4023     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4024
4025     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4026         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4027                                                  src_surface,
4028                                                  src_rect,
4029                                                  dst_surface,
4030                                                  dst_rect,
4031                                                  PP_PL3_LOAD_SAVE_N12,
4032                                                  NULL);
4033     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4034                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4035                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4036                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4037         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4038                                                  src_surface,
4039                                                  src_rect,
4040                                                  dst_surface,
4041                                                  dst_rect,
4042                                                  PP_PL3_LOAD_SAVE_PL3,
4043                                                  NULL);
4044     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4045                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4046         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4047                                                  src_surface,
4048                                                  src_rect,
4049                                                  dst_surface,
4050                                                  dst_rect,
4051                                                  PP_PL3_LOAD_SAVE_PA,
4052                                                  NULL);
4053     }
4054     else {
4055         assert(0);
4056     }
4057
4058     intel_batchbuffer_flush(pp_context->batch);
4059
4060     return vaStatus;
4061 }
4062
4063 static VAStatus
4064 i965_image_pl2_processing(VADriverContextP ctx,
4065                           const struct i965_surface *src_surface,
4066                           const VARectangle *src_rect,
4067                           struct i965_surface *dst_surface,
4068                           const VARectangle *dst_rect)
4069 {
4070     struct i965_driver_data *i965 = i965_driver_data(ctx);
4071     struct i965_post_processing_context *pp_context = i965->pp_context;
4072     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4073     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4074
4075     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4076         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4077                                                  src_surface,
4078                                                  src_rect,
4079                                                  dst_surface,
4080                                                  dst_rect,
4081                                                  PP_NV12_LOAD_SAVE_N12,
4082                                                  NULL);
4083     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4084                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4085                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4086                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4087         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4088                                                  src_surface,
4089                                                  src_rect,
4090                                                  dst_surface,
4091                                                  dst_rect,
4092                                                  PP_NV12_LOAD_SAVE_PL3,
4093                                                  NULL);
4094     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4095                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4096         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4097                                                  src_surface,
4098                                                  src_rect,
4099                                                  dst_surface,
4100                                                  dst_rect,
4101                                                  PP_NV12_LOAD_SAVE_PA,
4102                                                      NULL);
4103     }
4104
4105     intel_batchbuffer_flush(pp_context->batch);
4106
4107     return vaStatus;
4108 }
4109
4110 static VAStatus
4111 i965_image_pl1_processing(VADriverContextP ctx,
4112                           const struct i965_surface *src_surface,
4113                           const VARectangle *src_rect,
4114                           struct i965_surface *dst_surface,
4115                           const VARectangle *dst_rect)
4116 {
4117     struct i965_driver_data *i965 = i965_driver_data(ctx);
4118     struct i965_post_processing_context *pp_context = i965->pp_context;
4119     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4120
4121     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4122         i965_post_processing_internal(ctx, i965->pp_context,
4123                                       src_surface,
4124                                       src_rect,
4125                                       dst_surface,
4126                                       dst_rect,
4127                                       PP_PA_LOAD_SAVE_NV12,
4128                                       NULL);
4129     }
4130     else if (fourcc == VA_FOURCC_YV12) {
4131         i965_post_processing_internal(ctx, i965->pp_context,
4132                                       src_surface,
4133                                       src_rect,
4134                                       dst_surface,
4135                                       dst_rect,
4136                                       PP_PA_LOAD_SAVE_PL3,
4137                                       NULL);
4138
4139     }
4140     else {
4141         return VA_STATUS_ERROR_UNKNOWN;
4142     }
4143
4144     intel_batchbuffer_flush(pp_context->batch);
4145
4146     return VA_STATUS_SUCCESS;
4147 }
4148
4149 VAStatus
4150 i965_image_processing(VADriverContextP ctx,
4151                       const struct i965_surface *src_surface,
4152                       const VARectangle *src_rect,
4153                       struct i965_surface *dst_surface,
4154                       const VARectangle *dst_rect)
4155 {
4156     struct i965_driver_data *i965 = i965_driver_data(ctx);
4157     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4158
4159     if (HAS_PP(i965)) {
4160         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4161
4162         _i965LockMutex(&i965->pp_mutex);
4163
4164         switch (fourcc) {
4165         case VA_FOURCC('Y', 'V', '1', '2'):
4166         case VA_FOURCC('I', '4', '2', '0'):
4167         case VA_FOURCC('I', 'M', 'C', '1'):
4168         case VA_FOURCC('I', 'M', 'C', '3'):
4169             status = i965_image_pl3_processing(ctx,
4170                                                src_surface,
4171                                                src_rect,
4172                                                dst_surface,
4173                                                dst_rect);
4174             break;
4175
4176         case  VA_FOURCC('N', 'V', '1', '2'):
4177             status = i965_image_pl2_processing(ctx,
4178                                                src_surface,
4179                                                src_rect,
4180                                                dst_surface,
4181                                                dst_rect);
4182             break;
4183         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4184         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4185             status = i965_image_pl1_processing(ctx,
4186                                                src_surface,
4187                                                src_rect,
4188                                                dst_surface,
4189                                                dst_rect);
4190             break;
4191
4192         default:
4193             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4194             break;
4195         }
4196
4197         _i965UnlockMutex(&i965->pp_mutex);
4198     }
4199
4200     return status;
4201 }
4202
4203 static void
4204 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4205 {
4206     int i;
4207
4208     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4209     pp_context->surface_state_binding_table.bo = NULL;
4210
4211     dri_bo_unreference(pp_context->curbe.bo);
4212     pp_context->curbe.bo = NULL;
4213
4214     dri_bo_unreference(pp_context->sampler_state_table.bo);
4215     pp_context->sampler_state_table.bo = NULL;
4216
4217     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4218     pp_context->sampler_state_table.bo_8x8 = NULL;
4219
4220     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4221     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4222
4223     dri_bo_unreference(pp_context->idrt.bo);
4224     pp_context->idrt.bo = NULL;
4225     pp_context->idrt.num_interface_descriptors = 0;
4226
4227     dri_bo_unreference(pp_context->vfe_state.bo);
4228     pp_context->vfe_state.bo = NULL;
4229
4230     dri_bo_unreference(pp_context->stmm.bo);
4231     pp_context->stmm.bo = NULL;
4232
4233     for (i = 0; i < NUM_PP_MODULES; i++) {
4234         struct pp_module *pp_module = &pp_context->pp_modules[i];
4235
4236         dri_bo_unreference(pp_module->kernel.bo);
4237         pp_module->kernel.bo = NULL;
4238     }
4239
4240     free(pp_context->pp_static_parameter);
4241     free(pp_context->pp_inline_parameter);
4242     pp_context->pp_static_parameter = NULL;
4243     pp_context->pp_inline_parameter = NULL;
4244 }
4245
4246 Bool
4247 i965_post_processing_terminate(VADriverContextP ctx)
4248 {
4249     struct i965_driver_data *i965 = i965_driver_data(ctx);
4250     struct i965_post_processing_context *pp_context = i965->pp_context;
4251
4252     if (pp_context) {
4253         i965_post_processing_context_finalize(pp_context);
4254         free(pp_context);
4255     }
4256
4257     i965->pp_context = NULL;
4258
4259     return True;
4260 }
4261
4262 static void
4263 i965_post_processing_context_init(VADriverContextP ctx,
4264                                   struct i965_post_processing_context *pp_context,
4265                                   struct intel_batchbuffer *batch)
4266 {
4267     struct i965_driver_data *i965 = i965_driver_data(ctx);
4268     int i;
4269
4270     pp_context->urb.size = URB_SIZE((&i965->intel));
4271     pp_context->urb.num_vfe_entries = 32;
4272     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4273     pp_context->urb.num_cs_entries = 1;
4274
4275     if (IS_GEN7(i965->intel.device_id))
4276         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4277     else
4278         pp_context->urb.size_cs_entry = 2;
4279
4280     pp_context->urb.vfe_start = 0;
4281     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4282         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4283     assert(pp_context->urb.cs_start +
4284            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4285
4286     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4287     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4288     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4289
4290     if (IS_GEN7(i965->intel.device_id))
4291         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4292     else if (IS_GEN6(i965->intel.device_id))
4293         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4294     else if (IS_IRONLAKE(i965->intel.device_id))
4295         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4296
4297     for (i = 0; i < NUM_PP_MODULES; i++) {
4298         struct pp_module *pp_module = &pp_context->pp_modules[i];
4299         dri_bo_unreference(pp_module->kernel.bo);
4300         if (pp_module->kernel.bin && pp_module->kernel.size) {
4301             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4302                                                 pp_module->kernel.name,
4303                                                 pp_module->kernel.size,
4304                                                 4096);
4305             assert(pp_module->kernel.bo);
4306             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4307         } else {
4308             pp_module->kernel.bo = NULL;
4309         }
4310     }
4311
4312     /* static & inline parameters */
4313     if (IS_GEN7(i965->intel.device_id)) {
4314         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4315         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4316     } else {
4317         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4318         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4319     }
4320
4321     pp_context->batch = batch;
4322 }
4323
4324 Bool
4325 i965_post_processing_init(VADriverContextP ctx)
4326 {
4327     struct i965_driver_data *i965 = i965_driver_data(ctx);
4328     struct i965_post_processing_context *pp_context = i965->pp_context;
4329
4330     if (HAS_PP(i965)) {
4331         if (pp_context == NULL) {
4332             pp_context = calloc(1, sizeof(*pp_context));
4333             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4334             i965->pp_context = pp_context;
4335         }
4336     }
4337
4338     return True;
4339 }
4340
4341 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4342     PP_NULL,    /* VAProcFilterNone */
4343     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4344     PP_NULL,    /* VAProcFilterDeblocking */
4345     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4346     PP_NULL,    /* VAProcFilterSharpening */
4347     PP_NULL,    /* VAProcFilterColorBalance */
4348     PP_NULL,    /* VAProcFilterColorStandard */
4349     PP_NULL,    /* VAProcFilterFrameRateConversion */
4350 };
4351
4352 static const int proc_frame_to_pp_frame[3] = {
4353     I965_SURFACE_FLAG_FRAME,
4354     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4355     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4356 };
4357
4358 static void
4359 i965_proc_picture(VADriverContextP ctx,
4360                   VAProfile profile,
4361                   union codec_state *codec_state,
4362                   struct hw_context *hw_context)
4363 {
4364     struct i965_driver_data *i965 = i965_driver_data(ctx);
4365     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4366     struct proc_state *proc_state = &codec_state->proc;
4367     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4368     struct object_surface *obj_surface;
4369     struct i965_surface src_surface, dst_surface;
4370     VARectangle src_rect, dst_rect;
4371     VAStatus status;
4372     int i;
4373     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4374     int num_tmp_surfaces = 0;
4375     unsigned int tiling = 0, swizzle = 0;
4376     int in_width, in_height;
4377
4378     assert(pipeline_param->surface != VA_INVALID_ID);
4379     assert(proc_state->current_render_target != VA_INVALID_ID);
4380
4381     obj_surface = SURFACE(pipeline_param->surface);
4382     in_width = obj_surface->orig_width;
4383     in_height = obj_surface->orig_height;
4384     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4385
4386     src_surface.id = pipeline_param->surface;
4387     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4388     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4389
4390     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4391         VASurfaceID out_surface_id = VA_INVALID_ID;
4392
4393         src_surface.id = pipeline_param->surface;
4394         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4395         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4396         src_rect.x = 0;
4397         src_rect.y = 0;
4398         src_rect.width = in_width;
4399         src_rect.height = in_height;
4400
4401         status = i965_CreateSurfaces(ctx,
4402                                      in_width,
4403                                      in_height,
4404                                      VA_RT_FORMAT_YUV420,
4405                                      1,
4406                                      &out_surface_id);
4407         assert(status == VA_STATUS_SUCCESS);
4408         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4409         obj_surface = SURFACE(out_surface_id);
4410         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4411
4412         dst_surface.id = out_surface_id;
4413         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4414         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4415         dst_rect.x = 0;
4416         dst_rect.y = 0;
4417         dst_rect.width = in_width;
4418         dst_rect.height = in_height;
4419
4420         status = i965_image_processing(ctx,
4421                                        &src_surface,
4422                                        &src_rect,
4423                                        &dst_surface,
4424                                        &dst_rect);
4425         assert(status == VA_STATUS_SUCCESS);
4426
4427         src_surface.id = out_surface_id;
4428         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4429         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4430     }
4431
4432     if (pipeline_param->surface_region) {
4433         src_rect.x = pipeline_param->surface_region->x;
4434         src_rect.y = pipeline_param->surface_region->y;
4435         src_rect.width = pipeline_param->surface_region->width;
4436         src_rect.height = pipeline_param->surface_region->height;
4437     } else {
4438         src_rect.x = 0;
4439         src_rect.y = 0;
4440         src_rect.width = in_width;
4441         src_rect.height = in_height;
4442     }
4443
4444     if (pipeline_param->output_region) {
4445         dst_rect.x = pipeline_param->output_region->x;
4446         dst_rect.y = pipeline_param->output_region->y;
4447         dst_rect.width = pipeline_param->output_region->width;
4448         dst_rect.height = pipeline_param->output_region->height;
4449     } else {
4450         dst_rect.x = 0;
4451         dst_rect.y = 0;
4452         dst_rect.width = in_width;
4453         dst_rect.height = in_height;
4454     }
4455
4456     obj_surface = SURFACE(proc_state->current_render_target);
4457     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4458     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4459
4460     for (i = 0; i < pipeline_param->num_filters; i++) {
4461         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4462         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4463         VAProcFilterType filter_type = filter_param->type;
4464         VASurfaceID out_surface_id = VA_INVALID_ID;
4465         int kernel_index = procfilter_to_pp_flag[filter_type];
4466
4467         if (kernel_index != PP_NULL &&
4468             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4469             status = i965_CreateSurfaces(ctx,
4470                                          in_width,
4471                                          in_height,
4472                                          VA_RT_FORMAT_YUV420,
4473                                          1,
4474                                          &out_surface_id);
4475             assert(status == VA_STATUS_SUCCESS);
4476             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4477             obj_surface = SURFACE(out_surface_id);
4478             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4479             dst_surface.id = out_surface_id;
4480             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4481             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4482                                                    &src_surface,
4483                                                    &src_rect,
4484                                                    &dst_surface,
4485                                                    &src_rect,
4486                                                    kernel_index,
4487                                                    filter_param);
4488
4489             if (status == VA_STATUS_SUCCESS) {
4490                 src_surface.id = dst_surface.id;
4491                 src_surface.type = dst_surface.type;
4492                 src_surface.flags = dst_surface.flags;
4493             }
4494         }
4495     }
4496
4497     dst_surface.id = proc_state->current_render_target;
4498     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4499
4500     if (src_rect.width == dst_rect.width &&
4501         src_rect.height == dst_rect.height) {
4502         i965_post_processing_internal(ctx, &proc_context->pp_context,
4503                                       &src_surface,
4504                                       &src_rect,
4505                                       &dst_surface,
4506                                       &dst_rect,
4507                                       PP_NV12_LOAD_SAVE_N12,
4508                                       NULL);
4509     } else {
4510
4511         i965_post_processing_internal(ctx, &proc_context->pp_context,
4512                                       &src_surface,
4513                                       &src_rect,
4514                                       &dst_surface,
4515                                       &dst_rect,
4516                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4517                                       PP_NV12_AVS : PP_NV12_SCALING,
4518                                       NULL);
4519     }
4520
4521     if (num_tmp_surfaces)
4522         i965_DestroySurfaces(ctx,
4523                              tmp_surfaces,
4524                              num_tmp_surfaces);
4525
4526     intel_batchbuffer_flush(hw_context->batch);
4527 }
4528
4529 static void
4530 i965_proc_context_destroy(void *hw_context)
4531 {
4532     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4533
4534     i965_post_processing_context_finalize(&proc_context->pp_context);
4535     intel_batchbuffer_free(proc_context->base.batch);
4536     free(proc_context);
4537 }
4538
4539 struct hw_context *
4540 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4541 {
4542     struct intel_driver_data *intel = intel_driver_data(ctx);
4543     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4544
4545     proc_context->base.destroy = i965_proc_context_destroy;
4546     proc_context->base.run = i965_proc_picture;
4547     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4548     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4549
4550     return (struct hw_context *)proc_context;
4551 }