src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 111                                    const struct i965_surface *src_surface,
 112                                    const VARectangle *src_rect,
 113                                    struct i965_surface *dst_surface,
 114                                    const VARectangle *dst_rect,
 115                                    void *filter_param);
 116 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 117                                             const struct i965_surface *src_surface,
 118                                             const VARectangle *src_rect,
 119                                             struct i965_surface *dst_surface,
 120                                             const VARectangle *dst_rect,
 121                                             void *filter_param);
 122 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 123                                            const struct i965_surface *src_surface,
 124                                            const VARectangle *src_rect,
 125                                            struct i965_surface *dst_surface,
 126                                            const VARectangle *dst_rect,
 127                                            void *filter_param);
 128 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 129                                              const struct i965_surface *src_surface,
 130                                              const VARectangle *src_rect,
 131                                              struct i965_surface *dst_surface,
 132                                              const VARectangle *dst_rect,
 133                                              void *filter_param);
 134 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 135                                                 const struct i965_surface *src_surface,
 136                                                 const VARectangle *src_rect,
 137                                                 struct i965_surface *dst_surface,
 138                                                 const VARectangle *dst_rect,
 139                                                 void *filter_param);
 140 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 141                                         const struct i965_surface *src_surface,
 142                                         const VARectangle *src_rect,
 143                                         struct i965_surface *dst_surface,
 144                                         const VARectangle *dst_rect,
 145                                         void *filter_param);
 146 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 147                                       const struct i965_surface *src_surface,
 148                                       const VARectangle *src_rect,
 149                                       struct i965_surface *dst_surface,
 150                                       const VARectangle *dst_rect,
 151                                       void *filter_param);
 152
 153 static struct pp_module pp_modules_gen5[] = {
 154     {
 155         {
 156             "NULL module (for testing)",
 157             PP_NULL,
 158             pp_null_gen5,
 159             sizeof(pp_null_gen5),
 160             NULL,
 161         },
 162
 163         pp_null_initialize,
 164     },
 165
 166     {
 167         {
 168             "NV12_NV12",
 169             PP_NV12_LOAD_SAVE_N12,
 170             pp_nv12_load_save_nv12_gen5,
 171             sizeof(pp_nv12_load_save_nv12_gen5),
 172             NULL,
 173         },
 174
 175         pp_plx_load_save_plx_initialize,
 176     },
 177
 178     {
 179         {
 180             "NV12_PL3",
 181             PP_NV12_LOAD_SAVE_PL3,
 182             pp_nv12_load_save_pl3_gen5,
 183             sizeof(pp_nv12_load_save_pl3_gen5),
 184             NULL,
 185         },
 186
 187         pp_plx_load_save_plx_initialize,
 188     },
 189
 190     {
 191         {
 192             "PL3_NV12",
 193             PP_PL3_LOAD_SAVE_N12,
 194             pp_pl3_load_save_nv12_gen5,
 195             sizeof(pp_pl3_load_save_nv12_gen5),
 196             NULL,
 197         },
 198
 199         pp_plx_load_save_plx_initialize,
 200     },
 201
 202     {
 203         {
 204             "PL3_PL3",
 205             PP_PL3_LOAD_SAVE_N12,
 206             pp_pl3_load_save_pl3_gen5,
 207             sizeof(pp_pl3_load_save_pl3_gen5),
 208             NULL,
 209         },
 210
 211         pp_plx_load_save_plx_initialize
 212     },
 213
 214     {
 215         {
 216             "NV12 Scaling module",
 217             PP_NV12_SCALING,
 218             pp_nv12_scaling_gen5,
 219             sizeof(pp_nv12_scaling_gen5),
 220             NULL,
 221         },
 222
 223         pp_nv12_scaling_initialize,
 224     },
 225
 226     {
 227         {
 228             "NV12 AVS module",
 229             PP_NV12_AVS,
 230             pp_nv12_avs_gen5,
 231             sizeof(pp_nv12_avs_gen5),
 232             NULL,
 233         },
 234
 235         pp_nv12_avs_initialize_nlas,
 236     },
 237
 238     {
 239         {
 240             "NV12 DNDI module",
 241             PP_NV12_DNDI,
 242             pp_nv12_dndi_gen5,
 243             sizeof(pp_nv12_dndi_gen5),
 244             NULL,
 245         },
 246
 247         pp_nv12_dndi_initialize,
 248     },
 249
 250     {
 251         {
 252             "NV12 DN module",
 253             PP_NV12_DN,
 254             pp_nv12_dn_gen5,
 255             sizeof(pp_nv12_dn_gen5),
 256             NULL,
 257         },
 258
 259         pp_nv12_dn_initialize,
 260     },
 261
 262     {
 263         {
 264             "NV12_PA module",
 265             PP_NV12_LOAD_SAVE_PA,
 266             pp_nv12_load_save_pa_gen5,
 267             sizeof(pp_nv12_load_save_pa_gen5),
 268             NULL,
 269         },
 270
 271         pp_plx_load_save_plx_initialize,
 272     },
 273
 274     {
 275         {
 276             "PL3_PA module",
 277             PP_PL3_LOAD_SAVE_PA,
 278             pp_pl3_load_save_pa_gen5,
 279             sizeof(pp_pl3_load_save_pa_gen5),
 280             NULL,
 281         },
 282
 283         pp_plx_load_save_plx_initialize,
 284     },
 285
 286     {
 287         {
 288             "PA_NV12 module",
 289             PP_PA_LOAD_SAVE_NV12,
 290             pp_pa_load_save_nv12_gen5,
 291             sizeof(pp_pa_load_save_nv12_gen5),
 292             NULL,
 293         },
 294
 295         pp_plx_load_save_plx_initialize,
 296     },
 297
 298     {
 299         {
 300             "PA_PL3 module",
 301             PP_PA_LOAD_SAVE_PL3,
 302             pp_pa_load_save_pl3_gen5,
 303             sizeof(pp_pa_load_save_pl3_gen5),
 304             NULL,
 305         },
 306
 307         pp_plx_load_save_plx_initialize,
 308     },
 309
 310 };
 311
 312 static const uint32_t pp_null_gen6[][4] = {
 313 #include "shaders/post_processing/gen5_6/null.g6b"
 314 };
 315
 316 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 317 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 318 };
 319
 320 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 321 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 322 };
 323
 324 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 325 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 326 };
 327
 328 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 329 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 330 };
 331
 332 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 333 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 334 };
 335
 336 static const uint32_t pp_nv12_avs_gen6[][4] = {
 337 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 338 };
 339
 340 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 341 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 342 };
 343
 344 static const uint32_t pp_nv12_dn_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 350 };
 351
 352 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 354 };
 355
 356 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 362 };
 363
 364 static struct pp_module pp_modules_gen6[] = {
 365     {
 366         {
 367             "NULL module (for testing)",
 368             PP_NULL,
 369             pp_null_gen6,
 370             sizeof(pp_null_gen6),
 371             NULL,
 372         },
 373
 374         pp_null_initialize,
 375     },
 376
 377     {
 378         {
 379             "NV12_NV12",
 380             PP_NV12_LOAD_SAVE_N12,
 381             pp_nv12_load_save_nv12_gen6,
 382             sizeof(pp_nv12_load_save_nv12_gen6),
 383             NULL,
 384         },
 385
 386         pp_plx_load_save_plx_initialize,
 387     },
 388
 389     {
 390         {
 391             "NV12_PL3",
 392             PP_NV12_LOAD_SAVE_PL3,
 393             pp_nv12_load_save_pl3_gen6,
 394             sizeof(pp_nv12_load_save_pl3_gen6),
 395             NULL,
 396         },
 397
 398         pp_plx_load_save_plx_initialize,
 399     },
 400
 401     {
 402         {
 403             "PL3_NV12",
 404             PP_PL3_LOAD_SAVE_N12,
 405             pp_pl3_load_save_nv12_gen6,
 406             sizeof(pp_pl3_load_save_nv12_gen6),
 407             NULL,
 408         },
 409
 410         pp_plx_load_save_plx_initialize,
 411     },
 412
 413     {
 414         {
 415             "PL3_PL3",
 416             PP_PL3_LOAD_SAVE_N12,
 417             pp_pl3_load_save_pl3_gen6,
 418             sizeof(pp_pl3_load_save_pl3_gen6),
 419             NULL,
 420         },
 421
 422         pp_plx_load_save_plx_initialize,
 423     },
 424
 425     {
 426         {
 427             "NV12 Scaling module",
 428             PP_NV12_SCALING,
 429             pp_nv12_scaling_gen6,
 430             sizeof(pp_nv12_scaling_gen6),
 431             NULL,
 432         },
 433
 434         gen6_nv12_scaling_initialize,
 435     },
 436
 437     {
 438         {
 439             "NV12 AVS module",
 440             PP_NV12_AVS,
 441             pp_nv12_avs_gen6,
 442             sizeof(pp_nv12_avs_gen6),
 443             NULL,
 444         },
 445
 446         pp_nv12_avs_initialize_nlas,
 447     },
 448
 449     {
 450         {
 451             "NV12 DNDI module",
 452             PP_NV12_DNDI,
 453             pp_nv12_dndi_gen6,
 454             sizeof(pp_nv12_dndi_gen6),
 455             NULL,
 456         },
 457
 458         pp_nv12_dndi_initialize,
 459     },
 460
 461     {
 462         {
 463             "NV12 DN module",
 464             PP_NV12_DN,
 465             pp_nv12_dn_gen6,
 466             sizeof(pp_nv12_dn_gen6),
 467             NULL,
 468         },
 469
 470         pp_nv12_dn_initialize,
 471     },
 472     {
 473         {
 474             "NV12_PA module",
 475             PP_NV12_LOAD_SAVE_PA,
 476             pp_nv12_load_save_pa_gen6,
 477             sizeof(pp_nv12_load_save_pa_gen6),
 478             NULL,
 479         },
 480
 481         pp_plx_load_save_plx_initialize,
 482     },
 483
 484     {
 485         {
 486             "PL3_PA module",
 487             PP_PL3_LOAD_SAVE_PA,
 488             pp_pl3_load_save_pa_gen6,
 489             sizeof(pp_pl3_load_save_pa_gen6),
 490             NULL,
 491         },
 492
 493         pp_plx_load_save_plx_initialize,
 494     },
 495
 496     {
 497         {
 498             "PA_NV12 module",
 499             PP_PA_LOAD_SAVE_NV12,
 500             pp_pa_load_save_nv12_gen6,
 501             sizeof(pp_pa_load_save_nv12_gen6),
 502             NULL,
 503         },
 504
 505         pp_plx_load_save_plx_initialize,
 506     },
 507
 508     {
 509         {
 510             "PA_PL3 module",
 511             PP_PA_LOAD_SAVE_PL3,
 512             pp_pa_load_save_pl3_gen6,
 513             sizeof(pp_pa_load_save_pl3_gen6),
 514             NULL,
 515         },
 516
 517         pp_plx_load_save_plx_initialize,
 518     },
 519
 520 };
 521
 522 static const uint32_t pp_null_gen7[][4] = {
 523 };
 524
 525 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 526 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 527 };
 528
 529 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 530 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 531 };
 532
 533 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 534 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 535 };
 536
 537 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 538 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 539 };
 540
 541 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 542 #include "shaders/post_processing/gen7/avs.g7b"
 543 };
 544
 545 static const uint32_t pp_nv12_avs_gen7[][4] = {
 546 #include "shaders/post_processing/gen7/avs.g7b"
 547 };
 548
 549 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 550 // #include "shaders/post_processing/gen7/dndi.g7b"
 551 };
 552
 553 static const uint32_t pp_nv12_dn_gen7[][4] = {
 554 };
 555 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 556 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 557 };
 558 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 559 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 560 };
 561 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 562 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 563 };
 564 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 565 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 566 };
 567
 568 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 569                                            const struct i965_surface *src_surface,
 570                                            const VARectangle *src_rect,
 571                                            struct i965_surface *dst_surface,
 572                                            const VARectangle *dst_rect,
 573                                            void *filter_param);
 574 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 575                                              const struct i965_surface *src_surface,
 576                                              const VARectangle *src_rect,
 577                                              struct i965_surface *dst_surface,
 578                                              const VARectangle *dst_rect,
 579                                              void *filter_param);
 580 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 581                                            const struct i965_surface *src_surface,
 582                                            const VARectangle *src_rect,
 583                                            struct i965_surface *dst_surface,
 584                                            const VARectangle *dst_rect,
 585                                            void *filter_param);
 586
 587 static struct pp_module pp_modules_gen7[] = {
 588     {
 589         {
 590             "NULL module (for testing)",
 591             PP_NULL,
 592             pp_null_gen7,
 593             sizeof(pp_null_gen7),
 594             NULL,
 595         },
 596
 597         pp_null_initialize,
 598     },
 599
 600     {
 601         {
 602             "NV12_NV12",
 603             PP_NV12_LOAD_SAVE_N12,
 604             pp_nv12_load_save_nv12_gen7,
 605             sizeof(pp_nv12_load_save_nv12_gen7),
 606             NULL,
 607         },
 608
 609         gen7_pp_plx_avs_initialize,
 610     },
 611
 612     {
 613         {
 614             "NV12_PL3",
 615             PP_NV12_LOAD_SAVE_PL3,
 616             pp_nv12_load_save_pl3_gen7,
 617             sizeof(pp_nv12_load_save_pl3_gen7),
 618             NULL,
 619         },
 620
 621         gen7_pp_plx_avs_initialize,
 622     },
 623
 624     {
 625         {
 626             "PL3_NV12",
 627             PP_PL3_LOAD_SAVE_N12,
 628             pp_pl3_load_save_nv12_gen7,
 629             sizeof(pp_pl3_load_save_nv12_gen7),
 630             NULL,
 631         },
 632
 633         gen7_pp_plx_avs_initialize,
 634     },
 635
 636     {
 637         {
 638             "PL3_PL3",
 639             PP_PL3_LOAD_SAVE_N12,
 640             pp_pl3_load_save_pl3_gen7,
 641             sizeof(pp_pl3_load_save_pl3_gen7),
 642             NULL,
 643         },
 644
 645         gen7_pp_plx_avs_initialize,
 646     },
 647
 648     {
 649         {
 650             "NV12 Scaling module",
 651             PP_NV12_SCALING,
 652             pp_nv12_scaling_gen7,
 653             sizeof(pp_nv12_scaling_gen7),
 654             NULL,
 655         },
 656
 657         gen7_pp_plx_avs_initialize,
 658     },
 659
 660     {
 661         {
 662             "NV12 AVS module",
 663             PP_NV12_AVS,
 664             pp_nv12_avs_gen7,
 665             sizeof(pp_nv12_avs_gen7),
 666             NULL,
 667         },
 668
 669         gen7_pp_plx_avs_initialize,
 670     },
 671
 672     {
 673         {
 674             "NV12 DNDI module",
 675             PP_NV12_DNDI,
 676             pp_nv12_dndi_gen7,
 677             sizeof(pp_nv12_dndi_gen7),
 678             NULL,
 679         },
 680
 681         gen7_pp_nv12_dndi_initialize,
 682     },
 683
 684     {
 685         {
 686             "NV12 DN module",
 687             PP_NV12_DN,
 688             pp_nv12_dn_gen7,
 689             sizeof(pp_nv12_dn_gen7),
 690             NULL,
 691         },
 692
 693         gen7_pp_nv12_dn_initialize,
 694     },
 695     {
 696         {
 697             "NV12_PA module",
 698             PP_NV12_LOAD_SAVE_PA,
 699             pp_nv12_load_save_pa_gen7,
 700             sizeof(pp_nv12_load_save_pa_gen7),
 701             NULL,
 702         },
 703
 704         gen7_pp_plx_avs_initialize,
 705     },
 706
 707     {
 708         {
 709             "PL3_PA module",
 710             PP_PL3_LOAD_SAVE_PA,
 711             pp_pl3_load_save_pa_gen7,
 712             sizeof(pp_pl3_load_save_pa_gen7),
 713             NULL,
 714         },
 715
 716         gen7_pp_plx_avs_initialize,
 717     },
 718
 719     {
 720         {
 721             "PA_NV12 module",
 722             PP_PA_LOAD_SAVE_NV12,
 723             pp_pa_load_save_nv12_gen7,
 724             sizeof(pp_pa_load_save_nv12_gen7),
 725             NULL,
 726         },
 727
 728         gen7_pp_plx_avs_initialize,
 729     },
 730
 731     {
 732         {
 733             "PA_PL3 module",
 734             PP_PA_LOAD_SAVE_PL3,
 735             pp_pa_load_save_pl3_gen7,
 736             sizeof(pp_pa_load_save_pl3_gen7),
 737             NULL,
 738         },
 739
 740         gen7_pp_plx_avs_initialize,
 741     },
 742
 743 };
 744
 745 static int
 746 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 747 {
 748     struct i965_driver_data *i965 = i965_driver_data(ctx);
 749     int fourcc;
 750
 751     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 752         struct object_image *obj_image = IMAGE(surface->id);
 753         fourcc = obj_image->image.format.fourcc;
 754     } else {
 755         struct object_surface *obj_surface = SURFACE(surface->id);
 756         fourcc = obj_surface->fourcc;
 757     }
 758
 759     return fourcc;
 760 }
 761
 762 static void
 763 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 764 {
 765     switch (tiling) {
 766     case I915_TILING_NONE:
 767         ss->ss3.tiled_surface = 0;
 768         ss->ss3.tile_walk = 0;
 769         break;
 770     case I915_TILING_X:
 771         ss->ss3.tiled_surface = 1;
 772         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 773         break;
 774     case I915_TILING_Y:
 775         ss->ss3.tiled_surface = 1;
 776         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 777         break;
 778     }
 779 }
 780
 781 static void
 782 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 783 {
 784     switch (tiling) {
 785     case I915_TILING_NONE:
 786         ss->ss2.tiled_surface = 0;
 787         ss->ss2.tile_walk = 0;
 788         break;
 789     case I915_TILING_X:
 790         ss->ss2.tiled_surface = 1;
 791         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 792         break;
 793     case I915_TILING_Y:
 794         ss->ss2.tiled_surface = 1;
 795         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 796         break;
 797     }
 798 }
 799
 800 static void
 801 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 802 {
 803     switch (tiling) {
 804     case I915_TILING_NONE:
 805         ss->ss0.tiled_surface = 0;
 806         ss->ss0.tile_walk = 0;
 807         break;
 808     case I915_TILING_X:
 809         ss->ss0.tiled_surface = 1;
 810         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 811         break;
 812     case I915_TILING_Y:
 813         ss->ss0.tiled_surface = 1;
 814         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 815         break;
 816     }
 817 }
 818
 819 static void
 820 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 821 {
 822     switch (tiling) {
 823     case I915_TILING_NONE:
 824         ss->ss2.tiled_surface = 0;
 825         ss->ss2.tile_walk = 0;
 826         break;
 827     case I915_TILING_X:
 828         ss->ss2.tiled_surface = 1;
 829         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 830         break;
 831     case I915_TILING_Y:
 832         ss->ss2.tiled_surface = 1;
 833         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 834         break;
 835     }
 836 }
 837
 838 static void
 839 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 840 {
 841     struct i965_interface_descriptor *desc;
 842     dri_bo *bo;
 843     int pp_index = pp_context->current_pp;
 844
 845     bo = pp_context->idrt.bo;
 846     dri_bo_map(bo, 1);
 847     assert(bo->virtual);
 848     desc = bo->virtual;
 849     memset(desc, 0, sizeof(*desc));
 850     desc->desc0.grf_reg_blocks = 10;
 851     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 852     desc->desc1.const_urb_entry_read_offset = 0;
 853     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 854     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 855     desc->desc2.sampler_count = 0;
 856     desc->desc3.binding_table_entry_count = 0;
 857     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 858
 859     dri_bo_emit_reloc(bo,
 860                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 861                       desc->desc0.grf_reg_blocks,
 862                       offsetof(struct i965_interface_descriptor, desc0),
 863                       pp_context->pp_modules[pp_index].kernel.bo);
 864
 865     dri_bo_emit_reloc(bo,
 866                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 867                       desc->desc2.sampler_count << 2,
 868                       offsetof(struct i965_interface_descriptor, desc2),
 869                       pp_context->sampler_state_table.bo);
 870
 871     dri_bo_unmap(bo);
 872     pp_context->idrt.num_interface_descriptors++;
 873 }
 874
 875 static void
 876 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 877 {
 878     struct i965_vfe_state *vfe_state;
 879     dri_bo *bo;
 880
 881     bo = pp_context->vfe_state.bo;
 882     dri_bo_map(bo, 1);
 883     assert(bo->virtual);
 884     vfe_state = bo->virtual;
 885     memset(vfe_state, 0, sizeof(*vfe_state));
 886     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 887     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 888     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 889     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 890     vfe_state->vfe1.children_present = 0;
 891     vfe_state->vfe2.interface_descriptor_base =
 892         pp_context->idrt.bo->offset >> 4; /* reloc */
 893     dri_bo_emit_reloc(bo,
 894                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 895                       0,
 896                       offsetof(struct i965_vfe_state, vfe2),
 897                       pp_context->idrt.bo);
 898     dri_bo_unmap(bo);
 899 }
 900
 901 static void
 902 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 903 {
 904     unsigned char *constant_buffer;
 905     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 906
 907     assert(sizeof(*pp_static_parameter) == 128);
 908     dri_bo_map(pp_context->curbe.bo, 1);
 909     assert(pp_context->curbe.bo->virtual);
 910     constant_buffer = pp_context->curbe.bo->virtual;
 911     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 912     dri_bo_unmap(pp_context->curbe.bo);
 913 }
 914
 915 static void
 916 ironlake_pp_states_setup(VADriverContextP ctx,
 917                          struct i965_post_processing_context *pp_context)
 918 {
 919     ironlake_pp_interface_descriptor_table(pp_context);
 920     ironlake_pp_vfe_state(pp_context);
 921     ironlake_pp_upload_constants(pp_context);
 922 }
 923
 924 static void
 925 ironlake_pp_pipeline_select(VADriverContextP ctx,
 926                             struct i965_post_processing_context *pp_context)
 927 {
 928     struct intel_batchbuffer *batch = pp_context->batch;
 929
 930     BEGIN_BATCH(batch, 1);
 931     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 932     ADVANCE_BATCH(batch);
 933 }
 934
 935 static void
 936 ironlake_pp_urb_layout(VADriverContextP ctx,
 937                        struct i965_post_processing_context *pp_context)
 938 {
 939     struct intel_batchbuffer *batch = pp_context->batch;
 940     unsigned int vfe_fence, cs_fence;
 941
 942     vfe_fence = pp_context->urb.cs_start;
 943     cs_fence = pp_context->urb.size;
 944
 945     BEGIN_BATCH(batch, 3);
 946     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 947     OUT_BATCH(batch, 0);
 948     OUT_BATCH(batch,
 949               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 950               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 951     ADVANCE_BATCH(batch);
 952 }
 953
 954 static void
 955 ironlake_pp_state_base_address(VADriverContextP ctx,
 956                                struct i965_post_processing_context *pp_context)
 957 {
 958     struct intel_batchbuffer *batch = pp_context->batch;
 959
 960     BEGIN_BATCH(batch, 8);
 961     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 962     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 963     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 964     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 965     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 966     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 967     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 968     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 969     ADVANCE_BATCH(batch);
 970 }
 971
 972 static void
 973 ironlake_pp_state_pointers(VADriverContextP ctx,
 974                            struct i965_post_processing_context *pp_context)
 975 {
 976     struct intel_batchbuffer *batch = pp_context->batch;
 977
 978     BEGIN_BATCH(batch, 3);
 979     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 980     OUT_BATCH(batch, 0);
 981     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 982     ADVANCE_BATCH(batch);
 983 }
 984
 985 static void
 986 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 987                           struct i965_post_processing_context *pp_context)
 988 {
 989     struct intel_batchbuffer *batch = pp_context->batch;
 990
 991     BEGIN_BATCH(batch, 2);
 992     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 993     OUT_BATCH(batch,
 994               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 995               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 996     ADVANCE_BATCH(batch);
 997 }
 998
 999 static void
1000 ironlake_pp_constant_buffer(VADriverContextP ctx,
1001                             struct i965_post_processing_context *pp_context)
1002 {
1003     struct intel_batchbuffer *batch = pp_context->batch;
1004
1005     BEGIN_BATCH(batch, 2);
1006     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1007     OUT_RELOC(batch, pp_context->curbe.bo,
1008               I915_GEM_DOMAIN_INSTRUCTION, 0,
1009               pp_context->urb.size_cs_entry - 1);
1010     ADVANCE_BATCH(batch);
1011 }
1012
1013 static void
1014 ironlake_pp_object_walker(VADriverContextP ctx,
1015                           struct i965_post_processing_context *pp_context)
1016 {
1017     struct intel_batchbuffer *batch = pp_context->batch;
1018     int x, x_steps, y, y_steps;
1019     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1020
1021     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1022     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1023
1024     for (y = 0; y < y_steps; y++) {
1025         for (x = 0; x < x_steps; x++) {
1026             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1027                 BEGIN_BATCH(batch, 20);
1028                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1029                 OUT_BATCH(batch, 0);
1030                 OUT_BATCH(batch, 0); /* no indirect data */
1031                 OUT_BATCH(batch, 0);
1032
1033                 /* inline data grf 5-6 */
1034                 assert(sizeof(*pp_inline_parameter) == 64);
1035                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1036
1037                 ADVANCE_BATCH(batch);
1038             }
1039         }
1040     }
1041 }
1042
1043 static void
1044 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1045                            struct i965_post_processing_context *pp_context)
1046 {
1047     struct intel_batchbuffer *batch = pp_context->batch;
1048
1049     intel_batchbuffer_start_atomic(batch, 0x1000);
1050     intel_batchbuffer_emit_mi_flush(batch);
1051     ironlake_pp_pipeline_select(ctx, pp_context);
1052     ironlake_pp_state_base_address(ctx, pp_context);
1053     ironlake_pp_state_pointers(ctx, pp_context);
1054     ironlake_pp_urb_layout(ctx, pp_context);
1055     ironlake_pp_cs_urb_layout(ctx, pp_context);
1056     ironlake_pp_constant_buffer(ctx, pp_context);
1057     ironlake_pp_object_walker(ctx, pp_context);
1058     intel_batchbuffer_end_atomic(batch);
1059 }
1060
1061 // update u/v offset when the surface format are packed yuv
1062 static void i965_update_src_surface_uv_offset(
1063     VADriverContextP    ctx,
1064     struct i965_post_processing_context *pp_context,
1065     const struct i965_surface *surface)
1066 {
1067     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1068     int fourcc = pp_get_surface_fourcc(ctx, surface);
1069
1070     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1071         pp_static_parameter->grf1.source_packed_u_offset = 1;
1072         pp_static_parameter->grf1.source_packed_v_offset = 3;
1073     }
1074     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1075         pp_static_parameter->grf1.source_packed_y_offset = 1;
1076         pp_static_parameter->grf1.source_packed_v_offset = 2;
1077     }
1078
1079 }
1080
1081 static void i965_update_dst_surface_uv_offset(
1082     VADriverContextP    ctx,
1083     struct i965_post_processing_context *pp_context,
1084     const struct i965_surface *surface)
1085 {
1086     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1087     int fourcc = pp_get_surface_fourcc(ctx, surface);
1088
1089     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
1090         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1091         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1092     }
1093     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
1094         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1095         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1096     }
1097
1098 }
1099
1100 static void
1101 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1102                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1103                           int width, int height, int pitch, int format,
1104                           int index, int is_target)
1105 {
1106     struct i965_surface_state *ss;
1107     dri_bo *ss_bo;
1108     unsigned int tiling;
1109     unsigned int swizzle;
1110
1111     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1112     ss_bo = pp_context->surface_state_binding_table.bo;
1113     assert(ss_bo);
1114
1115     dri_bo_map(ss_bo, True);
1116     assert(ss_bo->virtual);
1117     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1118     memset(ss, 0, sizeof(*ss));
1119     ss->ss0.surface_type = I965_SURFACE_2D;
1120     ss->ss0.surface_format = format;
1121     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1122     ss->ss2.width = width - 1;
1123     ss->ss2.height = height - 1;
1124     ss->ss3.pitch = pitch - 1;
1125     pp_set_surface_tiling(ss, tiling);
1126     dri_bo_emit_reloc(ss_bo,
1127                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1128                       surf_bo_offset,
1129                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1130                       surf_bo);
1131     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1132     dri_bo_unmap(ss_bo);
1133 }
1134
1135 static void
1136 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1137                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1138                            int width, int height, int wpitch,
1139                            int xoffset, int yoffset,
1140                            int format, int interleave_chroma,
1141                            int index)
1142 {
1143     struct i965_surface_state2 *ss2;
1144     dri_bo *ss2_bo;
1145     unsigned int tiling;
1146     unsigned int swizzle;
1147
1148     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1149     ss2_bo = pp_context->surface_state_binding_table.bo;
1150     assert(ss2_bo);
1151
1152     dri_bo_map(ss2_bo, True);
1153     assert(ss2_bo->virtual);
1154     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1155     memset(ss2, 0, sizeof(*ss2));
1156     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1157     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1158     ss2->ss1.width = width - 1;
1159     ss2->ss1.height = height - 1;
1160     ss2->ss2.pitch = wpitch - 1;
1161     ss2->ss2.interleave_chroma = interleave_chroma;
1162     ss2->ss2.surface_format = format;
1163     ss2->ss3.x_offset_for_cb = xoffset;
1164     ss2->ss3.y_offset_for_cb = yoffset;
1165     pp_set_surface2_tiling(ss2, tiling);
1166     dri_bo_emit_reloc(ss2_bo,
1167                       I915_GEM_DOMAIN_RENDER, 0,
1168                       surf_bo_offset,
1169                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1170                       surf_bo);
1171     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1172     dri_bo_unmap(ss2_bo);
1173 }
1174
1175 static void
1176 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1177                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1178                           int width, int height, int pitch, int format,
1179                           int index, int is_target)
1180 {
1181     struct gen7_surface_state *ss;
1182     dri_bo *ss_bo;
1183     unsigned int tiling;
1184     unsigned int swizzle;
1185
1186     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1187     ss_bo = pp_context->surface_state_binding_table.bo;
1188     assert(ss_bo);
1189
1190     dri_bo_map(ss_bo, True);
1191     assert(ss_bo->virtual);
1192     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1193     memset(ss, 0, sizeof(*ss));
1194     ss->ss0.surface_type = I965_SURFACE_2D;
1195     ss->ss0.surface_format = format;
1196     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1197     ss->ss2.width = width - 1;
1198     ss->ss2.height = height - 1;
1199     ss->ss3.pitch = pitch - 1;
1200     gen7_pp_set_surface_tiling(ss, tiling);
1201     dri_bo_emit_reloc(ss_bo,
1202                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1203                       surf_bo_offset,
1204                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1205                       surf_bo);
1206     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1207     dri_bo_unmap(ss_bo);
1208 }
1209
1210 static void
1211 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1212                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1213                            int width, int height, int wpitch,
1214                            int xoffset, int yoffset,
1215                            int format, int interleave_chroma,
1216                            int index)
1217 {
1218     struct gen7_surface_state2 *ss2;
1219     dri_bo *ss2_bo;
1220     unsigned int tiling;
1221     unsigned int swizzle;
1222
1223     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1224     ss2_bo = pp_context->surface_state_binding_table.bo;
1225     assert(ss2_bo);
1226
1227     dri_bo_map(ss2_bo, True);
1228     assert(ss2_bo->virtual);
1229     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1230     memset(ss2, 0, sizeof(*ss2));
1231     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1232     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1233     ss2->ss1.width = width - 1;
1234     ss2->ss1.height = height - 1;
1235     ss2->ss2.pitch = wpitch - 1;
1236     ss2->ss2.interleave_chroma = interleave_chroma;
1237     ss2->ss2.surface_format = format;
1238     ss2->ss3.x_offset_for_cb = xoffset;
1239     ss2->ss3.y_offset_for_cb = yoffset;
1240     gen7_pp_set_surface2_tiling(ss2, tiling);
1241     dri_bo_emit_reloc(ss2_bo,
1242                       I915_GEM_DOMAIN_RENDER, 0,
1243                       surf_bo_offset,
1244                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1245                       surf_bo);
1246     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1247     dri_bo_unmap(ss2_bo);
1248 }
1249
1250 static void
1251 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1252                                 const struct i965_surface *surface,
1253                                 int base_index, int is_target,
1254                                 int *width, int *height, int *pitch, int *offset)
1255 {
1256     struct i965_driver_data *i965 = i965_driver_data(ctx);
1257     struct object_surface *obj_surface;
1258     struct object_image *obj_image;
1259     dri_bo *bo;
1260     int fourcc = pp_get_surface_fourcc(ctx, surface);
1261     const int Y = 0;
1262     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1263     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1264     const int UV = 1;
1265     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1266     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1267
1268     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1269         obj_surface = SURFACE(surface->id);
1270         bo = obj_surface->bo;
1271         width[0] = obj_surface->orig_width;
1272         height[0] = obj_surface->orig_height;
1273         pitch[0] = obj_surface->width;
1274         offset[0] = 0;
1275
1276         if (packed_yuv ) {
1277             width[0] = obj_surface->orig_width * 2;
1278             pitch[0] = obj_surface->width * 2;
1279         }
1280         else if (interleaved_uv) {
1281             width[1] = obj_surface->orig_width;
1282             height[1] = obj_surface->orig_height / 2;
1283             pitch[1] = obj_surface->width;
1284             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1285         } else {
1286             width[1] = obj_surface->orig_width / 2;
1287             height[1] = obj_surface->orig_height / 2;
1288             pitch[1] = obj_surface->width / 2;
1289             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1290             width[2] = obj_surface->orig_width / 2;
1291             height[2] = obj_surface->orig_height / 2;
1292             pitch[2] = obj_surface->width / 2;
1293             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1294         }
1295     } else {
1296         obj_image = IMAGE(surface->id);
1297         bo = obj_image->bo;
1298         width[0] = obj_image->image.width;
1299         height[0] = obj_image->image.height;
1300         pitch[0] = obj_image->image.pitches[0];
1301         offset[0] = obj_image->image.offsets[0];
1302
1303         if (packed_yuv ) {
1304             width[0] = obj_image->image.width * 2;
1305         }
1306         else if (interleaved_uv) {
1307             width[1] = obj_image->image.width;
1308             height[1] = obj_image->image.height / 2;
1309             pitch[1] = obj_image->image.pitches[1];
1310             offset[1] = obj_image->image.offsets[1];
1311         } else {
1312             width[1] = obj_image->image.width / 2;
1313             height[1] = obj_image->image.height / 2;
1314             pitch[1] = obj_image->image.pitches[1];
1315             offset[1] = obj_image->image.offsets[1];
1316             width[2] = obj_image->image.width / 2;
1317             height[2] = obj_image->image.height / 2;
1318             pitch[2] = obj_image->image.pitches[2];
1319             offset[2] = obj_image->image.offsets[2];
1320         }
1321     }
1322
1323     /* Y surface */
1324     i965_pp_set_surface_state(ctx, pp_context,
1325                               bo, offset[Y],
1326                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1327                               base_index, is_target);
1328
1329     if (!packed_yuv) {
1330         if (interleaved_uv) {
1331             i965_pp_set_surface_state(ctx, pp_context,
1332                                       bo, offset[UV],
1333                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1334                                       base_index + 1, is_target);
1335         } else {
1336             /* U surface */
1337             i965_pp_set_surface_state(ctx, pp_context,
1338                                       bo, offset[U],
1339                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1340                                       base_index + 1, is_target);
1341
1342             /* V surface */
1343             i965_pp_set_surface_state(ctx, pp_context,
1344                                       bo, offset[V],
1345                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1346                                       base_index + 2, is_target);
1347         }
1348     }
1349
1350 }
1351
1352 static void
1353 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1354                                      const struct i965_surface *surface,
1355                                      int base_index, int is_target,
1356                                      int *width, int *height, int *pitch, int *offset)
1357 {
1358     struct i965_driver_data *i965 = i965_driver_data(ctx);
1359     struct object_surface *obj_surface;
1360     struct object_image *obj_image;
1361     dri_bo *bo;
1362     int fourcc = pp_get_surface_fourcc(ctx, surface);
1363     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1364                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1365     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1366                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1367     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1368     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1369
1370     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1371         obj_surface = SURFACE(surface->id);
1372         bo = obj_surface->bo;
1373         width[0] = obj_surface->orig_width;
1374         height[0] = obj_surface->orig_height;
1375         pitch[0] = obj_surface->width;
1376         offset[0] = 0;
1377
1378         if (packed_yuv) {
1379             if (is_target)
1380                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1381             else
1382                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1383
1384             pitch[0] = obj_surface->width * 2;
1385         }
1386
1387         width[1] = obj_surface->cb_cr_width;
1388         height[1] = obj_surface->cb_cr_height;
1389         pitch[1] = obj_surface->cb_cr_pitch;
1390         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1391
1392         width[2] = obj_surface->cb_cr_width;
1393         height[2] = obj_surface->cb_cr_height;
1394         pitch[2] = obj_surface->cb_cr_pitch;
1395         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1396     } else {
1397         obj_image = IMAGE(surface->id);
1398         bo = obj_image->bo;
1399         width[0] = obj_image->image.width;
1400         height[0] = obj_image->image.height;
1401         pitch[0] = obj_image->image.pitches[0];
1402         offset[0] = obj_image->image.offsets[0];
1403
1404         if (packed_yuv) {
1405             if (is_target)
1406                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1407             else
1408                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1409         } else if (interleaved_uv) {
1410             width[1] = obj_image->image.width / 2;
1411             height[1] = obj_image->image.height / 2;
1412             pitch[1] = obj_image->image.pitches[1];
1413             offset[1] = obj_image->image.offsets[1];
1414         } else {
1415             width[1] = obj_image->image.width / 2;
1416             height[1] = obj_image->image.height / 2;
1417             pitch[1] = obj_image->image.pitches[U];
1418             offset[1] = obj_image->image.offsets[U];
1419             width[2] = obj_image->image.width / 2;
1420             height[2] = obj_image->image.height / 2;
1421             pitch[2] = obj_image->image.pitches[V];
1422             offset[2] = obj_image->image.offsets[V];
1423         }
1424     }
1425
1426     if (is_target) {
1427         gen7_pp_set_surface_state(ctx, pp_context,
1428                                   bo, 0,
1429                                   width[0] / 4, height[0], pitch[0],
1430                                   I965_SURFACEFORMAT_R8_SINT,
1431                                   base_index, 1);
1432
1433         if (!packed_yuv) {
1434             if (interleaved_uv) {
1435                 gen7_pp_set_surface_state(ctx, pp_context,
1436                                           bo, offset[1],
1437                                           width[1] / 2, height[1], pitch[1],
1438                                           I965_SURFACEFORMAT_R8G8_SINT,
1439                                           base_index + 1, 1);
1440             } else {
1441                 gen7_pp_set_surface_state(ctx, pp_context,
1442                                           bo, offset[1],
1443                                           width[1] / 4, height[1], pitch[1],
1444                                           I965_SURFACEFORMAT_R8_SINT,
1445                                           base_index + 1, 1);
1446                 gen7_pp_set_surface_state(ctx, pp_context,
1447                                           bo, offset[2],
1448                                           width[2] / 4, height[2], pitch[2],
1449                                           I965_SURFACEFORMAT_R8_SINT,
1450                                           base_index + 2, 1);
1451             }
1452         }
1453     } else {
1454         int format0 = SURFACE_FORMAT_Y8_UNORM;
1455
1456         switch (fourcc) {
1457         case VA_FOURCC('Y', 'U', 'Y', '2'):
1458             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1459             break;
1460
1461         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1462             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1463             break;
1464
1465         default:
1466             break;
1467         }
1468
1469         gen7_pp_set_surface2_state(ctx, pp_context,
1470                                    bo, offset[0],
1471                                    width[0], height[0], pitch[0],
1472                                    0, 0,
1473                                    format0, 0,
1474                                    base_index);
1475
1476         if (!packed_yuv) {
1477             if (interleaved_uv) {
1478                 gen7_pp_set_surface2_state(ctx, pp_context,
1479                                            bo, offset[1],
1480                                            width[1], height[1], pitch[1],
1481                                            0, 0,
1482                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1483                                            base_index + 1);
1484             } else {
1485                 gen7_pp_set_surface2_state(ctx, pp_context,
1486                                            bo, offset[1],
1487                                            width[1], height[1], pitch[1],
1488                                            0, 0,
1489                                            SURFACE_FORMAT_R8_UNORM, 0,
1490                                            base_index + 1);
1491                 gen7_pp_set_surface2_state(ctx, pp_context,
1492                                            bo, offset[2],
1493                                            width[2], height[2], pitch[2],
1494                                            0, 0,
1495                                            SURFACE_FORMAT_R8_UNORM, 0,
1496                                            base_index + 2);
1497             }
1498         }
1499     }
1500 }
1501
1502 static int
1503 pp_null_x_steps(void *private_context)
1504 {
1505     return 1;
1506 }
1507
1508 static int
1509 pp_null_y_steps(void *private_context)
1510 {
1511     return 1;
1512 }
1513
1514 static int
1515 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1516 {
1517     return 0;
1518 }
1519
1520 static VAStatus
1521 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1522                    const struct i965_surface *src_surface,
1523                    const VARectangle *src_rect,
1524                    struct i965_surface *dst_surface,
1525                    const VARectangle *dst_rect,
1526                    void *filter_param)
1527 {
1528     /* private function & data */
1529     pp_context->pp_x_steps = pp_null_x_steps;
1530     pp_context->pp_y_steps = pp_null_y_steps;
1531     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1532
1533     dst_surface->flags = src_surface->flags;
1534
1535     return VA_STATUS_SUCCESS;
1536 }
1537
1538 static int
1539 pp_load_save_x_steps(void *private_context)
1540 {
1541     return 1;
1542 }
1543
1544 static int
1545 pp_load_save_y_steps(void *private_context)
1546 {
1547     struct pp_load_save_context *pp_load_save_context = private_context;
1548
1549     return pp_load_save_context->dest_h / 8;
1550 }
1551
1552 static int
1553 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1554 {
1555     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1556
1557     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1558     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1559     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1560     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1561
1562     return 0;
1563 }
1564
1565 static VAStatus
1566 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1567                                 const struct i965_surface *src_surface,
1568                                 const VARectangle *src_rect,
1569                                 struct i965_surface *dst_surface,
1570                                 const VARectangle *dst_rect,
1571                                 void *filter_param)
1572 {
1573     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1574     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1575     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1576     int width[3], height[3], pitch[3], offset[3];
1577     const int Y = 0;
1578
1579     /* source surface */
1580     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1581                                     width, height, pitch, offset);
1582
1583     /* destination surface */
1584     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1585                                     width, height, pitch, offset);
1586
1587     /* private function & data */
1588     pp_context->pp_x_steps = pp_load_save_x_steps;
1589     pp_context->pp_y_steps = pp_load_save_y_steps;
1590     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1591     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1592     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1593
1594     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1595     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1596
1597     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1598     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1599
1600     // update u/v offset for packed yuv
1601     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
1602     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
1603
1604     dst_surface->flags = src_surface->flags;
1605
1606     return VA_STATUS_SUCCESS;
1607 }
1608
1609 static int
1610 pp_scaling_x_steps(void *private_context)
1611 {
1612     return 1;
1613 }
1614
1615 static int
1616 pp_scaling_y_steps(void *private_context)
1617 {
1618     struct pp_scaling_context *pp_scaling_context = private_context;
1619
1620     return pp_scaling_context->dest_h / 8;
1621 }
1622
1623 static int
1624 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1625 {
1626     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1627     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1628     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1629     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1630     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1631
1632     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1633     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1634     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1635     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1636
1637     return 0;
1638 }
1639
1640 static VAStatus
1641 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1642                            const struct i965_surface *src_surface,
1643                            const VARectangle *src_rect,
1644                            struct i965_surface *dst_surface,
1645                            const VARectangle *dst_rect,
1646                            void *filter_param)
1647 {
1648     struct i965_driver_data *i965 = i965_driver_data(ctx);
1649     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1650     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1651     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1652     struct object_surface *obj_surface;
1653     struct i965_sampler_state *sampler_state;
1654     int in_w, in_h, in_wpitch, in_hpitch;
1655     int out_w, out_h, out_wpitch, out_hpitch;
1656
1657     /* source surface */
1658     obj_surface = SURFACE(src_surface->id);
1659     in_w = obj_surface->orig_width;
1660     in_h = obj_surface->orig_height;
1661     in_wpitch = obj_surface->width;
1662     in_hpitch = obj_surface->height;
1663
1664     /* source Y surface index 1 */
1665     i965_pp_set_surface_state(ctx, pp_context,
1666                               obj_surface->bo, 0,
1667                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1668                               1, 0);
1669
1670     /* source UV surface index 2 */
1671     i965_pp_set_surface_state(ctx, pp_context,
1672                               obj_surface->bo, in_wpitch * in_hpitch,
1673                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1674                               2, 0);
1675
1676     /* destination surface */
1677     obj_surface = SURFACE(dst_surface->id);
1678     out_w = obj_surface->orig_width;
1679     out_h = obj_surface->orig_height;
1680     out_wpitch = obj_surface->width;
1681     out_hpitch = obj_surface->height;
1682
1683     /* destination Y surface index 7 */
1684     i965_pp_set_surface_state(ctx, pp_context,
1685                               obj_surface->bo, 0,
1686                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1687                               7, 1);
1688
1689     /* destination UV surface index 8 */
1690     i965_pp_set_surface_state(ctx, pp_context,
1691                               obj_surface->bo, out_wpitch * out_hpitch,
1692                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1693                               8, 1);
1694
1695     /* sampler state */
1696     dri_bo_map(pp_context->sampler_state_table.bo, True);
1697     assert(pp_context->sampler_state_table.bo->virtual);
1698     sampler_state = pp_context->sampler_state_table.bo->virtual;
1699
1700     /* SIMD16 Y index 1 */
1701     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1702     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1703     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1704     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1705     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1706
1707     /* SIMD16 UV index 2 */
1708     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1709     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1710     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1711     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1712     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1713
1714     dri_bo_unmap(pp_context->sampler_state_table.bo);
1715
1716     /* private function & data */
1717     pp_context->pp_x_steps = pp_scaling_x_steps;
1718     pp_context->pp_y_steps = pp_scaling_y_steps;
1719     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1720
1721     pp_scaling_context->dest_x = dst_rect->x;
1722     pp_scaling_context->dest_y = dst_rect->y;
1723     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1724     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1725     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1726     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1727
1728     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1729
1730     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1731     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1732     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1733     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1734     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1735
1736     dst_surface->flags = src_surface->flags;
1737
1738     return VA_STATUS_SUCCESS;
1739 }
1740
1741 static int
1742 pp_avs_x_steps(void *private_context)
1743 {
1744     struct pp_avs_context *pp_avs_context = private_context;
1745
1746     return pp_avs_context->dest_w / 16;
1747 }
1748
1749 static int
1750 pp_avs_y_steps(void *private_context)
1751 {
1752     return 1;
1753 }
1754
1755 static int
1756 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1757 {
1758     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1759     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1760     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1761     float src_x_steping, src_y_steping, video_step_delta;
1762     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1763
1764     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1765         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1766         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1767     } else if (tmp_w >= pp_avs_context->dest_w) {
1768         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1769         pp_inline_parameter->grf6.video_step_delta = 0;
1770
1771         if (x == 0) {
1772             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1773                 pp_avs_context->src_normalized_x;
1774         } else {
1775             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1776             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1777             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1778                 16 * 15 * video_step_delta / 2;
1779         }
1780     } else {
1781         int n0, n1, n2, nls_left, nls_right;
1782         int factor_a = 5, factor_b = 4;
1783         float f;
1784
1785         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1786         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1787         n2 = tmp_w / (16 * factor_a);
1788         nls_left = n0 + n2;
1789         nls_right = n1 + n2;
1790         f = (float) n2 * 16 / tmp_w;
1791
1792         if (n0 < 5) {
1793             pp_inline_parameter->grf6.video_step_delta = 0.0;
1794
1795             if (x == 0) {
1796                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1797                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1798             } else {
1799                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1800                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1801                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1802                     16 * 15 * video_step_delta / 2;
1803             }
1804         } else {
1805             if (x < nls_left) {
1806                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1807                 float a = f / (nls_left * 16 * factor_b);
1808                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1809
1810                 pp_inline_parameter->grf6.video_step_delta = b;
1811
1812                 if (x == 0) {
1813                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1814                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1815                 } else {
1816                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1817                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1818                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1819                         16 * 15 * video_step_delta / 2;
1820                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1821                 }
1822             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1823                 /* scale the center linearly */
1824                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1825                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1826                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1827                     16 * 15 * video_step_delta / 2;
1828                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1829                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1830             } else {
1831                 float a = f / (nls_right * 16 * factor_b);
1832                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1833
1834                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1835                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1836                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1837                     16 * 15 * video_step_delta / 2;
1838                 pp_inline_parameter->grf6.video_step_delta = -b;
1839
1840                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1841                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1842                 else
1843                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1844             }
1845         }
1846     }
1847
1848     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1849     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1850     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1851     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1852
1853     return 0;
1854 }
1855
1856 static VAStatus
1857 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1858                        const struct i965_surface *src_surface,
1859                        const VARectangle *src_rect,
1860                        struct i965_surface *dst_surface,
1861                        const VARectangle *dst_rect,
1862                        void *filter_param,
1863                        int nlas)
1864 {
1865     struct i965_driver_data *i965 = i965_driver_data(ctx);
1866     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1867     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1868     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1869     struct object_surface *obj_surface;
1870     struct i965_sampler_8x8 *sampler_8x8;
1871     struct i965_sampler_8x8_state *sampler_8x8_state;
1872     int index;
1873     int in_w, in_h, in_wpitch, in_hpitch;
1874     int out_w, out_h, out_wpitch, out_hpitch;
1875     int i;
1876
1877     /* surface */
1878     obj_surface = SURFACE(src_surface->id);
1879     in_w = obj_surface->orig_width;
1880     in_h = obj_surface->orig_height;
1881     in_wpitch = obj_surface->width;
1882     in_hpitch = obj_surface->height;
1883
1884     /* source Y surface index 1 */
1885     i965_pp_set_surface2_state(ctx, pp_context,
1886                                obj_surface->bo, 0,
1887                                in_w, in_h, in_wpitch,
1888                                0, 0,
1889                                SURFACE_FORMAT_Y8_UNORM, 0,
1890                                1);
1891
1892     /* source UV surface index 2 */
1893     i965_pp_set_surface2_state(ctx, pp_context,
1894                                obj_surface->bo, in_wpitch * in_hpitch,
1895                                in_w / 2, in_h / 2, in_wpitch,
1896                                0, 0,
1897                                SURFACE_FORMAT_R8B8_UNORM, 0,
1898                                2);
1899
1900     /* destination surface */
1901     obj_surface = SURFACE(dst_surface->id);
1902     out_w = obj_surface->orig_width;
1903     out_h = obj_surface->orig_height;
1904     out_wpitch = obj_surface->width;
1905     out_hpitch = obj_surface->height;
1906     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1907
1908     /* destination Y surface index 7 */
1909     i965_pp_set_surface_state(ctx, pp_context,
1910                               obj_surface->bo, 0,
1911                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1912                               7, 1);
1913
1914     /* destination UV surface index 8 */
1915     i965_pp_set_surface_state(ctx, pp_context,
1916                               obj_surface->bo, out_wpitch * out_hpitch,
1917                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1918                               8, 1);
1919
1920     /* sampler 8x8 state */
1921     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1922     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1923     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1924     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1925     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1926
1927     for (i = 0; i < 17; i++) {
1928         /* for Y channel, currently ignore */
1929         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1930         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1931         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1932         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1933         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1934         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1935         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1936         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1937         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1938         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1939         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1940         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1941         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1942         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1943         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1944         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1945         /* for U/V channel, 0.25 */
1946         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1947         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1948         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1949         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1950         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1951         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1952         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1953         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1954         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1955         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1956         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1957         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1958         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1959         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1960         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1961         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1962     }
1963
1964     sampler_8x8_state->dw136.default_sharpness_level = 0;
1965     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1966     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1967     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1968     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1969
1970     /* sampler 8x8 */
1971     dri_bo_map(pp_context->sampler_state_table.bo, True);
1972     assert(pp_context->sampler_state_table.bo->virtual);
1973     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1974     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1975
1976     /* sample_8x8 Y index 1 */
1977     index = 1;
1978     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1979     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1980     sampler_8x8[index].dw0.ief_bypass = 1;
1981     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1982     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1983     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1984     sampler_8x8[index].dw2.global_noise_estimation = 22;
1985     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1986     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1987     sampler_8x8[index].dw3.strong_edge_weight = 7;
1988     sampler_8x8[index].dw3.regular_weight = 2;
1989     sampler_8x8[index].dw3.non_edge_weight = 0;
1990     sampler_8x8[index].dw3.gain_factor = 40;
1991     sampler_8x8[index].dw4.steepness_boost = 0;
1992     sampler_8x8[index].dw4.steepness_threshold = 0;
1993     sampler_8x8[index].dw4.mr_boost = 0;
1994     sampler_8x8[index].dw4.mr_threshold = 5;
1995     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1996     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1997     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1998     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1999     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2000     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2001     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2002     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2003     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2004     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2005     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2006     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2007     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2008     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2009     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2010     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2011     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2012     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2013     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2014     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2015     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2016     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2017     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2018     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2019     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2020     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2021     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2022     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2023     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2024     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2025     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2026     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2027     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2028     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2029     sampler_8x8[index].dw13.limiter_boost = 0;
2030     sampler_8x8[index].dw13.minimum_limiter = 10;
2031     sampler_8x8[index].dw13.maximum_limiter = 11;
2032     sampler_8x8[index].dw14.clip_limiter = 130;
2033     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2034                       I915_GEM_DOMAIN_RENDER,
2035                       0,
2036                       0,
2037                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2038                       pp_context->sampler_state_table.bo_8x8);
2039
2040     /* sample_8x8 UV index 2 */
2041     index = 2;
2042     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2043     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2044     sampler_8x8[index].dw0.ief_bypass = 1;
2045     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2046     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2047     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2048     sampler_8x8[index].dw2.global_noise_estimation = 22;
2049     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2050     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2051     sampler_8x8[index].dw3.strong_edge_weight = 7;
2052     sampler_8x8[index].dw3.regular_weight = 2;
2053     sampler_8x8[index].dw3.non_edge_weight = 0;
2054     sampler_8x8[index].dw3.gain_factor = 40;
2055     sampler_8x8[index].dw4.steepness_boost = 0;
2056     sampler_8x8[index].dw4.steepness_threshold = 0;
2057     sampler_8x8[index].dw4.mr_boost = 0;
2058     sampler_8x8[index].dw4.mr_threshold = 5;
2059     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2060     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2061     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2062     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2063     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2064     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2065     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2066     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2067     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2068     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2069     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2070     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2071     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2072     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2073     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2074     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2075     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2076     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2077     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2078     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2079     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2080     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2081     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2082     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2083     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2084     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2085     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2086     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2087     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2088     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2089     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2090     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2091     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2092     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2093     sampler_8x8[index].dw13.limiter_boost = 0;
2094     sampler_8x8[index].dw13.minimum_limiter = 10;
2095     sampler_8x8[index].dw13.maximum_limiter = 11;
2096     sampler_8x8[index].dw14.clip_limiter = 130;
2097     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2098                       I915_GEM_DOMAIN_RENDER,
2099                       0,
2100                       0,
2101                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2102                       pp_context->sampler_state_table.bo_8x8);
2103
2104     dri_bo_unmap(pp_context->sampler_state_table.bo);
2105
2106     /* private function & data */
2107     pp_context->pp_x_steps = pp_avs_x_steps;
2108     pp_context->pp_y_steps = pp_avs_y_steps;
2109     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2110
2111     pp_avs_context->dest_x = dst_rect->x;
2112     pp_avs_context->dest_y = dst_rect->y;
2113     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2114     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2115     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2116     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2117     pp_avs_context->src_w = src_rect->width;
2118     pp_avs_context->src_h = src_rect->height;
2119
2120     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2121     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2122
2123     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2124     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2125     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2126     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2127     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2128     pp_inline_parameter->grf6.video_step_delta = 0.0;
2129
2130     dst_surface->flags = src_surface->flags;
2131
2132     return VA_STATUS_SUCCESS;
2133 }
2134
2135 static VAStatus
2136 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2137                             const struct i965_surface *src_surface,
2138                             const VARectangle *src_rect,
2139                             struct i965_surface *dst_surface,
2140                             const VARectangle *dst_rect,
2141                             void *filter_param)
2142 {
2143     return pp_nv12_avs_initialize(ctx, pp_context,
2144                                   src_surface,
2145                                   src_rect,
2146                                   dst_surface,
2147                                   dst_rect,
2148                                   filter_param,
2149                                   1);
2150 }
2151
2152 static VAStatus
2153 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2154                              const struct i965_surface *src_surface,
2155                              const VARectangle *src_rect,
2156                              struct i965_surface *dst_surface,
2157                              const VARectangle *dst_rect,
2158                              void *filter_param)
2159 {
2160     return pp_nv12_avs_initialize(ctx, pp_context,
2161                                   src_surface,
2162                                   src_rect,
2163                                   dst_surface,
2164                                   dst_rect,
2165                                   filter_param,
2166                                   0);
2167 }
2168
2169 static int
2170 gen7_pp_avs_x_steps(void *private_context)
2171 {
2172     struct pp_avs_context *pp_avs_context = private_context;
2173
2174     return pp_avs_context->dest_w / 16;
2175 }
2176
2177 static int
2178 gen7_pp_avs_y_steps(void *private_context)
2179 {
2180     struct pp_avs_context *pp_avs_context = private_context;
2181
2182     return pp_avs_context->dest_h / 16;
2183 }
2184
2185 static int
2186 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2187 {
2188     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2189     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2190
2191     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2192     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2193     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2194     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2195
2196     return 0;
2197 }
2198
2199 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2200                                               struct i965_post_processing_context *pp_context,
2201                                               const struct i965_surface *surface)
2202 {
2203     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2204     int fourcc = pp_get_surface_fourcc(ctx, surface);
2205
2206     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2207         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2208         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2209         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2210     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2211         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2212         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2213         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2214     }
2215 }
2216
2217 static VAStatus
2218 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2219                            const struct i965_surface *src_surface,
2220                            const VARectangle *src_rect,
2221                            struct i965_surface *dst_surface,
2222                            const VARectangle *dst_rect,
2223                            void *filter_param)
2224 {
2225     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2226     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2227     struct gen7_sampler_8x8 *sampler_8x8;
2228     struct i965_sampler_8x8_state *sampler_8x8_state;
2229     int index, i;
2230     int width[3], height[3], pitch[3], offset[3];
2231
2232     /* source surface */
2233     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2234                                          width, height, pitch, offset);
2235
2236     /* destination surface */
2237     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2238                                          width, height, pitch, offset);
2239
2240     /* sampler 8x8 state */
2241     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2242     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2243     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2244     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2245     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2246
2247     for (i = 0; i < 17; i++) {
2248         /* for Y channel, currently ignore */
2249         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2250         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2251         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2252         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2253         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2254         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2255         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2256         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2257         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2258         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2259         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2260         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2261         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2262         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2263         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2264         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2265         /* for U/V channel, 0.25 */
2266         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2267         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2268         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2269         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2270         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2271         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2272         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2273         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2274         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2275         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2276         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2277         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2278         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2279         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2280         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2281         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2282     }
2283
2284     sampler_8x8_state->dw136.default_sharpness_level = 0;
2285     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2286     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2287     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2288     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2289
2290     /* sampler 8x8 */
2291     dri_bo_map(pp_context->sampler_state_table.bo, True);
2292     assert(pp_context->sampler_state_table.bo->virtual);
2293     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2294     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2295
2296     /* sample_8x8 Y index 4 */
2297     index = 4;
2298     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2299     sampler_8x8[index].dw0.global_noise_estimation = 255;
2300     sampler_8x8[index].dw0.ief_bypass = 1;
2301
2302     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2303
2304     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2305     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2306     sampler_8x8[index].dw2.r5x_coefficient = 9;
2307     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2308     sampler_8x8[index].dw2.r5c_coefficient = 3;
2309
2310     sampler_8x8[index].dw3.r3x_coefficient = 27;
2311     sampler_8x8[index].dw3.r3c_coefficient = 5;
2312     sampler_8x8[index].dw3.gain_factor = 40;
2313     sampler_8x8[index].dw3.non_edge_weight = 1;
2314     sampler_8x8[index].dw3.regular_weight = 2;
2315     sampler_8x8[index].dw3.strong_edge_weight = 7;
2316     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2317
2318     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2319                       I915_GEM_DOMAIN_RENDER,
2320                       0,
2321                       0,
2322                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2323                       pp_context->sampler_state_table.bo_8x8);
2324
2325     /* sample_8x8 UV index 8 */
2326     index = 8;
2327     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2328     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2329     sampler_8x8[index].dw0.global_noise_estimation = 255;
2330     sampler_8x8[index].dw0.ief_bypass = 1;
2331     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2332     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2333     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2334     sampler_8x8[index].dw2.r5x_coefficient = 9;
2335     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2336     sampler_8x8[index].dw2.r5c_coefficient = 3;
2337     sampler_8x8[index].dw3.r3x_coefficient = 27;
2338     sampler_8x8[index].dw3.r3c_coefficient = 5;
2339     sampler_8x8[index].dw3.gain_factor = 40;
2340     sampler_8x8[index].dw3.non_edge_weight = 1;
2341     sampler_8x8[index].dw3.regular_weight = 2;
2342     sampler_8x8[index].dw3.strong_edge_weight = 7;
2343     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2344
2345     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2346                       I915_GEM_DOMAIN_RENDER,
2347                       0,
2348                       0,
2349                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2350                       pp_context->sampler_state_table.bo_8x8);
2351
2352     /* sampler_8x8 V, index 12 */
2353     index = 12;
2354     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2355     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2356     sampler_8x8[index].dw0.global_noise_estimation = 255;
2357     sampler_8x8[index].dw0.ief_bypass = 1;
2358     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2359     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2360     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2361     sampler_8x8[index].dw2.r5x_coefficient = 9;
2362     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2363     sampler_8x8[index].dw2.r5c_coefficient = 3;
2364     sampler_8x8[index].dw3.r3x_coefficient = 27;
2365     sampler_8x8[index].dw3.r3c_coefficient = 5;
2366     sampler_8x8[index].dw3.gain_factor = 40;
2367     sampler_8x8[index].dw3.non_edge_weight = 1;
2368     sampler_8x8[index].dw3.regular_weight = 2;
2369     sampler_8x8[index].dw3.strong_edge_weight = 7;
2370     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2371
2372     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2373                       I915_GEM_DOMAIN_RENDER,
2374                       0,
2375                       0,
2376                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2377                       pp_context->sampler_state_table.bo_8x8);
2378
2379     dri_bo_unmap(pp_context->sampler_state_table.bo);
2380
2381     /* private function & data */
2382     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2383     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2384     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2385
2386     pp_avs_context->dest_x = dst_rect->x;
2387     pp_avs_context->dest_y = dst_rect->y;
2388     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2389     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2390     pp_avs_context->src_w = src_rect->width;
2391     pp_avs_context->src_h = src_rect->height;
2392
2393     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2394     dw = MAX(dw, pp_avs_context->dest_w);
2395
2396     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2397     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2398     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2399     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2400     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2401
2402     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2403
2404     dst_surface->flags = src_surface->flags;
2405
2406     return VA_STATUS_SUCCESS;
2407 }
2408
2409 static int
2410 pp_dndi_x_steps(void *private_context)
2411 {
2412     return 1;
2413 }
2414
2415 static int
2416 pp_dndi_y_steps(void *private_context)
2417 {
2418     struct pp_dndi_context *pp_dndi_context = private_context;
2419
2420     return pp_dndi_context->dest_h / 4;
2421 }
2422
2423 static int
2424 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2425 {
2426     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2427
2428     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2429     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2430
2431     return 0;
2432 }
2433
2434 static VAStatus
2435 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2436                         const struct i965_surface *src_surface,
2437                         const VARectangle *src_rect,
2438                         struct i965_surface *dst_surface,
2439                         const VARectangle *dst_rect,
2440                         void *filter_param)
2441 {
2442     struct i965_driver_data *i965 = i965_driver_data(ctx);
2443     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2444     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2445     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2446     struct object_surface *obj_surface;
2447     struct i965_sampler_dndi *sampler_dndi;
2448     int index;
2449     int w, h;
2450     int orig_w, orig_h;
2451     int dndi_top_first = 1;
2452
2453     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2454         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2455
2456     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2457         dndi_top_first = 1;
2458     else
2459         dndi_top_first = 0;
2460
2461     /* surface */
2462     obj_surface = SURFACE(src_surface->id);
2463     orig_w = obj_surface->orig_width;
2464     orig_h = obj_surface->orig_height;
2465     w = obj_surface->width;
2466     h = obj_surface->height;
2467
2468     if (pp_context->stmm.bo == NULL) {
2469         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2470                                            "STMM surface",
2471                                            w * h,
2472                                            4096);
2473         assert(pp_context->stmm.bo);
2474     }
2475
2476     /* source UV surface index 2 */
2477     i965_pp_set_surface_state(ctx, pp_context,
2478                               obj_surface->bo, w * h,
2479                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2480                               2, 0);
2481
2482     /* source YUV surface index 4 */
2483     i965_pp_set_surface2_state(ctx, pp_context,
2484                                obj_surface->bo, 0,
2485                                orig_w, orig_h, w,
2486                                0, h,
2487                                SURFACE_FORMAT_PLANAR_420_8, 1,
2488                                4);
2489
2490     /* source STMM surface index 20 */
2491     i965_pp_set_surface_state(ctx, pp_context,
2492                               pp_context->stmm.bo, 0,
2493                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2494                               20, 1);
2495
2496     /* destination surface */
2497     obj_surface = SURFACE(dst_surface->id);
2498     orig_w = obj_surface->orig_width;
2499     orig_h = obj_surface->orig_height;
2500     w = obj_surface->width;
2501     h = obj_surface->height;
2502
2503     /* destination Y surface index 7 */
2504     i965_pp_set_surface_state(ctx, pp_context,
2505                               obj_surface->bo, 0,
2506                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2507                               7, 1);
2508
2509     /* destination UV surface index 8 */
2510     i965_pp_set_surface_state(ctx, pp_context,
2511                               obj_surface->bo, w * h,
2512                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2513                               8, 1);
2514     /* sampler dndi */
2515     dri_bo_map(pp_context->sampler_state_table.bo, True);
2516     assert(pp_context->sampler_state_table.bo->virtual);
2517     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2518     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2519
2520     /* sample dndi index 1 */
2521     index = 0;
2522     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2523     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2524     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2525     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2526
2527     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2528     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2529     sampler_dndi[index].dw1.stmm_c2 = 1;
2530     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2531     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2532
2533     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2534     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2535     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2536     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2537
2538     sampler_dndi[index].dw3.maximum_stmm = 128;
2539     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2540     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2541     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2542     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2543
2544     sampler_dndi[index].dw4.sdi_delta = 8;
2545     sampler_dndi[index].dw4.sdi_threshold = 128;
2546     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2547     sampler_dndi[index].dw4.stmm_shift_up = 0;
2548     sampler_dndi[index].dw4.stmm_shift_down = 0;
2549     sampler_dndi[index].dw4.minimum_stmm = 0;
2550
2551     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2552     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2553     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2554     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2555
2556     sampler_dndi[index].dw6.dn_enable = 1;
2557     sampler_dndi[index].dw6.di_enable = 1;
2558     sampler_dndi[index].dw6.di_partial = 0;
2559     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2560     sampler_dndi[index].dw6.dndi_stream_id = 0;
2561     sampler_dndi[index].dw6.dndi_first_frame = 1;
2562     sampler_dndi[index].dw6.progressive_dn = 0;
2563     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2564     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2565     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2566
2567     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2568     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2569     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2570     sampler_dndi[index].dw7.column_width_minus1 = 0;
2571
2572     dri_bo_unmap(pp_context->sampler_state_table.bo);
2573
2574     /* private function & data */
2575     pp_context->pp_x_steps = pp_dndi_x_steps;
2576     pp_context->pp_y_steps = pp_dndi_y_steps;
2577     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2578
2579     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2580     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2581     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2582     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2583
2584     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2585     pp_inline_parameter->grf5.number_blocks = w / 16;
2586     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2587     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2588
2589     pp_dndi_context->dest_w = w;
2590     pp_dndi_context->dest_h = h;
2591
2592     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2593
2594     return VA_STATUS_SUCCESS;
2595 }
2596
2597 static int
2598 pp_dn_x_steps(void *private_context)
2599 {
2600     return 1;
2601 }
2602
2603 static int
2604 pp_dn_y_steps(void *private_context)
2605 {
2606     struct pp_dn_context *pp_dn_context = private_context;
2607
2608     return pp_dn_context->dest_h / 8;
2609 }
2610
2611 static int
2612 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2613 {
2614     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2615
2616     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2617     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2618
2619     return 0;
2620 }
2621
2622 static VAStatus
2623 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2624                       const struct i965_surface *src_surface,
2625                       const VARectangle *src_rect,
2626                       struct i965_surface *dst_surface,
2627                       const VARectangle *dst_rect,
2628                       void *filter_param)
2629 {
2630     struct i965_driver_data *i965 = i965_driver_data(ctx);
2631     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2632     struct object_surface *obj_surface;
2633     struct i965_sampler_dndi *sampler_dndi;
2634     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2635     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2636     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2637     int index;
2638     int w, h;
2639     int orig_w, orig_h;
2640     int dn_strength = 15;
2641     int dndi_top_first = 1;
2642     int dn_progressive = 0;
2643
2644     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2645         dndi_top_first = 1;
2646         dn_progressive = 1;
2647     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2648         dndi_top_first = 1;
2649         dn_progressive = 0;
2650     } else {
2651         dndi_top_first = 0;
2652         dn_progressive = 0;
2653     }
2654
2655     if (dn_filter_param) {
2656         float value = dn_filter_param->value;
2657
2658         if (value > 1.0)
2659             value = 1.0;
2660
2661         if (value < 0.0)
2662             value = 0.0;
2663
2664         dn_strength = (int)(value * 31.0F);
2665     }
2666
2667     /* surface */
2668     obj_surface = SURFACE(src_surface->id);
2669     orig_w = obj_surface->orig_width;
2670     orig_h = obj_surface->orig_height;
2671     w = obj_surface->width;
2672     h = obj_surface->height;
2673
2674     if (pp_context->stmm.bo == NULL) {
2675         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2676                                            "STMM surface",
2677                                            w * h,
2678                                            4096);
2679         assert(pp_context->stmm.bo);
2680     }
2681
2682     /* source UV surface index 2 */
2683     i965_pp_set_surface_state(ctx, pp_context,
2684                               obj_surface->bo, w * h,
2685                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2686                               2, 0);
2687
2688     /* source YUV surface index 4 */
2689     i965_pp_set_surface2_state(ctx, pp_context,
2690                                obj_surface->bo, 0,
2691                                orig_w, orig_h, w,
2692                                0, h,
2693                                SURFACE_FORMAT_PLANAR_420_8, 1,
2694                                4);
2695
2696     /* source STMM surface index 20 */
2697     i965_pp_set_surface_state(ctx, pp_context,
2698                               pp_context->stmm.bo, 0,
2699                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2700                               20, 1);
2701
2702     /* destination surface */
2703     obj_surface = SURFACE(dst_surface->id);
2704     orig_w = obj_surface->orig_width;
2705     orig_h = obj_surface->orig_height;
2706     w = obj_surface->width;
2707     h = obj_surface->height;
2708
2709     /* destination Y surface index 7 */
2710     i965_pp_set_surface_state(ctx, pp_context,
2711                               obj_surface->bo, 0,
2712                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2713                               7, 1);
2714
2715     /* destination UV surface index 8 */
2716     i965_pp_set_surface_state(ctx, pp_context,
2717                               obj_surface->bo, w * h,
2718                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2719                               8, 1);
2720     /* sampler dn */
2721     dri_bo_map(pp_context->sampler_state_table.bo, True);
2722     assert(pp_context->sampler_state_table.bo->virtual);
2723     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2724     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2725
2726     /* sample dndi index 1 */
2727     index = 0;
2728     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2729     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2730     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2731     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2732
2733     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2734     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2735     sampler_dndi[index].dw1.stmm_c2 = 0;
2736     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2737     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2738
2739     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2740     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2741     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2742     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2743
2744     sampler_dndi[index].dw3.maximum_stmm = 128;
2745     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2746     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2747     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2748     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2749
2750     sampler_dndi[index].dw4.sdi_delta = 8;
2751     sampler_dndi[index].dw4.sdi_threshold = 128;
2752     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2753     sampler_dndi[index].dw4.stmm_shift_up = 0;
2754     sampler_dndi[index].dw4.stmm_shift_down = 0;
2755     sampler_dndi[index].dw4.minimum_stmm = 0;
2756
2757     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2758     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2759     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2760     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2761
2762     sampler_dndi[index].dw6.dn_enable = 1;
2763     sampler_dndi[index].dw6.di_enable = 0;
2764     sampler_dndi[index].dw6.di_partial = 0;
2765     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2766     sampler_dndi[index].dw6.dndi_stream_id = 1;
2767     sampler_dndi[index].dw6.dndi_first_frame = 1;
2768     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2769     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2770     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2771     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2772
2773     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2774     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2775     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2776     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2777
2778     dri_bo_unmap(pp_context->sampler_state_table.bo);
2779
2780     /* private function & data */
2781     pp_context->pp_x_steps = pp_dn_x_steps;
2782     pp_context->pp_y_steps = pp_dn_y_steps;
2783     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2784
2785     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2786     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2787     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2788     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2789
2790     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2791     pp_inline_parameter->grf5.number_blocks = w / 16;
2792     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2793     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2794
2795     pp_dn_context->dest_w = w;
2796     pp_dn_context->dest_h = h;
2797
2798     dst_surface->flags = src_surface->flags;
2799
2800     return VA_STATUS_SUCCESS;
2801 }
2802
2803 static int
2804 gen7_pp_dndi_x_steps(void *private_context)
2805 {
2806     struct pp_dndi_context *pp_dndi_context = private_context;
2807
2808     return pp_dndi_context->dest_w / 16;
2809 }
2810
2811 static int
2812 gen7_pp_dndi_y_steps(void *private_context)
2813 {
2814     struct pp_dndi_context *pp_dndi_context = private_context;
2815
2816     return pp_dndi_context->dest_h / 4;
2817 }
2818
2819 static int
2820 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2821 {
2822     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2823
2824     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2825     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2826
2827     return 0;
2828 }
2829
2830 static VAStatus
2831 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2832                              const struct i965_surface *src_surface,
2833                              const VARectangle *src_rect,
2834                              struct i965_surface *dst_surface,
2835                              const VARectangle *dst_rect,
2836                              void *filter_param)
2837 {
2838     struct i965_driver_data *i965 = i965_driver_data(ctx);
2839     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2840     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2841     struct object_surface *obj_surface;
2842     struct gen7_sampler_dndi *sampler_dndi;
2843     int index;
2844     int w, h;
2845     int orig_w, orig_h;
2846     int dndi_top_first = 1;
2847
2848     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2849         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2850
2851     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2852         dndi_top_first = 1;
2853     else
2854         dndi_top_first = 0;
2855
2856     /* surface */
2857     obj_surface = SURFACE(src_surface->id);
2858     orig_w = obj_surface->orig_width;
2859     orig_h = obj_surface->orig_height;
2860     w = obj_surface->width;
2861     h = obj_surface->height;
2862
2863     if (pp_context->stmm.bo == NULL) {
2864         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2865                                            "STMM surface",
2866                                            w * h,
2867                                            4096);
2868         assert(pp_context->stmm.bo);
2869     }
2870
2871     /* source UV surface index 1 */
2872     gen7_pp_set_surface_state(ctx, pp_context,
2873                               obj_surface->bo, w * h,
2874                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2875                               1, 0);
2876
2877     /* source YUV surface index 3 */
2878     gen7_pp_set_surface2_state(ctx, pp_context,
2879                                obj_surface->bo, 0,
2880                                orig_w, orig_h, w,
2881                                0, h,
2882                                SURFACE_FORMAT_PLANAR_420_8, 1,
2883                                3);
2884
2885     /* source (temporal reference) YUV surface index 4 */
2886     gen7_pp_set_surface2_state(ctx, pp_context,
2887                                obj_surface->bo, 0,
2888                                orig_w, orig_h, w,
2889                                0, h,
2890                                SURFACE_FORMAT_PLANAR_420_8, 1,
2891                                4);
2892
2893     /* STMM / History Statistics input surface, index 5 */
2894     gen7_pp_set_surface_state(ctx, pp_context,
2895                               pp_context->stmm.bo, 0,
2896                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2897                               5, 1);
2898
2899     /* destination surface */
2900     obj_surface = SURFACE(dst_surface->id);
2901     orig_w = obj_surface->orig_width;
2902     orig_h = obj_surface->orig_height;
2903     w = obj_surface->width;
2904     h = obj_surface->height;
2905
2906     /* destination(Previous frame) Y surface index 27 */
2907     gen7_pp_set_surface_state(ctx, pp_context,
2908                               obj_surface->bo, 0,
2909                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2910                               27, 1);
2911
2912     /* destination(Previous frame) UV surface index 28 */
2913     gen7_pp_set_surface_state(ctx, pp_context,
2914                               obj_surface->bo, w * h,
2915                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2916                               28, 1);
2917
2918     /* destination(Current frame) Y surface index 30 */
2919     gen7_pp_set_surface_state(ctx, pp_context,
2920                               obj_surface->bo, 0,
2921                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2922                               30, 1);
2923
2924     /* destination(Current frame) UV surface index 31 */
2925     gen7_pp_set_surface_state(ctx, pp_context,
2926                               obj_surface->bo, w * h,
2927                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2928                               31, 1);
2929
2930     /* STMM output surface, index 33 */
2931     gen7_pp_set_surface_state(ctx, pp_context,
2932                               pp_context->stmm.bo, 0,
2933                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2934                               33, 1);
2935
2936
2937     /* sampler dndi */
2938     dri_bo_map(pp_context->sampler_state_table.bo, True);
2939     assert(pp_context->sampler_state_table.bo->virtual);
2940     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2941     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2942
2943     /* sample dndi index 0 */
2944     index = 0;
2945     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2946     sampler_dndi[index].dw0.dnmh_delt = 8;
2947     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2948     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2949     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2950     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2951
2952     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2953     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2954     sampler_dndi[index].dw1.stmm_c2 = 0;
2955     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2956     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2957
2958     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2959     sampler_dndi[index].dw2.bne_edge_th = 1;
2960     sampler_dndi[index].dw2.smooth_mv_th = 0;
2961     sampler_dndi[index].dw2.sad_tight_th = 5;
2962     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2963     sampler_dndi[index].dw2.good_neighbor_th = 4;
2964
2965     sampler_dndi[index].dw3.maximum_stmm = 128;
2966     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2967     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2968     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2969     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2970
2971     sampler_dndi[index].dw4.sdi_delta = 8;
2972     sampler_dndi[index].dw4.sdi_threshold = 128;
2973     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2974     sampler_dndi[index].dw4.stmm_shift_up = 0;
2975     sampler_dndi[index].dw4.stmm_shift_down = 0;
2976     sampler_dndi[index].dw4.minimum_stmm = 0;
2977
2978     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2979     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2980     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2981     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2982
2983     sampler_dndi[index].dw6.dn_enable = 0;
2984     sampler_dndi[index].dw6.di_enable = 1;
2985     sampler_dndi[index].dw6.di_partial = 0;
2986     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2987     sampler_dndi[index].dw6.dndi_stream_id = 1;
2988     sampler_dndi[index].dw6.dndi_first_frame = 1;
2989     sampler_dndi[index].dw6.progressive_dn = 0;
2990     sampler_dndi[index].dw6.mcdi_enable = 0;
2991     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2992     sampler_dndi[index].dw6.cat_th1 = 0;
2993     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2994     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2995
2996     sampler_dndi[index].dw7.sad_tha = 5;
2997     sampler_dndi[index].dw7.sad_thb = 10;
2998     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2999     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3000     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3001     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3002     sampler_dndi[index].dw7.neighborpixel_th = 10;
3003     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3004
3005     dri_bo_unmap(pp_context->sampler_state_table.bo);
3006
3007     /* private function & data */
3008     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3009     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3010     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3011
3012     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3013     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3014     pp_static_parameter->grf1.di_top_field_first = 0;
3015     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3016
3017     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3018     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3019     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3020
3021     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3022     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3023
3024     pp_dndi_context->dest_w = w;
3025     pp_dndi_context->dest_h = h;
3026
3027     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3028
3029     return VA_STATUS_SUCCESS;
3030 }
3031
3032 static int
3033 gen7_pp_dn_x_steps(void *private_context)
3034 {
3035     return 1;
3036 }
3037
3038 static int
3039 gen7_pp_dn_y_steps(void *private_context)
3040 {
3041     struct pp_dn_context *pp_dn_context = private_context;
3042
3043     return pp_dn_context->dest_h / 4;
3044 }
3045
3046 static int
3047 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3048 {
3049     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3050
3051     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3052     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3053
3054     return 0;
3055 }
3056
3057 static VAStatus
3058 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3059                            const struct i965_surface *src_surface,
3060                            const VARectangle *src_rect,
3061                            struct i965_surface *dst_surface,
3062                            const VARectangle *dst_rect,
3063                            void *filter_param)
3064 {
3065     struct i965_driver_data *i965 = i965_driver_data(ctx);
3066     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3067     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3068     struct object_surface *obj_surface;
3069     struct gen7_sampler_dndi *sampler_dn;
3070     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3071     int index;
3072     int w, h;
3073     int orig_w, orig_h;
3074     int dn_strength = 15;
3075     int dndi_top_first = 1;
3076     int dn_progressive = 0;
3077
3078     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3079         dndi_top_first = 1;
3080         dn_progressive = 1;
3081     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3082         dndi_top_first = 1;
3083         dn_progressive = 0;
3084     } else {
3085         dndi_top_first = 0;
3086         dn_progressive = 0;
3087     }
3088
3089     if (dn_filter_param) {
3090         float value = dn_filter_param->value;
3091
3092         if (value > 1.0)
3093             value = 1.0;
3094
3095         if (value < 0.0)
3096             value = 0.0;
3097
3098         dn_strength = (int)(value * 31.0F);
3099     }
3100
3101     /* surface */
3102     obj_surface = SURFACE(src_surface->id);
3103     orig_w = obj_surface->orig_width;
3104     orig_h = obj_surface->orig_height;
3105     w = obj_surface->width;
3106     h = obj_surface->height;
3107
3108     if (pp_context->stmm.bo == NULL) {
3109         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3110                                            "STMM surface",
3111                                            w * h,
3112                                            4096);
3113         assert(pp_context->stmm.bo);
3114     }
3115
3116     /* source UV surface index 1 */
3117     gen7_pp_set_surface_state(ctx, pp_context,
3118                               obj_surface->bo, w * h,
3119                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3120                               1, 0);
3121
3122     /* source YUV surface index 3 */
3123     gen7_pp_set_surface2_state(ctx, pp_context,
3124                                obj_surface->bo, 0,
3125                                orig_w, orig_h, w,
3126                                0, h,
3127                                SURFACE_FORMAT_PLANAR_420_8, 1,
3128                                3);
3129
3130     /* source STMM surface index 5 */
3131     gen7_pp_set_surface_state(ctx, pp_context,
3132                               pp_context->stmm.bo, 0,
3133                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3134                               5, 1);
3135
3136     /* destination surface */
3137     obj_surface = SURFACE(dst_surface->id);
3138     orig_w = obj_surface->orig_width;
3139     orig_h = obj_surface->orig_height;
3140     w = obj_surface->width;
3141     h = obj_surface->height;
3142
3143     /* destination Y surface index 7 */
3144     gen7_pp_set_surface_state(ctx, pp_context,
3145                               obj_surface->bo, 0,
3146                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3147                               7, 1);
3148
3149     /* destination UV surface index 8 */
3150     gen7_pp_set_surface_state(ctx, pp_context,
3151                               obj_surface->bo, w * h,
3152                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3153                               8, 1);
3154     /* sampler dn */
3155     dri_bo_map(pp_context->sampler_state_table.bo, True);
3156     assert(pp_context->sampler_state_table.bo->virtual);
3157     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3158     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3159
3160     /* sample dn index 1 */
3161     index = 0;
3162     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3163     sampler_dn[index].dw0.dnmh_delt = 8;
3164     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3165     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3166     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3167     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3168
3169     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3170     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3171     sampler_dn[index].dw1.stmm_c2 = 0;
3172     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3173     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3174
3175     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3176     sampler_dn[index].dw2.bne_edge_th = 1;
3177     sampler_dn[index].dw2.smooth_mv_th = 0;
3178     sampler_dn[index].dw2.sad_tight_th = 5;
3179     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3180     sampler_dn[index].dw2.good_neighbor_th = 4;
3181
3182     sampler_dn[index].dw3.maximum_stmm = 128;
3183     sampler_dn[index].dw3.multipler_for_vecm = 2;
3184     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3185     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3186     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3187
3188     sampler_dn[index].dw4.sdi_delta = 8;
3189     sampler_dn[index].dw4.sdi_threshold = 128;
3190     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3191     sampler_dn[index].dw4.stmm_shift_up = 0;
3192     sampler_dn[index].dw4.stmm_shift_down = 0;
3193     sampler_dn[index].dw4.minimum_stmm = 0;
3194
3195     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3196     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3197     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3198     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3199
3200     sampler_dn[index].dw6.dn_enable = 1;
3201     sampler_dn[index].dw6.di_enable = 0;
3202     sampler_dn[index].dw6.di_partial = 0;
3203     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3204     sampler_dn[index].dw6.dndi_stream_id = 1;
3205     sampler_dn[index].dw6.dndi_first_frame = 1;
3206     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3207     sampler_dn[index].dw6.mcdi_enable = 0;
3208     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3209     sampler_dn[index].dw6.cat_th1 = 0;
3210     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3211     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3212
3213     sampler_dn[index].dw7.sad_tha = 5;
3214     sampler_dn[index].dw7.sad_thb = 10;
3215     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3216     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3217     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3218     sampler_dn[index].dw7.vdi_walker_enable = 0;
3219     sampler_dn[index].dw7.neighborpixel_th = 10;
3220     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3221
3222     dri_bo_unmap(pp_context->sampler_state_table.bo);
3223
3224     /* private function & data */
3225     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3226     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3227     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3228
3229     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3230     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3231     pp_static_parameter->grf1.di_top_field_first = 0;
3232     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3233
3234     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3235     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3236     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3237
3238     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3239     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3240
3241     pp_dn_context->dest_w = w;
3242     pp_dn_context->dest_h = h;
3243
3244     dst_surface->flags = src_surface->flags;
3245
3246     return VA_STATUS_SUCCESS;
3247 }
3248
3249 static VAStatus
3250 ironlake_pp_initialize(
3251     VADriverContextP   ctx,
3252     struct i965_post_processing_context *pp_context,
3253     const struct i965_surface *src_surface,
3254     const VARectangle *src_rect,
3255     struct i965_surface *dst_surface,
3256     const VARectangle *dst_rect,
3257     int                pp_index,
3258     void *filter_param
3259 )
3260 {
3261     VAStatus va_status;
3262     struct i965_driver_data *i965 = i965_driver_data(ctx);
3263     struct pp_module *pp_module;
3264     dri_bo *bo;
3265     int static_param_size, inline_param_size;
3266
3267     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3268     bo = dri_bo_alloc(i965->intel.bufmgr,
3269                       "surface state & binding table",
3270                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3271                       4096);
3272     assert(bo);
3273     pp_context->surface_state_binding_table.bo = bo;
3274
3275     dri_bo_unreference(pp_context->curbe.bo);
3276     bo = dri_bo_alloc(i965->intel.bufmgr,
3277                       "constant buffer",
3278                       4096,
3279                       4096);
3280     assert(bo);
3281     pp_context->curbe.bo = bo;
3282
3283     dri_bo_unreference(pp_context->idrt.bo);
3284     bo = dri_bo_alloc(i965->intel.bufmgr,
3285                       "interface discriptor",
3286                       sizeof(struct i965_interface_descriptor),
3287                       4096);
3288     assert(bo);
3289     pp_context->idrt.bo = bo;
3290     pp_context->idrt.num_interface_descriptors = 0;
3291
3292     dri_bo_unreference(pp_context->sampler_state_table.bo);
3293     bo = dri_bo_alloc(i965->intel.bufmgr,
3294                       "sampler state table",
3295                       4096,
3296                       4096);
3297     assert(bo);
3298     dri_bo_map(bo, True);
3299     memset(bo->virtual, 0, bo->size);
3300     dri_bo_unmap(bo);
3301     pp_context->sampler_state_table.bo = bo;
3302
3303     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3304     bo = dri_bo_alloc(i965->intel.bufmgr,
3305                       "sampler 8x8 state ",
3306                       4096,
3307                       4096);
3308     assert(bo);
3309     pp_context->sampler_state_table.bo_8x8 = bo;
3310
3311     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3312     bo = dri_bo_alloc(i965->intel.bufmgr,
3313                       "sampler 8x8 state ",
3314                       4096,
3315                       4096);
3316     assert(bo);
3317     pp_context->sampler_state_table.bo_8x8_uv = bo;
3318
3319     dri_bo_unreference(pp_context->vfe_state.bo);
3320     bo = dri_bo_alloc(i965->intel.bufmgr,
3321                       "vfe state",
3322                       sizeof(struct i965_vfe_state),
3323                       4096);
3324     assert(bo);
3325     pp_context->vfe_state.bo = bo;
3326
3327     static_param_size = sizeof(struct pp_static_parameter);
3328     inline_param_size = sizeof(struct pp_inline_parameter);
3329
3330     memset(pp_context->pp_static_parameter, 0, static_param_size);
3331     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3332
3333     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3334     pp_context->current_pp = pp_index;
3335     pp_module = &pp_context->pp_modules[pp_index];
3336
3337     if (pp_module->initialize)
3338         va_status = pp_module->initialize(ctx, pp_context,
3339                                           src_surface,
3340                                           src_rect,
3341                                           dst_surface,
3342                                           dst_rect,
3343                                           filter_param);
3344     else
3345         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3346
3347     return va_status;
3348 }
3349
3350 static VAStatus
3351 ironlake_post_processing(
3352     VADriverContextP   ctx,
3353     struct i965_post_processing_context *pp_context,
3354     const struct i965_surface *src_surface,
3355     const VARectangle *src_rect,
3356     struct i965_surface *dst_surface,
3357     const VARectangle *dst_rect,
3358     int                pp_index,
3359     void *filter_param
3360 )
3361 {
3362     VAStatus va_status;
3363
3364     va_status = ironlake_pp_initialize(ctx, pp_context,
3365                                        src_surface,
3366                                        src_rect,
3367                                        dst_surface,
3368                                        dst_rect,
3369                                        pp_index,
3370                                        filter_param);
3371
3372     if (va_status == VA_STATUS_SUCCESS) {
3373         ironlake_pp_states_setup(ctx, pp_context);
3374         ironlake_pp_pipeline_setup(ctx, pp_context);
3375     }
3376
3377     return va_status;
3378 }
3379
3380 static VAStatus
3381 gen6_pp_initialize(
3382     VADriverContextP   ctx,
3383     struct i965_post_processing_context *pp_context,
3384     const struct i965_surface *src_surface,
3385     const VARectangle *src_rect,
3386     struct i965_surface *dst_surface,
3387     const VARectangle *dst_rect,
3388     int                pp_index,
3389     void *filter_param
3390 )
3391 {
3392     VAStatus va_status;
3393     struct i965_driver_data *i965 = i965_driver_data(ctx);
3394     struct pp_module *pp_module;
3395     dri_bo *bo;
3396     int static_param_size, inline_param_size;
3397
3398     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3399     bo = dri_bo_alloc(i965->intel.bufmgr,
3400                       "surface state & binding table",
3401                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3402                       4096);
3403     assert(bo);
3404     pp_context->surface_state_binding_table.bo = bo;
3405
3406     dri_bo_unreference(pp_context->curbe.bo);
3407     bo = dri_bo_alloc(i965->intel.bufmgr,
3408                       "constant buffer",
3409                       4096,
3410                       4096);
3411     assert(bo);
3412     pp_context->curbe.bo = bo;
3413
3414     dri_bo_unreference(pp_context->idrt.bo);
3415     bo = dri_bo_alloc(i965->intel.bufmgr,
3416                       "interface discriptor",
3417                       sizeof(struct gen6_interface_descriptor_data),
3418                       4096);
3419     assert(bo);
3420     pp_context->idrt.bo = bo;
3421     pp_context->idrt.num_interface_descriptors = 0;
3422
3423     dri_bo_unreference(pp_context->sampler_state_table.bo);
3424     bo = dri_bo_alloc(i965->intel.bufmgr,
3425                       "sampler state table",
3426                       4096,
3427                       4096);
3428     assert(bo);
3429     dri_bo_map(bo, True);
3430     memset(bo->virtual, 0, bo->size);
3431     dri_bo_unmap(bo);
3432     pp_context->sampler_state_table.bo = bo;
3433
3434     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3435     bo = dri_bo_alloc(i965->intel.bufmgr,
3436                       "sampler 8x8 state ",
3437                       4096,
3438                       4096);
3439     assert(bo);
3440     pp_context->sampler_state_table.bo_8x8 = bo;
3441
3442     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3443     bo = dri_bo_alloc(i965->intel.bufmgr,
3444                       "sampler 8x8 state ",
3445                       4096,
3446                       4096);
3447     assert(bo);
3448     pp_context->sampler_state_table.bo_8x8_uv = bo;
3449
3450     dri_bo_unreference(pp_context->vfe_state.bo);
3451     bo = dri_bo_alloc(i965->intel.bufmgr,
3452                       "vfe state",
3453                       sizeof(struct i965_vfe_state),
3454                       4096);
3455     assert(bo);
3456     pp_context->vfe_state.bo = bo;
3457
3458     if (IS_GEN7(i965->intel.device_id)) {
3459         static_param_size = sizeof(struct gen7_pp_static_parameter);
3460         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3461     } else {
3462         static_param_size = sizeof(struct pp_static_parameter);
3463         inline_param_size = sizeof(struct pp_inline_parameter);
3464     }
3465
3466     memset(pp_context->pp_static_parameter, 0, static_param_size);
3467     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3468
3469     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3470     pp_context->current_pp = pp_index;
3471     pp_module = &pp_context->pp_modules[pp_index];
3472
3473     if (pp_module->initialize)
3474         va_status = pp_module->initialize(ctx, pp_context,
3475                                           src_surface,
3476                                           src_rect,
3477                                           dst_surface,
3478                                           dst_rect,
3479                                           filter_param);
3480     else
3481         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3482
3483     return va_status;
3484 }
3485
3486 static void
3487 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3488                                    struct i965_post_processing_context *pp_context)
3489 {
3490     struct i965_driver_data *i965 = i965_driver_data(ctx);
3491     struct gen6_interface_descriptor_data *desc;
3492     dri_bo *bo;
3493     int pp_index = pp_context->current_pp;
3494
3495     bo = pp_context->idrt.bo;
3496     dri_bo_map(bo, True);
3497     assert(bo->virtual);
3498     desc = bo->virtual;
3499     memset(desc, 0, sizeof(*desc));
3500     desc->desc0.kernel_start_pointer =
3501         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3502     desc->desc1.single_program_flow = 1;
3503     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3504     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3505     desc->desc2.sampler_state_pointer =
3506         pp_context->sampler_state_table.bo->offset >> 5;
3507     desc->desc3.binding_table_entry_count = 0;
3508     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3509     desc->desc4.constant_urb_entry_read_offset = 0;
3510
3511     if (IS_GEN7(i965->intel.device_id))
3512         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3513     else
3514         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3515
3516     dri_bo_emit_reloc(bo,
3517                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3518                       0,
3519                       offsetof(struct gen6_interface_descriptor_data, desc0),
3520                       pp_context->pp_modules[pp_index].kernel.bo);
3521
3522     dri_bo_emit_reloc(bo,
3523                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3524                       desc->desc2.sampler_count << 2,
3525                       offsetof(struct gen6_interface_descriptor_data, desc2),
3526                       pp_context->sampler_state_table.bo);
3527
3528     dri_bo_unmap(bo);
3529     pp_context->idrt.num_interface_descriptors++;
3530 }
3531
3532 static void
3533 gen6_pp_upload_constants(VADriverContextP ctx,
3534                          struct i965_post_processing_context *pp_context)
3535 {
3536     struct i965_driver_data *i965 = i965_driver_data(ctx);
3537     unsigned char *constant_buffer;
3538     int param_size;
3539
3540     assert(sizeof(struct pp_static_parameter) == 128);
3541     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3542
3543     if (IS_GEN7(i965->intel.device_id))
3544         param_size = sizeof(struct gen7_pp_static_parameter);
3545     else
3546         param_size = sizeof(struct pp_static_parameter);
3547
3548     dri_bo_map(pp_context->curbe.bo, 1);
3549     assert(pp_context->curbe.bo->virtual);
3550     constant_buffer = pp_context->curbe.bo->virtual;
3551     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3552     dri_bo_unmap(pp_context->curbe.bo);
3553 }
3554
3555 static void
3556 gen6_pp_states_setup(VADriverContextP ctx,
3557                      struct i965_post_processing_context *pp_context)
3558 {
3559     gen6_pp_interface_descriptor_table(ctx, pp_context);
3560     gen6_pp_upload_constants(ctx, pp_context);
3561 }
3562
3563 static void
3564 gen6_pp_pipeline_select(VADriverContextP ctx,
3565                         struct i965_post_processing_context *pp_context)
3566 {
3567     struct intel_batchbuffer *batch = pp_context->batch;
3568
3569     BEGIN_BATCH(batch, 1);
3570     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3571     ADVANCE_BATCH(batch);
3572 }
3573
3574 static void
3575 gen6_pp_state_base_address(VADriverContextP ctx,
3576                            struct i965_post_processing_context *pp_context)
3577 {
3578     struct intel_batchbuffer *batch = pp_context->batch;
3579
3580     BEGIN_BATCH(batch, 10);
3581     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3582     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3583     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3584     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3585     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3586     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3587     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3588     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3589     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3590     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3591     ADVANCE_BATCH(batch);
3592 }
3593
3594 static void
3595 gen6_pp_vfe_state(VADriverContextP ctx,
3596                   struct i965_post_processing_context *pp_context)
3597 {
3598     struct intel_batchbuffer *batch = pp_context->batch;
3599
3600     BEGIN_BATCH(batch, 8);
3601     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3602     OUT_BATCH(batch, 0);
3603     OUT_BATCH(batch,
3604               (pp_context->urb.num_vfe_entries - 1) << 16 |
3605               pp_context->urb.num_vfe_entries << 8);
3606     OUT_BATCH(batch, 0);
3607     OUT_BATCH(batch,
3608               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3609               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3610     OUT_BATCH(batch, 0);
3611     OUT_BATCH(batch, 0);
3612     OUT_BATCH(batch, 0);
3613     ADVANCE_BATCH(batch);
3614 }
3615
3616 static void
3617 gen6_pp_curbe_load(VADriverContextP ctx,
3618                    struct i965_post_processing_context *pp_context)
3619 {
3620     struct intel_batchbuffer *batch = pp_context->batch;
3621
3622     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3623
3624     BEGIN_BATCH(batch, 4);
3625     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3626     OUT_BATCH(batch, 0);
3627     OUT_BATCH(batch,
3628               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3629     OUT_RELOC(batch,
3630               pp_context->curbe.bo,
3631               I915_GEM_DOMAIN_INSTRUCTION, 0,
3632               0);
3633     ADVANCE_BATCH(batch);
3634 }
3635
3636 static void
3637 gen6_interface_descriptor_load(VADriverContextP ctx,
3638                                struct i965_post_processing_context *pp_context)
3639 {
3640     struct intel_batchbuffer *batch = pp_context->batch;
3641
3642     BEGIN_BATCH(batch, 4);
3643     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3644     OUT_BATCH(batch, 0);
3645     OUT_BATCH(batch,
3646               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3647     OUT_RELOC(batch,
3648               pp_context->idrt.bo,
3649               I915_GEM_DOMAIN_INSTRUCTION, 0,
3650               0);
3651     ADVANCE_BATCH(batch);
3652 }
3653
3654 static void
3655 gen6_pp_object_walker(VADriverContextP ctx,
3656                       struct i965_post_processing_context *pp_context)
3657 {
3658     struct i965_driver_data *i965 = i965_driver_data(ctx);
3659     struct intel_batchbuffer *batch = pp_context->batch;
3660     int x, x_steps, y, y_steps;
3661     int param_size, command_length_in_dws;
3662     dri_bo *command_buffer;
3663     unsigned int *command_ptr;
3664
3665     if (IS_GEN7(i965->intel.device_id))
3666         param_size = sizeof(struct gen7_pp_inline_parameter);
3667     else
3668         param_size = sizeof(struct pp_inline_parameter);
3669
3670     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3671     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3672     command_length_in_dws = 6 + (param_size >> 2);
3673     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3674                                   "command objects buffer",
3675                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3676                                   4096);
3677
3678     dri_bo_map(command_buffer, 1);
3679     command_ptr = command_buffer->virtual;
3680
3681     for (y = 0; y < y_steps; y++) {
3682         for (x = 0; x < x_steps; x++) {
3683             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3684                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3685                 *command_ptr++ = 0;
3686                 *command_ptr++ = 0;
3687                 *command_ptr++ = 0;
3688                 *command_ptr++ = 0;
3689                 *command_ptr++ = 0;
3690                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3691                 command_ptr += (param_size >> 2);
3692             }
3693         }
3694     }
3695
3696     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3697         *command_ptr++ = 0;
3698
3699     *command_ptr = MI_BATCH_BUFFER_END;
3700
3701     dri_bo_unmap(command_buffer);
3702
3703     BEGIN_BATCH(batch, 2);
3704     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3705     OUT_RELOC(batch, command_buffer,
3706               I915_GEM_DOMAIN_COMMAND, 0,
3707               0);
3708     ADVANCE_BATCH(batch);
3709
3710     dri_bo_unreference(command_buffer);
3711
3712     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3713      * will cause control to pass back to ring buffer
3714      */
3715     intel_batchbuffer_end_atomic(batch);
3716     intel_batchbuffer_flush(batch);
3717     intel_batchbuffer_start_atomic(batch, 0x1000);
3718 }
3719
3720 static void
3721 gen6_pp_pipeline_setup(VADriverContextP ctx,
3722                        struct i965_post_processing_context *pp_context)
3723 {
3724     struct intel_batchbuffer *batch = pp_context->batch;
3725
3726     intel_batchbuffer_start_atomic(batch, 0x1000);
3727     intel_batchbuffer_emit_mi_flush(batch);
3728     gen6_pp_pipeline_select(ctx, pp_context);
3729     gen6_pp_state_base_address(ctx, pp_context);
3730     gen6_pp_vfe_state(ctx, pp_context);
3731     gen6_pp_curbe_load(ctx, pp_context);
3732     gen6_interface_descriptor_load(ctx, pp_context);
3733     gen6_pp_object_walker(ctx, pp_context);
3734     intel_batchbuffer_end_atomic(batch);
3735 }
3736
3737 static VAStatus
3738 gen6_post_processing(
3739     VADriverContextP   ctx,
3740     struct i965_post_processing_context *pp_context,
3741     const struct i965_surface *src_surface,
3742     const VARectangle *src_rect,
3743     struct i965_surface *dst_surface,
3744     const VARectangle *dst_rect,
3745     int                pp_index,
3746     void * filter_param
3747 )
3748 {
3749     VAStatus va_status;
3750
3751     va_status = gen6_pp_initialize(ctx, pp_context,
3752                                    src_surface,
3753                                    src_rect,
3754                                    dst_surface,
3755                                    dst_rect,
3756                                    pp_index,
3757                                    filter_param);
3758
3759     if (va_status == VA_STATUS_SUCCESS) {
3760         gen6_pp_states_setup(ctx, pp_context);
3761         gen6_pp_pipeline_setup(ctx, pp_context);
3762     }
3763
3764     return va_status;
3765 }
3766
3767 static VAStatus
3768 i965_post_processing_internal(
3769     VADriverContextP   ctx,
3770     struct i965_post_processing_context *pp_context,
3771     const struct i965_surface *src_surface,
3772     const VARectangle *src_rect,
3773     struct i965_surface *dst_surface,
3774     const VARectangle *dst_rect,
3775     int                pp_index,
3776     void *filter_param
3777 )
3778 {
3779     struct i965_driver_data *i965 = i965_driver_data(ctx);
3780     VAStatus va_status;
3781
3782     if (IS_GEN6(i965->intel.device_id) ||
3783         IS_GEN7(i965->intel.device_id))
3784         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3785     else
3786         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3787
3788     return va_status;
3789 }
3790
3791 VAStatus
3792 i965_DestroySurfaces(VADriverContextP ctx,
3793                      VASurfaceID *surface_list,
3794                      int num_surfaces);
3795 VAStatus
3796 i965_CreateSurfaces(VADriverContextP ctx,
3797                     int width,
3798                     int height,
3799                     int format,
3800                     int num_surfaces,
3801                     VASurfaceID *surfaces);
3802
3803 static void
3804 rgb_to_yuv(unsigned int argb,
3805            unsigned char *y,
3806            unsigned char *u,
3807            unsigned char *v,
3808            unsigned char *a)
3809 {
3810     int r = ((argb >> 16) & 0xff);
3811     int g = ((argb >> 8) & 0xff);
3812     int b = ((argb >> 0) & 0xff);
3813
3814     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3815     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3816     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3817     *a = ((argb >> 24) & 0xff);
3818 }
3819
3820 static void
3821 i965_vpp_clear_surface(VADriverContextP ctx,
3822                        struct i965_post_processing_context *pp_context,
3823                        VASurfaceID surface,
3824                        unsigned int color)
3825 {
3826     struct i965_driver_data *i965 = i965_driver_data(ctx);
3827     struct intel_batchbuffer *batch = pp_context->batch;
3828     struct object_surface *obj_surface = SURFACE(surface);
3829     unsigned int blt_cmd, br13;
3830     unsigned int tiling = 0, swizzle = 0;
3831     int pitch;
3832     unsigned char y, u, v, a = 0;
3833
3834     /* Currently only support NV12 surface */
3835     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3836         return;
3837
3838     rgb_to_yuv(color, &y, &u, &v, &a);
3839
3840     if (a == 0)
3841         return;
3842
3843     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3844     blt_cmd = XY_COLOR_BLT_CMD;
3845     pitch = obj_surface->width;
3846
3847     if (tiling != I915_TILING_NONE) {
3848         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3849         pitch >>= 2;
3850     }
3851
3852     br13 = 0xf0 << 16;
3853     br13 |= BR13_8;
3854     br13 |= pitch;
3855
3856     if (IS_GEN6(i965->intel.device_id) ||
3857         IS_GEN7(i965->intel.device_id)) {
3858         intel_batchbuffer_start_atomic_blt(batch, 48);
3859         BEGIN_BLT_BATCH(batch, 12);
3860     } else {
3861         intel_batchbuffer_start_atomic(batch, 48);
3862         BEGIN_BATCH(batch, 12);
3863     }
3864
3865     OUT_BATCH(batch, blt_cmd);
3866     OUT_BATCH(batch, br13);
3867     OUT_BATCH(batch,
3868               0 << 16 |
3869               0);
3870     OUT_BATCH(batch,
3871               obj_surface->height << 16 |
3872               obj_surface->width);
3873     OUT_RELOC(batch, obj_surface->bo,
3874               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3875               0);
3876     OUT_BATCH(batch, y);
3877
3878     br13 = 0xf0 << 16;
3879     br13 |= BR13_565;
3880     br13 |= pitch;
3881
3882     OUT_BATCH(batch, blt_cmd);
3883     OUT_BATCH(batch, br13);
3884     OUT_BATCH(batch,
3885               0 << 16 |
3886               0);
3887     OUT_BATCH(batch,
3888               obj_surface->height / 2 << 16 |
3889               obj_surface->width / 2);
3890     OUT_RELOC(batch, obj_surface->bo,
3891               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3892               obj_surface->width * obj_surface->y_cb_offset);
3893     OUT_BATCH(batch, v << 8 | u);
3894
3895     ADVANCE_BATCH(batch);
3896     intel_batchbuffer_end_atomic(batch);
3897 }
3898
3899 VASurfaceID
3900 i965_post_processing(
3901     VADriverContextP   ctx,
3902     VASurfaceID        surface,
3903     const VARectangle *src_rect,
3904     const VARectangle *dst_rect,
3905     unsigned int       flags,
3906     int               *has_done_scaling
3907 )
3908 {
3909     struct i965_driver_data *i965 = i965_driver_data(ctx);
3910     VASurfaceID in_surface_id = surface;
3911     VASurfaceID out_surface_id = VA_INVALID_ID;
3912
3913     *has_done_scaling = 0;
3914
3915     if (HAS_PP(i965)) {
3916         struct object_surface *obj_surface;
3917         VAStatus status;
3918         struct i965_surface src_surface;
3919         struct i965_surface dst_surface;
3920
3921         obj_surface = SURFACE(in_surface_id);
3922
3923         /* Currently only support post processing for NV12 surface */
3924         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3925             return out_surface_id;
3926
3927         _i965LockMutex(&i965->pp_mutex);
3928
3929         if (flags & I965_PP_FLAG_MCDI) {
3930             status = i965_CreateSurfaces(ctx,
3931                                          obj_surface->orig_width,
3932                                          obj_surface->orig_height,
3933                                          VA_RT_FORMAT_YUV420,
3934                                          1,
3935                                          &out_surface_id);
3936             assert(status == VA_STATUS_SUCCESS);
3937             obj_surface = SURFACE(out_surface_id);
3938             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3939             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3940             src_surface.id = in_surface_id;
3941             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3942             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3943                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3944             dst_surface.id = out_surface_id;
3945             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3946             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3947
3948             i965_post_processing_internal(ctx, i965->pp_context,
3949                                           &src_surface,
3950                                           src_rect,
3951                                           &dst_surface,
3952                                           dst_rect,
3953                                           PP_NV12_DNDI,
3954                                           NULL);
3955         }
3956
3957         if (flags & I965_PP_FLAG_AVS) {
3958             struct i965_render_state *render_state = &i965->render_state;
3959             struct intel_region *dest_region = render_state->draw_region;
3960
3961             if (out_surface_id != VA_INVALID_ID)
3962                 in_surface_id = out_surface_id;
3963
3964             status = i965_CreateSurfaces(ctx,
3965                                          dest_region->width,
3966                                          dest_region->height,
3967                                          VA_RT_FORMAT_YUV420,
3968                                          1,
3969                                          &out_surface_id);
3970             assert(status == VA_STATUS_SUCCESS);
3971             obj_surface = SURFACE(out_surface_id);
3972             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3973             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3974             src_surface.id = in_surface_id;
3975             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3976             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3977             dst_surface.id = out_surface_id;
3978             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3979             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3980
3981             i965_post_processing_internal(ctx, i965->pp_context,
3982                                           &src_surface,
3983                                           src_rect,
3984                                           &dst_surface,
3985                                           dst_rect,
3986                                           PP_NV12_AVS,
3987                                           NULL);
3988
3989             if (in_surface_id != surface)
3990                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3991
3992             *has_done_scaling = 1;
3993         }
3994
3995         _i965UnlockMutex(&i965->pp_mutex);
3996     }
3997
3998     return out_surface_id;
3999 }
4000
4001 static VAStatus
4002 i965_image_pl3_processing(VADriverContextP ctx,
4003                           const struct i965_surface *src_surface,
4004                           const VARectangle *src_rect,
4005                           struct i965_surface *dst_surface,
4006                           const VARectangle *dst_rect)
4007 {
4008     struct i965_driver_data *i965 = i965_driver_data(ctx);
4009     struct i965_post_processing_context *pp_context = i965->pp_context;
4010     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4011     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4012
4013     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4014         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4015                                                  src_surface,
4016                                                  src_rect,
4017                                                  dst_surface,
4018                                                  dst_rect,
4019                                                  PP_PL3_LOAD_SAVE_N12,
4020                                                  NULL);
4021     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4022                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4023                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4024                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4025         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4026                                                  src_surface,
4027                                                  src_rect,
4028                                                  dst_surface,
4029                                                  dst_rect,
4030                                                  PP_PL3_LOAD_SAVE_PL3,
4031                                                  NULL);
4032     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4033                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4034         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4035                                                  src_surface,
4036                                                  src_rect,
4037                                                  dst_surface,
4038                                                  dst_rect,
4039                                                  PP_PL3_LOAD_SAVE_PA,
4040                                                  NULL);
4041     }
4042     else {
4043         assert(0);
4044     }
4045
4046     intel_batchbuffer_flush(pp_context->batch);
4047
4048     return vaStatus;
4049 }
4050
4051 static VAStatus
4052 i965_image_pl2_processing(VADriverContextP ctx,
4053                           const struct i965_surface *src_surface,
4054                           const VARectangle *src_rect,
4055                           struct i965_surface *dst_surface,
4056                           const VARectangle *dst_rect)
4057 {
4058     struct i965_driver_data *i965 = i965_driver_data(ctx);
4059     struct i965_post_processing_context *pp_context = i965->pp_context;
4060     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4061     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4062
4063     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4064         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4065                                                  src_surface,
4066                                                  src_rect,
4067                                                  dst_surface,
4068                                                  dst_rect,
4069                                                  PP_NV12_LOAD_SAVE_N12,
4070                                                  NULL);
4071     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4072                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4073                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4074                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4075         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4076                                                  src_surface,
4077                                                  src_rect,
4078                                                  dst_surface,
4079                                                  dst_rect,
4080                                                  PP_NV12_LOAD_SAVE_PL3,
4081                                                  NULL);
4082     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4083                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4084         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4085                                                  src_surface,
4086                                                  src_rect,
4087                                                  dst_surface,
4088                                                  dst_rect,
4089                                                  PP_NV12_LOAD_SAVE_PA,
4090                                                      NULL);
4091     }
4092
4093     intel_batchbuffer_flush(pp_context->batch);
4094
4095     return vaStatus;
4096 }
4097
4098 static VAStatus
4099 i965_image_pl1_processing(VADriverContextP ctx,
4100                           const struct i965_surface *src_surface,
4101                           const VARectangle *src_rect,
4102                           struct i965_surface *dst_surface,
4103                           const VARectangle *dst_rect)
4104 {
4105     struct i965_driver_data *i965 = i965_driver_data(ctx);
4106     struct i965_post_processing_context *pp_context = i965->pp_context;
4107     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4108
4109     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4110         i965_post_processing_internal(ctx, i965->pp_context,
4111                                       src_surface,
4112                                       src_rect,
4113                                       dst_surface,
4114                                       dst_rect,
4115                                       PP_PA_LOAD_SAVE_NV12,
4116                                       NULL);
4117     }
4118     else if (fourcc == VA_FOURCC_YV12) {
4119         i965_post_processing_internal(ctx, i965->pp_context,
4120                                       src_surface,
4121                                       src_rect,
4122                                       dst_surface,
4123                                       dst_rect,
4124                                       PP_PA_LOAD_SAVE_PL3,
4125                                       NULL);
4126
4127     }
4128     else {
4129         return VA_STATUS_ERROR_UNKNOWN;
4130     }
4131
4132     intel_batchbuffer_flush(pp_context->batch);
4133
4134     return VA_STATUS_SUCCESS;
4135 }
4136
4137 VAStatus
4138 i965_image_processing(VADriverContextP ctx,
4139                       const struct i965_surface *src_surface,
4140                       const VARectangle *src_rect,
4141                       struct i965_surface *dst_surface,
4142                       const VARectangle *dst_rect)
4143 {
4144     struct i965_driver_data *i965 = i965_driver_data(ctx);
4145     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4146
4147     if (HAS_PP(i965)) {
4148         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4149
4150         _i965LockMutex(&i965->pp_mutex);
4151
4152         switch (fourcc) {
4153         case VA_FOURCC('Y', 'V', '1', '2'):
4154         case VA_FOURCC('I', '4', '2', '0'):
4155         case VA_FOURCC('I', 'M', 'C', '1'):
4156         case VA_FOURCC('I', 'M', 'C', '3'):
4157             status = i965_image_pl3_processing(ctx,
4158                                                src_surface,
4159                                                src_rect,
4160                                                dst_surface,
4161                                                dst_rect);
4162             break;
4163
4164         case  VA_FOURCC('N', 'V', '1', '2'):
4165             status = i965_image_pl2_processing(ctx,
4166                                                src_surface,
4167                                                src_rect,
4168                                                dst_surface,
4169                                                dst_rect);
4170             break;
4171         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4172         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4173             status = i965_image_pl1_processing(ctx,
4174                                                src_surface,
4175                                                src_rect,
4176                                                dst_surface,
4177                                                dst_rect);
4178             break;
4179
4180         default:
4181             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4182             break;
4183         }
4184
4185         _i965UnlockMutex(&i965->pp_mutex);
4186     }
4187
4188     return status;
4189 }
4190
4191 static void
4192 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4193 {
4194     int i;
4195
4196     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4197     pp_context->surface_state_binding_table.bo = NULL;
4198
4199     dri_bo_unreference(pp_context->curbe.bo);
4200     pp_context->curbe.bo = NULL;
4201
4202     dri_bo_unreference(pp_context->sampler_state_table.bo);
4203     pp_context->sampler_state_table.bo = NULL;
4204
4205     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4206     pp_context->sampler_state_table.bo_8x8 = NULL;
4207
4208     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4209     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4210
4211     dri_bo_unreference(pp_context->idrt.bo);
4212     pp_context->idrt.bo = NULL;
4213     pp_context->idrt.num_interface_descriptors = 0;
4214
4215     dri_bo_unreference(pp_context->vfe_state.bo);
4216     pp_context->vfe_state.bo = NULL;
4217
4218     dri_bo_unreference(pp_context->stmm.bo);
4219     pp_context->stmm.bo = NULL;
4220
4221     for (i = 0; i < NUM_PP_MODULES; i++) {
4222         struct pp_module *pp_module = &pp_context->pp_modules[i];
4223
4224         dri_bo_unreference(pp_module->kernel.bo);
4225         pp_module->kernel.bo = NULL;
4226     }
4227
4228     free(pp_context->pp_static_parameter);
4229     free(pp_context->pp_inline_parameter);
4230     pp_context->pp_static_parameter = NULL;
4231     pp_context->pp_inline_parameter = NULL;
4232 }
4233
4234 Bool
4235 i965_post_processing_terminate(VADriverContextP ctx)
4236 {
4237     struct i965_driver_data *i965 = i965_driver_data(ctx);
4238     struct i965_post_processing_context *pp_context = i965->pp_context;
4239
4240     if (pp_context) {
4241         i965_post_processing_context_finalize(pp_context);
4242         free(pp_context);
4243     }
4244
4245     i965->pp_context = NULL;
4246
4247     return True;
4248 }
4249
4250 static void
4251 i965_post_processing_context_init(VADriverContextP ctx,
4252                                   struct i965_post_processing_context *pp_context,
4253                                   struct intel_batchbuffer *batch)
4254 {
4255     struct i965_driver_data *i965 = i965_driver_data(ctx);
4256     int i;
4257
4258     pp_context->urb.size = URB_SIZE((&i965->intel));
4259     pp_context->urb.num_vfe_entries = 32;
4260     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4261     pp_context->urb.num_cs_entries = 1;
4262
4263     if (IS_GEN7(i965->intel.device_id))
4264         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4265     else
4266         pp_context->urb.size_cs_entry = 2;
4267
4268     pp_context->urb.vfe_start = 0;
4269     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4270         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4271     assert(pp_context->urb.cs_start +
4272            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4273
4274     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4275     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4276     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4277
4278     if (IS_GEN7(i965->intel.device_id))
4279         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4280     else if (IS_GEN6(i965->intel.device_id))
4281         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4282     else if (IS_IRONLAKE(i965->intel.device_id))
4283         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4284
4285     for (i = 0; i < NUM_PP_MODULES; i++) {
4286         struct pp_module *pp_module = &pp_context->pp_modules[i];
4287         dri_bo_unreference(pp_module->kernel.bo);
4288         if (pp_module->kernel.bin && pp_module->kernel.size) {
4289             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4290                                                 pp_module->kernel.name,
4291                                                 pp_module->kernel.size,
4292                                                 4096);
4293             assert(pp_module->kernel.bo);
4294             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4295         } else {
4296             pp_module->kernel.bo = NULL;
4297         }
4298     }
4299
4300     /* static & inline parameters */
4301     if (IS_GEN7(i965->intel.device_id)) {
4302         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4303         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4304     } else {
4305         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4306         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4307     }
4308
4309     pp_context->batch = batch;
4310 }
4311
4312 Bool
4313 i965_post_processing_init(VADriverContextP ctx)
4314 {
4315     struct i965_driver_data *i965 = i965_driver_data(ctx);
4316     struct i965_post_processing_context *pp_context = i965->pp_context;
4317
4318     if (HAS_PP(i965)) {
4319         if (pp_context == NULL) {
4320             pp_context = calloc(1, sizeof(*pp_context));
4321             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4322             i965->pp_context = pp_context;
4323         }
4324     }
4325
4326     return True;
4327 }
4328
4329 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4330     PP_NULL,    /* VAProcFilterNone */
4331     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4332     PP_NULL,    /* VAProcFilterDeblocking */
4333     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4334     PP_NULL,    /* VAProcFilterSharpening */
4335     PP_NULL,    /* VAProcFilterColorBalance */
4336     PP_NULL,    /* VAProcFilterColorStandard */
4337     PP_NULL,    /* VAProcFilterFrameRateConversion */
4338 };
4339
4340 static const int proc_frame_to_pp_frame[3] = {
4341     I965_SURFACE_FLAG_FRAME,
4342     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4343     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4344 };
4345
4346 static void
4347 i965_proc_picture(VADriverContextP ctx,
4348                   VAProfile profile,
4349                   union codec_state *codec_state,
4350                   struct hw_context *hw_context)
4351 {
4352     struct i965_driver_data *i965 = i965_driver_data(ctx);
4353     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4354     struct proc_state *proc_state = &codec_state->proc;
4355     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4356     struct object_surface *obj_surface;
4357     struct i965_surface src_surface, dst_surface;
4358     VARectangle src_rect, dst_rect;
4359     VAStatus status;
4360     int i;
4361     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4362     int num_tmp_surfaces = 0;
4363     unsigned int tiling = 0, swizzle = 0;
4364     int in_width, in_height;
4365
4366     assert(pipeline_param->surface != VA_INVALID_ID);
4367     assert(proc_state->current_render_target != VA_INVALID_ID);
4368
4369     obj_surface = SURFACE(pipeline_param->surface);
4370     in_width = obj_surface->orig_width;
4371     in_height = obj_surface->orig_height;
4372     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4373
4374     src_surface.id = pipeline_param->surface;
4375     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4376     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4377
4378     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4379         VASurfaceID out_surface_id = VA_INVALID_ID;
4380
4381         src_surface.id = pipeline_param->surface;
4382         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4383         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4384         src_rect.x = 0;
4385         src_rect.y = 0;
4386         src_rect.width = in_width;
4387         src_rect.height = in_height;
4388
4389         status = i965_CreateSurfaces(ctx,
4390                                      in_width,
4391                                      in_height,
4392                                      VA_RT_FORMAT_YUV420,
4393                                      1,
4394                                      &out_surface_id);
4395         assert(status == VA_STATUS_SUCCESS);
4396         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4397         obj_surface = SURFACE(out_surface_id);
4398         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4399
4400         dst_surface.id = out_surface_id;
4401         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4402         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4403         dst_rect.x = 0;
4404         dst_rect.y = 0;
4405         dst_rect.width = in_width;
4406         dst_rect.height = in_height;
4407
4408         status = i965_image_processing(ctx,
4409                                        &src_surface,
4410                                        &src_rect,
4411                                        &dst_surface,
4412                                        &dst_rect);
4413         assert(status == VA_STATUS_SUCCESS);
4414
4415         src_surface.id = out_surface_id;
4416         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4417         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4418     }
4419
4420     if (pipeline_param->surface_region) {
4421         src_rect.x = pipeline_param->surface_region->x;
4422         src_rect.y = pipeline_param->surface_region->y;
4423         src_rect.width = pipeline_param->surface_region->width;
4424         src_rect.height = pipeline_param->surface_region->height;
4425     } else {
4426         src_rect.x = 0;
4427         src_rect.y = 0;
4428         src_rect.width = in_width;
4429         src_rect.height = in_height;
4430     }
4431
4432     if (pipeline_param->output_region) {
4433         dst_rect.x = pipeline_param->output_region->x;
4434         dst_rect.y = pipeline_param->output_region->y;
4435         dst_rect.width = pipeline_param->output_region->width;
4436         dst_rect.height = pipeline_param->output_region->height;
4437     } else {
4438         dst_rect.x = 0;
4439         dst_rect.y = 0;
4440         dst_rect.width = in_width;
4441         dst_rect.height = in_height;
4442     }
4443
4444     obj_surface = SURFACE(proc_state->current_render_target);
4445     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4446     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4447
4448     for (i = 0; i < pipeline_param->num_filters; i++) {
4449         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4450         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4451         VAProcFilterType filter_type = filter_param->type;
4452         VASurfaceID out_surface_id = VA_INVALID_ID;
4453         int kernel_index = procfilter_to_pp_flag[filter_type];
4454
4455         if (kernel_index != PP_NULL &&
4456             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4457             status = i965_CreateSurfaces(ctx,
4458                                          in_width,
4459                                          in_height,
4460                                          VA_RT_FORMAT_YUV420,
4461                                          1,
4462                                          &out_surface_id);
4463             assert(status == VA_STATUS_SUCCESS);
4464             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4465             obj_surface = SURFACE(out_surface_id);
4466             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4467             dst_surface.id = out_surface_id;
4468             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4469             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4470                                                    &src_surface,
4471                                                    &src_rect,
4472                                                    &dst_surface,
4473                                                    &src_rect,
4474                                                    kernel_index,
4475                                                    filter_param);
4476
4477             if (status == VA_STATUS_SUCCESS) {
4478                 src_surface.id = dst_surface.id;
4479                 src_surface.type = dst_surface.type;
4480                 src_surface.flags = dst_surface.flags;
4481             }
4482         }
4483     }
4484
4485     dst_surface.id = proc_state->current_render_target;
4486     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4487
4488     if (src_rect.width == dst_rect.width &&
4489         src_rect.height == dst_rect.height) {
4490         i965_post_processing_internal(ctx, &proc_context->pp_context,
4491                                       &src_surface,
4492                                       &src_rect,
4493                                       &dst_surface,
4494                                       &dst_rect,
4495                                       PP_NV12_LOAD_SAVE_N12,
4496                                       NULL);
4497     } else {
4498
4499         i965_post_processing_internal(ctx, &proc_context->pp_context,
4500                                       &src_surface,
4501                                       &src_rect,
4502                                       &dst_surface,
4503                                       &dst_rect,
4504                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4505                                       PP_NV12_AVS : PP_NV12_SCALING,
4506                                       NULL);
4507     }
4508
4509     if (num_tmp_surfaces)
4510         i965_DestroySurfaces(ctx,
4511                              tmp_surfaces,
4512                              num_tmp_surfaces);
4513
4514     intel_batchbuffer_flush(hw_context->batch);
4515 }
4516
4517 static void
4518 i965_proc_context_destroy(void *hw_context)
4519 {
4520     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4521
4522     i965_post_processing_context_finalize(&proc_context->pp_context);
4523     intel_batchbuffer_free(proc_context->base.batch);
4524     free(proc_context);
4525 }
4526
4527 struct hw_context *
4528 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4529 {
4530     struct intel_driver_data *intel = intel_driver_data(ctx);
4531     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4532
4533     proc_context->base.destroy = i965_proc_context_destroy;
4534     proc_context->base.run = i965_proc_picture;
4535     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4536     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4537
4538     return (struct hw_context *)proc_context;
4539 }