src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
  99 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
 100 };
 101
 102 static const uint32_t pp_pa_load_save_nv12_gen5[][4] = {
 103 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5"
 104 };
 105
 106 static const uint32_t pp_pa_load_save_pl3_gen5[][4] = {
 107 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5"
 108 };
 109
 110 static const uint32_t pp_rgbx_load_save_nv12_gen5[][4] = {
 111 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g4b.gen5"
 112 };
 113
 114 static const uint32_t pp_nv12_load_save_rgbx_gen5[][4] = {
 115 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g4b.gen5"
 116 };
 117
 118 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 119                                    const struct i965_surface *src_surface,
 120                                    const VARectangle *src_rect,
 121                                    struct i965_surface *dst_surface,
 122                                    const VARectangle *dst_rect,
 123                                    void *filter_param);
 124 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 125                                             const struct i965_surface *src_surface,
 126                                             const VARectangle *src_rect,
 127                                             struct i965_surface *dst_surface,
 128                                             const VARectangle *dst_rect,
 129                                             void *filter_param);
 130 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 131                                            const struct i965_surface *src_surface,
 132                                            const VARectangle *src_rect,
 133                                            struct i965_surface *dst_surface,
 134                                            const VARectangle *dst_rect,
 135                                            void *filter_param);
 136 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 137                                              const struct i965_surface *src_surface,
 138                                              const VARectangle *src_rect,
 139                                              struct i965_surface *dst_surface,
 140                                              const VARectangle *dst_rect,
 141                                              void *filter_param);
 142 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 143                                                 const struct i965_surface *src_surface,
 144                                                 const VARectangle *src_rect,
 145                                                 struct i965_surface *dst_surface,
 146                                                 const VARectangle *dst_rect,
 147                                                 void *filter_param);
 148 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 149                                         const struct i965_surface *src_surface,
 150                                         const VARectangle *src_rect,
 151                                         struct i965_surface *dst_surface,
 152                                         const VARectangle *dst_rect,
 153                                         void *filter_param);
 154 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 155                                       const struct i965_surface *src_surface,
 156                                       const VARectangle *src_rect,
 157                                       struct i965_surface *dst_surface,
 158                                       const VARectangle *dst_rect,
 159                                       void *filter_param);
 160
 161 static struct pp_module pp_modules_gen5[] = {
 162     {
 163         {
 164             "NULL module (for testing)",
 165             PP_NULL,
 166             pp_null_gen5,
 167             sizeof(pp_null_gen5),
 168             NULL,
 169         },
 170
 171         pp_null_initialize,
 172     },
 173
 174     {
 175         {
 176             "NV12_NV12",
 177             PP_NV12_LOAD_SAVE_N12,
 178             pp_nv12_load_save_nv12_gen5,
 179             sizeof(pp_nv12_load_save_nv12_gen5),
 180             NULL,
 181         },
 182
 183         pp_plx_load_save_plx_initialize,
 184     },
 185
 186     {
 187         {
 188             "NV12_PL3",
 189             PP_NV12_LOAD_SAVE_PL3,
 190             pp_nv12_load_save_pl3_gen5,
 191             sizeof(pp_nv12_load_save_pl3_gen5),
 192             NULL,
 193         },
 194
 195         pp_plx_load_save_plx_initialize,
 196     },
 197
 198     {
 199         {
 200             "PL3_NV12",
 201             PP_PL3_LOAD_SAVE_N12,
 202             pp_pl3_load_save_nv12_gen5,
 203             sizeof(pp_pl3_load_save_nv12_gen5),
 204             NULL,
 205         },
 206
 207         pp_plx_load_save_plx_initialize,
 208     },
 209
 210     {
 211         {
 212             "PL3_PL3",
 213             PP_PL3_LOAD_SAVE_N12,
 214             pp_pl3_load_save_pl3_gen5,
 215             sizeof(pp_pl3_load_save_pl3_gen5),
 216             NULL,
 217         },
 218
 219         pp_plx_load_save_plx_initialize
 220     },
 221
 222     {
 223         {
 224             "NV12 Scaling module",
 225             PP_NV12_SCALING,
 226             pp_nv12_scaling_gen5,
 227             sizeof(pp_nv12_scaling_gen5),
 228             NULL,
 229         },
 230
 231         pp_nv12_scaling_initialize,
 232     },
 233
 234     {
 235         {
 236             "NV12 AVS module",
 237             PP_NV12_AVS,
 238             pp_nv12_avs_gen5,
 239             sizeof(pp_nv12_avs_gen5),
 240             NULL,
 241         },
 242
 243         pp_nv12_avs_initialize_nlas,
 244     },
 245
 246     {
 247         {
 248             "NV12 DNDI module",
 249             PP_NV12_DNDI,
 250             pp_nv12_dndi_gen5,
 251             sizeof(pp_nv12_dndi_gen5),
 252             NULL,
 253         },
 254
 255         pp_nv12_dndi_initialize,
 256     },
 257
 258     {
 259         {
 260             "NV12 DN module",
 261             PP_NV12_DN,
 262             pp_nv12_dn_gen5,
 263             sizeof(pp_nv12_dn_gen5),
 264             NULL,
 265         },
 266
 267         pp_nv12_dn_initialize,
 268     },
 269
 270     {
 271         {
 272             "NV12_PA module",
 273             PP_NV12_LOAD_SAVE_PA,
 274             pp_nv12_load_save_pa_gen5,
 275             sizeof(pp_nv12_load_save_pa_gen5),
 276             NULL,
 277         },
 278
 279         pp_plx_load_save_plx_initialize,
 280     },
 281
 282     {
 283         {
 284             "PL3_PA module",
 285             PP_PL3_LOAD_SAVE_PA,
 286             pp_pl3_load_save_pa_gen5,
 287             sizeof(pp_pl3_load_save_pa_gen5),
 288             NULL,
 289         },
 290
 291         pp_plx_load_save_plx_initialize,
 292     },
 293
 294     {
 295         {
 296             "PA_NV12 module",
 297             PP_PA_LOAD_SAVE_NV12,
 298             pp_pa_load_save_nv12_gen5,
 299             sizeof(pp_pa_load_save_nv12_gen5),
 300             NULL,
 301         },
 302
 303         pp_plx_load_save_plx_initialize,
 304     },
 305
 306     {
 307         {
 308             "PA_PL3 module",
 309             PP_PA_LOAD_SAVE_PL3,
 310             pp_pa_load_save_pl3_gen5,
 311             sizeof(pp_pa_load_save_pl3_gen5),
 312             NULL,
 313         },
 314
 315         pp_plx_load_save_plx_initialize,
 316     },
 317
 318     {
 319         {
 320             "RGBX_NV12 module",
 321             PP_RGBX_LOAD_SAVE_NV12,
 322             pp_rgbx_load_save_nv12_gen5,
 323             sizeof(pp_rgbx_load_save_nv12_gen5),
 324             NULL,
 325         },
 326
 327         pp_plx_load_save_plx_initialize,
 328     },
 329
 330     {
 331         {
 332             "NV12_RGBX module",
 333             PP_NV12_LOAD_SAVE_RGBX,
 334             pp_nv12_load_save_rgbx_gen5,
 335             sizeof(pp_nv12_load_save_rgbx_gen5),
 336             NULL,
 337         },
 338
 339         pp_plx_load_save_plx_initialize,
 340     },
 341
 342 };
 343
 344 static const uint32_t pp_null_gen6[][4] = {
 345 #include "shaders/post_processing/gen5_6/null.g6b"
 346 };
 347
 348 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 349 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 350 };
 351
 352 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 353 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 354 };
 355
 356 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 357 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 358 };
 359
 360 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 361 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 362 };
 363
 364 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 365 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 366 };
 367
 368 static const uint32_t pp_nv12_avs_gen6[][4] = {
 369 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 370 };
 371
 372 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 373 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 374 };
 375
 376 static const uint32_t pp_nv12_dn_gen6[][4] = {
 377 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 378 };
 379
 380 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 381 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 382 };
 383
 384 static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
 385 #include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
 386 };
 387
 388 static const uint32_t pp_pa_load_save_nv12_gen6[][4] = {
 389 #include "shaders/post_processing/gen5_6/pa_load_save_nv12.g6b"
 390 };
 391
 392 static const uint32_t pp_pa_load_save_pl3_gen6[][4] = {
 393 #include "shaders/post_processing/gen5_6/pa_load_save_pl3.g6b"
 394 };
 395
 396 static const uint32_t pp_rgbx_load_save_nv12_gen6[][4] = {
 397 #include "shaders/post_processing/gen5_6/rgbx_load_save_nv12.g6b"
 398 };
 399
 400 static const uint32_t pp_nv12_load_save_rgbx_gen6[][4] = {
 401 #include "shaders/post_processing/gen5_6/nv12_load_save_rgbx.g6b"
 402 };
 403
 404 static struct pp_module pp_modules_gen6[] = {
 405     {
 406         {
 407             "NULL module (for testing)",
 408             PP_NULL,
 409             pp_null_gen6,
 410             sizeof(pp_null_gen6),
 411             NULL,
 412         },
 413
 414         pp_null_initialize,
 415     },
 416
 417     {
 418         {
 419             "NV12_NV12",
 420             PP_NV12_LOAD_SAVE_N12,
 421             pp_nv12_load_save_nv12_gen6,
 422             sizeof(pp_nv12_load_save_nv12_gen6),
 423             NULL,
 424         },
 425
 426         pp_plx_load_save_plx_initialize,
 427     },
 428
 429     {
 430         {
 431             "NV12_PL3",
 432             PP_NV12_LOAD_SAVE_PL3,
 433             pp_nv12_load_save_pl3_gen6,
 434             sizeof(pp_nv12_load_save_pl3_gen6),
 435             NULL,
 436         },
 437
 438         pp_plx_load_save_plx_initialize,
 439     },
 440
 441     {
 442         {
 443             "PL3_NV12",
 444             PP_PL3_LOAD_SAVE_N12,
 445             pp_pl3_load_save_nv12_gen6,
 446             sizeof(pp_pl3_load_save_nv12_gen6),
 447             NULL,
 448         },
 449
 450         pp_plx_load_save_plx_initialize,
 451     },
 452
 453     {
 454         {
 455             "PL3_PL3",
 456             PP_PL3_LOAD_SAVE_N12,
 457             pp_pl3_load_save_pl3_gen6,
 458             sizeof(pp_pl3_load_save_pl3_gen6),
 459             NULL,
 460         },
 461
 462         pp_plx_load_save_plx_initialize,
 463     },
 464
 465     {
 466         {
 467             "NV12 Scaling module",
 468             PP_NV12_SCALING,
 469             pp_nv12_scaling_gen6,
 470             sizeof(pp_nv12_scaling_gen6),
 471             NULL,
 472         },
 473
 474         gen6_nv12_scaling_initialize,
 475     },
 476
 477     {
 478         {
 479             "NV12 AVS module",
 480             PP_NV12_AVS,
 481             pp_nv12_avs_gen6,
 482             sizeof(pp_nv12_avs_gen6),
 483             NULL,
 484         },
 485
 486         pp_nv12_avs_initialize_nlas,
 487     },
 488
 489     {
 490         {
 491             "NV12 DNDI module",
 492             PP_NV12_DNDI,
 493             pp_nv12_dndi_gen6,
 494             sizeof(pp_nv12_dndi_gen6),
 495             NULL,
 496         },
 497
 498         pp_nv12_dndi_initialize,
 499     },
 500
 501     {
 502         {
 503             "NV12 DN module",
 504             PP_NV12_DN,
 505             pp_nv12_dn_gen6,
 506             sizeof(pp_nv12_dn_gen6),
 507             NULL,
 508         },
 509
 510         pp_nv12_dn_initialize,
 511     },
 512     {
 513         {
 514             "NV12_PA module",
 515             PP_NV12_LOAD_SAVE_PA,
 516             pp_nv12_load_save_pa_gen6,
 517             sizeof(pp_nv12_load_save_pa_gen6),
 518             NULL,
 519         },
 520
 521         pp_plx_load_save_plx_initialize,
 522     },
 523
 524     {
 525         {
 526             "PL3_PA module",
 527             PP_PL3_LOAD_SAVE_PA,
 528             pp_pl3_load_save_pa_gen6,
 529             sizeof(pp_pl3_load_save_pa_gen6),
 530             NULL,
 531         },
 532
 533         pp_plx_load_save_plx_initialize,
 534     },
 535
 536     {
 537         {
 538             "PA_NV12 module",
 539             PP_PA_LOAD_SAVE_NV12,
 540             pp_pa_load_save_nv12_gen6,
 541             sizeof(pp_pa_load_save_nv12_gen6),
 542             NULL,
 543         },
 544
 545         pp_plx_load_save_plx_initialize,
 546     },
 547
 548     {
 549         {
 550             "PA_PL3 module",
 551             PP_PA_LOAD_SAVE_PL3,
 552             pp_pa_load_save_pl3_gen6,
 553             sizeof(pp_pa_load_save_pl3_gen6),
 554             NULL,
 555         },
 556
 557         pp_plx_load_save_plx_initialize,
 558     },
 559
 560     {
 561         {
 562             "RGBX_NV12 module",
 563             PP_RGBX_LOAD_SAVE_NV12,
 564             pp_rgbx_load_save_nv12_gen6,
 565             sizeof(pp_rgbx_load_save_nv12_gen6),
 566             NULL,
 567         },
 568
 569         pp_plx_load_save_plx_initialize,
 570     },
 571
 572     {
 573         {
 574             "NV12_RGBX module",
 575             PP_NV12_LOAD_SAVE_RGBX,
 576             pp_nv12_load_save_rgbx_gen6,
 577             sizeof(pp_nv12_load_save_rgbx_gen6),
 578             NULL,
 579         },
 580
 581         pp_plx_load_save_plx_initialize,
 582     },
 583 };
 584
 585 static const uint32_t pp_null_gen7[][4] = {
 586 };
 587
 588 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 589 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 590 };
 591
 592 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 593 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 594 };
 595
 596 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 597 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 598 };
 599
 600 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 601 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 602 };
 603
 604 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 605 #include "shaders/post_processing/gen7/avs.g7b"
 606 };
 607
 608 static const uint32_t pp_nv12_avs_gen7[][4] = {
 609 #include "shaders/post_processing/gen7/avs.g7b"
 610 };
 611
 612 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 613 #include "shaders/post_processing/gen7/dndi.g7b"
 614 };
 615
 616 static const uint32_t pp_nv12_dn_gen7[][4] = {
 617 #include "shaders/post_processing/gen7/nv12_dn_nv12.g7b"
 618 };
 619 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 620 #include "shaders/post_processing/gen7/pl2_to_pa.g7b"
 621 };
 622 static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
 623 #include "shaders/post_processing/gen7/pl3_to_pa.g7b"
 624 };
 625 static const uint32_t pp_pa_load_save_nv12_gen7[][4] = {
 626 #include "shaders/post_processing/gen7/pa_to_pl2.g7b"
 627 };
 628 static const uint32_t pp_pa_load_save_pl3_gen7[][4] = {
 629 #include "shaders/post_processing/gen7/pa_to_pl3.g7b"
 630 };
 631 static const uint32_t pp_rgbx_load_save_nv12_gen7[][4] = {
 632 };
 633 static const uint32_t pp_nv12_load_save_rgbx_gen7[][4] = {
 634 };
 635
 636 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 637                                            const struct i965_surface *src_surface,
 638                                            const VARectangle *src_rect,
 639                                            struct i965_surface *dst_surface,
 640                                            const VARectangle *dst_rect,
 641                                            void *filter_param);
 642 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 643                                              const struct i965_surface *src_surface,
 644                                              const VARectangle *src_rect,
 645                                              struct i965_surface *dst_surface,
 646                                              const VARectangle *dst_rect,
 647                                              void *filter_param);
 648 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 649                                            const struct i965_surface *src_surface,
 650                                            const VARectangle *src_rect,
 651                                            struct i965_surface *dst_surface,
 652                                            const VARectangle *dst_rect,
 653                                            void *filter_param);
 654
 655 static struct pp_module pp_modules_gen7[] = {
 656     {
 657         {
 658             "NULL module (for testing)",
 659             PP_NULL,
 660             pp_null_gen7,
 661             sizeof(pp_null_gen7),
 662             NULL,
 663         },
 664
 665         pp_null_initialize,
 666     },
 667
 668     {
 669         {
 670             "NV12_NV12",
 671             PP_NV12_LOAD_SAVE_N12,
 672             pp_nv12_load_save_nv12_gen7,
 673             sizeof(pp_nv12_load_save_nv12_gen7),
 674             NULL,
 675         },
 676
 677         gen7_pp_plx_avs_initialize,
 678     },
 679
 680     {
 681         {
 682             "NV12_PL3",
 683             PP_NV12_LOAD_SAVE_PL3,
 684             pp_nv12_load_save_pl3_gen7,
 685             sizeof(pp_nv12_load_save_pl3_gen7),
 686             NULL,
 687         },
 688
 689         gen7_pp_plx_avs_initialize,
 690     },
 691
 692     {
 693         {
 694             "PL3_NV12",
 695             PP_PL3_LOAD_SAVE_N12,
 696             pp_pl3_load_save_nv12_gen7,
 697             sizeof(pp_pl3_load_save_nv12_gen7),
 698             NULL,
 699         },
 700
 701         gen7_pp_plx_avs_initialize,
 702     },
 703
 704     {
 705         {
 706             "PL3_PL3",
 707             PP_PL3_LOAD_SAVE_N12,
 708             pp_pl3_load_save_pl3_gen7,
 709             sizeof(pp_pl3_load_save_pl3_gen7),
 710             NULL,
 711         },
 712
 713         gen7_pp_plx_avs_initialize,
 714     },
 715
 716     {
 717         {
 718             "NV12 Scaling module",
 719             PP_NV12_SCALING,
 720             pp_nv12_scaling_gen7,
 721             sizeof(pp_nv12_scaling_gen7),
 722             NULL,
 723         },
 724
 725         gen7_pp_plx_avs_initialize,
 726     },
 727
 728     {
 729         {
 730             "NV12 AVS module",
 731             PP_NV12_AVS,
 732             pp_nv12_avs_gen7,
 733             sizeof(pp_nv12_avs_gen7),
 734             NULL,
 735         },
 736
 737         gen7_pp_plx_avs_initialize,
 738     },
 739
 740     {
 741         {
 742             "NV12 DNDI module",
 743             PP_NV12_DNDI,
 744             pp_nv12_dndi_gen7,
 745             sizeof(pp_nv12_dndi_gen7),
 746             NULL,
 747         },
 748
 749         gen7_pp_nv12_dndi_initialize,
 750     },
 751
 752     {
 753         {
 754             "NV12 DN module",
 755             PP_NV12_DN,
 756             pp_nv12_dn_gen7,
 757             sizeof(pp_nv12_dn_gen7),
 758             NULL,
 759         },
 760
 761         gen7_pp_nv12_dn_initialize,
 762     },
 763     {
 764         {
 765             "NV12_PA module",
 766             PP_NV12_LOAD_SAVE_PA,
 767             pp_nv12_load_save_pa_gen7,
 768             sizeof(pp_nv12_load_save_pa_gen7),
 769             NULL,
 770         },
 771
 772         gen7_pp_plx_avs_initialize,
 773     },
 774
 775     {
 776         {
 777             "PL3_PA module",
 778             PP_PL3_LOAD_SAVE_PA,
 779             pp_pl3_load_save_pa_gen7,
 780             sizeof(pp_pl3_load_save_pa_gen7),
 781             NULL,
 782         },
 783
 784         gen7_pp_plx_avs_initialize,
 785     },
 786
 787     {
 788         {
 789             "PA_NV12 module",
 790             PP_PA_LOAD_SAVE_NV12,
 791             pp_pa_load_save_nv12_gen7,
 792             sizeof(pp_pa_load_save_nv12_gen7),
 793             NULL,
 794         },
 795
 796         gen7_pp_plx_avs_initialize,
 797     },
 798
 799     {
 800         {
 801             "PA_PL3 module",
 802             PP_PA_LOAD_SAVE_PL3,
 803             pp_pa_load_save_pl3_gen7,
 804             sizeof(pp_pa_load_save_pl3_gen7),
 805             NULL,
 806         },
 807
 808         gen7_pp_plx_avs_initialize,
 809     },
 810
 811     {
 812         {
 813             "RGBX_NV12 module",
 814             PP_RGBX_LOAD_SAVE_NV12,
 815             pp_rgbx_load_save_nv12_gen7,
 816             sizeof(pp_rgbx_load_save_nv12_gen7),
 817             NULL,
 818         },
 819
 820         pp_plx_load_save_plx_initialize,
 821     },
 822
 823     {
 824         {
 825             "NV12_RGBX module",
 826             PP_NV12_LOAD_SAVE_RGBX,
 827             pp_nv12_load_save_rgbx_gen7,
 828             sizeof(pp_nv12_load_save_rgbx_gen7),
 829             NULL,
 830         },
 831
 832         pp_plx_load_save_plx_initialize,
 833     },
 834
 835 };
 836
 837 static int
 838 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 839 {
 840     struct i965_driver_data *i965 = i965_driver_data(ctx);
 841     int fourcc;
 842
 843     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 844         struct object_image *obj_image = IMAGE(surface->id);
 845         fourcc = obj_image->image.format.fourcc;
 846     } else {
 847         struct object_surface *obj_surface = SURFACE(surface->id);
 848         fourcc = obj_surface->fourcc;
 849     }
 850
 851     return fourcc;
 852 }
 853
 854 static void
 855 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 856 {
 857     switch (tiling) {
 858     case I915_TILING_NONE:
 859         ss->ss3.tiled_surface = 0;
 860         ss->ss3.tile_walk = 0;
 861         break;
 862     case I915_TILING_X:
 863         ss->ss3.tiled_surface = 1;
 864         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 865         break;
 866     case I915_TILING_Y:
 867         ss->ss3.tiled_surface = 1;
 868         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 869         break;
 870     }
 871 }
 872
 873 static void
 874 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 875 {
 876     switch (tiling) {
 877     case I915_TILING_NONE:
 878         ss->ss2.tiled_surface = 0;
 879         ss->ss2.tile_walk = 0;
 880         break;
 881     case I915_TILING_X:
 882         ss->ss2.tiled_surface = 1;
 883         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 884         break;
 885     case I915_TILING_Y:
 886         ss->ss2.tiled_surface = 1;
 887         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 888         break;
 889     }
 890 }
 891
 892 static void
 893 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 894 {
 895     switch (tiling) {
 896     case I915_TILING_NONE:
 897         ss->ss0.tiled_surface = 0;
 898         ss->ss0.tile_walk = 0;
 899         break;
 900     case I915_TILING_X:
 901         ss->ss0.tiled_surface = 1;
 902         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 903         break;
 904     case I915_TILING_Y:
 905         ss->ss0.tiled_surface = 1;
 906         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 907         break;
 908     }
 909 }
 910
 911 static void
 912 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 913 {
 914     switch (tiling) {
 915     case I915_TILING_NONE:
 916         ss->ss2.tiled_surface = 0;
 917         ss->ss2.tile_walk = 0;
 918         break;
 919     case I915_TILING_X:
 920         ss->ss2.tiled_surface = 1;
 921         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 922         break;
 923     case I915_TILING_Y:
 924         ss->ss2.tiled_surface = 1;
 925         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 926         break;
 927     }
 928 }
 929
 930 static void
 931 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 932 {
 933     struct i965_interface_descriptor *desc;
 934     dri_bo *bo;
 935     int pp_index = pp_context->current_pp;
 936
 937     bo = pp_context->idrt.bo;
 938     dri_bo_map(bo, 1);
 939     assert(bo->virtual);
 940     desc = bo->virtual;
 941     memset(desc, 0, sizeof(*desc));
 942     desc->desc0.grf_reg_blocks = 10;
 943     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 944     desc->desc1.const_urb_entry_read_offset = 0;
 945     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 946     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 947     desc->desc2.sampler_count = 0;
 948     desc->desc3.binding_table_entry_count = 0;
 949     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 950
 951     dri_bo_emit_reloc(bo,
 952                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 953                       desc->desc0.grf_reg_blocks,
 954                       offsetof(struct i965_interface_descriptor, desc0),
 955                       pp_context->pp_modules[pp_index].kernel.bo);
 956
 957     dri_bo_emit_reloc(bo,
 958                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 959                       desc->desc2.sampler_count << 2,
 960                       offsetof(struct i965_interface_descriptor, desc2),
 961                       pp_context->sampler_state_table.bo);
 962
 963     dri_bo_unmap(bo);
 964     pp_context->idrt.num_interface_descriptors++;
 965 }
 966
 967 static void
 968 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 969 {
 970     struct i965_vfe_state *vfe_state;
 971     dri_bo *bo;
 972
 973     bo = pp_context->vfe_state.bo;
 974     dri_bo_map(bo, 1);
 975     assert(bo->virtual);
 976     vfe_state = bo->virtual;
 977     memset(vfe_state, 0, sizeof(*vfe_state));
 978     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 979     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 980     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 981     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 982     vfe_state->vfe1.children_present = 0;
 983     vfe_state->vfe2.interface_descriptor_base =
 984         pp_context->idrt.bo->offset >> 4; /* reloc */
 985     dri_bo_emit_reloc(bo,
 986                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 987                       0,
 988                       offsetof(struct i965_vfe_state, vfe2),
 989                       pp_context->idrt.bo);
 990     dri_bo_unmap(bo);
 991 }
 992
 993 static void
 994 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 995 {
 996     unsigned char *constant_buffer;
 997     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 998
 999     assert(sizeof(*pp_static_parameter) == 128);
1000     dri_bo_map(pp_context->curbe.bo, 1);
1001     assert(pp_context->curbe.bo->virtual);
1002     constant_buffer = pp_context->curbe.bo->virtual;
1003     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
1004     dri_bo_unmap(pp_context->curbe.bo);
1005 }
1006
1007 static void
1008 ironlake_pp_states_setup(VADriverContextP ctx,
1009                          struct i965_post_processing_context *pp_context)
1010 {
1011     ironlake_pp_interface_descriptor_table(pp_context);
1012     ironlake_pp_vfe_state(pp_context);
1013     ironlake_pp_upload_constants(pp_context);
1014 }
1015
1016 static void
1017 ironlake_pp_pipeline_select(VADriverContextP ctx,
1018                             struct i965_post_processing_context *pp_context)
1019 {
1020     struct intel_batchbuffer *batch = pp_context->batch;
1021
1022     BEGIN_BATCH(batch, 1);
1023     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
1024     ADVANCE_BATCH(batch);
1025 }
1026
1027 static void
1028 ironlake_pp_urb_layout(VADriverContextP ctx,
1029                        struct i965_post_processing_context *pp_context)
1030 {
1031     struct intel_batchbuffer *batch = pp_context->batch;
1032     unsigned int vfe_fence, cs_fence;
1033
1034     vfe_fence = pp_context->urb.cs_start;
1035     cs_fence = pp_context->urb.size;
1036
1037     BEGIN_BATCH(batch, 3);
1038     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
1039     OUT_BATCH(batch, 0);
1040     OUT_BATCH(batch,
1041               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
1042               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
1043     ADVANCE_BATCH(batch);
1044 }
1045
1046 static void
1047 ironlake_pp_state_base_address(VADriverContextP ctx,
1048                                struct i965_post_processing_context *pp_context)
1049 {
1050     struct intel_batchbuffer *batch = pp_context->batch;
1051
1052     BEGIN_BATCH(batch, 8);
1053     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
1054     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1055     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
1056     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1057     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1058     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1059     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1060     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
1061     ADVANCE_BATCH(batch);
1062 }
1063
1064 static void
1065 ironlake_pp_state_pointers(VADriverContextP ctx,
1066                            struct i965_post_processing_context *pp_context)
1067 {
1068     struct intel_batchbuffer *batch = pp_context->batch;
1069
1070     BEGIN_BATCH(batch, 3);
1071     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
1072     OUT_BATCH(batch, 0);
1073     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
1074     ADVANCE_BATCH(batch);
1075 }
1076
1077 static void
1078 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
1079                           struct i965_post_processing_context *pp_context)
1080 {
1081     struct intel_batchbuffer *batch = pp_context->batch;
1082
1083     BEGIN_BATCH(batch, 2);
1084     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
1085     OUT_BATCH(batch,
1086               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
1087               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
1088     ADVANCE_BATCH(batch);
1089 }
1090
1091 static void
1092 ironlake_pp_constant_buffer(VADriverContextP ctx,
1093                             struct i965_post_processing_context *pp_context)
1094 {
1095     struct intel_batchbuffer *batch = pp_context->batch;
1096
1097     BEGIN_BATCH(batch, 2);
1098     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
1099     OUT_RELOC(batch, pp_context->curbe.bo,
1100               I915_GEM_DOMAIN_INSTRUCTION, 0,
1101               pp_context->urb.size_cs_entry - 1);
1102     ADVANCE_BATCH(batch);
1103 }
1104
1105 static void
1106 ironlake_pp_object_walker(VADriverContextP ctx,
1107                           struct i965_post_processing_context *pp_context)
1108 {
1109     struct intel_batchbuffer *batch = pp_context->batch;
1110     int x, x_steps, y, y_steps;
1111     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1112
1113     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
1114     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
1115
1116     for (y = 0; y < y_steps; y++) {
1117         for (x = 0; x < x_steps; x++) {
1118             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
1119                 BEGIN_BATCH(batch, 20);
1120                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
1121                 OUT_BATCH(batch, 0);
1122                 OUT_BATCH(batch, 0); /* no indirect data */
1123                 OUT_BATCH(batch, 0);
1124
1125                 /* inline data grf 5-6 */
1126                 assert(sizeof(*pp_inline_parameter) == 64);
1127                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
1128
1129                 ADVANCE_BATCH(batch);
1130             }
1131         }
1132     }
1133 }
1134
1135 static void
1136 ironlake_pp_pipeline_setup(VADriverContextP ctx,
1137                            struct i965_post_processing_context *pp_context)
1138 {
1139     struct intel_batchbuffer *batch = pp_context->batch;
1140
1141     intel_batchbuffer_start_atomic(batch, 0x1000);
1142     intel_batchbuffer_emit_mi_flush(batch);
1143     ironlake_pp_pipeline_select(ctx, pp_context);
1144     ironlake_pp_state_base_address(ctx, pp_context);
1145     ironlake_pp_state_pointers(ctx, pp_context);
1146     ironlake_pp_urb_layout(ctx, pp_context);
1147     ironlake_pp_cs_urb_layout(ctx, pp_context);
1148     ironlake_pp_constant_buffer(ctx, pp_context);
1149     ironlake_pp_object_walker(ctx, pp_context);
1150     intel_batchbuffer_end_atomic(batch);
1151 }
1152
1153 // update u/v offset when the surface format are packed yuv
1154 static void i965_update_src_surface_static_parameter(
1155     VADriverContextP    ctx,
1156     struct i965_post_processing_context *pp_context,
1157     const struct i965_surface *surface)
1158 {
1159     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1160     int fourcc = pp_get_surface_fourcc(ctx, surface);
1161
1162     switch (fourcc) {
1163     case VA_FOURCC('Y', 'U', 'Y', '2'):
1164         pp_static_parameter->grf1.source_packed_u_offset = 1;
1165         pp_static_parameter->grf1.source_packed_v_offset = 3;
1166         break;
1167     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1168         pp_static_parameter->grf1.source_packed_y_offset = 1;
1169         pp_static_parameter->grf1.source_packed_v_offset = 2;
1170         break;
1171     case VA_FOURCC('B', 'G', 'R', 'X'):
1172     case VA_FOURCC('B', 'G', 'R', 'A'):
1173         pp_static_parameter->grf1.source_rgb_layout = 0;
1174         break;
1175     case VA_FOURCC('R', 'G', 'B', 'X'):
1176     case VA_FOURCC('R', 'G', 'B', 'A'):
1177         pp_static_parameter->grf1.source_rgb_layout = 1;
1178         break;
1179     default:
1180         break;
1181     }
1182
1183 }
1184
1185 static void i965_update_dst_surface_static_parameter(
1186     VADriverContextP    ctx,
1187     struct i965_post_processing_context *pp_context,
1188     const struct i965_surface *surface)
1189 {
1190     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1191     int fourcc = pp_get_surface_fourcc(ctx, surface);
1192
1193     switch (fourcc) {
1194     case VA_FOURCC('Y', 'U', 'Y', '2'):
1195         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
1196         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
1197         break;
1198     case VA_FOURCC('U', 'Y', 'V', 'Y'):
1199         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
1200         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
1201         break;
1202     case VA_FOURCC('B', 'G', 'R', 'X'):
1203     case VA_FOURCC('B', 'G', 'R', 'A'):
1204         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 0;
1205         break;
1206     case VA_FOURCC('R', 'G', 'B', 'X'):
1207     case VA_FOURCC('R', 'G', 'B', 'A'):
1208         pp_static_parameter->grf1.r1_2.csc.destination_rgb_layout = 1;
1209         break;
1210     default:
1211         break;
1212     }
1213
1214 }
1215
1216 static void
1217 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1218                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1219                           int width, int height, int pitch, int format,
1220                           int index, int is_target)
1221 {
1222     struct i965_surface_state *ss;
1223     dri_bo *ss_bo;
1224     unsigned int tiling;
1225     unsigned int swizzle;
1226
1227     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1228     ss_bo = pp_context->surface_state_binding_table.bo;
1229     assert(ss_bo);
1230
1231     dri_bo_map(ss_bo, True);
1232     assert(ss_bo->virtual);
1233     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1234     memset(ss, 0, sizeof(*ss));
1235     ss->ss0.surface_type = I965_SURFACE_2D;
1236     ss->ss0.surface_format = format;
1237     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1238     ss->ss2.width = width - 1;
1239     ss->ss2.height = height - 1;
1240     ss->ss3.pitch = pitch - 1;
1241     pp_set_surface_tiling(ss, tiling);
1242     dri_bo_emit_reloc(ss_bo,
1243                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1244                       surf_bo_offset,
1245                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
1246                       surf_bo);
1247     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1248     dri_bo_unmap(ss_bo);
1249 }
1250
1251 static void
1252 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1253                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1254                            int width, int height, int wpitch,
1255                            int xoffset, int yoffset,
1256                            int format, int interleave_chroma,
1257                            int index)
1258 {
1259     struct i965_surface_state2 *ss2;
1260     dri_bo *ss2_bo;
1261     unsigned int tiling;
1262     unsigned int swizzle;
1263
1264     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1265     ss2_bo = pp_context->surface_state_binding_table.bo;
1266     assert(ss2_bo);
1267
1268     dri_bo_map(ss2_bo, True);
1269     assert(ss2_bo->virtual);
1270     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1271     memset(ss2, 0, sizeof(*ss2));
1272     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1273     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1274     ss2->ss1.width = width - 1;
1275     ss2->ss1.height = height - 1;
1276     ss2->ss2.pitch = wpitch - 1;
1277     ss2->ss2.interleave_chroma = interleave_chroma;
1278     ss2->ss2.surface_format = format;
1279     ss2->ss3.x_offset_for_cb = xoffset;
1280     ss2->ss3.y_offset_for_cb = yoffset;
1281     pp_set_surface2_tiling(ss2, tiling);
1282     dri_bo_emit_reloc(ss2_bo,
1283                       I915_GEM_DOMAIN_RENDER, 0,
1284                       surf_bo_offset,
1285                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
1286                       surf_bo);
1287     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1288     dri_bo_unmap(ss2_bo);
1289 }
1290
1291 static void
1292 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1293                           dri_bo *surf_bo, unsigned long surf_bo_offset,
1294                           int width, int height, int pitch, int format,
1295                           int index, int is_target)
1296 {
1297     struct gen7_surface_state *ss;
1298     dri_bo *ss_bo;
1299     unsigned int tiling;
1300     unsigned int swizzle;
1301
1302     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1303     ss_bo = pp_context->surface_state_binding_table.bo;
1304     assert(ss_bo);
1305
1306     dri_bo_map(ss_bo, True);
1307     assert(ss_bo->virtual);
1308     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1309     memset(ss, 0, sizeof(*ss));
1310     ss->ss0.surface_type = I965_SURFACE_2D;
1311     ss->ss0.surface_format = format;
1312     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1313     ss->ss2.width = width - 1;
1314     ss->ss2.height = height - 1;
1315     ss->ss3.pitch = pitch - 1;
1316     gen7_pp_set_surface_tiling(ss, tiling);
1317     dri_bo_emit_reloc(ss_bo,
1318                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1319                       surf_bo_offset,
1320                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1321                       surf_bo);
1322     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1323     dri_bo_unmap(ss_bo);
1324 }
1325
1326 static void
1327 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1328                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1329                            int width, int height, int wpitch,
1330                            int xoffset, int yoffset,
1331                            int format, int interleave_chroma,
1332                            int index)
1333 {
1334     struct gen7_surface_state2 *ss2;
1335     dri_bo *ss2_bo;
1336     unsigned int tiling;
1337     unsigned int swizzle;
1338
1339     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1340     ss2_bo = pp_context->surface_state_binding_table.bo;
1341     assert(ss2_bo);
1342
1343     dri_bo_map(ss2_bo, True);
1344     assert(ss2_bo->virtual);
1345     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1346     memset(ss2, 0, sizeof(*ss2));
1347     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1348     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1349     ss2->ss1.width = width - 1;
1350     ss2->ss1.height = height - 1;
1351     ss2->ss2.pitch = wpitch - 1;
1352     ss2->ss2.interleave_chroma = interleave_chroma;
1353     ss2->ss2.surface_format = format;
1354     ss2->ss3.x_offset_for_cb = xoffset;
1355     ss2->ss3.y_offset_for_cb = yoffset;
1356     gen7_pp_set_surface2_tiling(ss2, tiling);
1357     dri_bo_emit_reloc(ss2_bo,
1358                       I915_GEM_DOMAIN_RENDER, 0,
1359                       surf_bo_offset,
1360                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1361                       surf_bo);
1362     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1363     dri_bo_unmap(ss2_bo);
1364 }
1365
1366 static void
1367 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1368                                 const struct i965_surface *surface,
1369                                 int base_index, int is_target,
1370                                 int *width, int *height, int *pitch, int *offset)
1371 {
1372     struct i965_driver_data *i965 = i965_driver_data(ctx);
1373     struct object_surface *obj_surface;
1374     struct object_image *obj_image;
1375     dri_bo *bo;
1376     int fourcc = pp_get_surface_fourcc(ctx, surface);
1377     const int Y = 0;
1378     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1379     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1380     const int UV = 1;
1381     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1382     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1383     int full_packed_format = (fourcc == VA_FOURCC('R', 'G', 'B', 'A') ||
1384                               fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
1385                               fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
1386                               fourcc == VA_FOURCC('B', 'G', 'R', 'X'));
1387     int scale_factor_of_1st_plane_width_in_byte = 1;
1388
1389     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1390         obj_surface = SURFACE(surface->id);
1391         bo = obj_surface->bo;
1392         width[0] = obj_surface->orig_width;
1393         height[0] = obj_surface->orig_height;
1394         pitch[0] = obj_surface->width;
1395         offset[0] = 0;
1396
1397         if (full_packed_format) {
1398             scale_factor_of_1st_plane_width_in_byte = 4;
1399             pitch[0] = obj_surface->width * 4;
1400         }
1401         else if (packed_yuv ) {
1402             scale_factor_of_1st_plane_width_in_byte =  2;
1403             pitch[0] = obj_surface->width * 2;
1404         }
1405         else if (interleaved_uv) {
1406             width[1] = obj_surface->orig_width;
1407             height[1] = obj_surface->orig_height / 2;
1408             pitch[1] = obj_surface->width;
1409             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1410         } else {
1411             width[1] = obj_surface->orig_width / 2;
1412             height[1] = obj_surface->orig_height / 2;
1413             pitch[1] = obj_surface->width / 2;
1414             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1415             width[2] = obj_surface->orig_width / 2;
1416             height[2] = obj_surface->orig_height / 2;
1417             pitch[2] = obj_surface->width / 2;
1418             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1419         }
1420     } else {
1421         obj_image = IMAGE(surface->id);
1422         bo = obj_image->bo;
1423         width[0] = obj_image->image.width;
1424         height[0] = obj_image->image.height;
1425         pitch[0] = obj_image->image.pitches[0];
1426         offset[0] = obj_image->image.offsets[0];
1427
1428         if (full_packed_format) {
1429             scale_factor_of_1st_plane_width_in_byte = 4;
1430         }
1431         else if (packed_yuv ) {
1432             scale_factor_of_1st_plane_width_in_byte = 2;
1433         }
1434         else if (interleaved_uv) {
1435             width[1] = obj_image->image.width;
1436             height[1] = obj_image->image.height / 2;
1437             pitch[1] = obj_image->image.pitches[1];
1438             offset[1] = obj_image->image.offsets[1];
1439         } else {
1440             width[1] = obj_image->image.width / 2;
1441             height[1] = obj_image->image.height / 2;
1442             pitch[1] = obj_image->image.pitches[1];
1443             offset[1] = obj_image->image.offsets[1];
1444             width[2] = obj_image->image.width / 2;
1445             height[2] = obj_image->image.height / 2;
1446             pitch[2] = obj_image->image.pitches[2];
1447             offset[2] = obj_image->image.offsets[2];
1448         }
1449     }
1450
1451     /* Y surface */
1452     i965_pp_set_surface_state(ctx, pp_context,
1453                               bo, offset[Y],
1454                               width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1455                               base_index, is_target);
1456
1457     if (!packed_yuv && !full_packed_format) {
1458         if (interleaved_uv) {
1459             i965_pp_set_surface_state(ctx, pp_context,
1460                                       bo, offset[UV],
1461                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1462                                       base_index + 1, is_target);
1463         } else {
1464             /* U surface */
1465             i965_pp_set_surface_state(ctx, pp_context,
1466                                       bo, offset[U],
1467                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1468                                       base_index + 1, is_target);
1469
1470             /* V surface */
1471             i965_pp_set_surface_state(ctx, pp_context,
1472                                       bo, offset[V],
1473                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1474                                       base_index + 2, is_target);
1475         }
1476     }
1477
1478 }
1479
1480 static void
1481 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1482                                      const struct i965_surface *surface,
1483                                      int base_index, int is_target,
1484                                      int *width, int *height, int *pitch, int *offset)
1485 {
1486     struct i965_driver_data *i965 = i965_driver_data(ctx);
1487     struct object_surface *obj_surface;
1488     struct object_image *obj_image;
1489     dri_bo *bo;
1490     int fourcc = pp_get_surface_fourcc(ctx, surface);
1491     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1492                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1493     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1494                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1495     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1496     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1497
1498     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1499         obj_surface = SURFACE(surface->id);
1500         bo = obj_surface->bo;
1501         width[0] = obj_surface->orig_width;
1502         height[0] = obj_surface->orig_height;
1503         pitch[0] = obj_surface->width;
1504         offset[0] = 0;
1505
1506         if (packed_yuv) {
1507             if (is_target)
1508                 width[0] = obj_surface->orig_width * 2; /* surface format is R8, so double the width */
1509             else
1510                 width[0] = obj_surface->orig_width;     /* surface foramt is YCBCR, width is specified in units of pixels */
1511
1512             pitch[0] = obj_surface->width * 2;
1513         }
1514
1515         width[1] = obj_surface->cb_cr_width;
1516         height[1] = obj_surface->cb_cr_height;
1517         pitch[1] = obj_surface->cb_cr_pitch;
1518         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1519
1520         width[2] = obj_surface->cb_cr_width;
1521         height[2] = obj_surface->cb_cr_height;
1522         pitch[2] = obj_surface->cb_cr_pitch;
1523         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1524     } else {
1525         obj_image = IMAGE(surface->id);
1526         bo = obj_image->bo;
1527         width[0] = obj_image->image.width;
1528         height[0] = obj_image->image.height;
1529         pitch[0] = obj_image->image.pitches[0];
1530         offset[0] = obj_image->image.offsets[0];
1531
1532         if (packed_yuv) {
1533             if (is_target)
1534                 width[0] = obj_image->image.width * 2;  /* surface format is R8, so double the width */
1535             else
1536                 width[0] = obj_image->image.width;      /* surface foramt is YCBCR, width is specified in units of pixels */
1537         } else if (interleaved_uv) {
1538             width[1] = obj_image->image.width / 2;
1539             height[1] = obj_image->image.height / 2;
1540             pitch[1] = obj_image->image.pitches[1];
1541             offset[1] = obj_image->image.offsets[1];
1542         } else {
1543             width[1] = obj_image->image.width / 2;
1544             height[1] = obj_image->image.height / 2;
1545             pitch[1] = obj_image->image.pitches[U];
1546             offset[1] = obj_image->image.offsets[U];
1547             width[2] = obj_image->image.width / 2;
1548             height[2] = obj_image->image.height / 2;
1549             pitch[2] = obj_image->image.pitches[V];
1550             offset[2] = obj_image->image.offsets[V];
1551         }
1552     }
1553
1554     if (is_target) {
1555         gen7_pp_set_surface_state(ctx, pp_context,
1556                                   bo, 0,
1557                                   width[0] / 4, height[0], pitch[0],
1558                                   I965_SURFACEFORMAT_R8_SINT,
1559                                   base_index, 1);
1560
1561         if (!packed_yuv) {
1562             if (interleaved_uv) {
1563                 gen7_pp_set_surface_state(ctx, pp_context,
1564                                           bo, offset[1],
1565                                           width[1] / 2, height[1], pitch[1],
1566                                           I965_SURFACEFORMAT_R8G8_SINT,
1567                                           base_index + 1, 1);
1568             } else {
1569                 gen7_pp_set_surface_state(ctx, pp_context,
1570                                           bo, offset[1],
1571                                           width[1] / 4, height[1], pitch[1],
1572                                           I965_SURFACEFORMAT_R8_SINT,
1573                                           base_index + 1, 1);
1574                 gen7_pp_set_surface_state(ctx, pp_context,
1575                                           bo, offset[2],
1576                                           width[2] / 4, height[2], pitch[2],
1577                                           I965_SURFACEFORMAT_R8_SINT,
1578                                           base_index + 2, 1);
1579             }
1580         }
1581     } else {
1582         int format0 = SURFACE_FORMAT_Y8_UNORM;
1583
1584         switch (fourcc) {
1585         case VA_FOURCC('Y', 'U', 'Y', '2'):
1586             format0 = SURFACE_FORMAT_YCRCB_NORMAL;
1587             break;
1588
1589         case VA_FOURCC('U', 'Y', 'V', 'Y'):
1590             format0 = SURFACE_FORMAT_YCRCB_SWAPY;
1591             break;
1592
1593         default:
1594             break;
1595         }
1596
1597         gen7_pp_set_surface2_state(ctx, pp_context,
1598                                    bo, offset[0],
1599                                    width[0], height[0], pitch[0],
1600                                    0, 0,
1601                                    format0, 0,
1602                                    base_index);
1603
1604         if (!packed_yuv) {
1605             if (interleaved_uv) {
1606                 gen7_pp_set_surface2_state(ctx, pp_context,
1607                                            bo, offset[1],
1608                                            width[1], height[1], pitch[1],
1609                                            0, 0,
1610                                            SURFACE_FORMAT_R8B8_UNORM, 0,
1611                                            base_index + 1);
1612             } else {
1613                 gen7_pp_set_surface2_state(ctx, pp_context,
1614                                            bo, offset[1],
1615                                            width[1], height[1], pitch[1],
1616                                            0, 0,
1617                                            SURFACE_FORMAT_R8_UNORM, 0,
1618                                            base_index + 1);
1619                 gen7_pp_set_surface2_state(ctx, pp_context,
1620                                            bo, offset[2],
1621                                            width[2], height[2], pitch[2],
1622                                            0, 0,
1623                                            SURFACE_FORMAT_R8_UNORM, 0,
1624                                            base_index + 2);
1625             }
1626         }
1627     }
1628 }
1629
1630 static int
1631 pp_null_x_steps(void *private_context)
1632 {
1633     return 1;
1634 }
1635
1636 static int
1637 pp_null_y_steps(void *private_context)
1638 {
1639     return 1;
1640 }
1641
1642 static int
1643 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1644 {
1645     return 0;
1646 }
1647
1648 static VAStatus
1649 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1650                    const struct i965_surface *src_surface,
1651                    const VARectangle *src_rect,
1652                    struct i965_surface *dst_surface,
1653                    const VARectangle *dst_rect,
1654                    void *filter_param)
1655 {
1656     /* private function & data */
1657     pp_context->pp_x_steps = pp_null_x_steps;
1658     pp_context->pp_y_steps = pp_null_y_steps;
1659     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1660
1661     dst_surface->flags = src_surface->flags;
1662
1663     return VA_STATUS_SUCCESS;
1664 }
1665
1666 static int
1667 pp_load_save_x_steps(void *private_context)
1668 {
1669     return 1;
1670 }
1671
1672 static int
1673 pp_load_save_y_steps(void *private_context)
1674 {
1675     struct pp_load_save_context *pp_load_save_context = private_context;
1676
1677     return pp_load_save_context->dest_h / 8;
1678 }
1679
1680 static int
1681 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1682 {
1683     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1684
1685     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1686     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1687
1688     return 0;
1689 }
1690
1691 static void calculate_boundary_block_mask(struct i965_post_processing_context *pp_context, int width, int height)
1692 {
1693     #define BLOCK_WIDTH 16
1694     #define BLOCK_HEIGHT 8
1695     int i = 0;
1696     if (width%BLOCK_WIDTH){
1697         pp_context->block_horizontal_mask = (1 << (width%BLOCK_WIDTH)) - 1;
1698     }
1699     else {
1700         pp_context->block_horizontal_mask = 0xffff;
1701     }
1702
1703     if (height%BLOCK_HEIGHT){
1704         pp_context->block_vertical_mask = (1 << (height%BLOCK_HEIGHT)) - 1;
1705     }
1706     else {
1707         pp_context->block_vertical_mask = 0xff;
1708     }
1709
1710 }
1711 static VAStatus
1712 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1713                                 const struct i965_surface *src_surface,
1714                                 const VARectangle *src_rect,
1715                                 struct i965_surface *dst_surface,
1716                                 const VARectangle *dst_rect,
1717                                 void *filter_param)
1718 {
1719     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1720     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1721     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1722     int width[3], height[3], pitch[3], offset[3];
1723     const int Y = 0;
1724
1725     /* source surface */
1726     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1727                                     width, height, pitch, offset);
1728
1729     /* destination surface */
1730     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1731                                     width, height, pitch, offset);
1732
1733     /* private function & data */
1734     pp_context->pp_x_steps = pp_load_save_x_steps;
1735     pp_context->pp_y_steps = pp_load_save_y_steps;
1736     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1737     pp_load_save_context->dest_h = ALIGN(height[Y], 8);
1738     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1739
1740     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1741     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1742
1743     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1744     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1745
1746     // update u/v offset for packed yuv
1747     i965_update_src_surface_static_parameter (ctx, pp_context, src_surface);
1748     i965_update_dst_surface_static_parameter (ctx, pp_context, dst_surface);
1749
1750     dst_surface->flags = src_surface->flags;
1751
1752     return VA_STATUS_SUCCESS;
1753 }
1754
1755 static int
1756 pp_scaling_x_steps(void *private_context)
1757 {
1758     return 1;
1759 }
1760
1761 static int
1762 pp_scaling_y_steps(void *private_context)
1763 {
1764     struct pp_scaling_context *pp_scaling_context = private_context;
1765
1766     return pp_scaling_context->dest_h / 8;
1767 }
1768
1769 static int
1770 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1771 {
1772     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1773     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1774     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1775     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1776     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1777
1778     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1779     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1780     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1781     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1782
1783     return 0;
1784 }
1785
1786 static VAStatus
1787 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1788                            const struct i965_surface *src_surface,
1789                            const VARectangle *src_rect,
1790                            struct i965_surface *dst_surface,
1791                            const VARectangle *dst_rect,
1792                            void *filter_param)
1793 {
1794     struct i965_driver_data *i965 = i965_driver_data(ctx);
1795     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1796     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1797     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1798     struct object_surface *obj_surface;
1799     struct i965_sampler_state *sampler_state;
1800     int in_w, in_h, in_wpitch, in_hpitch;
1801     int out_w, out_h, out_wpitch, out_hpitch;
1802
1803     /* source surface */
1804     obj_surface = SURFACE(src_surface->id);
1805     in_w = obj_surface->orig_width;
1806     in_h = obj_surface->orig_height;
1807     in_wpitch = obj_surface->width;
1808     in_hpitch = obj_surface->height;
1809
1810     /* source Y surface index 1 */
1811     i965_pp_set_surface_state(ctx, pp_context,
1812                               obj_surface->bo, 0,
1813                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1814                               1, 0);
1815
1816     /* source UV surface index 2 */
1817     i965_pp_set_surface_state(ctx, pp_context,
1818                               obj_surface->bo, in_wpitch * in_hpitch,
1819                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1820                               2, 0);
1821
1822     /* destination surface */
1823     obj_surface = SURFACE(dst_surface->id);
1824     out_w = obj_surface->orig_width;
1825     out_h = obj_surface->orig_height;
1826     out_wpitch = obj_surface->width;
1827     out_hpitch = obj_surface->height;
1828
1829     /* destination Y surface index 7 */
1830     i965_pp_set_surface_state(ctx, pp_context,
1831                               obj_surface->bo, 0,
1832                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1833                               7, 1);
1834
1835     /* destination UV surface index 8 */
1836     i965_pp_set_surface_state(ctx, pp_context,
1837                               obj_surface->bo, out_wpitch * out_hpitch,
1838                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1839                               8, 1);
1840
1841     /* sampler state */
1842     dri_bo_map(pp_context->sampler_state_table.bo, True);
1843     assert(pp_context->sampler_state_table.bo->virtual);
1844     sampler_state = pp_context->sampler_state_table.bo->virtual;
1845
1846     /* SIMD16 Y index 1 */
1847     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1848     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1849     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1850     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1851     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1852
1853     /* SIMD16 UV index 2 */
1854     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1855     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1856     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1857     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1858     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1859
1860     dri_bo_unmap(pp_context->sampler_state_table.bo);
1861
1862     /* private function & data */
1863     pp_context->pp_x_steps = pp_scaling_x_steps;
1864     pp_context->pp_y_steps = pp_scaling_y_steps;
1865     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1866
1867     pp_scaling_context->dest_x = dst_rect->x;
1868     pp_scaling_context->dest_y = dst_rect->y;
1869     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1870     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1871     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1872     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1873
1874     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1875
1876     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1877     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1878     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1879
1880     dst_surface->flags = src_surface->flags;
1881
1882     return VA_STATUS_SUCCESS;
1883 }
1884
1885 static int
1886 pp_avs_x_steps(void *private_context)
1887 {
1888     struct pp_avs_context *pp_avs_context = private_context;
1889
1890     return pp_avs_context->dest_w / 16;
1891 }
1892
1893 static int
1894 pp_avs_y_steps(void *private_context)
1895 {
1896     return 1;
1897 }
1898
1899 static int
1900 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1901 {
1902     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1903     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1904     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1905     float src_x_steping, src_y_steping, video_step_delta;
1906     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1907
1908     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1909         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1910         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1911     } else if (tmp_w >= pp_avs_context->dest_w) {
1912         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1913         pp_inline_parameter->grf6.video_step_delta = 0;
1914
1915         if (x == 0) {
1916             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1917                 pp_avs_context->src_normalized_x;
1918         } else {
1919             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1920             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1921             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1922                 16 * 15 * video_step_delta / 2;
1923         }
1924     } else {
1925         int n0, n1, n2, nls_left, nls_right;
1926         int factor_a = 5, factor_b = 4;
1927         float f;
1928
1929         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1930         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1931         n2 = tmp_w / (16 * factor_a);
1932         nls_left = n0 + n2;
1933         nls_right = n1 + n2;
1934         f = (float) n2 * 16 / tmp_w;
1935
1936         if (n0 < 5) {
1937             pp_inline_parameter->grf6.video_step_delta = 0.0;
1938
1939             if (x == 0) {
1940                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1941                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1942             } else {
1943                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1944                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1945                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1946                     16 * 15 * video_step_delta / 2;
1947             }
1948         } else {
1949             if (x < nls_left) {
1950                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1951                 float a = f / (nls_left * 16 * factor_b);
1952                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1953
1954                 pp_inline_parameter->grf6.video_step_delta = b;
1955
1956                 if (x == 0) {
1957                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1958                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1959                 } else {
1960                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1961                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1962                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1963                         16 * 15 * video_step_delta / 2;
1964                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1965                 }
1966             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1967                 /* scale the center linearly */
1968                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1969                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1970                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1971                     16 * 15 * video_step_delta / 2;
1972                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1973                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1974             } else {
1975                 float a = f / (nls_right * 16 * factor_b);
1976                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1977
1978                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1979                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1980                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1981                     16 * 15 * video_step_delta / 2;
1982                 pp_inline_parameter->grf6.video_step_delta = -b;
1983
1984                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1985                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1986                 else
1987                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1988             }
1989         }
1990     }
1991
1992     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1993     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1994     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1995     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1996
1997     return 0;
1998 }
1999
2000 static VAStatus
2001 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2002                        const struct i965_surface *src_surface,
2003                        const VARectangle *src_rect,
2004                        struct i965_surface *dst_surface,
2005                        const VARectangle *dst_rect,
2006                        void *filter_param,
2007                        int nlas)
2008 {
2009     struct i965_driver_data *i965 = i965_driver_data(ctx);
2010     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2011     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2012     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2013     struct object_surface *obj_surface;
2014     struct i965_sampler_8x8 *sampler_8x8;
2015     struct i965_sampler_8x8_state *sampler_8x8_state;
2016     int index;
2017     int in_w, in_h, in_wpitch, in_hpitch;
2018     int out_w, out_h, out_wpitch, out_hpitch;
2019     int i;
2020
2021     /* surface */
2022     obj_surface = SURFACE(src_surface->id);
2023     in_w = obj_surface->orig_width;
2024     in_h = obj_surface->orig_height;
2025     in_wpitch = obj_surface->width;
2026     in_hpitch = obj_surface->height;
2027
2028     /* source Y surface index 1 */
2029     i965_pp_set_surface2_state(ctx, pp_context,
2030                                obj_surface->bo, 0,
2031                                in_w, in_h, in_wpitch,
2032                                0, 0,
2033                                SURFACE_FORMAT_Y8_UNORM, 0,
2034                                1);
2035
2036     /* source UV surface index 2 */
2037     i965_pp_set_surface2_state(ctx, pp_context,
2038                                obj_surface->bo, in_wpitch * in_hpitch,
2039                                in_w / 2, in_h / 2, in_wpitch,
2040                                0, 0,
2041                                SURFACE_FORMAT_R8B8_UNORM, 0,
2042                                2);
2043
2044     /* destination surface */
2045     obj_surface = SURFACE(dst_surface->id);
2046     out_w = obj_surface->orig_width;
2047     out_h = obj_surface->orig_height;
2048     out_wpitch = obj_surface->width;
2049     out_hpitch = obj_surface->height;
2050     assert(out_w <= out_wpitch && out_h <= out_hpitch);
2051
2052     /* destination Y surface index 7 */
2053     i965_pp_set_surface_state(ctx, pp_context,
2054                               obj_surface->bo, 0,
2055                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2056                               7, 1);
2057
2058     /* destination UV surface index 8 */
2059     i965_pp_set_surface_state(ctx, pp_context,
2060                               obj_surface->bo, out_wpitch * out_hpitch,
2061                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2062                               8, 1);
2063
2064     /* sampler 8x8 state */
2065     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2066     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2067     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2068     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2069     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2070
2071     for (i = 0; i < 17; i++) {
2072         /* for Y channel, currently ignore */
2073         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
2074         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
2075         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
2076         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
2077         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
2078         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
2079         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
2080         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
2081         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
2082         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
2083         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
2084         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
2085         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
2086         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
2087         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
2088         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
2089         /* for U/V channel, 0.25 */
2090         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2091         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2092         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2093         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2094         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2095         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2096         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2097         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2098         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2099         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2100         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2101         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2102         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2103         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2104         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2105         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2106     }
2107
2108     sampler_8x8_state->dw136.default_sharpness_level = 0;
2109     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2110     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2111     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2112     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2113
2114     /* sampler 8x8 */
2115     dri_bo_map(pp_context->sampler_state_table.bo, True);
2116     assert(pp_context->sampler_state_table.bo->virtual);
2117     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
2118     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2119
2120     /* sample_8x8 Y index 1 */
2121     index = 1;
2122     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2123     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2124     sampler_8x8[index].dw0.ief_bypass = 1;
2125     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2126     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2127     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2128     sampler_8x8[index].dw2.global_noise_estimation = 22;
2129     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2130     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2131     sampler_8x8[index].dw3.strong_edge_weight = 7;
2132     sampler_8x8[index].dw3.regular_weight = 2;
2133     sampler_8x8[index].dw3.non_edge_weight = 0;
2134     sampler_8x8[index].dw3.gain_factor = 40;
2135     sampler_8x8[index].dw4.steepness_boost = 0;
2136     sampler_8x8[index].dw4.steepness_threshold = 0;
2137     sampler_8x8[index].dw4.mr_boost = 0;
2138     sampler_8x8[index].dw4.mr_threshold = 5;
2139     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2140     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2141     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2142     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2143     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2144     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2145     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2146     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2147     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2148     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2149     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2150     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2151     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2152     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2153     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2154     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2155     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2156     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2157     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2158     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2159     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2160     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2161     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2162     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2163     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2164     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2165     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2166     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2167     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2168     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2169     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2170     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2171     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2172     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2173     sampler_8x8[index].dw13.limiter_boost = 0;
2174     sampler_8x8[index].dw13.minimum_limiter = 10;
2175     sampler_8x8[index].dw13.maximum_limiter = 11;
2176     sampler_8x8[index].dw14.clip_limiter = 130;
2177     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2178                       I915_GEM_DOMAIN_RENDER,
2179                       0,
2180                       0,
2181                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2182                       pp_context->sampler_state_table.bo_8x8);
2183
2184     /* sample_8x8 UV index 2 */
2185     index = 2;
2186     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2187     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
2188     sampler_8x8[index].dw0.ief_bypass = 1;
2189     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
2190     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
2191     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2192     sampler_8x8[index].dw2.global_noise_estimation = 22;
2193     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2194     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2195     sampler_8x8[index].dw3.strong_edge_weight = 7;
2196     sampler_8x8[index].dw3.regular_weight = 2;
2197     sampler_8x8[index].dw3.non_edge_weight = 0;
2198     sampler_8x8[index].dw3.gain_factor = 40;
2199     sampler_8x8[index].dw4.steepness_boost = 0;
2200     sampler_8x8[index].dw4.steepness_threshold = 0;
2201     sampler_8x8[index].dw4.mr_boost = 0;
2202     sampler_8x8[index].dw4.mr_threshold = 5;
2203     sampler_8x8[index].dw5.pwl1_point_1 = 4;
2204     sampler_8x8[index].dw5.pwl1_point_2 = 12;
2205     sampler_8x8[index].dw5.pwl1_point_3 = 16;
2206     sampler_8x8[index].dw5.pwl1_point_4 = 26;
2207     sampler_8x8[index].dw6.pwl1_point_5 = 40;
2208     sampler_8x8[index].dw6.pwl1_point_6 = 160;
2209     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
2210     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
2211     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
2212     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
2213     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
2214     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
2215     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
2216     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
2217     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
2218     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
2219     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
2220     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
2221     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
2222     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
2223     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
2224     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
2225     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
2226     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
2227     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
2228     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
2229     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
2230     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
2231     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
2232     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
2233     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
2234     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
2235     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
2236     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
2237     sampler_8x8[index].dw13.limiter_boost = 0;
2238     sampler_8x8[index].dw13.minimum_limiter = 10;
2239     sampler_8x8[index].dw13.maximum_limiter = 11;
2240     sampler_8x8[index].dw14.clip_limiter = 130;
2241     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2242                       I915_GEM_DOMAIN_RENDER,
2243                       0,
2244                       0,
2245                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2246                       pp_context->sampler_state_table.bo_8x8);
2247
2248     dri_bo_unmap(pp_context->sampler_state_table.bo);
2249
2250     /* private function & data */
2251     pp_context->pp_x_steps = pp_avs_x_steps;
2252     pp_context->pp_y_steps = pp_avs_y_steps;
2253     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
2254
2255     pp_avs_context->dest_x = dst_rect->x;
2256     pp_avs_context->dest_y = dst_rect->y;
2257     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2258     pp_avs_context->dest_h = ALIGN(dst_rect->height, 8);
2259     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
2260     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
2261     pp_avs_context->src_w = src_rect->width;
2262     pp_avs_context->src_h = src_rect->height;
2263
2264     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
2265     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
2266
2267     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
2268     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
2269     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
2270     pp_inline_parameter->grf6.video_step_delta = 0.0;
2271
2272     dst_surface->flags = src_surface->flags;
2273
2274     return VA_STATUS_SUCCESS;
2275 }
2276
2277 static VAStatus
2278 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2279                             const struct i965_surface *src_surface,
2280                             const VARectangle *src_rect,
2281                             struct i965_surface *dst_surface,
2282                             const VARectangle *dst_rect,
2283                             void *filter_param)
2284 {
2285     return pp_nv12_avs_initialize(ctx, pp_context,
2286                                   src_surface,
2287                                   src_rect,
2288                                   dst_surface,
2289                                   dst_rect,
2290                                   filter_param,
2291                                   1);
2292 }
2293
2294 static VAStatus
2295 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2296                              const struct i965_surface *src_surface,
2297                              const VARectangle *src_rect,
2298                              struct i965_surface *dst_surface,
2299                              const VARectangle *dst_rect,
2300                              void *filter_param)
2301 {
2302     return pp_nv12_avs_initialize(ctx, pp_context,
2303                                   src_surface,
2304                                   src_rect,
2305                                   dst_surface,
2306                                   dst_rect,
2307                                   filter_param,
2308                                   0);
2309 }
2310
2311 static int
2312 gen7_pp_avs_x_steps(void *private_context)
2313 {
2314     struct pp_avs_context *pp_avs_context = private_context;
2315
2316     return pp_avs_context->dest_w / 16;
2317 }
2318
2319 static int
2320 gen7_pp_avs_y_steps(void *private_context)
2321 {
2322     struct pp_avs_context *pp_avs_context = private_context;
2323
2324     return pp_avs_context->dest_h / 16;
2325 }
2326
2327 static int
2328 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2329 {
2330     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2331     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2332
2333     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
2334     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
2335     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
2336     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
2337
2338     return 0;
2339 }
2340
2341 static void gen7_update_src_surface_uv_offset(VADriverContextP    ctx,
2342                                               struct i965_post_processing_context *pp_context,
2343                                               const struct i965_surface *surface)
2344 {
2345     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2346     int fourcc = pp_get_surface_fourcc(ctx, surface);
2347
2348     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
2349         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2350         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2351         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2352     } else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
2353         pp_static_parameter->grf2.di_destination_packed_y_component_offset = 1;
2354         pp_static_parameter->grf2.di_destination_packed_u_component_offset = 0;
2355         pp_static_parameter->grf2.di_destination_packed_v_component_offset = 2;
2356     }
2357 }
2358
2359 static VAStatus
2360 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2361                            const struct i965_surface *src_surface,
2362                            const VARectangle *src_rect,
2363                            struct i965_surface *dst_surface,
2364                            const VARectangle *dst_rect,
2365                            void *filter_param)
2366 {
2367     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
2368     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2369     struct gen7_sampler_8x8 *sampler_8x8;
2370     struct i965_sampler_8x8_state *sampler_8x8_state;
2371     int index, i;
2372     int width[3], height[3], pitch[3], offset[3];
2373     int src_width, src_height;
2374
2375     /* source surface */
2376     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
2377                                          width, height, pitch, offset);
2378     src_width = width[0];
2379     src_height = height[0];
2380
2381     /* destination surface */
2382     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
2383                                          width, height, pitch, offset);
2384
2385     /* sampler 8x8 state */
2386     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2387     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2388     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2389     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2390     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2391
2392     for (i = 0; i < 17; i++) {
2393         /* for Y channel, currently ignore */
2394         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2395         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2396         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2397         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2398         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2399         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2400         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2401         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2402         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2403         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2404         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2405         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2406         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2407         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2408         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2409         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2410         /* for U/V channel, 0.25 */
2411         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2412         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2413         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2414         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2415         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2416         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2417         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2418         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2419         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2420         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2421         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2422         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2423         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2424         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2425         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2426         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2427     }
2428
2429     sampler_8x8_state->dw136.default_sharpness_level = 0;
2430     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2431     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2432     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2433     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2434
2435     /* sampler 8x8 */
2436     dri_bo_map(pp_context->sampler_state_table.bo, True);
2437     assert(pp_context->sampler_state_table.bo->virtual);
2438     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2439     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2440
2441     /* sample_8x8 Y index 4 */
2442     index = 4;
2443     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2444     sampler_8x8[index].dw0.global_noise_estimation = 255;
2445     sampler_8x8[index].dw0.ief_bypass = 1;
2446
2447     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2448
2449     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2450     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2451     sampler_8x8[index].dw2.r5x_coefficient = 9;
2452     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2453     sampler_8x8[index].dw2.r5c_coefficient = 3;
2454
2455     sampler_8x8[index].dw3.r3x_coefficient = 27;
2456     sampler_8x8[index].dw3.r3c_coefficient = 5;
2457     sampler_8x8[index].dw3.gain_factor = 40;
2458     sampler_8x8[index].dw3.non_edge_weight = 1;
2459     sampler_8x8[index].dw3.regular_weight = 2;
2460     sampler_8x8[index].dw3.strong_edge_weight = 7;
2461     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2462
2463     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2464                       I915_GEM_DOMAIN_RENDER,
2465                       0,
2466                       0,
2467                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2468                       pp_context->sampler_state_table.bo_8x8);
2469
2470     /* sample_8x8 UV index 8 */
2471     index = 8;
2472     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2473     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2474     sampler_8x8[index].dw0.global_noise_estimation = 255;
2475     sampler_8x8[index].dw0.ief_bypass = 1;
2476     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2477     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2478     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2479     sampler_8x8[index].dw2.r5x_coefficient = 9;
2480     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2481     sampler_8x8[index].dw2.r5c_coefficient = 3;
2482     sampler_8x8[index].dw3.r3x_coefficient = 27;
2483     sampler_8x8[index].dw3.r3c_coefficient = 5;
2484     sampler_8x8[index].dw3.gain_factor = 40;
2485     sampler_8x8[index].dw3.non_edge_weight = 1;
2486     sampler_8x8[index].dw3.regular_weight = 2;
2487     sampler_8x8[index].dw3.strong_edge_weight = 7;
2488     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2489
2490     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2491                       I915_GEM_DOMAIN_RENDER,
2492                       0,
2493                       0,
2494                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2495                       pp_context->sampler_state_table.bo_8x8);
2496
2497     /* sampler_8x8 V, index 12 */
2498     index = 12;
2499     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2500     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2501     sampler_8x8[index].dw0.global_noise_estimation = 255;
2502     sampler_8x8[index].dw0.ief_bypass = 1;
2503     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2504     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2505     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2506     sampler_8x8[index].dw2.r5x_coefficient = 9;
2507     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2508     sampler_8x8[index].dw2.r5c_coefficient = 3;
2509     sampler_8x8[index].dw3.r3x_coefficient = 27;
2510     sampler_8x8[index].dw3.r3c_coefficient = 5;
2511     sampler_8x8[index].dw3.gain_factor = 40;
2512     sampler_8x8[index].dw3.non_edge_weight = 1;
2513     sampler_8x8[index].dw3.regular_weight = 2;
2514     sampler_8x8[index].dw3.strong_edge_weight = 7;
2515     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2516
2517     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2518                       I915_GEM_DOMAIN_RENDER,
2519                       0,
2520                       0,
2521                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2522                       pp_context->sampler_state_table.bo_8x8);
2523
2524     dri_bo_unmap(pp_context->sampler_state_table.bo);
2525
2526     /* private function & data */
2527     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2528     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2529     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2530
2531     pp_avs_context->dest_x = dst_rect->x;
2532     pp_avs_context->dest_y = dst_rect->y;
2533     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2534     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2535     pp_avs_context->src_w = src_rect->width;
2536     pp_avs_context->src_h = src_rect->height;
2537
2538     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2539     dw = MAX(dw, pp_avs_context->dest_w);
2540
2541     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2542     pp_static_parameter->grf2.avs_wa_enable = 1; /* must be set for GEN7 */
2543     pp_static_parameter->grf2.avs_wa_width = dw;
2544     pp_static_parameter->grf2.avs_wa_one_div_256_width = (float) 1.0 / (256 * dw);
2545     pp_static_parameter->grf2.avs_wa_five_div_256_width = (float) 5.0 / (256 * dw);
2546
2547     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2548     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) src_rect->height / src_height / pp_avs_context->dest_h;
2549     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2550     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2551
2552     gen7_update_src_surface_uv_offset(ctx, pp_context, dst_surface);
2553
2554     dst_surface->flags = src_surface->flags;
2555
2556     return VA_STATUS_SUCCESS;
2557 }
2558
2559 static int
2560 pp_dndi_x_steps(void *private_context)
2561 {
2562     return 1;
2563 }
2564
2565 static int
2566 pp_dndi_y_steps(void *private_context)
2567 {
2568     struct pp_dndi_context *pp_dndi_context = private_context;
2569
2570     return pp_dndi_context->dest_h / 4;
2571 }
2572
2573 static int
2574 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2575 {
2576     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2577
2578     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2579     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2580
2581     return 0;
2582 }
2583
2584 static VAStatus
2585 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2586                         const struct i965_surface *src_surface,
2587                         const VARectangle *src_rect,
2588                         struct i965_surface *dst_surface,
2589                         const VARectangle *dst_rect,
2590                         void *filter_param)
2591 {
2592     struct i965_driver_data *i965 = i965_driver_data(ctx);
2593     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2594     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2595     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2596     struct object_surface *obj_surface;
2597     struct i965_sampler_dndi *sampler_dndi;
2598     int index;
2599     int w, h;
2600     int orig_w, orig_h;
2601     int dndi_top_first = 1;
2602
2603     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2604         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2605
2606     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2607         dndi_top_first = 1;
2608     else
2609         dndi_top_first = 0;
2610
2611     /* surface */
2612     obj_surface = SURFACE(src_surface->id);
2613     orig_w = obj_surface->orig_width;
2614     orig_h = obj_surface->orig_height;
2615     w = obj_surface->width;
2616     h = obj_surface->height;
2617
2618     if (pp_context->stmm.bo == NULL) {
2619         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2620                                            "STMM surface",
2621                                            w * h,
2622                                            4096);
2623         assert(pp_context->stmm.bo);
2624     }
2625
2626     /* source UV surface index 2 */
2627     i965_pp_set_surface_state(ctx, pp_context,
2628                               obj_surface->bo, w * h,
2629                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2630                               2, 0);
2631
2632     /* source YUV surface index 4 */
2633     i965_pp_set_surface2_state(ctx, pp_context,
2634                                obj_surface->bo, 0,
2635                                orig_w, orig_h, w,
2636                                0, h,
2637                                SURFACE_FORMAT_PLANAR_420_8, 1,
2638                                4);
2639
2640     /* source STMM surface index 20 */
2641     i965_pp_set_surface_state(ctx, pp_context,
2642                               pp_context->stmm.bo, 0,
2643                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2644                               20, 1);
2645
2646     /* destination surface */
2647     obj_surface = SURFACE(dst_surface->id);
2648     orig_w = obj_surface->orig_width;
2649     orig_h = obj_surface->orig_height;
2650     w = obj_surface->width;
2651     h = obj_surface->height;
2652
2653     /* destination Y surface index 7 */
2654     i965_pp_set_surface_state(ctx, pp_context,
2655                               obj_surface->bo, 0,
2656                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2657                               7, 1);
2658
2659     /* destination UV surface index 8 */
2660     i965_pp_set_surface_state(ctx, pp_context,
2661                               obj_surface->bo, w * h,
2662                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2663                               8, 1);
2664     /* sampler dndi */
2665     dri_bo_map(pp_context->sampler_state_table.bo, True);
2666     assert(pp_context->sampler_state_table.bo->virtual);
2667     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2668     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2669
2670     /* sample dndi index 1 */
2671     index = 0;
2672     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2673     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2674     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2675     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2676
2677     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2678     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2679     sampler_dndi[index].dw1.stmm_c2 = 1;
2680     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2681     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2682
2683     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2684     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2685     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2686     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2687
2688     sampler_dndi[index].dw3.maximum_stmm = 128;
2689     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2690     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2691     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2692     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2693
2694     sampler_dndi[index].dw4.sdi_delta = 8;
2695     sampler_dndi[index].dw4.sdi_threshold = 128;
2696     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2697     sampler_dndi[index].dw4.stmm_shift_up = 0;
2698     sampler_dndi[index].dw4.stmm_shift_down = 0;
2699     sampler_dndi[index].dw4.minimum_stmm = 0;
2700
2701     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2702     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2703     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2704     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2705
2706     sampler_dndi[index].dw6.dn_enable = 1;
2707     sampler_dndi[index].dw6.di_enable = 1;
2708     sampler_dndi[index].dw6.di_partial = 0;
2709     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2710     sampler_dndi[index].dw6.dndi_stream_id = 0;
2711     sampler_dndi[index].dw6.dndi_first_frame = 1;
2712     sampler_dndi[index].dw6.progressive_dn = 0;
2713     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2714     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2715     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2716
2717     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2718     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2719     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2720     sampler_dndi[index].dw7.column_width_minus1 = 0;
2721
2722     dri_bo_unmap(pp_context->sampler_state_table.bo);
2723
2724     /* private function & data */
2725     pp_context->pp_x_steps = pp_dndi_x_steps;
2726     pp_context->pp_y_steps = pp_dndi_y_steps;
2727     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2728
2729     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2730     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2731     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2732     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2733
2734     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2735     pp_inline_parameter->grf5.number_blocks = w / 16;
2736     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2737     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2738
2739     pp_dndi_context->dest_w = w;
2740     pp_dndi_context->dest_h = h;
2741
2742     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2743
2744     return VA_STATUS_SUCCESS;
2745 }
2746
2747 static int
2748 pp_dn_x_steps(void *private_context)
2749 {
2750     return 1;
2751 }
2752
2753 static int
2754 pp_dn_y_steps(void *private_context)
2755 {
2756     struct pp_dn_context *pp_dn_context = private_context;
2757
2758     return pp_dn_context->dest_h / 8;
2759 }
2760
2761 static int
2762 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2763 {
2764     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2765
2766     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2767     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2768
2769     return 0;
2770 }
2771
2772 static VAStatus
2773 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2774                       const struct i965_surface *src_surface,
2775                       const VARectangle *src_rect,
2776                       struct i965_surface *dst_surface,
2777                       const VARectangle *dst_rect,
2778                       void *filter_param)
2779 {
2780     struct i965_driver_data *i965 = i965_driver_data(ctx);
2781     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2782     struct object_surface *obj_surface;
2783     struct i965_sampler_dndi *sampler_dndi;
2784     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2785     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2786     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2787     int index;
2788     int w, h;
2789     int orig_w, orig_h;
2790     int dn_strength = 15;
2791     int dndi_top_first = 1;
2792     int dn_progressive = 0;
2793
2794     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2795         dndi_top_first = 1;
2796         dn_progressive = 1;
2797     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2798         dndi_top_first = 1;
2799         dn_progressive = 0;
2800     } else {
2801         dndi_top_first = 0;
2802         dn_progressive = 0;
2803     }
2804
2805     if (dn_filter_param) {
2806         float value = dn_filter_param->value;
2807
2808         if (value > 1.0)
2809             value = 1.0;
2810
2811         if (value < 0.0)
2812             value = 0.0;
2813
2814         dn_strength = (int)(value * 31.0F);
2815     }
2816
2817     /* surface */
2818     obj_surface = SURFACE(src_surface->id);
2819     orig_w = obj_surface->orig_width;
2820     orig_h = obj_surface->orig_height;
2821     w = obj_surface->width;
2822     h = obj_surface->height;
2823
2824     if (pp_context->stmm.bo == NULL) {
2825         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2826                                            "STMM surface",
2827                                            w * h,
2828                                            4096);
2829         assert(pp_context->stmm.bo);
2830     }
2831
2832     /* source UV surface index 2 */
2833     i965_pp_set_surface_state(ctx, pp_context,
2834                               obj_surface->bo, w * h,
2835                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2836                               2, 0);
2837
2838     /* source YUV surface index 4 */
2839     i965_pp_set_surface2_state(ctx, pp_context,
2840                                obj_surface->bo, 0,
2841                                orig_w, orig_h, w,
2842                                0, h,
2843                                SURFACE_FORMAT_PLANAR_420_8, 1,
2844                                4);
2845
2846     /* source STMM surface index 20 */
2847     i965_pp_set_surface_state(ctx, pp_context,
2848                               pp_context->stmm.bo, 0,
2849                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2850                               20, 1);
2851
2852     /* destination surface */
2853     obj_surface = SURFACE(dst_surface->id);
2854     orig_w = obj_surface->orig_width;
2855     orig_h = obj_surface->orig_height;
2856     w = obj_surface->width;
2857     h = obj_surface->height;
2858
2859     /* destination Y surface index 7 */
2860     i965_pp_set_surface_state(ctx, pp_context,
2861                               obj_surface->bo, 0,
2862                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2863                               7, 1);
2864
2865     /* destination UV surface index 8 */
2866     i965_pp_set_surface_state(ctx, pp_context,
2867                               obj_surface->bo, w * h,
2868                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2869                               8, 1);
2870     /* sampler dn */
2871     dri_bo_map(pp_context->sampler_state_table.bo, True);
2872     assert(pp_context->sampler_state_table.bo->virtual);
2873     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2874     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2875
2876     /* sample dndi index 1 */
2877     index = 0;
2878     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2879     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2880     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2881     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2882
2883     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2884     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2885     sampler_dndi[index].dw1.stmm_c2 = 0;
2886     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2887     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2888
2889     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2890     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2891     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2892     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2893
2894     sampler_dndi[index].dw3.maximum_stmm = 128;
2895     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2896     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2897     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2898     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2899
2900     sampler_dndi[index].dw4.sdi_delta = 8;
2901     sampler_dndi[index].dw4.sdi_threshold = 128;
2902     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2903     sampler_dndi[index].dw4.stmm_shift_up = 0;
2904     sampler_dndi[index].dw4.stmm_shift_down = 0;
2905     sampler_dndi[index].dw4.minimum_stmm = 0;
2906
2907     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2908     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2909     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2910     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2911
2912     sampler_dndi[index].dw6.dn_enable = 1;
2913     sampler_dndi[index].dw6.di_enable = 0;
2914     sampler_dndi[index].dw6.di_partial = 0;
2915     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2916     sampler_dndi[index].dw6.dndi_stream_id = 1;
2917     sampler_dndi[index].dw6.dndi_first_frame = 1;
2918     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2919     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2920     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2921     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2922
2923     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2924     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2925     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2926     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2927
2928     dri_bo_unmap(pp_context->sampler_state_table.bo);
2929
2930     /* private function & data */
2931     pp_context->pp_x_steps = pp_dn_x_steps;
2932     pp_context->pp_y_steps = pp_dn_y_steps;
2933     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2934
2935     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2936     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2937     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2938     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2939
2940     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2941     pp_inline_parameter->grf5.number_blocks = w / 16;
2942     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2943     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2944
2945     pp_dn_context->dest_w = w;
2946     pp_dn_context->dest_h = h;
2947
2948     dst_surface->flags = src_surface->flags;
2949
2950     return VA_STATUS_SUCCESS;
2951 }
2952
2953 static int
2954 gen7_pp_dndi_x_steps(void *private_context)
2955 {
2956     struct pp_dndi_context *pp_dndi_context = private_context;
2957
2958     return pp_dndi_context->dest_w / 16;
2959 }
2960
2961 static int
2962 gen7_pp_dndi_y_steps(void *private_context)
2963 {
2964     struct pp_dndi_context *pp_dndi_context = private_context;
2965
2966     return pp_dndi_context->dest_h / 4;
2967 }
2968
2969 static int
2970 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2971 {
2972     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2973
2974     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2975     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2976
2977     return 0;
2978 }
2979
2980 static VAStatus
2981 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2982                              const struct i965_surface *src_surface,
2983                              const VARectangle *src_rect,
2984                              struct i965_surface *dst_surface,
2985                              const VARectangle *dst_rect,
2986                              void *filter_param)
2987 {
2988     struct i965_driver_data *i965 = i965_driver_data(ctx);
2989     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2990     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2991     struct object_surface *obj_surface;
2992     struct gen7_sampler_dndi *sampler_dndi;
2993     int index;
2994     int w, h;
2995     int orig_w, orig_h;
2996     int dndi_top_first = 1;
2997
2998     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2999         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
3000
3001     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
3002         dndi_top_first = 1;
3003     else
3004         dndi_top_first = 0;
3005
3006     /* surface */
3007     obj_surface = SURFACE(src_surface->id);
3008     orig_w = obj_surface->orig_width;
3009     orig_h = obj_surface->orig_height;
3010     w = obj_surface->width;
3011     h = obj_surface->height;
3012
3013     if (pp_context->stmm.bo == NULL) {
3014         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3015                                            "STMM surface",
3016                                            w * h,
3017                                            4096);
3018         assert(pp_context->stmm.bo);
3019     }
3020
3021     /* source UV surface index 1 */
3022     gen7_pp_set_surface_state(ctx, pp_context,
3023                               obj_surface->bo, w * h,
3024                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3025                               1, 0);
3026
3027     /* source YUV surface index 3 */
3028     gen7_pp_set_surface2_state(ctx, pp_context,
3029                                obj_surface->bo, 0,
3030                                orig_w, orig_h, w,
3031                                0, h,
3032                                SURFACE_FORMAT_PLANAR_420_8, 1,
3033                                3);
3034
3035     /* source (temporal reference) YUV surface index 4 */
3036     gen7_pp_set_surface2_state(ctx, pp_context,
3037                                obj_surface->bo, 0,
3038                                orig_w, orig_h, w,
3039                                0, h,
3040                                SURFACE_FORMAT_PLANAR_420_8, 1,
3041                                4);
3042
3043     /* STMM / History Statistics input surface, index 5 */
3044     gen7_pp_set_surface_state(ctx, pp_context,
3045                               pp_context->stmm.bo, 0,
3046                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3047                               5, 1);
3048
3049     /* destination surface */
3050     obj_surface = SURFACE(dst_surface->id);
3051     orig_w = obj_surface->orig_width;
3052     orig_h = obj_surface->orig_height;
3053     w = obj_surface->width;
3054     h = obj_surface->height;
3055
3056     /* destination(Previous frame) Y surface index 27 */
3057     gen7_pp_set_surface_state(ctx, pp_context,
3058                               obj_surface->bo, 0,
3059                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3060                               27, 1);
3061
3062     /* destination(Previous frame) UV surface index 28 */
3063     gen7_pp_set_surface_state(ctx, pp_context,
3064                               obj_surface->bo, w * h,
3065                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3066                               28, 1);
3067
3068     /* destination(Current frame) Y surface index 30 */
3069     gen7_pp_set_surface_state(ctx, pp_context,
3070                               obj_surface->bo, 0,
3071                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3072                               30, 1);
3073
3074     /* destination(Current frame) UV surface index 31 */
3075     gen7_pp_set_surface_state(ctx, pp_context,
3076                               obj_surface->bo, w * h,
3077                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3078                               31, 1);
3079
3080     /* STMM output surface, index 33 */
3081     gen7_pp_set_surface_state(ctx, pp_context,
3082                               pp_context->stmm.bo, 0,
3083                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3084                               33, 1);
3085
3086
3087     /* sampler dndi */
3088     dri_bo_map(pp_context->sampler_state_table.bo, True);
3089     assert(pp_context->sampler_state_table.bo->virtual);
3090     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
3091     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
3092
3093     /* sample dndi index 0 */
3094     index = 0;
3095     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
3096     sampler_dndi[index].dw0.dnmh_delt = 8;
3097     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
3098     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
3099     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
3100     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
3101
3102     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3103     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
3104     sampler_dndi[index].dw1.stmm_c2 = 0;
3105     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
3106     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
3107
3108     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
3109     sampler_dndi[index].dw2.bne_edge_th = 1;
3110     sampler_dndi[index].dw2.smooth_mv_th = 0;
3111     sampler_dndi[index].dw2.sad_tight_th = 5;
3112     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
3113     sampler_dndi[index].dw2.good_neighbor_th = 4;
3114
3115     sampler_dndi[index].dw3.maximum_stmm = 128;
3116     sampler_dndi[index].dw3.multipler_for_vecm = 2;
3117     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3118     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3119     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
3120
3121     sampler_dndi[index].dw4.sdi_delta = 8;
3122     sampler_dndi[index].dw4.sdi_threshold = 128;
3123     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3124     sampler_dndi[index].dw4.stmm_shift_up = 0;
3125     sampler_dndi[index].dw4.stmm_shift_down = 0;
3126     sampler_dndi[index].dw4.minimum_stmm = 0;
3127
3128     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
3129     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
3130     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3131     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3132
3133     sampler_dndi[index].dw6.dn_enable = 0;
3134     sampler_dndi[index].dw6.di_enable = 1;
3135     sampler_dndi[index].dw6.di_partial = 0;
3136     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
3137     sampler_dndi[index].dw6.dndi_stream_id = 1;
3138     sampler_dndi[index].dw6.dndi_first_frame = 1;
3139     sampler_dndi[index].dw6.progressive_dn = 0;
3140     sampler_dndi[index].dw6.mcdi_enable = 0;
3141     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
3142     sampler_dndi[index].dw6.cat_th1 = 0;
3143     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
3144     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
3145
3146     sampler_dndi[index].dw7.sad_tha = 5;
3147     sampler_dndi[index].dw7.sad_thb = 10;
3148     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
3149     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
3150     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
3151     sampler_dndi[index].dw7.vdi_walker_enable = 0;
3152     sampler_dndi[index].dw7.neighborpixel_th = 10;
3153     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
3154
3155     dri_bo_unmap(pp_context->sampler_state_table.bo);
3156
3157     /* private function & data */
3158     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
3159     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
3160     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
3161
3162     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3163     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3164     pp_static_parameter->grf1.di_top_field_first = 0;
3165     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3166
3167     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3168     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3169     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3170
3171     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3172     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3173
3174     pp_dndi_context->dest_w = w;
3175     pp_dndi_context->dest_h = h;
3176
3177     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
3178
3179     return VA_STATUS_SUCCESS;
3180 }
3181
3182 static int
3183 gen7_pp_dn_x_steps(void *private_context)
3184 {
3185     struct pp_dn_context *pp_dn_context = private_context;
3186
3187     return pp_dn_context->dest_w / 16;
3188 }
3189
3190 static int
3191 gen7_pp_dn_y_steps(void *private_context)
3192 {
3193     struct pp_dn_context *pp_dn_context = private_context;
3194
3195     return pp_dn_context->dest_h / 4;
3196 }
3197
3198 static int
3199 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
3200 {
3201     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3202
3203     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
3204     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
3205
3206     return 0;
3207 }
3208
3209 static VAStatus
3210 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
3211                            const struct i965_surface *src_surface,
3212                            const VARectangle *src_rect,
3213                            struct i965_surface *dst_surface,
3214                            const VARectangle *dst_rect,
3215                            void *filter_param)
3216 {
3217     struct i965_driver_data *i965 = i965_driver_data(ctx);
3218     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
3219     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3220     struct object_surface *obj_surface;
3221     struct gen7_sampler_dndi *sampler_dn;
3222     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
3223     int index;
3224     int w, h;
3225     int orig_w, orig_h;
3226     int dn_strength = 15;
3227     int dndi_top_first = 1;
3228     int dn_progressive = 0;
3229
3230     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
3231         dndi_top_first = 1;
3232         dn_progressive = 1;
3233     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
3234         dndi_top_first = 1;
3235         dn_progressive = 0;
3236     } else {
3237         dndi_top_first = 0;
3238         dn_progressive = 0;
3239     }
3240
3241     if (dn_filter_param) {
3242         float value = dn_filter_param->value;
3243
3244         if (value > 1.0)
3245             value = 1.0;
3246
3247         if (value < 0.0)
3248             value = 0.0;
3249
3250         dn_strength = (int)(value * 31.0F);
3251     }
3252
3253     /* surface */
3254     obj_surface = SURFACE(src_surface->id);
3255     orig_w = obj_surface->orig_width;
3256     orig_h = obj_surface->orig_height;
3257     w = obj_surface->width;
3258     h = obj_surface->height;
3259
3260     if (pp_context->stmm.bo == NULL) {
3261         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
3262                                            "STMM surface",
3263                                            w * h,
3264                                            4096);
3265         assert(pp_context->stmm.bo);
3266     }
3267
3268     /* source UV surface index 1 */
3269     gen7_pp_set_surface_state(ctx, pp_context,
3270                               obj_surface->bo, w * h,
3271                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3272                               1, 0);
3273
3274     /* source YUV surface index 3 */
3275     gen7_pp_set_surface2_state(ctx, pp_context,
3276                                obj_surface->bo, 0,
3277                                orig_w, orig_h, w,
3278                                0, h,
3279                                SURFACE_FORMAT_PLANAR_420_8, 1,
3280                                3);
3281
3282     /* source (temporal reference) YUV surface index 4 */
3283     gen7_pp_set_surface2_state(ctx, pp_context,
3284                                obj_surface->bo, 0,
3285                                orig_w, orig_h, w,
3286                                0, h,
3287                                SURFACE_FORMAT_PLANAR_420_8, 1,
3288                                4);
3289
3290     /* STMM / History Statistics input surface, index 5 */
3291     gen7_pp_set_surface_state(ctx, pp_context,
3292                               pp_context->stmm.bo, 0,
3293                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3294                               5, 1);
3295
3296     /* destination surface */
3297     obj_surface = SURFACE(dst_surface->id);
3298     orig_w = obj_surface->orig_width;
3299     orig_h = obj_surface->orig_height;
3300     w = obj_surface->width;
3301     h = obj_surface->height;
3302
3303     /* destination Y surface index 24 */
3304     gen7_pp_set_surface_state(ctx, pp_context,
3305                               obj_surface->bo, 0,
3306                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3307                               24, 1);
3308
3309     /* destination UV surface index 25 */
3310     gen7_pp_set_surface_state(ctx, pp_context,
3311                               obj_surface->bo, w * h,
3312                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3313                               25, 1);
3314
3315     /* sampler dn */
3316     dri_bo_map(pp_context->sampler_state_table.bo, True);
3317     assert(pp_context->sampler_state_table.bo->virtual);
3318     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
3319     sampler_dn = pp_context->sampler_state_table.bo->virtual;
3320
3321     /* sample dn index 1 */
3322     index = 0;
3323     sampler_dn[index].dw0.denoise_asd_threshold = 0;
3324     sampler_dn[index].dw0.dnmh_delt = 8;
3325     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
3326     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
3327     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
3328     sampler_dn[index].dw0.denoise_stad_threshold = 0;
3329
3330     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
3331     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
3332     sampler_dn[index].dw1.stmm_c2 = 0;
3333     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
3334     sampler_dn[index].dw1.temporal_difference_threshold = 16;
3335
3336     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
3337     sampler_dn[index].dw2.bne_edge_th = 1;
3338     sampler_dn[index].dw2.smooth_mv_th = 0;
3339     sampler_dn[index].dw2.sad_tight_th = 5;
3340     sampler_dn[index].dw2.cat_slope_minus1 = 9;
3341     sampler_dn[index].dw2.good_neighbor_th = 4;
3342
3343     sampler_dn[index].dw3.maximum_stmm = 128;
3344     sampler_dn[index].dw3.multipler_for_vecm = 2;
3345     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
3346     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
3347     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
3348
3349     sampler_dn[index].dw4.sdi_delta = 8;
3350     sampler_dn[index].dw4.sdi_threshold = 128;
3351     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
3352     sampler_dn[index].dw4.stmm_shift_up = 0;
3353     sampler_dn[index].dw4.stmm_shift_down = 0;
3354     sampler_dn[index].dw4.minimum_stmm = 0;
3355
3356     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
3357     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
3358     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
3359     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
3360
3361     sampler_dn[index].dw6.dn_enable = 1;
3362     sampler_dn[index].dw6.di_enable = 0;
3363     sampler_dn[index].dw6.di_partial = 0;
3364     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
3365     sampler_dn[index].dw6.dndi_stream_id = 1;
3366     sampler_dn[index].dw6.dndi_first_frame = 1;
3367     sampler_dn[index].dw6.progressive_dn = dn_progressive;
3368     sampler_dn[index].dw6.mcdi_enable = 0;
3369     sampler_dn[index].dw6.fmd_tear_threshold = 32;
3370     sampler_dn[index].dw6.cat_th1 = 0;
3371     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
3372     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
3373
3374     sampler_dn[index].dw7.sad_tha = 5;
3375     sampler_dn[index].dw7.sad_thb = 10;
3376     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
3377     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
3378     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
3379     sampler_dn[index].dw7.vdi_walker_enable = 0;
3380     sampler_dn[index].dw7.neighborpixel_th = 10;
3381     sampler_dn[index].dw7.column_width_minus1 = w / 16;
3382
3383     dri_bo_unmap(pp_context->sampler_state_table.bo);
3384
3385     /* private function & data */
3386     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
3387     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
3388     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
3389
3390     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
3391     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
3392     pp_static_parameter->grf1.di_top_field_first = 0;
3393     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
3394
3395     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
3396     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
3397     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
3398
3399     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
3400     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
3401
3402     pp_dn_context->dest_w = w;
3403     pp_dn_context->dest_h = h;
3404
3405     dst_surface->flags = src_surface->flags;
3406
3407     return VA_STATUS_SUCCESS;
3408 }
3409
3410 static VAStatus
3411 ironlake_pp_initialize(
3412     VADriverContextP   ctx,
3413     struct i965_post_processing_context *pp_context,
3414     const struct i965_surface *src_surface,
3415     const VARectangle *src_rect,
3416     struct i965_surface *dst_surface,
3417     const VARectangle *dst_rect,
3418     int                pp_index,
3419     void *filter_param
3420 )
3421 {
3422     VAStatus va_status;
3423     struct i965_driver_data *i965 = i965_driver_data(ctx);
3424     struct pp_module *pp_module;
3425     dri_bo *bo;
3426     int static_param_size, inline_param_size;
3427
3428     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3429     bo = dri_bo_alloc(i965->intel.bufmgr,
3430                       "surface state & binding table",
3431                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3432                       4096);
3433     assert(bo);
3434     pp_context->surface_state_binding_table.bo = bo;
3435
3436     dri_bo_unreference(pp_context->curbe.bo);
3437     bo = dri_bo_alloc(i965->intel.bufmgr,
3438                       "constant buffer",
3439                       4096,
3440                       4096);
3441     assert(bo);
3442     pp_context->curbe.bo = bo;
3443
3444     dri_bo_unreference(pp_context->idrt.bo);
3445     bo = dri_bo_alloc(i965->intel.bufmgr,
3446                       "interface discriptor",
3447                       sizeof(struct i965_interface_descriptor),
3448                       4096);
3449     assert(bo);
3450     pp_context->idrt.bo = bo;
3451     pp_context->idrt.num_interface_descriptors = 0;
3452
3453     dri_bo_unreference(pp_context->sampler_state_table.bo);
3454     bo = dri_bo_alloc(i965->intel.bufmgr,
3455                       "sampler state table",
3456                       4096,
3457                       4096);
3458     assert(bo);
3459     dri_bo_map(bo, True);
3460     memset(bo->virtual, 0, bo->size);
3461     dri_bo_unmap(bo);
3462     pp_context->sampler_state_table.bo = bo;
3463
3464     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3465     bo = dri_bo_alloc(i965->intel.bufmgr,
3466                       "sampler 8x8 state ",
3467                       4096,
3468                       4096);
3469     assert(bo);
3470     pp_context->sampler_state_table.bo_8x8 = bo;
3471
3472     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3473     bo = dri_bo_alloc(i965->intel.bufmgr,
3474                       "sampler 8x8 state ",
3475                       4096,
3476                       4096);
3477     assert(bo);
3478     pp_context->sampler_state_table.bo_8x8_uv = bo;
3479
3480     dri_bo_unreference(pp_context->vfe_state.bo);
3481     bo = dri_bo_alloc(i965->intel.bufmgr,
3482                       "vfe state",
3483                       sizeof(struct i965_vfe_state),
3484                       4096);
3485     assert(bo);
3486     pp_context->vfe_state.bo = bo;
3487
3488     static_param_size = sizeof(struct pp_static_parameter);
3489     inline_param_size = sizeof(struct pp_inline_parameter);
3490
3491     memset(pp_context->pp_static_parameter, 0, static_param_size);
3492     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3493
3494     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3495     pp_context->current_pp = pp_index;
3496     pp_module = &pp_context->pp_modules[pp_index];
3497
3498     if (pp_module->initialize)
3499         va_status = pp_module->initialize(ctx, pp_context,
3500                                           src_surface,
3501                                           src_rect,
3502                                           dst_surface,
3503                                           dst_rect,
3504                                           filter_param);
3505     else
3506         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3507
3508     calculate_boundary_block_mask(pp_context, dst_rect->width, dst_rect->height);
3509
3510     return va_status;
3511 }
3512
3513 static VAStatus
3514 ironlake_post_processing(
3515     VADriverContextP   ctx,
3516     struct i965_post_processing_context *pp_context,
3517     const struct i965_surface *src_surface,
3518     const VARectangle *src_rect,
3519     struct i965_surface *dst_surface,
3520     const VARectangle *dst_rect,
3521     int                pp_index,
3522     void *filter_param
3523 )
3524 {
3525     VAStatus va_status;
3526
3527     va_status = ironlake_pp_initialize(ctx, pp_context,
3528                                        src_surface,
3529                                        src_rect,
3530                                        dst_surface,
3531                                        dst_rect,
3532                                        pp_index,
3533                                        filter_param);
3534
3535     if (va_status == VA_STATUS_SUCCESS) {
3536         ironlake_pp_states_setup(ctx, pp_context);
3537         ironlake_pp_pipeline_setup(ctx, pp_context);
3538     }
3539
3540     return va_status;
3541 }
3542
3543 static VAStatus
3544 gen6_pp_initialize(
3545     VADriverContextP   ctx,
3546     struct i965_post_processing_context *pp_context,
3547     const struct i965_surface *src_surface,
3548     const VARectangle *src_rect,
3549     struct i965_surface *dst_surface,
3550     const VARectangle *dst_rect,
3551     int                pp_index,
3552     void *filter_param
3553 )
3554 {
3555     VAStatus va_status;
3556     struct i965_driver_data *i965 = i965_driver_data(ctx);
3557     struct pp_module *pp_module;
3558     dri_bo *bo;
3559     int static_param_size, inline_param_size;
3560
3561     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3562     bo = dri_bo_alloc(i965->intel.bufmgr,
3563                       "surface state & binding table",
3564                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3565                       4096);
3566     assert(bo);
3567     pp_context->surface_state_binding_table.bo = bo;
3568
3569     dri_bo_unreference(pp_context->curbe.bo);
3570     bo = dri_bo_alloc(i965->intel.bufmgr,
3571                       "constant buffer",
3572                       4096,
3573                       4096);
3574     assert(bo);
3575     pp_context->curbe.bo = bo;
3576
3577     dri_bo_unreference(pp_context->idrt.bo);
3578     bo = dri_bo_alloc(i965->intel.bufmgr,
3579                       "interface discriptor",
3580                       sizeof(struct gen6_interface_descriptor_data),
3581                       4096);
3582     assert(bo);
3583     pp_context->idrt.bo = bo;
3584     pp_context->idrt.num_interface_descriptors = 0;
3585
3586     dri_bo_unreference(pp_context->sampler_state_table.bo);
3587     bo = dri_bo_alloc(i965->intel.bufmgr,
3588                       "sampler state table",
3589                       4096,
3590                       4096);
3591     assert(bo);
3592     dri_bo_map(bo, True);
3593     memset(bo->virtual, 0, bo->size);
3594     dri_bo_unmap(bo);
3595     pp_context->sampler_state_table.bo = bo;
3596
3597     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3598     bo = dri_bo_alloc(i965->intel.bufmgr,
3599                       "sampler 8x8 state ",
3600                       4096,
3601                       4096);
3602     assert(bo);
3603     pp_context->sampler_state_table.bo_8x8 = bo;
3604
3605     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3606     bo = dri_bo_alloc(i965->intel.bufmgr,
3607                       "sampler 8x8 state ",
3608                       4096,
3609                       4096);
3610     assert(bo);
3611     pp_context->sampler_state_table.bo_8x8_uv = bo;
3612
3613     dri_bo_unreference(pp_context->vfe_state.bo);
3614     bo = dri_bo_alloc(i965->intel.bufmgr,
3615                       "vfe state",
3616                       sizeof(struct i965_vfe_state),
3617                       4096);
3618     assert(bo);
3619     pp_context->vfe_state.bo = bo;
3620
3621     if (IS_GEN7(i965->intel.device_id)) {
3622         static_param_size = sizeof(struct gen7_pp_static_parameter);
3623         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3624     } else {
3625         static_param_size = sizeof(struct pp_static_parameter);
3626         inline_param_size = sizeof(struct pp_inline_parameter);
3627     }
3628
3629     memset(pp_context->pp_static_parameter, 0, static_param_size);
3630     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3631
3632     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3633     pp_context->current_pp = pp_index;
3634     pp_module = &pp_context->pp_modules[pp_index];
3635
3636     if (pp_module->initialize)
3637         va_status = pp_module->initialize(ctx, pp_context,
3638                                           src_surface,
3639                                           src_rect,
3640                                           dst_surface,
3641                                           dst_rect,
3642                                           filter_param);
3643     else
3644         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3645
3646     return va_status;
3647 }
3648
3649 static void
3650 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3651                                    struct i965_post_processing_context *pp_context)
3652 {
3653     struct i965_driver_data *i965 = i965_driver_data(ctx);
3654     struct gen6_interface_descriptor_data *desc;
3655     dri_bo *bo;
3656     int pp_index = pp_context->current_pp;
3657
3658     bo = pp_context->idrt.bo;
3659     dri_bo_map(bo, True);
3660     assert(bo->virtual);
3661     desc = bo->virtual;
3662     memset(desc, 0, sizeof(*desc));
3663     desc->desc0.kernel_start_pointer =
3664         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3665     desc->desc1.single_program_flow = 1;
3666     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3667     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3668     desc->desc2.sampler_state_pointer =
3669         pp_context->sampler_state_table.bo->offset >> 5;
3670     desc->desc3.binding_table_entry_count = 0;
3671     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3672     desc->desc4.constant_urb_entry_read_offset = 0;
3673
3674     if (IS_GEN7(i965->intel.device_id))
3675         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3676     else
3677         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3678
3679     dri_bo_emit_reloc(bo,
3680                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3681                       0,
3682                       offsetof(struct gen6_interface_descriptor_data, desc0),
3683                       pp_context->pp_modules[pp_index].kernel.bo);
3684
3685     dri_bo_emit_reloc(bo,
3686                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3687                       desc->desc2.sampler_count << 2,
3688                       offsetof(struct gen6_interface_descriptor_data, desc2),
3689                       pp_context->sampler_state_table.bo);
3690
3691     dri_bo_unmap(bo);
3692     pp_context->idrt.num_interface_descriptors++;
3693 }
3694
3695 static void
3696 gen6_pp_upload_constants(VADriverContextP ctx,
3697                          struct i965_post_processing_context *pp_context)
3698 {
3699     struct i965_driver_data *i965 = i965_driver_data(ctx);
3700     unsigned char *constant_buffer;
3701     int param_size;
3702
3703     assert(sizeof(struct pp_static_parameter) == 128);
3704     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3705
3706     if (IS_GEN7(i965->intel.device_id))
3707         param_size = sizeof(struct gen7_pp_static_parameter);
3708     else
3709         param_size = sizeof(struct pp_static_parameter);
3710
3711     dri_bo_map(pp_context->curbe.bo, 1);
3712     assert(pp_context->curbe.bo->virtual);
3713     constant_buffer = pp_context->curbe.bo->virtual;
3714     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3715     dri_bo_unmap(pp_context->curbe.bo);
3716 }
3717
3718 static void
3719 gen6_pp_states_setup(VADriverContextP ctx,
3720                      struct i965_post_processing_context *pp_context)
3721 {
3722     gen6_pp_interface_descriptor_table(ctx, pp_context);
3723     gen6_pp_upload_constants(ctx, pp_context);
3724 }
3725
3726 static void
3727 gen6_pp_pipeline_select(VADriverContextP ctx,
3728                         struct i965_post_processing_context *pp_context)
3729 {
3730     struct intel_batchbuffer *batch = pp_context->batch;
3731
3732     BEGIN_BATCH(batch, 1);
3733     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3734     ADVANCE_BATCH(batch);
3735 }
3736
3737 static void
3738 gen6_pp_state_base_address(VADriverContextP ctx,
3739                            struct i965_post_processing_context *pp_context)
3740 {
3741     struct intel_batchbuffer *batch = pp_context->batch;
3742
3743     BEGIN_BATCH(batch, 10);
3744     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3745     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3746     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3747     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3748     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3749     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3750     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3751     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3752     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3753     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3754     ADVANCE_BATCH(batch);
3755 }
3756
3757 static void
3758 gen6_pp_vfe_state(VADriverContextP ctx,
3759                   struct i965_post_processing_context *pp_context)
3760 {
3761     struct intel_batchbuffer *batch = pp_context->batch;
3762
3763     BEGIN_BATCH(batch, 8);
3764     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3765     OUT_BATCH(batch, 0);
3766     OUT_BATCH(batch,
3767               (pp_context->urb.num_vfe_entries - 1) << 16 |
3768               pp_context->urb.num_vfe_entries << 8);
3769     OUT_BATCH(batch, 0);
3770     OUT_BATCH(batch,
3771               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3772               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3773     OUT_BATCH(batch, 0);
3774     OUT_BATCH(batch, 0);
3775     OUT_BATCH(batch, 0);
3776     ADVANCE_BATCH(batch);
3777 }
3778
3779 static void
3780 gen6_pp_curbe_load(VADriverContextP ctx,
3781                    struct i965_post_processing_context *pp_context)
3782 {
3783     struct intel_batchbuffer *batch = pp_context->batch;
3784
3785     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3786
3787     BEGIN_BATCH(batch, 4);
3788     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3789     OUT_BATCH(batch, 0);
3790     OUT_BATCH(batch,
3791               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3792     OUT_RELOC(batch,
3793               pp_context->curbe.bo,
3794               I915_GEM_DOMAIN_INSTRUCTION, 0,
3795               0);
3796     ADVANCE_BATCH(batch);
3797 }
3798
3799 static void
3800 gen6_interface_descriptor_load(VADriverContextP ctx,
3801                                struct i965_post_processing_context *pp_context)
3802 {
3803     struct intel_batchbuffer *batch = pp_context->batch;
3804
3805     BEGIN_BATCH(batch, 4);
3806     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3807     OUT_BATCH(batch, 0);
3808     OUT_BATCH(batch,
3809               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3810     OUT_RELOC(batch,
3811               pp_context->idrt.bo,
3812               I915_GEM_DOMAIN_INSTRUCTION, 0,
3813               0);
3814     ADVANCE_BATCH(batch);
3815 }
3816
3817 static void update_block_mask_parameter(struct i965_post_processing_context *pp_context, int x, int y, int x_steps, int y_steps)
3818 {
3819     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3820
3821     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
3822     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
3823     pp_inline_parameter->grf6.block_vertical_mask = pp_context->block_vertical_mask;
3824     pp_inline_parameter->grf6.block_horizontal_mask = pp_context->block_horizontal_mask;
3825
3826     /* 1 x N */
3827     if (x_steps == 1) {
3828         if (y == y_steps-1) {
3829             pp_inline_parameter->grf5.block_vertical_mask = pp_context->block_vertical_mask;
3830         }
3831         else {
3832             pp_inline_parameter->grf6.block_vertical_mask = 0xff;
3833         }
3834     }
3835
3836     /* M x 1 */
3837     if (y_steps == 1) {
3838         if (x == x_steps-1) {
3839             pp_inline_parameter->grf5.block_horizontal_mask = pp_context->block_horizontal_mask;
3840         }
3841         else {
3842             pp_inline_parameter->grf6.block_horizontal_mask = 0xffff;
3843         }
3844     }
3845
3846 }
3847
3848 static void
3849 gen6_pp_object_walker(VADriverContextP ctx,
3850                       struct i965_post_processing_context *pp_context)
3851 {
3852     struct i965_driver_data *i965 = i965_driver_data(ctx);
3853     struct intel_batchbuffer *batch = pp_context->batch;
3854     int x, x_steps, y, y_steps;
3855     int param_size, command_length_in_dws;
3856     dri_bo *command_buffer;
3857     unsigned int *command_ptr;
3858
3859     if (IS_GEN7(i965->intel.device_id))
3860         param_size = sizeof(struct gen7_pp_inline_parameter);
3861     else
3862         param_size = sizeof(struct pp_inline_parameter);
3863
3864     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3865     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3866     command_length_in_dws = 6 + (param_size >> 2);
3867     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3868                                   "command objects buffer",
3869                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3870                                   4096);
3871
3872     dri_bo_map(command_buffer, 1);
3873     command_ptr = command_buffer->virtual;
3874
3875     for (y = 0; y < y_steps; y++) {
3876         for (x = 0; x < x_steps; x++) {
3877             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3878                 // some common block parameter update goes here, apply to all pp functions
3879                 update_block_mask_parameter (pp_context, x, y, x_steps, y_steps);
3880
3881                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3882                 *command_ptr++ = 0;
3883                 *command_ptr++ = 0;
3884                 *command_ptr++ = 0;
3885                 *command_ptr++ = 0;
3886                 *command_ptr++ = 0;
3887                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3888                 command_ptr += (param_size >> 2);
3889             }
3890         }
3891     }
3892
3893     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3894         *command_ptr++ = 0;
3895
3896     *command_ptr = MI_BATCH_BUFFER_END;
3897
3898     dri_bo_unmap(command_buffer);
3899
3900     BEGIN_BATCH(batch, 2);
3901     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3902     OUT_RELOC(batch, command_buffer,
3903               I915_GEM_DOMAIN_COMMAND, 0,
3904               0);
3905     ADVANCE_BATCH(batch);
3906
3907     dri_bo_unreference(command_buffer);
3908
3909     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3910      * will cause control to pass back to ring buffer
3911      */
3912     intel_batchbuffer_end_atomic(batch);
3913     intel_batchbuffer_flush(batch);
3914     intel_batchbuffer_start_atomic(batch, 0x1000);
3915 }
3916
3917 static void
3918 gen6_pp_pipeline_setup(VADriverContextP ctx,
3919                        struct i965_post_processing_context *pp_context)
3920 {
3921     struct intel_batchbuffer *batch = pp_context->batch;
3922
3923     intel_batchbuffer_start_atomic(batch, 0x1000);
3924     intel_batchbuffer_emit_mi_flush(batch);
3925     gen6_pp_pipeline_select(ctx, pp_context);
3926     gen6_pp_state_base_address(ctx, pp_context);
3927     gen6_pp_vfe_state(ctx, pp_context);
3928     gen6_pp_curbe_load(ctx, pp_context);
3929     gen6_interface_descriptor_load(ctx, pp_context);
3930     gen6_pp_object_walker(ctx, pp_context);
3931     intel_batchbuffer_end_atomic(batch);
3932 }
3933
3934 static VAStatus
3935 gen6_post_processing(
3936     VADriverContextP   ctx,
3937     struct i965_post_processing_context *pp_context,
3938     const struct i965_surface *src_surface,
3939     const VARectangle *src_rect,
3940     struct i965_surface *dst_surface,
3941     const VARectangle *dst_rect,
3942     int                pp_index,
3943     void * filter_param
3944 )
3945 {
3946     VAStatus va_status;
3947
3948     va_status = gen6_pp_initialize(ctx, pp_context,
3949                                    src_surface,
3950                                    src_rect,
3951                                    dst_surface,
3952                                    dst_rect,
3953                                    pp_index,
3954                                    filter_param);
3955
3956     if (va_status == VA_STATUS_SUCCESS) {
3957         gen6_pp_states_setup(ctx, pp_context);
3958         gen6_pp_pipeline_setup(ctx, pp_context);
3959     }
3960
3961     return va_status;
3962 }
3963
3964 static VAStatus
3965 i965_post_processing_internal(
3966     VADriverContextP   ctx,
3967     struct i965_post_processing_context *pp_context,
3968     const struct i965_surface *src_surface,
3969     const VARectangle *src_rect,
3970     struct i965_surface *dst_surface,
3971     const VARectangle *dst_rect,
3972     int                pp_index,
3973     void *filter_param
3974 )
3975 {
3976     struct i965_driver_data *i965 = i965_driver_data(ctx);
3977     VAStatus va_status;
3978
3979     if (IS_GEN6(i965->intel.device_id) ||
3980         IS_GEN7(i965->intel.device_id))
3981         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3982     else
3983         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3984
3985     return va_status;
3986 }
3987
3988 VAStatus
3989 i965_DestroySurfaces(VADriverContextP ctx,
3990                      VASurfaceID *surface_list,
3991                      int num_surfaces);
3992 VAStatus
3993 i965_CreateSurfaces(VADriverContextP ctx,
3994                     int width,
3995                     int height,
3996                     int format,
3997                     int num_surfaces,
3998                     VASurfaceID *surfaces);
3999
4000 static void
4001 rgb_to_yuv(unsigned int argb,
4002            unsigned char *y,
4003            unsigned char *u,
4004            unsigned char *v,
4005            unsigned char *a)
4006 {
4007     int r = ((argb >> 16) & 0xff);
4008     int g = ((argb >> 8) & 0xff);
4009     int b = ((argb >> 0) & 0xff);
4010
4011     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
4012     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
4013     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
4014     *a = ((argb >> 24) & 0xff);
4015 }
4016
4017 static void
4018 i965_vpp_clear_surface(VADriverContextP ctx,
4019                        struct i965_post_processing_context *pp_context,
4020                        VASurfaceID surface,
4021                        unsigned int color)
4022 {
4023     struct i965_driver_data *i965 = i965_driver_data(ctx);
4024     struct intel_batchbuffer *batch = pp_context->batch;
4025     struct object_surface *obj_surface = SURFACE(surface);
4026     unsigned int blt_cmd, br13;
4027     unsigned int tiling = 0, swizzle = 0;
4028     int pitch;
4029     unsigned char y, u, v, a = 0;
4030
4031     /* Currently only support NV12 surface */
4032     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
4033         return;
4034
4035     rgb_to_yuv(color, &y, &u, &v, &a);
4036
4037     if (a == 0)
4038         return;
4039
4040     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4041     blt_cmd = XY_COLOR_BLT_CMD;
4042     pitch = obj_surface->width;
4043
4044     if (tiling != I915_TILING_NONE) {
4045         blt_cmd |= XY_COLOR_BLT_DST_TILED;
4046         pitch >>= 2;
4047     }
4048
4049     br13 = 0xf0 << 16;
4050     br13 |= BR13_8;
4051     br13 |= pitch;
4052
4053     if (IS_GEN6(i965->intel.device_id) ||
4054         IS_GEN7(i965->intel.device_id)) {
4055         intel_batchbuffer_start_atomic_blt(batch, 48);
4056         BEGIN_BLT_BATCH(batch, 12);
4057     } else {
4058         intel_batchbuffer_start_atomic(batch, 48);
4059         BEGIN_BATCH(batch, 12);
4060     }
4061
4062     OUT_BATCH(batch, blt_cmd);
4063     OUT_BATCH(batch, br13);
4064     OUT_BATCH(batch,
4065               0 << 16 |
4066               0);
4067     OUT_BATCH(batch,
4068               obj_surface->height << 16 |
4069               obj_surface->width);
4070     OUT_RELOC(batch, obj_surface->bo,
4071               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4072               0);
4073     OUT_BATCH(batch, y);
4074
4075     br13 = 0xf0 << 16;
4076     br13 |= BR13_565;
4077     br13 |= pitch;
4078
4079     OUT_BATCH(batch, blt_cmd);
4080     OUT_BATCH(batch, br13);
4081     OUT_BATCH(batch,
4082               0 << 16 |
4083               0);
4084     OUT_BATCH(batch,
4085               obj_surface->height / 2 << 16 |
4086               obj_surface->width / 2);
4087     OUT_RELOC(batch, obj_surface->bo,
4088               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
4089               obj_surface->width * obj_surface->y_cb_offset);
4090     OUT_BATCH(batch, v << 8 | u);
4091
4092     ADVANCE_BATCH(batch);
4093     intel_batchbuffer_end_atomic(batch);
4094 }
4095
4096 VASurfaceID
4097 i965_post_processing(
4098     VADriverContextP   ctx,
4099     VASurfaceID        surface,
4100     const VARectangle *src_rect,
4101     const VARectangle *dst_rect,
4102     unsigned int       flags,
4103     int               *has_done_scaling
4104 )
4105 {
4106     struct i965_driver_data *i965 = i965_driver_data(ctx);
4107     VASurfaceID in_surface_id = surface;
4108     VASurfaceID out_surface_id = VA_INVALID_ID;
4109
4110     *has_done_scaling = 0;
4111
4112     if (HAS_PP(i965)) {
4113         struct object_surface *obj_surface;
4114         VAStatus status;
4115         struct i965_surface src_surface;
4116         struct i965_surface dst_surface;
4117
4118         obj_surface = SURFACE(in_surface_id);
4119
4120         /* Currently only support post processing for NV12 surface */
4121         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
4122             return out_surface_id;
4123
4124         _i965LockMutex(&i965->pp_mutex);
4125
4126         if (flags & I965_PP_FLAG_MCDI) {
4127             status = i965_CreateSurfaces(ctx,
4128                                          obj_surface->orig_width,
4129                                          obj_surface->orig_height,
4130                                          VA_RT_FORMAT_YUV420,
4131                                          1,
4132                                          &out_surface_id);
4133             assert(status == VA_STATUS_SUCCESS);
4134             obj_surface = SURFACE(out_surface_id);
4135             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4136             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4137             src_surface.id = in_surface_id;
4138             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4139             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
4140                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
4141             dst_surface.id = out_surface_id;
4142             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4143             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4144
4145             i965_post_processing_internal(ctx, i965->pp_context,
4146                                           &src_surface,
4147                                           src_rect,
4148                                           &dst_surface,
4149                                           dst_rect,
4150                                           PP_NV12_DNDI,
4151                                           NULL);
4152         }
4153
4154         if (flags & I965_PP_FLAG_AVS) {
4155             struct i965_render_state *render_state = &i965->render_state;
4156             struct intel_region *dest_region = render_state->draw_region;
4157
4158             if (out_surface_id != VA_INVALID_ID)
4159                 in_surface_id = out_surface_id;
4160
4161             status = i965_CreateSurfaces(ctx,
4162                                          dest_region->width,
4163                                          dest_region->height,
4164                                          VA_RT_FORMAT_YUV420,
4165                                          1,
4166                                          &out_surface_id);
4167             assert(status == VA_STATUS_SUCCESS);
4168             obj_surface = SURFACE(out_surface_id);
4169             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4170             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
4171             src_surface.id = in_surface_id;
4172             src_surface.type = I965_SURFACE_TYPE_SURFACE;
4173             src_surface.flags = I965_SURFACE_FLAG_FRAME;
4174             dst_surface.id = out_surface_id;
4175             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4176             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4177
4178             i965_post_processing_internal(ctx, i965->pp_context,
4179                                           &src_surface,
4180                                           src_rect,
4181                                           &dst_surface,
4182                                           dst_rect,
4183                                           PP_NV12_AVS,
4184                                           NULL);
4185
4186             if (in_surface_id != surface)
4187                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
4188
4189             *has_done_scaling = 1;
4190         }
4191
4192         _i965UnlockMutex(&i965->pp_mutex);
4193     }
4194
4195     return out_surface_id;
4196 }
4197
4198 static VAStatus
4199 i965_image_pl1_rgbx_processing(VADriverContextP ctx,
4200                           const struct i965_surface *src_surface,
4201                           const VARectangle *src_rect,
4202                           struct i965_surface *dst_surface,
4203                           const VARectangle *dst_rect)
4204 {
4205     struct i965_driver_data *i965 = i965_driver_data(ctx);
4206     struct i965_post_processing_context *pp_context = i965->pp_context;
4207     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4208
4209     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4210         i965_post_processing_internal(ctx, i965->pp_context,
4211                                       src_surface,
4212                                       src_rect,
4213                                       dst_surface,
4214                                       dst_rect,
4215                                       PP_RGBX_LOAD_SAVE_NV12,
4216                                       NULL);
4217     } else {
4218         assert(0);
4219         return VA_STATUS_ERROR_UNKNOWN;
4220     }
4221
4222     intel_batchbuffer_flush(pp_context->batch);
4223
4224     return VA_STATUS_SUCCESS;
4225 }
4226
4227 static VAStatus
4228 i965_image_pl3_processing(VADriverContextP ctx,
4229                           const struct i965_surface *src_surface,
4230                           const VARectangle *src_rect,
4231                           struct i965_surface *dst_surface,
4232                           const VARectangle *dst_rect)
4233 {
4234     struct i965_driver_data *i965 = i965_driver_data(ctx);
4235     struct i965_post_processing_context *pp_context = i965->pp_context;
4236     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4237     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4238
4239     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4240         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4241                                                  src_surface,
4242                                                  src_rect,
4243                                                  dst_surface,
4244                                                  dst_rect,
4245                                                  PP_PL3_LOAD_SAVE_N12,
4246                                                  NULL);
4247     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4248                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4249                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4250                fourcc == VA_FOURCC('I', '4', '2', '0')) {
4251         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4252                                                  src_surface,
4253                                                  src_rect,
4254                                                  dst_surface,
4255                                                  dst_rect,
4256                                                  PP_PL3_LOAD_SAVE_PL3,
4257                                                  NULL);
4258     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4259                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4260         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4261                                                  src_surface,
4262                                                  src_rect,
4263                                                  dst_surface,
4264                                                  dst_rect,
4265                                                  PP_PL3_LOAD_SAVE_PA,
4266                                                  NULL);
4267     }
4268     else {
4269         assert(0);
4270     }
4271
4272     intel_batchbuffer_flush(pp_context->batch);
4273
4274     return vaStatus;
4275 }
4276
4277 static VAStatus
4278 i965_image_pl2_processing(VADriverContextP ctx,
4279                           const struct i965_surface *src_surface,
4280                           const VARectangle *src_rect,
4281                           struct i965_surface *dst_surface,
4282                           const VARectangle *dst_rect)
4283 {
4284     struct i965_driver_data *i965 = i965_driver_data(ctx);
4285     struct i965_post_processing_context *pp_context = i965->pp_context;
4286     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4287     VAStatus vaStatus = VA_STATUS_ERROR_UNIMPLEMENTED;
4288
4289     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4290         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4291                                                  src_surface,
4292                                                  src_rect,
4293                                                  dst_surface,
4294                                                  dst_rect,
4295                                                  PP_NV12_LOAD_SAVE_N12,
4296                                                  NULL);
4297     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
4298                fourcc == VA_FOURCC('I', 'M', 'C', '3') ||
4299                fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
4300                fourcc == VA_FOURCC('I', '4', '2', '0') ) {
4301         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4302                                                  src_surface,
4303                                                  src_rect,
4304                                                  dst_surface,
4305                                                  dst_rect,
4306                                                  PP_NV12_LOAD_SAVE_PL3,
4307                                                  NULL);
4308     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') ||
4309                fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
4310         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4311                                                  src_surface,
4312                                                  src_rect,
4313                                                  dst_surface,
4314                                                  dst_rect,
4315                                                  PP_NV12_LOAD_SAVE_PA,
4316                                                      NULL);
4317     } else if (fourcc == VA_FOURCC('B', 'G', 'R', 'X') ||
4318                fourcc == VA_FOURCC('B', 'G', 'R', 'A') ||
4319                fourcc == VA_FOURCC('R', 'G', 'B', 'X') ||
4320                fourcc == VA_FOURCC('R', 'G', 'B', 'A') ) {
4321         vaStatus = i965_post_processing_internal(ctx, i965->pp_context,
4322                                       src_surface,
4323                                       src_rect,
4324                                       dst_surface,
4325                                       dst_rect,
4326                                       PP_NV12_LOAD_SAVE_RGBX,
4327                                       NULL);
4328     } else {
4329         assert(0);
4330         return VA_STATUS_ERROR_UNKNOWN;
4331     }
4332
4333     intel_batchbuffer_flush(pp_context->batch);
4334
4335     return vaStatus;
4336 }
4337
4338 static VAStatus
4339 i965_image_pl1_processing(VADriverContextP ctx,
4340                           const struct i965_surface *src_surface,
4341                           const VARectangle *src_rect,
4342                           struct i965_surface *dst_surface,
4343                           const VARectangle *dst_rect)
4344 {
4345     struct i965_driver_data *i965 = i965_driver_data(ctx);
4346     struct i965_post_processing_context *pp_context = i965->pp_context;
4347     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
4348
4349     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
4350         i965_post_processing_internal(ctx, i965->pp_context,
4351                                       src_surface,
4352                                       src_rect,
4353                                       dst_surface,
4354                                       dst_rect,
4355                                       PP_PA_LOAD_SAVE_NV12,
4356                                       NULL);
4357     }
4358     else if (fourcc == VA_FOURCC_YV12) {
4359         i965_post_processing_internal(ctx, i965->pp_context,
4360                                       src_surface,
4361                                       src_rect,
4362                                       dst_surface,
4363                                       dst_rect,
4364                                       PP_PA_LOAD_SAVE_PL3,
4365                                       NULL);
4366
4367     }
4368     else {
4369         return VA_STATUS_ERROR_UNKNOWN;
4370     }
4371
4372     intel_batchbuffer_flush(pp_context->batch);
4373
4374     return VA_STATUS_SUCCESS;
4375 }
4376
4377 VAStatus
4378 i965_image_processing(VADriverContextP ctx,
4379                       const struct i965_surface *src_surface,
4380                       const VARectangle *src_rect,
4381                       struct i965_surface *dst_surface,
4382                       const VARectangle *dst_rect)
4383 {
4384     struct i965_driver_data *i965 = i965_driver_data(ctx);
4385     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
4386
4387     if (HAS_PP(i965)) {
4388         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
4389
4390         _i965LockMutex(&i965->pp_mutex);
4391
4392         switch (fourcc) {
4393         case VA_FOURCC('Y', 'V', '1', '2'):
4394         case VA_FOURCC('I', '4', '2', '0'):
4395         case VA_FOURCC('I', 'M', 'C', '1'):
4396         case VA_FOURCC('I', 'M', 'C', '3'):
4397             status = i965_image_pl3_processing(ctx,
4398                                                src_surface,
4399                                                src_rect,
4400                                                dst_surface,
4401                                                dst_rect);
4402             break;
4403
4404         case  VA_FOURCC('N', 'V', '1', '2'):
4405             status = i965_image_pl2_processing(ctx,
4406                                                src_surface,
4407                                                src_rect,
4408                                                dst_surface,
4409                                                dst_rect);
4410             break;
4411         case  VA_FOURCC('Y', 'U', 'Y', '2'):
4412         case VA_FOURCC('U', 'Y', 'V', 'Y'):
4413             status = i965_image_pl1_processing(ctx,
4414                                                src_surface,
4415                                                src_rect,
4416                                                dst_surface,
4417                                                dst_rect);
4418             break;
4419         case VA_FOURCC('B', 'G', 'R', 'A'):
4420         case VA_FOURCC('B', 'G', 'R', 'X'):
4421         case VA_FOURCC('R', 'G', 'B', 'A'):
4422         case VA_FOURCC('R', 'G', 'B', 'X'):
4423             status = i965_image_pl1_rgbx_processing(ctx,
4424                                                src_surface,
4425                                                src_rect,
4426                                                dst_surface,
4427                                                dst_rect);
4428             break;
4429         default:
4430             status = VA_STATUS_ERROR_UNIMPLEMENTED;
4431             break;
4432         }
4433
4434         _i965UnlockMutex(&i965->pp_mutex);
4435     }
4436
4437     return status;
4438 }
4439
4440 static void
4441 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
4442 {
4443     int i;
4444
4445     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
4446     pp_context->surface_state_binding_table.bo = NULL;
4447
4448     dri_bo_unreference(pp_context->curbe.bo);
4449     pp_context->curbe.bo = NULL;
4450
4451     dri_bo_unreference(pp_context->sampler_state_table.bo);
4452     pp_context->sampler_state_table.bo = NULL;
4453
4454     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
4455     pp_context->sampler_state_table.bo_8x8 = NULL;
4456
4457     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
4458     pp_context->sampler_state_table.bo_8x8_uv = NULL;
4459
4460     dri_bo_unreference(pp_context->idrt.bo);
4461     pp_context->idrt.bo = NULL;
4462     pp_context->idrt.num_interface_descriptors = 0;
4463
4464     dri_bo_unreference(pp_context->vfe_state.bo);
4465     pp_context->vfe_state.bo = NULL;
4466
4467     dri_bo_unreference(pp_context->stmm.bo);
4468     pp_context->stmm.bo = NULL;
4469
4470     for (i = 0; i < NUM_PP_MODULES; i++) {
4471         struct pp_module *pp_module = &pp_context->pp_modules[i];
4472
4473         dri_bo_unreference(pp_module->kernel.bo);
4474         pp_module->kernel.bo = NULL;
4475     }
4476
4477     free(pp_context->pp_static_parameter);
4478     free(pp_context->pp_inline_parameter);
4479     pp_context->pp_static_parameter = NULL;
4480     pp_context->pp_inline_parameter = NULL;
4481 }
4482
4483 Bool
4484 i965_post_processing_terminate(VADriverContextP ctx)
4485 {
4486     struct i965_driver_data *i965 = i965_driver_data(ctx);
4487     struct i965_post_processing_context *pp_context = i965->pp_context;
4488
4489     if (pp_context) {
4490         i965_post_processing_context_finalize(pp_context);
4491         free(pp_context);
4492     }
4493
4494     i965->pp_context = NULL;
4495
4496     return True;
4497 }
4498
4499 static void
4500 i965_post_processing_context_init(VADriverContextP ctx,
4501                                   struct i965_post_processing_context *pp_context,
4502                                   struct intel_batchbuffer *batch)
4503 {
4504     struct i965_driver_data *i965 = i965_driver_data(ctx);
4505     int i;
4506
4507     pp_context->urb.size = URB_SIZE((&i965->intel));
4508     pp_context->urb.num_vfe_entries = 32;
4509     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
4510     pp_context->urb.num_cs_entries = 1;
4511
4512     if (IS_GEN7(i965->intel.device_id))
4513         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
4514     else
4515         pp_context->urb.size_cs_entry = 2;
4516
4517     pp_context->urb.vfe_start = 0;
4518     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4519         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4520     assert(pp_context->urb.cs_start +
4521            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4522
4523     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4524     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4525     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4526
4527     if (IS_GEN7(i965->intel.device_id))
4528         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4529     else if (IS_GEN6(i965->intel.device_id))
4530         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4531     else if (IS_IRONLAKE(i965->intel.device_id))
4532         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4533
4534     for (i = 0; i < NUM_PP_MODULES; i++) {
4535         struct pp_module *pp_module = &pp_context->pp_modules[i];
4536         dri_bo_unreference(pp_module->kernel.bo);
4537         if (pp_module->kernel.bin && pp_module->kernel.size) {
4538             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4539                                                 pp_module->kernel.name,
4540                                                 pp_module->kernel.size,
4541                                                 4096);
4542             assert(pp_module->kernel.bo);
4543             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4544         } else {
4545             pp_module->kernel.bo = NULL;
4546         }
4547     }
4548
4549     /* static & inline parameters */
4550     if (IS_GEN7(i965->intel.device_id)) {
4551         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4552         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4553     } else {
4554         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4555         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4556     }
4557
4558     pp_context->batch = batch;
4559 }
4560
4561 Bool
4562 i965_post_processing_init(VADriverContextP ctx)
4563 {
4564     struct i965_driver_data *i965 = i965_driver_data(ctx);
4565     struct i965_post_processing_context *pp_context = i965->pp_context;
4566
4567     if (HAS_PP(i965)) {
4568         if (pp_context == NULL) {
4569             pp_context = calloc(1, sizeof(*pp_context));
4570             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4571             i965->pp_context = pp_context;
4572         }
4573     }
4574
4575     return True;
4576 }
4577
4578 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4579     PP_NULL,    /* VAProcFilterNone */
4580     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4581     PP_NULL,    /* VAProcFilterDeblocking */
4582     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4583     PP_NULL,    /* VAProcFilterSharpening */
4584     PP_NULL,    /* VAProcFilterColorBalance */
4585     PP_NULL,    /* VAProcFilterColorStandard */
4586     PP_NULL,    /* VAProcFilterFrameRateConversion */
4587 };
4588
4589 static const int proc_frame_to_pp_frame[3] = {
4590     I965_SURFACE_FLAG_FRAME,
4591     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4592     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4593 };
4594
4595 static void
4596 i965_proc_picture(VADriverContextP ctx,
4597                   VAProfile profile,
4598                   union codec_state *codec_state,
4599                   struct hw_context *hw_context)
4600 {
4601     struct i965_driver_data *i965 = i965_driver_data(ctx);
4602     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4603     struct proc_state *proc_state = &codec_state->proc;
4604     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4605     struct object_surface *obj_surface;
4606     struct i965_surface src_surface, dst_surface;
4607     VARectangle src_rect, dst_rect;
4608     VAStatus status;
4609     int i;
4610     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4611     int num_tmp_surfaces = 0;
4612     unsigned int tiling = 0, swizzle = 0;
4613     int in_width, in_height;
4614
4615     assert(pipeline_param->surface != VA_INVALID_ID);
4616     assert(proc_state->current_render_target != VA_INVALID_ID);
4617
4618     obj_surface = SURFACE(pipeline_param->surface);
4619     in_width = obj_surface->orig_width;
4620     in_height = obj_surface->orig_height;
4621     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4622
4623     src_surface.id = pipeline_param->surface;
4624     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4625     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4626
4627     VASurfaceID out_surface_id = VA_INVALID_ID;
4628     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4629         src_surface.id = pipeline_param->surface;
4630         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4631         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4632         src_rect.x = 0;
4633         src_rect.y = 0;
4634         src_rect.width = in_width;
4635         src_rect.height = in_height;
4636
4637         status = i965_CreateSurfaces(ctx,
4638                                      in_width,
4639                                      in_height,
4640                                      VA_RT_FORMAT_YUV420,
4641                                      1,
4642                                      &out_surface_id);
4643         assert(status == VA_STATUS_SUCCESS);
4644         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4645         obj_surface = SURFACE(out_surface_id);
4646         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4647
4648         dst_surface.id = out_surface_id;
4649         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4650         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4651         dst_rect.x = 0;
4652         dst_rect.y = 0;
4653         dst_rect.width = in_width;
4654         dst_rect.height = in_height;
4655
4656         status = i965_image_processing(ctx,
4657                                        &src_surface,
4658                                        &src_rect,
4659                                        &dst_surface,
4660                                        &dst_rect);
4661         assert(status == VA_STATUS_SUCCESS);
4662
4663         src_surface.id = out_surface_id;
4664         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4665         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4666     }
4667
4668     if (pipeline_param->surface_region) {
4669         src_rect.x = pipeline_param->surface_region->x;
4670         src_rect.y = pipeline_param->surface_region->y;
4671         src_rect.width = pipeline_param->surface_region->width;
4672         src_rect.height = pipeline_param->surface_region->height;
4673     } else {
4674         src_rect.x = 0;
4675         src_rect.y = 0;
4676         src_rect.width = in_width;
4677         src_rect.height = in_height;
4678     }
4679
4680     if (pipeline_param->output_region) {
4681         dst_rect.x = pipeline_param->output_region->x;
4682         dst_rect.y = pipeline_param->output_region->y;
4683         dst_rect.width = pipeline_param->output_region->width;
4684         dst_rect.height = pipeline_param->output_region->height;
4685     } else {
4686         dst_rect.x = 0;
4687         dst_rect.y = 0;
4688         dst_rect.width = in_width;
4689         dst_rect.height = in_height;
4690     }
4691
4692     for (i = 0; i < pipeline_param->num_filters; i++) {
4693         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4694         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4695         VAProcFilterType filter_type = filter_param->type;
4696         out_surface_id = VA_INVALID_ID;
4697         int kernel_index = procfilter_to_pp_flag[filter_type];
4698
4699         if (kernel_index != PP_NULL &&
4700             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4701             status = i965_CreateSurfaces(ctx,
4702                                          in_width,
4703                                          in_height,
4704                                          VA_RT_FORMAT_YUV420,
4705                                          1,
4706                                          &out_surface_id);
4707             assert(status == VA_STATUS_SUCCESS);
4708             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4709             obj_surface = SURFACE(out_surface_id);
4710             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4711             dst_surface.id = out_surface_id;
4712             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4713             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4714                                                    &src_surface,
4715                                                    &src_rect,
4716                                                    &dst_surface,
4717                                                    &src_rect,
4718                                                    kernel_index,
4719                                                    filter_param);
4720
4721             if (status == VA_STATUS_SUCCESS) {
4722                 src_surface.id = dst_surface.id;
4723                 src_surface.type = dst_surface.type;
4724                 src_surface.flags = dst_surface.flags;
4725             }
4726         }
4727     }
4728
4729     obj_surface = SURFACE(proc_state->current_render_target);
4730     int csc_needed = 0;
4731     if (obj_surface->fourcc && obj_surface->fourcc !=  VA_FOURCC('N','V','1','2')){
4732         csc_needed = 1;
4733         out_surface_id = VA_INVALID_ID;
4734         status = i965_CreateSurfaces(ctx,
4735                                      obj_surface->orig_width,
4736                                      obj_surface->orig_height,
4737                                      VA_RT_FORMAT_YUV420,
4738                                      1,
4739                                      &out_surface_id);
4740         assert(status == VA_STATUS_SUCCESS);
4741         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4742         struct object_surface *csc_surface = SURFACE(out_surface_id);
4743         i965_check_alloc_surface_bo(ctx, csc_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4744         dst_surface.id = out_surface_id;
4745     } else {
4746         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4747         dst_surface.id = proc_state->current_render_target;
4748     }
4749
4750     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4751     i965_vpp_clear_surface(ctx, &proc_context->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4752     if (src_rect.width == dst_rect.width &&
4753         src_rect.height == dst_rect.height) {
4754         i965_post_processing_internal(ctx, &proc_context->pp_context,
4755                                       &src_surface,
4756                                       &src_rect,
4757                                       &dst_surface,
4758                                       &dst_rect,
4759                                       PP_NV12_LOAD_SAVE_N12,
4760                                       NULL);
4761     } else {
4762
4763         i965_post_processing_internal(ctx, &proc_context->pp_context,
4764                                       &src_surface,
4765                                       &src_rect,
4766                                       &dst_surface,
4767                                       &dst_rect,
4768                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4769                                       PP_NV12_AVS : PP_NV12_SCALING,
4770                                       NULL);
4771     }
4772
4773     if (csc_needed) {
4774         src_surface.id = dst_surface.id;
4775         src_surface.type = dst_surface.type;
4776         src_surface.flags = dst_surface.flags;
4777         dst_surface.id = proc_state->current_render_target;
4778         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4779         i965_image_processing(ctx, &src_surface, &dst_rect, &dst_surface, &dst_rect);
4780     }
4781
4782     if (num_tmp_surfaces)
4783         i965_DestroySurfaces(ctx,
4784                              tmp_surfaces,
4785                              num_tmp_surfaces);
4786
4787     intel_batchbuffer_flush(hw_context->batch);
4788 }
4789
4790 static void
4791 i965_proc_context_destroy(void *hw_context)
4792 {
4793     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4794
4795     i965_post_processing_context_finalize(&proc_context->pp_context);
4796     intel_batchbuffer_free(proc_context->base.batch);
4797     free(proc_context);
4798 }
4799
4800 struct hw_context *
4801 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4802 {
4803     struct intel_driver_data *intel = intel_driver_data(ctx);
4804     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4805
4806     proc_context->base.destroy = i965_proc_context_destroy;
4807     proc_context->base.run = i965_proc_picture;
4808     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4809     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4810
4811     return (struct hw_context *)proc_context;
4812 }