src/i965_post_processing.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_post_processing.h"
  40 #include "i965_render.h"
  41
  42 #define HAS_PP(ctx) (IS_IRONLAKE((ctx)->intel.device_id) ||     \
  43                      IS_GEN6((ctx)->intel.device_id) ||         \
  44                      IS_GEN7((ctx)->intel.device_id))
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_I965        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_I965        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_I965          MAX(SURFACE_STATE_PADDED_SIZE_0_I965, SURFACE_STATE_PADDED_SIZE_1_I965)
  49
  50 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  51 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  52 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  53
  54 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_I965, SURFACE_STATE_PADDED_SIZE_GEN7)
  55 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  56 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_PP_SURFACES)
  57
  58 static const uint32_t pp_null_gen5[][4] = {
  59 #include "shaders/post_processing/gen5_6/null.g4b.gen5"
  60 };
  61
  62 static const uint32_t pp_nv12_load_save_nv12_gen5[][4] = {
  63 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5"
  64 };
  65
  66 static const uint32_t pp_nv12_load_save_pl3_gen5[][4] = {
  67 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5"
  68 };
  69
  70 static const uint32_t pp_pl3_load_save_nv12_gen5[][4] = {
  71 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5"
  72 };
  73
  74 static const uint32_t pp_pl3_load_save_pl3_gen5[][4] = {
  75 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5"
  76 };
  77
  78 static const uint32_t pp_nv12_scaling_gen5[][4] = {
  79 #include "shaders/post_processing/gen5_6/nv12_scaling_nv12.g4b.gen5"
  80 };
  81
  82 static const uint32_t pp_nv12_avs_gen5[][4] = {
  83 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5"
  84 };
  85
  86 static const uint32_t pp_nv12_dndi_gen5[][4] = {
  87 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5"
  88 };
  89
  90 static const uint32_t pp_nv12_dn_gen5[][4] = {
  91 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5"
  92 };
  93
  94 static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
  95 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
  96 };
  97
  98 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  99                                    const struct i965_surface *src_surface,
 100                                    const VARectangle *src_rect,
 101                                    struct i965_surface *dst_surface,
 102                                    const VARectangle *dst_rect,
 103                                    void *filter_param);
 104 static VAStatus pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 105                                             const struct i965_surface *src_surface,
 106                                             const VARectangle *src_rect,
 107                                             struct i965_surface *dst_surface,
 108                                             const VARectangle *dst_rect,
 109                                             void *filter_param);
 110 static VAStatus pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 111                                            const struct i965_surface *src_surface,
 112                                            const VARectangle *src_rect,
 113                                            struct i965_surface *dst_surface,
 114                                            const VARectangle *dst_rect,
 115                                            void *filter_param);
 116 static VAStatus gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 117                                              const struct i965_surface *src_surface,
 118                                              const VARectangle *src_rect,
 119                                              struct i965_surface *dst_surface,
 120                                              const VARectangle *dst_rect,
 121                                              void *filter_param);
 122 static VAStatus pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 123                                                 const struct i965_surface *src_surface,
 124                                                 const VARectangle *src_rect,
 125                                                 struct i965_surface *dst_surface,
 126                                                 const VARectangle *dst_rect,
 127                                                 void *filter_param);
 128 static VAStatus pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 129                                         const struct i965_surface *src_surface,
 130                                         const VARectangle *src_rect,
 131                                         struct i965_surface *dst_surface,
 132                                         const VARectangle *dst_rect,
 133                                         void *filter_param);
 134 static VAStatus pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 135                                       const struct i965_surface *src_surface,
 136                                       const VARectangle *src_rect,
 137                                       struct i965_surface *dst_surface,
 138                                       const VARectangle *dst_rect,
 139                                       void *filter_param);
 140
 141 static struct pp_module pp_modules_gen5[] = {
 142     {
 143         {
 144             "NULL module (for testing)",
 145             PP_NULL,
 146             pp_null_gen5,
 147             sizeof(pp_null_gen5),
 148             NULL,
 149         },
 150
 151         pp_null_initialize,
 152     },
 153
 154     {
 155         {
 156             "NV12_NV12",
 157             PP_NV12_LOAD_SAVE_N12,
 158             pp_nv12_load_save_nv12_gen5,
 159             sizeof(pp_nv12_load_save_nv12_gen5),
 160             NULL,
 161         },
 162
 163         pp_plx_load_save_plx_initialize,
 164     },
 165
 166     {
 167         {
 168             "NV12_PL3",
 169             PP_NV12_LOAD_SAVE_PL3,
 170             pp_nv12_load_save_pl3_gen5,
 171             sizeof(pp_nv12_load_save_pl3_gen5),
 172             NULL,
 173         },
 174
 175         pp_plx_load_save_plx_initialize,
 176     },
 177
 178     {
 179         {
 180             "PL3_NV12",
 181             PP_PL3_LOAD_SAVE_N12,
 182             pp_pl3_load_save_nv12_gen5,
 183             sizeof(pp_pl3_load_save_nv12_gen5),
 184             NULL,
 185         },
 186
 187         pp_plx_load_save_plx_initialize,
 188     },
 189
 190     {
 191         {
 192             "PL3_PL3",
 193             PP_PL3_LOAD_SAVE_N12,
 194             pp_pl3_load_save_pl3_gen5,
 195             sizeof(pp_pl3_load_save_pl3_gen5),
 196             NULL,
 197         },
 198
 199         pp_plx_load_save_plx_initialize
 200     },
 201
 202     {
 203         {
 204             "NV12 Scaling module",
 205             PP_NV12_SCALING,
 206             pp_nv12_scaling_gen5,
 207             sizeof(pp_nv12_scaling_gen5),
 208             NULL,
 209         },
 210
 211         pp_nv12_scaling_initialize,
 212     },
 213
 214     {
 215         {
 216             "NV12 AVS module",
 217             PP_NV12_AVS,
 218             pp_nv12_avs_gen5,
 219             sizeof(pp_nv12_avs_gen5),
 220             NULL,
 221         },
 222
 223         pp_nv12_avs_initialize_nlas,
 224     },
 225
 226     {
 227         {
 228             "NV12 DNDI module",
 229             PP_NV12_DNDI,
 230             pp_nv12_dndi_gen5,
 231             sizeof(pp_nv12_dndi_gen5),
 232             NULL,
 233         },
 234
 235         pp_nv12_dndi_initialize,
 236     },
 237
 238     {
 239         {
 240             "NV12 DN module",
 241             PP_NV12_DN,
 242             pp_nv12_dn_gen5,
 243             sizeof(pp_nv12_dn_gen5),
 244             NULL,
 245         },
 246
 247         pp_nv12_dn_initialize,
 248     },
 249
 250     {
 251         {
 252             "NV12_PA module",
 253             PP_NV12_LOAD_SAVE_PA,
 254             pp_nv12_load_save_pa_gen5,
 255             sizeof(pp_nv12_load_save_pa_gen5),
 256             NULL,
 257         },
 258
 259         pp_plx_load_save_plx_initialize,
 260     },
 261
 262 };
 263
 264 static const uint32_t pp_null_gen6[][4] = {
 265 #include "shaders/post_processing/gen5_6/null.g6b"
 266 };
 267
 268 static const uint32_t pp_nv12_load_save_nv12_gen6[][4] = {
 269 #include "shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b"
 270 };
 271
 272 static const uint32_t pp_nv12_load_save_pl3_gen6[][4] = {
 273 #include "shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b"
 274 };
 275
 276 static const uint32_t pp_pl3_load_save_nv12_gen6[][4] = {
 277 #include "shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b"
 278 };
 279
 280 static const uint32_t pp_pl3_load_save_pl3_gen6[][4] = {
 281 #include "shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b"
 282 };
 283
 284 static const uint32_t pp_nv12_scaling_gen6[][4] = {
 285 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 286 };
 287
 288 static const uint32_t pp_nv12_avs_gen6[][4] = {
 289 #include "shaders/post_processing/gen5_6/nv12_avs_nv12.g6b"
 290 };
 291
 292 static const uint32_t pp_nv12_dndi_gen6[][4] = {
 293 #include "shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b"
 294 };
 295
 296 static const uint32_t pp_nv12_dn_gen6[][4] = {
 297 #include "shaders/post_processing/gen5_6/nv12_dn_nv12.g6b"
 298 };
 299
 300 static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 301 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 302 };
 303
 304 static struct pp_module pp_modules_gen6[] = {
 305     {
 306         {
 307             "NULL module (for testing)",
 308             PP_NULL,
 309             pp_null_gen6,
 310             sizeof(pp_null_gen6),
 311             NULL,
 312         },
 313
 314         pp_null_initialize,
 315     },
 316
 317     {
 318         {
 319             "NV12_NV12",
 320             PP_NV12_LOAD_SAVE_N12,
 321             pp_nv12_load_save_nv12_gen6,
 322             sizeof(pp_nv12_load_save_nv12_gen6),
 323             NULL,
 324         },
 325
 326         pp_plx_load_save_plx_initialize,
 327     },
 328
 329     {
 330         {
 331             "NV12_PL3",
 332             PP_NV12_LOAD_SAVE_PL3,
 333             pp_nv12_load_save_pl3_gen6,
 334             sizeof(pp_nv12_load_save_pl3_gen6),
 335             NULL,
 336         },
 337
 338         pp_plx_load_save_plx_initialize,
 339     },
 340
 341     {
 342         {
 343             "PL3_NV12",
 344             PP_PL3_LOAD_SAVE_N12,
 345             pp_pl3_load_save_nv12_gen6,
 346             sizeof(pp_pl3_load_save_nv12_gen6),
 347             NULL,
 348         },
 349
 350         pp_plx_load_save_plx_initialize,
 351     },
 352
 353     {
 354         {
 355             "PL3_PL3",
 356             PP_PL3_LOAD_SAVE_N12,
 357             pp_pl3_load_save_pl3_gen6,
 358             sizeof(pp_pl3_load_save_pl3_gen6),
 359             NULL,
 360         },
 361
 362         pp_plx_load_save_plx_initialize,
 363     },
 364
 365     {
 366         {
 367             "NV12 Scaling module",
 368             PP_NV12_SCALING,
 369             pp_nv12_scaling_gen6,
 370             sizeof(pp_nv12_scaling_gen6),
 371             NULL,
 372         },
 373
 374         gen6_nv12_scaling_initialize,
 375     },
 376
 377     {
 378         {
 379             "NV12 AVS module",
 380             PP_NV12_AVS,
 381             pp_nv12_avs_gen6,
 382             sizeof(pp_nv12_avs_gen6),
 383             NULL,
 384         },
 385
 386         pp_nv12_avs_initialize_nlas,
 387     },
 388
 389     {
 390         {
 391             "NV12 DNDI module",
 392             PP_NV12_DNDI,
 393             pp_nv12_dndi_gen6,
 394             sizeof(pp_nv12_dndi_gen6),
 395             NULL,
 396         },
 397
 398         pp_nv12_dndi_initialize,
 399     },
 400
 401     {
 402         {
 403             "NV12 DN module",
 404             PP_NV12_DN,
 405             pp_nv12_dn_gen6,
 406             sizeof(pp_nv12_dn_gen6),
 407             NULL,
 408         },
 409
 410         pp_nv12_dn_initialize,
 411     },
 412     {
 413         {
 414             "NV12_PA module",
 415             PP_NV12_LOAD_SAVE_PA,
 416             pp_nv12_load_save_pa_gen6,
 417             sizeof(pp_nv12_load_save_pa_gen6),
 418             NULL,
 419         },
 420
 421         pp_plx_load_save_plx_initialize,
 422     },
 423
 424
 425 };
 426
 427 static const uint32_t pp_null_gen7[][4] = {
 428 };
 429
 430 static const uint32_t pp_nv12_load_save_nv12_gen7[][4] = {
 431 #include "shaders/post_processing/gen7/pl2_to_pl2.g7b"
 432 };
 433
 434 static const uint32_t pp_nv12_load_save_pl3_gen7[][4] = {
 435 #include "shaders/post_processing/gen7/pl2_to_pl3.g7b"
 436 };
 437
 438 static const uint32_t pp_pl3_load_save_nv12_gen7[][4] = {
 439 #include "shaders/post_processing/gen7/pl3_to_pl2.g7b"
 440 };
 441
 442 static const uint32_t pp_pl3_load_save_pl3_gen7[][4] = {
 443 #include "shaders/post_processing/gen7/pl3_to_pl3.g7b"
 444 };
 445
 446 static const uint32_t pp_nv12_scaling_gen7[][4] = {
 447 #include "shaders/post_processing/gen7/avs.g7b"
 448 };
 449
 450 static const uint32_t pp_nv12_avs_gen7[][4] = {
 451 #include "shaders/post_processing/gen7/avs.g7b"
 452 };
 453
 454 static const uint32_t pp_nv12_dndi_gen7[][4] = {
 455 #include "shaders/post_processing/gen7/dndi.g7b"
 456 };
 457
 458 static const uint32_t pp_nv12_dn_gen7[][4] = {
 459 };
 460 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 461 };
 462
 463 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 464                                            const struct i965_surface *src_surface,
 465                                            const VARectangle *src_rect,
 466                                            struct i965_surface *dst_surface,
 467                                            const VARectangle *dst_rect,
 468                                            void *filter_param);
 469 static VAStatus gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 470                                              const struct i965_surface *src_surface,
 471                                              const VARectangle *src_rect,
 472                                              struct i965_surface *dst_surface,
 473                                              const VARectangle *dst_rect,
 474                                              void *filter_param);
 475 static VAStatus gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 476                                            const struct i965_surface *src_surface,
 477                                            const VARectangle *src_rect,
 478                                            struct i965_surface *dst_surface,
 479                                            const VARectangle *dst_rect,
 480                                            void *filter_param);
 481
 482 static struct pp_module pp_modules_gen7[] = {
 483     {
 484         {
 485             "NULL module (for testing)",
 486             PP_NULL,
 487             pp_null_gen7,
 488             sizeof(pp_null_gen7),
 489             NULL,
 490         },
 491
 492         pp_null_initialize,
 493     },
 494
 495     {
 496         {
 497             "NV12_NV12",
 498             PP_NV12_LOAD_SAVE_N12,
 499             pp_nv12_load_save_nv12_gen7,
 500             sizeof(pp_nv12_load_save_nv12_gen7),
 501             NULL,
 502         },
 503
 504         gen7_pp_plx_avs_initialize,
 505     },
 506
 507     {
 508         {
 509             "NV12_PL3",
 510             PP_NV12_LOAD_SAVE_PL3,
 511             pp_nv12_load_save_pl3_gen7,
 512             sizeof(pp_nv12_load_save_pl3_gen7),
 513             NULL,
 514         },
 515
 516         gen7_pp_plx_avs_initialize,
 517     },
 518
 519     {
 520         {
 521             "PL3_NV12",
 522             PP_PL3_LOAD_SAVE_N12,
 523             pp_pl3_load_save_nv12_gen7,
 524             sizeof(pp_pl3_load_save_nv12_gen7),
 525             NULL,
 526         },
 527
 528         gen7_pp_plx_avs_initialize,
 529     },
 530
 531     {
 532         {
 533             "PL3_PL3",
 534             PP_PL3_LOAD_SAVE_N12,
 535             pp_pl3_load_save_pl3_gen7,
 536             sizeof(pp_pl3_load_save_pl3_gen7),
 537             NULL,
 538         },
 539
 540         gen7_pp_plx_avs_initialize,
 541     },
 542
 543     {
 544         {
 545             "NV12 Scaling module",
 546             PP_NV12_SCALING,
 547             pp_nv12_scaling_gen7,
 548             sizeof(pp_nv12_scaling_gen7),
 549             NULL,
 550         },
 551
 552         gen7_pp_plx_avs_initialize,
 553     },
 554
 555     {
 556         {
 557             "NV12 AVS module",
 558             PP_NV12_AVS,
 559             pp_nv12_avs_gen7,
 560             sizeof(pp_nv12_avs_gen7),
 561             NULL,
 562         },
 563
 564         gen7_pp_plx_avs_initialize,
 565     },
 566
 567     {
 568         {
 569             "NV12 DNDI module",
 570             PP_NV12_DNDI,
 571             pp_nv12_dndi_gen7,
 572             sizeof(pp_nv12_dndi_gen7),
 573             NULL,
 574         },
 575
 576         gen7_pp_nv12_dndi_initialize,
 577     },
 578
 579     {
 580         {
 581             "NV12 DN module",
 582             PP_NV12_DN,
 583             pp_nv12_dn_gen7,
 584             sizeof(pp_nv12_dn_gen7),
 585             NULL,
 586         },
 587
 588         gen7_pp_nv12_dn_initialize,
 589     },
 590     {
 591         {
 592             "NV12_PA module",
 593             PP_NV12_LOAD_SAVE_PA,
 594             pp_nv12_load_save_pa_gen7,
 595             sizeof(pp_nv12_load_save_pa_gen7),
 596             NULL,
 597         },
 598
 599         pp_plx_load_save_plx_initialize,
 600     },
 601
 602 };
 603
 604 static int
 605 pp_get_surface_fourcc(VADriverContextP ctx, const struct i965_surface *surface)
 606 {
 607     struct i965_driver_data *i965 = i965_driver_data(ctx);
 608     int fourcc;
 609
 610     if (surface->type == I965_SURFACE_TYPE_IMAGE) {
 611         struct object_image *obj_image = IMAGE(surface->id);
 612         fourcc = obj_image->image.format.fourcc;
 613     } else {
 614         struct object_surface *obj_surface = SURFACE(surface->id);
 615         fourcc = obj_surface->fourcc;
 616     }
 617
 618     return fourcc;
 619 }
 620
 621 static void
 622 pp_set_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 623 {
 624     switch (tiling) {
 625     case I915_TILING_NONE:
 626         ss->ss3.tiled_surface = 0;
 627         ss->ss3.tile_walk = 0;
 628         break;
 629     case I915_TILING_X:
 630         ss->ss3.tiled_surface = 1;
 631         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 632         break;
 633     case I915_TILING_Y:
 634         ss->ss3.tiled_surface = 1;
 635         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 636         break;
 637     }
 638 }
 639
 640 static void
 641 pp_set_surface2_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 642 {
 643     switch (tiling) {
 644     case I915_TILING_NONE:
 645         ss->ss2.tiled_surface = 0;
 646         ss->ss2.tile_walk = 0;
 647         break;
 648     case I915_TILING_X:
 649         ss->ss2.tiled_surface = 1;
 650         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 651         break;
 652     case I915_TILING_Y:
 653         ss->ss2.tiled_surface = 1;
 654         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 655         break;
 656     }
 657 }
 658
 659 static void
 660 gen7_pp_set_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 661 {
 662     switch (tiling) {
 663     case I915_TILING_NONE:
 664         ss->ss0.tiled_surface = 0;
 665         ss->ss0.tile_walk = 0;
 666         break;
 667     case I915_TILING_X:
 668         ss->ss0.tiled_surface = 1;
 669         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 670         break;
 671     case I915_TILING_Y:
 672         ss->ss0.tiled_surface = 1;
 673         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 674         break;
 675     }
 676 }
 677
 678 static void
 679 gen7_pp_set_surface2_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 680 {
 681     switch (tiling) {
 682     case I915_TILING_NONE:
 683         ss->ss2.tiled_surface = 0;
 684         ss->ss2.tile_walk = 0;
 685         break;
 686     case I915_TILING_X:
 687         ss->ss2.tiled_surface = 1;
 688         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 689         break;
 690     case I915_TILING_Y:
 691         ss->ss2.tiled_surface = 1;
 692         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 693         break;
 694     }
 695 }
 696
 697 static void
 698 ironlake_pp_interface_descriptor_table(struct i965_post_processing_context *pp_context)
 699 {
 700     struct i965_interface_descriptor *desc;
 701     dri_bo *bo;
 702     int pp_index = pp_context->current_pp;
 703
 704     bo = pp_context->idrt.bo;
 705     dri_bo_map(bo, 1);
 706     assert(bo->virtual);
 707     desc = bo->virtual;
 708     memset(desc, 0, sizeof(*desc));
 709     desc->desc0.grf_reg_blocks = 10;
 710     desc->desc0.kernel_start_pointer = pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
 711     desc->desc1.const_urb_entry_read_offset = 0;
 712     desc->desc1.const_urb_entry_read_len = 4; /* grf 1-4 */
 713     desc->desc2.sampler_state_pointer = pp_context->sampler_state_table.bo->offset >> 5;
 714     desc->desc2.sampler_count = 0;
 715     desc->desc3.binding_table_entry_count = 0;
 716     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 717
 718     dri_bo_emit_reloc(bo,
 719                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 720                       desc->desc0.grf_reg_blocks,
 721                       offsetof(struct i965_interface_descriptor, desc0),
 722                       pp_context->pp_modules[pp_index].kernel.bo);
 723
 724     dri_bo_emit_reloc(bo,
 725                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 726                       desc->desc2.sampler_count << 2,
 727                       offsetof(struct i965_interface_descriptor, desc2),
 728                       pp_context->sampler_state_table.bo);
 729
 730     dri_bo_unmap(bo);
 731     pp_context->idrt.num_interface_descriptors++;
 732 }
 733
 734 static void
 735 ironlake_pp_vfe_state(struct i965_post_processing_context *pp_context)
 736 {
 737     struct i965_vfe_state *vfe_state;
 738     dri_bo *bo;
 739
 740     bo = pp_context->vfe_state.bo;
 741     dri_bo_map(bo, 1);
 742     assert(bo->virtual);
 743     vfe_state = bo->virtual;
 744     memset(vfe_state, 0, sizeof(*vfe_state));
 745     vfe_state->vfe1.max_threads = pp_context->urb.num_vfe_entries - 1;
 746     vfe_state->vfe1.urb_entry_alloc_size = pp_context->urb.size_vfe_entry - 1;
 747     vfe_state->vfe1.num_urb_entries = pp_context->urb.num_vfe_entries;
 748     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 749     vfe_state->vfe1.children_present = 0;
 750     vfe_state->vfe2.interface_descriptor_base =
 751         pp_context->idrt.bo->offset >> 4; /* reloc */
 752     dri_bo_emit_reloc(bo,
 753                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 754                       0,
 755                       offsetof(struct i965_vfe_state, vfe2),
 756                       pp_context->idrt.bo);
 757     dri_bo_unmap(bo);
 758 }
 759
 760 static void
 761 ironlake_pp_upload_constants(struct i965_post_processing_context *pp_context)
 762 {
 763     unsigned char *constant_buffer;
 764     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
 765
 766     assert(sizeof(*pp_static_parameter) == 128);
 767     dri_bo_map(pp_context->curbe.bo, 1);
 768     assert(pp_context->curbe.bo->virtual);
 769     constant_buffer = pp_context->curbe.bo->virtual;
 770     memcpy(constant_buffer, pp_static_parameter, sizeof(*pp_static_parameter));
 771     dri_bo_unmap(pp_context->curbe.bo);
 772 }
 773
 774 static void
 775 ironlake_pp_states_setup(VADriverContextP ctx,
 776                          struct i965_post_processing_context *pp_context)
 777 {
 778     ironlake_pp_interface_descriptor_table(pp_context);
 779     ironlake_pp_vfe_state(pp_context);
 780     ironlake_pp_upload_constants(pp_context);
 781 }
 782
 783 static void
 784 ironlake_pp_pipeline_select(VADriverContextP ctx,
 785                             struct i965_post_processing_context *pp_context)
 786 {
 787     struct intel_batchbuffer *batch = pp_context->batch;
 788
 789     BEGIN_BATCH(batch, 1);
 790     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 791     ADVANCE_BATCH(batch);
 792 }
 793
 794 static void
 795 ironlake_pp_urb_layout(VADriverContextP ctx,
 796                        struct i965_post_processing_context *pp_context)
 797 {
 798     struct intel_batchbuffer *batch = pp_context->batch;
 799     unsigned int vfe_fence, cs_fence;
 800
 801     vfe_fence = pp_context->urb.cs_start;
 802     cs_fence = pp_context->urb.size;
 803
 804     BEGIN_BATCH(batch, 3);
 805     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 806     OUT_BATCH(batch, 0);
 807     OUT_BATCH(batch,
 808               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 809               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 810     ADVANCE_BATCH(batch);
 811 }
 812
 813 static void
 814 ironlake_pp_state_base_address(VADriverContextP ctx,
 815                                struct i965_post_processing_context *pp_context)
 816 {
 817     struct intel_batchbuffer *batch = pp_context->batch;
 818
 819     BEGIN_BATCH(batch, 8);
 820     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 821     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 822     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 823     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 824     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 825     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 826     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 827     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 828     ADVANCE_BATCH(batch);
 829 }
 830
 831 static void
 832 ironlake_pp_state_pointers(VADriverContextP ctx,
 833                            struct i965_post_processing_context *pp_context)
 834 {
 835     struct intel_batchbuffer *batch = pp_context->batch;
 836
 837     BEGIN_BATCH(batch, 3);
 838     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 839     OUT_BATCH(batch, 0);
 840     OUT_RELOC(batch, pp_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 841     ADVANCE_BATCH(batch);
 842 }
 843
 844 static void
 845 ironlake_pp_cs_urb_layout(VADriverContextP ctx,
 846                           struct i965_post_processing_context *pp_context)
 847 {
 848     struct intel_batchbuffer *batch = pp_context->batch;
 849
 850     BEGIN_BATCH(batch, 2);
 851     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 852     OUT_BATCH(batch,
 853               ((pp_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 854               (pp_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 855     ADVANCE_BATCH(batch);
 856 }
 857
 858 static void
 859 ironlake_pp_constant_buffer(VADriverContextP ctx,
 860                             struct i965_post_processing_context *pp_context)
 861 {
 862     struct intel_batchbuffer *batch = pp_context->batch;
 863
 864     BEGIN_BATCH(batch, 2);
 865     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 866     OUT_RELOC(batch, pp_context->curbe.bo,
 867               I915_GEM_DOMAIN_INSTRUCTION, 0,
 868               pp_context->urb.size_cs_entry - 1);
 869     ADVANCE_BATCH(batch);
 870 }
 871
 872 static void
 873 ironlake_pp_object_walker(VADriverContextP ctx,
 874                           struct i965_post_processing_context *pp_context)
 875 {
 876     struct intel_batchbuffer *batch = pp_context->batch;
 877     int x, x_steps, y, y_steps;
 878     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
 879
 880     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
 881     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
 882
 883     for (y = 0; y < y_steps; y++) {
 884         for (x = 0; x < x_steps; x++) {
 885             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
 886                 BEGIN_BATCH(batch, 20);
 887                 OUT_BATCH(batch, CMD_MEDIA_OBJECT | 18);
 888                 OUT_BATCH(batch, 0);
 889                 OUT_BATCH(batch, 0); /* no indirect data */
 890                 OUT_BATCH(batch, 0);
 891
 892                 /* inline data grf 5-6 */
 893                 assert(sizeof(*pp_inline_parameter) == 64);
 894                 intel_batchbuffer_data(batch, pp_inline_parameter, sizeof(*pp_inline_parameter));
 895
 896                 ADVANCE_BATCH(batch);
 897             }
 898         }
 899     }
 900 }
 901
 902 static void
 903 ironlake_pp_pipeline_setup(VADriverContextP ctx,
 904                            struct i965_post_processing_context *pp_context)
 905 {
 906     struct intel_batchbuffer *batch = pp_context->batch;
 907
 908     intel_batchbuffer_start_atomic(batch, 0x1000);
 909     intel_batchbuffer_emit_mi_flush(batch);
 910     ironlake_pp_pipeline_select(ctx, pp_context);
 911     ironlake_pp_state_base_address(ctx, pp_context);
 912     ironlake_pp_state_pointers(ctx, pp_context);
 913     ironlake_pp_urb_layout(ctx, pp_context);
 914     ironlake_pp_cs_urb_layout(ctx, pp_context);
 915     ironlake_pp_constant_buffer(ctx, pp_context);
 916     ironlake_pp_object_walker(ctx, pp_context);
 917     intel_batchbuffer_end_atomic(batch);
 918 }
 919
 920 static void
 921 i965_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 922                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 923                           int width, int height, int pitch, int format,
 924                           int index, int is_target)
 925 {
 926     struct i965_surface_state *ss;
 927     dri_bo *ss_bo;
 928     unsigned int tiling;
 929     unsigned int swizzle;
 930
 931     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 932     ss_bo = pp_context->surface_state_binding_table.bo;
 933     assert(ss_bo);
 934
 935     dri_bo_map(ss_bo, True);
 936     assert(ss_bo->virtual);
 937     ss = (struct i965_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
 938     memset(ss, 0, sizeof(*ss));
 939     ss->ss0.surface_type = I965_SURFACE_2D;
 940     ss->ss0.surface_format = format;
 941     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
 942     ss->ss2.width = width - 1;
 943     ss->ss2.height = height - 1;
 944     ss->ss3.pitch = pitch - 1;
 945     pp_set_surface_tiling(ss, tiling);
 946     dri_bo_emit_reloc(ss_bo,
 947                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
 948                       surf_bo_offset,
 949                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 950                       surf_bo);
 951     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 952     dri_bo_unmap(ss_bo);
 953 }
 954
 955 static void
 956 i965_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 957                            dri_bo *surf_bo, unsigned long surf_bo_offset,
 958                            int width, int height, int wpitch,
 959                            int xoffset, int yoffset,
 960                            int format, int interleave_chroma,
 961                            int index)
 962 {
 963     struct i965_surface_state2 *ss2;
 964     dri_bo *ss2_bo;
 965     unsigned int tiling;
 966     unsigned int swizzle;
 967
 968     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
 969     ss2_bo = pp_context->surface_state_binding_table.bo;
 970     assert(ss2_bo);
 971
 972     dri_bo_map(ss2_bo, True);
 973     assert(ss2_bo->virtual);
 974     ss2 = (struct i965_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
 975     memset(ss2, 0, sizeof(*ss2));
 976     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
 977     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
 978     ss2->ss1.width = width - 1;
 979     ss2->ss1.height = height - 1;
 980     ss2->ss2.pitch = wpitch - 1;
 981     ss2->ss2.interleave_chroma = interleave_chroma;
 982     ss2->ss2.surface_format = format;
 983     ss2->ss3.x_offset_for_cb = xoffset;
 984     ss2->ss3.y_offset_for_cb = yoffset;
 985     pp_set_surface2_tiling(ss2, tiling);
 986     dri_bo_emit_reloc(ss2_bo,
 987                       I915_GEM_DOMAIN_RENDER, 0,
 988                       surf_bo_offset,
 989                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
 990                       surf_bo);
 991     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 992     dri_bo_unmap(ss2_bo);
 993 }
 994
 995 static void
 996 gen7_pp_set_surface_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 997                           dri_bo *surf_bo, unsigned long surf_bo_offset,
 998                           int width, int height, int pitch, int format,
 999                           int index, int is_target)
1000 {
1001     struct gen7_surface_state *ss;
1002     dri_bo *ss_bo;
1003     unsigned int tiling;
1004     unsigned int swizzle;
1005
1006     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1007     ss_bo = pp_context->surface_state_binding_table.bo;
1008     assert(ss_bo);
1009
1010     dri_bo_map(ss_bo, True);
1011     assert(ss_bo->virtual);
1012     ss = (struct gen7_surface_state *)((char *)ss_bo->virtual + SURFACE_STATE_OFFSET(index));
1013     memset(ss, 0, sizeof(*ss));
1014     ss->ss0.surface_type = I965_SURFACE_2D;
1015     ss->ss0.surface_format = format;
1016     ss->ss1.base_addr = surf_bo->offset + surf_bo_offset;
1017     ss->ss2.width = width - 1;
1018     ss->ss2.height = height - 1;
1019     ss->ss3.pitch = pitch - 1;
1020     gen7_pp_set_surface_tiling(ss, tiling);
1021     dri_bo_emit_reloc(ss_bo,
1022                       I915_GEM_DOMAIN_RENDER, is_target ? I915_GEM_DOMAIN_RENDER : 0,
1023                       surf_bo_offset,
1024                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
1025                       surf_bo);
1026     ((unsigned int *)((char *)ss_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1027     dri_bo_unmap(ss_bo);
1028 }
1029
1030 static void
1031 gen7_pp_set_surface2_state(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1032                            dri_bo *surf_bo, unsigned long surf_bo_offset,
1033                            int width, int height, int wpitch,
1034                            int xoffset, int yoffset,
1035                            int format, int interleave_chroma,
1036                            int index)
1037 {
1038     struct gen7_surface_state2 *ss2;
1039     dri_bo *ss2_bo;
1040     unsigned int tiling;
1041     unsigned int swizzle;
1042
1043     dri_bo_get_tiling(surf_bo, &tiling, &swizzle);
1044     ss2_bo = pp_context->surface_state_binding_table.bo;
1045     assert(ss2_bo);
1046
1047     dri_bo_map(ss2_bo, True);
1048     assert(ss2_bo->virtual);
1049     ss2 = (struct gen7_surface_state2 *)((char *)ss2_bo->virtual + SURFACE_STATE_OFFSET(index));
1050     memset(ss2, 0, sizeof(*ss2));
1051     ss2->ss0.surface_base_address = surf_bo->offset + surf_bo_offset;
1052     ss2->ss1.cbcr_pixel_offset_v_direction = 0;
1053     ss2->ss1.width = width - 1;
1054     ss2->ss1.height = height - 1;
1055     ss2->ss2.pitch = wpitch - 1;
1056     ss2->ss2.interleave_chroma = interleave_chroma;
1057     ss2->ss2.surface_format = format;
1058     ss2->ss3.x_offset_for_cb = xoffset;
1059     ss2->ss3.y_offset_for_cb = yoffset;
1060     gen7_pp_set_surface2_tiling(ss2, tiling);
1061     dri_bo_emit_reloc(ss2_bo,
1062                       I915_GEM_DOMAIN_RENDER, 0,
1063                       surf_bo_offset,
1064                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
1065                       surf_bo);
1066     ((unsigned int *)((char *)ss2_bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
1067     dri_bo_unmap(ss2_bo);
1068 }
1069
1070 static void
1071 pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1072                                 const struct i965_surface *surface,
1073                                 int base_index, int is_target,
1074                                 int *width, int *height, int *pitch, int *offset)
1075 {
1076     struct i965_driver_data *i965 = i965_driver_data(ctx);
1077     struct object_surface *obj_surface;
1078     struct object_image *obj_image;
1079     dri_bo *bo;
1080     int fourcc = pp_get_surface_fourcc(ctx, surface);
1081     const int Y = 0;
1082     const int U = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 2 : 1;
1083     const int V = fourcc == VA_FOURCC('Y', 'V', '1', '2') ? 1 : 2;
1084     const int UV = 1;
1085     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1086     int packed_yuv = (fourcc == VA_FOURCC('Y', 'U', 'Y', '2') || fourcc == VA_FOURCC('U', 'Y', 'V', 'Y'));
1087
1088     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1089         obj_surface = SURFACE(surface->id);
1090         bo = obj_surface->bo;
1091         width[0] = obj_surface->orig_width;
1092         height[0] = obj_surface->orig_height;
1093         pitch[0] = obj_surface->width;
1094         offset[0] = 0;
1095
1096         if (packed_yuv ) {
1097             width[0] = obj_surface->orig_width * 2;
1098             pitch[0] = obj_surface->width * 2;
1099         }
1100         else if (interleaved_uv) {
1101             width[1] = obj_surface->orig_width;
1102             height[1] = obj_surface->orig_height / 2;
1103             pitch[1] = obj_surface->width;
1104             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1105         } else {
1106             width[1] = obj_surface->orig_width / 2;
1107             height[1] = obj_surface->orig_height / 2;
1108             pitch[1] = obj_surface->width / 2;
1109             offset[1] = offset[0] + obj_surface->width * obj_surface->height;
1110             width[2] = obj_surface->orig_width / 2;
1111             height[2] = obj_surface->orig_height / 2;
1112             pitch[2] = obj_surface->width / 2;
1113             offset[2] = offset[1] + (obj_surface->width / 2) * (obj_surface->height / 2);
1114         }
1115     } else {
1116         obj_image = IMAGE(surface->id);
1117         bo = obj_image->bo;
1118         width[0] = obj_image->image.width;
1119         height[0] = obj_image->image.height;
1120         pitch[0] = obj_image->image.pitches[0];
1121         offset[0] = obj_image->image.offsets[0];
1122
1123         if (interleaved_uv) {
1124             width[1] = obj_image->image.width;
1125             height[1] = obj_image->image.height / 2;
1126             pitch[1] = obj_image->image.pitches[1];
1127             offset[1] = obj_image->image.offsets[1];
1128         } else {
1129             width[1] = obj_image->image.width / 2;
1130             height[1] = obj_image->image.height / 2;
1131             pitch[1] = obj_image->image.pitches[1];
1132             offset[1] = obj_image->image.offsets[1];
1133             width[2] = obj_image->image.width / 2;
1134             height[2] = obj_image->image.height / 2;
1135             pitch[2] = obj_image->image.pitches[2];
1136             offset[2] = obj_image->image.offsets[2];
1137         }
1138     }
1139
1140     /* Y surface */
1141     i965_pp_set_surface_state(ctx, pp_context,
1142                               bo, offset[Y],
1143                               width[Y] / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
1144                               base_index, is_target);
1145
1146     if (!packed_yuv) {
1147         if (interleaved_uv) {
1148             i965_pp_set_surface_state(ctx, pp_context,
1149                                       bo, offset[UV],
1150                                       width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
1151                                       base_index + 1, is_target);
1152         } else {
1153             /* U surface */
1154             i965_pp_set_surface_state(ctx, pp_context,
1155                                       bo, offset[U],
1156                                       width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
1157                                       base_index + 1, is_target);
1158
1159             /* V surface */
1160             i965_pp_set_surface_state(ctx, pp_context,
1161                                       bo, offset[V],
1162                                       width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
1163                                       base_index + 2, is_target);
1164         }
1165     }
1166
1167 }
1168
1169 static void
1170 gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1171                                      const struct i965_surface *surface,
1172                                      int base_index, int is_target,
1173                                      int *width, int *height, int *pitch, int *offset)
1174 {
1175     struct i965_driver_data *i965 = i965_driver_data(ctx);
1176     struct object_surface *obj_surface;
1177     struct object_image *obj_image;
1178     dri_bo *bo;
1179     int fourcc = pp_get_surface_fourcc(ctx, surface);
1180     const int U = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1181                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 2 : 1;
1182     const int V = (fourcc == VA_FOURCC('Y', 'V', '1', '2') ||
1183                    fourcc == VA_FOURCC('I', 'M', 'C', '1')) ? 1 : 2;
1184     int interleaved_uv = fourcc == VA_FOURCC('N', 'V', '1', '2');
1185
1186     if (surface->type == I965_SURFACE_TYPE_SURFACE) {
1187         obj_surface = SURFACE(surface->id);
1188         bo = obj_surface->bo;
1189         width[0] = obj_surface->orig_width;
1190         height[0] = obj_surface->orig_height;
1191         pitch[0] = obj_surface->width;
1192         offset[0] = 0;
1193
1194         width[1] = obj_surface->cb_cr_width;
1195         height[1] = obj_surface->cb_cr_height;
1196         pitch[1] = obj_surface->cb_cr_pitch;
1197         offset[1] = obj_surface->y_cb_offset * obj_surface->width;
1198
1199         width[2] = obj_surface->cb_cr_width;
1200         height[2] = obj_surface->cb_cr_height;
1201         pitch[2] = obj_surface->cb_cr_pitch;
1202         offset[2] = obj_surface->y_cr_offset * obj_surface->width;
1203     } else {
1204         obj_image = IMAGE(surface->id);
1205         bo = obj_image->bo;
1206         width[0] = obj_image->image.width;
1207         height[0] = obj_image->image.height;
1208         pitch[0] = obj_image->image.pitches[0];
1209         offset[0] = obj_image->image.offsets[0];
1210
1211         if (interleaved_uv) {
1212             width[1] = obj_image->image.width;
1213             height[1] = obj_image->image.height / 2;
1214             pitch[1] = obj_image->image.pitches[1];
1215             offset[1] = obj_image->image.offsets[1];
1216         } else {
1217             width[1] = obj_image->image.width / 2;
1218             height[1] = obj_image->image.height / 2;
1219             pitch[1] = obj_image->image.pitches[U];
1220             offset[1] = obj_image->image.offsets[U];
1221             width[2] = obj_image->image.width / 2;
1222             height[2] = obj_image->image.height / 2;
1223             pitch[2] = obj_image->image.pitches[V];
1224             offset[2] = obj_image->image.offsets[V];
1225         }
1226     }
1227
1228     if (is_target) {
1229         gen7_pp_set_surface_state(ctx, pp_context,
1230                                   bo, 0,
1231                                   width[0] / 4, height[0], pitch[0],
1232                                   I965_SURFACEFORMAT_R8_SINT,
1233                                   base_index, 1);
1234
1235         if (interleaved_uv) {
1236             gen7_pp_set_surface_state(ctx, pp_context,
1237                                       bo, offset[1],
1238                                       width[1] / 2, height[1], pitch[1],
1239                                       I965_SURFACEFORMAT_R8G8_SINT,
1240                                       base_index + 1, 1);
1241         } else {
1242             gen7_pp_set_surface_state(ctx, pp_context,
1243                                       bo, offset[1],
1244                                       width[1] / 4, height[1], pitch[1],
1245                                       I965_SURFACEFORMAT_R8_SINT,
1246                                       base_index + 1, 1);
1247             gen7_pp_set_surface_state(ctx, pp_context,
1248                                       bo, offset[2],
1249                                       width[2] / 4, height[2], pitch[2],
1250                                       I965_SURFACEFORMAT_R8_SINT,
1251                                       base_index + 2, 1);
1252         }
1253     } else {
1254         gen7_pp_set_surface2_state(ctx, pp_context,
1255                                    bo, offset[0],
1256                                    width[0], height[0], pitch[0],
1257                                    0, 0,
1258                                    SURFACE_FORMAT_Y8_UNORM, 0,
1259                                    base_index);
1260
1261         if (interleaved_uv) {
1262             gen7_pp_set_surface2_state(ctx, pp_context,
1263                                        bo, offset[1],
1264                                        width[1], height[1], pitch[1],
1265                                        0, 0,
1266                                        SURFACE_FORMAT_R8B8_UNORM, 0,
1267                                        base_index + 1);
1268         } else {
1269             gen7_pp_set_surface2_state(ctx, pp_context,
1270                                        bo, offset[1],
1271                                        width[1], height[1], pitch[1],
1272                                        0, 0,
1273                                        SURFACE_FORMAT_R8_UNORM, 0,
1274                                        base_index + 1);
1275             gen7_pp_set_surface2_state(ctx, pp_context,
1276                                        bo, offset[2],
1277                                        width[2], height[2], pitch[2],
1278                                        0, 0,
1279                                        SURFACE_FORMAT_R8_UNORM, 0,
1280                                        base_index + 2);
1281         }
1282     }
1283 }
1284
1285 static int
1286 pp_null_x_steps(void *private_context)
1287 {
1288     return 1;
1289 }
1290
1291 static int
1292 pp_null_y_steps(void *private_context)
1293 {
1294     return 1;
1295 }
1296
1297 static int
1298 pp_null_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1299 {
1300     return 0;
1301 }
1302
1303 static VAStatus
1304 pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1305                    const struct i965_surface *src_surface,
1306                    const VARectangle *src_rect,
1307                    struct i965_surface *dst_surface,
1308                    const VARectangle *dst_rect,
1309                    void *filter_param)
1310 {
1311     /* private function & data */
1312     pp_context->pp_x_steps = pp_null_x_steps;
1313     pp_context->pp_y_steps = pp_null_y_steps;
1314     pp_context->pp_set_block_parameter = pp_null_set_block_parameter;
1315
1316     dst_surface->flags = src_surface->flags;
1317
1318     return VA_STATUS_SUCCESS;
1319 }
1320
1321 static int
1322 pp_load_save_x_steps(void *private_context)
1323 {
1324     return 1;
1325 }
1326
1327 static int
1328 pp_load_save_y_steps(void *private_context)
1329 {
1330     struct pp_load_save_context *pp_load_save_context = private_context;
1331
1332     return pp_load_save_context->dest_h / 8;
1333 }
1334
1335 static int
1336 pp_load_save_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1337 {
1338     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1339
1340     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1341     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1342     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
1343     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
1344
1345     return 0;
1346 }
1347
1348 static VAStatus
1349 pp_plx_load_save_plx_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1350                                 const struct i965_surface *src_surface,
1351                                 const VARectangle *src_rect,
1352                                 struct i965_surface *dst_surface,
1353                                 const VARectangle *dst_rect,
1354                                 void *filter_param)
1355 {
1356     struct pp_load_save_context *pp_load_save_context = (struct pp_load_save_context *)&pp_context->private_context;
1357     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1358     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1359     int width[3], height[3], pitch[3], offset[3];
1360     const int Y = 0;
1361
1362     /* source surface */
1363     pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 1, 0,
1364                                     width, height, pitch, offset);
1365
1366     /* destination surface */
1367     pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 7, 1,
1368                                     width, height, pitch, offset);
1369
1370     /* private function & data */
1371     pp_context->pp_x_steps = pp_load_save_x_steps;
1372     pp_context->pp_y_steps = pp_load_save_y_steps;
1373     pp_context->pp_set_block_parameter = pp_load_save_set_block_parameter;
1374     pp_load_save_context->dest_h = ALIGN(height[Y], 16);
1375     pp_load_save_context->dest_w = ALIGN(width[Y], 16);
1376
1377     pp_inline_parameter->grf5.block_count_x = ALIGN(width[Y], 16) / 16;   /* 1 x N */
1378     pp_inline_parameter->grf5.number_blocks = ALIGN(width[Y], 16) / 16;
1379
1380     pp_static_parameter->grf3.horizontal_origin_offset = src_rect->x;
1381     pp_static_parameter->grf3.vertical_origin_offset = src_rect->y;
1382
1383     dst_surface->flags = src_surface->flags;
1384
1385     return VA_STATUS_SUCCESS;
1386 }
1387
1388 static int
1389 pp_scaling_x_steps(void *private_context)
1390 {
1391     return 1;
1392 }
1393
1394 static int
1395 pp_scaling_y_steps(void *private_context)
1396 {
1397     struct pp_scaling_context *pp_scaling_context = private_context;
1398
1399     return pp_scaling_context->dest_h / 8;
1400 }
1401
1402 static int
1403 pp_scaling_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1404 {
1405     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1406     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1407     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1408     float src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1409     float src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1410
1411     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_scaling_context->src_normalized_x;
1412     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_scaling_context->src_normalized_y;
1413     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_scaling_context->dest_x;
1414     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_scaling_context->dest_y;
1415
1416     return 0;
1417 }
1418
1419 static VAStatus
1420 pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1421                            const struct i965_surface *src_surface,
1422                            const VARectangle *src_rect,
1423                            struct i965_surface *dst_surface,
1424                            const VARectangle *dst_rect,
1425                            void *filter_param)
1426 {
1427     struct i965_driver_data *i965 = i965_driver_data(ctx);
1428     struct pp_scaling_context *pp_scaling_context = (struct pp_scaling_context *)&pp_context->private_context;
1429     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1430     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1431     struct object_surface *obj_surface;
1432     struct i965_sampler_state *sampler_state;
1433     int in_w, in_h, in_wpitch, in_hpitch;
1434     int out_w, out_h, out_wpitch, out_hpitch;
1435
1436     /* source surface */
1437     obj_surface = SURFACE(src_surface->id);
1438     in_w = obj_surface->orig_width;
1439     in_h = obj_surface->orig_height;
1440     in_wpitch = obj_surface->width;
1441     in_hpitch = obj_surface->height;
1442
1443     /* source Y surface index 1 */
1444     i965_pp_set_surface_state(ctx, pp_context,
1445                               obj_surface->bo, 0,
1446                               in_w, in_h, in_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1447                               1, 0);
1448
1449     /* source UV surface index 2 */
1450     i965_pp_set_surface_state(ctx, pp_context,
1451                               obj_surface->bo, in_wpitch * in_hpitch,
1452                               in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1453                               2, 0);
1454
1455     /* destination surface */
1456     obj_surface = SURFACE(dst_surface->id);
1457     out_w = obj_surface->orig_width;
1458     out_h = obj_surface->orig_height;
1459     out_wpitch = obj_surface->width;
1460     out_hpitch = obj_surface->height;
1461
1462     /* destination Y surface index 7 */
1463     i965_pp_set_surface_state(ctx, pp_context,
1464                               obj_surface->bo, 0,
1465                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1466                               7, 1);
1467
1468     /* destination UV surface index 8 */
1469     i965_pp_set_surface_state(ctx, pp_context,
1470                               obj_surface->bo, out_wpitch * out_hpitch,
1471                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1472                               8, 1);
1473
1474     /* sampler state */
1475     dri_bo_map(pp_context->sampler_state_table.bo, True);
1476     assert(pp_context->sampler_state_table.bo->virtual);
1477     sampler_state = pp_context->sampler_state_table.bo->virtual;
1478
1479     /* SIMD16 Y index 1 */
1480     sampler_state[1].ss0.min_filter = I965_MAPFILTER_LINEAR;
1481     sampler_state[1].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1482     sampler_state[1].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1483     sampler_state[1].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1484     sampler_state[1].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1485
1486     /* SIMD16 UV index 2 */
1487     sampler_state[2].ss0.min_filter = I965_MAPFILTER_LINEAR;
1488     sampler_state[2].ss0.mag_filter = I965_MAPFILTER_LINEAR;
1489     sampler_state[2].ss1.r_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1490     sampler_state[2].ss1.s_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1491     sampler_state[2].ss1.t_wrap_mode = I965_TEXCOORDMODE_CLAMP;
1492
1493     dri_bo_unmap(pp_context->sampler_state_table.bo);
1494
1495     /* private function & data */
1496     pp_context->pp_x_steps = pp_scaling_x_steps;
1497     pp_context->pp_y_steps = pp_scaling_y_steps;
1498     pp_context->pp_set_block_parameter = pp_scaling_set_block_parameter;
1499
1500     pp_scaling_context->dest_x = dst_rect->x;
1501     pp_scaling_context->dest_y = dst_rect->y;
1502     pp_scaling_context->dest_w = ALIGN(dst_rect->width, 16);
1503     pp_scaling_context->dest_h = ALIGN(dst_rect->height, 16);
1504     pp_scaling_context->src_normalized_x = (float)src_rect->x / in_w;
1505     pp_scaling_context->src_normalized_y = (float)src_rect->y / in_h;
1506
1507     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1508
1509     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1510     pp_inline_parameter->grf5.block_count_x = pp_scaling_context->dest_w / 16;   /* 1 x N */
1511     pp_inline_parameter->grf5.number_blocks = pp_scaling_context->dest_w / 16;
1512     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1513     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1514
1515     dst_surface->flags = src_surface->flags;
1516
1517     return VA_STATUS_SUCCESS;
1518 }
1519
1520 static int
1521 pp_avs_x_steps(void *private_context)
1522 {
1523     struct pp_avs_context *pp_avs_context = private_context;
1524
1525     return pp_avs_context->dest_w / 16;
1526 }
1527
1528 static int
1529 pp_avs_y_steps(void *private_context)
1530 {
1531     return 1;
1532 }
1533
1534 static int
1535 pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1536 {
1537     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1538     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1539     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1540     float src_x_steping, src_y_steping, video_step_delta;
1541     int tmp_w = ALIGN(pp_avs_context->dest_h * pp_avs_context->src_w / pp_avs_context->src_h, 16);
1542
1543     if (pp_static_parameter->grf4.r4_2.avs.nlas == 0) {
1544         src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1545         pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = src_x_steping * x * 16 + pp_avs_context->src_normalized_x;
1546     } else if (tmp_w >= pp_avs_context->dest_w) {
1547         pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1548         pp_inline_parameter->grf6.video_step_delta = 0;
1549
1550         if (x == 0) {
1551             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = (float)(tmp_w - pp_avs_context->dest_w) / tmp_w / 2 +
1552                 pp_avs_context->src_normalized_x;
1553         } else {
1554             src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1555             video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1556             pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1557                 16 * 15 * video_step_delta / 2;
1558         }
1559     } else {
1560         int n0, n1, n2, nls_left, nls_right;
1561         int factor_a = 5, factor_b = 4;
1562         float f;
1563
1564         n0 = (pp_avs_context->dest_w - tmp_w) / (16 * 2);
1565         n1 = (pp_avs_context->dest_w - tmp_w) / 16 - n0;
1566         n2 = tmp_w / (16 * factor_a);
1567         nls_left = n0 + n2;
1568         nls_right = n1 + n2;
1569         f = (float) n2 * 16 / tmp_w;
1570
1571         if (n0 < 5) {
1572             pp_inline_parameter->grf6.video_step_delta = 0.0;
1573
1574             if (x == 0) {
1575                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / pp_avs_context->dest_w;
1576                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1577             } else {
1578                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1579                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1580                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1581                     16 * 15 * video_step_delta / 2;
1582             }
1583         } else {
1584             if (x < nls_left) {
1585                 /* f = a * nls_left * 16 + b * nls_left * 16 * (nls_left * 16 - 1) / 2 */
1586                 float a = f / (nls_left * 16 * factor_b);
1587                 float b = (f - nls_left * 16 * a) * 2 / (nls_left * 16 * (nls_left * 16 - 1));
1588
1589                 pp_inline_parameter->grf6.video_step_delta = b;
1590
1591                 if (x == 0) {
1592                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin = pp_avs_context->src_normalized_x;
1593                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a;
1594                 } else {
1595                     src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1596                     video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1597                     pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1598                         16 * 15 * video_step_delta / 2;
1599                     pp_inline_parameter->grf5.normalized_video_x_scaling_step += 16 * b;
1600                 }
1601             } else if (x < (pp_avs_context->dest_w / 16 - nls_right)) {
1602                 /* scale the center linearly */
1603                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1604                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1605                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1606                     16 * 15 * video_step_delta / 2;
1607                 pp_inline_parameter->grf6.video_step_delta = 0.0;
1608                 pp_inline_parameter->grf5.normalized_video_x_scaling_step = 1.0 / tmp_w;
1609             } else {
1610                 float a = f / (nls_right * 16 * factor_b);
1611                 float b = (f - nls_right * 16 * a) * 2 / (nls_right * 16 * (nls_right * 16 - 1));
1612
1613                 src_x_steping = pp_inline_parameter->grf5.normalized_video_x_scaling_step;
1614                 video_step_delta = pp_inline_parameter->grf6.video_step_delta;
1615                 pp_inline_parameter->grf5.r5_1.source_surface_block_normalized_horizontal_origin += src_x_steping * 16 +
1616                     16 * 15 * video_step_delta / 2;
1617                 pp_inline_parameter->grf6.video_step_delta = -b;
1618
1619                 if (x == (pp_avs_context->dest_w / 16 - nls_right))
1620                     pp_inline_parameter->grf5.normalized_video_x_scaling_step = a + (nls_right * 16  - 1) * b;
1621                 else
1622                     pp_inline_parameter->grf5.normalized_video_x_scaling_step -= b * 16;
1623             }
1624         }
1625     }
1626
1627     src_y_steping = pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step;
1628     pp_inline_parameter->grf5.source_surface_block_normalized_vertical_origin = src_y_steping * y * 8 + pp_avs_context->src_normalized_y;
1629     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1630     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8 + pp_avs_context->dest_y;
1631
1632     return 0;
1633 }
1634
1635 static VAStatus
1636 pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1637                        const struct i965_surface *src_surface,
1638                        const VARectangle *src_rect,
1639                        struct i965_surface *dst_surface,
1640                        const VARectangle *dst_rect,
1641                        void *filter_param,
1642                        int nlas)
1643 {
1644     struct i965_driver_data *i965 = i965_driver_data(ctx);
1645     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1646     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1647     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1648     struct object_surface *obj_surface;
1649     struct i965_sampler_8x8 *sampler_8x8;
1650     struct i965_sampler_8x8_state *sampler_8x8_state;
1651     int index;
1652     int in_w, in_h, in_wpitch, in_hpitch;
1653     int out_w, out_h, out_wpitch, out_hpitch;
1654     int i;
1655
1656     /* surface */
1657     obj_surface = SURFACE(src_surface->id);
1658     in_w = obj_surface->orig_width;
1659     in_h = obj_surface->orig_height;
1660     in_wpitch = obj_surface->width;
1661     in_hpitch = obj_surface->height;
1662
1663     /* source Y surface index 1 */
1664     i965_pp_set_surface2_state(ctx, pp_context,
1665                                obj_surface->bo, 0,
1666                                in_w, in_h, in_wpitch,
1667                                0, 0,
1668                                SURFACE_FORMAT_Y8_UNORM, 0,
1669                                1);
1670
1671     /* source UV surface index 2 */
1672     i965_pp_set_surface2_state(ctx, pp_context,
1673                                obj_surface->bo, in_wpitch * in_hpitch,
1674                                in_w / 2, in_h / 2, in_wpitch,
1675                                0, 0,
1676                                SURFACE_FORMAT_R8B8_UNORM, 0,
1677                                2);
1678
1679     /* destination surface */
1680     obj_surface = SURFACE(dst_surface->id);
1681     out_w = obj_surface->orig_width;
1682     out_h = obj_surface->orig_height;
1683     out_wpitch = obj_surface->width;
1684     out_hpitch = obj_surface->height;
1685     assert(out_w <= out_wpitch && out_h <= out_hpitch);
1686
1687     /* destination Y surface index 7 */
1688     i965_pp_set_surface_state(ctx, pp_context,
1689                               obj_surface->bo, 0,
1690                               out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
1691                               7, 1);
1692
1693     /* destination UV surface index 8 */
1694     i965_pp_set_surface_state(ctx, pp_context,
1695                               obj_surface->bo, out_wpitch * out_hpitch,
1696                               out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
1697                               8, 1);
1698
1699     /* sampler 8x8 state */
1700     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
1701     assert(pp_context->sampler_state_table.bo_8x8->virtual);
1702     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
1703     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
1704     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
1705
1706     for (i = 0; i < 17; i++) {
1707         /* for Y channel, currently ignore */
1708         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x00;
1709         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x00;
1710         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x08;
1711         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x18;
1712         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x18;
1713         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x08;
1714         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x00;
1715         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x00;
1716         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x00;
1717         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x00;
1718         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x10;
1719         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x10;
1720         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x10;
1721         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x10;
1722         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x00;
1723         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x00;
1724         /* for U/V channel, 0.25 */
1725         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
1726         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
1727         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
1728         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
1729         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
1730         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
1731         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
1732         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
1733         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
1734         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
1735         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
1736         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
1737         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
1738         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
1739         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
1740         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
1741     }
1742
1743     sampler_8x8_state->dw136.default_sharpness_level = 0;
1744     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
1745     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
1746     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
1747     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
1748
1749     /* sampler 8x8 */
1750     dri_bo_map(pp_context->sampler_state_table.bo, True);
1751     assert(pp_context->sampler_state_table.bo->virtual);
1752     assert(sizeof(*sampler_8x8) == sizeof(int) * 16);
1753     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
1754
1755     /* sample_8x8 Y index 1 */
1756     index = 1;
1757     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1758     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1759     sampler_8x8[index].dw0.ief_bypass = 1;
1760     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1761     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1762     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1763     sampler_8x8[index].dw2.global_noise_estimation = 22;
1764     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1765     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1766     sampler_8x8[index].dw3.strong_edge_weight = 7;
1767     sampler_8x8[index].dw3.regular_weight = 2;
1768     sampler_8x8[index].dw3.non_edge_weight = 0;
1769     sampler_8x8[index].dw3.gain_factor = 40;
1770     sampler_8x8[index].dw4.steepness_boost = 0;
1771     sampler_8x8[index].dw4.steepness_threshold = 0;
1772     sampler_8x8[index].dw4.mr_boost = 0;
1773     sampler_8x8[index].dw4.mr_threshold = 5;
1774     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1775     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1776     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1777     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1778     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1779     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1780     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1781     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1782     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1783     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1784     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1785     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1786     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1787     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1788     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1789     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1790     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1791     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1792     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1793     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1794     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1795     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1796     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1797     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1798     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1799     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1800     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1801     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1802     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1803     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1804     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1805     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1806     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1807     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1808     sampler_8x8[index].dw13.limiter_boost = 0;
1809     sampler_8x8[index].dw13.minimum_limiter = 10;
1810     sampler_8x8[index].dw13.maximum_limiter = 11;
1811     sampler_8x8[index].dw14.clip_limiter = 130;
1812     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1813                       I915_GEM_DOMAIN_RENDER,
1814                       0,
1815                       0,
1816                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1817                       pp_context->sampler_state_table.bo_8x8);
1818
1819     /* sample_8x8 UV index 2 */
1820     index = 2;
1821     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
1822     sampler_8x8[index].dw0.avs_filter_type = AVS_FILTER_ADAPTIVE_8_TAP;
1823     sampler_8x8[index].dw0.ief_bypass = 1;
1824     sampler_8x8[index].dw0.ief_filter_type = IEF_FILTER_DETAIL;
1825     sampler_8x8[index].dw0.ief_filter_size = IEF_FILTER_SIZE_5X5;
1826     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
1827     sampler_8x8[index].dw2.global_noise_estimation = 22;
1828     sampler_8x8[index].dw2.strong_edge_threshold = 8;
1829     sampler_8x8[index].dw2.weak_edge_threshold = 1;
1830     sampler_8x8[index].dw3.strong_edge_weight = 7;
1831     sampler_8x8[index].dw3.regular_weight = 2;
1832     sampler_8x8[index].dw3.non_edge_weight = 0;
1833     sampler_8x8[index].dw3.gain_factor = 40;
1834     sampler_8x8[index].dw4.steepness_boost = 0;
1835     sampler_8x8[index].dw4.steepness_threshold = 0;
1836     sampler_8x8[index].dw4.mr_boost = 0;
1837     sampler_8x8[index].dw4.mr_threshold = 5;
1838     sampler_8x8[index].dw5.pwl1_point_1 = 4;
1839     sampler_8x8[index].dw5.pwl1_point_2 = 12;
1840     sampler_8x8[index].dw5.pwl1_point_3 = 16;
1841     sampler_8x8[index].dw5.pwl1_point_4 = 26;
1842     sampler_8x8[index].dw6.pwl1_point_5 = 40;
1843     sampler_8x8[index].dw6.pwl1_point_6 = 160;
1844     sampler_8x8[index].dw6.pwl1_r3_bias_0 = 127;
1845     sampler_8x8[index].dw6.pwl1_r3_bias_1 = 98;
1846     sampler_8x8[index].dw7.pwl1_r3_bias_2 = 88;
1847     sampler_8x8[index].dw7.pwl1_r3_bias_3 = 64;
1848     sampler_8x8[index].dw7.pwl1_r3_bias_4 = 44;
1849     sampler_8x8[index].dw7.pwl1_r3_bias_5 = 0;
1850     sampler_8x8[index].dw8.pwl1_r3_bias_6 = 0;
1851     sampler_8x8[index].dw8.pwl1_r5_bias_0 = 3;
1852     sampler_8x8[index].dw8.pwl1_r5_bias_1 = 32;
1853     sampler_8x8[index].dw8.pwl1_r5_bias_2 = 32;
1854     sampler_8x8[index].dw9.pwl1_r5_bias_3 = 58;
1855     sampler_8x8[index].dw9.pwl1_r5_bias_4 = 100;
1856     sampler_8x8[index].dw9.pwl1_r5_bias_5 = 108;
1857     sampler_8x8[index].dw9.pwl1_r5_bias_6 = 88;
1858     sampler_8x8[index].dw10.pwl1_r3_slope_0 = -116;
1859     sampler_8x8[index].dw10.pwl1_r3_slope_1 = -20;
1860     sampler_8x8[index].dw10.pwl1_r3_slope_2 = -96;
1861     sampler_8x8[index].dw10.pwl1_r3_slope_3 = -32;
1862     sampler_8x8[index].dw11.pwl1_r3_slope_4 = -50;
1863     sampler_8x8[index].dw11.pwl1_r3_slope_5 = 0;
1864     sampler_8x8[index].dw11.pwl1_r3_slope_6 = 0;
1865     sampler_8x8[index].dw11.pwl1_r5_slope_0 = 116;
1866     sampler_8x8[index].dw12.pwl1_r5_slope_1 = 0;
1867     sampler_8x8[index].dw12.pwl1_r5_slope_2 = 114;
1868     sampler_8x8[index].dw12.pwl1_r5_slope_3 = 67;
1869     sampler_8x8[index].dw12.pwl1_r5_slope_4 = 9;
1870     sampler_8x8[index].dw13.pwl1_r5_slope_5 = -3;
1871     sampler_8x8[index].dw13.pwl1_r5_slope_6 = -15;
1872     sampler_8x8[index].dw13.limiter_boost = 0;
1873     sampler_8x8[index].dw13.minimum_limiter = 10;
1874     sampler_8x8[index].dw13.maximum_limiter = 11;
1875     sampler_8x8[index].dw14.clip_limiter = 130;
1876     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
1877                       I915_GEM_DOMAIN_RENDER,
1878                       0,
1879                       0,
1880                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
1881                       pp_context->sampler_state_table.bo_8x8);
1882
1883     dri_bo_unmap(pp_context->sampler_state_table.bo);
1884
1885     /* private function & data */
1886     pp_context->pp_x_steps = pp_avs_x_steps;
1887     pp_context->pp_y_steps = pp_avs_y_steps;
1888     pp_context->pp_set_block_parameter = pp_avs_set_block_parameter;
1889
1890     pp_avs_context->dest_x = dst_rect->x;
1891     pp_avs_context->dest_y = dst_rect->y;
1892     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
1893     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
1894     pp_avs_context->src_normalized_x = (float)src_rect->x / in_w;
1895     pp_avs_context->src_normalized_y = (float)src_rect->y / in_h;
1896     pp_avs_context->src_w = src_rect->width;
1897     pp_avs_context->src_h = src_rect->height;
1898
1899     pp_static_parameter->grf4.r4_2.avs.nlas = nlas;
1900     pp_static_parameter->grf1.r1_6.normalized_video_y_scaling_step = (float) src_rect->height / in_h / dst_rect->height;
1901
1902     pp_inline_parameter->grf5.normalized_video_x_scaling_step = (float) src_rect->width / in_w / dst_rect->width;
1903     pp_inline_parameter->grf5.block_count_x = 1;        /* M x 1 */
1904     pp_inline_parameter->grf5.number_blocks = pp_avs_context->dest_h / 8;
1905     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
1906     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
1907     pp_inline_parameter->grf6.video_step_delta = 0.0;
1908
1909     dst_surface->flags = src_surface->flags;
1910
1911     return VA_STATUS_SUCCESS;
1912 }
1913
1914 static VAStatus
1915 pp_nv12_avs_initialize_nlas(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1916                             const struct i965_surface *src_surface,
1917                             const VARectangle *src_rect,
1918                             struct i965_surface *dst_surface,
1919                             const VARectangle *dst_rect,
1920                             void *filter_param)
1921 {
1922     return pp_nv12_avs_initialize(ctx, pp_context,
1923                                   src_surface,
1924                                   src_rect,
1925                                   dst_surface,
1926                                   dst_rect,
1927                                   filter_param,
1928                                   1);
1929 }
1930
1931 static VAStatus
1932 gen6_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1933                              const struct i965_surface *src_surface,
1934                              const VARectangle *src_rect,
1935                              struct i965_surface *dst_surface,
1936                              const VARectangle *dst_rect,
1937                              void *filter_param)
1938 {
1939     return pp_nv12_avs_initialize(ctx, pp_context,
1940                                   src_surface,
1941                                   src_rect,
1942                                   dst_surface,
1943                                   dst_rect,
1944                                   filter_param,
1945                                   0);
1946 }
1947
1948 static int
1949 gen7_pp_avs_x_steps(void *private_context)
1950 {
1951     struct pp_avs_context *pp_avs_context = private_context;
1952
1953     return pp_avs_context->dest_w / 16;
1954 }
1955
1956 static int
1957 gen7_pp_avs_y_steps(void *private_context)
1958 {
1959     struct pp_avs_context *pp_avs_context = private_context;
1960
1961     return pp_avs_context->dest_h / 16;
1962 }
1963
1964 static int
1965 gen7_pp_avs_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
1966 {
1967     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1968     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
1969
1970     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16 + pp_avs_context->dest_x;
1971     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 16 + pp_avs_context->dest_y;
1972     pp_inline_parameter->grf7.constant_0 = 0xffffffff;
1973     pp_inline_parameter->grf7.sampler_load_main_video_x_scaling_step = 1.0 / pp_avs_context->src_w;
1974
1975     return 0;
1976 }
1977
1978 static VAStatus
1979 gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
1980                            const struct i965_surface *src_surface,
1981                            const VARectangle *src_rect,
1982                            struct i965_surface *dst_surface,
1983                            const VARectangle *dst_rect,
1984                            void *filter_param)
1985 {
1986     struct pp_avs_context *pp_avs_context = (struct pp_avs_context *)&pp_context->private_context;
1987     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
1988     struct gen7_sampler_8x8 *sampler_8x8;
1989     struct i965_sampler_8x8_state *sampler_8x8_state;
1990     int index, i;
1991     int width[3], height[3], pitch[3], offset[3];
1992
1993     /* source surface */
1994     gen7_pp_set_media_rw_message_surface(ctx, pp_context, src_surface, 0, 0,
1995                                          width, height, pitch, offset);
1996
1997     /* destination surface */
1998     gen7_pp_set_media_rw_message_surface(ctx, pp_context, dst_surface, 24, 1,
1999                                          width, height, pitch, offset);
2000
2001     /* sampler 8x8 state */
2002     dri_bo_map(pp_context->sampler_state_table.bo_8x8, True);
2003     assert(pp_context->sampler_state_table.bo_8x8->virtual);
2004     assert(sizeof(*sampler_8x8_state) == sizeof(int) * 138);
2005     sampler_8x8_state = pp_context->sampler_state_table.bo_8x8->virtual;
2006     memset(sampler_8x8_state, 0, sizeof(*sampler_8x8_state));
2007
2008     for (i = 0; i < 17; i++) {
2009         /* for Y channel, currently ignore */
2010         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c0 = 0x0;
2011         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c1 = 0x0;
2012         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c2 = 0x0;
2013         sampler_8x8_state->coefficients[i].dw0.table_0x_filter_c3 = 0x0;
2014         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c4 = 0x0;
2015         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c5 = 0x0;
2016         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c6 = 0x0;
2017         sampler_8x8_state->coefficients[i].dw1.table_0x_filter_c7 = 0x0;
2018         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c0 = 0x0;
2019         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c1 = 0x0;
2020         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c2 = 0x0;
2021         sampler_8x8_state->coefficients[i].dw2.table_0y_filter_c3 = 0x0;
2022         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c4 = 0x0;
2023         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c5 = 0x0;
2024         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c6 = 0x0;
2025         sampler_8x8_state->coefficients[i].dw3.table_0y_filter_c7 = 0x0;
2026         /* for U/V channel, 0.25 */
2027         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c0 = 0x0;
2028         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c1 = 0x0;
2029         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c2 = 0x10;
2030         sampler_8x8_state->coefficients[i].dw4.table_1x_filter_c3 = 0x10;
2031         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c4 = 0x10;
2032         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c5 = 0x10;
2033         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c6 = 0x0;
2034         sampler_8x8_state->coefficients[i].dw5.table_1x_filter_c7 = 0x0;
2035         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c0 = 0x0;
2036         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c1 = 0x0;
2037         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c2 = 0x10;
2038         sampler_8x8_state->coefficients[i].dw6.table_1y_filter_c3 = 0x10;
2039         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c4 = 0x10;
2040         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c5 = 0x10;
2041         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c6 = 0x0;
2042         sampler_8x8_state->coefficients[i].dw7.table_1y_filter_c7 = 0x0;
2043     }
2044
2045     sampler_8x8_state->dw136.default_sharpness_level = 0;
2046     sampler_8x8_state->dw137.adaptive_filter_for_all_channel = 1;
2047     sampler_8x8_state->dw137.bypass_y_adaptive_filtering = 1;
2048     sampler_8x8_state->dw137.bypass_x_adaptive_filtering = 1;
2049     dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
2050
2051     /* sampler 8x8 */
2052     dri_bo_map(pp_context->sampler_state_table.bo, True);
2053     assert(pp_context->sampler_state_table.bo->virtual);
2054     assert(sizeof(*sampler_8x8) == sizeof(int) * 4);
2055     sampler_8x8 = pp_context->sampler_state_table.bo->virtual;
2056
2057     /* sample_8x8 Y index 4 */
2058     index = 4;
2059     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2060     sampler_8x8[index].dw0.global_noise_estimation = 255;
2061     sampler_8x8[index].dw0.ief_bypass = 1;
2062
2063     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2064
2065     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2066     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2067     sampler_8x8[index].dw2.r5x_coefficient = 9;
2068     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2069     sampler_8x8[index].dw2.r5c_coefficient = 3;
2070
2071     sampler_8x8[index].dw3.r3x_coefficient = 27;
2072     sampler_8x8[index].dw3.r3c_coefficient = 5;
2073     sampler_8x8[index].dw3.gain_factor = 40;
2074     sampler_8x8[index].dw3.non_edge_weight = 1;
2075     sampler_8x8[index].dw3.regular_weight = 2;
2076     sampler_8x8[index].dw3.strong_edge_weight = 7;
2077     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2078
2079     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2080                       I915_GEM_DOMAIN_RENDER,
2081                       0,
2082                       0,
2083                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2084                       pp_context->sampler_state_table.bo_8x8);
2085
2086     /* sample_8x8 UV index 8 */
2087     index = 8;
2088     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2089     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2090     sampler_8x8[index].dw0.global_noise_estimation = 255;
2091     sampler_8x8[index].dw0.ief_bypass = 1;
2092     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2093     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2094     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2095     sampler_8x8[index].dw2.r5x_coefficient = 9;
2096     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2097     sampler_8x8[index].dw2.r5c_coefficient = 3;
2098     sampler_8x8[index].dw3.r3x_coefficient = 27;
2099     sampler_8x8[index].dw3.r3c_coefficient = 5;
2100     sampler_8x8[index].dw3.gain_factor = 40;
2101     sampler_8x8[index].dw3.non_edge_weight = 1;
2102     sampler_8x8[index].dw3.regular_weight = 2;
2103     sampler_8x8[index].dw3.strong_edge_weight = 7;
2104     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2105
2106     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2107                       I915_GEM_DOMAIN_RENDER,
2108                       0,
2109                       0,
2110                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2111                       pp_context->sampler_state_table.bo_8x8);
2112
2113     /* sampler_8x8 V, index 12 */
2114     index = 12;
2115     memset(&sampler_8x8[index], 0, sizeof(*sampler_8x8));
2116     sampler_8x8[index].dw0.disable_8x8_filter = 0;
2117     sampler_8x8[index].dw0.global_noise_estimation = 255;
2118     sampler_8x8[index].dw0.ief_bypass = 1;
2119     sampler_8x8[index].dw1.sampler_8x8_state_pointer = pp_context->sampler_state_table.bo_8x8->offset >> 5;
2120     sampler_8x8[index].dw2.weak_edge_threshold = 1;
2121     sampler_8x8[index].dw2.strong_edge_threshold = 8;
2122     sampler_8x8[index].dw2.r5x_coefficient = 9;
2123     sampler_8x8[index].dw2.r5cx_coefficient = 8;
2124     sampler_8x8[index].dw2.r5c_coefficient = 3;
2125     sampler_8x8[index].dw3.r3x_coefficient = 27;
2126     sampler_8x8[index].dw3.r3c_coefficient = 5;
2127     sampler_8x8[index].dw3.gain_factor = 40;
2128     sampler_8x8[index].dw3.non_edge_weight = 1;
2129     sampler_8x8[index].dw3.regular_weight = 2;
2130     sampler_8x8[index].dw3.strong_edge_weight = 7;
2131     sampler_8x8[index].dw3.ief4_smooth_enable = 0;
2132
2133     dri_bo_emit_reloc(pp_context->sampler_state_table.bo,
2134                       I915_GEM_DOMAIN_RENDER,
2135                       0,
2136                       0,
2137                       sizeof(*sampler_8x8) * index + offsetof(struct i965_sampler_8x8, dw1),
2138                       pp_context->sampler_state_table.bo_8x8);
2139
2140     dri_bo_unmap(pp_context->sampler_state_table.bo);
2141
2142     /* private function & data */
2143     pp_context->pp_x_steps = gen7_pp_avs_x_steps;
2144     pp_context->pp_y_steps = gen7_pp_avs_y_steps;
2145     pp_context->pp_set_block_parameter = gen7_pp_avs_set_block_parameter;
2146
2147     pp_avs_context->dest_x = dst_rect->x;
2148     pp_avs_context->dest_y = dst_rect->y;
2149     pp_avs_context->dest_w = ALIGN(dst_rect->width, 16);
2150     pp_avs_context->dest_h = ALIGN(dst_rect->height, 16);
2151     pp_avs_context->src_w = src_rect->width;
2152     pp_avs_context->src_h = src_rect->height;
2153
2154     int dw = (pp_avs_context->src_w - 1) / 16 + 1;
2155     dw = MAX(dw, pp_avs_context->dest_w);
2156
2157     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2158     pp_static_parameter->grf3.sampler_load_horizontal_scaling_step_ratio = (float) pp_avs_context->src_w / dw;
2159     pp_static_parameter->grf4.sampler_load_vertical_scaling_step = (float) 1.0 / pp_avs_context->dest_h;
2160     pp_static_parameter->grf5.sampler_load_vertical_frame_origin = -(float)pp_avs_context->dest_y / pp_avs_context->dest_h;
2161     pp_static_parameter->grf6.sampler_load_horizontal_frame_origin = -(float)pp_avs_context->dest_x / dw;
2162
2163     dst_surface->flags = src_surface->flags;
2164
2165     return VA_STATUS_SUCCESS;
2166 }
2167
2168 static int
2169 pp_dndi_x_steps(void *private_context)
2170 {
2171     return 1;
2172 }
2173
2174 static int
2175 pp_dndi_y_steps(void *private_context)
2176 {
2177     struct pp_dndi_context *pp_dndi_context = private_context;
2178
2179     return pp_dndi_context->dest_h / 4;
2180 }
2181
2182 static int
2183 pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2184 {
2185     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2186
2187     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2188     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2189
2190     return 0;
2191 }
2192
2193 static VAStatus
2194 pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2195                         const struct i965_surface *src_surface,
2196                         const VARectangle *src_rect,
2197                         struct i965_surface *dst_surface,
2198                         const VARectangle *dst_rect,
2199                         void *filter_param)
2200 {
2201     struct i965_driver_data *i965 = i965_driver_data(ctx);
2202     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2203     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2204     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2205     struct object_surface *obj_surface;
2206     struct i965_sampler_dndi *sampler_dndi;
2207     int index;
2208     int w, h;
2209     int orig_w, orig_h;
2210     int dndi_top_first = 1;
2211
2212     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2213         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2214
2215     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2216         dndi_top_first = 1;
2217     else
2218         dndi_top_first = 0;
2219
2220     /* surface */
2221     obj_surface = SURFACE(src_surface->id);
2222     orig_w = obj_surface->orig_width;
2223     orig_h = obj_surface->orig_height;
2224     w = obj_surface->width;
2225     h = obj_surface->height;
2226
2227     if (pp_context->stmm.bo == NULL) {
2228         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2229                                            "STMM surface",
2230                                            w * h,
2231                                            4096);
2232         assert(pp_context->stmm.bo);
2233     }
2234
2235     /* source UV surface index 2 */
2236     i965_pp_set_surface_state(ctx, pp_context,
2237                               obj_surface->bo, w * h,
2238                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2239                               2, 0);
2240
2241     /* source YUV surface index 4 */
2242     i965_pp_set_surface2_state(ctx, pp_context,
2243                                obj_surface->bo, 0,
2244                                orig_w, orig_h, w,
2245                                0, h,
2246                                SURFACE_FORMAT_PLANAR_420_8, 1,
2247                                4);
2248
2249     /* source STMM surface index 20 */
2250     i965_pp_set_surface_state(ctx, pp_context,
2251                               pp_context->stmm.bo, 0,
2252                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2253                               20, 1);
2254
2255     /* destination surface */
2256     obj_surface = SURFACE(dst_surface->id);
2257     orig_w = obj_surface->orig_width;
2258     orig_h = obj_surface->orig_height;
2259     w = obj_surface->width;
2260     h = obj_surface->height;
2261
2262     /* destination Y surface index 7 */
2263     i965_pp_set_surface_state(ctx, pp_context,
2264                               obj_surface->bo, 0,
2265                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2266                               7, 1);
2267
2268     /* destination UV surface index 8 */
2269     i965_pp_set_surface_state(ctx, pp_context,
2270                               obj_surface->bo, w * h,
2271                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2272                               8, 1);
2273     /* sampler dndi */
2274     dri_bo_map(pp_context->sampler_state_table.bo, True);
2275     assert(pp_context->sampler_state_table.bo->virtual);
2276     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2277     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2278
2279     /* sample dndi index 1 */
2280     index = 0;
2281     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2282     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2283     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2284     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2285
2286     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2287     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 4;
2288     sampler_dndi[index].dw1.stmm_c2 = 1;
2289     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2290     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2291
2292     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2293     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2294     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2295     sampler_dndi[index].dw2.good_neighbor_threshold = 4;                // 0-63
2296
2297     sampler_dndi[index].dw3.maximum_stmm = 128;
2298     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2299     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2300     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2301     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2302
2303     sampler_dndi[index].dw4.sdi_delta = 8;
2304     sampler_dndi[index].dw4.sdi_threshold = 128;
2305     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2306     sampler_dndi[index].dw4.stmm_shift_up = 0;
2307     sampler_dndi[index].dw4.stmm_shift_down = 0;
2308     sampler_dndi[index].dw4.minimum_stmm = 0;
2309
2310     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 8;
2311     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 32;
2312     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 64;
2313     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 32;
2314
2315     sampler_dndi[index].dw6.dn_enable = 1;
2316     sampler_dndi[index].dw6.di_enable = 1;
2317     sampler_dndi[index].dw6.di_partial = 0;
2318     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2319     sampler_dndi[index].dw6.dndi_stream_id = 0;
2320     sampler_dndi[index].dw6.dndi_first_frame = 1;
2321     sampler_dndi[index].dw6.progressive_dn = 0;
2322     sampler_dndi[index].dw6.fmd_tear_threshold = 63;
2323     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2324     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2325
2326     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2327     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2328     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2329     sampler_dndi[index].dw7.column_width_minus1 = 0;
2330
2331     dri_bo_unmap(pp_context->sampler_state_table.bo);
2332
2333     /* private function & data */
2334     pp_context->pp_x_steps = pp_dndi_x_steps;
2335     pp_context->pp_y_steps = pp_dndi_y_steps;
2336     pp_context->pp_set_block_parameter = pp_dndi_set_block_parameter;
2337
2338     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2339     pp_static_parameter->grf1.r1_6.di.top_field_first = dndi_top_first;
2340     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 0;
2341     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 0;
2342
2343     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2344     pp_inline_parameter->grf5.number_blocks = w / 16;
2345     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2346     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2347
2348     pp_dndi_context->dest_w = w;
2349     pp_dndi_context->dest_h = h;
2350
2351     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2352
2353     return VA_STATUS_SUCCESS;
2354 }
2355
2356 static int
2357 pp_dn_x_steps(void *private_context)
2358 {
2359     return 1;
2360 }
2361
2362 static int
2363 pp_dn_y_steps(void *private_context)
2364 {
2365     struct pp_dn_context *pp_dn_context = private_context;
2366
2367     return pp_dn_context->dest_h / 8;
2368 }
2369
2370 static int
2371 pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2372 {
2373     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2374
2375     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2376     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 8;
2377
2378     return 0;
2379 }
2380
2381 static VAStatus
2382 pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2383                       const struct i965_surface *src_surface,
2384                       const VARectangle *src_rect,
2385                       struct i965_surface *dst_surface,
2386                       const VARectangle *dst_rect,
2387                       void *filter_param)
2388 {
2389     struct i965_driver_data *i965 = i965_driver_data(ctx);
2390     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2391     struct object_surface *obj_surface;
2392     struct i965_sampler_dndi *sampler_dndi;
2393     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2394     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2395     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2396     int index;
2397     int w, h;
2398     int orig_w, orig_h;
2399     int dn_strength = 15;
2400     int dndi_top_first = 1;
2401     int dn_progressive = 0;
2402
2403     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2404         dndi_top_first = 1;
2405         dn_progressive = 1;
2406     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2407         dndi_top_first = 1;
2408         dn_progressive = 0;
2409     } else {
2410         dndi_top_first = 0;
2411         dn_progressive = 0;
2412     }
2413
2414     if (dn_filter_param) {
2415         float value = dn_filter_param->value;
2416
2417         if (value > 1.0)
2418             value = 1.0;
2419
2420         if (value < 0.0)
2421             value = 0.0;
2422
2423         dn_strength = (int)(value * 31.0F);
2424     }
2425
2426     /* surface */
2427     obj_surface = SURFACE(src_surface->id);
2428     orig_w = obj_surface->orig_width;
2429     orig_h = obj_surface->orig_height;
2430     w = obj_surface->width;
2431     h = obj_surface->height;
2432
2433     if (pp_context->stmm.bo == NULL) {
2434         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2435                                            "STMM surface",
2436                                            w * h,
2437                                            4096);
2438         assert(pp_context->stmm.bo);
2439     }
2440
2441     /* source UV surface index 2 */
2442     i965_pp_set_surface_state(ctx, pp_context,
2443                               obj_surface->bo, w * h,
2444                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2445                               2, 0);
2446
2447     /* source YUV surface index 4 */
2448     i965_pp_set_surface2_state(ctx, pp_context,
2449                                obj_surface->bo, 0,
2450                                orig_w, orig_h, w,
2451                                0, h,
2452                                SURFACE_FORMAT_PLANAR_420_8, 1,
2453                                4);
2454
2455     /* source STMM surface index 20 */
2456     i965_pp_set_surface_state(ctx, pp_context,
2457                               pp_context->stmm.bo, 0,
2458                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2459                               20, 1);
2460
2461     /* destination surface */
2462     obj_surface = SURFACE(dst_surface->id);
2463     orig_w = obj_surface->orig_width;
2464     orig_h = obj_surface->orig_height;
2465     w = obj_surface->width;
2466     h = obj_surface->height;
2467
2468     /* destination Y surface index 7 */
2469     i965_pp_set_surface_state(ctx, pp_context,
2470                               obj_surface->bo, 0,
2471                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2472                               7, 1);
2473
2474     /* destination UV surface index 8 */
2475     i965_pp_set_surface_state(ctx, pp_context,
2476                               obj_surface->bo, w * h,
2477                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2478                               8, 1);
2479     /* sampler dn */
2480     dri_bo_map(pp_context->sampler_state_table.bo, True);
2481     assert(pp_context->sampler_state_table.bo->virtual);
2482     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2483     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2484
2485     /* sample dndi index 1 */
2486     index = 0;
2487     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2488     sampler_dndi[index].dw0.denoise_history_delta = 8;          // 0-15, default is 8
2489     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2490     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2491
2492     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2493     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2494     sampler_dndi[index].dw1.stmm_c2 = 0;
2495     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2496     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2497
2498     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2499     sampler_dndi[index].dw2.block_noise_estimate_edge_threshold = 7;    // 0-15
2500     sampler_dndi[index].dw2.denoise_edge_threshold = 7;                 // 0-15
2501     sampler_dndi[index].dw2.good_neighbor_threshold = 7;                // 0-63
2502
2503     sampler_dndi[index].dw3.maximum_stmm = 128;
2504     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2505     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2506     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2507     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2508
2509     sampler_dndi[index].dw4.sdi_delta = 8;
2510     sampler_dndi[index].dw4.sdi_threshold = 128;
2511     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2512     sampler_dndi[index].dw4.stmm_shift_up = 0;
2513     sampler_dndi[index].dw4.stmm_shift_down = 0;
2514     sampler_dndi[index].dw4.minimum_stmm = 0;
2515
2516     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2517     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2518     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2519     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2520
2521     sampler_dndi[index].dw6.dn_enable = 1;
2522     sampler_dndi[index].dw6.di_enable = 0;
2523     sampler_dndi[index].dw6.di_partial = 0;
2524     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2525     sampler_dndi[index].dw6.dndi_stream_id = 1;
2526     sampler_dndi[index].dw6.dndi_first_frame = 1;
2527     sampler_dndi[index].dw6.progressive_dn = dn_progressive;
2528     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2529     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2530     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2531
2532     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2533     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2534     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2535     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2536
2537     dri_bo_unmap(pp_context->sampler_state_table.bo);
2538
2539     /* private function & data */
2540     pp_context->pp_x_steps = pp_dn_x_steps;
2541     pp_context->pp_y_steps = pp_dn_y_steps;
2542     pp_context->pp_set_block_parameter = pp_dn_set_block_parameter;
2543
2544     pp_static_parameter->grf1.statistics_surface_picth = w / 2;
2545     pp_static_parameter->grf1.r1_6.di.top_field_first = 0;
2546     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m2 = 64;
2547     pp_static_parameter->grf4.r4_2.di.motion_history_coefficient_m1 = 192;
2548
2549     pp_inline_parameter->grf5.block_count_x = w / 16;   /* 1 x N */
2550     pp_inline_parameter->grf5.number_blocks = w / 16;
2551     pp_inline_parameter->grf5.block_vertical_mask = 0xff;
2552     pp_inline_parameter->grf5.block_horizontal_mask = 0xffff;
2553
2554     pp_dn_context->dest_w = w;
2555     pp_dn_context->dest_h = h;
2556
2557     dst_surface->flags = src_surface->flags;
2558
2559     return VA_STATUS_SUCCESS;
2560 }
2561
2562 static int
2563 gen7_pp_dndi_x_steps(void *private_context)
2564 {
2565     struct pp_dndi_context *pp_dndi_context = private_context;
2566
2567     return pp_dndi_context->dest_w / 16;
2568 }
2569
2570 static int
2571 gen7_pp_dndi_y_steps(void *private_context)
2572 {
2573     struct pp_dndi_context *pp_dndi_context = private_context;
2574
2575     return pp_dndi_context->dest_h / 4;
2576 }
2577
2578 static int
2579 gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2580 {
2581     struct gen7_pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2582
2583     pp_inline_parameter->grf7.destination_block_horizontal_origin = x * 16;
2584     pp_inline_parameter->grf7.destination_block_vertical_origin = y * 4;
2585
2586     return 0;
2587 }
2588
2589 static VAStatus
2590 gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2591                              const struct i965_surface *src_surface,
2592                              const VARectangle *src_rect,
2593                              struct i965_surface *dst_surface,
2594                              const VARectangle *dst_rect,
2595                              void *filter_param)
2596 {
2597     struct i965_driver_data *i965 = i965_driver_data(ctx);
2598     struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->private_context;
2599     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2600     struct object_surface *obj_surface;
2601     struct gen7_sampler_dndi *sampler_dndi;
2602     int index;
2603     int w, h;
2604     int orig_w, orig_h;
2605     int dndi_top_first = 1;
2606
2607     if (src_surface->flags == I965_SURFACE_FLAG_FRAME)
2608         return VA_STATUS_ERROR_FLAG_NOT_SUPPORTED;
2609
2610     if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST)
2611         dndi_top_first = 1;
2612     else
2613         dndi_top_first = 0;
2614
2615     /* surface */
2616     obj_surface = SURFACE(src_surface->id);
2617     orig_w = obj_surface->orig_width;
2618     orig_h = obj_surface->orig_height;
2619     w = obj_surface->width;
2620     h = obj_surface->height;
2621
2622     if (pp_context->stmm.bo == NULL) {
2623         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2624                                            "STMM surface",
2625                                            w * h,
2626                                            4096);
2627         assert(pp_context->stmm.bo);
2628     }
2629
2630     /* source UV surface index 1 */
2631     gen7_pp_set_surface_state(ctx, pp_context,
2632                               obj_surface->bo, w * h,
2633                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2634                               1, 0);
2635
2636     /* source YUV surface index 3 */
2637     gen7_pp_set_surface2_state(ctx, pp_context,
2638                                obj_surface->bo, 0,
2639                                orig_w, orig_h, w,
2640                                0, h,
2641                                SURFACE_FORMAT_PLANAR_420_8, 1,
2642                                3);
2643
2644     /* source (temporal reference) YUV surface index 4 */
2645     gen7_pp_set_surface2_state(ctx, pp_context,
2646                                obj_surface->bo, 0,
2647                                orig_w, orig_h, w,
2648                                0, h,
2649                                SURFACE_FORMAT_PLANAR_420_8, 1,
2650                                4);
2651
2652     /* STMM / History Statistics input surface, index 5 */
2653     gen7_pp_set_surface_state(ctx, pp_context,
2654                               pp_context->stmm.bo, 0,
2655                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2656                               5, 1);
2657
2658     /* destination surface */
2659     obj_surface = SURFACE(dst_surface->id);
2660     orig_w = obj_surface->orig_width;
2661     orig_h = obj_surface->orig_height;
2662     w = obj_surface->width;
2663     h = obj_surface->height;
2664
2665     /* destination(Previous frame) Y surface index 27 */
2666     gen7_pp_set_surface_state(ctx, pp_context,
2667                               obj_surface->bo, 0,
2668                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2669                               27, 1);
2670
2671     /* destination(Previous frame) UV surface index 28 */
2672     gen7_pp_set_surface_state(ctx, pp_context,
2673                               obj_surface->bo, w * h,
2674                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2675                               28, 1);
2676
2677     /* destination(Current frame) Y surface index 30 */
2678     gen7_pp_set_surface_state(ctx, pp_context,
2679                               obj_surface->bo, 0,
2680                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2681                               30, 1);
2682
2683     /* destination(Current frame) UV surface index 31 */
2684     gen7_pp_set_surface_state(ctx, pp_context,
2685                               obj_surface->bo, w * h,
2686                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2687                               31, 1);
2688
2689     /* STMM output surface, index 33 */
2690     gen7_pp_set_surface_state(ctx, pp_context,
2691                               pp_context->stmm.bo, 0,
2692                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2693                               33, 1);
2694
2695
2696     /* sampler dndi */
2697     dri_bo_map(pp_context->sampler_state_table.bo, True);
2698     assert(pp_context->sampler_state_table.bo->virtual);
2699     assert(sizeof(*sampler_dndi) == sizeof(int) * 8);
2700     sampler_dndi = pp_context->sampler_state_table.bo->virtual;
2701
2702     /* sample dndi index 0 */
2703     index = 0;
2704     sampler_dndi[index].dw0.denoise_asd_threshold = 0;
2705     sampler_dndi[index].dw0.dnmh_delt = 8;
2706     sampler_dndi[index].dw0.vdi_walker_y_stride = 0;
2707     sampler_dndi[index].dw0.vdi_walker_frame_sharing_enable = 0;
2708     sampler_dndi[index].dw0.denoise_maximum_history = 128;      // 128-240
2709     sampler_dndi[index].dw0.denoise_stad_threshold = 0;
2710
2711     sampler_dndi[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2712     sampler_dndi[index].dw1.denoise_moving_pixel_threshold = 0;
2713     sampler_dndi[index].dw1.stmm_c2 = 0;
2714     sampler_dndi[index].dw1.low_temporal_difference_threshold = 8;
2715     sampler_dndi[index].dw1.temporal_difference_threshold = 16;
2716
2717     sampler_dndi[index].dw2.block_noise_estimate_noise_threshold = 15;   // 0-31
2718     sampler_dndi[index].dw2.bne_edge_th = 1;
2719     sampler_dndi[index].dw2.smooth_mv_th = 0;
2720     sampler_dndi[index].dw2.sad_tight_th = 5;
2721     sampler_dndi[index].dw2.cat_slope_minus1 = 9;
2722     sampler_dndi[index].dw2.good_neighbor_th = 4;
2723
2724     sampler_dndi[index].dw3.maximum_stmm = 128;
2725     sampler_dndi[index].dw3.multipler_for_vecm = 2;
2726     sampler_dndi[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2727     sampler_dndi[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2728     sampler_dndi[index].dw3.stmm_blending_constant_select = 0;
2729
2730     sampler_dndi[index].dw4.sdi_delta = 8;
2731     sampler_dndi[index].dw4.sdi_threshold = 128;
2732     sampler_dndi[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2733     sampler_dndi[index].dw4.stmm_shift_up = 0;
2734     sampler_dndi[index].dw4.stmm_shift_down = 0;
2735     sampler_dndi[index].dw4.minimum_stmm = 0;
2736
2737     sampler_dndi[index].dw5.fmd_temporal_difference_threshold = 0;
2738     sampler_dndi[index].dw5.sdi_fallback_mode_2_constant = 0;
2739     sampler_dndi[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2740     sampler_dndi[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2741
2742     sampler_dndi[index].dw6.dn_enable = 0;
2743     sampler_dndi[index].dw6.di_enable = 1;
2744     sampler_dndi[index].dw6.di_partial = 0;
2745     sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
2746     sampler_dndi[index].dw6.dndi_stream_id = 1;
2747     sampler_dndi[index].dw6.dndi_first_frame = 1;
2748     sampler_dndi[index].dw6.progressive_dn = 0;
2749     sampler_dndi[index].dw6.mcdi_enable = 0;
2750     sampler_dndi[index].dw6.fmd_tear_threshold = 32;
2751     sampler_dndi[index].dw6.cat_th1 = 0;
2752     sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 32;
2753     sampler_dndi[index].dw6.fmd1_vertical_difference_threshold = 32;
2754
2755     sampler_dndi[index].dw7.sad_tha = 5;
2756     sampler_dndi[index].dw7.sad_thb = 10;
2757     sampler_dndi[index].dw7.fmd_for_1st_field_of_current_frame = 0;
2758     sampler_dndi[index].dw7.mc_pixel_consistency_th = 25;
2759     sampler_dndi[index].dw7.fmd_for_2nd_field_of_previous_frame = 0;
2760     sampler_dndi[index].dw7.vdi_walker_enable = 0;
2761     sampler_dndi[index].dw7.neighborpixel_th = 10;
2762     sampler_dndi[index].dw7.column_width_minus1 = w / 16;
2763
2764     dri_bo_unmap(pp_context->sampler_state_table.bo);
2765
2766     /* private function & data */
2767     pp_context->pp_x_steps = gen7_pp_dndi_x_steps;
2768     pp_context->pp_y_steps = gen7_pp_dndi_y_steps;
2769     pp_context->pp_set_block_parameter = gen7_pp_dndi_set_block_parameter;
2770
2771     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2772     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2773     pp_static_parameter->grf1.di_top_field_first = 0;
2774     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2775
2776     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2777     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2778     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2779
2780     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2781     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2782
2783     pp_dndi_context->dest_w = w;
2784     pp_dndi_context->dest_h = h;
2785
2786     dst_surface->flags = I965_SURFACE_FLAG_FRAME;
2787
2788     return VA_STATUS_SUCCESS;
2789 }
2790
2791 static int
2792 gen7_pp_dn_x_steps(void *private_context)
2793 {
2794     return 1;
2795 }
2796
2797 static int
2798 gen7_pp_dn_y_steps(void *private_context)
2799 {
2800     struct pp_dn_context *pp_dn_context = private_context;
2801
2802     return pp_dn_context->dest_h / 4;
2803 }
2804
2805 static int
2806 gen7_pp_dn_set_block_parameter(struct i965_post_processing_context *pp_context, int x, int y)
2807 {
2808     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
2809
2810     pp_inline_parameter->grf5.destination_block_horizontal_origin = x * 16;
2811     pp_inline_parameter->grf5.destination_block_vertical_origin = y * 4;
2812
2813     return 0;
2814 }
2815
2816 static VAStatus
2817 gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
2818                            const struct i965_surface *src_surface,
2819                            const VARectangle *src_rect,
2820                            struct i965_surface *dst_surface,
2821                            const VARectangle *dst_rect,
2822                            void *filter_param)
2823 {
2824     struct i965_driver_data *i965 = i965_driver_data(ctx);
2825     struct pp_dn_context *pp_dn_context = (struct pp_dn_context *)&pp_context->private_context;
2826     struct gen7_pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
2827     struct object_surface *obj_surface;
2828     struct gen7_sampler_dndi *sampler_dn;
2829     VAProcFilterParameterBuffer *dn_filter_param = filter_param; /* FIXME: parameter */
2830     int index;
2831     int w, h;
2832     int orig_w, orig_h;
2833     int dn_strength = 15;
2834     int dndi_top_first = 1;
2835     int dn_progressive = 0;
2836
2837     if (src_surface->flags == I965_SURFACE_FLAG_FRAME) {
2838         dndi_top_first = 1;
2839         dn_progressive = 1;
2840     } else if (src_surface->flags == I965_SURFACE_FLAG_TOP_FIELD_FIRST) {
2841         dndi_top_first = 1;
2842         dn_progressive = 0;
2843     } else {
2844         dndi_top_first = 0;
2845         dn_progressive = 0;
2846     }
2847
2848     if (dn_filter_param) {
2849         float value = dn_filter_param->value;
2850
2851         if (value > 1.0)
2852             value = 1.0;
2853
2854         if (value < 0.0)
2855             value = 0.0;
2856
2857         dn_strength = (int)(value * 31.0F);
2858     }
2859
2860     /* surface */
2861     obj_surface = SURFACE(src_surface->id);
2862     orig_w = obj_surface->orig_width;
2863     orig_h = obj_surface->orig_height;
2864     w = obj_surface->width;
2865     h = obj_surface->height;
2866
2867     if (pp_context->stmm.bo == NULL) {
2868         pp_context->stmm.bo = dri_bo_alloc(i965->intel.bufmgr,
2869                                            "STMM surface",
2870                                            w * h,
2871                                            4096);
2872         assert(pp_context->stmm.bo);
2873     }
2874
2875     /* source UV surface index 1 */
2876     gen7_pp_set_surface_state(ctx, pp_context,
2877                               obj_surface->bo, w * h,
2878                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2879                               1, 0);
2880
2881     /* source YUV surface index 3 */
2882     gen7_pp_set_surface2_state(ctx, pp_context,
2883                                obj_surface->bo, 0,
2884                                orig_w, orig_h, w,
2885                                0, h,
2886                                SURFACE_FORMAT_PLANAR_420_8, 1,
2887                                3);
2888
2889     /* source STMM surface index 5 */
2890     gen7_pp_set_surface_state(ctx, pp_context,
2891                               pp_context->stmm.bo, 0,
2892                               orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2893                               5, 1);
2894
2895     /* destination surface */
2896     obj_surface = SURFACE(dst_surface->id);
2897     orig_w = obj_surface->orig_width;
2898     orig_h = obj_surface->orig_height;
2899     w = obj_surface->width;
2900     h = obj_surface->height;
2901
2902     /* destination Y surface index 7 */
2903     gen7_pp_set_surface_state(ctx, pp_context,
2904                               obj_surface->bo, 0,
2905                               orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
2906                               7, 1);
2907
2908     /* destination UV surface index 8 */
2909     gen7_pp_set_surface_state(ctx, pp_context,
2910                               obj_surface->bo, w * h,
2911                               orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2912                               8, 1);
2913     /* sampler dn */
2914     dri_bo_map(pp_context->sampler_state_table.bo, True);
2915     assert(pp_context->sampler_state_table.bo->virtual);
2916     assert(sizeof(*sampler_dn) == sizeof(int) * 8);
2917     sampler_dn = pp_context->sampler_state_table.bo->virtual;
2918
2919     /* sample dn index 1 */
2920     index = 0;
2921     sampler_dn[index].dw0.denoise_asd_threshold = 0;
2922     sampler_dn[index].dw0.dnmh_delt = 8;
2923     sampler_dn[index].dw0.vdi_walker_y_stride = 0;
2924     sampler_dn[index].dw0.vdi_walker_frame_sharing_enable = 0;
2925     sampler_dn[index].dw0.denoise_maximum_history = 128;      // 128-240
2926     sampler_dn[index].dw0.denoise_stad_threshold = 0;
2927
2928     sampler_dn[index].dw1.denoise_threshold_for_sum_of_complexity_measure = 64;
2929     sampler_dn[index].dw1.denoise_moving_pixel_threshold = 0;
2930     sampler_dn[index].dw1.stmm_c2 = 0;
2931     sampler_dn[index].dw1.low_temporal_difference_threshold = 8;
2932     sampler_dn[index].dw1.temporal_difference_threshold = 16;
2933
2934     sampler_dn[index].dw2.block_noise_estimate_noise_threshold = dn_strength;   // 0-31
2935     sampler_dn[index].dw2.bne_edge_th = 1;
2936     sampler_dn[index].dw2.smooth_mv_th = 0;
2937     sampler_dn[index].dw2.sad_tight_th = 5;
2938     sampler_dn[index].dw2.cat_slope_minus1 = 9;
2939     sampler_dn[index].dw2.good_neighbor_th = 4;
2940
2941     sampler_dn[index].dw3.maximum_stmm = 128;
2942     sampler_dn[index].dw3.multipler_for_vecm = 2;
2943     sampler_dn[index].dw3.blending_constant_across_time_for_small_values_of_stmm = 0;
2944     sampler_dn[index].dw3.blending_constant_across_time_for_large_values_of_stmm = 64;
2945     sampler_dn[index].dw3.stmm_blending_constant_select = 0;
2946
2947     sampler_dn[index].dw4.sdi_delta = 8;
2948     sampler_dn[index].dw4.sdi_threshold = 128;
2949     sampler_dn[index].dw4.stmm_output_shift = 7;                      // stmm_max - stmm_min = 2 ^ stmm_output_shift
2950     sampler_dn[index].dw4.stmm_shift_up = 0;
2951     sampler_dn[index].dw4.stmm_shift_down = 0;
2952     sampler_dn[index].dw4.minimum_stmm = 0;
2953
2954     sampler_dn[index].dw5.fmd_temporal_difference_threshold = 0;
2955     sampler_dn[index].dw5.sdi_fallback_mode_2_constant = 0;
2956     sampler_dn[index].dw5.sdi_fallback_mode_1_t2_constant = 0;
2957     sampler_dn[index].dw5.sdi_fallback_mode_1_t1_constant = 0;
2958
2959     sampler_dn[index].dw6.dn_enable = 1;
2960     sampler_dn[index].dw6.di_enable = 0;
2961     sampler_dn[index].dw6.di_partial = 0;
2962     sampler_dn[index].dw6.dndi_top_first = dndi_top_first;
2963     sampler_dn[index].dw6.dndi_stream_id = 1;
2964     sampler_dn[index].dw6.dndi_first_frame = 1;
2965     sampler_dn[index].dw6.progressive_dn = dn_progressive;
2966     sampler_dn[index].dw6.mcdi_enable = 0;
2967     sampler_dn[index].dw6.fmd_tear_threshold = 32;
2968     sampler_dn[index].dw6.cat_th1 = 0;
2969     sampler_dn[index].dw6.fmd2_vertical_difference_threshold = 32;
2970     sampler_dn[index].dw6.fmd1_vertical_difference_threshold = 32;
2971
2972     sampler_dn[index].dw7.sad_tha = 5;
2973     sampler_dn[index].dw7.sad_thb = 10;
2974     sampler_dn[index].dw7.fmd_for_1st_field_of_current_frame = 2;
2975     sampler_dn[index].dw7.mc_pixel_consistency_th = 25;
2976     sampler_dn[index].dw7.fmd_for_2nd_field_of_previous_frame = 1;
2977     sampler_dn[index].dw7.vdi_walker_enable = 0;
2978     sampler_dn[index].dw7.neighborpixel_th = 10;
2979     sampler_dn[index].dw7.column_width_minus1 = w / 16;
2980
2981     dri_bo_unmap(pp_context->sampler_state_table.bo);
2982
2983     /* private function & data */
2984     pp_context->pp_x_steps = gen7_pp_dn_x_steps;
2985     pp_context->pp_y_steps = gen7_pp_dn_y_steps;
2986     pp_context->pp_set_block_parameter = gen7_pp_dn_set_block_parameter;
2987
2988     pp_static_parameter->grf1.di_statistics_surface_pitch_div2 = w / 2;
2989     pp_static_parameter->grf1.di_statistics_surface_height_div4 = h / 4;
2990     pp_static_parameter->grf1.di_top_field_first = 0;
2991     pp_static_parameter->grf1.pointer_to_inline_parameter = 7;
2992
2993     pp_static_parameter->grf2.di_destination_packed_y_component_offset = 0;
2994     pp_static_parameter->grf2.di_destination_packed_u_component_offset = 1;
2995     pp_static_parameter->grf2.di_destination_packed_v_component_offset = 3;
2996
2997     pp_static_parameter->grf4.di_hoffset_svf_from_dvf = 0;
2998     pp_static_parameter->grf4.di_voffset_svf_from_dvf = 0;
2999
3000     pp_dn_context->dest_w = w;
3001     pp_dn_context->dest_h = h;
3002
3003     dst_surface->flags = src_surface->flags;
3004
3005     return VA_STATUS_SUCCESS;
3006 }
3007
3008 // update u/v offset when the surface format are packed yuv
3009 static void i965_update_src_surface_uv_offset(
3010     VADriverContextP    ctx,
3011     struct i965_post_processing_context *pp_context,
3012     const struct i965_surface *surface)
3013 {
3014     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3015     int fourcc = pp_get_surface_fourcc(ctx, surface);
3016
3017     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3018         pp_static_parameter->grf1.source_packed_u_offset = 1;
3019         pp_static_parameter->grf1.source_packed_v_offset = 3;
3020     }
3021     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3022         pp_static_parameter->grf1.source_packed_y_offset = 1;
3023         pp_static_parameter->grf1.source_packed_v_offset = 2;
3024     }
3025
3026 }
3027
3028 static void i965_update_dst_surface_uv_offset(
3029     VADriverContextP    ctx,
3030     struct i965_post_processing_context *pp_context,
3031     const struct i965_surface *surface)
3032 {
3033     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3034     int fourcc = pp_get_surface_fourcc(ctx, surface);
3035
3036     if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3037         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_u_offset = 1;
3038         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 3;
3039     }
3040     else if (fourcc == VA_FOURCC('U', 'Y', 'V', 'Y')) {
3041         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_y_offset = 1;
3042         pp_static_parameter->grf1.r1_2.load_and_save.destination_packed_v_offset = 2;
3043     }
3044
3045 }
3046
3047 static VAStatus
3048 ironlake_pp_initialize(
3049     VADriverContextP   ctx,
3050     struct i965_post_processing_context *pp_context,
3051     const struct i965_surface *src_surface,
3052     const VARectangle *src_rect,
3053     struct i965_surface *dst_surface,
3054     const VARectangle *dst_rect,
3055     int                pp_index,
3056     void *filter_param
3057 )
3058 {
3059     VAStatus va_status;
3060     struct i965_driver_data *i965 = i965_driver_data(ctx);
3061     struct pp_module *pp_module;
3062     dri_bo *bo;
3063     int static_param_size, inline_param_size;
3064
3065     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3066     bo = dri_bo_alloc(i965->intel.bufmgr,
3067                       "surface state & binding table",
3068                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3069                       4096);
3070     assert(bo);
3071     pp_context->surface_state_binding_table.bo = bo;
3072
3073     dri_bo_unreference(pp_context->curbe.bo);
3074     bo = dri_bo_alloc(i965->intel.bufmgr,
3075                       "constant buffer",
3076                       4096,
3077                       4096);
3078     assert(bo);
3079     pp_context->curbe.bo = bo;
3080
3081     dri_bo_unreference(pp_context->idrt.bo);
3082     bo = dri_bo_alloc(i965->intel.bufmgr,
3083                       "interface discriptor",
3084                       sizeof(struct i965_interface_descriptor),
3085                       4096);
3086     assert(bo);
3087     pp_context->idrt.bo = bo;
3088     pp_context->idrt.num_interface_descriptors = 0;
3089
3090     dri_bo_unreference(pp_context->sampler_state_table.bo);
3091     bo = dri_bo_alloc(i965->intel.bufmgr,
3092                       "sampler state table",
3093                       4096,
3094                       4096);
3095     assert(bo);
3096     dri_bo_map(bo, True);
3097     memset(bo->virtual, 0, bo->size);
3098     dri_bo_unmap(bo);
3099     pp_context->sampler_state_table.bo = bo;
3100
3101     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3102     bo = dri_bo_alloc(i965->intel.bufmgr,
3103                       "sampler 8x8 state ",
3104                       4096,
3105                       4096);
3106     assert(bo);
3107     pp_context->sampler_state_table.bo_8x8 = bo;
3108
3109     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3110     bo = dri_bo_alloc(i965->intel.bufmgr,
3111                       "sampler 8x8 state ",
3112                       4096,
3113                       4096);
3114     assert(bo);
3115     pp_context->sampler_state_table.bo_8x8_uv = bo;
3116
3117     dri_bo_unreference(pp_context->vfe_state.bo);
3118     bo = dri_bo_alloc(i965->intel.bufmgr,
3119                       "vfe state",
3120                       sizeof(struct i965_vfe_state),
3121                       4096);
3122     assert(bo);
3123     pp_context->vfe_state.bo = bo;
3124
3125     if (IS_GEN7(i965->intel.device_id)) {
3126         static_param_size = sizeof(struct gen7_pp_static_parameter);
3127         inline_param_size = sizeof(struct gen7_pp_inline_parameter);
3128     } else {
3129         static_param_size = sizeof(struct pp_static_parameter);
3130         inline_param_size = sizeof(struct pp_inline_parameter);
3131     }
3132
3133     memset(pp_context->pp_static_parameter, 0, static_param_size);
3134     memset(pp_context->pp_inline_parameter, 0, inline_param_size);
3135
3136     // update u/v offset for packed yuv
3137     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3138     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3139
3140     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3141     pp_context->current_pp = pp_index;
3142     pp_module = &pp_context->pp_modules[pp_index];
3143
3144     if (pp_module->initialize)
3145         va_status = pp_module->initialize(ctx, pp_context,
3146                                           src_surface,
3147                                           src_rect,
3148                                           dst_surface,
3149                                           dst_rect,
3150                                           filter_param);
3151     else
3152         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3153
3154     return va_status;
3155 }
3156
3157 static VAStatus
3158 ironlake_post_processing(
3159     VADriverContextP   ctx,
3160     struct i965_post_processing_context *pp_context,
3161     const struct i965_surface *src_surface,
3162     const VARectangle *src_rect,
3163     struct i965_surface *dst_surface,
3164     const VARectangle *dst_rect,
3165     int                pp_index,
3166     void *filter_param
3167 )
3168 {
3169     VAStatus va_status;
3170
3171     va_status = ironlake_pp_initialize(ctx, pp_context,
3172                                        src_surface,
3173                                        src_rect,
3174                                        dst_surface,
3175                                        dst_rect,
3176                                        pp_index,
3177                                        filter_param);
3178
3179     if (va_status == VA_STATUS_SUCCESS) {
3180         ironlake_pp_states_setup(ctx, pp_context);
3181         ironlake_pp_pipeline_setup(ctx, pp_context);
3182     }
3183
3184     return va_status;
3185 }
3186
3187 static VAStatus
3188 gen6_pp_initialize(
3189     VADriverContextP   ctx,
3190     struct i965_post_processing_context *pp_context,
3191     const struct i965_surface *src_surface,
3192     const VARectangle *src_rect,
3193     struct i965_surface *dst_surface,
3194     const VARectangle *dst_rect,
3195     int                pp_index,
3196     void *filter_param
3197 )
3198 {
3199     VAStatus va_status;
3200     struct i965_driver_data *i965 = i965_driver_data(ctx);
3201     struct pp_module *pp_module;
3202     dri_bo *bo;
3203     struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
3204     struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
3205
3206     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3207     bo = dri_bo_alloc(i965->intel.bufmgr,
3208                       "surface state & binding table",
3209                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_PP_SURFACES,
3210                       4096);
3211     assert(bo);
3212     pp_context->surface_state_binding_table.bo = bo;
3213
3214     dri_bo_unreference(pp_context->curbe.bo);
3215     bo = dri_bo_alloc(i965->intel.bufmgr,
3216                       "constant buffer",
3217                       4096,
3218                       4096);
3219     assert(bo);
3220     pp_context->curbe.bo = bo;
3221
3222     dri_bo_unreference(pp_context->idrt.bo);
3223     bo = dri_bo_alloc(i965->intel.bufmgr,
3224                       "interface discriptor",
3225                       sizeof(struct gen6_interface_descriptor_data),
3226                       4096);
3227     assert(bo);
3228     pp_context->idrt.bo = bo;
3229     pp_context->idrt.num_interface_descriptors = 0;
3230
3231     dri_bo_unreference(pp_context->sampler_state_table.bo);
3232     bo = dri_bo_alloc(i965->intel.bufmgr,
3233                       "sampler state table",
3234                       4096,
3235                       4096);
3236     assert(bo);
3237     dri_bo_map(bo, True);
3238     memset(bo->virtual, 0, bo->size);
3239     dri_bo_unmap(bo);
3240     pp_context->sampler_state_table.bo = bo;
3241
3242     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3243     bo = dri_bo_alloc(i965->intel.bufmgr,
3244                       "sampler 8x8 state ",
3245                       4096,
3246                       4096);
3247     assert(bo);
3248     pp_context->sampler_state_table.bo_8x8 = bo;
3249
3250     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3251     bo = dri_bo_alloc(i965->intel.bufmgr,
3252                       "sampler 8x8 state ",
3253                       4096,
3254                       4096);
3255     assert(bo);
3256     pp_context->sampler_state_table.bo_8x8_uv = bo;
3257
3258     dri_bo_unreference(pp_context->vfe_state.bo);
3259     bo = dri_bo_alloc(i965->intel.bufmgr,
3260                       "vfe state",
3261                       sizeof(struct i965_vfe_state),
3262                       4096);
3263     assert(bo);
3264     pp_context->vfe_state.bo = bo;
3265
3266     memset(pp_static_parameter, 0, sizeof(*pp_static_parameter));
3267     memset(pp_inline_parameter, 0, sizeof(*pp_inline_parameter));
3268
3269     // update u/v offset for packed yuv
3270     i965_update_src_surface_uv_offset (ctx, pp_context, src_surface);
3271     i965_update_dst_surface_uv_offset (ctx, pp_context, dst_surface);
3272
3273     assert(pp_index >= PP_NULL && pp_index < NUM_PP_MODULES);
3274     pp_context->current_pp = pp_index;
3275     pp_module = &pp_context->pp_modules[pp_index];
3276
3277     if (pp_module->initialize)
3278         va_status = pp_module->initialize(ctx, pp_context,
3279                                           src_surface,
3280                                           src_rect,
3281                                           dst_surface,
3282                                           dst_rect,
3283                                           filter_param);
3284     else
3285         va_status = VA_STATUS_ERROR_UNIMPLEMENTED;
3286
3287     return va_status;
3288 }
3289
3290 static void
3291 gen6_pp_interface_descriptor_table(VADriverContextP   ctx,
3292                                    struct i965_post_processing_context *pp_context)
3293 {
3294     struct i965_driver_data *i965 = i965_driver_data(ctx);
3295     struct gen6_interface_descriptor_data *desc;
3296     dri_bo *bo;
3297     int pp_index = pp_context->current_pp;
3298
3299     bo = pp_context->idrt.bo;
3300     dri_bo_map(bo, True);
3301     assert(bo->virtual);
3302     desc = bo->virtual;
3303     memset(desc, 0, sizeof(*desc));
3304     desc->desc0.kernel_start_pointer =
3305         pp_context->pp_modules[pp_index].kernel.bo->offset >> 6; /* reloc */
3306     desc->desc1.single_program_flow = 1;
3307     desc->desc1.floating_point_mode = FLOATING_POINT_IEEE_754;
3308     desc->desc2.sampler_count = 1;      /* 1 - 4 samplers used */
3309     desc->desc2.sampler_state_pointer =
3310         pp_context->sampler_state_table.bo->offset >> 5;
3311     desc->desc3.binding_table_entry_count = 0;
3312     desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
3313     desc->desc4.constant_urb_entry_read_offset = 0;
3314
3315     if (IS_GEN7(i965->intel.device_id))
3316         desc->desc4.constant_urb_entry_read_length = 6; /* grf 1-6 */
3317     else
3318         desc->desc4.constant_urb_entry_read_length = 4; /* grf 1-4 */
3319
3320     dri_bo_emit_reloc(bo,
3321                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3322                       0,
3323                       offsetof(struct gen6_interface_descriptor_data, desc0),
3324                       pp_context->pp_modules[pp_index].kernel.bo);
3325
3326     dri_bo_emit_reloc(bo,
3327                       I915_GEM_DOMAIN_INSTRUCTION, 0,
3328                       desc->desc2.sampler_count << 2,
3329                       offsetof(struct gen6_interface_descriptor_data, desc2),
3330                       pp_context->sampler_state_table.bo);
3331
3332     dri_bo_unmap(bo);
3333     pp_context->idrt.num_interface_descriptors++;
3334 }
3335
3336 static void
3337 gen6_pp_upload_constants(VADriverContextP ctx,
3338                          struct i965_post_processing_context *pp_context)
3339 {
3340     struct i965_driver_data *i965 = i965_driver_data(ctx);
3341     unsigned char *constant_buffer;
3342     int param_size;
3343
3344     assert(sizeof(struct pp_static_parameter) == 128);
3345     assert(sizeof(struct gen7_pp_static_parameter) == 192);
3346
3347     if (IS_GEN7(i965->intel.device_id))
3348         param_size = sizeof(struct gen7_pp_static_parameter);
3349     else
3350         param_size = sizeof(struct pp_static_parameter);
3351
3352     dri_bo_map(pp_context->curbe.bo, 1);
3353     assert(pp_context->curbe.bo->virtual);
3354     constant_buffer = pp_context->curbe.bo->virtual;
3355     memcpy(constant_buffer, pp_context->pp_static_parameter, param_size);
3356     dri_bo_unmap(pp_context->curbe.bo);
3357 }
3358
3359 static void
3360 gen6_pp_states_setup(VADriverContextP ctx,
3361                      struct i965_post_processing_context *pp_context)
3362 {
3363     gen6_pp_interface_descriptor_table(ctx, pp_context);
3364     gen6_pp_upload_constants(ctx, pp_context);
3365 }
3366
3367 static void
3368 gen6_pp_pipeline_select(VADriverContextP ctx,
3369                         struct i965_post_processing_context *pp_context)
3370 {
3371     struct intel_batchbuffer *batch = pp_context->batch;
3372
3373     BEGIN_BATCH(batch, 1);
3374     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
3375     ADVANCE_BATCH(batch);
3376 }
3377
3378 static void
3379 gen6_pp_state_base_address(VADriverContextP ctx,
3380                            struct i965_post_processing_context *pp_context)
3381 {
3382     struct intel_batchbuffer *batch = pp_context->batch;
3383
3384     BEGIN_BATCH(batch, 10);
3385     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (10 - 2));
3386     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3387     OUT_RELOC(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
3388     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3389     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3390     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3391     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3392     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3393     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3394     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
3395     ADVANCE_BATCH(batch);
3396 }
3397
3398 static void
3399 gen6_pp_vfe_state(VADriverContextP ctx,
3400                   struct i965_post_processing_context *pp_context)
3401 {
3402     struct intel_batchbuffer *batch = pp_context->batch;
3403
3404     BEGIN_BATCH(batch, 8);
3405     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | (8 - 2));
3406     OUT_BATCH(batch, 0);
3407     OUT_BATCH(batch,
3408               (pp_context->urb.num_vfe_entries - 1) << 16 |
3409               pp_context->urb.num_vfe_entries << 8);
3410     OUT_BATCH(batch, 0);
3411     OUT_BATCH(batch,
3412               (pp_context->urb.size_vfe_entry * 2) << 16 |  /* URB Entry Allocation Size, in 256 bits unit */
3413               (pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2)); /* CURBE Allocation Size, in 256 bits unit */
3414     OUT_BATCH(batch, 0);
3415     OUT_BATCH(batch, 0);
3416     OUT_BATCH(batch, 0);
3417     ADVANCE_BATCH(batch);
3418 }
3419
3420 static void
3421 gen6_pp_curbe_load(VADriverContextP ctx,
3422                    struct i965_post_processing_context *pp_context)
3423 {
3424     struct intel_batchbuffer *batch = pp_context->batch;
3425
3426     assert(pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32 <= pp_context->curbe.bo->size);
3427
3428     BEGIN_BATCH(batch, 4);
3429     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
3430     OUT_BATCH(batch, 0);
3431     OUT_BATCH(batch,
3432               pp_context->urb.size_cs_entry * pp_context->urb.num_cs_entries * 2 * 32);
3433     OUT_RELOC(batch,
3434               pp_context->curbe.bo,
3435               I915_GEM_DOMAIN_INSTRUCTION, 0,
3436               0);
3437     ADVANCE_BATCH(batch);
3438 }
3439
3440 static void
3441 gen6_interface_descriptor_load(VADriverContextP ctx,
3442                                struct i965_post_processing_context *pp_context)
3443 {
3444     struct intel_batchbuffer *batch = pp_context->batch;
3445
3446     BEGIN_BATCH(batch, 4);
3447     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
3448     OUT_BATCH(batch, 0);
3449     OUT_BATCH(batch,
3450               pp_context->idrt.num_interface_descriptors * sizeof(struct gen6_interface_descriptor_data));
3451     OUT_RELOC(batch,
3452               pp_context->idrt.bo,
3453               I915_GEM_DOMAIN_INSTRUCTION, 0,
3454               0);
3455     ADVANCE_BATCH(batch);
3456 }
3457
3458 static void
3459 gen6_pp_object_walker(VADriverContextP ctx,
3460                       struct i965_post_processing_context *pp_context)
3461 {
3462     struct i965_driver_data *i965 = i965_driver_data(ctx);
3463     struct intel_batchbuffer *batch = pp_context->batch;
3464     int x, x_steps, y, y_steps;
3465     int param_size, command_length_in_dws;
3466     dri_bo *command_buffer;
3467     unsigned int *command_ptr;
3468
3469     if (IS_GEN7(i965->intel.device_id))
3470         param_size = sizeof(struct gen7_pp_inline_parameter);
3471     else
3472         param_size = sizeof(struct pp_inline_parameter);
3473
3474     x_steps = pp_context->pp_x_steps(&pp_context->private_context);
3475     y_steps = pp_context->pp_y_steps(&pp_context->private_context);
3476     command_length_in_dws = 6 + (param_size >> 2);
3477     command_buffer = dri_bo_alloc(i965->intel.bufmgr,
3478                                   "command objects buffer",
3479                                   command_length_in_dws * 4 * x_steps * y_steps + 8,
3480                                   4096);
3481
3482     dri_bo_map(command_buffer, 1);
3483     command_ptr = command_buffer->virtual;
3484
3485     for (y = 0; y < y_steps; y++) {
3486         for (x = 0; x < x_steps; x++) {
3487             if (!pp_context->pp_set_block_parameter(pp_context, x, y)) {
3488                 *command_ptr++ = (CMD_MEDIA_OBJECT | (command_length_in_dws - 2));
3489                 *command_ptr++ = 0;
3490                 *command_ptr++ = 0;
3491                 *command_ptr++ = 0;
3492                 *command_ptr++ = 0;
3493                 *command_ptr++ = 0;
3494                 memcpy(command_ptr, pp_context->pp_inline_parameter, param_size);
3495                 command_ptr += (param_size >> 2);
3496             }
3497         }
3498     }
3499
3500     if (command_length_in_dws * x_steps * y_steps % 2 == 0)
3501         *command_ptr++ = 0;
3502
3503     *command_ptr = MI_BATCH_BUFFER_END;
3504
3505     dri_bo_unmap(command_buffer);
3506
3507     BEGIN_BATCH(batch, 2);
3508     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
3509     OUT_RELOC(batch, command_buffer,
3510               I915_GEM_DOMAIN_COMMAND, 0,
3511               0);
3512     ADVANCE_BATCH(batch);
3513
3514     dri_bo_unreference(command_buffer);
3515
3516     /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
3517      * will cause control to pass back to ring buffer
3518      */
3519     intel_batchbuffer_end_atomic(batch);
3520     intel_batchbuffer_flush(batch);
3521     intel_batchbuffer_start_atomic(batch, 0x1000);
3522 }
3523
3524 static void
3525 gen6_pp_pipeline_setup(VADriverContextP ctx,
3526                        struct i965_post_processing_context *pp_context)
3527 {
3528     struct intel_batchbuffer *batch = pp_context->batch;
3529
3530     intel_batchbuffer_start_atomic(batch, 0x1000);
3531     intel_batchbuffer_emit_mi_flush(batch);
3532     gen6_pp_pipeline_select(ctx, pp_context);
3533     gen6_pp_state_base_address(ctx, pp_context);
3534     gen6_pp_vfe_state(ctx, pp_context);
3535     gen6_pp_curbe_load(ctx, pp_context);
3536     gen6_interface_descriptor_load(ctx, pp_context);
3537     gen6_pp_object_walker(ctx, pp_context);
3538     intel_batchbuffer_end_atomic(batch);
3539 }
3540
3541 static VAStatus
3542 gen6_post_processing(
3543     VADriverContextP   ctx,
3544     struct i965_post_processing_context *pp_context,
3545     const struct i965_surface *src_surface,
3546     const VARectangle *src_rect,
3547     struct i965_surface *dst_surface,
3548     const VARectangle *dst_rect,
3549     int                pp_index,
3550     void * filter_param
3551 )
3552 {
3553     VAStatus va_status;
3554
3555     va_status = gen6_pp_initialize(ctx, pp_context,
3556                                    src_surface,
3557                                    src_rect,
3558                                    dst_surface,
3559                                    dst_rect,
3560                                    pp_index,
3561                                    filter_param);
3562
3563     if (va_status == VA_STATUS_SUCCESS) {
3564         gen6_pp_states_setup(ctx, pp_context);
3565         gen6_pp_pipeline_setup(ctx, pp_context);
3566     }
3567
3568     return va_status;
3569 }
3570
3571 static VAStatus
3572 i965_post_processing_internal(
3573     VADriverContextP   ctx,
3574     struct i965_post_processing_context *pp_context,
3575     const struct i965_surface *src_surface,
3576     const VARectangle *src_rect,
3577     struct i965_surface *dst_surface,
3578     const VARectangle *dst_rect,
3579     int                pp_index,
3580     void *filter_param
3581 )
3582 {
3583     struct i965_driver_data *i965 = i965_driver_data(ctx);
3584     VAStatus va_status;
3585
3586     if (IS_GEN6(i965->intel.device_id) ||
3587         IS_GEN7(i965->intel.device_id))
3588         va_status = gen6_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3589     else
3590         va_status = ironlake_post_processing(ctx, pp_context, src_surface, src_rect, dst_surface, dst_rect, pp_index, filter_param);
3591
3592     return va_status;
3593 }
3594
3595 VAStatus
3596 i965_DestroySurfaces(VADriverContextP ctx,
3597                      VASurfaceID *surface_list,
3598                      int num_surfaces);
3599 VAStatus
3600 i965_CreateSurfaces(VADriverContextP ctx,
3601                     int width,
3602                     int height,
3603                     int format,
3604                     int num_surfaces,
3605                     VASurfaceID *surfaces);
3606
3607 static void
3608 rgb_to_yuv(unsigned int argb,
3609            unsigned char *y,
3610            unsigned char *u,
3611            unsigned char *v,
3612            unsigned char *a)
3613 {
3614     int r = ((argb >> 16) & 0xff);
3615     int g = ((argb >> 8) & 0xff);
3616     int b = ((argb >> 0) & 0xff);
3617
3618     *y = (257 * r + 504 * g + 98 * b) / 1000 + 16;
3619     *v = (439 * r - 368 * g - 71 * b) / 1000 + 128;
3620     *u = (-148 * r - 291 * g + 439 * b) / 1000 + 128;
3621     *a = ((argb >> 24) & 0xff);
3622 }
3623
3624 static void
3625 i965_vpp_clear_surface(VADriverContextP ctx,
3626                        struct i965_post_processing_context *pp_context,
3627                        VASurfaceID surface,
3628                        unsigned int color)
3629 {
3630     struct i965_driver_data *i965 = i965_driver_data(ctx);
3631     struct intel_batchbuffer *batch = pp_context->batch;
3632     struct object_surface *obj_surface = SURFACE(surface);
3633     unsigned int blt_cmd, br13;
3634     unsigned int tiling = 0, swizzle = 0;
3635     int pitch;
3636     unsigned char y, u, v, a;
3637
3638     /* Currently only support NV12 surface */
3639     if (!obj_surface || obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3640         return;
3641
3642     rgb_to_yuv(color, &y, &u, &v, &a);
3643
3644     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
3645     blt_cmd = XY_COLOR_BLT_CMD;
3646     pitch = obj_surface->width;
3647
3648     if (tiling != I915_TILING_NONE) {
3649         blt_cmd |= XY_COLOR_BLT_DST_TILED;
3650         pitch >>= 2;
3651     }
3652
3653     br13 = 0xf0 << 16;
3654     br13 |= BR13_8;
3655     br13 |= pitch;
3656
3657     if (IS_GEN6(i965->intel.device_id) ||
3658         IS_GEN7(i965->intel.device_id)) {
3659         intel_batchbuffer_start_atomic_blt(batch, 48);
3660         BEGIN_BLT_BATCH(batch, 12);
3661     } else {
3662         intel_batchbuffer_start_atomic(batch, 48);
3663         BEGIN_BATCH(batch, 12);
3664     }
3665
3666     OUT_BATCH(batch, blt_cmd);
3667     OUT_BATCH(batch, br13);
3668     OUT_BATCH(batch,
3669               0 << 16 |
3670               0);
3671     OUT_BATCH(batch,
3672               obj_surface->height << 16 |
3673               obj_surface->width);
3674     OUT_RELOC(batch, obj_surface->bo,
3675               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3676               0);
3677     OUT_BATCH(batch, y);
3678
3679     br13 = 0xf0 << 16;
3680     br13 |= BR13_565;
3681     br13 |= pitch;
3682
3683     OUT_BATCH(batch, blt_cmd);
3684     OUT_BATCH(batch, br13);
3685     OUT_BATCH(batch,
3686               0 << 16 |
3687               0);
3688     OUT_BATCH(batch,
3689               obj_surface->height / 2 << 16 |
3690               obj_surface->width / 2);
3691     OUT_RELOC(batch, obj_surface->bo,
3692               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
3693               obj_surface->width * obj_surface->y_cb_offset);
3694     OUT_BATCH(batch, v << 8 | u);
3695
3696     ADVANCE_BATCH(batch);
3697     intel_batchbuffer_end_atomic(batch);
3698 }
3699
3700 VASurfaceID
3701 i965_post_processing(
3702     VADriverContextP   ctx,
3703     VASurfaceID        surface,
3704     const VARectangle *src_rect,
3705     const VARectangle *dst_rect,
3706     unsigned int       flags,
3707     int               *has_done_scaling
3708 )
3709 {
3710     struct i965_driver_data *i965 = i965_driver_data(ctx);
3711     VASurfaceID in_surface_id = surface;
3712     VASurfaceID out_surface_id = VA_INVALID_ID;
3713
3714     *has_done_scaling = 0;
3715
3716     if (HAS_PP(i965)) {
3717         struct object_surface *obj_surface;
3718         VAStatus status;
3719         struct i965_surface src_surface;
3720         struct i965_surface dst_surface;
3721
3722         obj_surface = SURFACE(in_surface_id);
3723
3724         /* Currently only support post processing for NV12 surface */
3725         if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2'))
3726             return out_surface_id;
3727
3728         _i965LockMutex(&i965->pp_mutex);
3729
3730         if (flags & I965_PP_FLAG_MCDI) {
3731             status = i965_CreateSurfaces(ctx,
3732                                          obj_surface->orig_width,
3733                                          obj_surface->orig_height,
3734                                          VA_RT_FORMAT_YUV420,
3735                                          1,
3736                                          &out_surface_id);
3737             assert(status == VA_STATUS_SUCCESS);
3738             obj_surface = SURFACE(out_surface_id);
3739             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3740             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3741             src_surface.id = in_surface_id;
3742             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3743             src_surface.flags = (flags & I965_PP_FLAG_TOP_FIELD) ?
3744                 I965_SURFACE_FLAG_TOP_FIELD_FIRST : I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST;
3745             dst_surface.id = out_surface_id;
3746             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3747             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3748
3749             i965_post_processing_internal(ctx, i965->pp_context,
3750                                           &src_surface,
3751                                           src_rect,
3752                                           &dst_surface,
3753                                           dst_rect,
3754                                           PP_NV12_DNDI,
3755                                           NULL);
3756         }
3757
3758         if (flags & I965_PP_FLAG_AVS) {
3759             struct i965_render_state *render_state = &i965->render_state;
3760             struct intel_region *dest_region = render_state->draw_region;
3761
3762             if (out_surface_id != VA_INVALID_ID)
3763                 in_surface_id = out_surface_id;
3764
3765             status = i965_CreateSurfaces(ctx,
3766                                          dest_region->width,
3767                                          dest_region->height,
3768                                          VA_RT_FORMAT_YUV420,
3769                                          1,
3770                                          &out_surface_id);
3771             assert(status == VA_STATUS_SUCCESS);
3772             obj_surface = SURFACE(out_surface_id);
3773             i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
3774             i965_vpp_clear_surface(ctx, i965->pp_context, out_surface_id, 0);
3775             src_surface.id = in_surface_id;
3776             src_surface.type = I965_SURFACE_TYPE_SURFACE;
3777             src_surface.flags = I965_SURFACE_FLAG_FRAME;
3778             dst_surface.id = out_surface_id;
3779             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
3780             dst_surface.flags = I965_SURFACE_FLAG_FRAME;
3781
3782             i965_post_processing_internal(ctx, i965->pp_context,
3783                                           &src_surface,
3784                                           src_rect,
3785                                           &dst_surface,
3786                                           dst_rect,
3787                                           PP_NV12_AVS,
3788                                           NULL);
3789
3790             if (in_surface_id != surface)
3791                 i965_DestroySurfaces(ctx, &in_surface_id, 1);
3792
3793             *has_done_scaling = 1;
3794         }
3795
3796         _i965UnlockMutex(&i965->pp_mutex);
3797     }
3798
3799     return out_surface_id;
3800 }
3801
3802 static VAStatus
3803 i965_image_pl3_processing(VADriverContextP ctx,
3804                           const struct i965_surface *src_surface,
3805                           const VARectangle *src_rect,
3806                           struct i965_surface *dst_surface,
3807                           const VARectangle *dst_rect)
3808 {
3809     struct i965_driver_data *i965 = i965_driver_data(ctx);
3810     struct i965_post_processing_context *pp_context = i965->pp_context;
3811     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3812
3813     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3814         i965_post_processing_internal(ctx, i965->pp_context,
3815                                       src_surface,
3816                                       src_rect,
3817                                       dst_surface,
3818                                       dst_rect,
3819                                       PP_PL3_LOAD_SAVE_N12,
3820                                       NULL);
3821     } else {
3822         i965_post_processing_internal(ctx, i965->pp_context,
3823                                       src_surface,
3824                                       src_rect,
3825                                       dst_surface,
3826                                       dst_rect,
3827                                       PP_PL3_LOAD_SAVE_PL3,
3828                                       NULL);
3829     }
3830
3831     intel_batchbuffer_flush(pp_context->batch);
3832
3833     return VA_STATUS_SUCCESS;
3834 }
3835
3836 static VAStatus
3837 i965_image_pl2_processing(VADriverContextP ctx,
3838                           const struct i965_surface *src_surface,
3839                           const VARectangle *src_rect,
3840                           struct i965_surface *dst_surface,
3841                           const VARectangle *dst_rect)
3842 {
3843     struct i965_driver_data *i965 = i965_driver_data(ctx);
3844     struct i965_post_processing_context *pp_context = i965->pp_context;
3845     int fourcc = pp_get_surface_fourcc(ctx, dst_surface);
3846
3847     if (fourcc == VA_FOURCC('N', 'V', '1', '2')) {
3848         i965_post_processing_internal(ctx, i965->pp_context,
3849                                       src_surface,
3850                                       src_rect,
3851                                       dst_surface,
3852                                       dst_rect,
3853                                       PP_NV12_LOAD_SAVE_N12,
3854                                       NULL);
3855     } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') ||
3856                fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
3857         i965_post_processing_internal(ctx, i965->pp_context,
3858                                       src_surface,
3859                                       src_rect,
3860                                       dst_surface,
3861                                       dst_rect,
3862                                       PP_NV12_LOAD_SAVE_PL3,
3863                                       NULL);
3864     } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
3865         i965_post_processing_internal(ctx, i965->pp_context,
3866                                       src_surface,
3867                                       src_rect,
3868                                       dst_surface,
3869                                       dst_rect,
3870                                       PP_NV12_LOAD_SAVE_PA,
3871                                       NULL);
3872     }
3873
3874     intel_batchbuffer_flush(pp_context->batch);
3875
3876     return VA_STATUS_SUCCESS;
3877 }
3878
3879 VAStatus
3880 i965_image_processing(VADriverContextP ctx,
3881                       const struct i965_surface *src_surface,
3882                       const VARectangle *src_rect,
3883                       struct i965_surface *dst_surface,
3884                       const VARectangle *dst_rect)
3885 {
3886     struct i965_driver_data *i965 = i965_driver_data(ctx);
3887     VAStatus status = VA_STATUS_ERROR_UNIMPLEMENTED;
3888
3889     if (HAS_PP(i965)) {
3890         int fourcc = pp_get_surface_fourcc(ctx, src_surface);
3891
3892         _i965LockMutex(&i965->pp_mutex);
3893
3894         switch (fourcc) {
3895         case VA_FOURCC('Y', 'V', '1', '2'):
3896         case VA_FOURCC('I', '4', '2', '0'):
3897         case VA_FOURCC('I', 'M', 'C', '1'):
3898         case VA_FOURCC('I', 'M', 'C', '3'):
3899             status = i965_image_pl3_processing(ctx,
3900                                                src_surface,
3901                                                src_rect,
3902                                                dst_surface,
3903                                                dst_rect);
3904             break;
3905
3906         case  VA_FOURCC('N', 'V', '1', '2'):
3907             status = i965_image_pl2_processing(ctx,
3908                                                src_surface,
3909                                                src_rect,
3910                                                dst_surface,
3911                                                dst_rect);
3912             break;
3913
3914         default:
3915             status = VA_STATUS_ERROR_UNIMPLEMENTED;
3916             break;
3917         }
3918
3919         _i965UnlockMutex(&i965->pp_mutex);
3920     }
3921
3922     return status;
3923 }
3924
3925 static void
3926 i965_post_processing_context_finalize(struct i965_post_processing_context *pp_context)
3927 {
3928     int i;
3929
3930     dri_bo_unreference(pp_context->surface_state_binding_table.bo);
3931     pp_context->surface_state_binding_table.bo = NULL;
3932
3933     dri_bo_unreference(pp_context->curbe.bo);
3934     pp_context->curbe.bo = NULL;
3935
3936     dri_bo_unreference(pp_context->sampler_state_table.bo);
3937     pp_context->sampler_state_table.bo = NULL;
3938
3939     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8);
3940     pp_context->sampler_state_table.bo_8x8 = NULL;
3941
3942     dri_bo_unreference(pp_context->sampler_state_table.bo_8x8_uv);
3943     pp_context->sampler_state_table.bo_8x8_uv = NULL;
3944
3945     dri_bo_unreference(pp_context->idrt.bo);
3946     pp_context->idrt.bo = NULL;
3947     pp_context->idrt.num_interface_descriptors = 0;
3948
3949     dri_bo_unreference(pp_context->vfe_state.bo);
3950     pp_context->vfe_state.bo = NULL;
3951
3952     dri_bo_unreference(pp_context->stmm.bo);
3953     pp_context->stmm.bo = NULL;
3954
3955     for (i = 0; i < NUM_PP_MODULES; i++) {
3956         struct pp_module *pp_module = &pp_context->pp_modules[i];
3957
3958         dri_bo_unreference(pp_module->kernel.bo);
3959         pp_module->kernel.bo = NULL;
3960     }
3961
3962     free(pp_context->pp_static_parameter);
3963     free(pp_context->pp_inline_parameter);
3964     pp_context->pp_static_parameter = NULL;
3965     pp_context->pp_inline_parameter = NULL;
3966 }
3967
3968 Bool
3969 i965_post_processing_terminate(VADriverContextP ctx)
3970 {
3971     struct i965_driver_data *i965 = i965_driver_data(ctx);
3972     struct i965_post_processing_context *pp_context = i965->pp_context;
3973
3974     if (pp_context) {
3975         i965_post_processing_context_finalize(pp_context);
3976         free(pp_context);
3977     }
3978
3979     i965->pp_context = NULL;
3980
3981     return True;
3982 }
3983
3984 static void
3985 i965_post_processing_context_init(VADriverContextP ctx,
3986                                   struct i965_post_processing_context *pp_context,
3987                                   struct intel_batchbuffer *batch)
3988 {
3989     struct i965_driver_data *i965 = i965_driver_data(ctx);
3990     int i;
3991
3992     pp_context->urb.size = URB_SIZE((&i965->intel));
3993     pp_context->urb.num_vfe_entries = 32;
3994     pp_context->urb.size_vfe_entry = 1;     /* in 512 bits unit */
3995     pp_context->urb.num_cs_entries = 1;
3996
3997     if (IS_GEN7(i965->intel.device_id))
3998         pp_context->urb.size_cs_entry = 4;      /* in 512 bits unit */
3999     else
4000         pp_context->urb.size_cs_entry = 2;
4001
4002     pp_context->urb.vfe_start = 0;
4003     pp_context->urb.cs_start = pp_context->urb.vfe_start +
4004         pp_context->urb.num_vfe_entries * pp_context->urb.size_vfe_entry;
4005     assert(pp_context->urb.cs_start +
4006            pp_context->urb.num_cs_entries * pp_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
4007
4008     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen5));
4009     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen6));
4010     assert(NUM_PP_MODULES == ARRAY_ELEMS(pp_modules_gen7));
4011
4012     if (IS_GEN7(i965->intel.device_id))
4013         memcpy(pp_context->pp_modules, pp_modules_gen7, sizeof(pp_context->pp_modules));
4014     else if (IS_GEN6(i965->intel.device_id))
4015         memcpy(pp_context->pp_modules, pp_modules_gen6, sizeof(pp_context->pp_modules));
4016     else if (IS_IRONLAKE(i965->intel.device_id))
4017         memcpy(pp_context->pp_modules, pp_modules_gen5, sizeof(pp_context->pp_modules));
4018
4019     for (i = 0; i < NUM_PP_MODULES; i++) {
4020         struct pp_module *pp_module = &pp_context->pp_modules[i];
4021         dri_bo_unreference(pp_module->kernel.bo);
4022         if (pp_module->kernel.bin && pp_module->kernel.size) {
4023             pp_module->kernel.bo = dri_bo_alloc(i965->intel.bufmgr,
4024                                                 pp_module->kernel.name,
4025                                                 pp_module->kernel.size,
4026                                                 4096);
4027             assert(pp_module->kernel.bo);
4028             dri_bo_subdata(pp_module->kernel.bo, 0, pp_module->kernel.size, pp_module->kernel.bin);
4029         } else {
4030             pp_module->kernel.bo = NULL;
4031         }
4032     }
4033
4034     /* static & inline parameters */
4035     if (IS_GEN7(i965->intel.device_id)) {
4036         pp_context->pp_static_parameter = calloc(sizeof(struct gen7_pp_static_parameter), 1);
4037         pp_context->pp_inline_parameter = calloc(sizeof(struct gen7_pp_inline_parameter), 1);
4038     } else {
4039         pp_context->pp_static_parameter = calloc(sizeof(struct pp_static_parameter), 1);
4040         pp_context->pp_inline_parameter = calloc(sizeof(struct pp_inline_parameter), 1);
4041     }
4042
4043     pp_context->batch = batch;
4044 }
4045
4046 Bool
4047 i965_post_processing_init(VADriverContextP ctx)
4048 {
4049     struct i965_driver_data *i965 = i965_driver_data(ctx);
4050     struct i965_post_processing_context *pp_context = i965->pp_context;
4051
4052     if (HAS_PP(i965)) {
4053         if (pp_context == NULL) {
4054             pp_context = calloc(1, sizeof(*pp_context));
4055             i965_post_processing_context_init(ctx, pp_context, i965->batch);
4056             i965->pp_context = pp_context;
4057         }
4058     }
4059
4060     return True;
4061 }
4062
4063 static const int procfilter_to_pp_flag[VAProcFilterCount] = {
4064     PP_NULL,    /* VAProcFilterNone */
4065     PP_NV12_DN, /* VAProcFilterNoiseReduction */
4066     PP_NV12_DNDI, /* VAProcFilterDeinterlacing */
4067     PP_NULL,    /* VAProcFilterSharpening */
4068     PP_NULL,    /* VAProcFilterColorBalance */
4069     PP_NULL,    /* VAProcFilterColorStandard */
4070 };
4071
4072 static const int proc_frame_to_pp_frame[3] = {
4073     I965_SURFACE_FLAG_FRAME,
4074     I965_SURFACE_FLAG_TOP_FIELD_FIRST,
4075     I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
4076 };
4077
4078 static void
4079 i965_proc_picture(VADriverContextP ctx,
4080                   VAProfile profile,
4081                   union codec_state *codec_state,
4082                   struct hw_context *hw_context)
4083 {
4084     struct i965_driver_data *i965 = i965_driver_data(ctx);
4085     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4086     struct proc_state *proc_state = &codec_state->proc;
4087     VAProcPipelineParameterBuffer *pipeline_param = (VAProcPipelineParameterBuffer *)proc_state->pipeline_param->buffer;
4088     struct object_surface *obj_surface;
4089     struct i965_surface src_surface, dst_surface;
4090     VARectangle src_rect, dst_rect;
4091     VAStatus status;
4092     int i;
4093     VASurfaceID tmp_surfaces[VAProcFilterCount + 4];
4094     int num_tmp_surfaces = 0;
4095     unsigned int tiling = 0, swizzle = 0;
4096     int in_width, in_height;
4097
4098     assert(pipeline_param->surface != VA_INVALID_ID);
4099     assert(proc_state->current_render_target != VA_INVALID_ID);
4100
4101     obj_surface = SURFACE(pipeline_param->surface);
4102     in_width = obj_surface->orig_width;
4103     in_height = obj_surface->orig_height;
4104     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
4105
4106     src_surface.id = pipeline_param->surface;
4107     src_surface.type = I965_SURFACE_TYPE_SURFACE;
4108     src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4109
4110     if (obj_surface->fourcc != VA_FOURCC('N', 'V', '1', '2')) {
4111         VASurfaceID out_surface_id = VA_INVALID_ID;
4112
4113         src_surface.id = pipeline_param->surface;
4114         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4115         src_surface.flags = I965_SURFACE_FLAG_FRAME;
4116         src_rect.x = 0;
4117         src_rect.y = 0;
4118         src_rect.width = in_width;
4119         src_rect.height = in_height;
4120
4121         status = i965_CreateSurfaces(ctx,
4122                                      in_width,
4123                                      in_height,
4124                                      VA_RT_FORMAT_YUV420,
4125                                      1,
4126                                      &out_surface_id);
4127         assert(status == VA_STATUS_SUCCESS);
4128         tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4129         obj_surface = SURFACE(out_surface_id);
4130         i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
4131
4132         dst_surface.id = out_surface_id;
4133         dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4134         dst_surface.flags = I965_SURFACE_FLAG_FRAME;
4135         dst_rect.x = 0;
4136         dst_rect.y = 0;
4137         dst_rect.width = in_width;
4138         dst_rect.height = in_height;
4139
4140         status = i965_image_processing(ctx,
4141                                        &src_surface,
4142                                        &src_rect,
4143                                        &dst_surface,
4144                                        &dst_rect);
4145         assert(status == VA_STATUS_SUCCESS);
4146
4147         src_surface.id = out_surface_id;
4148         src_surface.type = I965_SURFACE_TYPE_SURFACE;
4149         src_surface.flags = proc_frame_to_pp_frame[pipeline_param->filter_flags & 0x3];
4150     }
4151
4152     if (pipeline_param->surface_region) {
4153         src_rect.x = pipeline_param->surface_region->x;
4154         src_rect.y = pipeline_param->surface_region->y;
4155         src_rect.width = pipeline_param->surface_region->width;
4156         src_rect.height = pipeline_param->surface_region->height;
4157     } else {
4158         src_rect.x = 0;
4159         src_rect.y = 0;
4160         src_rect.width = in_width;
4161         src_rect.height = in_height;
4162     }
4163
4164     if (pipeline_param->output_region) {
4165         dst_rect.x = pipeline_param->output_region->x;
4166         dst_rect.y = pipeline_param->output_region->y;
4167         dst_rect.width = pipeline_param->output_region->width;
4168         dst_rect.height = pipeline_param->output_region->height;
4169     } else {
4170         dst_rect.x = 0;
4171         dst_rect.y = 0;
4172         dst_rect.width = in_width;
4173         dst_rect.height = in_height;
4174     }
4175
4176     obj_surface = SURFACE(proc_state->current_render_target);
4177     i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4178     i965_vpp_clear_surface(ctx, i965->pp_context, proc_state->current_render_target, pipeline_param->output_background_color);
4179
4180     for (i = 0; i < pipeline_param->num_filters; i++) {
4181         struct object_buffer *obj_buffer = BUFFER(pipeline_param->filters[i]);
4182         VAProcFilterParameterBufferBase *filter_param = (VAProcFilterParameterBufferBase *)obj_buffer->buffer_store->buffer;
4183         VAProcFilterType filter_type = filter_param->type;
4184         VASurfaceID out_surface_id = VA_INVALID_ID;
4185         int kernel_index = procfilter_to_pp_flag[filter_type];
4186
4187         if (kernel_index != PP_NULL &&
4188             proc_context->pp_context.pp_modules[kernel_index].kernel.bo != NULL) {
4189             status = i965_CreateSurfaces(ctx,
4190                                          in_width,
4191                                          in_height,
4192                                          VA_RT_FORMAT_YUV420,
4193                                          1,
4194                                          &out_surface_id);
4195             assert(status == VA_STATUS_SUCCESS);
4196             tmp_surfaces[num_tmp_surfaces++] = out_surface_id;
4197             obj_surface = SURFACE(out_surface_id);
4198             i965_check_alloc_surface_bo(ctx, obj_surface, !!tiling, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
4199             dst_surface.id = out_surface_id;
4200             dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4201             status = i965_post_processing_internal(ctx, &proc_context->pp_context,
4202                                                    &src_surface,
4203                                                    &src_rect,
4204                                                    &dst_surface,
4205                                                    &src_rect,
4206                                                    kernel_index,
4207                                                    filter_param);
4208
4209             if (status == VA_STATUS_SUCCESS) {
4210                 src_surface.id = dst_surface.id;
4211                 src_surface.type = dst_surface.type;
4212                 src_surface.flags = dst_surface.flags;
4213             }
4214         }
4215     }
4216
4217     dst_surface.id = proc_state->current_render_target;
4218     dst_surface.type = I965_SURFACE_TYPE_SURFACE;
4219
4220     if (src_rect.width == dst_rect.width &&
4221         src_rect.height == dst_rect.height) {
4222         i965_post_processing_internal(ctx, &proc_context->pp_context,
4223                                       &src_surface,
4224                                       &src_rect,
4225                                       &dst_surface,
4226                                       &dst_rect,
4227                                       PP_NV12_LOAD_SAVE_N12,
4228                                       NULL);
4229     } else {
4230
4231         i965_post_processing_internal(ctx, &proc_context->pp_context,
4232                                       &src_surface,
4233                                       &src_rect,
4234                                       &dst_surface,
4235                                       &dst_rect,
4236                                       (pipeline_param->filter_flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC ?
4237                                       PP_NV12_AVS : PP_NV12_SCALING,
4238                                       NULL);
4239     }
4240
4241     if (num_tmp_surfaces)
4242         i965_DestroySurfaces(ctx,
4243                              tmp_surfaces,
4244                              num_tmp_surfaces);
4245
4246     intel_batchbuffer_flush(hw_context->batch);
4247 }
4248
4249 static void
4250 i965_proc_context_destroy(void *hw_context)
4251 {
4252     struct i965_proc_context *proc_context = (struct i965_proc_context *)hw_context;
4253
4254     i965_post_processing_context_finalize(&proc_context->pp_context);
4255     intel_batchbuffer_free(proc_context->base.batch);
4256     free(proc_context);
4257 }
4258
4259 struct hw_context *
4260 i965_proc_context_init(VADriverContextP ctx, struct object_config *obj_config)
4261 {
4262     struct intel_driver_data *intel = intel_driver_data(ctx);
4263     struct i965_proc_context *proc_context = calloc(1, sizeof(struct i965_proc_context));
4264
4265     proc_context->base.destroy = i965_proc_context_destroy;
4266     proc_context->base.run = i965_proc_picture;
4267     proc_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
4268     i965_post_processing_context_init(ctx, &proc_context->pp_context, proc_context->base.batch);
4269
4270     return (struct hw_context *)proc_context;
4271 }