7 #include "intel_batchbuffer.h"
8 #include "intel_driver.h"
10 #include "i965_defines.h"
11 #include "i965_drv_video.h"
12 #include "i965_media.h"
13 #include "i965_media_h264.h"
25 struct intra_kernel_header
28 unsigned char intra_4x4_luma_mode_0_offset;
29 unsigned char intra_4x4_luma_mode_1_offset;
30 unsigned char intra_4x4_luma_mode_2_offset;
31 unsigned char intra_4x4_luma_mode_3_offset;
33 unsigned char intra_4x4_luma_mode_4_offset;
34 unsigned char intra_4x4_luma_mode_5_offset;
35 unsigned char intra_4x4_luma_mode_6_offset;
36 unsigned char intra_4x4_luma_mode_7_offset;
38 unsigned char intra_4x4_luma_mode_8_offset;
40 unsigned short top_reference_offset;
42 unsigned char intra_8x8_luma_mode_0_offset;
43 unsigned char intra_8x8_luma_mode_1_offset;
44 unsigned char intra_8x8_luma_mode_2_offset;
45 unsigned char intra_8x8_luma_mode_3_offset;
47 unsigned char intra_8x8_luma_mode_4_offset;
48 unsigned char intra_8x8_luma_mode_5_offset;
49 unsigned char intra_8x8_luma_mode_6_offset;
50 unsigned char intra_8x8_luma_mode_7_offset;
52 unsigned char intra_8x8_luma_mode_8_offset;
54 unsigned short const_reverse_data_transfer_intra_8x8;
56 unsigned char intra_16x16_luma_mode_0_offset;
57 unsigned char intra_16x16_luma_mode_1_offset;
58 unsigned char intra_16x16_luma_mode_2_offset;
59 unsigned char intra_16x16_luma_mode_3_offset;
61 unsigned char intra_chroma_mode_0_offset;
62 unsigned char intra_chroma_mode_1_offset;
63 unsigned char intra_chroma_mode_2_offset;
64 unsigned char intra_chroma_mode_3_offset;
66 unsigned int const_intra_16x16_plane_0;
68 unsigned int const_intra_16x16_chroma_plane_0;
70 unsigned int const_intra_16x16_chroma_plane_1;
72 unsigned int const_intra_16x16_plane_1;
74 unsigned int left_shift_count_reverse_dw_ordering;
76 unsigned int const_reverse_data_transfer_intra_4x4;
78 unsigned int intra_4x4_pred_mode_offset;
81 struct inter_kernel_header
83 unsigned short weight_offset;
84 unsigned char weight_offset_flag;
88 #include "shaders/h264/mc/export.inc"
89 static unsigned long avc_mc_kernel_offset_gen4[] = {
90 INTRA_16x16_IP * INST_UNIT_GEN4,
91 INTRA_8x8_IP * INST_UNIT_GEN4,
92 INTRA_4x4_IP * INST_UNIT_GEN4,
93 INTRA_PCM_IP * INST_UNIT_GEN4,
94 FRAME_MB_IP * INST_UNIT_GEN4,
95 FIELD_MB_IP * INST_UNIT_GEN4,
96 MBAFF_MB_IP * INST_UNIT_GEN4
99 struct intra_kernel_header intra_kernel_header_gen4 = {
101 (INTRA_4X4_HORIZONTAL_IP - INTRA_4X4_VERTICAL_IP),
102 (INTRA_4X4_DC_IP - INTRA_4X4_VERTICAL_IP),
103 (INTRA_4X4_DIAG_DOWN_LEFT_IP - INTRA_4X4_VERTICAL_IP),
105 (INTRA_4X4_DIAG_DOWN_RIGHT_IP - INTRA_4X4_VERTICAL_IP),
106 (INTRA_4X4_VERT_RIGHT_IP - INTRA_4X4_VERTICAL_IP),
107 (INTRA_4X4_HOR_DOWN_IP - INTRA_4X4_VERTICAL_IP),
108 (INTRA_4X4_VERT_LEFT_IP - INTRA_4X4_VERTICAL_IP),
110 (INTRA_4X4_HOR_UP_IP - INTRA_4X4_VERTICAL_IP),
115 (INTRA_8X8_HORIZONTAL_IP - INTRA_8X8_VERTICAL_IP),
116 (INTRA_8X8_DC_IP - INTRA_8X8_VERTICAL_IP),
117 (INTRA_8X8_DIAG_DOWN_LEFT_IP - INTRA_8X8_VERTICAL_IP),
119 (INTRA_8X8_DIAG_DOWN_RIGHT_IP - INTRA_8X8_VERTICAL_IP),
120 (INTRA_8X8_VERT_RIGHT_IP - INTRA_8X8_VERTICAL_IP),
121 (INTRA_8X8_HOR_DOWN_IP - INTRA_8X8_VERTICAL_IP),
122 (INTRA_8X8_VERT_LEFT_IP - INTRA_8X8_VERTICAL_IP),
124 (INTRA_8X8_HOR_UP_IP - INTRA_8X8_VERTICAL_IP),
129 (INTRA_16x16_HORIZONTAL_IP - INTRA_16x16_VERTICAL_IP),
130 (INTRA_16x16_DC_IP - INTRA_16x16_VERTICAL_IP),
131 (INTRA_16x16_PLANE_IP - INTRA_16x16_VERTICAL_IP),
134 (INTRA_CHROMA_HORIZONTAL_IP - INTRA_CHROMA_DC_IP),
135 (INTRA_CHROMA_VERTICAL_IP - INTRA_CHROMA_DC_IP),
136 (INTRA_Chroma_PLANE_IP - INTRA_CHROMA_DC_IP),
150 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB3_IP) * 0x1000000 +
151 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB2_IP) * 0x10000 +
152 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB1_IP) * 0x100 +
153 (intra_Pred_4x4_Y_IP - ADD_ERROR_SB0_IP)
156 static const uint32_t h264_avc_combined_gen4[][4] = {
157 #include "shaders/h264/mc/avc_mc.g4b"
160 static const uint32_t h264_avc_null_gen4[][4] = {
161 #include "shaders/h264/mc/null.g4b"
164 static struct i965_kernel h264_avc_kernels_gen4[] = {
166 "AVC combined kernel",
168 h264_avc_combined_gen4,
169 sizeof(h264_avc_combined_gen4),
177 sizeof(h264_avc_null_gen4),
183 #include "shaders/h264/mc/export.inc.gen5"
184 static unsigned long avc_mc_kernel_offset_gen5[] = {
185 INTRA_16x16_IP_GEN5 * INST_UNIT_GEN5,
186 INTRA_8x8_IP_GEN5 * INST_UNIT_GEN5,
187 INTRA_4x4_IP_GEN5 * INST_UNIT_GEN5,
188 INTRA_PCM_IP_GEN5 * INST_UNIT_GEN5,
189 FRAME_MB_IP_GEN5 * INST_UNIT_GEN5,
190 FIELD_MB_IP_GEN5 * INST_UNIT_GEN5,
191 MBAFF_MB_IP_GEN5 * INST_UNIT_GEN5
194 struct intra_kernel_header intra_kernel_header_gen5 = {
196 (INTRA_4X4_HORIZONTAL_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
197 (INTRA_4X4_DC_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
198 (INTRA_4X4_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
200 (INTRA_4X4_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
201 (INTRA_4X4_VERT_RIGHT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
202 (INTRA_4X4_HOR_DOWN_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
203 (INTRA_4X4_VERT_LEFT_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
205 (INTRA_4X4_HOR_UP_IP_GEN5 - INTRA_4X4_VERTICAL_IP_GEN5),
210 (INTRA_8X8_HORIZONTAL_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
211 (INTRA_8X8_DC_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
212 (INTRA_8X8_DIAG_DOWN_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
214 (INTRA_8X8_DIAG_DOWN_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
215 (INTRA_8X8_VERT_RIGHT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
216 (INTRA_8X8_HOR_DOWN_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
217 (INTRA_8X8_VERT_LEFT_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
219 (INTRA_8X8_HOR_UP_IP_GEN5 - INTRA_8X8_VERTICAL_IP_GEN5),
224 (INTRA_16x16_HORIZONTAL_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5),
225 (INTRA_16x16_DC_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5),
226 (INTRA_16x16_PLANE_IP_GEN5 - INTRA_16x16_VERTICAL_IP_GEN5),
229 (INTRA_CHROMA_HORIZONTAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5),
230 (INTRA_CHROMA_VERTICAL_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5),
231 (INTRA_Chroma_PLANE_IP_GEN5 - INTRA_CHROMA_DC_IP_GEN5),
245 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB3_IP_GEN5) * 0x1000000 +
246 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB2_IP_GEN5) * 0x10000 +
247 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB1_IP_GEN5) * 0x100 +
248 (intra_Pred_4x4_Y_IP_GEN5 - ADD_ERROR_SB0_IP_GEN5)
251 static const uint32_t h264_avc_combined_gen5[][4] = {
252 #include "shaders/h264/mc/avc_mc.g4b.gen5"
255 static const uint32_t h264_avc_null_gen5[][4] = {
256 #include "shaders/h264/mc/null.g4b.gen5"
259 static struct i965_kernel h264_avc_kernels_gen5[] = {
261 "AVC combined kernel",
263 h264_avc_combined_gen5,
264 sizeof(h264_avc_combined_gen5),
272 sizeof(h264_avc_null_gen5),
277 #define NUM_AVC_MC_INTERFACES (sizeof(avc_mc_kernel_offset_gen4) / sizeof(avc_mc_kernel_offset_gen4[0]))
278 static unsigned long *avc_mc_kernel_offset = NULL;
280 static struct intra_kernel_header *intra_kernel_header = NULL;
283 i965_media_h264_surface_state(VADriverContextP ctx,
285 struct object_surface *obj_surface,
286 unsigned long offset,
287 int w, int h, int pitch,
289 int vert_line_stride,
290 int vert_line_stride_ofs,
292 struct i965_media_context *media_context)
294 struct i965_driver_data *i965 = i965_driver_data(ctx);
295 struct i965_surface_state *ss;
297 uint32_t write_domain, read_domain;
299 assert(obj_surface->bo);
301 bo = dri_bo_alloc(i965->intel.bufmgr,
303 sizeof(struct i965_surface_state), 32);
308 memset(ss, 0, sizeof(*ss));
309 ss->ss0.surface_type = I965_SURFACE_2D;
310 ss->ss0.surface_format = format;
311 ss->ss0.vert_line_stride = vert_line_stride;
312 ss->ss0.vert_line_stride_ofs = vert_line_stride_ofs;
313 ss->ss1.base_addr = obj_surface->bo->offset + offset;
314 ss->ss2.width = w - 1;
315 ss->ss2.height = h - 1;
316 ss->ss3.pitch = pitch - 1;
319 write_domain = I915_GEM_DOMAIN_RENDER;
320 read_domain = I915_GEM_DOMAIN_RENDER;
323 read_domain = I915_GEM_DOMAIN_SAMPLER;
326 dri_bo_emit_reloc(bo,
327 read_domain, write_domain,
329 offsetof(struct i965_surface_state, ss1),
333 assert(index < MAX_MEDIA_SURFACES);
334 media_context->surface_state[index].bo = bo;
338 i965_media_h264_surfaces_setup(VADriverContextP ctx,
339 struct decode_state *decode_state,
340 struct i965_media_context *media_context)
342 struct i965_driver_data *i965 = i965_driver_data(ctx);
343 struct i965_h264_context *i965_h264_context;
344 struct object_surface *obj_surface;
345 VAPictureParameterBufferH264 *pic_param;
346 VAPictureH264 *va_pic;
350 assert(media_context->private_context);
351 i965_h264_context = (struct i965_h264_context *)media_context->private_context;
353 assert(decode_state->pic_param && decode_state->pic_param->buffer);
354 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
357 va_pic = &pic_param->CurrPic;
358 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
359 obj_surface = SURFACE(va_pic->picture_id);
361 w = obj_surface->width;
362 h = obj_surface->height;
363 field_picture = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
364 i965_media_h264_surface_state(ctx, 0, obj_surface,
365 0, w / 4, h / (1 + field_picture), w,
368 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
369 I965_SURFACEFORMAT_R8_SINT, /* Y */
371 i965_media_h264_surface_state(ctx, 1, obj_surface,
372 w * h, w / 4, h / 2 / (1 + field_picture), w,
375 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
376 I965_SURFACEFORMAT_R8G8_SINT, /* INTERLEAVED U/V */
379 /* Reference Pictures */
380 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
381 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID) {
383 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
384 va_pic = &pic_param->ReferenceFrames[j];
386 if (va_pic->flags & VA_PICTURE_H264_INVALID)
389 if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) {
397 obj_surface = SURFACE(va_pic->picture_id);
399 w = obj_surface->width;
400 h = obj_surface->height;
401 field_picture = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
402 i965_media_h264_surface_state(ctx, 2 + i, obj_surface,
403 0, w / 4, h / (1 + field_picture), w,
406 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
407 I965_SURFACEFORMAT_R8_SINT, /* Y */
409 i965_media_h264_surface_state(ctx, 18 + i, obj_surface,
410 w * h, w / 4, h / 2 / (1 + field_picture), w,
413 !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD),
414 I965_SURFACEFORMAT_R8G8_SINT, /* INTERLEAVED U/V */
421 i965_media_h264_binding_table(VADriverContextP ctx, struct i965_media_context *media_context)
424 unsigned int *binding_table;
425 dri_bo *bo = media_context->binding_table.bo;
429 binding_table = bo->virtual;
430 memset(binding_table, 0, bo->size);
432 for (i = 0; i < MAX_MEDIA_SURFACES; i++) {
433 if (media_context->surface_state[i].bo) {
434 binding_table[i] = media_context->surface_state[i].bo->offset;
435 dri_bo_emit_reloc(bo,
436 I915_GEM_DOMAIN_INSTRUCTION, 0,
438 i * sizeof(*binding_table),
439 media_context->surface_state[i].bo);
443 dri_bo_unmap(media_context->binding_table.bo);
447 i965_media_h264_interface_descriptor_remap_table(VADriverContextP ctx, struct i965_media_context *media_context)
449 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)media_context->private_context;
450 struct i965_interface_descriptor *desc;
454 bo = media_context->idrt.bo;
459 for (i = 0; i < NUM_AVC_MC_INTERFACES; i++) {
460 int kernel_offset = avc_mc_kernel_offset[i];
461 memset(desc, 0, sizeof(*desc));
462 desc->desc0.grf_reg_blocks = 7;
463 desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
464 desc->desc1.const_urb_entry_read_offset = 0;
465 desc->desc1.const_urb_entry_read_len = 2;
466 desc->desc3.binding_table_entry_count = 0;
467 desc->desc3.binding_table_pointer =
468 media_context->binding_table.bo->offset >> 5; /*reloc */
470 dri_bo_emit_reloc(bo,
471 I915_GEM_DOMAIN_INSTRUCTION, 0,
472 desc->desc0.grf_reg_blocks + kernel_offset,
473 i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
474 i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo);
476 dri_bo_emit_reloc(bo,
477 I915_GEM_DOMAIN_INSTRUCTION, 0,
478 desc->desc3.binding_table_entry_count,
479 i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
480 media_context->binding_table.bo);
488 i965_media_h264_vfe_state(VADriverContextP ctx, struct i965_media_context *media_context)
490 struct i965_vfe_state *vfe_state;
493 bo = media_context->vfe_state.bo;
496 vfe_state = bo->virtual;
497 memset(vfe_state, 0, sizeof(*vfe_state));
498 vfe_state->vfe0.extend_vfe_state_present = 1;
499 vfe_state->vfe1.max_threads = media_context->urb.num_vfe_entries - 1;
500 vfe_state->vfe1.urb_entry_alloc_size = media_context->urb.size_vfe_entry - 1;
501 vfe_state->vfe1.num_urb_entries = media_context->urb.num_vfe_entries;
502 vfe_state->vfe1.vfe_mode = VFE_AVC_IT_MODE;
503 vfe_state->vfe1.children_present = 0;
504 vfe_state->vfe2.interface_descriptor_base =
505 media_context->idrt.bo->offset >> 4; /* reloc */
506 dri_bo_emit_reloc(bo,
507 I915_GEM_DOMAIN_INSTRUCTION, 0,
509 offsetof(struct i965_vfe_state, vfe2),
510 media_context->idrt.bo);
515 i965_media_h264_vfe_state_extension(VADriverContextP ctx,
516 struct decode_state *decode_state,
517 struct i965_media_context *media_context)
519 struct i965_h264_context *i965_h264_context;
520 struct i965_vfe_state_ex *vfe_state_ex;
521 VAPictureParameterBufferH264 *pic_param;
522 int mbaff_frame_flag;
524 assert(media_context->private_context);
525 i965_h264_context = (struct i965_h264_context *)media_context->private_context;
527 assert(decode_state->pic_param && decode_state->pic_param->buffer);
528 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
529 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
530 !pic_param->pic_fields.bits.field_pic_flag);
532 assert(media_context->extended_state.bo);
533 dri_bo_map(media_context->extended_state.bo, 1);
534 assert(media_context->extended_state.bo->virtual);
535 vfe_state_ex = media_context->extended_state.bo->virtual;
536 memset(vfe_state_ex, 0, sizeof(*vfe_state_ex));
539 * Indirect data buffer:
540 * --------------------------------------------------------
541 * | Motion Vectors | Weight/Offset data | Residual data |
542 * --------------------------------------------------------
543 * R4-R7: Motion Vectors
544 * R8-R9: Weight/Offset
545 * R10-R33: Residual data
547 vfe_state_ex->vfex1.avc.residual_data_fix_offset_flag = !!RESIDUAL_DATA_OFFSET;
548 vfe_state_ex->vfex1.avc.residual_data_offset = RESIDUAL_DATA_OFFSET;
550 if (i965_h264_context->picture.i_flag) {
551 vfe_state_ex->vfex1.avc.sub_field_present_flag = PRESENT_NOMV; /* NoMV */
552 vfe_state_ex->vfex1.avc.weight_grf_offset = 0;
553 vfe_state_ex->vfex1.avc.residual_grf_offset = 0;
555 vfe_state_ex->vfex1.avc.sub_field_present_flag = PRESENT_MV_WO; /* Both MV and W/O */
556 vfe_state_ex->vfex1.avc.weight_grf_offset = 4;
557 vfe_state_ex->vfex1.avc.residual_grf_offset = 6;
560 if (!pic_param->pic_fields.bits.field_pic_flag) {
561 if (mbaff_frame_flag) {
562 vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16;
563 vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8;
564 vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4;
565 vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM;
566 vfe_state_ex->remap_table0.remap_index_4 = MBAFF_MOTION;
567 vfe_state_ex->remap_table0.remap_index_5 = MBAFF_MOTION;
568 vfe_state_ex->remap_table0.remap_index_6 = MBAFF_MOTION;
569 vfe_state_ex->remap_table0.remap_index_7 = MBAFF_MOTION;
571 vfe_state_ex->remap_table1.remap_index_8 = MBAFF_MOTION;
572 vfe_state_ex->remap_table1.remap_index_9 = MBAFF_MOTION;
573 vfe_state_ex->remap_table1.remap_index_10 = MBAFF_MOTION;
574 vfe_state_ex->remap_table1.remap_index_11 = MBAFF_MOTION;
575 vfe_state_ex->remap_table1.remap_index_12 = MBAFF_MOTION;
576 vfe_state_ex->remap_table1.remap_index_13 = MBAFF_MOTION;
577 vfe_state_ex->remap_table1.remap_index_14 = MBAFF_MOTION;
578 vfe_state_ex->remap_table1.remap_index_15 = MBAFF_MOTION;
580 vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16;
581 vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8;
582 vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4;
583 vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM;
584 vfe_state_ex->remap_table0.remap_index_4 = FRAMEMB_MOTION;
585 vfe_state_ex->remap_table0.remap_index_5 = FRAMEMB_MOTION;
586 vfe_state_ex->remap_table0.remap_index_6 = FRAMEMB_MOTION;
587 vfe_state_ex->remap_table0.remap_index_7 = FRAMEMB_MOTION;
589 vfe_state_ex->remap_table1.remap_index_8 = FRAMEMB_MOTION;
590 vfe_state_ex->remap_table1.remap_index_9 = FRAMEMB_MOTION;
591 vfe_state_ex->remap_table1.remap_index_10 = FRAMEMB_MOTION;
592 vfe_state_ex->remap_table1.remap_index_11 = FRAMEMB_MOTION;
593 vfe_state_ex->remap_table1.remap_index_12 = FRAMEMB_MOTION;
594 vfe_state_ex->remap_table1.remap_index_13 = FRAMEMB_MOTION;
595 vfe_state_ex->remap_table1.remap_index_14 = FRAMEMB_MOTION;
596 vfe_state_ex->remap_table1.remap_index_15 = FRAMEMB_MOTION;
599 vfe_state_ex->remap_table0.remap_index_0 = INTRA_16X16;
600 vfe_state_ex->remap_table0.remap_index_1 = INTRA_8X8;
601 vfe_state_ex->remap_table0.remap_index_2 = INTRA_4X4;
602 vfe_state_ex->remap_table0.remap_index_3 = INTRA_PCM;
603 vfe_state_ex->remap_table0.remap_index_4 = FIELDMB_MOTION;
604 vfe_state_ex->remap_table0.remap_index_5 = FIELDMB_MOTION;
605 vfe_state_ex->remap_table0.remap_index_6 = FIELDMB_MOTION;
606 vfe_state_ex->remap_table0.remap_index_7 = FIELDMB_MOTION;
608 vfe_state_ex->remap_table1.remap_index_8 = FIELDMB_MOTION;
609 vfe_state_ex->remap_table1.remap_index_9 = FIELDMB_MOTION;
610 vfe_state_ex->remap_table1.remap_index_10 = FIELDMB_MOTION;
611 vfe_state_ex->remap_table1.remap_index_11 = FIELDMB_MOTION;
612 vfe_state_ex->remap_table1.remap_index_12 = FIELDMB_MOTION;
613 vfe_state_ex->remap_table1.remap_index_13 = FIELDMB_MOTION;
614 vfe_state_ex->remap_table1.remap_index_14 = FIELDMB_MOTION;
615 vfe_state_ex->remap_table1.remap_index_15 = FIELDMB_MOTION;
618 if (i965_h264_context->use_avc_hw_scoreboard) {
619 vfe_state_ex->scoreboard0.enable = 1;
620 vfe_state_ex->scoreboard0.type = SCOREBOARD_STALLING;
621 vfe_state_ex->scoreboard0.mask = 0xff;
623 vfe_state_ex->scoreboard1.delta_x0 = -1;
624 vfe_state_ex->scoreboard1.delta_y0 = 0;
625 vfe_state_ex->scoreboard1.delta_x1 = 0;
626 vfe_state_ex->scoreboard1.delta_y1 = -1;
627 vfe_state_ex->scoreboard1.delta_x2 = 1;
628 vfe_state_ex->scoreboard1.delta_y2 = -1;
629 vfe_state_ex->scoreboard1.delta_x3 = -1;
630 vfe_state_ex->scoreboard1.delta_y3 = -1;
632 vfe_state_ex->scoreboard2.delta_x4 = -1;
633 vfe_state_ex->scoreboard2.delta_y4 = 1;
634 vfe_state_ex->scoreboard2.delta_x5 = 0;
635 vfe_state_ex->scoreboard2.delta_y5 = -2;
636 vfe_state_ex->scoreboard2.delta_x6 = 1;
637 vfe_state_ex->scoreboard2.delta_y6 = -2;
638 vfe_state_ex->scoreboard2.delta_x7 = -1;
639 vfe_state_ex->scoreboard2.delta_y7 = -2;
642 dri_bo_unmap(media_context->extended_state.bo);
646 i965_media_h264_upload_constants(VADriverContextP ctx,
647 struct decode_state *decode_state,
648 struct i965_media_context *media_context)
650 struct i965_h264_context *i965_h264_context;
651 unsigned char *constant_buffer;
652 VASliceParameterBufferH264 *slice_param;
654 assert(media_context->private_context);
655 i965_h264_context = (struct i965_h264_context *)media_context->private_context;
657 assert(decode_state->slice_params[0] && decode_state->slice_params[0]->buffer);
658 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[0]->buffer;
660 dri_bo_map(media_context->curbe.bo, 1);
661 assert(media_context->curbe.bo->virtual);
662 constant_buffer = media_context->curbe.bo->virtual;
664 /* HW solution for W=128 */
665 if (i965_h264_context->use_hw_w128) {
666 memcpy(constant_buffer, intra_kernel_header, sizeof(*intra_kernel_header));
668 if (slice_param->slice_type == SLICE_TYPE_I ||
669 slice_param->slice_type == SLICE_TYPE_SI) {
670 memcpy(constant_buffer, intra_kernel_header, sizeof(*intra_kernel_header));
672 /* FIXME: Need to upload CURBE data to inter kernel interface
673 * to support weighted prediction work-around
675 *(short *)constant_buffer = i965_h264_context->weight128_offset0;
676 constant_buffer += 2;
677 *(char *)constant_buffer = i965_h264_context->weight128_offset0_flag;
679 *constant_buffer = 0;
683 dri_bo_unmap(media_context->curbe.bo);
687 i965_media_h264_states_setup(VADriverContextP ctx,
688 struct decode_state *decode_state,
689 struct i965_media_context *media_context)
691 struct i965_h264_context *i965_h264_context;
693 assert(media_context->private_context);
694 i965_h264_context = (struct i965_h264_context *)media_context->private_context;
696 i965_avc_bsd_pipeline(ctx, decode_state, i965_h264_context);
698 if (i965_h264_context->use_avc_hw_scoreboard)
699 i965_avc_hw_scoreboard(ctx, decode_state, i965_h264_context);
701 i965_media_h264_surfaces_setup(ctx, decode_state, media_context);
702 i965_media_h264_binding_table(ctx, media_context);
703 i965_media_h264_interface_descriptor_remap_table(ctx, media_context);
704 i965_media_h264_vfe_state_extension(ctx, decode_state, media_context);
705 i965_media_h264_vfe_state(ctx, media_context);
706 i965_media_h264_upload_constants(ctx, decode_state, media_context);
710 i965_media_h264_objects(VADriverContextP ctx,
711 struct decode_state *decode_state,
712 struct i965_media_context *media_context)
714 struct intel_batchbuffer *batch = media_context->base.batch;
715 struct i965_h264_context *i965_h264_context;
716 unsigned int *object_command;
718 assert(media_context->private_context);
719 i965_h264_context = (struct i965_h264_context *)media_context->private_context;
721 dri_bo_map(i965_h264_context->avc_it_command_mb_info.bo, True);
722 assert(i965_h264_context->avc_it_command_mb_info.bo->virtual);
723 object_command = i965_h264_context->avc_it_command_mb_info.bo->virtual;
724 memset(object_command, 0, i965_h264_context->avc_it_command_mb_info.mbs * i965_h264_context->use_avc_hw_scoreboard * MB_CMD_IN_BYTES);
725 object_command += i965_h264_context->avc_it_command_mb_info.mbs * (1 + i965_h264_context->use_avc_hw_scoreboard) * MB_CMD_IN_DWS;
726 *object_command++ = 0;
727 *object_command = MI_BATCH_BUFFER_END;
728 dri_bo_unmap(i965_h264_context->avc_it_command_mb_info.bo);
730 BEGIN_BATCH(batch, 2);
731 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
732 OUT_RELOC(batch, i965_h264_context->avc_it_command_mb_info.bo,
733 I915_GEM_DOMAIN_COMMAND, 0,
735 ADVANCE_BATCH(batch);
737 /* Have to execute the batch buffer here becuase MI_BATCH_BUFFER_END
738 * will cause control to pass back to ring buffer
740 intel_batchbuffer_end_atomic(batch);
741 intel_batchbuffer_flush(batch);
742 intel_batchbuffer_start_atomic(batch, 0x1000);
743 i965_avc_ildb(ctx, decode_state, i965_h264_context);
747 i965_media_h264_free_private_context(void **data)
749 struct i965_h264_context *i965_h264_context = *data;
752 if (i965_h264_context == NULL)
755 i965_avc_ildb_ternimate(&i965_h264_context->avc_ildb_context);
756 i965_avc_hw_scoreboard_ternimate(&i965_h264_context->avc_hw_scoreboard_context);
757 i965_avc_bsd_ternimate(&i965_h264_context->i965_avc_bsd_context);
758 dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo);
759 dri_bo_unreference(i965_h264_context->avc_it_data.bo);
760 dri_bo_unreference(i965_h264_context->avc_ildb_data.bo);
762 for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
763 struct i965_kernel *kernel = &i965_h264_context->avc_kernels[i];
765 dri_bo_unreference(kernel->bo);
769 free(i965_h264_context);
774 i965_media_h264_decode_init(VADriverContextP ctx,
775 struct decode_state *decode_state,
776 struct i965_media_context *media_context)
778 struct i965_driver_data *i965 = i965_driver_data(ctx);
779 struct i965_h264_context *i965_h264_context = media_context->private_context;
781 VAPictureParameterBufferH264 *pic_param;
783 assert(decode_state->pic_param && decode_state->pic_param->buffer);
784 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
785 i965_h264_context->picture.width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
786 i965_h264_context->picture.height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff) /
787 (1 + !!pic_param->pic_fields.bits.field_pic_flag); /* picture height */
788 i965_h264_context->picture.mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
789 !pic_param->pic_fields.bits.field_pic_flag);
790 i965_h264_context->avc_it_command_mb_info.mbs = (i965_h264_context->picture.width_in_mbs *
791 i965_h264_context->picture.height_in_mbs);
793 dri_bo_unreference(i965_h264_context->avc_it_command_mb_info.bo);
794 bo = dri_bo_alloc(i965->intel.bufmgr,
795 "avc it command mb info",
796 i965_h264_context->avc_it_command_mb_info.mbs * MB_CMD_IN_BYTES * (1 + i965_h264_context->use_avc_hw_scoreboard) + 8,
799 i965_h264_context->avc_it_command_mb_info.bo = bo;
801 dri_bo_unreference(i965_h264_context->avc_it_data.bo);
802 bo = dri_bo_alloc(i965->intel.bufmgr,
804 i965_h264_context->avc_it_command_mb_info.mbs *
806 (1 + !!pic_param->pic_fields.bits.field_pic_flag),
809 i965_h264_context->avc_it_data.bo = bo;
810 i965_h264_context->avc_it_data.write_offset = 0;
811 dri_bo_unreference(media_context->indirect_object.bo);
812 media_context->indirect_object.bo = bo;
813 dri_bo_reference(media_context->indirect_object.bo);
814 media_context->indirect_object.offset = i965_h264_context->avc_it_data.write_offset;
816 dri_bo_unreference(i965_h264_context->avc_ildb_data.bo);
817 bo = dri_bo_alloc(i965->intel.bufmgr,
818 "AVC-ILDB Data Buffer",
819 i965_h264_context->avc_it_command_mb_info.mbs * 64 * 2,
822 i965_h264_context->avc_ildb_data.bo = bo;
825 i965_avc_bsd_decode_init(ctx, i965_h264_context);
828 if (i965_h264_context->use_avc_hw_scoreboard)
829 i965_avc_hw_scoreboard_decode_init(ctx, i965_h264_context);
832 i965_avc_ildb_decode_init(ctx, i965_h264_context);
834 /* for Media pipeline */
835 media_context->extended_state.enabled = 1;
836 dri_bo_unreference(media_context->extended_state.bo);
837 bo = dri_bo_alloc(i965->intel.bufmgr,
839 sizeof(struct i965_vfe_state_ex), 32);
841 media_context->extended_state.bo = bo;
845 i965_media_h264_dec_context_init(VADriverContextP ctx, struct i965_media_context *media_context)
847 struct i965_driver_data *i965 = i965_driver_data(ctx);
848 struct i965_h264_context *i965_h264_context;
851 i965_h264_context = calloc(1, sizeof(struct i965_h264_context));
854 assert(NUM_H264_AVC_KERNELS == (sizeof(h264_avc_kernels_gen5) /
855 sizeof(h264_avc_kernels_gen5[0])));
856 assert(NUM_AVC_MC_INTERFACES == (sizeof(avc_mc_kernel_offset_gen5) /
857 sizeof(avc_mc_kernel_offset_gen5[0])));
858 if (IS_IRONLAKE(i965->intel.device_id)) {
859 memcpy(i965_h264_context->avc_kernels, h264_avc_kernels_gen5, sizeof(i965_h264_context->avc_kernels));
860 avc_mc_kernel_offset = avc_mc_kernel_offset_gen5;
861 intra_kernel_header = &intra_kernel_header_gen5;
862 i965_h264_context->use_avc_hw_scoreboard = 1;
863 i965_h264_context->use_hw_w128 = 1;
865 memcpy(i965_h264_context->avc_kernels, h264_avc_kernels_gen4, sizeof(i965_h264_context->avc_kernels));
866 avc_mc_kernel_offset = avc_mc_kernel_offset_gen4;
867 intra_kernel_header = &intra_kernel_header_gen4;
868 i965_h264_context->use_avc_hw_scoreboard = 0;
869 i965_h264_context->use_hw_w128 = 0;
872 for (i = 0; i < NUM_H264_AVC_KERNELS; i++) {
873 struct i965_kernel *kernel = &i965_h264_context->avc_kernels[i];
874 kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
876 kernel->size, 0x1000);
878 dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
881 for (i = 0; i < 16; i++) {
882 i965_h264_context->fsid_list[i].surface_id = VA_INVALID_ID;
883 i965_h264_context->fsid_list[i].frame_store_id = -1;
886 i965_h264_context->batch = media_context->base.batch;
888 media_context->private_context = i965_h264_context;
889 media_context->free_private_context = i965_media_h264_free_private_context;
892 if (IS_IRONLAKE(i965->intel.device_id)) {
893 media_context->urb.num_vfe_entries = 63;
895 media_context->urb.num_vfe_entries = 23;
898 media_context->urb.size_vfe_entry = 16;
900 media_context->urb.num_cs_entries = 1;
901 media_context->urb.size_cs_entry = 1;
903 media_context->urb.vfe_start = 0;
904 media_context->urb.cs_start = media_context->urb.vfe_start +
905 media_context->urb.num_vfe_entries * media_context->urb.size_vfe_entry;
906 assert(media_context->urb.cs_start +
907 media_context->urb.num_cs_entries * media_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
910 media_context->media_states_setup = i965_media_h264_states_setup;
911 media_context->media_objects = i965_media_h264_objects;