src/i965_gpe_utils.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Xiang Haihao <haihao.xiang@intel.com>
  25  */
  26
  27 #ifndef _I965_GPE_UTILS_H_
  28 #define _I965_GPE_UTILS_H_
  29
  30 #include <i915_drm.h>
  31 #include <intel_bufmgr.h>
  32
  33 #include "i965_defines.h"
  34 #include "i965_drv_video.h"
  35 #include "i965_structs.h"
  36
  37 #define MAX_GPE_KERNELS    32
  38
  39 struct i965_buffer_surface
  40 {
  41     dri_bo *bo;
  42     unsigned int num_blocks;
  43     unsigned int size_block;
  44     unsigned int pitch;
  45 };
  46
  47 struct i965_gpe_context
  48 {
  49     struct {
  50         dri_bo *bo;
  51         unsigned int length;            /* in bytes */
  52     } surface_state_binding_table;
  53
  54     struct {
  55         dri_bo *bo;
  56         unsigned int max_entries;
  57         unsigned int entry_size;        /* in bytes */
  58     } idrt;
  59
  60     struct {
  61         dri_bo *bo;
  62         unsigned int length;            /* in bytes */
  63     } curbe;
  64
  65     struct {
  66         unsigned int gpgpu_mode : 1;
  67         unsigned int pad0 : 7;
  68         unsigned int max_num_threads : 16;
  69         unsigned int num_urb_entries : 8;
  70         unsigned int urb_entry_size : 16;
  71         unsigned int curbe_allocation_size : 16;
  72     } vfe_state;
  73
  74     /* vfe_desc5/6/7 is used to determine whether the HW scoreboard is used.
  75      * If scoreboard is not used, don't touch them
  76      */
  77     union {
  78         unsigned int dword;
  79         struct {
  80                 unsigned int mask:8;
  81                 unsigned int pad:22;
  82                 unsigned int type:1;
  83                 unsigned int enable:1;
  84         } scoreboard0;
  85     }vfe_desc5;
  86
  87     union {
  88         unsigned int dword;
  89         struct {
  90                 int delta_x0:4;
  91                 int delta_y0:4;
  92                 int delta_x1:4;
  93                 int delta_y1:4;
  94                 int delta_x2:4;
  95                 int delta_y2:4;
  96                 int delta_x3:4;
  97                 int delta_y3:4;
  98         } scoreboard1;
  99      } vfe_desc6;
 100
 101     union {
 102         unsigned int dword;
 103         struct {
 104                 int delta_x4:4;
 105                 int delta_y4:4;
 106                 int delta_x5:4;
 107                 int delta_y5:4;
 108                 int delta_x6:4;
 109                 int delta_y6:4;
 110                 int delta_x7:4;
 111                 int delta_y7:4;
 112         } scoreboard2;
 113      } vfe_desc7;
 114
 115     unsigned int num_kernels;
 116     struct i965_kernel kernels[MAX_GPE_KERNELS];
 117
 118     struct {
 119         dri_bo *bo;
 120         int bo_size;
 121         unsigned int end_offset;
 122     } instruction_state;
 123
 124     struct {
 125         dri_bo *bo;
 126     } indirect_state;
 127
 128     struct {
 129         dri_bo *bo;
 130         int bo_size;
 131         unsigned int end_offset;
 132     } dynamic_state;
 133
 134     unsigned int sampler_offset;
 135     int sampler_size;
 136     unsigned int idrt_offset;
 137     int idrt_size;
 138     unsigned int curbe_offset;
 139     int curbe_size;
 140 };
 141
 142 void i965_gpe_context_destroy(struct i965_gpe_context *gpe_context);
 143 void i965_gpe_context_init(VADriverContextP ctx,
 144                            struct i965_gpe_context *gpe_context);
 145 void i965_gpe_load_kernels(VADriverContextP ctx,
 146                            struct i965_gpe_context *gpe_context,
 147                            struct i965_kernel *kernel_list,
 148                            unsigned int num_kernels);
 149 void gen6_gpe_pipeline_setup(VADriverContextP ctx,
 150                              struct i965_gpe_context *gpe_context,
 151                              struct intel_batchbuffer *batch);
 152 void i965_gpe_surface2_setup(VADriverContextP ctx,
 153                              struct i965_gpe_context *gpe_context,
 154                              struct object_surface *obj_surface,
 155                              unsigned long binding_table_offset,
 156                              unsigned long surface_state_offset);
 157 void i965_gpe_media_rw_surface_setup(VADriverContextP ctx,
 158                                      struct i965_gpe_context *gpe_context,
 159                                      struct object_surface *obj_surface,
 160                                      unsigned long binding_table_offset,
 161                                      unsigned long surface_state_offset);
 162 void i965_gpe_buffer_suface_setup(VADriverContextP ctx,
 163                                   struct i965_gpe_context *gpe_context,
 164                                   struct i965_buffer_surface *buffer_surface,
 165                                   unsigned long binding_table_offset,
 166                                   unsigned long surface_state_offset);
 167 void gen7_gpe_surface2_setup(VADriverContextP ctx,
 168                              struct i965_gpe_context *gpe_context,
 169                              struct object_surface *obj_surface,
 170                              unsigned long binding_table_offset,
 171                              unsigned long surface_state_offset);
 172 void gen7_gpe_media_rw_surface_setup(VADriverContextP ctx,
 173                                      struct i965_gpe_context *gpe_context,
 174                                      struct object_surface *obj_surface,
 175                                      unsigned long binding_table_offset,
 176                                      unsigned long surface_state_offset);
 177 void gen7_gpe_buffer_suface_setup(VADriverContextP ctx,
 178                                   struct i965_gpe_context *gpe_context,
 179                                   struct i965_buffer_surface *buffer_surface,
 180                                   unsigned long binding_table_offset,
 181                                   unsigned long surface_state_offset);
 182 void gen75_gpe_media_chroma_surface_setup(VADriverContextP ctx,
 183                                      struct i965_gpe_context *gpe_context,
 184                                      struct object_surface *obj_surface,
 185                                      unsigned long binding_table_offset,
 186                                      unsigned long surface_state_offset);
 187
 188 extern void gen8_gpe_surface2_setup(VADriverContextP ctx,
 189                              struct i965_gpe_context *gpe_context,
 190                              struct object_surface *obj_surface,
 191                              unsigned long binding_table_offset,
 192                              unsigned long surface_state_offset);
 193 extern void gen8_gpe_media_rw_surface_setup(VADriverContextP ctx,
 194                                      struct i965_gpe_context *gpe_context,
 195                                      struct object_surface *obj_surface,
 196                                      unsigned long binding_table_offset,
 197                                      unsigned long surface_state_offset);
 198 extern void gen8_gpe_buffer_suface_setup(VADriverContextP ctx,
 199                                   struct i965_gpe_context *gpe_context,
 200                                   struct i965_buffer_surface *buffer_surface,
 201                                   unsigned long binding_table_offset,
 202                                   unsigned long surface_state_offset);
 203 extern void gen8_gpe_media_chroma_surface_setup(VADriverContextP ctx,
 204                                      struct i965_gpe_context *gpe_context,
 205                                      struct object_surface *obj_surface,
 206                                      unsigned long binding_table_offset,
 207                                      unsigned long surface_state_offset);
 208
 209 void gen8_gpe_pipeline_setup(VADriverContextP ctx,
 210                              struct i965_gpe_context *gpe_context,
 211                              struct intel_batchbuffer *batch);
 212
 213
 214 void gen8_gpe_context_destroy(struct i965_gpe_context *gpe_context);
 215 void gen8_gpe_context_init(VADriverContextP ctx,
 216                            struct i965_gpe_context *gpe_context);
 217
 218 void gen8_gpe_load_kernels(VADriverContextP ctx,
 219                            struct i965_gpe_context *gpe_context,
 220                            struct i965_kernel *kernel_list,
 221                            unsigned int num_kernels);
 222 #endif /* _I965_GPE_UTILS_H_ */