src/i965_drv_video.h

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zou Nan hai <nanhai.zou@intel.com>
  27  *
  28  */
  29
  30 #ifndef _I965_DRV_VIDEO_H_
  31 #define _I965_DRV_VIDEO_H_
  32
  33 #include <va/va.h>
  34 #include <va/va_enc_h264.h>
  35 #include <va/va_enc_mpeg2.h>
  36 #include <va/va_vpp.h>
  37 #include <va/va_backend.h>
  38 #include <va/va_backend_vpp.h>
  39
  40 #include "i965_mutext.h"
  41 #include "object_heap.h"
  42 #include "intel_driver.h"
  43
  44 #define I965_MAX_PROFILES                       11
  45 #define I965_MAX_ENTRYPOINTS                    5
  46 #define I965_MAX_CONFIG_ATTRIBUTES              10
  47 #define I965_MAX_IMAGE_FORMATS                  10
  48 #define I965_MAX_SUBPIC_FORMATS                 6
  49 #define I965_MAX_SUBPIC_SUM                     4
  50
  51 #define INTEL_STR_DRIVER_VENDOR                 "Intel"
  52 #define INTEL_STR_DRIVER_NAME                   "i965"
  53
  54 #define I965_SURFACE_TYPE_IMAGE                 0
  55 #define I965_SURFACE_TYPE_SURFACE               1
  56
  57 #define I965_SURFACE_FLAG_FRAME                 0x00000000
  58 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST       0x00000001
  59 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST   0x00000002
  60
  61 struct i965_surface
  62 {
  63     struct object_base *base;
  64     int type;
  65     int flags;
  66 };
  67
  68 struct i965_kernel
  69 {
  70     char *name;
  71     int interface;
  72     const uint32_t (*bin)[4];
  73     int size;
  74     dri_bo *bo;
  75 };
  76
  77 struct buffer_store
  78 {
  79     unsigned char *buffer;
  80     dri_bo *bo;
  81     int ref_count;
  82     int num_elements;
  83 };
  84
  85 struct object_config
  86 {
  87     struct object_base base;
  88     VAProfile profile;
  89     VAEntrypoint entrypoint;
  90     VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
  91     int num_attribs;
  92 };
  93
  94 #define NUM_SLICES     10
  95
  96 struct decode_state
  97 {
  98     struct buffer_store *pic_param;
  99     struct buffer_store **slice_params;
 100     struct buffer_store *iq_matrix;
 101     struct buffer_store *bit_plane;
 102     struct buffer_store *huffman_table;
 103     struct buffer_store **slice_datas;
 104     VASurfaceID current_render_target;
 105     int max_slice_params;
 106     int max_slice_datas;
 107     int num_slice_params;
 108     int num_slice_datas;
 109
 110     struct object_surface *render_object;
 111     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 112 };
 113
 114 struct encode_state
 115 {
 116     struct buffer_store *seq_param;
 117     struct buffer_store *pic_param;
 118     struct buffer_store *pic_control;
 119     struct buffer_store *iq_matrix;
 120     struct buffer_store *q_matrix;
 121     struct buffer_store **slice_params;
 122     int max_slice_params;
 123     int num_slice_params;
 124
 125     /* for ext */
 126     struct buffer_store *seq_param_ext;
 127     struct buffer_store *pic_param_ext;
 128     struct buffer_store *packed_header_param[4];
 129     struct buffer_store *packed_header_data[4];
 130     struct buffer_store **slice_params_ext;
 131     int max_slice_params_ext;
 132     int num_slice_params_ext;
 133     int last_packed_header_type;
 134
 135     struct buffer_store *misc_param[8];
 136
 137     VASurfaceID current_render_target;
 138     struct object_surface *input_yuv_object;
 139     struct object_surface *reconstructed_object;
 140     struct object_buffer *coded_buf_object;
 141     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 142 };
 143
 144 struct proc_state
 145 {
 146     struct buffer_store *pipeline_param;
 147
 148     VASurfaceID current_render_target;
 149 };
 150
 151 #define CODEC_DEC       0
 152 #define CODEC_ENC       1
 153 #define CODEC_PROC      2
 154
 155 union codec_state
 156 {
 157     struct decode_state decode;
 158     struct encode_state encode;
 159     struct proc_state proc;
 160 };
 161
 162 struct hw_context
 163 {
 164     VAStatus (*run)(VADriverContextP ctx,
 165                     VAProfile profile,
 166                     union codec_state *codec_state,
 167                     struct hw_context *hw_context);
 168     void (*destroy)(void *);
 169     struct intel_batchbuffer *batch;
 170 };
 171
 172 struct object_context
 173 {
 174     struct object_base base;
 175     VAContextID context_id;
 176     struct object_config *obj_config;
 177     VASurfaceID *render_targets;                //input->encode, output->decode
 178     int num_render_targets;
 179     int picture_width;
 180     int picture_height;
 181     int flags;
 182     int codec_type;
 183     union codec_state codec_state;
 184     struct hw_context *hw_context;
 185 };
 186
 187 #define SURFACE_REFERENCED      (1 << 0)
 188 #define SURFACE_DISPLAYED       (1 << 1)
 189 #define SURFACE_DERIVED         (1 << 2)
 190 #define SURFACE_REF_DIS_MASK    ((SURFACE_REFERENCED) | \
 191                                  (SURFACE_DISPLAYED))
 192 #define SURFACE_ALL_MASK        ((SURFACE_REFERENCED) | \
 193                                  (SURFACE_DISPLAYED) |  \
 194                                  (SURFACE_DERIVED))
 195
 196 struct object_surface
 197 {
 198     struct object_base base;
 199     VASurfaceStatus status;
 200     VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
 201     struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
 202     unsigned int subpic_render_idx;
 203
 204     int width;
 205     int height;
 206     int size;
 207     int orig_width;
 208     int orig_height;
 209     int flags;
 210     unsigned int fourcc;
 211     dri_bo *bo;
 212     VAImageID locked_image_id;
 213     void (*free_private_data)(void **data);
 214     void *private_data;
 215     unsigned int subsampling;
 216     int x_cb_offset;
 217     int y_cb_offset;
 218     int x_cr_offset;
 219     int y_cr_offset;
 220     int cb_cr_width;
 221     int cb_cr_height;
 222     int cb_cr_pitch;
 223 };
 224
 225 struct object_buffer
 226 {
 227     struct object_base base;
 228     struct buffer_store *buffer_store;
 229     int max_num_elements;
 230     int num_elements;
 231     int size_element;
 232     VABufferType type;
 233 };
 234
 235 struct object_image
 236 {
 237     struct object_base base;
 238     VAImage image;
 239     dri_bo *bo;
 240     unsigned int *palette;
 241     VASurfaceID derived_surface;
 242 };
 243
 244 struct object_subpic
 245 {
 246     struct object_base base;
 247     VAImageID image;
 248     struct object_image *obj_image;
 249     VARectangle src_rect;
 250     VARectangle dst_rect;
 251     unsigned int format;
 252     int width;
 253     int height;
 254     int pitch;
 255     float global_alpha;
 256     dri_bo *bo;
 257     unsigned int flags;
 258 };
 259
 260 struct hw_codec_info
 261 {
 262     struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
 263     struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
 264     struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
 265     int max_width;
 266     int max_height;
 267
 268     unsigned int has_mpeg2_decoding:1;
 269     unsigned int has_mpeg2_encoding:1;
 270     unsigned int has_h264_decoding:1;
 271     unsigned int has_h264_encoding:1;
 272     unsigned int has_vc1_decoding:1;
 273     unsigned int has_vc1_encoding:1;
 274     unsigned int has_jpeg_decoding:1;
 275     unsigned int has_jpeg_encoding:1;
 276     unsigned int has_vpp:1;
 277     unsigned int has_accelerated_getimage:1;
 278     unsigned int has_accelerated_putimage:1;
 279     unsigned int has_tiled_surface:1;
 280 };
 281
 282
 283 #include "i965_render.h"
 284
 285 struct i965_driver_data
 286 {
 287     struct intel_driver_data intel;
 288     struct object_heap config_heap;
 289     struct object_heap context_heap;
 290     struct object_heap surface_heap;
 291     struct object_heap buffer_heap;
 292     struct object_heap image_heap;
 293     struct object_heap subpic_heap;
 294     struct hw_codec_info *codec_info;
 295
 296     _I965Mutex render_mutex;
 297     _I965Mutex pp_mutex;
 298     struct intel_batchbuffer *batch;
 299     struct i965_render_state render_state;
 300     void *pp_context;
 301     char va_vendor[256];
 302
 303     VADisplayAttribute *display_attributes;
 304     unsigned int num_display_attributes;
 305     VADisplayAttribute *rotation_attrib;
 306
 307     VAContextID current_context_id;
 308
 309     /* VA/DRI (X11) specific data */
 310     struct va_dri_output *dri_output;
 311
 312     /* VA/Wayland specific data */
 313     struct va_wl_output *wl_output;
 314 };
 315
 316 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
 317 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
 318 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
 319 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
 320 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
 321 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
 322
 323 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
 324 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
 325 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
 326 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
 327 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
 328 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
 329
 330 #define FOURCC_IA44 0x34344149
 331 #define FOURCC_AI44 0x34344941
 332
 333 #define STRIDE(w)               (((w) + 0xf) & ~0xf)
 334 #define SIZE_YUV420(w, h)       (h * (STRIDE(w) + STRIDE(w >> 1)))
 335
 336 static INLINE struct i965_driver_data *
 337 i965_driver_data(VADriverContextP ctx)
 338 {
 339     return (struct i965_driver_data *)(ctx->pDriverData);
 340 }
 341
 342 void
 343 i965_check_alloc_surface_bo(VADriverContextP ctx,
 344                             struct object_surface *obj_surface,
 345                             int tiled,
 346                             unsigned int fourcc,
 347                             unsigned int subsampling);
 348
 349 int
 350 va_enc_packed_type_to_idx(int packed_type);
 351
 352 /* reserve 2 byte for internal using */
 353 #define CODED_H264      0
 354 #define CODED_MPEG2     1
 355
 356 #define H264_DELIMITER0 0x00
 357 #define H264_DELIMITER1 0x00
 358 #define H264_DELIMITER2 0x00
 359 #define H264_DELIMITER3 0x00
 360 #define H264_DELIMITER4 0x00
 361
 362 #define MPEG2_DELIMITER0        0x00
 363 #define MPEG2_DELIMITER1        0x00
 364 #define MPEG2_DELIMITER2        0x00
 365 #define MPEG2_DELIMITER3        0x00
 366 #define MPEG2_DELIMITER4        0xb0
 367
 368 struct i965_coded_buffer_segment
 369 {
 370     VACodedBufferSegment base;
 371     unsigned char mapped;
 372     unsigned char codec;
 373 };
 374
 375 #define I965_CODEDBUFFER_HEADER_SIZE   ALIGN(sizeof(struct i965_coded_buffer_segment), 64)
 376
 377
 378 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
 379                 VABufferID buf_id,       /* in */
 380                 void **pbuf);            /* out */
 381
 382 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
 383
 384 #endif /* _I965_DRV_VIDEO_H_ */