src/i965_drv_video.h

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zou Nan hai <nanhai.zou@intel.com>
  27  *
  28  */
  29
  30 #ifndef _I965_DRV_VIDEO_H_
  31 #define _I965_DRV_VIDEO_H_
  32
  33 #include <va/va.h>
  34 #include <va/va_enc_h264.h>
  35 #include <va/va_enc_mpeg2.h>
  36 #include <va/va_vpp.h>
  37 #include <va/va_backend.h>
  38 #include <va/va_backend_vpp.h>
  39
  40 #include "i965_mutext.h"
  41 #include "object_heap.h"
  42 #include "intel_driver.h"
  43
  44 #define I965_MAX_PROFILES                       11
  45 #define I965_MAX_ENTRYPOINTS                    5
  46 #define I965_MAX_CONFIG_ATTRIBUTES              10
  47 #define I965_MAX_IMAGE_FORMATS                  10
  48 #define I965_MAX_SUBPIC_FORMATS                 6
  49 #define I965_MAX_SUBPIC_SUM                     4
  50 #define I965_MAX_SURFACE_ATTRIBUTES             16
  51
  52 #define INTEL_STR_DRIVER_VENDOR                 "Intel"
  53 #define INTEL_STR_DRIVER_NAME                   "i965"
  54
  55 #define I965_SURFACE_TYPE_IMAGE                 0
  56 #define I965_SURFACE_TYPE_SURFACE               1
  57
  58 #define I965_SURFACE_FLAG_FRAME                 0x00000000
  59 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST       0x00000001
  60 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST   0x00000002
  61
  62 struct i965_surface
  63 {
  64     struct object_base *base;
  65     int type;
  66     int flags;
  67 };
  68
  69 struct i965_kernel
  70 {
  71     char *name;
  72     int interface;
  73     const uint32_t (*bin)[4];
  74     int size;
  75     dri_bo *bo;
  76 };
  77
  78 struct buffer_store
  79 {
  80     unsigned char *buffer;
  81     dri_bo *bo;
  82     int ref_count;
  83     int num_elements;
  84 };
  85
  86 struct object_config
  87 {
  88     struct object_base base;
  89     VAProfile profile;
  90     VAEntrypoint entrypoint;
  91     VAConfigAttrib attrib_list[I965_MAX_CONFIG_ATTRIBUTES];
  92     int num_attribs;
  93 };
  94
  95 #define NUM_SLICES     10
  96
  97 struct decode_state
  98 {
  99     struct buffer_store *pic_param;
 100     struct buffer_store **slice_params;
 101     struct buffer_store *iq_matrix;
 102     struct buffer_store *bit_plane;
 103     struct buffer_store *huffman_table;
 104     struct buffer_store **slice_datas;
 105     VASurfaceID current_render_target;
 106     int max_slice_params;
 107     int max_slice_datas;
 108     int num_slice_params;
 109     int num_slice_datas;
 110
 111     struct object_surface *render_object;
 112     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 113 };
 114
 115 struct encode_state
 116 {
 117     struct buffer_store *seq_param;
 118     struct buffer_store *pic_param;
 119     struct buffer_store *pic_control;
 120     struct buffer_store *iq_matrix;
 121     struct buffer_store *q_matrix;
 122     struct buffer_store **slice_params;
 123     int max_slice_params;
 124     int num_slice_params;
 125
 126     /* for ext */
 127     struct buffer_store *seq_param_ext;
 128     struct buffer_store *pic_param_ext;
 129     struct buffer_store *packed_header_param[4];
 130     struct buffer_store *packed_header_data[4];
 131     struct buffer_store **slice_params_ext;
 132     int max_slice_params_ext;
 133     int num_slice_params_ext;
 134     int last_packed_header_type;
 135
 136     struct buffer_store *misc_param[8];
 137
 138     VASurfaceID current_render_target;
 139     struct object_surface *input_yuv_object;
 140     struct object_surface *reconstructed_object;
 141     struct object_buffer *coded_buf_object;
 142     struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
 143 };
 144
 145 struct proc_state
 146 {
 147     struct buffer_store *pipeline_param;
 148
 149     VASurfaceID current_render_target;
 150 };
 151
 152 #define CODEC_DEC       0
 153 #define CODEC_ENC       1
 154 #define CODEC_PROC      2
 155
 156 union codec_state
 157 {
 158     struct decode_state decode;
 159     struct encode_state encode;
 160     struct proc_state proc;
 161 };
 162
 163 struct hw_context
 164 {
 165     VAStatus (*run)(VADriverContextP ctx,
 166                     VAProfile profile,
 167                     union codec_state *codec_state,
 168                     struct hw_context *hw_context);
 169     void (*destroy)(void *);
 170     struct intel_batchbuffer *batch;
 171 };
 172
 173 struct object_context
 174 {
 175     struct object_base base;
 176     VAContextID context_id;
 177     struct object_config *obj_config;
 178     VASurfaceID *render_targets;                //input->encode, output->decode
 179     int num_render_targets;
 180     int picture_width;
 181     int picture_height;
 182     int flags;
 183     int codec_type;
 184     union codec_state codec_state;
 185     struct hw_context *hw_context;
 186 };
 187
 188 #define SURFACE_REFERENCED      (1 << 0)
 189 #define SURFACE_DISPLAYED       (1 << 1)
 190 #define SURFACE_DERIVED         (1 << 2)
 191 #define SURFACE_REF_DIS_MASK    ((SURFACE_REFERENCED) | \
 192                                  (SURFACE_DISPLAYED))
 193 #define SURFACE_ALL_MASK        ((SURFACE_REFERENCED) | \
 194                                  (SURFACE_DISPLAYED) |  \
 195                                  (SURFACE_DERIVED))
 196
 197 struct object_surface
 198 {
 199     struct object_base base;
 200     VASurfaceStatus status;
 201     VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
 202     struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
 203     unsigned int subpic_render_idx;
 204
 205     int width;
 206     int height;
 207     int size;
 208     int orig_width;
 209     int orig_height;
 210     int flags;
 211     unsigned int fourcc;
 212     dri_bo *bo;
 213     VAImageID locked_image_id;
 214     void (*free_private_data)(void **data);
 215     void *private_data;
 216     unsigned int subsampling;
 217     int x_cb_offset;
 218     int y_cb_offset;
 219     int x_cr_offset;
 220     int y_cr_offset;
 221     int cb_cr_width;
 222     int cb_cr_height;
 223     int cb_cr_pitch;
 224 };
 225
 226 struct object_buffer
 227 {
 228     struct object_base base;
 229     struct buffer_store *buffer_store;
 230     int max_num_elements;
 231     int num_elements;
 232     int size_element;
 233     VABufferType type;
 234 };
 235
 236 struct object_image
 237 {
 238     struct object_base base;
 239     VAImage image;
 240     dri_bo *bo;
 241     unsigned int *palette;
 242     VASurfaceID derived_surface;
 243 };
 244
 245 struct object_subpic
 246 {
 247     struct object_base base;
 248     VAImageID image;
 249     struct object_image *obj_image;
 250     VARectangle src_rect;
 251     VARectangle dst_rect;
 252     unsigned int format;
 253     int width;
 254     int height;
 255     int pitch;
 256     float global_alpha;
 257     dri_bo *bo;
 258     unsigned int flags;
 259 };
 260
 261 #define I965_RING_NULL  0
 262 #define I965_RING_BSD   1
 263 #define I965_RING_BLT   2
 264 #define I965_RING_VEBOX 3
 265
 266 struct i965_filter
 267 {
 268     VAProcFilterType type;
 269     int ring;
 270 };
 271
 272 struct hw_codec_info
 273 {
 274     struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
 275     struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
 276     struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
 277     int max_width;
 278     int max_height;
 279
 280     unsigned int has_mpeg2_decoding:1;
 281     unsigned int has_mpeg2_encoding:1;
 282     unsigned int has_h264_decoding:1;
 283     unsigned int has_h264_encoding:1;
 284     unsigned int has_vc1_decoding:1;
 285     unsigned int has_vc1_encoding:1;
 286     unsigned int has_jpeg_decoding:1;
 287     unsigned int has_jpeg_encoding:1;
 288     unsigned int has_vpp:1;
 289     unsigned int has_accelerated_getimage:1;
 290     unsigned int has_accelerated_putimage:1;
 291     unsigned int has_tiled_surface:1;
 292     unsigned int has_di_motion_adptive:1;
 293     unsigned int has_di_motion_compensated:1;
 294
 295     unsigned int num_filters;
 296     struct i965_filter filters[VAProcFilterCount];
 297 };
 298
 299
 300 #include "i965_render.h"
 301
 302 struct i965_driver_data
 303 {
 304     struct intel_driver_data intel;
 305     struct object_heap config_heap;
 306     struct object_heap context_heap;
 307     struct object_heap surface_heap;
 308     struct object_heap buffer_heap;
 309     struct object_heap image_heap;
 310     struct object_heap subpic_heap;
 311     struct hw_codec_info *codec_info;
 312
 313     _I965Mutex render_mutex;
 314     _I965Mutex pp_mutex;
 315     struct intel_batchbuffer *batch;
 316     struct i965_render_state render_state;
 317     void *pp_context;
 318     char va_vendor[256];
 319
 320     VADisplayAttribute *display_attributes;
 321     unsigned int num_display_attributes;
 322     VADisplayAttribute *rotation_attrib;
 323     VAContextID current_context_id;
 324
 325     /* VA/DRI (X11) specific data */
 326     struct va_dri_output *dri_output;
 327
 328     /* VA/Wayland specific data */
 329     struct va_wl_output *wl_output;
 330 };
 331
 332 #define NEW_CONFIG_ID() object_heap_allocate(&i965->config_heap);
 333 #define NEW_CONTEXT_ID() object_heap_allocate(&i965->context_heap);
 334 #define NEW_SURFACE_ID() object_heap_allocate(&i965->surface_heap);
 335 #define NEW_BUFFER_ID() object_heap_allocate(&i965->buffer_heap);
 336 #define NEW_IMAGE_ID() object_heap_allocate(&i965->image_heap);
 337 #define NEW_SUBPIC_ID() object_heap_allocate(&i965->subpic_heap);
 338
 339 #define CONFIG(id) ((struct object_config *)object_heap_lookup(&i965->config_heap, id))
 340 #define CONTEXT(id) ((struct object_context *)object_heap_lookup(&i965->context_heap, id))
 341 #define SURFACE(id) ((struct object_surface *)object_heap_lookup(&i965->surface_heap, id))
 342 #define BUFFER(id) ((struct object_buffer *)object_heap_lookup(&i965->buffer_heap, id))
 343 #define IMAGE(id) ((struct object_image *)object_heap_lookup(&i965->image_heap, id))
 344 #define SUBPIC(id) ((struct object_subpic *)object_heap_lookup(&i965->subpic_heap, id))
 345
 346 #define FOURCC_IA44 0x34344149
 347 #define FOURCC_AI44 0x34344941
 348
 349 #define STRIDE(w)               (((w) + 0xf) & ~0xf)
 350 #define SIZE_YUV420(w, h)       (h * (STRIDE(w) + STRIDE(w >> 1)))
 351
 352 static INLINE struct i965_driver_data *
 353 i965_driver_data(VADriverContextP ctx)
 354 {
 355     return (struct i965_driver_data *)(ctx->pDriverData);
 356 }
 357
 358 void
 359 i965_check_alloc_surface_bo(VADriverContextP ctx,
 360                             struct object_surface *obj_surface,
 361                             int tiled,
 362                             unsigned int fourcc,
 363                             unsigned int subsampling);
 364
 365 int
 366 va_enc_packed_type_to_idx(int packed_type);
 367
 368 /* reserve 2 byte for internal using */
 369 #define CODED_H264      0
 370 #define CODED_MPEG2     1
 371
 372 #define H264_DELIMITER0 0x00
 373 #define H264_DELIMITER1 0x00
 374 #define H264_DELIMITER2 0x00
 375 #define H264_DELIMITER3 0x00
 376 #define H264_DELIMITER4 0x00
 377
 378 #define MPEG2_DELIMITER0        0x00
 379 #define MPEG2_DELIMITER1        0x00
 380 #define MPEG2_DELIMITER2        0x00
 381 #define MPEG2_DELIMITER3        0x00
 382 #define MPEG2_DELIMITER4        0xb0
 383
 384 struct i965_coded_buffer_segment
 385 {
 386     VACodedBufferSegment base;
 387     unsigned char mapped;
 388     unsigned char codec;
 389 };
 390
 391 #define I965_CODEDBUFFER_HEADER_SIZE   ALIGN(sizeof(struct i965_coded_buffer_segment), 64)
 392
 393 extern VAStatus i965_MapBuffer(VADriverContextP ctx,
 394                 VABufferID buf_id,       /* in */
 395                 void **pbuf);            /* out */
 396
 397 extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
 398
 399 #define I965_SURFACE_MEM_NATIVE             0
 400 #define I965_SURFACE_MEM_GEM_FLINK          1
 401 #define I965_SURFACE_MEM_DRM_PRIME          2
 402
 403 #endif /* _I965_DRV_VIDEO_H_ */