src/i915_3d.h

   1 /* -*- c-basic-offset: 4 -*- */
   2 /*
   3  * Copyright © 2006,2010 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Eric Anholt <eric@anholt.net>
  26  *    Chris Wilson <chris@chris-wilson.co.uk>
  27  *
  28  */
  29
  30 /* Each instruction is 3 dwords long, though most don't require all
  31  * this space.  Maximum of 123 instructions.  Smaller maxes per insn
  32  * type.
  33  */
  34 #define _3DSTATE_PIXEL_SHADER_PROGRAM    (CMD_3D|(0x1d<<24)|(0x5<<16))
  35
  36 #define REG_TYPE_R                 0 /* temporary regs, no need to
  37                                       * dcl, must be written before
  38                                       * read -- Preserved between
  39                                       * phases.
  40                                       */
  41 #define REG_TYPE_T                 1 /* Interpolated values, must be
  42                                       * dcl'ed before use.
  43                                       *
  44                                       * 0..7: texture coord,
  45                                       * 8: diffuse spec,
  46                                       * 9: specular color,
  47                                       * 10: fog parameter in w.
  48                                       */
  49 #define REG_TYPE_CONST             2 /* Restriction: only one const
  50                                       * can be referenced per
  51                                       * instruction, though it may be
  52                                       * selected for multiple inputs.
  53                                       * Constants not initialized
  54                                       * default to zero.
  55                                       */
  56 #define REG_TYPE_S                 3 /* sampler */
  57 #define REG_TYPE_OC                4 /* output color (rgba) */
  58 #define REG_TYPE_OD                5 /* output depth (w), xyz are
  59                                       * temporaries.  If not written,
  60                                       * interpolated depth is used?
  61                                       */
  62 #define REG_TYPE_U                 6 /* unpreserved temporaries */
  63 #define REG_TYPE_MASK              0x7
  64 #define REG_TYPE_SHIFT             4
  65 #define REG_NR_MASK                0xf
  66
  67 /* REG_TYPE_T:
  68 */
  69 #define T_TEX0     0
  70 #define T_TEX1     1
  71 #define T_TEX2     2
  72 #define T_TEX3     3
  73 #define T_TEX4     4
  74 #define T_TEX5     5
  75 #define T_TEX6     6
  76 #define T_TEX7     7
  77 #define T_DIFFUSE  8
  78 #define T_SPECULAR 9
  79 #define T_FOG_W    10           /* interpolated fog is in W coord */
  80
  81 /* Arithmetic instructions */
  82
  83 /* .replicate_swizzle == selection and replication of a particular
  84  * scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww
  85  */
  86 #define A0_NOP    (0x0<<24)             /* no operation */
  87 #define A0_ADD    (0x1<<24)             /* dst = src0 + src1 */
  88 #define A0_MOV    (0x2<<24)             /* dst = src0 */
  89 #define A0_MUL    (0x3<<24)             /* dst = src0 * src1 */
  90 #define A0_MAD    (0x4<<24)             /* dst = src0 * src1 + src2 */
  91 #define A0_DP2ADD (0x5<<24)             /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */
  92 #define A0_DP3    (0x6<<24)             /* dst.xyzw = src0.xyz dot src1.xyz */
  93 #define A0_DP4    (0x7<<24)             /* dst.xyzw = src0.xyzw dot src1.xyzw */
  94 #define A0_FRC    (0x8<<24)             /* dst = src0 - floor(src0) */
  95 #define A0_RCP    (0x9<<24)             /* dst.xyzw = 1/(src0.replicate_swizzle) */
  96 #define A0_RSQ    (0xa<<24)             /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */
  97 #define A0_EXP    (0xb<<24)             /* dst.xyzw = exp2(src0.replicate_swizzle) */
  98 #define A0_LOG    (0xc<<24)             /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */
  99 #define A0_CMP    (0xd<<24)             /* dst = (src0 >= 0.0) ? src1 : src2 */
 100 #define A0_MIN    (0xe<<24)             /* dst = (src0 < src1) ? src0 : src1 */
 101 #define A0_MAX    (0xf<<24)             /* dst = (src0 >= src1) ? src0 : src1 */
 102 #define A0_FLR    (0x10<<24)            /* dst = floor(src0) */
 103 #define A0_MOD    (0x11<<24)            /* dst = src0 fmod 1.0 */
 104 #define A0_TRC    (0x12<<24)            /* dst = int(src0) */
 105 #define A0_SGE    (0x13<<24)            /* dst = src0 >= src1 ? 1.0 : 0.0 */
 106 #define A0_SLT    (0x14<<24)            /* dst = src0 < src1 ? 1.0 : 0.0 */
 107 #define A0_DEST_SATURATE                 (1<<22)
 108 #define A0_DEST_TYPE_SHIFT                19
 109 /* Allow: R, OC, OD, U */
 110 #define A0_DEST_NR_SHIFT                 14
 111 /* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */
 112 #define A0_DEST_CHANNEL_X                (1<<10)
 113 #define A0_DEST_CHANNEL_Y                (2<<10)
 114 #define A0_DEST_CHANNEL_Z                (4<<10)
 115 #define A0_DEST_CHANNEL_W                (8<<10)
 116 #define A0_DEST_CHANNEL_ALL              (0xf<<10)
 117 #define A0_DEST_CHANNEL_SHIFT            10
 118 #define A0_SRC0_TYPE_SHIFT               7
 119 #define A0_SRC0_NR_SHIFT                 2
 120
 121 #define A0_DEST_CHANNEL_XY              (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y)
 122 #define A0_DEST_CHANNEL_XYZ             (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z)
 123
 124 #define SRC_X        0
 125 #define SRC_Y        1
 126 #define SRC_Z        2
 127 #define SRC_W        3
 128 #define SRC_ZERO     4
 129 #define SRC_ONE      5
 130
 131 #define A1_SRC0_CHANNEL_X_NEGATE         (1<<31)
 132 #define A1_SRC0_CHANNEL_X_SHIFT          28
 133 #define A1_SRC0_CHANNEL_Y_NEGATE         (1<<27)
 134 #define A1_SRC0_CHANNEL_Y_SHIFT          24
 135 #define A1_SRC0_CHANNEL_Z_NEGATE         (1<<23)
 136 #define A1_SRC0_CHANNEL_Z_SHIFT          20
 137 #define A1_SRC0_CHANNEL_W_NEGATE         (1<<19)
 138 #define A1_SRC0_CHANNEL_W_SHIFT          16
 139 #define A1_SRC1_TYPE_SHIFT               13
 140 #define A1_SRC1_NR_SHIFT                 8
 141 #define A1_SRC1_CHANNEL_X_NEGATE         (1<<7)
 142 #define A1_SRC1_CHANNEL_X_SHIFT          4
 143 #define A1_SRC1_CHANNEL_Y_NEGATE         (1<<3)
 144 #define A1_SRC1_CHANNEL_Y_SHIFT          0
 145
 146 #define A2_SRC1_CHANNEL_Z_NEGATE         (1<<31)
 147 #define A2_SRC1_CHANNEL_Z_SHIFT          28
 148 #define A2_SRC1_CHANNEL_W_NEGATE         (1<<27)
 149 #define A2_SRC1_CHANNEL_W_SHIFT          24
 150 #define A2_SRC2_TYPE_SHIFT               21
 151 #define A2_SRC2_NR_SHIFT                 16
 152 #define A2_SRC2_CHANNEL_X_NEGATE         (1<<15)
 153 #define A2_SRC2_CHANNEL_X_SHIFT          12
 154 #define A2_SRC2_CHANNEL_Y_NEGATE         (1<<11)
 155 #define A2_SRC2_CHANNEL_Y_SHIFT          8
 156 #define A2_SRC2_CHANNEL_Z_NEGATE         (1<<7)
 157 #define A2_SRC2_CHANNEL_Z_SHIFT          4
 158 #define A2_SRC2_CHANNEL_W_NEGATE         (1<<3)
 159 #define A2_SRC2_CHANNEL_W_SHIFT          0
 160
 161 /* Texture instructions */
 162 #define T0_TEXLD     (0x15<<24) /* Sample texture using predeclared
 163                                  * sampler and address, and output
 164                                  * filtered texel data to destination
 165                                  * register */
 166 #define T0_TEXLDP    (0x16<<24) /* Same as texld but performs a
 167                                  * perspective divide of the texture
 168                                  * coordinate .xyz values by .w before
 169                                  * sampling. */
 170 #define T0_TEXLDB    (0x17<<24) /* Same as texld but biases the
 171                                  * computed LOD by w.  Only S4.6 two's
 172                                  * comp is used.  This implies that a
 173                                  * float to fixed conversion is
 174                                  * done. */
 175 #define T0_TEXKILL   (0x18<<24) /* Does not perform a sampling
 176                                  * operation.  Simply kills the pixel
 177                                  * if any channel of the address
 178                                  * register is < 0.0. */
 179 #define T0_DEST_TYPE_SHIFT                19
 180 /* Allow: R, OC, OD, U */
 181 /* Note: U (unpreserved) regs do not retain their values between
 182  * phases (cannot be used for feedback)
 183  *
 184  * Note: oC and OD registers can only be used as the destination of a
 185  * texture instruction once per phase (this is an implementation
 186  * restriction).
 187  */
 188 #define T0_DEST_NR_SHIFT                 14
 189 /* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */
 190 #define T0_SAMPLER_NR_SHIFT              0 /* This field ignored for TEXKILL */
 191 #define T0_SAMPLER_NR_MASK               (0xf<<0)
 192
 193 #define T1_ADDRESS_REG_TYPE_SHIFT        24 /* Reg to use as texture coord */
 194 /* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */
 195 #define T1_ADDRESS_REG_NR_SHIFT          17
 196 #define T2_MBZ                           0
 197
 198 /* Declaration instructions */
 199 #define D0_DCL       (0x19<<24) /* Declare a t (interpolated attrib)
 200                                  * register or an s (sampler)
 201                                  * register. */
 202 #define D0_SAMPLE_TYPE_SHIFT              22
 203 #define D0_SAMPLE_TYPE_2D                 (0x0<<22)
 204 #define D0_SAMPLE_TYPE_CUBE               (0x1<<22)
 205 #define D0_SAMPLE_TYPE_VOLUME             (0x2<<22)
 206 #define D0_SAMPLE_TYPE_MASK               (0x3<<22)
 207
 208 #define D0_TYPE_SHIFT                19
 209 /* Allow: T, S */
 210 #define D0_NR_SHIFT                  14
 211 /* Allow T: 0..10, S: 0..15 */
 212 #define D0_CHANNEL_X                (1<<10)
 213 #define D0_CHANNEL_Y                (2<<10)
 214 #define D0_CHANNEL_Z                (4<<10)
 215 #define D0_CHANNEL_W                (8<<10)
 216 #define D0_CHANNEL_ALL              (0xf<<10)
 217 #define D0_CHANNEL_NONE             (0<<10)
 218
 219 #define D0_CHANNEL_XY               (D0_CHANNEL_X|D0_CHANNEL_Y)
 220 #define D0_CHANNEL_XYZ              (D0_CHANNEL_XY|D0_CHANNEL_Z)
 221
 222 /* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse
 223  * or specular declarations.
 224  *
 225  * For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw)
 226  *
 227  * Must be zero for S (sampler) dcls
 228  */
 229 #define D1_MBZ                          0
 230 #define D2_MBZ                          0
 231
 232
 233 /* MASK_* are the unshifted bitmasks of the destination mask in arithmetic
 234  * operations
 235  */
 236 #define MASK_X                  0x1
 237 #define MASK_Y                  0x2
 238 #define MASK_Z                  0x4
 239 #define MASK_W                  0x8
 240 #define MASK_XYZ                (MASK_X | MASK_Y | MASK_Z)
 241 #define MASK_XYZW               (MASK_XYZ | MASK_W)
 242 #define MASK_SATURATE           0x10
 243
 244 /* Temporary, undeclared regs. Preserved between phases */
 245 #define FS_R0                   ((REG_TYPE_R << REG_TYPE_SHIFT) | 0)
 246 #define FS_R1                   ((REG_TYPE_R << REG_TYPE_SHIFT) | 1)
 247 #define FS_R2                   ((REG_TYPE_R << REG_TYPE_SHIFT) | 2)
 248 #define FS_R3                   ((REG_TYPE_R << REG_TYPE_SHIFT) | 3)
 249
 250 /* Texture coordinate regs.  Must be declared. */
 251 #define FS_T0                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 0)
 252 #define FS_T1                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 1)
 253 #define FS_T2                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 2)
 254 #define FS_T3                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 3)
 255 #define FS_T4                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 4)
 256 #define FS_T5                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 5)
 257 #define FS_T6                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 6)
 258 #define FS_T7                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 7)
 259 #define FS_T8                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 8)
 260 #define FS_T9                   ((REG_TYPE_T << REG_TYPE_SHIFT) | 9)
 261 #define FS_T10                  ((REG_TYPE_T << REG_TYPE_SHIFT) | 10)
 262
 263 /* Constant values */
 264 #define FS_C0                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 0)
 265 #define FS_C1                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 1)
 266 #define FS_C2                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 2)
 267 #define FS_C3                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 3)
 268 #define FS_C4                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 4)
 269 #define FS_C5                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 5)
 270 #define FS_C6                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 6)
 271 #define FS_C7                   ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 7)
 272
 273 /* Sampler regs */
 274 #define FS_S0                   ((REG_TYPE_S << REG_TYPE_SHIFT) | 0)
 275 #define FS_S1                   ((REG_TYPE_S << REG_TYPE_SHIFT) | 1)
 276 #define FS_S2                   ((REG_TYPE_S << REG_TYPE_SHIFT) | 2)
 277 #define FS_S3                   ((REG_TYPE_S << REG_TYPE_SHIFT) | 3)
 278
 279 /* Output color */
 280 #define FS_OC                   ((REG_TYPE_OC << REG_TYPE_SHIFT) | 0)
 281
 282 /* Output depth */
 283 #define FS_OD                   ((REG_TYPE_OD << REG_TYPE_SHIFT) | 0)
 284
 285 /* Unpreserved temporary regs */
 286 #define FS_U0                   ((REG_TYPE_U << REG_TYPE_SHIFT) | 0)
 287 #define FS_U1                   ((REG_TYPE_U << REG_TYPE_SHIFT) | 1)
 288 #define FS_U2                   ((REG_TYPE_U << REG_TYPE_SHIFT) | 2)
 289 #define FS_U3                   ((REG_TYPE_U << REG_TYPE_SHIFT) | 3)
 290
 291 #define X_CHANNEL_SHIFT (REG_TYPE_SHIFT + 3)
 292 #define Y_CHANNEL_SHIFT (X_CHANNEL_SHIFT + 4)
 293 #define Z_CHANNEL_SHIFT (Y_CHANNEL_SHIFT + 4)
 294 #define W_CHANNEL_SHIFT (Z_CHANNEL_SHIFT + 4)
 295
 296 #define REG_CHANNEL_MASK 0xf
 297
 298 #define REG_NR(reg)             ((reg) & REG_NR_MASK)
 299 #define REG_TYPE(reg)           (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK)
 300 #define REG_X(reg)              (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
 301 #define REG_Y(reg)              (((reg) >> Y_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
 302 #define REG_Z(reg)              (((reg) >> Z_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
 303 #define REG_W(reg)              (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
 304
 305 enum i915_fs_channel {
 306         X_CHANNEL_VAL = 0,
 307         Y_CHANNEL_VAL,
 308         Z_CHANNEL_VAL,
 309         W_CHANNEL_VAL,
 310         ZERO_CHANNEL_VAL,
 311         ONE_CHANNEL_VAL,
 312
 313         NEG_X_CHANNEL_VAL = X_CHANNEL_VAL | 0x8,
 314         NEG_Y_CHANNEL_VAL = Y_CHANNEL_VAL | 0x8,
 315         NEG_Z_CHANNEL_VAL = Z_CHANNEL_VAL | 0x8,
 316         NEG_W_CHANNEL_VAL = W_CHANNEL_VAL | 0x8,
 317         NEG_ONE_CHANNEL_VAL = ONE_CHANNEL_VAL | 0x8
 318 };
 319
 320 #define i915_fs_operand(reg, x, y, z, w) \
 321         (reg) | \
 322 (x##_CHANNEL_VAL << X_CHANNEL_SHIFT) | \
 323 (y##_CHANNEL_VAL << Y_CHANNEL_SHIFT) | \
 324 (z##_CHANNEL_VAL << Z_CHANNEL_SHIFT) | \
 325 (w##_CHANNEL_VAL << W_CHANNEL_SHIFT)
 326
 327 /**
 328  * Construct an operand description for using a register with no swizzling
 329  */
 330 #define i915_fs_operand_reg(reg)                                        \
 331         i915_fs_operand(reg, X, Y, Z, W)
 332
 333 #define i915_fs_operand_reg_negate(reg)                                 \
 334         i915_fs_operand(reg, NEG_X, NEG_Y, NEG_Z, NEG_W)
 335
 336 /**
 337  * Returns an operand containing (0.0, 0.0, 0.0, 0.0).
 338  */
 339 #define i915_fs_operand_zero() i915_fs_operand(FS_R0, ZERO, ZERO, ZERO, ZERO)
 340
 341 /**
 342  * Returns an unused operand
 343  */
 344 #define i915_fs_operand_none() i915_fs_operand_zero()
 345
 346 /**
 347  * Returns an operand containing (1.0, 1.0, 1.0, 1.0).
 348  */
 349 #define i915_fs_operand_one() i915_fs_operand(FS_R0, ONE, ONE, ONE, ONE)
 350
 351 #define i915_get_hardware_channel_val(val, shift, negate) \
 352         (((val & 0x7) << shift) | ((val & 0x8) ? negate : 0))
 353
 354 /**
 355  * Outputs a fragment shader command to declare a sampler or texture register.
 356  */
 357 #define i915_fs_dcl(reg)                                                \
 358         do {                                                                    \
 359                 OUT_BATCH(D0_DCL | \
 360                           (REG_TYPE(reg) << D0_TYPE_SHIFT) | \
 361                           (REG_NR(reg) << D0_NR_SHIFT) | \
 362                           ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
 363                 OUT_BATCH(0); \
 364                 OUT_BATCH(0); \
 365         } while (0)
 366
 367 #define i915_fs_texld(dest_reg, sampler_reg, address_reg)               \
 368         do {                                                                    \
 369                 OUT_BATCH(T0_TEXLD | \
 370                           (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
 371                           (REG_NR(dest_reg) << T0_DEST_NR_SHIFT) | \
 372                           (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
 373                 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
 374                           (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
 375                 OUT_BATCH(0); \
 376         } while (0)
 377
 378 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg)              \
 379         do {                                                                    \
 380                 OUT_BATCH(T0_TEXLDP | \
 381                           (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
 382                           (REG_NR(dest_reg) << T0_DEST_NR_SHIFT) | \
 383                           (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
 384                 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
 385                           (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
 386                 OUT_BATCH(0); \
 387         } while (0)
 388
 389 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2)     \
 390         _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
 391
 392 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2)       \
 393         _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
 394
 395 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
 396         do { \
 397                 /* Set up destination register and write mask */ \
 398                 OUT_BATCH(cmd | \
 399                           (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
 400                           (REG_NR(dest_reg) << A0_DEST_NR_SHIFT) | \
 401                           (((dest_mask) & ~MASK_SATURATE) << A0_DEST_CHANNEL_SHIFT) | \
 402                           (((dest_mask) & MASK_SATURATE) ? A0_DEST_SATURATE : 0) | \
 403                           /* Set up operand 0 */ \
 404                           (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
 405                           (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
 406                 OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
 407                                                         A1_SRC0_CHANNEL_X_SHIFT, \
 408                                                         A1_SRC0_CHANNEL_X_NEGATE) | \
 409                           i915_get_hardware_channel_val(REG_Y(operand0), \
 410                                                         A1_SRC0_CHANNEL_Y_SHIFT, \
 411                                                         A1_SRC0_CHANNEL_Y_NEGATE) | \
 412                           i915_get_hardware_channel_val(REG_Z(operand0), \
 413                                                         A1_SRC0_CHANNEL_Z_SHIFT, \
 414                                                         A1_SRC0_CHANNEL_Z_NEGATE) | \
 415                           i915_get_hardware_channel_val(REG_W(operand0), \
 416                                                         A1_SRC0_CHANNEL_W_SHIFT, \
 417                                                         A1_SRC0_CHANNEL_W_NEGATE) | \
 418                           /* Set up operand 1 */ \
 419                           (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
 420                           (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
 421                           i915_get_hardware_channel_val(REG_X(operand1), \
 422                                                         A1_SRC1_CHANNEL_X_SHIFT, \
 423                                                         A1_SRC1_CHANNEL_X_NEGATE) | \
 424                           i915_get_hardware_channel_val(REG_Y(operand1), \
 425                                                         A1_SRC1_CHANNEL_Y_SHIFT, \
 426                                                         A1_SRC1_CHANNEL_Y_NEGATE)); \
 427                 OUT_BATCH(i915_get_hardware_channel_val(REG_Z(operand1), \
 428                                                         A2_SRC1_CHANNEL_Z_SHIFT, \
 429                                                         A2_SRC1_CHANNEL_Z_NEGATE) | \
 430                           i915_get_hardware_channel_val(REG_W(operand1), \
 431                                                         A2_SRC1_CHANNEL_W_SHIFT, \
 432                                                         A2_SRC1_CHANNEL_W_NEGATE) | \
 433                           /* Set up operand 2 */ \
 434                           (REG_TYPE(operand2) << A2_SRC2_TYPE_SHIFT) | \
 435                           (REG_NR(operand2) << A2_SRC2_NR_SHIFT) | \
 436                           i915_get_hardware_channel_val(REG_X(operand2), \
 437                                                         A2_SRC2_CHANNEL_X_SHIFT, \
 438                                                         A2_SRC2_CHANNEL_X_NEGATE) | \
 439                           i915_get_hardware_channel_val(REG_Y(operand2), \
 440                                                         A2_SRC2_CHANNEL_Y_SHIFT, \
 441                                                         A2_SRC2_CHANNEL_Y_NEGATE) | \
 442                           i915_get_hardware_channel_val(REG_Z(operand2), \
 443                                                         A2_SRC2_CHANNEL_Z_SHIFT, \
 444                                                         A2_SRC2_CHANNEL_Z_NEGATE) | \
 445                           i915_get_hardware_channel_val(REG_W(operand2), \
 446                                                         A2_SRC2_CHANNEL_W_SHIFT, \
 447                                                         A2_SRC2_CHANNEL_W_NEGATE)); \
 448         } while (0)
 449
 450 #define _i915_fs_arith(cmd, dest_reg, operand0, operand1, operand2) do {\
 451         /* Set up destination register and write mask */ \
 452         OUT_BATCH(cmd | \
 453                   (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
 454                   (REG_NR(dest_reg) << A0_DEST_NR_SHIFT) | \
 455                   (A0_DEST_CHANNEL_ALL) | \
 456                   /* Set up operand 0 */ \
 457                   (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
 458                   (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
 459         OUT_BATCH(i915_get_hardware_channel_val(REG_X(operand0), \
 460                                                 A1_SRC0_CHANNEL_X_SHIFT, \
 461                                                 A1_SRC0_CHANNEL_X_NEGATE) | \
 462                   i915_get_hardware_channel_val(REG_Y(operand0), \
 463                                                 A1_SRC0_CHANNEL_Y_SHIFT, \
 464                                                 A1_SRC0_CHANNEL_Y_NEGATE) | \
 465                   i915_get_hardware_channel_val(REG_Z(operand0), \
 466                                                 A1_SRC0_CHANNEL_Z_SHIFT, \
 467                                                 A1_SRC0_CHANNEL_Z_NEGATE) | \
 468                   i915_get_hardware_channel_val(REG_W(operand0), \
 469                                                 A1_SRC0_CHANNEL_W_SHIFT, \
 470                                                 A1_SRC0_CHANNEL_W_NEGATE) | \
 471                   /* Set up operand 1 */ \
 472                   (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
 473                   (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
 474                   i915_get_hardware_channel_val(REG_X(operand1), \
 475                                                 A1_SRC1_CHANNEL_X_SHIFT, \
 476                                                 A1_SRC1_CHANNEL_X_NEGATE) | \
 477                   i915_get_hardware_channel_val(REG_Y(operand1), \
 478                                                 A1_SRC1_CHANNEL_Y_SHIFT, \
 479                                                 A1_SRC1_CHANNEL_Y_NEGATE)); \
 480         OUT_BATCH(i915_get_hardware_channel_val(REG_Z(operand1), \
 481                                                 A2_SRC1_CHANNEL_Z_SHIFT, \
 482                                                 A2_SRC1_CHANNEL_Z_NEGATE) | \
 483                   i915_get_hardware_channel_val(REG_W(operand1), \
 484                                                 A2_SRC1_CHANNEL_W_SHIFT, \
 485                                                 A2_SRC1_CHANNEL_W_NEGATE) | \
 486                   /* Set up operand 2 */ \
 487                   (REG_TYPE(operand2) << A2_SRC2_TYPE_SHIFT) | \
 488                   (REG_NR(operand2) << A2_SRC2_NR_SHIFT) | \
 489                   i915_get_hardware_channel_val(REG_X(operand2), \
 490                                                 A2_SRC2_CHANNEL_X_SHIFT, \
 491                                                 A2_SRC2_CHANNEL_X_NEGATE) | \
 492                   i915_get_hardware_channel_val(REG_Y(operand2), \
 493                                                 A2_SRC2_CHANNEL_Y_SHIFT, \
 494                                                 A2_SRC2_CHANNEL_Y_NEGATE) | \
 495                   i915_get_hardware_channel_val(REG_Z(operand2), \
 496                                                 A2_SRC2_CHANNEL_Z_SHIFT, \
 497                                                 A2_SRC2_CHANNEL_Z_NEGATE) | \
 498                   i915_get_hardware_channel_val(REG_W(operand2), \
 499                                                 A2_SRC2_CHANNEL_W_SHIFT, \
 500                                                 A2_SRC2_CHANNEL_W_NEGATE)); \
 501 } while (0)
 502
 503 #define i915_fs_mov(dest_reg, operand0)                                 \
 504         i915_fs_arith(MOV, dest_reg, \
 505                       operand0,                 \
 506                       i915_fs_operand_none(),                   \
 507                       i915_fs_operand_none())
 508
 509 #define i915_fs_mov_masked(dest_reg, dest_mask, operand0)               \
 510         i915_fs_arith_masked (MOV, dest_reg, dest_mask, \
 511                               operand0, \
 512                               i915_fs_operand_none(), \
 513                               i915_fs_operand_none())
 514
 515
 516 #define i915_fs_frc(dest_reg, operand0)                                 \
 517         i915_fs_arith (FRC, dest_reg, \
 518                        operand0,                        \
 519                        i915_fs_operand_none(),                  \
 520                        i915_fs_operand_none())
 521
 522 /** Add operand0 and operand1 and put the result in dest_reg */
 523 #define i915_fs_add(dest_reg, operand0, operand1)                       \
 524         i915_fs_arith (ADD, dest_reg, \
 525                        operand0, operand1,      \
 526                        i915_fs_operand_none())
 527
 528 /** Multiply operand0 and operand1 and put the result in dest_reg */
 529 #define i915_fs_mul(dest_reg, operand0, operand1)                       \
 530         i915_fs_arith (MUL, dest_reg, \
 531                        operand0, operand1,      \
 532                        i915_fs_operand_none())
 533
 534 /** Computes 1/sqrt(operand0.replicate_swizzle) puts the result in dest_reg */
 535 #define i915_fs_rsq(dest_reg, dest_mask, operand0)              \
 536         do {                                                                    \
 537                 if (dest_mask) {                                                        \
 538                         i915_fs_arith_masked (RSQ, dest_reg, dest_mask, \
 539                                               operand0,                 \
 540                                               i915_fs_operand_none (),                  \
 541                                               i915_fs_operand_none ());                 \
 542                 } else { \
 543                         i915_fs_arith (RSQ, dest_reg, \
 544                                        operand0, \
 545                                        i915_fs_operand_none (), \
 546                                        i915_fs_operand_none ()); \
 547                 } \
 548         } while (0)
 549
 550 /** Puts the minimum of operand0 and operand1 in dest_reg */
 551 #define i915_fs_min(dest_reg, operand0, operand1)                       \
 552         i915_fs_arith (MIN, dest_reg, \
 553                        operand0, operand1, \
 554                        i915_fs_operand_none())
 555
 556 /** Puts the maximum of operand0 and operand1 in dest_reg */
 557 #define i915_fs_max(dest_reg, operand0, operand1)                       \
 558         i915_fs_arith (MAX, dest_reg, \
 559                        operand0, operand1, \
 560                        i915_fs_operand_none())
 561
 562 #define i915_fs_cmp(dest_reg, operand0, operand1, operand2)             \
 563         i915_fs_arith (CMP, dest_reg, operand0, operand1, operand2)
 564
 565 /** Perform operand0 * operand1 + operand2 and put the result in dest_reg */
 566 #define i915_fs_mad(dest_reg, dest_mask, op0, op1, op2) \
 567         do {                                                                    \
 568                 if (dest_mask) {                                                        \
 569                         i915_fs_arith_masked (MAD, dest_reg, dest_mask, op0, op1, op2); \
 570                 } else { \
 571                         i915_fs_arith (MAD, dest_reg, op0, op1, op2); \
 572                 } \
 573         } while (0)
 574
 575 #define i915_fs_dp2add(dest_reg, dest_mask, op0, op1, op2)      \
 576         do {                                                                    \
 577                 if (dest_mask) {                                                        \
 578                         i915_fs_arith_masked (DP2ADD, dest_reg, dest_mask, op0, op1, op2); \
 579                 } else { \
 580                         i915_fs_arith (DP2ADD, dest_reg, op0, op1, op2); \
 581                 } \
 582         } while (0)
 583
 584 /**
 585  * Perform a 3-component dot-product of operand0 and operand1 and put the
 586  * resulting scalar in the channels of dest_reg specified by the dest_mask.
 587  */
 588 #define i915_fs_dp3(dest_reg, dest_mask, op0, op1)      \
 589         do {                                                                    \
 590                 if (dest_mask) {                                                        \
 591                         i915_fs_arith_masked (DP3, dest_reg, dest_mask, \
 592                                               op0, op1,\
 593                                               i915_fs_operand_none());                  \
 594                 } else { \
 595                         i915_fs_arith (DP3, dest_reg, op0, op1,\
 596                                        i915_fs_operand_none());                 \
 597                 } \
 598         } while (0)
 599
 600 /**
 601  * Sets up local state for accumulating a fragment shader buffer.
 602  *
 603  * \param x maximum number of shader commands that may be used between
 604  *        a FS_START and FS_END
 605  */
 606 #define FS_LOCALS()                                                     \
 607         uint32_t _shader_offset
 608
 609 #define FS_BEGIN()                                                      \
 610         do {                                                                    \
 611                 _shader_offset = intel->batch_used++;                           \
 612         } while (0)
 613
 614 #define FS_END()                                                        \
 615         do {                                                                    \
 616                 intel->batch_ptr[_shader_offset] =                                      \
 617                 _3DSTATE_PIXEL_SHADER_PROGRAM |                                 \
 618                 (intel->batch_used - _shader_offset - 2);                       \
 619         } while (0);