Initial code release
[adaptation/xorg-x11-drv-intel.git] / src / i915_3d.c
1 /**************************************************************************
2  * 
3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4  * All Rights Reserved.
5  * 
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  * 
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  * 
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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26  **************************************************************************/
27
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "xf86.h"
33 #include "intel.h"
34
35 #include "i915_reg.h"
36
37 void I915EmitInvarientState(ScrnInfoPtr scrn)
38 {
39         intel_screen_private *intel = intel_get_screen_private(scrn);
40
41         assert(intel->in_batch_atomic);
42
43         OUT_BATCH(_3DSTATE_AA_CMD |
44                   AA_LINE_ECAAR_WIDTH_ENABLE |
45                   AA_LINE_ECAAR_WIDTH_1_0 |
46                   AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
47
48         /* Disable independent alpha blend */
49         OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
50                   IAB_MODIFY_ENABLE |
51                   IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
52                   IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
53                                            IAB_SRC_FACTOR_SHIFT) |
54                   IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
55                                            IAB_DST_FACTOR_SHIFT));
56
57         OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
58         OUT_BATCH(0);
59
60         OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
61         OUT_BATCH(0);
62
63         OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
64         OUT_BATCH(0);
65
66         /* Don't support texture crossbar yet */
67         OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
68                   CSB_TCB(0, 0) |
69                   CSB_TCB(1, 1) |
70                   CSB_TCB(2, 2) |
71                   CSB_TCB(3, 3) |
72                   CSB_TCB(4, 4) |
73                   CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
74
75         OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
76                   ENABLE_POINT_RASTER_RULE |
77                   OGL_POINT_RASTER_RULE |
78                   ENABLE_LINE_STRIP_PROVOKE_VRTX |
79                   ENABLE_TRI_FAN_PROVOKE_VRTX |
80                   LINE_STRIP_PROVOKE_VRTX(1) |
81                   TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
82
83         OUT_BATCH(_3DSTATE_MODES_4_CMD |
84                   ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
85                   ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
86                   ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
87
88         OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
89         OUT_BATCH(0x00000000);  /* Disable texture coordinate wrap-shortest */
90         OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
91                   S4_LINE_WIDTH_ONE |
92                   S4_CULLMODE_NONE |
93                   S4_VFMT_XY);
94         OUT_BATCH(0x00000000);  /* Stencil. */
95
96         OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
97         OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
98         OUT_BATCH(0);
99         OUT_BATCH(0);
100
101         OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
102
103         OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);  /* disable indirect state */
104         OUT_BATCH(0);
105
106         OUT_BATCH(_3DSTATE_STIPPLE);
107         OUT_BATCH(0x00000000);
108
109         OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
110 }