2 * PASS (Power Aware System Service)
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
6 * Licensed under the Apache License, Version 2.0 (the License);
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
10 * http://www.apache.org/licenses/LICENSE-2.0
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
21 #include <pass/hal-log.h>
26 #include "../shared/sysfs.h"
29 #define HAL_VERSION MAKE_2B_CODE_4(VER_MAJOR,VER_MINOR,VER_REVISION,VER_RELEASE)
30 #define DEV_VERSION_GPU MAKE_2B_CODE_2(1,0)
32 #define DEVFREQ_GPU_PATH_PREFIX "/sys/class/devfreq/"
33 #define DEVFREQ_GPU_CURR_GOVERNOR_PATH_SUFFIX "/governor"
34 #define DEVFREQ_GPU_CURR_FREQ_PATH_SUFFIX "/cur_freq"
35 #define DEVFREQ_GPU_MIN_FREQ_PATH_SUFFIX "/min_freq"
36 #define DEVFREQ_GPU_MAX_FREQ_PATH_SUFFIX "/max_freq"
38 #define TMU_PATH_PREFIX "/sys/class/thermal/thermal_zone"
39 #define TMU_TEMP_PATH_SUFFIX "/temp"
40 #define TMU_POLICY_PATH_SUFFIX "/policy"
42 #define TM2_GPU_THERMAL_ZONE_NUM 2
44 static int tm2_dvfs_get_curr_governor(char *res_name, char *governor)
49 if ((!res_name) || (!governor))
52 snprintf(path, PATH_MAX, "%s%s%s",
53 DEVFREQ_GPU_PATH_PREFIX,
55 DEVFREQ_GPU_CURR_GOVERNOR_PATH_SUFFIX);
57 ret = sysfs_read_str(path, governor, BUFF_MAX);
64 static int tm2_dvfs_set_curr_governor(char *res_name, char *governor)
69 if ((!res_name) || (!governor))
72 snprintf(path, PATH_MAX, "%s%s%s",
73 DEVFREQ_GPU_PATH_PREFIX,
75 DEVFREQ_GPU_CURR_GOVERNOR_PATH_SUFFIX);
77 ret = sysfs_write_str(path, governor);
84 static int tm2_dvfs_get_curr_freq(char *res_name)
92 snprintf(path, PATH_MAX, "%s%s%s",
93 DEVFREQ_GPU_PATH_PREFIX,
95 DEVFREQ_GPU_CURR_FREQ_PATH_SUFFIX);
97 ret = sysfs_read_int(path, &freq);
104 static int tm2_dvfs_get_min_freq(char *res_name)
112 snprintf(path, PATH_MAX, "%s%s%s",
113 DEVFREQ_GPU_PATH_PREFIX,
115 DEVFREQ_GPU_MIN_FREQ_PATH_SUFFIX);
117 ret = sysfs_read_int(path, &freq);
124 static int tm2_dvfs_set_min_freq(char *res_name, int freq)
129 if ((!res_name) || (freq < 0))
132 snprintf(path, PATH_MAX, "%s%s%s",
133 DEVFREQ_GPU_PATH_PREFIX,
135 DEVFREQ_GPU_MIN_FREQ_PATH_SUFFIX);
137 ret = sysfs_write_int(path, freq);
144 static int tm2_dvfs_get_max_freq(char *res_name)
152 snprintf(path, PATH_MAX, "%s%s%s",
153 DEVFREQ_GPU_PATH_PREFIX,
155 DEVFREQ_GPU_MAX_FREQ_PATH_SUFFIX);
157 ret = sysfs_read_int(path, &freq);
164 static int tm2_dvfs_set_max_freq(char *res_name, int freq)
169 if ((!res_name) || (freq < 0))
172 snprintf(path, PATH_MAX, "%s%s%s",
173 DEVFREQ_GPU_PATH_PREFIX,
175 DEVFREQ_GPU_MAX_FREQ_PATH_SUFFIX);
177 ret = sysfs_write_int(path, freq);
184 static struct pass_resource_dvfs_ops tm2_gpu_dvfs_ops = {
185 .get_curr_governor = tm2_dvfs_get_curr_governor,
186 .set_curr_governor = tm2_dvfs_set_curr_governor,
187 .get_avail_governor = NULL,
188 .get_curr_freq = tm2_dvfs_get_curr_freq,
189 .get_min_freq = tm2_dvfs_get_min_freq,
190 .set_min_freq = tm2_dvfs_set_min_freq,
191 .get_max_freq = tm2_dvfs_get_max_freq,
192 .set_max_freq = tm2_dvfs_set_max_freq,
193 .get_up_threshold = NULL,
194 .set_up_threshold = NULL,
195 .get_load_table = NULL,
198 static int tm2_tmu_get_temp(char *res_name)
207 snprintf(path, PATH_MAX, "%s%d%s",
209 TM2_GPU_THERMAL_ZONE_NUM,
210 TMU_TEMP_PATH_SUFFIX);
212 ret = sysfs_read_int(path, &temp);
219 static int tm2_tmu_get_policy(char *res_name, char *policy)
224 if ((!res_name) || (!policy))
227 snprintf(path, PATH_MAX, "%s%d%s",
229 TM2_GPU_THERMAL_ZONE_NUM,
230 TMU_POLICY_PATH_SUFFIX);
232 ret = sysfs_read_str(path, policy, BUFF_MAX);
239 static struct pass_resource_tmu_ops tm2_gpu_tmu_ops = {
240 .get_temp = tm2_tmu_get_temp,
241 .get_policy = tm2_tmu_get_policy,
244 static int tm2_gpu_open(char *res_name, struct pass_resource_info *info,
245 struct pass_resource_common **common)
247 struct pass_resource_gpu *gpu_res;
252 /* TODO: Possibility of a memory leak */
253 gpu_res = calloc(1, sizeof(struct pass_resource_gpu));
257 gpu_res->common.info = info;
258 gpu_res->dvfs = tm2_gpu_dvfs_ops;
259 gpu_res->tmu = tm2_gpu_tmu_ops;
261 *common = (struct pass_resource_common *) gpu_res;
266 static int tm2_gpu_close(char *res_name, struct pass_resource_common *common)
276 HAL_MODULE_STRUCTURE = {
277 .magic = HAL_INFO_TAG,
278 .hal_version = HAL_VERSION,
279 .device_version = DEV_VERSION_GPU,
280 .id = PASS_RESOURCE_GPU_ID,
281 .name = PASS_RESOURCE_GPU_NAME,
282 .author = "Wook Song <wook16.song@samsung.com>",
283 .open = tm2_gpu_open,
284 .close = tm2_gpu_close,