2 * PASS (Power Aware System Service)
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
6 * Licensed under the Apache License, Version 2.0 (the License);
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
10 * http://www.apache.org/licenses/LICENSE-2.0
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
21 #include <pass/hal-log.h>
26 #include "../shared/sysfs.h"
29 #define HAL_VERSION MAKE_2B_CODE_4(VER_MAJOR,VER_MINOR,VER_REVISION,VER_RELEASE)
30 #define DEV_VERSION_GPU MAKE_2B_CODE_2(1,0)
32 #define DEVFREQ_GPU_PATH_PREFIX "/sys/class/devfreq/"
33 #define DEVFREQ_GPU_CURR_GOVERNOR_PATH_SUFFIX "/governor"
34 #define DEVFREQ_GPU_CURR_FREQ_PATH_SUFFIX "/cur_freq"
35 #define DEVFREQ_GPU_MIN_FREQ_PATH_SUFFIX "/min_freq"
36 #define DEVFREQ_GPU_MAX_FREQ_PATH_SUFFIX "/max_freq"
38 #define TMU_PATH_PREFIX "/sys/class/thermal/"
39 #define TMU_TEMP_PATH_SUFFIX "/temp"
40 #define TMU_POLICY_PATH_SUFFIX "/policy"
42 static int tm2_dvfs_get_curr_governor(char *res_name, char *governor)
47 if ((!res_name) || (!governor))
50 snprintf(path, PATH_MAX, "%s%s%s",
51 DEVFREQ_GPU_PATH_PREFIX,
53 DEVFREQ_GPU_CURR_GOVERNOR_PATH_SUFFIX);
55 ret = sysfs_read_str(path, governor, BUFF_MAX);
62 static int tm2_dvfs_set_curr_governor(char *res_name, char *governor)
67 if ((!res_name) || (!governor))
70 snprintf(path, PATH_MAX, "%s%s%s",
71 DEVFREQ_GPU_PATH_PREFIX,
73 DEVFREQ_GPU_CURR_GOVERNOR_PATH_SUFFIX);
75 ret = sysfs_write_str(path, governor);
82 static int tm2_dvfs_get_curr_freq(char *res_name)
90 snprintf(path, PATH_MAX, "%s%s%s",
91 DEVFREQ_GPU_PATH_PREFIX,
93 DEVFREQ_GPU_CURR_FREQ_PATH_SUFFIX);
95 ret = sysfs_read_int(path, &freq);
102 static int tm2_dvfs_get_min_freq(char *res_name)
110 snprintf(path, PATH_MAX, "%s%s%s",
111 DEVFREQ_GPU_PATH_PREFIX,
113 DEVFREQ_GPU_MIN_FREQ_PATH_SUFFIX);
115 ret = sysfs_read_int(path, &freq);
122 static int tm2_dvfs_set_min_freq(char *res_name, int freq)
127 if ((!res_name) || (freq < 0))
130 snprintf(path, PATH_MAX, "%s%s%s",
131 DEVFREQ_GPU_PATH_PREFIX,
133 DEVFREQ_GPU_MIN_FREQ_PATH_SUFFIX);
135 ret = sysfs_write_int(path, freq);
142 static int tm2_dvfs_get_max_freq(char *res_name)
150 snprintf(path, PATH_MAX, "%s%s%s",
151 DEVFREQ_GPU_PATH_PREFIX,
153 DEVFREQ_GPU_MAX_FREQ_PATH_SUFFIX);
155 ret = sysfs_read_int(path, &freq);
162 static int tm2_dvfs_set_max_freq(char *res_name, int freq)
167 if ((!res_name) || (freq < 0))
170 snprintf(path, PATH_MAX, "%s%s%s",
171 DEVFREQ_GPU_PATH_PREFIX,
173 DEVFREQ_GPU_MAX_FREQ_PATH_SUFFIX);
175 ret = sysfs_write_int(path, freq);
182 static struct pass_resource_dvfs_ops tm2_gpu_dvfs_ops = {
183 .get_curr_governor = tm2_dvfs_get_curr_governor,
184 .set_curr_governor = tm2_dvfs_set_curr_governor,
185 .get_avail_governor = NULL,
186 .get_curr_freq = tm2_dvfs_get_curr_freq,
187 .get_min_freq = tm2_dvfs_get_min_freq,
188 .set_min_freq = tm2_dvfs_set_min_freq,
189 .get_max_freq = tm2_dvfs_get_max_freq,
190 .set_max_freq = tm2_dvfs_set_max_freq,
191 .get_up_threshold = NULL,
192 .set_up_threshold = NULL,
193 .get_load_table = NULL,
196 static int tm2_tmu_get_temp(char *res_thermal_name);
205 snprintf(path, PATH_MAX, "%s%s%s",
208 TMU_TEMP_PATH_SUFFIX);
210 ret = sysfs_read_int(path, &temp);
217 static int tm2_tmu_get_policy(char *res_thermal_name, char *policy)
222 if ((!res_name) || (!policy))
225 snprintf(path, PATH_MAX, "%s%s%s",
228 TMU_POLICY_PATH_SUFFIX);
230 ret = sysfs_read_str(path, policy, BUFF_MAX);
237 static struct pass_resource_tmu_ops tm2_gpu_tmu_ops = {
238 .get_temp = tm2_tmu_get_temp,
239 .get_policy = tm2_tmu_get_policy,
242 static int tm2_gpu_open(char *res_name, struct pass_resource_info *info,
243 struct pass_resource_common **common)
245 struct pass_resource_gpu *gpu_res;
250 /* TODO: Possibility of a memory leak */
251 gpu_res = calloc(1, sizeof(struct pass_resource_gpu));
255 gpu_res->common.info = info;
256 gpu_res->dvfs = tm2_gpu_dvfs_ops;
257 gpu_res->tmu = tm2_gpu_tmu_ops;
259 *common = (struct pass_resource_common *) gpu_res;
264 static int tm2_gpu_close(char *res_name, struct pass_resource_common *common)
274 HAL_MODULE_STRUCTURE = {
275 .magic = HAL_INFO_TAG,
276 .hal_version = HAL_VERSION,
277 .device_version = DEV_VERSION_GPU,
278 .id = PASS_RESOURCE_GPU_ID,
279 .name = PASS_RESOURCE_GPU_NAME,
280 .author = "Wook Song <wook16.song@samsung.com>",
281 .open = tm2_gpu_open,
282 .close = tm2_gpu_close,