src/gen7_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30
  31 #include <va/va_dec_jpeg.h>
  32
  33 #include "intel_batchbuffer.h"
  34 #include "intel_driver.h"
  35 #include "i965_defines.h"
  36 #include "i965_drv_video.h"
  37 #include "i965_decoder_utils.h"
  38
  39 #include "gen7_mfd.h"
  40 #include "intel_media.h"
  41
  42 static const uint32_t zigzag_direct[64] = {
  43     0,   1,  8, 16,  9,  2,  3, 10,
  44     17, 24, 32, 25, 18, 11,  4,  5,
  45     12, 19, 26, 33, 40, 48, 41, 34,
  46     27, 20, 13,  6,  7, 14, 21, 28,
  47     35, 42, 49, 56, 57, 50, 43, 36,
  48     29, 22, 15, 23, 30, 37, 44, 51,
  49     58, 59, 52, 45, 38, 31, 39, 46,
  50     53, 60, 61, 54, 47, 55, 62, 63
  51 };
  52
  53 static void
  54 gen7_mfd_init_avc_surface(VADriverContextP ctx,
  55                           VAPictureParameterBufferH264 *pic_param,
  56                           struct object_surface *obj_surface)
  57 {
  58     struct i965_driver_data *i965 = i965_driver_data(ctx);
  59     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
  60     int width_in_mbs, height_in_mbs;
  61
  62     obj_surface->free_private_data = gen_free_avc_surface;
  63     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
  64     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
  65
  66     if (!gen7_avc_surface) {
  67         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  68         assert((obj_surface->size & 0x3f) == 0);
  69         obj_surface->private_data = gen7_avc_surface;
  70     }
  71
  72     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  73                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  74
  75     if (gen7_avc_surface->dmv_top == NULL) {
  76         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  77                                                  "direct mv w/r buffer",
  78                                                  width_in_mbs * (height_in_mbs + 1) * 64,
  79                                                  0x1000);
  80         assert(gen7_avc_surface->dmv_top);
  81     }
  82
  83     if (gen7_avc_surface->dmv_bottom_flag &&
  84         gen7_avc_surface->dmv_bottom == NULL) {
  85         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  86                                                     "direct mv w/r buffer",
  87                                                     width_in_mbs * (height_in_mbs + 1) * 64,
  88                                                     0x1000);
  89         assert(gen7_avc_surface->dmv_bottom);
  90     }
  91 }
  92
  93 static void
  94 gen7_mfd_pipe_mode_select(VADriverContextP ctx,
  95                           struct decode_state *decode_state,
  96                           int standard_select,
  97                           struct gen7_mfd_context *gen7_mfd_context)
  98 {
  99     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 100
 101     assert(standard_select == MFX_FORMAT_MPEG2 ||
 102            standard_select == MFX_FORMAT_AVC ||
 103            standard_select == MFX_FORMAT_VC1 ||
 104            standard_select == MFX_FORMAT_JPEG);
 105
 106     BEGIN_BCS_BATCH(batch, 5);
 107     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 108     OUT_BCS_BATCH(batch,
 109                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 110                   (MFD_MODE_VLD << 15) | /* VLD mode */
 111                   (0 << 10) | /* disable Stream-Out */
 112                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 113                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 114                   (0 << 5)  | /* not in stitch mode */
 115                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 116                   (standard_select << 0));
 117     OUT_BCS_BATCH(batch,
 118                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 119                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 120                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 121                   (0 << 1)  |
 122                   (0 << 0));
 123     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 124     OUT_BCS_BATCH(batch, 0); /* reserved */
 125     ADVANCE_BCS_BATCH(batch);
 126 }
 127
 128 static void
 129 gen7_mfd_surface_state(VADriverContextP ctx,
 130                        struct decode_state *decode_state,
 131                        int standard_select,
 132                        struct gen7_mfd_context *gen7_mfd_context)
 133 {
 134     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 135     struct object_surface *obj_surface = decode_state->render_object;
 136     unsigned int y_cb_offset;
 137     unsigned int y_cr_offset;
 138     unsigned int surface_format;
 139
 140     assert(obj_surface);
 141
 142     y_cb_offset = obj_surface->y_cb_offset;
 143     y_cr_offset = obj_surface->y_cr_offset;
 144
 145     surface_format = obj_surface->fourcc == VA_FOURCC_Y800 ?
 146         MFX_SURFACE_MONOCHROME : MFX_SURFACE_PLANAR_420_8;
 147
 148     BEGIN_BCS_BATCH(batch, 6);
 149     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 150     OUT_BCS_BATCH(batch, 0);
 151     OUT_BCS_BATCH(batch,
 152                   ((obj_surface->orig_height - 1) << 18) |
 153                   ((obj_surface->orig_width - 1) << 4));
 154     OUT_BCS_BATCH(batch,
 155                   (surface_format << 28) | /* 420 planar YUV surface */
 156                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 157                   (0 << 22) | /* surface object control state, ignored */
 158                   ((obj_surface->width - 1) << 3) | /* pitch */
 159                   (0 << 2)  | /* must be 0 */
 160                   (1 << 1)  | /* must be tiled */
 161                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 162     OUT_BCS_BATCH(batch,
 163                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 164                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 165     OUT_BCS_BATCH(batch,
 166                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 167                   (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 168     ADVANCE_BCS_BATCH(batch);
 169 }
 170
 171 static void
 172 gen7_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 173                              struct decode_state *decode_state,
 174                              int standard_select,
 175                              struct gen7_mfd_context *gen7_mfd_context)
 176 {
 177     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 178     int i;
 179
 180     BEGIN_BCS_BATCH(batch, 24);
 181     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 182     if (gen7_mfd_context->pre_deblocking_output.valid)
 183         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 184                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                       0);
 186     else
 187         OUT_BCS_BATCH(batch, 0);
 188
 189     if (gen7_mfd_context->post_deblocking_output.valid)
 190         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 191                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 192                       0);
 193     else
 194         OUT_BCS_BATCH(batch, 0);
 195
 196     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 197     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 198
 199     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 200         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 201                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 202                       0);
 203     else
 204         OUT_BCS_BATCH(batch, 0);
 205
 206     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 207         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 208                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 209                       0);
 210     else
 211         OUT_BCS_BATCH(batch, 0);
 212
 213     /* DW 7..22 */
 214     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 215         struct object_surface *obj_surface;
 216
 217         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 218             gen7_mfd_context->reference_surface[i].obj_surface &&
 219             gen7_mfd_context->reference_surface[i].obj_surface->bo) {
 220             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 221
 222             OUT_BCS_RELOC(batch, obj_surface->bo,
 223                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 224                           0);
 225         } else {
 226             OUT_BCS_BATCH(batch, 0);
 227         }
 228     }
 229
 230     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 231     ADVANCE_BCS_BATCH(batch);
 232 }
 233
 234 static void
 235 gen7_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 236                                  dri_bo *slice_data_bo,
 237                                  int standard_select,
 238                                  struct gen7_mfd_context *gen7_mfd_context)
 239 {
 240     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 241
 242     BEGIN_BCS_BATCH(batch, 11);
 243     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 244     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 245     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 246     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 247     OUT_BCS_BATCH(batch, 0);
 248     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 249     OUT_BCS_BATCH(batch, 0);
 250     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 251     OUT_BCS_BATCH(batch, 0);
 252     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 253     OUT_BCS_BATCH(batch, 0);
 254     ADVANCE_BCS_BATCH(batch);
 255 }
 256
 257 static void
 258 gen7_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 259                                  struct decode_state *decode_state,
 260                                  int standard_select,
 261                                  struct gen7_mfd_context *gen7_mfd_context)
 262 {
 263     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 264
 265     BEGIN_BCS_BATCH(batch, 4);
 266     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 267
 268     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 269         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 270                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 271                       0);
 272     else
 273         OUT_BCS_BATCH(batch, 0);
 274
 275     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 276         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 277                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 278                       0);
 279     else
 280         OUT_BCS_BATCH(batch, 0);
 281
 282     if (gen7_mfd_context->bitplane_read_buffer.valid)
 283         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 284                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 285                       0);
 286     else
 287         OUT_BCS_BATCH(batch, 0);
 288
 289     ADVANCE_BCS_BATCH(batch);
 290 }
 291
 292 static void
 293 gen7_mfd_qm_state(VADriverContextP ctx,
 294                   int qm_type,
 295                   unsigned char *qm,
 296                   int qm_length,
 297                   struct gen7_mfd_context *gen7_mfd_context)
 298 {
 299     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 300     unsigned int qm_buffer[16];
 301
 302     assert(qm_length <= 16 * 4);
 303     memcpy(qm_buffer, qm, qm_length);
 304
 305     BEGIN_BCS_BATCH(batch, 18);
 306     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 307     OUT_BCS_BATCH(batch, qm_type << 0);
 308     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 309     ADVANCE_BCS_BATCH(batch);
 310 }
 311
 312 static void
 313 gen7_mfd_avc_img_state(VADriverContextP ctx,
 314                        struct decode_state *decode_state,
 315                        struct gen7_mfd_context *gen7_mfd_context)
 316 {
 317     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 318     int img_struct;
 319     int mbaff_frame_flag;
 320     unsigned int width_in_mbs, height_in_mbs;
 321     VAPictureParameterBufferH264 *pic_param;
 322
 323     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 324     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 325
 326     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 327         img_struct = 1;
 328     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 329         img_struct = 3;
 330     else
 331         img_struct = 0;
 332
 333     if ((img_struct & 0x1) == 0x1) {
 334         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 335     } else {
 336         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 337     }
 338
 339     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 340         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 341         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 342     } else {
 343         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 344     }
 345
 346     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 347                         !pic_param->pic_fields.bits.field_pic_flag);
 348
 349     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 350     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 351
 352     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 353     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 354            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 355     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 356
 357     BEGIN_BCS_BATCH(batch, 16);
 358     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 359     OUT_BCS_BATCH(batch,
 360                   (width_in_mbs * height_in_mbs - 1));
 361     OUT_BCS_BATCH(batch,
 362                   ((height_in_mbs - 1) << 16) |
 363                   ((width_in_mbs - 1) << 0));
 364     OUT_BCS_BATCH(batch,
 365                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 366                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 367                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 368                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 369                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 370                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 371                   (img_struct << 8));
 372     OUT_BCS_BATCH(batch,
 373                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 374                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 375                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 376                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 377                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 378                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 379                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 380                   (mbaff_frame_flag << 1) |
 381                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 382     OUT_BCS_BATCH(batch, 0);
 383     OUT_BCS_BATCH(batch, 0);
 384     OUT_BCS_BATCH(batch, 0);
 385     OUT_BCS_BATCH(batch, 0);
 386     OUT_BCS_BATCH(batch, 0);
 387     OUT_BCS_BATCH(batch, 0);
 388     OUT_BCS_BATCH(batch, 0);
 389     OUT_BCS_BATCH(batch, 0);
 390     OUT_BCS_BATCH(batch, 0);
 391     OUT_BCS_BATCH(batch, 0);
 392     OUT_BCS_BATCH(batch, 0);
 393     ADVANCE_BCS_BATCH(batch);
 394 }
 395
 396 static void
 397 gen7_mfd_avc_qm_state(VADriverContextP ctx,
 398                       struct decode_state *decode_state,
 399                       struct gen7_mfd_context *gen7_mfd_context)
 400 {
 401     VAIQMatrixBufferH264 *iq_matrix;
 402     VAPictureParameterBufferH264 *pic_param;
 403
 404     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 405         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 406     else
 407         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 408
 409     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 410     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 411
 412     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 413     gen7_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 414
 415     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 416         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 417         gen7_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 418     }
 419 }
 420
 421 static void
 422 gen7_mfd_avc_directmode_state(VADriverContextP ctx,
 423                               struct decode_state *decode_state,
 424                               VAPictureParameterBufferH264 *pic_param,
 425                               VASliceParameterBufferH264 *slice_param,
 426                               struct gen7_mfd_context *gen7_mfd_context)
 427 {
 428     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 429     struct object_surface *obj_surface;
 430     GenAvcSurface *gen7_avc_surface;
 431     VAPictureH264 *va_pic;
 432     int i, j;
 433
 434     BEGIN_BCS_BATCH(batch, 69);
 435     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 436
 437     /* reference surfaces 0..15 */
 438     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 439         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 440             gen7_mfd_context->reference_surface[i].obj_surface &&
 441             gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
 442
 443             obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
 444             gen7_avc_surface = obj_surface->private_data;
 445             OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 446                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 447                           0);
 448
 449             if (gen7_avc_surface->dmv_bottom_flag == 1)
 450                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 451                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 452                               0);
 453             else
 454                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 455                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 456                               0);
 457         } else {
 458             OUT_BCS_BATCH(batch, 0);
 459             OUT_BCS_BATCH(batch, 0);
 460         }
 461     }
 462
 463     /* the current decoding frame/field */
 464     va_pic = &pic_param->CurrPic;
 465     obj_surface = decode_state->render_object;
 466     assert(obj_surface->bo && obj_surface->private_data);
 467     gen7_avc_surface = obj_surface->private_data;
 468
 469     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 470                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 471                   0);
 472
 473     if (gen7_avc_surface->dmv_bottom_flag == 1)
 474         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 475                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 476                       0);
 477     else
 478         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 479                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 480                       0);
 481
 482     /* POC List */
 483     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 484         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 485             int found = 0;
 486
 487             assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL);
 488
 489             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 490                 va_pic = &pic_param->ReferenceFrames[j];
 491
 492                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 493                     continue;
 494
 495                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 496                     found = 1;
 497                     break;
 498                 }
 499             }
 500
 501             assert(found == 1);
 502             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 503
 504             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 505             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 506         } else {
 507             OUT_BCS_BATCH(batch, 0);
 508             OUT_BCS_BATCH(batch, 0);
 509         }
 510     }
 511
 512     va_pic = &pic_param->CurrPic;
 513     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 514     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 515
 516     ADVANCE_BCS_BATCH(batch);
 517 }
 518
 519 static void
 520 gen7_mfd_avc_slice_state(VADriverContextP ctx,
 521                          VAPictureParameterBufferH264 *pic_param,
 522                          VASliceParameterBufferH264 *slice_param,
 523                          VASliceParameterBufferH264 *next_slice_param,
 524                          struct gen7_mfd_context *gen7_mfd_context)
 525 {
 526     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 527     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 528     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 529     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 530     int num_ref_idx_l0, num_ref_idx_l1;
 531     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 532                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 533     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 534     int slice_type;
 535
 536     if (slice_param->slice_type == SLICE_TYPE_I ||
 537         slice_param->slice_type == SLICE_TYPE_SI) {
 538         slice_type = SLICE_TYPE_I;
 539     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 540                slice_param->slice_type == SLICE_TYPE_SP) {
 541         slice_type = SLICE_TYPE_P;
 542     } else {
 543         assert(slice_param->slice_type == SLICE_TYPE_B);
 544         slice_type = SLICE_TYPE_B;
 545     }
 546
 547     if (slice_type == SLICE_TYPE_I) {
 548         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 549         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 550         num_ref_idx_l0 = 0;
 551         num_ref_idx_l1 = 0;
 552     } else if (slice_type == SLICE_TYPE_P) {
 553         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 554         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 555         num_ref_idx_l1 = 0;
 556     } else {
 557         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 558         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 559     }
 560
 561     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 562     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 563     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 564
 565     if (next_slice_param) {
 566         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 567         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 568         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 569     } else {
 570         next_slice_hor_pos = 0;
 571         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 572     }
 573
 574     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 575     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 576     OUT_BCS_BATCH(batch, slice_type);
 577     OUT_BCS_BATCH(batch,
 578                   (num_ref_idx_l1 << 24) |
 579                   (num_ref_idx_l0 << 16) |
 580                   (slice_param->chroma_log2_weight_denom << 8) |
 581                   (slice_param->luma_log2_weight_denom << 0));
 582     OUT_BCS_BATCH(batch,
 583                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 584                   (slice_param->disable_deblocking_filter_idc << 27) |
 585                   (slice_param->cabac_init_idc << 24) |
 586                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 587                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 588                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 589     OUT_BCS_BATCH(batch,
 590                   (slice_ver_pos << 24) |
 591                   (slice_hor_pos << 16) |
 592                   (first_mb_in_slice << 0));
 593     OUT_BCS_BATCH(batch,
 594                   (next_slice_ver_pos << 16) |
 595                   (next_slice_hor_pos << 0));
 596     OUT_BCS_BATCH(batch,
 597                   (next_slice_param == NULL) << 19); /* last slice flag */
 598     OUT_BCS_BATCH(batch, 0);
 599     OUT_BCS_BATCH(batch, 0);
 600     OUT_BCS_BATCH(batch, 0);
 601     OUT_BCS_BATCH(batch, 0);
 602     ADVANCE_BCS_BATCH(batch);
 603 }
 604
 605 static inline void
 606 gen7_mfd_avc_ref_idx_state(VADriverContextP ctx,
 607                            VAPictureParameterBufferH264 *pic_param,
 608                            VASliceParameterBufferH264 *slice_param,
 609                            struct gen7_mfd_context *gen7_mfd_context)
 610 {
 611     gen6_send_avc_ref_idx_state(
 612         gen7_mfd_context->base.batch,
 613         slice_param,
 614         gen7_mfd_context->reference_surface
 615     );
 616 }
 617
 618 static void
 619 gen7_mfd_avc_weightoffset_state(VADriverContextP ctx,
 620                                 VAPictureParameterBufferH264 *pic_param,
 621                                 VASliceParameterBufferH264 *slice_param,
 622                                 struct gen7_mfd_context *gen7_mfd_context)
 623 {
 624     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 625     int i, j, num_weight_offset_table = 0;
 626     short weightoffsets[32 * 6];
 627
 628     if ((slice_param->slice_type == SLICE_TYPE_P ||
 629          slice_param->slice_type == SLICE_TYPE_SP) &&
 630         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 631         num_weight_offset_table = 1;
 632     }
 633
 634     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 635         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 636         num_weight_offset_table = 2;
 637     }
 638
 639     for (i = 0; i < num_weight_offset_table; i++) {
 640         BEGIN_BCS_BATCH(batch, 98);
 641         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 642         OUT_BCS_BATCH(batch, i);
 643
 644         if (i == 0) {
 645             for (j = 0; j < 32; j++) {
 646                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 647                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 648                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 649                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 650                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 651                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 652             }
 653         } else {
 654             for (j = 0; j < 32; j++) {
 655                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 656                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 657                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 658                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 659                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 660                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 661             }
 662         }
 663
 664         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 665         ADVANCE_BCS_BATCH(batch);
 666     }
 667 }
 668
 669 static void
 670 gen7_mfd_avc_bsd_object(VADriverContextP ctx,
 671                         VAPictureParameterBufferH264 *pic_param,
 672                         VASliceParameterBufferH264 *slice_param,
 673                         dri_bo *slice_data_bo,
 674                         VASliceParameterBufferH264 *next_slice_param,
 675                         struct gen7_mfd_context *gen7_mfd_context)
 676 {
 677     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 678     unsigned int slice_data_bit_offset;
 679
 680     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 681         slice_data_bo,
 682         slice_param,
 683         pic_param->pic_fields.bits.entropy_coding_mode_flag
 684     );
 685
 686     /* the input bitsteam format on GEN7 differs from GEN6 */
 687     BEGIN_BCS_BATCH(batch, 6);
 688     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 689     OUT_BCS_BATCH(batch,
 690                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 691     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 692     OUT_BCS_BATCH(batch,
 693                   (0 << 31) |
 694                   (0 << 14) |
 695                   (0 << 12) |
 696                   (0 << 10) |
 697                   (0 << 8));
 698     OUT_BCS_BATCH(batch,
 699                   ((slice_data_bit_offset >> 3) << 16) |
 700                   (1 << 7)  |
 701                   (0 << 5)  |
 702                   (0 << 4)  |
 703                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 704                   (slice_data_bit_offset & 0x7));
 705     OUT_BCS_BATCH(batch, 0);
 706     ADVANCE_BCS_BATCH(batch);
 707 }
 708
 709 static inline void
 710 gen7_mfd_avc_context_init(
 711     VADriverContextP         ctx,
 712     struct gen7_mfd_context *gen7_mfd_context
 713 )
 714 {
 715     /* Initialize flat scaling lists */
 716     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
 717 }
 718
 719 static void
 720 gen7_mfd_avc_decode_init(VADriverContextP ctx,
 721                          struct decode_state *decode_state,
 722                          struct gen7_mfd_context *gen7_mfd_context)
 723 {
 724     VAPictureParameterBufferH264 *pic_param;
 725     VASliceParameterBufferH264 *slice_param;
 726     struct i965_driver_data *i965 = i965_driver_data(ctx);
 727     struct object_surface *obj_surface;
 728     dri_bo *bo;
 729     int i, j, enable_avc_ildb = 0;
 730     unsigned int width_in_mbs, height_in_mbs;
 731
 732     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 733         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 734         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 735
 736         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 737             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 738             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 739                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 740                    (slice_param->slice_type == SLICE_TYPE_P) ||
 741                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 742                    (slice_param->slice_type == SLICE_TYPE_B));
 743
 744             if (slice_param->disable_deblocking_filter_idc != 1) {
 745                 enable_avc_ildb = 1;
 746                 break;
 747             }
 748
 749             slice_param++;
 750         }
 751     }
 752
 753     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 754     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 755     intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface);
 756     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 757     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 758     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
 759     assert(height_in_mbs > 0 && height_in_mbs <= 256);
 760
 761     /* Current decoded picture */
 762     obj_surface = decode_state->render_object;
 763     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
 764     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
 765
 766     avc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
 767     gen7_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 768
 769     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 770     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 771     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 772     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 773
 774     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 775     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 776     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 777     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 778
 779     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 780     bo = dri_bo_alloc(i965->intel.bufmgr,
 781                       "intra row store",
 782                       width_in_mbs * 64,
 783                       0x1000);
 784     assert(bo);
 785     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 786     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 787
 788     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 789     bo = dri_bo_alloc(i965->intel.bufmgr,
 790                       "deblocking filter row store",
 791                       width_in_mbs * 64 * 4,
 792                       0x1000);
 793     assert(bo);
 794     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 795     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 796
 797     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 798     bo = dri_bo_alloc(i965->intel.bufmgr,
 799                       "bsd mpc row store",
 800                       width_in_mbs * 64 * 2,
 801                       0x1000);
 802     assert(bo);
 803     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 804     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 805
 806     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 807     bo = dri_bo_alloc(i965->intel.bufmgr,
 808                       "mpr row store",
 809                       width_in_mbs * 64 * 2,
 810                       0x1000);
 811     assert(bo);
 812     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 813     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 814
 815     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 816 }
 817
 818 static void
 819 gen7_mfd_avc_decode_picture(VADriverContextP ctx,
 820                             struct decode_state *decode_state,
 821                             struct gen7_mfd_context *gen7_mfd_context)
 822 {
 823     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 824     VAPictureParameterBufferH264 *pic_param;
 825     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 826     dri_bo *slice_data_bo;
 827     int i, j;
 828
 829     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 830     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 831     gen7_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
 832
 833     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 834     intel_batchbuffer_emit_mi_flush(batch);
 835     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 836     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 837     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 838     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
 839     gen7_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
 840     gen7_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
 841
 842     for (j = 0; j < decode_state->num_slice_params; j++) {
 843         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 844         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 845         slice_data_bo = decode_state->slice_datas[j]->bo;
 846         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
 847
 848         if (j == decode_state->num_slice_params - 1)
 849             next_slice_group_param = NULL;
 850         else
 851             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 852
 853         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 854             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 855             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 856                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 857                    (slice_param->slice_type == SLICE_TYPE_P) ||
 858                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 859                    (slice_param->slice_type == SLICE_TYPE_B));
 860
 861             if (i < decode_state->slice_params[j]->num_elements - 1)
 862                 next_slice_param = slice_param + 1;
 863             else
 864                 next_slice_param = next_slice_group_param;
 865
 866             gen7_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
 867             gen7_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
 868             gen7_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
 869             gen7_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
 870             gen7_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
 871             slice_param++;
 872         }
 873     }
 874
 875     intel_batchbuffer_end_atomic(batch);
 876     intel_batchbuffer_flush(batch);
 877 }
 878
 879 static void
 880 gen7_mfd_mpeg2_decode_init(VADriverContextP ctx,
 881                            struct decode_state *decode_state,
 882                            struct gen7_mfd_context *gen7_mfd_context)
 883 {
 884     VAPictureParameterBufferMPEG2 *pic_param;
 885     struct i965_driver_data *i965 = i965_driver_data(ctx);
 886     struct object_surface *obj_surface;
 887     dri_bo *bo;
 888     unsigned int width_in_mbs;
 889
 890     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 891     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 892     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 893
 894     mpeg2_set_reference_surfaces(
 895         ctx,
 896         gen7_mfd_context->reference_surface,
 897         decode_state,
 898         pic_param
 899     );
 900
 901     /* Current decoded picture */
 902     obj_surface = decode_state->render_object;
 903     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
 904
 905     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 906     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 907     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 908     gen7_mfd_context->pre_deblocking_output.valid = 1;
 909
 910     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 911     bo = dri_bo_alloc(i965->intel.bufmgr,
 912                       "bsd mpc row store",
 913                       width_in_mbs * 96,
 914                       0x1000);
 915     assert(bo);
 916     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 917     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 918
 919     gen7_mfd_context->post_deblocking_output.valid = 0;
 920     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
 921     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
 922     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
 923     gen7_mfd_context->bitplane_read_buffer.valid = 0;
 924 }
 925
 926 static void
 927 gen7_mfd_mpeg2_pic_state(VADriverContextP ctx,
 928                          struct decode_state *decode_state,
 929                          struct gen7_mfd_context *gen7_mfd_context)
 930 {
 931     struct i965_driver_data * const i965 = i965_driver_data(ctx);
 932     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 933     VAPictureParameterBufferMPEG2 *pic_param;
 934     unsigned int slice_concealment_disable_bit = 0;
 935
 936     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 937     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 938
 939     if (IS_HASWELL(i965->intel.device_info)) {
 940         /* XXX: disable concealment for now */
 941         slice_concealment_disable_bit = 1;
 942     }
 943
 944     BEGIN_BCS_BATCH(batch, 13);
 945     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
 946     OUT_BCS_BATCH(batch,
 947                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
 948                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
 949                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
 950                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
 951                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
 952                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
 953                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
 954                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
 955                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
 956                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
 957                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
 958                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
 959     OUT_BCS_BATCH(batch,
 960                   pic_param->picture_coding_type << 9);
 961     OUT_BCS_BATCH(batch,
 962                   (slice_concealment_disable_bit << 31) |
 963                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
 964                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
 965     OUT_BCS_BATCH(batch, 0);
 966     OUT_BCS_BATCH(batch, 0);
 967     OUT_BCS_BATCH(batch, 0);
 968     OUT_BCS_BATCH(batch, 0);
 969     OUT_BCS_BATCH(batch, 0);
 970     OUT_BCS_BATCH(batch, 0);
 971     OUT_BCS_BATCH(batch, 0);
 972     OUT_BCS_BATCH(batch, 0);
 973     OUT_BCS_BATCH(batch, 0);
 974     ADVANCE_BCS_BATCH(batch);
 975 }
 976
 977 static void
 978 gen7_mfd_mpeg2_qm_state(VADriverContextP ctx,
 979                         struct decode_state *decode_state,
 980                         struct gen7_mfd_context *gen7_mfd_context)
 981 {
 982     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
 983     int i, j;
 984
 985     /* Update internal QM state */
 986     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
 987         VAIQMatrixBufferMPEG2 * const iq_matrix =
 988             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
 989
 990         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
 991             iq_matrix->load_intra_quantiser_matrix) {
 992             gen_iq_matrix->load_intra_quantiser_matrix =
 993                 iq_matrix->load_intra_quantiser_matrix;
 994             if (iq_matrix->load_intra_quantiser_matrix) {
 995                 for (j = 0; j < 64; j++)
 996                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
 997                         iq_matrix->intra_quantiser_matrix[j];
 998             }
 999         }
1000
1001         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1002             iq_matrix->load_non_intra_quantiser_matrix) {
1003             gen_iq_matrix->load_non_intra_quantiser_matrix =
1004                 iq_matrix->load_non_intra_quantiser_matrix;
1005             if (iq_matrix->load_non_intra_quantiser_matrix) {
1006                 for (j = 0; j < 64; j++)
1007                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1008                         iq_matrix->non_intra_quantiser_matrix[j];
1009             }
1010         }
1011     }
1012
1013     /* Commit QM state to HW */
1014     for (i = 0; i < 2; i++) {
1015         unsigned char *qm = NULL;
1016         int qm_type;
1017
1018         if (i == 0) {
1019             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1020                 qm = gen_iq_matrix->intra_quantiser_matrix;
1021                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1022             }
1023         } else {
1024             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1025                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1026                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1027             }
1028         }
1029
1030         if (!qm)
1031             continue;
1032
1033         gen7_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1034     }
1035 }
1036
1037 uint32_t mpeg2_get_slice_data_length(dri_bo *slice_data_bo, VASliceParameterBufferMPEG2 *slice_param)
1038 {
1039     uint8_t *buf;
1040     uint32_t buf_offset = slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3);
1041     uint32_t buf_size = slice_param->slice_data_size - (slice_param->macroblock_offset >> 3);
1042     uint32_t i;
1043
1044     dri_bo_map(slice_data_bo, 0);
1045     buf = (uint8_t *)slice_data_bo->virtual + buf_offset;
1046
1047     for (i = 3; i < buf_size; i++) {
1048         if (buf[i - 3] &&
1049             !buf[i - 2] &&
1050             !buf[i - 1] &&
1051             !buf[i]) {
1052             dri_bo_unmap(slice_data_bo);
1053             return i - 3 + 1;
1054         }
1055     }
1056
1057     dri_bo_unmap(slice_data_bo);
1058     return buf_size;
1059 }
1060
1061 static void
1062 gen7_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1063                           VAPictureParameterBufferMPEG2 *pic_param,
1064                           VASliceParameterBufferMPEG2 *slice_param,
1065                           dri_bo *slice_data_bo,
1066                           VASliceParameterBufferMPEG2 *next_slice_param,
1067                           struct gen7_mfd_context *gen7_mfd_context)
1068 {
1069     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1070     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1071     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1072     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1073
1074     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1075         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1076         is_field_pic = 1;
1077     is_field_pic_wa = is_field_pic &&
1078         gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1079
1080     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1081     hpos0 = slice_param->slice_horizontal_position;
1082
1083     if (next_slice_param == NULL) {
1084         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1085         hpos1 = 0;
1086     } else {
1087         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1088         hpos1 = next_slice_param->slice_horizontal_position;
1089     }
1090
1091     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1092
1093     BEGIN_BCS_BATCH(batch, 5);
1094     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1095     OUT_BCS_BATCH(batch,
1096                   mpeg2_get_slice_data_length(slice_data_bo, slice_param));
1097     OUT_BCS_BATCH(batch,
1098                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1099     OUT_BCS_BATCH(batch,
1100                   hpos0 << 24 |
1101                   vpos0 << 16 |
1102                   mb_count << 8 |
1103                   (next_slice_param == NULL) << 5 |
1104                   (next_slice_param == NULL) << 3 |
1105                   (slice_param->macroblock_offset & 0x7));
1106     OUT_BCS_BATCH(batch,
1107                   (slice_param->quantiser_scale_code << 24) |
1108                   (IS_HASWELL(i965->intel.device_info) ? (vpos1 << 8 | hpos1) : 0));
1109     ADVANCE_BCS_BATCH(batch);
1110 }
1111
1112 static void
1113 gen7_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1114                               struct decode_state *decode_state,
1115                               struct gen7_mfd_context *gen7_mfd_context)
1116 {
1117     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1118     VAPictureParameterBufferMPEG2 *pic_param;
1119     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1120     dri_bo *slice_data_bo;
1121     int i, j;
1122
1123     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1124     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1125
1126     gen7_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1127     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1128     intel_batchbuffer_emit_mi_flush(batch);
1129     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1130     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1131     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1132     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1133     gen7_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1134     gen7_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1135
1136     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1137         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1138             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1139
1140     for (j = 0; j < decode_state->num_slice_params; j++) {
1141         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1142         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1143         slice_data_bo = decode_state->slice_datas[j]->bo;
1144         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1145
1146         if (j == decode_state->num_slice_params - 1)
1147             next_slice_group_param = NULL;
1148         else
1149             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1150
1151         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1152             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1153
1154             if (i < decode_state->slice_params[j]->num_elements - 1)
1155                 next_slice_param = slice_param + 1;
1156             else
1157                 next_slice_param = next_slice_group_param;
1158
1159             gen7_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1160             slice_param++;
1161         }
1162     }
1163
1164     intel_batchbuffer_end_atomic(batch);
1165     intel_batchbuffer_flush(batch);
1166 }
1167
1168 static const int va_to_gen7_vc1_pic_type[5] = {
1169     GEN7_VC1_I_PICTURE,
1170     GEN7_VC1_P_PICTURE,
1171     GEN7_VC1_B_PICTURE,
1172     GEN7_VC1_BI_PICTURE,
1173     GEN7_VC1_P_PICTURE,
1174 };
1175
1176 static const int va_to_gen7_vc1_mv[4] = {
1177     1, /* 1-MV */
1178     2, /* 1-MV half-pel */
1179     3, /* 1-MV half-pef bilinear */
1180     0, /* Mixed MV */
1181 };
1182
1183 static const int b_picture_scale_factor[21] = {
1184     128, 85,  170, 64,  192,
1185     51,  102, 153, 204, 43,
1186     215, 37,  74,  111, 148,
1187     185, 222, 32,  96,  160,
1188     224,
1189 };
1190
1191 static const int va_to_gen7_vc1_condover[3] = {
1192     0,
1193     2,
1194     3
1195 };
1196
1197 static const int va_to_gen7_vc1_profile[4] = {
1198     GEN7_VC1_SIMPLE_PROFILE,
1199     GEN7_VC1_MAIN_PROFILE,
1200     GEN7_VC1_RESERVED_PROFILE,
1201     GEN7_VC1_ADVANCED_PROFILE
1202 };
1203
1204 static void
1205 gen7_mfd_free_vc1_surface(void **data)
1206 {
1207     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1208
1209     if (!gen7_vc1_surface)
1210         return;
1211
1212     dri_bo_unreference(gen7_vc1_surface->dmv);
1213     free(gen7_vc1_surface);
1214     *data = NULL;
1215 }
1216
1217 static void
1218 gen7_mfd_init_vc1_surface(VADriverContextP ctx,
1219                           VAPictureParameterBufferVC1 *pic_param,
1220                           struct object_surface *obj_surface)
1221 {
1222     struct i965_driver_data *i965 = i965_driver_data(ctx);
1223     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1224     int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1225     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1226
1227     obj_surface->free_private_data = gen7_mfd_free_vc1_surface;
1228
1229     if (!gen7_vc1_surface) {
1230         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1231         assert((obj_surface->size & 0x3f) == 0);
1232         obj_surface->private_data = gen7_vc1_surface;
1233     }
1234
1235     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1236
1237     if (gen7_vc1_surface->dmv == NULL) {
1238         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1239                                              "direct mv w/r buffer",
1240                                              width_in_mbs * height_in_mbs * 64,
1241                                              0x1000);
1242     }
1243 }
1244
1245 static void
1246 gen7_mfd_vc1_decode_init(VADriverContextP ctx,
1247                          struct decode_state *decode_state,
1248                          struct gen7_mfd_context *gen7_mfd_context)
1249 {
1250     VAPictureParameterBufferVC1 *pic_param;
1251     struct i965_driver_data *i965 = i965_driver_data(ctx);
1252     struct object_surface *obj_surface;
1253     dri_bo *bo;
1254     int width_in_mbs;
1255     int picture_type;
1256
1257     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1258     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1259     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1260     picture_type = pic_param->picture_fields.bits.picture_type;
1261
1262     intel_update_vc1_frame_store_index(ctx,
1263                                        decode_state,
1264                                        pic_param,
1265                                        gen7_mfd_context->reference_surface);
1266
1267     /* Current decoded picture */
1268     obj_surface = decode_state->render_object;
1269     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1270     gen7_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1271
1272     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1273     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1274     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1275     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1276
1277     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1278     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1279     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1280     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1281
1282     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1283     bo = dri_bo_alloc(i965->intel.bufmgr,
1284                       "intra row store",
1285                       width_in_mbs * 64,
1286                       0x1000);
1287     assert(bo);
1288     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1289     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1290
1291     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1292     bo = dri_bo_alloc(i965->intel.bufmgr,
1293                       "deblocking filter row store",
1294                       width_in_mbs * 7 * 64,
1295                       0x1000);
1296     assert(bo);
1297     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1298     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1299
1300     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1301     bo = dri_bo_alloc(i965->intel.bufmgr,
1302                       "bsd mpc row store",
1303                       width_in_mbs * 96,
1304                       0x1000);
1305     assert(bo);
1306     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1307     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1308
1309     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1310
1311     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1312     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1313
1314     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1315         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1316         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1317         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1318         int src_w, src_h;
1319         uint8_t *src = NULL, *dst = NULL;
1320
1321         assert(decode_state->bit_plane->buffer);
1322         src = decode_state->bit_plane->buffer;
1323
1324         bo = dri_bo_alloc(i965->intel.bufmgr,
1325                           "VC-1 Bitplane",
1326                           bitplane_width * height_in_mbs,
1327                           0x1000);
1328         assert(bo);
1329         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1330
1331         dri_bo_map(bo, True);
1332         assert(bo->virtual);
1333         dst = bo->virtual;
1334
1335         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1336             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1337                 int src_index, dst_index;
1338                 int src_shift;
1339                 uint8_t src_value;
1340
1341                 src_index = (src_h * width_in_mbs + src_w) / 2;
1342                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1343                 src_value = ((src[src_index] >> src_shift) & 0xf);
1344
1345                 if (picture_type == GEN7_VC1_SKIPPED_PICTURE){
1346                     src_value |= 0x2;
1347                 }
1348
1349                 dst_index = src_w / 2;
1350                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1351             }
1352
1353             if (src_w & 1)
1354                 dst[src_w / 2] >>= 4;
1355
1356             dst += bitplane_width;
1357         }
1358
1359         dri_bo_unmap(bo);
1360     } else
1361         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1362 }
1363
1364 static void
1365 gen7_mfd_vc1_pic_state(VADriverContextP ctx,
1366                        struct decode_state *decode_state,
1367                        struct gen7_mfd_context *gen7_mfd_context)
1368 {
1369     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1370     VAPictureParameterBufferVC1 *pic_param;
1371     struct object_surface *obj_surface;
1372     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1373     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1374     int unified_mv_mode;
1375     int ref_field_pic_polarity = 0;
1376     int scale_factor = 0;
1377     int trans_ac_y = 0;
1378     int dmv_surface_valid = 0;
1379     int brfd = 0;
1380     int fcm = 0;
1381     int picture_type;
1382     int profile;
1383     int overlap;
1384     int interpolation_mode = 0;
1385
1386     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1387     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1388
1389     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1390     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1391     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1392     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1393     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1394     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1395     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1396     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1397
1398     if (dquant == 0) {
1399         alt_pquant_config = 0;
1400         alt_pquant_edge_mask = 0;
1401     } else if (dquant == 2) {
1402         alt_pquant_config = 1;
1403         alt_pquant_edge_mask = 0xf;
1404     } else {
1405         assert(dquant == 1);
1406         if (dquantfrm == 0) {
1407             alt_pquant_config = 0;
1408             alt_pquant_edge_mask = 0;
1409             alt_pq = 0;
1410         } else {
1411             assert(dquantfrm == 1);
1412             alt_pquant_config = 1;
1413
1414             switch (dqprofile) {
1415             case 3:
1416                 if (dqbilevel == 0) {
1417                     alt_pquant_config = 2;
1418                     alt_pquant_edge_mask = 0;
1419                 } else {
1420                     assert(dqbilevel == 1);
1421                     alt_pquant_config = 3;
1422                     alt_pquant_edge_mask = 0;
1423                 }
1424                 break;
1425
1426             case 0:
1427                 alt_pquant_edge_mask = 0xf;
1428                 break;
1429
1430             case 1:
1431                 if (dqdbedge == 3)
1432                     alt_pquant_edge_mask = 0x9;
1433                 else
1434                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1435
1436                 break;
1437
1438             case 2:
1439                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1440                 break;
1441
1442             default:
1443                 assert(0);
1444             }
1445         }
1446     }
1447
1448     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1449         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1450         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1451     } else {
1452         assert(pic_param->mv_fields.bits.mv_mode < 4);
1453         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1454     }
1455
1456     if (pic_param->sequence_fields.bits.interlace == 1 &&
1457         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1458         /* FIXME: calculate reference field picture polarity */
1459         assert(0);
1460         ref_field_pic_polarity = 0;
1461     }
1462
1463     if (pic_param->b_picture_fraction < 21)
1464         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1465
1466     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1467
1468     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1469         picture_type == GEN7_VC1_I_PICTURE)
1470         picture_type = GEN7_VC1_BI_PICTURE;
1471
1472     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1473         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1474     else {
1475         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1476         /*
1477          * 8.3.6.2.1 Transform Type Selection
1478          * If variable-sized transform coding is not enabled,
1479          * then the 8x8 transform shall be used for all blocks.
1480          * it is also MFX_VC1_PIC_STATE requirement.
1481          */
1482         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1483             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1484             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1485         }
1486     }
1487
1488
1489     if (picture_type == GEN7_VC1_B_PICTURE) {
1490         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1491
1492         obj_surface = decode_state->reference_objects[1];
1493
1494         if (obj_surface)
1495             gen7_vc1_surface = obj_surface->private_data;
1496
1497         if (!gen7_vc1_surface ||
1498             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1499              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1500             dmv_surface_valid = 0;
1501         else
1502             dmv_surface_valid = 1;
1503     }
1504
1505     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1506
1507     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1508         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1509     else {
1510         if (pic_param->picture_fields.bits.top_field_first)
1511             fcm = 2;
1512         else
1513             fcm = 3;
1514     }
1515
1516     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1517         brfd = pic_param->reference_fields.bits.reference_distance;
1518         brfd = (scale_factor * brfd) >> 8;
1519         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1520
1521         if (brfd < 0)
1522             brfd = 0;
1523     }
1524
1525     overlap = 0;
1526     if (profile != GEN7_VC1_ADVANCED_PROFILE){
1527         if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1528             pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) {
1529             overlap = 1;
1530         }
1531     }else {
1532         if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE &&
1533              pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1534               overlap = 1;
1535         }
1536         if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE ||
1537             pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){
1538              if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1539                 overlap = 1;
1540              } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1541                         va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1542                  overlap = 1;
1543              }
1544         }
1545     }
1546
1547     assert(pic_param->conditional_overlap_flag < 3);
1548     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1549
1550     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1551         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1552          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1553         interpolation_mode = 9; /* Half-pel bilinear */
1554     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1555              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1556               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1557         interpolation_mode = 1; /* Half-pel bicubic */
1558     else
1559         interpolation_mode = 0; /* Quarter-pel bicubic */
1560
1561     BEGIN_BCS_BATCH(batch, 6);
1562     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1563     OUT_BCS_BATCH(batch,
1564                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1565                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1566     OUT_BCS_BATCH(batch,
1567                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1568                   dmv_surface_valid << 15 |
1569                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1570                   pic_param->rounding_control << 13 |
1571                   pic_param->sequence_fields.bits.syncmarker << 12 |
1572                   interpolation_mode << 8 |
1573                   0 << 7 | /* FIXME: scale up or down ??? */
1574                   pic_param->range_reduction_frame << 6 |
1575                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
1576                   overlap << 4 |
1577                   !pic_param->picture_fields.bits.is_first_field << 3 |
1578                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1579     OUT_BCS_BATCH(batch,
1580                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1581                   picture_type << 26 |
1582                   fcm << 24 |
1583                   alt_pq << 16 |
1584                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1585                   scale_factor << 0);
1586     OUT_BCS_BATCH(batch,
1587                   unified_mv_mode << 28 |
1588                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1589                   pic_param->fast_uvmc_flag << 26 |
1590                   ref_field_pic_polarity << 25 |
1591                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1592                   pic_param->reference_fields.bits.reference_distance << 20 |
1593                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1594                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1595                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1596                   alt_pquant_edge_mask << 4 |
1597                   alt_pquant_config << 2 |
1598                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1599                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1600     OUT_BCS_BATCH(batch,
1601                   !!pic_param->bitplane_present.value << 31 |
1602                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
1603                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
1604                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
1605                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
1606                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
1607                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
1608                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
1609                   pic_param->mv_fields.bits.mv_table << 20 |
1610                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1611                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1612                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1613                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1614                   pic_param->mb_mode_table << 8 |
1615                   trans_ac_y << 6 |
1616                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1617                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1618                   pic_param->cbp_table << 0);
1619     ADVANCE_BCS_BATCH(batch);
1620 }
1621
1622 static void
1623 gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1624                              struct decode_state *decode_state,
1625                              struct gen7_mfd_context *gen7_mfd_context)
1626 {
1627     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1628     VAPictureParameterBufferVC1 *pic_param;
1629     int intensitycomp_single;
1630
1631     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1632     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1633
1634     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1635     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1636     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1637
1638     BEGIN_BCS_BATCH(batch, 6);
1639     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1640     OUT_BCS_BATCH(batch,
1641                   0 << 14 | /* FIXME: double ??? */
1642                   0 << 12 |
1643                   intensitycomp_single << 10 |
1644                   intensitycomp_single << 8 |
1645                   0 << 4 | /* FIXME: interlace mode */
1646                   0);
1647     OUT_BCS_BATCH(batch,
1648                   pic_param->luma_shift << 16 |
1649                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1650     OUT_BCS_BATCH(batch, 0);
1651     OUT_BCS_BATCH(batch, 0);
1652     OUT_BCS_BATCH(batch, 0);
1653     ADVANCE_BCS_BATCH(batch);
1654 }
1655
1656
1657 static void
1658 gen7_mfd_vc1_directmode_state(VADriverContextP ctx,
1659                               struct decode_state *decode_state,
1660                               struct gen7_mfd_context *gen7_mfd_context)
1661 {
1662     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1663     struct object_surface *obj_surface;
1664     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1665
1666     obj_surface = decode_state->render_object;
1667
1668     if (obj_surface && obj_surface->private_data) {
1669         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1670     }
1671
1672     obj_surface = decode_state->reference_objects[1];
1673
1674     if (obj_surface && obj_surface->private_data) {
1675         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1676     }
1677
1678     BEGIN_BCS_BATCH(batch, 3);
1679     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1680
1681     if (dmv_write_buffer)
1682         OUT_BCS_RELOC(batch, dmv_write_buffer,
1683                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1684                       0);
1685     else
1686         OUT_BCS_BATCH(batch, 0);
1687
1688     if (dmv_read_buffer)
1689         OUT_BCS_RELOC(batch, dmv_read_buffer,
1690                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1691                       0);
1692     else
1693         OUT_BCS_BATCH(batch, 0);
1694
1695     ADVANCE_BCS_BATCH(batch);
1696 }
1697
1698 static int
1699 gen7_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1700 {
1701     int out_slice_data_bit_offset;
1702     int slice_header_size = in_slice_data_bit_offset / 8;
1703     int i, j;
1704
1705     if (profile != 3)
1706         out_slice_data_bit_offset = in_slice_data_bit_offset;
1707     else {
1708         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1709             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1710                 i++, j += 2;
1711             }
1712         }
1713
1714         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1715     }
1716
1717     return out_slice_data_bit_offset;
1718 }
1719
1720 static void
1721 gen7_mfd_vc1_bsd_object(VADriverContextP ctx,
1722                         VAPictureParameterBufferVC1 *pic_param,
1723                         VASliceParameterBufferVC1 *slice_param,
1724                         VASliceParameterBufferVC1 *next_slice_param,
1725                         dri_bo *slice_data_bo,
1726                         struct gen7_mfd_context *gen7_mfd_context)
1727 {
1728     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1729     int next_slice_start_vert_pos;
1730     int macroblock_offset;
1731     uint8_t *slice_data = NULL;
1732
1733     dri_bo_map(slice_data_bo, 0);
1734     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1735     macroblock_offset = gen7_mfd_vc1_get_macroblock_bit_offset(slice_data,
1736                                                                slice_param->macroblock_offset,
1737                                                                pic_param->sequence_fields.bits.profile);
1738     dri_bo_unmap(slice_data_bo);
1739
1740     if (next_slice_param)
1741         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1742     else
1743         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1744
1745     BEGIN_BCS_BATCH(batch, 5);
1746     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1747     OUT_BCS_BATCH(batch,
1748                   slice_param->slice_data_size - (macroblock_offset >> 3));
1749     OUT_BCS_BATCH(batch,
1750                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1751     OUT_BCS_BATCH(batch,
1752                   slice_param->slice_vertical_position << 16 |
1753                   next_slice_start_vert_pos << 0);
1754     OUT_BCS_BATCH(batch,
1755                   (macroblock_offset & 0x7));
1756     ADVANCE_BCS_BATCH(batch);
1757 }
1758
1759 static void
1760 gen7_mfd_vc1_decode_picture(VADriverContextP ctx,
1761                             struct decode_state *decode_state,
1762                             struct gen7_mfd_context *gen7_mfd_context)
1763 {
1764     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1765     VAPictureParameterBufferVC1 *pic_param;
1766     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1767     dri_bo *slice_data_bo;
1768     int i, j;
1769
1770     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1771     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1772
1773     gen7_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1774     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1775     intel_batchbuffer_emit_mi_flush(batch);
1776     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1777     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1778     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1779     gen7_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1780     gen7_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1781     gen7_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1782     gen7_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1783
1784     for (j = 0; j < decode_state->num_slice_params; j++) {
1785         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1786         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1787         slice_data_bo = decode_state->slice_datas[j]->bo;
1788         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1789
1790         if (j == decode_state->num_slice_params - 1)
1791             next_slice_group_param = NULL;
1792         else
1793             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1794
1795         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1796             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1797
1798             if (i < decode_state->slice_params[j]->num_elements - 1)
1799                 next_slice_param = slice_param + 1;
1800             else
1801                 next_slice_param = next_slice_group_param;
1802
1803             gen7_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1804             slice_param++;
1805         }
1806     }
1807
1808     intel_batchbuffer_end_atomic(batch);
1809     intel_batchbuffer_flush(batch);
1810 }
1811
1812 static void
1813 gen7_mfd_jpeg_decode_init(VADriverContextP ctx,
1814                           struct decode_state *decode_state,
1815                           struct gen7_mfd_context *gen7_mfd_context)
1816 {
1817     struct object_surface *obj_surface;
1818     VAPictureParameterBufferJPEGBaseline *pic_param;
1819     int subsampling = SUBSAMPLE_YUV420;
1820     int fourcc = VA_FOURCC_IMC3;
1821
1822     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1823
1824     if (pic_param->num_components == 1) {
1825         subsampling = SUBSAMPLE_YUV400;
1826         fourcc = VA_FOURCC_Y800;
1827     } else if (pic_param->num_components == 3) {
1828         int h1 = pic_param->components[0].h_sampling_factor;
1829         int h2 = pic_param->components[1].h_sampling_factor;
1830         int h3 = pic_param->components[2].h_sampling_factor;
1831         int v1 = pic_param->components[0].v_sampling_factor;
1832         int v2 = pic_param->components[1].v_sampling_factor;
1833         int v3 = pic_param->components[2].v_sampling_factor;
1834
1835         if (h1 == 2 && h2 == 1 && h3 == 1 &&
1836             v1 == 2 && v2 == 1 && v3 == 1) {
1837             subsampling = SUBSAMPLE_YUV420;
1838             fourcc = VA_FOURCC_IMC3;
1839         } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1840                    v1 == 1 && v2 == 1 && v3 == 1) {
1841             subsampling = SUBSAMPLE_YUV422H;
1842             fourcc = VA_FOURCC_422H;
1843         } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1844                    v1 == 1 && v2 == 1 && v3 == 1) {
1845             subsampling = SUBSAMPLE_YUV444;
1846             fourcc = VA_FOURCC_444P;
1847         } else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1848                    v1 == 1 && v2 == 1 && v3 == 1) {
1849             subsampling = SUBSAMPLE_YUV411;
1850             fourcc = VA_FOURCC_411P;
1851         } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1852                    v1 == 2 && v2 == 1 && v3 == 1) {
1853             subsampling = SUBSAMPLE_YUV422V;
1854             fourcc = VA_FOURCC_422V;
1855         } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1856                    v1 == 2 && v2 == 2 && v3 == 2) {
1857             subsampling = SUBSAMPLE_YUV422H;
1858             fourcc = VA_FOURCC_422H;
1859         } else if (h2 == 2 && h2 == 2 && h3 == 2 &&
1860                    v1 == 2 && v2 == 1 && v3 == 1) {
1861             subsampling = SUBSAMPLE_YUV422V;
1862             fourcc = VA_FOURCC_422V;
1863         } else
1864             assert(0);
1865     } else {
1866         assert(0);
1867     }
1868
1869     /* Current decoded picture */
1870     obj_surface = decode_state->render_object;
1871     i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
1872
1873     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1874     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1875     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1876     gen7_mfd_context->pre_deblocking_output.valid = 1;
1877
1878     gen7_mfd_context->post_deblocking_output.bo = NULL;
1879     gen7_mfd_context->post_deblocking_output.valid = 0;
1880
1881     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1882     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1883
1884     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1885     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1886
1887     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1888     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
1889
1890     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1891     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1892
1893     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1894     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1895 }
1896
1897 static const int va_to_gen7_jpeg_rotation[4] = {
1898     GEN7_JPEG_ROTATION_0,
1899     GEN7_JPEG_ROTATION_90,
1900     GEN7_JPEG_ROTATION_180,
1901     GEN7_JPEG_ROTATION_270
1902 };
1903
1904 static void
1905 gen7_mfd_jpeg_pic_state(VADriverContextP ctx,
1906                         struct decode_state *decode_state,
1907                         struct gen7_mfd_context *gen7_mfd_context)
1908 {
1909     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1910     VAPictureParameterBufferJPEGBaseline *pic_param;
1911     int chroma_type = GEN7_YUV420;
1912     int frame_width_in_blks;
1913     int frame_height_in_blks;
1914
1915     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1916     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1917
1918     if (pic_param->num_components == 1)
1919         chroma_type = GEN7_YUV400;
1920     else if (pic_param->num_components == 3) {
1921         int h1 = pic_param->components[0].h_sampling_factor;
1922         int h2 = pic_param->components[1].h_sampling_factor;
1923         int h3 = pic_param->components[2].h_sampling_factor;
1924         int v1 = pic_param->components[0].v_sampling_factor;
1925         int v2 = pic_param->components[1].v_sampling_factor;
1926         int v3 = pic_param->components[2].v_sampling_factor;
1927
1928         if (h1 == 2 && h2 == 1 && h3 == 1 &&
1929             v1 == 2 && v2 == 1 && v3 == 1)
1930             chroma_type = GEN7_YUV420;
1931         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1932                  v1 == 1 && v2 == 1 && v3 == 1)
1933             chroma_type = GEN7_YUV422H_2Y;
1934         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1935                  v1 == 1 && v2 == 1 && v3 == 1)
1936             chroma_type = GEN7_YUV444;
1937         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1938                  v1 == 1 && v2 == 1 && v3 == 1)
1939             chroma_type = GEN7_YUV411;
1940         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1941                  v1 == 2 && v2 == 1 && v3 == 1)
1942             chroma_type = GEN7_YUV422V_2Y;
1943         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1944                  v1 == 2 && v2 == 2 && v3 == 2)
1945             chroma_type = GEN7_YUV422H_4Y;
1946         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
1947                  v1 == 2 && v2 == 1 && v3 == 1)
1948             chroma_type = GEN7_YUV422V_4Y;
1949         else
1950             assert(0);
1951     }
1952
1953     if (chroma_type == GEN7_YUV400 ||
1954         chroma_type == GEN7_YUV444 ||
1955         chroma_type == GEN7_YUV422V_2Y) {
1956         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
1957         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
1958     } else if (chroma_type == GEN7_YUV411) {
1959         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
1960         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
1961     } else {
1962         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
1963         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
1964     }
1965
1966     BEGIN_BCS_BATCH(batch, 3);
1967     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
1968     OUT_BCS_BATCH(batch,
1969                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
1970                   (chroma_type << 0));
1971     OUT_BCS_BATCH(batch,
1972                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
1973                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
1974     ADVANCE_BCS_BATCH(batch);
1975 }
1976
1977 static const int va_to_gen7_jpeg_hufftable[2] = {
1978     MFX_HUFFTABLE_ID_Y,
1979     MFX_HUFFTABLE_ID_UV
1980 };
1981
1982 static void
1983 gen7_mfd_jpeg_huff_table_state(VADriverContextP ctx,
1984                                struct decode_state *decode_state,
1985                                struct gen7_mfd_context *gen7_mfd_context,
1986                                int num_tables)
1987 {
1988     VAHuffmanTableBufferJPEGBaseline *huffman_table;
1989     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1990     int index;
1991
1992     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
1993         return;
1994
1995     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
1996
1997     for (index = 0; index < num_tables; index++) {
1998         int id = va_to_gen7_jpeg_hufftable[index];
1999         if (!huffman_table->load_huffman_table[index])
2000             continue;
2001         BEGIN_BCS_BATCH(batch, 53);
2002         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2003         OUT_BCS_BATCH(batch, id);
2004         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2005         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2006         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2007         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2008         ADVANCE_BCS_BATCH(batch);
2009     }
2010 }
2011
2012 static const int va_to_gen7_jpeg_qm[5] = {
2013     -1,
2014     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2015     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2016     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2017     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2018 };
2019
2020 static void
2021 gen7_mfd_jpeg_qm_state(VADriverContextP ctx,
2022                        struct decode_state *decode_state,
2023                        struct gen7_mfd_context *gen7_mfd_context)
2024 {
2025     VAPictureParameterBufferJPEGBaseline *pic_param;
2026     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2027     int index;
2028
2029     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2030         return;
2031
2032     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2033     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2034
2035     assert(pic_param->num_components <= 3);
2036
2037     for (index = 0; index < pic_param->num_components; index++) {
2038         int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2039         int qm_type;
2040         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2041         unsigned char raster_qm[64];
2042         int j;
2043
2044         if (id > 4 || id < 1)
2045             continue;
2046
2047         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2048             continue;
2049
2050         qm_type = va_to_gen7_jpeg_qm[id];
2051
2052         for (j = 0; j < 64; j++)
2053             raster_qm[zigzag_direct[j]] = qm[j];
2054
2055         gen7_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2056     }
2057 }
2058
2059 static void
2060 gen7_mfd_jpeg_bsd_object(VADriverContextP ctx,
2061                          VAPictureParameterBufferJPEGBaseline *pic_param,
2062                          VASliceParameterBufferJPEGBaseline *slice_param,
2063                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2064                          dri_bo *slice_data_bo,
2065                          struct gen7_mfd_context *gen7_mfd_context)
2066 {
2067     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2068     int scan_component_mask = 0;
2069     int i;
2070
2071     assert(slice_param->num_components > 0);
2072     assert(slice_param->num_components < 4);
2073     assert(slice_param->num_components <= pic_param->num_components);
2074
2075     for (i = 0; i < slice_param->num_components; i++) {
2076         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2077         case 1:
2078             scan_component_mask |= (1 << 0);
2079             break;
2080         case 2:
2081             scan_component_mask |= (1 << 1);
2082             break;
2083         case 3:
2084             scan_component_mask |= (1 << 2);
2085             break;
2086         default:
2087             assert(0);
2088             break;
2089         }
2090     }
2091
2092     BEGIN_BCS_BATCH(batch, 6);
2093     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2094     OUT_BCS_BATCH(batch,
2095                   slice_param->slice_data_size);
2096     OUT_BCS_BATCH(batch,
2097                   slice_param->slice_data_offset);
2098     OUT_BCS_BATCH(batch,
2099                   slice_param->slice_horizontal_position << 16 |
2100                   slice_param->slice_vertical_position << 0);
2101     OUT_BCS_BATCH(batch,
2102                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2103                   (scan_component_mask << 27) |                 /* scan components */
2104                   (0 << 26) |   /* disable interrupt allowed */
2105                   (slice_param->num_mcus << 0));                /* MCU count */
2106     OUT_BCS_BATCH(batch,
2107                   (slice_param->restart_interval << 0));    /* RestartInterval */
2108     ADVANCE_BCS_BATCH(batch);
2109 }
2110
2111 /* Workaround for JPEG decoding on Ivybridge */
2112
2113 VAStatus
2114 i965_CreateSurfaces(VADriverContextP ctx,
2115                     int width,
2116                     int height,
2117                     int format,
2118                     int num_surfaces,
2119                     VASurfaceID *surfaces);
2120
2121 static struct {
2122     int width;
2123     int height;
2124     unsigned char data[32];
2125     int data_size;
2126     int data_bit_offset;
2127     int qp;
2128 } gen7_jpeg_wa_clip = {
2129     16,
2130     16,
2131     {
2132         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2133         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2134     },
2135     14,
2136     40,
2137     28,
2138 };
2139
2140 static void
2141 gen7_jpeg_wa_init(VADriverContextP ctx,
2142                   struct gen7_mfd_context *gen7_mfd_context)
2143 {
2144     struct i965_driver_data *i965 = i965_driver_data(ctx);
2145     VAStatus status;
2146     struct object_surface *obj_surface;
2147
2148     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2149         i965_DestroySurfaces(ctx,
2150                              &gen7_mfd_context->jpeg_wa_surface_id,
2151                              1);
2152
2153     status = i965_CreateSurfaces(ctx,
2154                                  gen7_jpeg_wa_clip.width,
2155                                  gen7_jpeg_wa_clip.height,
2156                                  VA_RT_FORMAT_YUV420,
2157                                  1,
2158                                  &gen7_mfd_context->jpeg_wa_surface_id);
2159     assert(status == VA_STATUS_SUCCESS);
2160
2161     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2162     assert(obj_surface);
2163     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2164     gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2165
2166     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2167         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2168                                                                "JPEG WA data",
2169                                                                0x1000,
2170                                                                0x1000);
2171         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2172                        0,
2173                        gen7_jpeg_wa_clip.data_size,
2174                        gen7_jpeg_wa_clip.data);
2175     }
2176 }
2177
2178 static void
2179 gen7_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2180                               struct gen7_mfd_context *gen7_mfd_context)
2181 {
2182     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2183
2184     BEGIN_BCS_BATCH(batch, 5);
2185     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2186     OUT_BCS_BATCH(batch,
2187                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2188                   (MFD_MODE_VLD << 15) | /* VLD mode */
2189                   (0 << 10) | /* disable Stream-Out */
2190                   (0 << 9)  | /* Post Deblocking Output */
2191                   (1 << 8)  | /* Pre Deblocking Output */
2192                   (0 << 5)  | /* not in stitch mode */
2193                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2194                   (MFX_FORMAT_AVC << 0));
2195     OUT_BCS_BATCH(batch,
2196                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2197                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2198                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2199                   (0 << 1)  |
2200                   (0 << 0));
2201     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2202     OUT_BCS_BATCH(batch, 0); /* reserved */
2203     ADVANCE_BCS_BATCH(batch);
2204 }
2205
2206 static void
2207 gen7_jpeg_wa_surface_state(VADriverContextP ctx,
2208                            struct gen7_mfd_context *gen7_mfd_context)
2209 {
2210     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2211     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2212
2213     BEGIN_BCS_BATCH(batch, 6);
2214     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2215     OUT_BCS_BATCH(batch, 0);
2216     OUT_BCS_BATCH(batch,
2217                   ((obj_surface->orig_width - 1) << 18) |
2218                   ((obj_surface->orig_height - 1) << 4));
2219     OUT_BCS_BATCH(batch,
2220                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2221                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2222                   (0 << 22) | /* surface object control state, ignored */
2223                   ((obj_surface->width - 1) << 3) | /* pitch */
2224                   (0 << 2)  | /* must be 0 */
2225                   (1 << 1)  | /* must be tiled */
2226                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2227     OUT_BCS_BATCH(batch,
2228                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2229                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2230     OUT_BCS_BATCH(batch,
2231                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2232                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2233     ADVANCE_BCS_BATCH(batch);
2234 }
2235
2236 static void
2237 gen7_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2238                                  struct gen7_mfd_context *gen7_mfd_context)
2239 {
2240     struct i965_driver_data *i965 = i965_driver_data(ctx);
2241     struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2242     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2243     dri_bo *intra_bo;
2244     int i;
2245
2246     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2247                             "intra row store",
2248                             128 * 64,
2249                             0x1000);
2250
2251     BEGIN_BCS_BATCH(batch, 24);
2252     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2253     OUT_BCS_RELOC(batch,
2254                   obj_surface->bo,
2255                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2256                   0);
2257
2258     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2259
2260     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2261     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2262
2263     OUT_BCS_RELOC(batch,
2264                   intra_bo,
2265                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2266                   0);
2267
2268     OUT_BCS_BATCH(batch, 0);
2269
2270     /* DW 7..22 */
2271     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2272         OUT_BCS_BATCH(batch, 0);
2273     }
2274
2275     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2276     ADVANCE_BCS_BATCH(batch);
2277
2278     dri_bo_unreference(intra_bo);
2279 }
2280
2281 static void
2282 gen7_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2283                                      struct gen7_mfd_context *gen7_mfd_context)
2284 {
2285     struct i965_driver_data *i965 = i965_driver_data(ctx);
2286     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2287     dri_bo *bsd_mpc_bo, *mpr_bo;
2288
2289     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2290                               "bsd mpc row store",
2291                               11520, /* 1.5 * 120 * 64 */
2292                               0x1000);
2293
2294     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2295                           "mpr row store",
2296                           7680, /* 1. 0 * 120 * 64 */
2297                           0x1000);
2298
2299     BEGIN_BCS_BATCH(batch, 4);
2300     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2301
2302     OUT_BCS_RELOC(batch,
2303                   bsd_mpc_bo,
2304                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2305                   0);
2306
2307     OUT_BCS_RELOC(batch,
2308                   mpr_bo,
2309                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2310                   0);
2311     OUT_BCS_BATCH(batch, 0);
2312
2313     ADVANCE_BCS_BATCH(batch);
2314
2315     dri_bo_unreference(bsd_mpc_bo);
2316     dri_bo_unreference(mpr_bo);
2317 }
2318
2319 static void
2320 gen7_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2321                           struct gen7_mfd_context *gen7_mfd_context)
2322 {
2323
2324 }
2325
2326 static void
2327 gen7_jpeg_wa_avc_img_state(VADriverContextP ctx,
2328                            struct gen7_mfd_context *gen7_mfd_context)
2329 {
2330     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2331     int img_struct = 0;
2332     int mbaff_frame_flag = 0;
2333     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2334
2335     BEGIN_BCS_BATCH(batch, 16);
2336     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2337     OUT_BCS_BATCH(batch,
2338                   (width_in_mbs * height_in_mbs - 1));
2339     OUT_BCS_BATCH(batch,
2340                   ((height_in_mbs - 1) << 16) |
2341                   ((width_in_mbs - 1) << 0));
2342     OUT_BCS_BATCH(batch,
2343                   (0 << 24) |
2344                   (0 << 16) |
2345                   (0 << 14) |
2346                   (0 << 13) |
2347                   (0 << 12) | /* differ from GEN6 */
2348                   (0 << 10) |
2349                   (img_struct << 8));
2350     OUT_BCS_BATCH(batch,
2351                   (1 << 10) | /* 4:2:0 */
2352                   (1 << 7) |  /* CABAC */
2353                   (0 << 6) |
2354                   (0 << 5) |
2355                   (0 << 4) |
2356                   (0 << 3) |
2357                   (1 << 2) |
2358                   (mbaff_frame_flag << 1) |
2359                   (0 << 0));
2360     OUT_BCS_BATCH(batch, 0);
2361     OUT_BCS_BATCH(batch, 0);
2362     OUT_BCS_BATCH(batch, 0);
2363     OUT_BCS_BATCH(batch, 0);
2364     OUT_BCS_BATCH(batch, 0);
2365     OUT_BCS_BATCH(batch, 0);
2366     OUT_BCS_BATCH(batch, 0);
2367     OUT_BCS_BATCH(batch, 0);
2368     OUT_BCS_BATCH(batch, 0);
2369     OUT_BCS_BATCH(batch, 0);
2370     OUT_BCS_BATCH(batch, 0);
2371     ADVANCE_BCS_BATCH(batch);
2372 }
2373
2374 static void
2375 gen7_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2376                                   struct gen7_mfd_context *gen7_mfd_context)
2377 {
2378     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2379     int i;
2380
2381     BEGIN_BCS_BATCH(batch, 69);
2382     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2383
2384     /* reference surfaces 0..15 */
2385     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2386         OUT_BCS_BATCH(batch, 0); /* top */
2387         OUT_BCS_BATCH(batch, 0); /* bottom */
2388     }
2389
2390     /* the current decoding frame/field */
2391     OUT_BCS_BATCH(batch, 0); /* top */
2392     OUT_BCS_BATCH(batch, 0); /* bottom */
2393
2394     /* POC List */
2395     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2396         OUT_BCS_BATCH(batch, 0);
2397         OUT_BCS_BATCH(batch, 0);
2398     }
2399
2400     OUT_BCS_BATCH(batch, 0);
2401     OUT_BCS_BATCH(batch, 0);
2402
2403     ADVANCE_BCS_BATCH(batch);
2404 }
2405
2406 static void
2407 gen7_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2408                                      struct gen7_mfd_context *gen7_mfd_context)
2409 {
2410     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2411
2412     BEGIN_BCS_BATCH(batch, 11);
2413     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2414     OUT_BCS_RELOC(batch,
2415                   gen7_mfd_context->jpeg_wa_slice_data_bo,
2416                   I915_GEM_DOMAIN_INSTRUCTION, 0,
2417                   0);
2418     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2419     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2420     OUT_BCS_BATCH(batch, 0);
2421     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2422     OUT_BCS_BATCH(batch, 0);
2423     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2424     OUT_BCS_BATCH(batch, 0);
2425     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2426     OUT_BCS_BATCH(batch, 0);
2427     ADVANCE_BCS_BATCH(batch);
2428 }
2429
2430 static void
2431 gen7_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2432                             struct gen7_mfd_context *gen7_mfd_context)
2433 {
2434     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2435
2436     /* the input bitsteam format on GEN7 differs from GEN6 */
2437     BEGIN_BCS_BATCH(batch, 6);
2438     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2439     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2440     OUT_BCS_BATCH(batch, 0);
2441     OUT_BCS_BATCH(batch,
2442                   (0 << 31) |
2443                   (0 << 14) |
2444                   (0 << 12) |
2445                   (0 << 10) |
2446                   (0 << 8));
2447     OUT_BCS_BATCH(batch,
2448                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2449                   (0 << 5)  |
2450                   (0 << 4)  |
2451                   (1 << 3) | /* LastSlice Flag */
2452                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2453     OUT_BCS_BATCH(batch, 0);
2454     ADVANCE_BCS_BATCH(batch);
2455 }
2456
2457 static void
2458 gen7_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2459                              struct gen7_mfd_context *gen7_mfd_context)
2460 {
2461     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2462     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2463     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2464     int first_mb_in_slice = 0;
2465     int slice_type = SLICE_TYPE_I;
2466
2467     BEGIN_BCS_BATCH(batch, 11);
2468     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2469     OUT_BCS_BATCH(batch, slice_type);
2470     OUT_BCS_BATCH(batch,
2471                   (num_ref_idx_l1 << 24) |
2472                   (num_ref_idx_l0 << 16) |
2473                   (0 << 8) |
2474                   (0 << 0));
2475     OUT_BCS_BATCH(batch,
2476                   (0 << 29) |
2477                   (1 << 27) |   /* disable Deblocking */
2478                   (0 << 24) |
2479                   (gen7_jpeg_wa_clip.qp << 16) |
2480                   (0 << 8) |
2481                   (0 << 0));
2482     OUT_BCS_BATCH(batch,
2483                   (slice_ver_pos << 24) |
2484                   (slice_hor_pos << 16) |
2485                   (first_mb_in_slice << 0));
2486     OUT_BCS_BATCH(batch,
2487                   (next_slice_ver_pos << 16) |
2488                   (next_slice_hor_pos << 0));
2489     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2490     OUT_BCS_BATCH(batch, 0);
2491     OUT_BCS_BATCH(batch, 0);
2492     OUT_BCS_BATCH(batch, 0);
2493     OUT_BCS_BATCH(batch, 0);
2494     ADVANCE_BCS_BATCH(batch);
2495 }
2496
2497 static void
2498 gen7_mfd_jpeg_wa(VADriverContextP ctx,
2499                  struct gen7_mfd_context *gen7_mfd_context)
2500 {
2501     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2502     gen7_jpeg_wa_init(ctx, gen7_mfd_context);
2503     intel_batchbuffer_emit_mi_flush(batch);
2504     gen7_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2505     gen7_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2506     gen7_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2507     gen7_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2508     gen7_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2509     gen7_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2510     gen7_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2511
2512     gen7_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2513     gen7_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2514     gen7_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2515 }
2516
2517 void
2518 gen7_mfd_jpeg_decode_picture(VADriverContextP ctx,
2519                              struct decode_state *decode_state,
2520                              struct gen7_mfd_context *gen7_mfd_context)
2521 {
2522     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2523     VAPictureParameterBufferJPEGBaseline *pic_param;
2524     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2525     dri_bo *slice_data_bo;
2526     int i, j, max_selector = 0;
2527
2528     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2529     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2530
2531     /* Currently only support Baseline DCT */
2532     gen7_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2533     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2534     gen7_mfd_jpeg_wa(ctx, gen7_mfd_context);
2535     intel_batchbuffer_emit_mi_flush(batch);
2536     gen7_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2537     gen7_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2538     gen7_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2539     gen7_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2540     gen7_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2541
2542     for (j = 0; j < decode_state->num_slice_params; j++) {
2543         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2544         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2545         slice_data_bo = decode_state->slice_datas[j]->bo;
2546         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2547
2548         if (j == decode_state->num_slice_params - 1)
2549             next_slice_group_param = NULL;
2550         else
2551             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2552
2553         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2554             int component;
2555
2556             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2557
2558             if (i < decode_state->slice_params[j]->num_elements - 1)
2559                 next_slice_param = slice_param + 1;
2560             else
2561                 next_slice_param = next_slice_group_param;
2562
2563             for (component = 0; component < slice_param->num_components; component++) {
2564                 if (max_selector < slice_param->components[component].dc_table_selector)
2565                     max_selector = slice_param->components[component].dc_table_selector;
2566
2567                 if (max_selector < slice_param->components[component].ac_table_selector)
2568                     max_selector = slice_param->components[component].ac_table_selector;
2569             }
2570
2571             slice_param++;
2572         }
2573     }
2574
2575     assert(max_selector < 2);
2576     gen7_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2577
2578     for (j = 0; j < decode_state->num_slice_params; j++) {
2579         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2580         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2581         slice_data_bo = decode_state->slice_datas[j]->bo;
2582         gen7_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2583
2584         if (j == decode_state->num_slice_params - 1)
2585             next_slice_group_param = NULL;
2586         else
2587             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2588
2589         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2590             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2591
2592             if (i < decode_state->slice_params[j]->num_elements - 1)
2593                 next_slice_param = slice_param + 1;
2594             else
2595                 next_slice_param = next_slice_group_param;
2596
2597             gen7_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2598             slice_param++;
2599         }
2600     }
2601
2602     intel_batchbuffer_end_atomic(batch);
2603     intel_batchbuffer_flush(batch);
2604 }
2605
2606 static VAStatus
2607 gen7_mfd_decode_picture(VADriverContextP ctx,
2608                         VAProfile profile,
2609                         union codec_state *codec_state,
2610                         struct hw_context *hw_context)
2611
2612 {
2613     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2614     struct decode_state *decode_state = &codec_state->decode;
2615     VAStatus vaStatus;
2616
2617     assert(gen7_mfd_context);
2618
2619     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
2620
2621     if (vaStatus != VA_STATUS_SUCCESS)
2622         goto out;
2623
2624     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2625
2626     switch (profile) {
2627     case VAProfileMPEG2Simple:
2628     case VAProfileMPEG2Main:
2629         gen7_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2630         break;
2631
2632     case VAProfileH264ConstrainedBaseline:
2633     case VAProfileH264Main:
2634     case VAProfileH264High:
2635         gen7_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2636         break;
2637
2638     case VAProfileVC1Simple:
2639     case VAProfileVC1Main:
2640     case VAProfileVC1Advanced:
2641         gen7_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2642         break;
2643
2644     case VAProfileJPEGBaseline:
2645         gen7_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2646         break;
2647
2648     default:
2649         assert(0);
2650         break;
2651     }
2652
2653     vaStatus = VA_STATUS_SUCCESS;
2654
2655 out:
2656     return vaStatus;
2657 }
2658
2659 static void
2660 gen7_mfd_context_destroy(void *hw_context)
2661 {
2662     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2663
2664     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2665     gen7_mfd_context->post_deblocking_output.bo = NULL;
2666
2667     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2668     gen7_mfd_context->pre_deblocking_output.bo = NULL;
2669
2670     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2671     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2672
2673     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2674     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2675
2676     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2677     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2678
2679     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2680     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2681
2682     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2683     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2684
2685     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2686
2687     intel_batchbuffer_free(gen7_mfd_context->base.batch);
2688     free(gen7_mfd_context);
2689 }
2690
2691 static void gen7_mfd_mpeg2_context_init(VADriverContextP ctx,
2692                                     struct gen7_mfd_context *gen7_mfd_context)
2693 {
2694     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2695     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2696     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2697     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2698 }
2699
2700 struct hw_context *
2701 gen7_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2702 {
2703     struct intel_driver_data *intel = intel_driver_data(ctx);
2704     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2705     int i;
2706
2707     gen7_mfd_context->base.destroy = gen7_mfd_context_destroy;
2708     gen7_mfd_context->base.run = gen7_mfd_decode_picture;
2709     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2710
2711     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2712         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2713         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2714         gen7_mfd_context->reference_surface[i].obj_surface = NULL;
2715     }
2716
2717     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2718     gen7_mfd_context->jpeg_wa_surface_object = NULL;
2719
2720     switch (obj_config->profile) {
2721     case VAProfileMPEG2Simple:
2722     case VAProfileMPEG2Main:
2723         gen7_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2724         break;
2725
2726     case VAProfileH264ConstrainedBaseline:
2727     case VAProfileH264Main:
2728     case VAProfileH264High:
2729         gen7_mfd_avc_context_init(ctx, gen7_mfd_context);
2730         break;
2731     default:
2732         break;
2733     }
2734     return (struct hw_context *)gen7_mfd_context;
2735 }