2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
37 #include "i965_defines.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
45 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32)
48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32)
49 #define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
51 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
52 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
53 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
55 #define VME_INTRA_SHADER 0
56 #define VME_INTER_SHADER 1
57 #define VME_BATCHBUFFER 2
59 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
60 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
61 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
63 #define VME_MSG_LENGTH 32
65 static const uint32_t gen75_vme_intra_frame[][4] = {
66 #include "shaders/vme/intra_frame_haswell.g75b"
69 static const uint32_t gen75_vme_inter_frame[][4] = {
70 #include "shaders/vme/inter_frame_haswell.g75b"
73 static const uint32_t gen75_vme_batchbuffer[][4] = {
74 #include "shaders/vme/batchbuffer.g75b"
77 static struct i965_kernel gen75_vme_kernels[] = {
80 VME_INTRA_SHADER, /*index*/
81 gen75_vme_intra_frame,
82 sizeof(gen75_vme_intra_frame),
88 gen75_vme_inter_frame,
89 sizeof(gen75_vme_inter_frame),
95 gen75_vme_batchbuffer,
96 sizeof(gen75_vme_batchbuffer),
101 /* only used for VME source surface state */
103 gen75_vme_source_surface_state(VADriverContextP ctx,
105 struct object_surface *obj_surface,
106 struct intel_encoder_context *encoder_context)
108 struct gen6_vme_context *vme_context = encoder_context->vme_context;
110 vme_context->vme_surface2_setup(ctx,
111 &vme_context->gpe_context,
113 BINDING_TABLE_OFFSET(index),
114 SURFACE_STATE_OFFSET(index));
118 gen75_vme_media_source_surface_state(VADriverContextP ctx,
120 struct object_surface *obj_surface,
121 struct intel_encoder_context *encoder_context)
123 struct gen6_vme_context *vme_context = encoder_context->vme_context;
125 vme_context->vme_media_rw_surface_setup(ctx,
126 &vme_context->gpe_context,
128 BINDING_TABLE_OFFSET(index),
129 SURFACE_STATE_OFFSET(index));
133 gen75_vme_media_chroma_source_surface_state(VADriverContextP ctx,
135 struct object_surface *obj_surface,
136 struct intel_encoder_context *encoder_context)
138 struct gen6_vme_context *vme_context = encoder_context->vme_context;
140 vme_context->vme_media_chroma_surface_setup(ctx,
141 &vme_context->gpe_context,
143 BINDING_TABLE_OFFSET(index),
144 SURFACE_STATE_OFFSET(index));
148 gen75_vme_output_buffer_setup(VADriverContextP ctx,
149 struct encode_state *encode_state,
151 struct intel_encoder_context *encoder_context)
154 struct i965_driver_data *i965 = i965_driver_data(ctx);
155 struct gen6_vme_context *vme_context = encoder_context->vme_context;
156 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
157 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
158 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
159 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
160 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
162 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
163 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
166 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
168 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
170 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
171 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
172 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
175 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
177 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
179 assert(vme_context->vme_output.bo);
180 vme_context->vme_buffer_suface_setup(ctx,
181 &vme_context->gpe_context,
182 &vme_context->vme_output,
183 BINDING_TABLE_OFFSET(index),
184 SURFACE_STATE_OFFSET(index));
188 gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
189 struct encode_state *encode_state,
191 struct intel_encoder_context *encoder_context)
194 struct i965_driver_data *i965 = i965_driver_data(ctx);
195 struct gen6_vme_context *vme_context = encoder_context->vme_context;
196 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
197 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
198 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
200 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
201 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
202 vme_context->vme_batchbuffer.pitch = 16;
203 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
205 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
207 vme_context->vme_buffer_suface_setup(ctx,
208 &vme_context->gpe_context,
209 &vme_context->vme_batchbuffer,
210 BINDING_TABLE_OFFSET(index),
211 SURFACE_STATE_OFFSET(index));
215 gen75_vme_surface_setup(VADriverContextP ctx,
216 struct encode_state *encode_state,
218 struct intel_encoder_context *encoder_context)
220 struct i965_driver_data *i965 = i965_driver_data(ctx);
221 struct object_surface *obj_surface;
222 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
224 /*Setup surfaces state*/
225 /* current picture for encoding */
226 obj_surface = SURFACE(encoder_context->input_yuv_surface);
228 gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
229 gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
230 gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
234 obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
236 if ( obj_surface->bo != NULL)
237 gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
240 obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
242 if ( obj_surface->bo != NULL )
243 gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
247 gen75_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
248 gen75_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
250 return VA_STATUS_SUCCESS;
253 static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
254 struct encode_state *encode_state,
255 struct intel_encoder_context *encoder_context)
257 struct gen6_vme_context *vme_context = encoder_context->vme_context;
258 struct gen6_interface_descriptor_data *desc;
262 bo = vme_context->gpe_context.idrt.bo;
267 for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
268 struct i965_kernel *kernel;
269 kernel = &vme_context->gpe_context.kernels[i];
270 assert(sizeof(*desc) == 32);
271 /*Setup the descritor table*/
272 memset(desc, 0, sizeof(*desc));
273 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
274 desc->desc2.sampler_count = 0; /* FIXME: */
275 desc->desc2.sampler_state_pointer = 0;
276 desc->desc3.binding_table_entry_count = 1; /* FIXME: */
277 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
278 desc->desc4.constant_urb_entry_read_offset = 0;
279 desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
282 dri_bo_emit_reloc(bo,
283 I915_GEM_DOMAIN_INSTRUCTION, 0,
285 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
291 return VA_STATUS_SUCCESS;
294 static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
295 struct encode_state *encode_state,
296 struct intel_encoder_context *encoder_context)
298 struct gen6_vme_context *vme_context = encoder_context->vme_context;
299 unsigned char *constant_buffer;
301 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
302 assert(vme_context->gpe_context.curbe.bo->virtual);
303 constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
305 /* VME MV/Mb cost table is passed by using const buffer */
306 /* Now it uses the fixed search path. So it is constructed directly
309 memcpy(constant_buffer, (char *)vme_context->vme_state_message, 32);
311 dri_bo_unmap( vme_context->gpe_context.curbe.bo);
313 return VA_STATUS_SUCCESS;
316 static const unsigned int intra_mb_mode_cost_table[] = {
317 0x31110001, // for qp0
318 0x09110001, // for qp1
319 0x15030001, // for qp2
320 0x0b030001, // for qp3
321 0x0d030011, // for qp4
322 0x17210011, // for qp5
323 0x41210011, // for qp6
324 0x19210011, // for qp7
325 0x25050003, // for qp8
326 0x1b130003, // for qp9
327 0x1d130003, // for qp10
328 0x27070021, // for qp11
329 0x51310021, // for qp12
330 0x29090021, // for qp13
331 0x35150005, // for qp14
332 0x2b0b0013, // for qp15
333 0x2d0d0013, // for qp16
334 0x37170007, // for qp17
335 0x61410031, // for qp18
336 0x39190009, // for qp19
337 0x45250015, // for qp20
338 0x3b1b000b, // for qp21
339 0x3d1d000d, // for qp22
340 0x47270017, // for qp23
341 0x71510041, // for qp24 ! center for qp=0..30
342 0x49290019, // for qp25
343 0x55350025, // for qp26
344 0x4b2b001b, // for qp27
345 0x4d2d001d, // for qp28
346 0x57370027, // for qp29
347 0x81610051, // for qp30
348 0x57270017, // for qp31
349 0x81510041, // for qp32 ! center for qp=31..51
350 0x59290019, // for qp33
351 0x65350025, // for qp34
352 0x5b2b001b, // for qp35
353 0x5d2d001d, // for qp36
354 0x67370027, // for qp37
355 0x91610051, // for qp38
356 0x69390029, // for qp39
357 0x75450035, // for qp40
358 0x6b3b002b, // for qp41
359 0x6d3d002d, // for qp42
360 0x77470037, // for qp43
361 0xa1710061, // for qp44
362 0x79490039, // for qp45
363 0x85550045, // for qp46
364 0x7b4b003b, // for qp47
365 0x7d4d003d, // for qp48
366 0x87570047, // for qp49
367 0xb1810071, // for qp50
368 0x89590049 // for qp51
371 static void gen75_vme_state_setup_fixup(VADriverContextP ctx,
372 struct encode_state *encode_state,
373 struct intel_encoder_context *encoder_context,
374 unsigned int *vme_state_message)
376 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
377 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
378 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
380 if (slice_param->slice_type != SLICE_TYPE_I &&
381 slice_param->slice_type != SLICE_TYPE_SI)
383 if (encoder_context->rate_control_mode == VA_RC_CQP)
384 vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
386 vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[slice_param->slice_type].QpPrimeY];
389 static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
390 struct encode_state *encode_state,
392 struct intel_encoder_context *encoder_context)
394 struct gen6_vme_context *vme_context = encoder_context->vme_context;
395 unsigned int *vme_state_message;
398 //pass the MV/Mb cost into VME message on HASWell
399 assert(vme_context->vme_state_message);
400 vme_state_message = (unsigned int *)vme_context->vme_state_message;
402 vme_state_message[0] = 0x4a4a4a4a;
403 vme_state_message[1] = 0x4a4a4a4a;
404 vme_state_message[2] = 0x4a4a4a4a;
405 vme_state_message[3] = 0x22120200;
406 vme_state_message[4] = 0x62524232;
408 for (i=5; i < 8; i++) {
409 vme_state_message[i] = 0;
412 gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
414 return VA_STATUS_SUCCESS;
418 gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
419 struct encode_state *encode_state,
420 int mb_width, int mb_height,
422 int transform_8x8_mode_flag,
423 struct intel_encoder_context *encoder_context)
425 struct gen6_vme_context *vme_context = encoder_context->vme_context;
426 int mb_x = 0, mb_y = 0;
428 unsigned int *command_ptr;
430 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
431 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
433 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
434 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
435 int slice_mb_begin = pSliceParameter->macroblock_address;
436 int slice_mb_number = pSliceParameter->num_macroblocks;
438 for (i = 0; i < slice_mb_number; ) {
439 int mb_count = i + slice_mb_begin;
440 mb_x = mb_count % mb_width;
441 mb_y = mb_count / mb_width;
443 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
444 *command_ptr++ = kernel;
451 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
452 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | ((i==0) << 1));
459 *command_ptr++ = MI_BATCH_BUFFER_END;
461 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
464 static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
466 struct i965_driver_data *i965 = i965_driver_data(ctx);
467 struct gen6_vme_context *vme_context = encoder_context->vme_context;
470 i965_gpe_context_init(ctx, &vme_context->gpe_context);
472 /* VME output buffer */
473 dri_bo_unreference(vme_context->vme_output.bo);
474 vme_context->vme_output.bo = NULL;
476 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
477 vme_context->vme_batchbuffer.bo = NULL;
480 dri_bo_unreference(vme_context->vme_state.bo);
481 vme_context->vme_state.bo = NULL;
484 static void gen75_vme_pipeline_programing(VADriverContextP ctx,
485 struct encode_state *encode_state,
486 struct intel_encoder_context *encoder_context)
488 struct gen6_vme_context *vme_context = encoder_context->vme_context;
489 struct intel_batchbuffer *batch = encoder_context->base.batch;
490 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
491 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
492 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
493 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
494 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
495 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
497 gen75_vme_fill_vme_batchbuffer(ctx,
499 width_in_mbs, height_in_mbs,
500 is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
501 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
504 intel_batchbuffer_start_atomic(batch, 0x1000);
505 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
506 BEGIN_BATCH(batch, 2);
507 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
509 vme_context->vme_batchbuffer.bo,
510 I915_GEM_DOMAIN_COMMAND, 0,
512 ADVANCE_BATCH(batch);
514 intel_batchbuffer_end_atomic(batch);
517 static VAStatus gen75_vme_prepare(VADriverContextP ctx,
518 struct encode_state *encode_state,
519 struct intel_encoder_context *encoder_context)
521 VAStatus vaStatus = VA_STATUS_SUCCESS;
522 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
523 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
525 /*Setup all the memory object*/
526 gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
527 gen75_vme_interface_setup(ctx, encode_state, encoder_context);
528 gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
529 gen75_vme_constant_setup(ctx, encode_state, encoder_context);
531 /*Programing media pipeline*/
532 gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
537 static VAStatus gen75_vme_run(VADriverContextP ctx,
538 struct encode_state *encode_state,
539 struct intel_encoder_context *encoder_context)
541 struct intel_batchbuffer *batch = encoder_context->base.batch;
543 intel_batchbuffer_flush(batch);
545 return VA_STATUS_SUCCESS;
548 static VAStatus gen75_vme_stop(VADriverContextP ctx,
549 struct encode_state *encode_state,
550 struct intel_encoder_context *encoder_context)
552 return VA_STATUS_SUCCESS;
556 gen75_vme_pipeline(VADriverContextP ctx,
558 struct encode_state *encode_state,
559 struct intel_encoder_context *encoder_context)
561 gen75_vme_media_init(ctx, encoder_context);
562 gen75_vme_prepare(ctx, encode_state, encoder_context);
563 gen75_vme_run(ctx, encode_state, encoder_context);
564 gen75_vme_stop(ctx, encode_state, encoder_context);
566 return VA_STATUS_SUCCESS;
570 gen75_vme_context_destroy(void *context)
572 struct gen6_vme_context *vme_context = context;
574 i965_gpe_context_destroy(&vme_context->gpe_context);
576 dri_bo_unreference(vme_context->vme_output.bo);
577 vme_context->vme_output.bo = NULL;
579 dri_bo_unreference(vme_context->vme_state.bo);
580 vme_context->vme_state.bo = NULL;
582 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
583 vme_context->vme_batchbuffer.bo = NULL;
585 if (vme_context->vme_state_message) {
586 free(vme_context->vme_state_message);
587 vme_context->vme_state_message = NULL;
593 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
595 struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
597 vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
599 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
600 vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
602 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
604 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
605 vme_context->gpe_context.vfe_state.num_urb_entries = 16;
606 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
607 vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
608 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
610 i965_gpe_load_kernels(ctx,
611 &vme_context->gpe_context,
613 GEN6_VME_KERNEL_NUMBER);
614 vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
615 vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
616 vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
617 vme_context->vme_media_chroma_surface_setup = gen75_gpe_media_chroma_surface_setup;
619 encoder_context->vme_context = vme_context;
620 encoder_context->vme_context_destroy = gen75_vme_context_destroy;
621 encoder_context->vme_pipeline = gen75_vme_pipeline;
623 vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));