src/gen75_vme.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhao Yakui <yakui.zhao@intel.com>
  26  *    Xiang Haihao <haihao.xiang@intel.com>
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "gen6_vme.h"
  41 #include "gen6_mfc.h"
  42
  43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  45 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  46
  47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  49 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  50
  51 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  52 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  53 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  54
  55 #define VME_INTRA_SHADER        0
  56 #define VME_INTER_SHADER        1
  57 #define VME_BATCHBUFFER         2
  58
  59 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  60 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  61 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  62
  63 #define VME_MSG_LENGTH          32
  64
  65 static const uint32_t gen75_vme_intra_frame[][4] = {
  66 #include "shaders/vme/intra_frame_haswell.g75b"
  67 };
  68
  69 static const uint32_t gen75_vme_inter_frame[][4] = {
  70 #include "shaders/vme/inter_frame_haswell.g75b"
  71 };
  72
  73 static const uint32_t gen75_vme_batchbuffer[][4] = {
  74 #include "shaders/vme/batchbuffer.g75b"
  75 };
  76
  77 static struct i965_kernel gen75_vme_kernels[] = {
  78     {
  79         "VME Intra Frame",
  80         VME_INTRA_SHADER, /*index*/
  81         gen75_vme_intra_frame,
  82         sizeof(gen75_vme_intra_frame),
  83         NULL
  84     },
  85     {
  86         "VME inter Frame",
  87         VME_INTER_SHADER,
  88         gen75_vme_inter_frame,
  89         sizeof(gen75_vme_inter_frame),
  90         NULL
  91     },
  92     {
  93         "VME BATCHBUFFER",
  94         VME_BATCHBUFFER,
  95         gen75_vme_batchbuffer,
  96         sizeof(gen75_vme_batchbuffer),
  97         NULL
  98     },
  99 };
 100
 101 /* only used for VME source surface state */
 102 static void
 103 gen75_vme_source_surface_state(VADriverContextP ctx,
 104                                int index,
 105                                struct object_surface *obj_surface,
 106                                struct intel_encoder_context *encoder_context)
 107 {
 108     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 109
 110     vme_context->vme_surface2_setup(ctx,
 111                                     &vme_context->gpe_context,
 112                                     obj_surface,
 113                                     BINDING_TABLE_OFFSET(index),
 114                                     SURFACE_STATE_OFFSET(index));
 115 }
 116
 117 static void
 118 gen75_vme_media_source_surface_state(VADriverContextP ctx,
 119                                      int index,
 120                                      struct object_surface *obj_surface,
 121                                      struct intel_encoder_context *encoder_context)
 122 {
 123     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 124
 125     vme_context->vme_media_rw_surface_setup(ctx,
 126                                             &vme_context->gpe_context,
 127                                             obj_surface,
 128                                             BINDING_TABLE_OFFSET(index),
 129                                             SURFACE_STATE_OFFSET(index));
 130 }
 131
 132 static void
 133 gen75_vme_media_chroma_source_surface_state(VADriverContextP ctx,
 134                                             int index,
 135                                             struct object_surface *obj_surface,
 136                                             struct intel_encoder_context *encoder_context)
 137 {
 138     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 139
 140     vme_context->vme_media_chroma_surface_setup(ctx,
 141                                                 &vme_context->gpe_context,
 142                                                 obj_surface,
 143                                                 BINDING_TABLE_OFFSET(index),
 144                                                 SURFACE_STATE_OFFSET(index));
 145 }
 146
 147 static void
 148 gen75_vme_output_buffer_setup(VADriverContextP ctx,
 149                               struct encode_state *encode_state,
 150                               int index,
 151                               struct intel_encoder_context *encoder_context)
 152
 153 {
 154     struct i965_driver_data *i965 = i965_driver_data(ctx);
 155     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 156     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 157     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 158     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 159     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 160     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 161
 162     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 163     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 164
 165     if (is_intra)
 166         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
 167     else
 168         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
 169     /*
 170      * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
 171      * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
 172      * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
 173      */
 174
 175     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 176                                               "VME output buffer",
 177                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 178                                               0x1000);
 179     assert(vme_context->vme_output.bo);
 180     vme_context->vme_buffer_suface_setup(ctx,
 181                                          &vme_context->gpe_context,
 182                                          &vme_context->vme_output,
 183                                          BINDING_TABLE_OFFSET(index),
 184                                          SURFACE_STATE_OFFSET(index));
 185 }
 186
 187 static void
 188 gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 189                                        struct encode_state *encode_state,
 190                                        int index,
 191                                        struct intel_encoder_context *encoder_context)
 192
 193 {
 194     struct i965_driver_data *i965 = i965_driver_data(ctx);
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 197     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 198     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 199
 200     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 201     vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
 202     vme_context->vme_batchbuffer.pitch = 16;
 203     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 204                                                    "VME batchbuffer",
 205                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 206                                                    0x1000);
 207     vme_context->vme_buffer_suface_setup(ctx,
 208                                          &vme_context->gpe_context,
 209                                          &vme_context->vme_batchbuffer,
 210                                          BINDING_TABLE_OFFSET(index),
 211                                          SURFACE_STATE_OFFSET(index));
 212 }
 213
 214 static VAStatus
 215 gen75_vme_surface_setup(VADriverContextP ctx,
 216                         struct encode_state *encode_state,
 217                         int is_intra,
 218                         struct intel_encoder_context *encoder_context)
 219 {
 220     struct i965_driver_data *i965 = i965_driver_data(ctx);
 221     struct object_surface *obj_surface;
 222     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 223
 224     /*Setup surfaces state*/
 225     /* current picture for encoding */
 226     obj_surface = SURFACE(encoder_context->input_yuv_surface);
 227     assert(obj_surface);
 228     gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 229     gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 230     gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
 231
 232     if (!is_intra) {
 233         /* reference 0 */
 234         obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
 235         assert(obj_surface);
 236         if ( obj_surface->bo != NULL)
 237             gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 238
 239         /* reference 1 */
 240         obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
 241         assert(obj_surface);
 242         if ( obj_surface->bo != NULL )
 243             gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 244     }
 245
 246     /* VME output */
 247     gen75_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 248     gen75_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 249
 250     return VA_STATUS_SUCCESS;
 251 }
 252
 253 static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
 254                                           struct encode_state *encode_state,
 255                                           struct intel_encoder_context *encoder_context)
 256 {
 257     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 258     struct gen6_interface_descriptor_data *desc;
 259     int i;
 260     dri_bo *bo;
 261
 262     bo = vme_context->gpe_context.idrt.bo;
 263     dri_bo_map(bo, 1);
 264     assert(bo->virtual);
 265     desc = bo->virtual;
 266
 267     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 268         struct i965_kernel *kernel;
 269         kernel = &vme_context->gpe_context.kernels[i];
 270         assert(sizeof(*desc) == 32);
 271         /*Setup the descritor table*/
 272         memset(desc, 0, sizeof(*desc));
 273         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 274         desc->desc2.sampler_count = 0; /* FIXME: */
 275         desc->desc2.sampler_state_pointer = 0;
 276         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 277         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 278         desc->desc4.constant_urb_entry_read_offset = 0;
 279         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 280
 281         /*kernel start*/
 282         dri_bo_emit_reloc(bo,
 283                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 284                           0,
 285                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 286                           kernel->bo);
 287         desc++;
 288     }
 289     dri_bo_unmap(bo);
 290
 291     return VA_STATUS_SUCCESS;
 292 }
 293
 294 static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
 295                                          struct encode_state *encode_state,
 296                                          struct intel_encoder_context *encoder_context)
 297 {
 298     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 299     unsigned char *constant_buffer;
 300     unsigned int *vme_state_message;
 301     int mv_num = 32;
 302
 303     vme_state_message = (unsigned int *)vme_context->vme_state_message;
 304     if (vme_context->h264_level >= 30) {
 305         mv_num = 16;
 306         if (vme_context->h264_level >= 31)
 307             mv_num = 8;
 308     }
 309     vme_state_message[31] = mv_num;
 310
 311     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
 312     assert(vme_context->gpe_context.curbe.bo->virtual);
 313     constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
 314
 315     /* VME MV/Mb cost table is passed by using const buffer */
 316     /* Now it uses the fixed search path. So it is constructed directly
 317      * in the GPU shader.
 318      */
 319     memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
 320
 321     dri_bo_unmap( vme_context->gpe_context.curbe.bo);
 322
 323     return VA_STATUS_SUCCESS;
 324 }
 325
 326 static const unsigned int intra_mb_mode_cost_table[] = {
 327     0x31110001, // for qp0
 328     0x09110001, // for qp1
 329     0x15030001, // for qp2
 330     0x0b030001, // for qp3
 331     0x0d030011, // for qp4
 332     0x17210011, // for qp5
 333     0x41210011, // for qp6
 334     0x19210011, // for qp7
 335     0x25050003, // for qp8
 336     0x1b130003, // for qp9
 337     0x1d130003, // for qp10
 338     0x27070021, // for qp11
 339     0x51310021, // for qp12
 340     0x29090021, // for qp13
 341     0x35150005, // for qp14
 342     0x2b0b0013, // for qp15
 343     0x2d0d0013, // for qp16
 344     0x37170007, // for qp17
 345     0x61410031, // for qp18
 346     0x39190009, // for qp19
 347     0x45250015, // for qp20
 348     0x3b1b000b, // for qp21
 349     0x3d1d000d, // for qp22
 350     0x47270017, // for qp23
 351     0x71510041, // for qp24 ! center for qp=0..30
 352     0x49290019, // for qp25
 353     0x55350025, // for qp26
 354     0x4b2b001b, // for qp27
 355     0x4d2d001d, // for qp28
 356     0x57370027, // for qp29
 357     0x81610051, // for qp30
 358     0x57270017, // for qp31
 359     0x81510041, // for qp32 ! center for qp=31..51
 360     0x59290019, // for qp33
 361     0x65350025, // for qp34
 362     0x5b2b001b, // for qp35
 363     0x5d2d001d, // for qp36
 364     0x67370027, // for qp37
 365     0x91610051, // for qp38
 366     0x69390029, // for qp39
 367     0x75450035, // for qp40
 368     0x6b3b002b, // for qp41
 369     0x6d3d002d, // for qp42
 370     0x77470037, // for qp43
 371     0xa1710061, // for qp44
 372     0x79490039, // for qp45
 373     0x85550045, // for qp46
 374     0x7b4b003b, // for qp47
 375     0x7d4d003d, // for qp48
 376     0x87570047, // for qp49
 377     0xb1810071, // for qp50
 378     0x89590049  // for qp51
 379 };
 380
 381 static void gen75_vme_state_setup_fixup(VADriverContextP ctx,
 382                                         struct encode_state *encode_state,
 383                                         struct intel_encoder_context *encoder_context,
 384                                         unsigned int *vme_state_message)
 385 {
 386     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 387     VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 388     VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 389
 390     if (slice_param->slice_type != SLICE_TYPE_I &&
 391         slice_param->slice_type != SLICE_TYPE_SI)
 392         return;
 393     if (encoder_context->rate_control_mode == VA_RC_CQP)
 394         vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
 395     else
 396         vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[slice_param->slice_type].QpPrimeY];
 397 }
 398
 399 static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
 400                                           struct encode_state *encode_state,
 401                                           int is_intra,
 402                                           struct intel_encoder_context *encoder_context)
 403 {
 404     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 405     unsigned int *vme_state_message;
 406     int i;
 407
 408     //pass the MV/Mb cost into VME message on HASWell
 409     assert(vme_context->vme_state_message);
 410     vme_state_message = (unsigned int *)vme_context->vme_state_message;
 411
 412     vme_state_message[0] = 0x4a4a4a4a;
 413     vme_state_message[1] = 0x4a4a4a4a;
 414     vme_state_message[2] = 0x4a4a4a4a;
 415     vme_state_message[3] = 0x22120200;
 416     vme_state_message[4] = 0x62524232;
 417
 418     for (i=5; i < 8; i++) {
 419         vme_state_message[i] = 0;
 420     }
 421
 422     gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
 423
 424     return VA_STATUS_SUCCESS;
 425 }
 426
 427 static void
 428 gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 429                                struct encode_state *encode_state,
 430                                int mb_width, int mb_height,
 431                                int kernel,
 432                                int transform_8x8_mode_flag,
 433                                struct intel_encoder_context *encoder_context)
 434 {
 435     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 436     int mb_x = 0, mb_y = 0;
 437     int i, s;
 438     unsigned int *command_ptr;
 439
 440 #define         INTRA_PRED_AVAIL_FLAG_AE        0x60
 441 #define         INTRA_PRED_AVAIL_FLAG_B         0x10
 442 #define         INTRA_PRED_AVAIL_FLAG_C         0x8
 443 #define         INTRA_PRED_AVAIL_FLAG_D         0x4
 444 #define         INTRA_PRED_AVAIL_FLAG_BCD_MASK  0x1C
 445
 446     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 447     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 448
 449     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 450         VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 451         int slice_mb_begin = pSliceParameter->macroblock_address;
 452         int slice_mb_number = pSliceParameter->num_macroblocks;
 453         unsigned int mb_intra_ub;
 454         int slice_mb_x = pSliceParameter->macroblock_address % mb_width;
 455         for (i = 0; i < slice_mb_number;  ) {
 456             int mb_count = i + slice_mb_begin;
 457             mb_x = mb_count % mb_width;
 458             mb_y = mb_count / mb_width;
 459             mb_intra_ub = 0;
 460             if (mb_x != 0) {
 461                 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
 462             }
 463             if (mb_y != 0) {
 464                 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
 465                 if (mb_x != 0)
 466                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
 467                 if (mb_x != (mb_width -1))
 468                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
 469             }
 470             if (i < mb_width) {
 471                 if (i == 0)
 472                     mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
 473                 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
 474                 if ((i == (mb_width - 1)) && slice_mb_x) {
 475                     mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
 476                 }
 477             }
 478
 479             if ((i == mb_width) && slice_mb_x) {
 480                 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
 481             }
 482             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 483             *command_ptr++ = kernel;
 484             *command_ptr++ = 0;
 485             *command_ptr++ = 0;
 486             *command_ptr++ = 0;
 487             *command_ptr++ = 0;
 488
 489             /*inline data */
 490             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 491             *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
 492
 493             i += 1;
 494         }
 495     }
 496
 497     *command_ptr++ = 0;
 498     *command_ptr++ = MI_BATCH_BUFFER_END;
 499
 500     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 501 }
 502
 503 static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 504 {
 505     struct i965_driver_data *i965 = i965_driver_data(ctx);
 506     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 507     dri_bo *bo;
 508
 509     i965_gpe_context_init(ctx, &vme_context->gpe_context);
 510
 511     /* VME output buffer */
 512     dri_bo_unreference(vme_context->vme_output.bo);
 513     vme_context->vme_output.bo = NULL;
 514
 515     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 516     vme_context->vme_batchbuffer.bo = NULL;
 517
 518     /* VME state */
 519     dri_bo_unreference(vme_context->vme_state.bo);
 520     vme_context->vme_state.bo = NULL;
 521 }
 522
 523 static void gen75_vme_pipeline_programing(VADriverContextP ctx,
 524                                           struct encode_state *encode_state,
 525                                           struct intel_encoder_context *encoder_context)
 526 {
 527     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 528     struct intel_batchbuffer *batch = encoder_context->base.batch;
 529     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 530     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 531     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 532     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 533     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 534     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 535
 536     gen75_vme_fill_vme_batchbuffer(ctx,
 537                                    encode_state,
 538                                    width_in_mbs, height_in_mbs,
 539                                    is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
 540                                    pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 541                                    encoder_context);
 542
 543     intel_batchbuffer_start_atomic(batch, 0x1000);
 544     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 545     BEGIN_BATCH(batch, 2);
 546     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 547     OUT_RELOC(batch,
 548               vme_context->vme_batchbuffer.bo,
 549               I915_GEM_DOMAIN_COMMAND, 0,
 550               0);
 551     ADVANCE_BATCH(batch);
 552
 553     intel_batchbuffer_end_atomic(batch);
 554 }
 555
 556 static VAStatus gen75_vme_prepare(VADriverContextP ctx,
 557                                   struct encode_state *encode_state,
 558                                   struct intel_encoder_context *encoder_context)
 559 {
 560     VAStatus vaStatus = VA_STATUS_SUCCESS;
 561     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 562     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 563     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 564     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 565
 566     if (!vme_context->h264_level ||
 567         (vme_context->h264_level != pSequenceParameter->level_idc)) {
 568         vme_context->h264_level = pSequenceParameter->level_idc;
 569     }
 570
 571     intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
 572
 573     /*Setup all the memory object*/
 574     gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
 575     gen75_vme_interface_setup(ctx, encode_state, encoder_context);
 576     //gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
 577     gen75_vme_constant_setup(ctx, encode_state, encoder_context);
 578
 579     /*Programing media pipeline*/
 580     gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
 581
 582     return vaStatus;
 583 }
 584
 585 static VAStatus gen75_vme_run(VADriverContextP ctx,
 586                               struct encode_state *encode_state,
 587                               struct intel_encoder_context *encoder_context)
 588 {
 589     struct intel_batchbuffer *batch = encoder_context->base.batch;
 590
 591     intel_batchbuffer_flush(batch);
 592
 593     return VA_STATUS_SUCCESS;
 594 }
 595
 596 static VAStatus gen75_vme_stop(VADriverContextP ctx,
 597                                struct encode_state *encode_state,
 598                                struct intel_encoder_context *encoder_context)
 599 {
 600     return VA_STATUS_SUCCESS;
 601 }
 602
 603 static VAStatus
 604 gen75_vme_pipeline(VADriverContextP ctx,
 605                    VAProfile profile,
 606                    struct encode_state *encode_state,
 607                    struct intel_encoder_context *encoder_context)
 608 {
 609     gen75_vme_media_init(ctx, encoder_context);
 610     gen75_vme_prepare(ctx, encode_state, encoder_context);
 611     gen75_vme_run(ctx, encode_state, encoder_context);
 612     gen75_vme_stop(ctx, encode_state, encoder_context);
 613
 614     return VA_STATUS_SUCCESS;
 615 }
 616
 617 static void
 618 gen75_vme_context_destroy(void *context)
 619 {
 620     struct gen6_vme_context *vme_context = context;
 621
 622     i965_gpe_context_destroy(&vme_context->gpe_context);
 623
 624     dri_bo_unreference(vme_context->vme_output.bo);
 625     vme_context->vme_output.bo = NULL;
 626
 627     dri_bo_unreference(vme_context->vme_state.bo);
 628     vme_context->vme_state.bo = NULL;
 629
 630     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 631     vme_context->vme_batchbuffer.bo = NULL;
 632
 633     if (vme_context->vme_state_message) {
 634         free(vme_context->vme_state_message);
 635         vme_context->vme_state_message = NULL;
 636     }
 637
 638     free(vme_context);
 639 }
 640
 641 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 642 {
 643     struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
 644
 645     vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
 646
 647     vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
 648     vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
 649
 650     vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
 651
 652     vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
 653     vme_context->gpe_context.vfe_state.num_urb_entries = 16;
 654     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
 655     vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
 656     vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
 657
 658     i965_gpe_load_kernels(ctx,
 659                           &vme_context->gpe_context,
 660                           gen75_vme_kernels,
 661                           GEN6_VME_KERNEL_NUMBER);
 662     vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
 663     vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
 664     vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
 665     vme_context->vme_media_chroma_surface_setup = gen75_gpe_media_chroma_surface_setup;
 666
 667     encoder_context->vme_context = vme_context;
 668     encoder_context->vme_context_destroy = gen75_vme_context_destroy;
 669     encoder_context->vme_pipeline = gen75_vme_pipeline;
 670
 671     vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));
 672     return True;
 673 }