2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
37 #include "i965_defines.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
45 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32)
48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32)
49 #define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
51 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
52 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
53 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
55 #define VME_INTRA_SHADER 0
56 #define VME_INTER_SHADER 1
57 #define VME_BATCHBUFFER 2
59 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
60 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
61 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
63 #define VME_MSG_LENGTH 32
65 static const uint32_t gen75_vme_intra_frame[][4] = {
66 #include "shaders/vme/intra_frame_haswell.g75b"
69 static const uint32_t gen75_vme_inter_frame[][4] = {
70 #include "shaders/vme/inter_frame_haswell.g75b"
73 static const uint32_t gen75_vme_batchbuffer[][4] = {
74 #include "shaders/vme/batchbuffer.g75b"
77 static struct i965_kernel gen75_vme_kernels[] = {
80 VME_INTRA_SHADER, /*index*/
81 gen75_vme_intra_frame,
82 sizeof(gen75_vme_intra_frame),
88 gen75_vme_inter_frame,
89 sizeof(gen75_vme_inter_frame),
95 gen75_vme_batchbuffer,
96 sizeof(gen75_vme_batchbuffer),
101 static const uint32_t gen75_vme_mpeg2_intra_frame[][4] = {
102 #include "shaders/vme/intra_frame_haswell.g75b"
105 static const uint32_t gen75_vme_mpeg2_inter_frame[][4] = {
106 #include "shaders/vme/inter_frame_haswell.g75b"
109 static const uint32_t gen75_vme_mpeg2_batchbuffer[][4] = {
110 #include "shaders/vme/batchbuffer.g75b"
113 static struct i965_kernel gen75_vme_mpeg2_kernels[] = {
116 VME_INTRA_SHADER, /*index*/
117 gen75_vme_mpeg2_intra_frame,
118 sizeof(gen75_vme_mpeg2_intra_frame),
124 gen75_vme_mpeg2_inter_frame,
125 sizeof(gen75_vme_mpeg2_inter_frame),
131 gen75_vme_mpeg2_batchbuffer,
132 sizeof(gen75_vme_mpeg2_batchbuffer),
137 /* only used for VME source surface state */
139 gen75_vme_source_surface_state(VADriverContextP ctx,
141 struct object_surface *obj_surface,
142 struct intel_encoder_context *encoder_context)
144 struct gen6_vme_context *vme_context = encoder_context->vme_context;
146 vme_context->vme_surface2_setup(ctx,
147 &vme_context->gpe_context,
149 BINDING_TABLE_OFFSET(index),
150 SURFACE_STATE_OFFSET(index));
154 gen75_vme_media_source_surface_state(VADriverContextP ctx,
156 struct object_surface *obj_surface,
157 struct intel_encoder_context *encoder_context)
159 struct gen6_vme_context *vme_context = encoder_context->vme_context;
161 vme_context->vme_media_rw_surface_setup(ctx,
162 &vme_context->gpe_context,
164 BINDING_TABLE_OFFSET(index),
165 SURFACE_STATE_OFFSET(index));
169 gen75_vme_media_chroma_source_surface_state(VADriverContextP ctx,
171 struct object_surface *obj_surface,
172 struct intel_encoder_context *encoder_context)
174 struct gen6_vme_context *vme_context = encoder_context->vme_context;
176 vme_context->vme_media_chroma_surface_setup(ctx,
177 &vme_context->gpe_context,
179 BINDING_TABLE_OFFSET(index),
180 SURFACE_STATE_OFFSET(index));
184 gen75_vme_output_buffer_setup(VADriverContextP ctx,
185 struct encode_state *encode_state,
187 struct intel_encoder_context *encoder_context)
190 struct i965_driver_data *i965 = i965_driver_data(ctx);
191 struct gen6_vme_context *vme_context = encoder_context->vme_context;
192 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
193 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
194 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
195 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
196 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
198 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
199 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
202 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
204 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
206 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
207 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
208 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
211 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
213 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
215 assert(vme_context->vme_output.bo);
216 vme_context->vme_buffer_suface_setup(ctx,
217 &vme_context->gpe_context,
218 &vme_context->vme_output,
219 BINDING_TABLE_OFFSET(index),
220 SURFACE_STATE_OFFSET(index));
224 gen75_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
225 struct encode_state *encode_state,
227 struct intel_encoder_context *encoder_context)
230 struct i965_driver_data *i965 = i965_driver_data(ctx);
231 struct gen6_vme_context *vme_context = encoder_context->vme_context;
232 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
233 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
234 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
236 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
237 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
238 vme_context->vme_batchbuffer.pitch = 16;
239 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
241 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
243 vme_context->vme_buffer_suface_setup(ctx,
244 &vme_context->gpe_context,
245 &vme_context->vme_batchbuffer,
246 BINDING_TABLE_OFFSET(index),
247 SURFACE_STATE_OFFSET(index));
251 gen75_vme_surface_setup(VADriverContextP ctx,
252 struct encode_state *encode_state,
254 struct intel_encoder_context *encoder_context)
256 struct i965_driver_data *i965 = i965_driver_data(ctx);
257 struct object_surface *obj_surface;
258 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
260 /*Setup surfaces state*/
261 /* current picture for encoding */
262 obj_surface = SURFACE(encoder_context->input_yuv_surface);
264 gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
265 gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
266 gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
270 obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
272 if ( obj_surface->bo != NULL)
273 gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
276 obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
278 if ( obj_surface->bo != NULL )
279 gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
283 gen75_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
284 gen75_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
286 return VA_STATUS_SUCCESS;
289 static VAStatus gen75_vme_interface_setup(VADriverContextP ctx,
290 struct encode_state *encode_state,
291 struct intel_encoder_context *encoder_context)
293 struct gen6_vme_context *vme_context = encoder_context->vme_context;
294 struct gen6_interface_descriptor_data *desc;
298 bo = vme_context->gpe_context.idrt.bo;
303 for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
304 struct i965_kernel *kernel;
305 kernel = &vme_context->gpe_context.kernels[i];
306 assert(sizeof(*desc) == 32);
307 /*Setup the descritor table*/
308 memset(desc, 0, sizeof(*desc));
309 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
310 desc->desc2.sampler_count = 0; /* FIXME: */
311 desc->desc2.sampler_state_pointer = 0;
312 desc->desc3.binding_table_entry_count = 1; /* FIXME: */
313 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
314 desc->desc4.constant_urb_entry_read_offset = 0;
315 desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
318 dri_bo_emit_reloc(bo,
319 I915_GEM_DOMAIN_INSTRUCTION, 0,
321 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
327 return VA_STATUS_SUCCESS;
330 static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
331 struct encode_state *encode_state,
332 struct intel_encoder_context *encoder_context)
334 struct gen6_vme_context *vme_context = encoder_context->vme_context;
335 unsigned char *constant_buffer;
336 unsigned int *vme_state_message;
339 vme_state_message = (unsigned int *)vme_context->vme_state_message;
341 if (encoder_context->profile == VAProfileH264Baseline ||
342 encoder_context->profile == VAProfileH264Main ||
343 encoder_context->profile == VAProfileH264High) {
344 if (vme_context->h264_level >= 30) {
347 if (vme_context->h264_level >= 31)
350 } else if (encoder_context->profile == VAProfileMPEG2Simple ||
351 encoder_context->profile == VAProfileMPEG2Main) {
355 vme_state_message[31] = mv_num;
357 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
358 assert(vme_context->gpe_context.curbe.bo->virtual);
359 constant_buffer = vme_context->gpe_context.curbe.bo->virtual;
361 /* VME MV/Mb cost table is passed by using const buffer */
362 /* Now it uses the fixed search path. So it is constructed directly
365 memcpy(constant_buffer, (char *)vme_context->vme_state_message, 128);
367 dri_bo_unmap(vme_context->gpe_context.curbe.bo);
369 return VA_STATUS_SUCCESS;
372 static const unsigned int intra_mb_mode_cost_table[] = {
373 0x31110001, // for qp0
374 0x09110001, // for qp1
375 0x15030001, // for qp2
376 0x0b030001, // for qp3
377 0x0d030011, // for qp4
378 0x17210011, // for qp5
379 0x41210011, // for qp6
380 0x19210011, // for qp7
381 0x25050003, // for qp8
382 0x1b130003, // for qp9
383 0x1d130003, // for qp10
384 0x27070021, // for qp11
385 0x51310021, // for qp12
386 0x29090021, // for qp13
387 0x35150005, // for qp14
388 0x2b0b0013, // for qp15
389 0x2d0d0013, // for qp16
390 0x37170007, // for qp17
391 0x61410031, // for qp18
392 0x39190009, // for qp19
393 0x45250015, // for qp20
394 0x3b1b000b, // for qp21
395 0x3d1d000d, // for qp22
396 0x47270017, // for qp23
397 0x71510041, // for qp24 ! center for qp=0..30
398 0x49290019, // for qp25
399 0x55350025, // for qp26
400 0x4b2b001b, // for qp27
401 0x4d2d001d, // for qp28
402 0x57370027, // for qp29
403 0x81610051, // for qp30
404 0x57270017, // for qp31
405 0x81510041, // for qp32 ! center for qp=31..51
406 0x59290019, // for qp33
407 0x65350025, // for qp34
408 0x5b2b001b, // for qp35
409 0x5d2d001d, // for qp36
410 0x67370027, // for qp37
411 0x91610051, // for qp38
412 0x69390029, // for qp39
413 0x75450035, // for qp40
414 0x6b3b002b, // for qp41
415 0x6d3d002d, // for qp42
416 0x77470037, // for qp43
417 0xa1710061, // for qp44
418 0x79490039, // for qp45
419 0x85550045, // for qp46
420 0x7b4b003b, // for qp47
421 0x7d4d003d, // for qp48
422 0x87570047, // for qp49
423 0xb1810071, // for qp50
424 0x89590049 // for qp51
427 static void gen75_vme_state_setup_fixup(VADriverContextP ctx,
428 struct encode_state *encode_state,
429 struct intel_encoder_context *encoder_context,
430 unsigned int *vme_state_message)
432 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
433 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
434 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
436 if (slice_param->slice_type != SLICE_TYPE_I &&
437 slice_param->slice_type != SLICE_TYPE_SI)
439 if (encoder_context->rate_control_mode == VA_RC_CQP)
440 vme_state_message[0] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
442 vme_state_message[0] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[slice_param->slice_type].QpPrimeY];
445 static VAStatus gen75_vme_vme_state_setup(VADriverContextP ctx,
446 struct encode_state *encode_state,
448 struct intel_encoder_context *encoder_context)
450 struct gen6_vme_context *vme_context = encoder_context->vme_context;
451 unsigned int *vme_state_message;
454 //pass the MV/Mb cost into VME message on HASWell
455 assert(vme_context->vme_state_message);
456 vme_state_message = (unsigned int *)vme_context->vme_state_message;
458 vme_state_message[0] = 0x4a4a4a4a;
459 vme_state_message[1] = 0x4a4a4a4a;
460 vme_state_message[2] = 0x4a4a4a4a;
461 vme_state_message[3] = 0x22120200;
462 vme_state_message[4] = 0x62524232;
464 for (i=5; i < 8; i++) {
465 vme_state_message[i] = 0;
468 switch (encoder_context->profile) {
469 case VAProfileH264Baseline:
470 case VAProfileH264Main:
471 case VAProfileH264High:
472 gen75_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
481 return VA_STATUS_SUCCESS;
485 gen75_vme_fill_vme_batchbuffer(VADriverContextP ctx,
486 struct encode_state *encode_state,
487 int mb_width, int mb_height,
489 int transform_8x8_mode_flag,
490 struct intel_encoder_context *encoder_context)
492 struct gen6_vme_context *vme_context = encoder_context->vme_context;
493 int mb_x = 0, mb_y = 0;
495 unsigned int *command_ptr;
497 #define INTRA_PRED_AVAIL_FLAG_AE 0x60
498 #define INTRA_PRED_AVAIL_FLAG_B 0x10
499 #define INTRA_PRED_AVAIL_FLAG_C 0x8
500 #define INTRA_PRED_AVAIL_FLAG_D 0x4
501 #define INTRA_PRED_AVAIL_FLAG_BCD_MASK 0x1C
503 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
504 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
506 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
507 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
508 int slice_mb_begin = pSliceParameter->macroblock_address;
509 int slice_mb_number = pSliceParameter->num_macroblocks;
510 unsigned int mb_intra_ub;
511 int slice_mb_x = pSliceParameter->macroblock_address % mb_width;
512 for (i = 0; i < slice_mb_number; ) {
513 int mb_count = i + slice_mb_begin;
514 mb_x = mb_count % mb_width;
515 mb_y = mb_count / mb_width;
518 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
521 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
523 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
524 if (mb_x != (mb_width -1))
525 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
529 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
530 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
531 if ((i == (mb_width - 1)) && slice_mb_x) {
532 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
536 if ((i == mb_width) && slice_mb_x) {
537 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
539 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
540 *command_ptr++ = kernel;
547 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
548 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
555 *command_ptr++ = MI_BATCH_BUFFER_END;
557 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
560 static void gen75_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
562 struct i965_driver_data *i965 = i965_driver_data(ctx);
563 struct gen6_vme_context *vme_context = encoder_context->vme_context;
566 i965_gpe_context_init(ctx, &vme_context->gpe_context);
568 /* VME output buffer */
569 dri_bo_unreference(vme_context->vme_output.bo);
570 vme_context->vme_output.bo = NULL;
572 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
573 vme_context->vme_batchbuffer.bo = NULL;
576 dri_bo_unreference(vme_context->vme_state.bo);
577 vme_context->vme_state.bo = NULL;
580 static void gen75_vme_pipeline_programing(VADriverContextP ctx,
581 struct encode_state *encode_state,
582 struct intel_encoder_context *encoder_context)
584 struct gen6_vme_context *vme_context = encoder_context->vme_context;
585 struct intel_batchbuffer *batch = encoder_context->base.batch;
586 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
587 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
588 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
589 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
590 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
591 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
593 gen75_vme_fill_vme_batchbuffer(ctx,
595 width_in_mbs, height_in_mbs,
596 is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
597 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
600 intel_batchbuffer_start_atomic(batch, 0x1000);
601 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
602 BEGIN_BATCH(batch, 2);
603 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
605 vme_context->vme_batchbuffer.bo,
606 I915_GEM_DOMAIN_COMMAND, 0,
608 ADVANCE_BATCH(batch);
610 intel_batchbuffer_end_atomic(batch);
613 static VAStatus gen75_vme_prepare(VADriverContextP ctx,
614 struct encode_state *encode_state,
615 struct intel_encoder_context *encoder_context)
617 VAStatus vaStatus = VA_STATUS_SUCCESS;
618 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
619 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
620 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
621 struct gen6_vme_context *vme_context = encoder_context->vme_context;
623 if (!vme_context->h264_level ||
624 (vme_context->h264_level != pSequenceParameter->level_idc)) {
625 vme_context->h264_level = pSequenceParameter->level_idc;
628 intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
630 /*Setup all the memory object*/
631 gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
632 gen75_vme_interface_setup(ctx, encode_state, encoder_context);
633 //gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
634 gen75_vme_constant_setup(ctx, encode_state, encoder_context);
636 /*Programing media pipeline*/
637 gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
642 static VAStatus gen75_vme_run(VADriverContextP ctx,
643 struct encode_state *encode_state,
644 struct intel_encoder_context *encoder_context)
646 struct intel_batchbuffer *batch = encoder_context->base.batch;
648 intel_batchbuffer_flush(batch);
650 return VA_STATUS_SUCCESS;
653 static VAStatus gen75_vme_stop(VADriverContextP ctx,
654 struct encode_state *encode_state,
655 struct intel_encoder_context *encoder_context)
657 return VA_STATUS_SUCCESS;
661 gen75_vme_pipeline(VADriverContextP ctx,
663 struct encode_state *encode_state,
664 struct intel_encoder_context *encoder_context)
666 gen75_vme_media_init(ctx, encoder_context);
667 gen75_vme_prepare(ctx, encode_state, encoder_context);
668 gen75_vme_run(ctx, encode_state, encoder_context);
669 gen75_vme_stop(ctx, encode_state, encoder_context);
671 return VA_STATUS_SUCCESS;
675 gen75_vme_mpeg2_output_buffer_setup(VADriverContextP ctx,
676 struct encode_state *encode_state,
679 struct intel_encoder_context *encoder_context)
682 struct i965_driver_data *i965 = i965_driver_data(ctx);
683 struct gen6_vme_context *vme_context = encoder_context->vme_context;
684 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
685 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
686 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
688 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
689 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
692 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 2;
694 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES * 24;
696 * Inter MV . 32-byte Intra search + 16 IME info + 128 IME MV + 32 IME Ref
697 * + 16 FBR Info + 128 FBR MV + 32 FBR Ref.
698 * 16 * (2 + 2 * (1 + 8 + 2))= 16 * 24.
701 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
703 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
705 assert(vme_context->vme_output.bo);
706 vme_context->vme_buffer_suface_setup(ctx,
707 &vme_context->gpe_context,
708 &vme_context->vme_output,
709 BINDING_TABLE_OFFSET(index),
710 SURFACE_STATE_OFFSET(index));
714 gen75_vme_mpeg2_output_vme_batchbuffer_setup(VADriverContextP ctx,
715 struct encode_state *encode_state,
717 struct intel_encoder_context *encoder_context)
720 struct i965_driver_data *i965 = i965_driver_data(ctx);
721 struct gen6_vme_context *vme_context = encoder_context->vme_context;
722 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
723 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
724 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
726 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
727 vme_context->vme_batchbuffer.size_block = 64; /* 4 OWORDs */
728 vme_context->vme_batchbuffer.pitch = 16;
729 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
731 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
733 vme_context->vme_buffer_suface_setup(ctx,
734 &vme_context->gpe_context,
735 &vme_context->vme_batchbuffer,
736 BINDING_TABLE_OFFSET(index),
737 SURFACE_STATE_OFFSET(index));
741 gen75_vme_mpeg2_surface_setup(VADriverContextP ctx,
742 struct encode_state *encode_state,
744 struct intel_encoder_context *encoder_context)
746 struct i965_driver_data *i965 = i965_driver_data(ctx);
747 struct object_surface *obj_surface;
748 VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
750 /*Setup surfaces state*/
751 /* current picture for encoding */
752 obj_surface = SURFACE(encoder_context->input_yuv_surface);
754 gen75_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
755 gen75_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
756 gen75_vme_media_chroma_source_surface_state(ctx, 6, obj_surface, encoder_context);
760 obj_surface = SURFACE(pic_param->forward_reference_picture);
762 if ( obj_surface->bo != NULL)
763 gen75_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
766 obj_surface = SURFACE(pic_param->backward_reference_picture);
768 if ( obj_surface->bo != NULL )
769 gen75_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
773 gen75_vme_mpeg2_output_buffer_setup(ctx, encode_state, 3, is_intra, encoder_context);
774 gen75_vme_mpeg2_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
776 return VA_STATUS_SUCCESS;
780 gen75_vme_mpeg2_fill_vme_batchbuffer(VADriverContextP ctx,
781 struct encode_state *encode_state,
782 int mb_width, int mb_height,
784 int transform_8x8_mode_flag,
785 struct intel_encoder_context *encoder_context)
787 struct gen6_vme_context *vme_context = encoder_context->vme_context;
788 int mb_x = 0, mb_y = 0;
790 unsigned int *command_ptr;
792 #define INTRA_PRED_AVAIL_FLAG_AE 0x60
793 #define INTRA_PRED_AVAIL_FLAG_B 0x10
794 #define INTRA_PRED_AVAIL_FLAG_C 0x8
795 #define INTRA_PRED_AVAIL_FLAG_D 0x4
796 #define INTRA_PRED_AVAIL_FLAG_BCD_MASK 0x1C
798 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
799 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
801 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
802 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[s]->buffer;
804 for (j = 0; j < encode_state->slice_params_ext[s]->num_elements; j++) {
805 int slice_mb_begin = slice_param->macroblock_address;
806 int slice_mb_number = slice_param->num_macroblocks;
807 unsigned int mb_intra_ub;
808 int slice_mb_x = slice_param->macroblock_address % mb_width;
810 for (i = 0; i < slice_mb_number;) {
811 int mb_count = i + slice_mb_begin;
813 mb_x = mb_count % mb_width;
814 mb_y = mb_count / mb_width;
818 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_AE;
822 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_B;
825 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_D;
827 if (mb_x != (mb_width -1))
828 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
833 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_AE);
835 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_BCD_MASK);
837 if ((i == (mb_width - 1)) && slice_mb_x) {
838 mb_intra_ub |= INTRA_PRED_AVAIL_FLAG_C;
842 if ((i == mb_width) && slice_mb_x) {
843 mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
846 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
847 *command_ptr++ = kernel;
854 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
855 *command_ptr++ = ( (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
865 *command_ptr++ = MI_BATCH_BUFFER_END;
867 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
871 gen75_vme_mpeg2_pipeline_programing(VADriverContextP ctx,
872 struct encode_state *encode_state,
874 struct intel_encoder_context *encoder_context)
876 struct gen6_vme_context *vme_context = encoder_context->vme_context;
877 struct intel_batchbuffer *batch = encoder_context->base.batch;
878 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
879 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
880 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
882 gen75_vme_mpeg2_fill_vme_batchbuffer(ctx,
884 width_in_mbs, height_in_mbs,
885 is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
889 intel_batchbuffer_start_atomic(batch, 0x1000);
890 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
891 BEGIN_BATCH(batch, 2);
892 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
894 vme_context->vme_batchbuffer.bo,
895 I915_GEM_DOMAIN_COMMAND, 0,
897 ADVANCE_BATCH(batch);
899 intel_batchbuffer_end_atomic(batch);
903 gen75_vme_mpeg2_prepare(VADriverContextP ctx,
904 struct encode_state *encode_state,
905 struct intel_encoder_context *encoder_context)
907 VAStatus vaStatus = VA_STATUS_SUCCESS;
908 VAEncSliceParameterBufferMPEG2 *slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[0]->buffer;
910 /*Setup all the memory object*/
911 gen75_vme_mpeg2_surface_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
912 gen75_vme_interface_setup(ctx, encode_state, encoder_context);
913 gen75_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
914 gen75_vme_constant_setup(ctx, encode_state, encoder_context);
916 /*Programing media pipeline*/
917 gen75_vme_mpeg2_pipeline_programing(ctx, encode_state, slice_param->is_intra_slice, encoder_context);
923 gen75_vme_mpeg2_pipeline(VADriverContextP ctx,
925 struct encode_state *encode_state,
926 struct intel_encoder_context *encoder_context)
928 gen75_vme_media_init(ctx, encoder_context);
929 gen75_vme_mpeg2_prepare(ctx, encode_state, encoder_context);
930 gen75_vme_run(ctx, encode_state, encoder_context);
931 gen75_vme_stop(ctx, encode_state, encoder_context);
933 return VA_STATUS_SUCCESS;
937 gen75_vme_context_destroy(void *context)
939 struct gen6_vme_context *vme_context = context;
941 i965_gpe_context_destroy(&vme_context->gpe_context);
943 dri_bo_unreference(vme_context->vme_output.bo);
944 vme_context->vme_output.bo = NULL;
946 dri_bo_unreference(vme_context->vme_state.bo);
947 vme_context->vme_state.bo = NULL;
949 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
950 vme_context->vme_batchbuffer.bo = NULL;
952 if (vme_context->vme_state_message) {
953 free(vme_context->vme_state_message);
954 vme_context->vme_state_message = NULL;
960 Bool gen75_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
962 struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
963 struct i965_kernel *vme_kernel_list = NULL;
965 switch (encoder_context->profile) {
966 case VAProfileH264Baseline:
967 case VAProfileH264Main:
968 case VAProfileH264High:
969 vme_kernel_list = gen75_vme_kernels;
970 encoder_context->vme_pipeline = gen75_vme_pipeline;
974 case VAProfileMPEG2Simple:
975 case VAProfileMPEG2Main:
976 vme_kernel_list = gen75_vme_mpeg2_kernels;
977 encoder_context->vme_pipeline = gen75_vme_mpeg2_pipeline;
988 vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
990 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
991 vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
993 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
995 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
996 vme_context->gpe_context.vfe_state.num_urb_entries = 16;
997 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
998 vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
999 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
1001 i965_gpe_load_kernels(ctx,
1002 &vme_context->gpe_context,
1004 GEN6_VME_KERNEL_NUMBER);
1005 vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
1006 vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
1007 vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
1008 vme_context->vme_media_chroma_surface_setup = gen75_gpe_media_chroma_surface_setup;
1010 encoder_context->vme_context = vme_context;
1011 encoder_context->vme_context_destroy = gen75_vme_context_destroy;
1013 vme_context->vme_state_message = malloc(VME_MSG_LENGTH * sizeof(int));