src/gen75_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zhao  Yakui  <yakui.zhao@intel.com>
  27  *
  28  */
  29
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include <assert.h>
  34 #include <va/va_dec_jpeg.h>
  35
  36 #include "intel_batchbuffer.h"
  37 #include "intel_driver.h"
  38
  39 #include "i965_defines.h"
  40 #include "i965_drv_video.h"
  41 #include "i965_decoder_utils.h"
  42
  43 #include "gen7_mfd.h"
  44
  45 #define B0_STEP_REV             2
  46 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
  47
  48 static const uint32_t zigzag_direct[64] = {
  49     0,   1,  8, 16,  9,  2,  3, 10,
  50     17, 24, 32, 25, 18, 11,  4,  5,
  51     12, 19, 26, 33, 40, 48, 41, 34,
  52     27, 20, 13,  6,  7, 14, 21, 28,
  53     35, 42, 49, 56, 57, 50, 43, 36,
  54     29, 22, 15, 23, 30, 37, 44, 51,
  55     58, 59, 52, 45, 38, 31, 39, 46,
  56     53, 60, 61, 54, 47, 55, 62, 63
  57 };
  58
  59 static void
  60 gen75_mfd_avc_frame_store_index(VADriverContextP ctx,
  61                                VAPictureParameterBufferH264 *pic_param,
  62                                struct gen7_mfd_context *gen7_mfd_context)
  63 {
  64     struct i965_driver_data *i965 = i965_driver_data(ctx);
  65     int i, j;
  66
  67     assert(ARRAY_ELEMS(gen7_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
  68
  69     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
  70         int found = 0;
  71
  72         if (gen7_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
  73             continue;
  74
  75         for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
  76             VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
  77             if (ref_pic->flags & VA_PICTURE_H264_INVALID)
  78                 continue;
  79
  80             if (gen7_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
  81                 found = 1;
  82                 break;
  83             }
  84         }
  85
  86         if (!found) {
  87             struct object_surface *obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
  88             obj_surface->flags &= ~SURFACE_REFERENCED;
  89
  90             if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
  91                 dri_bo_unreference(obj_surface->bo);
  92                 obj_surface->bo = NULL;
  93                 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
  94             }
  95
  96             if (obj_surface->free_private_data)
  97                 obj_surface->free_private_data(&obj_surface->private_data);
  98
  99             gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
 100             gen7_mfd_context->reference_surface[i].frame_store_id = -1;
 101         }
 102     }
 103
 104     for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
 105         VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
 106         int found = 0;
 107
 108         if (ref_pic->flags & VA_PICTURE_H264_INVALID)
 109             continue;
 110
 111         for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 112             if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 113                 continue;
 114
 115             if (gen7_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
 116                 found = 1;
 117                 break;
 118             }
 119         }
 120
 121         if (!found) {
 122             int frame_idx;
 123             struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
 124
 125             assert(obj_surface);
 126             i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 127
 128             for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface); frame_idx++) {
 129                 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 130                     if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 131                         continue;
 132
 133                     if (gen7_mfd_context->reference_surface[j].frame_store_id == frame_idx)
 134                         break;
 135                 }
 136
 137                 if (j == ARRAY_ELEMS(gen7_mfd_context->reference_surface))
 138                     break;
 139             }
 140
 141             assert(frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface));
 142
 143             for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 144                 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
 145                     gen7_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
 146                     gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 147                     break;
 148                 }
 149             }
 150         }
 151     }
 152
 153     /* sort */
 154     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface) - 1; i++) {
 155         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 156             gen7_mfd_context->reference_surface[i].frame_store_id == i)
 157             continue;
 158
 159         for (j = i + 1; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 160             if (gen7_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
 161                 gen7_mfd_context->reference_surface[j].frame_store_id == i) {
 162                 VASurfaceID id = gen7_mfd_context->reference_surface[i].surface_id;
 163                 int frame_idx = gen7_mfd_context->reference_surface[i].frame_store_id;
 164
 165                 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[j].surface_id;
 166                 gen7_mfd_context->reference_surface[i].frame_store_id = gen7_mfd_context->reference_surface[j].frame_store_id;
 167                 gen7_mfd_context->reference_surface[j].surface_id = id;
 168                 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 169                 break;
 170             }
 171         }
 172     }
 173 }
 174
 175 static void
 176 gen75_mfd_free_avc_surface(void **data)
 177 {
 178     struct gen7_avc_surface *gen7_avc_surface = *data;
 179
 180     if (!gen7_avc_surface)
 181         return;
 182
 183     dri_bo_unreference(gen7_avc_surface->dmv_top);
 184     gen7_avc_surface->dmv_top = NULL;
 185     dri_bo_unreference(gen7_avc_surface->dmv_bottom);
 186     gen7_avc_surface->dmv_bottom = NULL;
 187
 188     free(gen7_avc_surface);
 189     *data = NULL;
 190 }
 191
 192 static void
 193 gen75_mfd_init_avc_surface(VADriverContextP ctx,
 194                           VAPictureParameterBufferH264 *pic_param,
 195                           struct object_surface *obj_surface)
 196 {
 197     struct i965_driver_data *i965 = i965_driver_data(ctx);
 198     struct gen7_avc_surface *gen7_avc_surface = obj_surface->private_data;
 199     int width_in_mbs, height_in_mbs;
 200
 201     obj_surface->free_private_data = gen75_mfd_free_avc_surface;
 202     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 203     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 204
 205     if (!gen7_avc_surface) {
 206         gen7_avc_surface = calloc(sizeof(struct gen7_avc_surface), 1);
 207         assert((obj_surface->size & 0x3f) == 0);
 208         obj_surface->private_data = gen7_avc_surface;
 209     }
 210
 211     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
 212                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
 213
 214     if (gen7_avc_surface->dmv_top == NULL) {
 215         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
 216                                                  "direct mv w/r buffer",
 217                                                  width_in_mbs * height_in_mbs * 128,
 218                                                  0x1000);
 219         assert(gen7_avc_surface->dmv_top);
 220     }
 221
 222     if (gen7_avc_surface->dmv_bottom_flag &&
 223         gen7_avc_surface->dmv_bottom == NULL) {
 224         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
 225                                                     "direct mv w/r buffer",
 226                                                     width_in_mbs * height_in_mbs * 128,
 227                                                     0x1000);
 228         assert(gen7_avc_surface->dmv_bottom);
 229     }
 230 }
 231
 232 static void
 233 gen75_mfd_pipe_mode_select(VADriverContextP ctx,
 234                           struct decode_state *decode_state,
 235                           int standard_select,
 236                           struct gen7_mfd_context *gen7_mfd_context)
 237 {
 238     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 239
 240     assert(standard_select == MFX_FORMAT_MPEG2 ||
 241            standard_select == MFX_FORMAT_AVC ||
 242            standard_select == MFX_FORMAT_VC1 ||
 243            standard_select == MFX_FORMAT_JPEG);
 244
 245     BEGIN_BCS_BATCH(batch, 5);
 246     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 247     OUT_BCS_BATCH(batch,
 248                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 249                   (MFD_MODE_VLD << 15) | /* VLD mode */
 250                   (0 << 10) | /* disable Stream-Out */
 251                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 252                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 253                   (0 << 5)  | /* not in stitch mode */
 254                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 255                   (standard_select << 0));
 256     OUT_BCS_BATCH(batch,
 257                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 258                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 259                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 260                   (0 << 1)  |
 261                   (0 << 0));
 262     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 263     OUT_BCS_BATCH(batch, 0); /* reserved */
 264     ADVANCE_BCS_BATCH(batch);
 265 }
 266
 267 static void
 268 gen75_mfd_surface_state(VADriverContextP ctx,
 269                        struct decode_state *decode_state,
 270                        int standard_select,
 271                        struct gen7_mfd_context *gen7_mfd_context)
 272 {
 273     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 274     struct i965_driver_data *i965 = i965_driver_data(ctx);
 275     struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
 276     unsigned int y_cb_offset;
 277     unsigned int y_cr_offset;
 278
 279     assert(obj_surface);
 280
 281     y_cb_offset = obj_surface->y_cb_offset;
 282     y_cr_offset = obj_surface->y_cr_offset;
 283
 284     BEGIN_BCS_BATCH(batch, 6);
 285     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 286     OUT_BCS_BATCH(batch, 0);
 287     OUT_BCS_BATCH(batch,
 288                   ((obj_surface->orig_height - 1) << 18) |
 289                   ((obj_surface->orig_width - 1) << 4));
 290     OUT_BCS_BATCH(batch,
 291                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 292                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 293                   (0 << 22) | /* surface object control state, ignored */
 294                   ((obj_surface->width - 1) << 3) | /* pitch */
 295                   (0 << 2)  | /* must be 0 */
 296                   (1 << 1)  | /* must be tiled */
 297                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 298     OUT_BCS_BATCH(batch,
 299                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 300                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 301     OUT_BCS_BATCH(batch,
 302                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 303                   (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 304     ADVANCE_BCS_BATCH(batch);
 305 }
 306
 307 static void
 308 gen75_mfd_pipe_buf_addr_state_bplus(VADriverContextP ctx,
 309                              struct decode_state *decode_state,
 310                              int standard_select,
 311                              struct gen7_mfd_context *gen7_mfd_context)
 312 {
 313     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 314     struct i965_driver_data *i965 = i965_driver_data(ctx);
 315     int i;
 316
 317     BEGIN_BCS_BATCH(batch, 61);
 318     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
 319         /* Pre-deblock 1-3 */
 320     if (gen7_mfd_context->pre_deblocking_output.valid)
 321         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 322                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 323                       0);
 324     else
 325         OUT_BCS_BATCH(batch, 0);
 326
 327         OUT_BCS_BATCH(batch, 0);
 328         OUT_BCS_BATCH(batch, 0);
 329         /* Post-debloing 4-6 */
 330     if (gen7_mfd_context->post_deblocking_output.valid)
 331         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 332                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 333                       0);
 334     else
 335         OUT_BCS_BATCH(batch, 0);
 336
 337         OUT_BCS_BATCH(batch, 0);
 338         OUT_BCS_BATCH(batch, 0);
 339
 340         /* uncompressed-video & stream out 7-12 */
 341     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 342     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 343         OUT_BCS_BATCH(batch, 0);
 344         OUT_BCS_BATCH(batch, 0);
 345         OUT_BCS_BATCH(batch, 0);
 346         OUT_BCS_BATCH(batch, 0);
 347
 348         /* intra row-store scratch 13-15 */
 349     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 350         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 351                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 352                       0);
 353     else
 354         OUT_BCS_BATCH(batch, 0);
 355
 356         OUT_BCS_BATCH(batch, 0);
 357         OUT_BCS_BATCH(batch, 0);
 358         /* deblocking-filter-row-store 16-18 */
 359     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 360         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 361                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 362                       0);
 363     else
 364         OUT_BCS_BATCH(batch, 0);
 365         OUT_BCS_BATCH(batch, 0);
 366         OUT_BCS_BATCH(batch, 0);
 367
 368     /* DW 19..50 */
 369     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 370         struct object_surface *obj_surface;
 371
 372         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 373             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 374             assert(obj_surface && obj_surface->bo);
 375
 376             OUT_BCS_RELOC(batch, obj_surface->bo,
 377                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 378                           0);
 379         } else {
 380             OUT_BCS_BATCH(batch, 0);
 381         }
 382             OUT_BCS_BATCH(batch, 0);
 383     }
 384         /* reference property 51 */
 385     OUT_BCS_BATCH(batch, 0);
 386
 387         /* Macroblock status & ILDB 52-57 */
 388         OUT_BCS_BATCH(batch, 0);
 389         OUT_BCS_BATCH(batch, 0);
 390         OUT_BCS_BATCH(batch, 0);
 391         OUT_BCS_BATCH(batch, 0);
 392         OUT_BCS_BATCH(batch, 0);
 393         OUT_BCS_BATCH(batch, 0);
 394
 395         /* the second Macroblock status 58-60 */
 396         OUT_BCS_BATCH(batch, 0);
 397         OUT_BCS_BATCH(batch, 0);
 398         OUT_BCS_BATCH(batch, 0);
 399     ADVANCE_BCS_BATCH(batch);
 400 }
 401
 402 static void
 403 gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 404                              struct decode_state *decode_state,
 405                              int standard_select,
 406                              struct gen7_mfd_context *gen7_mfd_context)
 407 {
 408     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 409     struct i965_driver_data *i965 = i965_driver_data(ctx);
 410     int i;
 411
 412         if (IS_STEPPING_BPLUS(i965)) {
 413                 gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state,
 414                                 standard_select, gen7_mfd_context);
 415                 return;
 416         }
 417     BEGIN_BCS_BATCH(batch, 25);
 418     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
 419     if (gen7_mfd_context->pre_deblocking_output.valid)
 420         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 421                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 422                       0);
 423     else
 424         OUT_BCS_BATCH(batch, 0);
 425
 426     if (gen7_mfd_context->post_deblocking_output.valid)
 427         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 428                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 429                       0);
 430     else
 431         OUT_BCS_BATCH(batch, 0);
 432
 433     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 434     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 435
 436     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 437         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 438                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 439                       0);
 440     else
 441         OUT_BCS_BATCH(batch, 0);
 442
 443     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 444         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 445                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 446                       0);
 447     else
 448         OUT_BCS_BATCH(batch, 0);
 449
 450     /* DW 7..22 */
 451     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 452         struct object_surface *obj_surface;
 453
 454         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 455             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 456             assert(obj_surface && obj_surface->bo);
 457
 458             OUT_BCS_RELOC(batch, obj_surface->bo,
 459                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 460                           0);
 461         } else {
 462             OUT_BCS_BATCH(batch, 0);
 463         }
 464     }
 465
 466     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 467     OUT_BCS_BATCH(batch, 0);   /* ignore DW24 for decoding */
 468     ADVANCE_BCS_BATCH(batch);
 469 }
 470
 471 static void
 472 gen75_mfd_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
 473                                  dri_bo *slice_data_bo,
 474                                  int standard_select,
 475                                  struct gen7_mfd_context *gen7_mfd_context)
 476 {
 477     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 478
 479     BEGIN_BCS_BATCH(batch, 26);
 480     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
 481         /* MFX In BS 1-5 */
 482     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 483     OUT_BCS_BATCH(batch, 0);
 484     OUT_BCS_BATCH(batch, 0);
 485         /* Upper bound 4-5 */
 486     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 487     OUT_BCS_BATCH(batch, 0);
 488
 489         /* MFX indirect MV 6-10 */
 490     OUT_BCS_BATCH(batch, 0);
 491     OUT_BCS_BATCH(batch, 0);
 492     OUT_BCS_BATCH(batch, 0);
 493     OUT_BCS_BATCH(batch, 0);
 494     OUT_BCS_BATCH(batch, 0);
 495
 496         /* MFX IT_COFF 11-15 */
 497     OUT_BCS_BATCH(batch, 0);
 498     OUT_BCS_BATCH(batch, 0);
 499     OUT_BCS_BATCH(batch, 0);
 500     OUT_BCS_BATCH(batch, 0);
 501     OUT_BCS_BATCH(batch, 0);
 502
 503         /* MFX IT_DBLK 16-20 */
 504     OUT_BCS_BATCH(batch, 0);
 505     OUT_BCS_BATCH(batch, 0);
 506     OUT_BCS_BATCH(batch, 0);
 507     OUT_BCS_BATCH(batch, 0);
 508     OUT_BCS_BATCH(batch, 0);
 509
 510         /* MFX PAK_BSE object for encoder 21-25 */
 511     OUT_BCS_BATCH(batch, 0);
 512     OUT_BCS_BATCH(batch, 0);
 513     OUT_BCS_BATCH(batch, 0);
 514     OUT_BCS_BATCH(batch, 0);
 515     OUT_BCS_BATCH(batch, 0);
 516
 517     ADVANCE_BCS_BATCH(batch);
 518 }
 519
 520 static void
 521 gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 522                                  dri_bo *slice_data_bo,
 523                                  int standard_select,
 524                                  struct gen7_mfd_context *gen7_mfd_context)
 525 {
 526     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 527
 528     struct i965_driver_data *i965 = i965_driver_data(ctx);
 529
 530         if (IS_STEPPING_BPLUS(i965)) {
 531                 gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo,
 532                                         standard_select, gen7_mfd_context);
 533                 return;
 534         }
 535     BEGIN_BCS_BATCH(batch, 11);
 536     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 537     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 538     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 539     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 540     OUT_BCS_BATCH(batch, 0);
 541     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 542     OUT_BCS_BATCH(batch, 0);
 543     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 544     OUT_BCS_BATCH(batch, 0);
 545     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 546     OUT_BCS_BATCH(batch, 0);
 547     ADVANCE_BCS_BATCH(batch);
 548 }
 549
 550 static void
 551 gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
 552                                  struct decode_state *decode_state,
 553                                  int standard_select,
 554                                  struct gen7_mfd_context *gen7_mfd_context)
 555 {
 556     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 557
 558     BEGIN_BCS_BATCH(batch, 10);
 559     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
 560
 561     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 562         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 563                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 564                       0);
 565         else
 566                 OUT_BCS_BATCH(batch, 0);
 567
 568     OUT_BCS_BATCH(batch, 0);
 569     OUT_BCS_BATCH(batch, 0);
 570         /* MPR Row Store Scratch buffer 4-6 */
 571     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 572         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 573                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 574                       0);
 575     else
 576             OUT_BCS_BATCH(batch, 0);
 577     OUT_BCS_BATCH(batch, 0);
 578     OUT_BCS_BATCH(batch, 0);
 579
 580         /* Bitplane 7-9 */
 581     if (gen7_mfd_context->bitplane_read_buffer.valid)
 582         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 583                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 584                       0);
 585     else
 586         OUT_BCS_BATCH(batch, 0);
 587     OUT_BCS_BATCH(batch, 0);
 588     OUT_BCS_BATCH(batch, 0);
 589     ADVANCE_BCS_BATCH(batch);
 590 }
 591
 592 static void
 593 gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 594                                  struct decode_state *decode_state,
 595                                  int standard_select,
 596                                  struct gen7_mfd_context *gen7_mfd_context)
 597 {
 598     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 599     struct i965_driver_data *i965 = i965_driver_data(ctx);
 600
 601         if (IS_STEPPING_BPLUS(i965)) {
 602                 gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state,
 603                                         standard_select, gen7_mfd_context);
 604                 return;
 605         }
 606
 607     BEGIN_BCS_BATCH(batch, 4);
 608     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 609
 610     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 611         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 612                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 613                       0);
 614     else
 615         OUT_BCS_BATCH(batch, 0);
 616
 617     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 618         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 619                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 620                       0);
 621     else
 622         OUT_BCS_BATCH(batch, 0);
 623
 624     if (gen7_mfd_context->bitplane_read_buffer.valid)
 625         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 626                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 627                       0);
 628     else
 629         OUT_BCS_BATCH(batch, 0);
 630
 631     ADVANCE_BCS_BATCH(batch);
 632 }
 633
 634 #if 0
 635 static void
 636 gen7_mfd_aes_state(VADriverContextP ctx,
 637                    struct decode_state *decode_state,
 638                    int standard_select)
 639 {
 640     /* FIXME */
 641 }
 642 #endif
 643
 644 static void
 645 gen75_mfd_qm_state(VADriverContextP ctx,
 646                   int qm_type,
 647                   unsigned char *qm,
 648                   int qm_length,
 649                   struct gen7_mfd_context *gen7_mfd_context)
 650 {
 651     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 652     unsigned int qm_buffer[16];
 653
 654     assert(qm_length <= 16 * 4);
 655     memcpy(qm_buffer, qm, qm_length);
 656
 657     BEGIN_BCS_BATCH(batch, 18);
 658     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 659     OUT_BCS_BATCH(batch, qm_type << 0);
 660     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 661     ADVANCE_BCS_BATCH(batch);
 662 }
 663
 664 #if 0
 665 static void
 666 gen7_mfd_wait(VADriverContextP ctx,
 667               struct decode_state *decode_state,
 668               int standard_select,
 669               struct gen7_mfd_context *gen7_mfd_context)
 670 {
 671     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 672
 673     BEGIN_BCS_BATCH(batch, 1);
 674     OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
 675     ADVANCE_BCS_BATCH(batch);
 676 }
 677 #endif
 678
 679 static void
 680 gen75_mfd_avc_img_state(VADriverContextP ctx,
 681                        struct decode_state *decode_state,
 682                        struct gen7_mfd_context *gen7_mfd_context)
 683 {
 684     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 685     int img_struct;
 686     int mbaff_frame_flag;
 687     unsigned int width_in_mbs, height_in_mbs;
 688     VAPictureParameterBufferH264 *pic_param;
 689
 690     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 691     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 692     assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
 693
 694     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 695         img_struct = 1;
 696     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 697         img_struct = 3;
 698     else
 699         img_struct = 0;
 700
 701     if ((img_struct & 0x1) == 0x1) {
 702         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 703     } else {
 704         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 705     }
 706
 707     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 708         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 709         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 710     } else {
 711         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 712     }
 713
 714     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 715                         !pic_param->pic_fields.bits.field_pic_flag);
 716
 717     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 718     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 719
 720     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 721     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 722            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 723     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 724
 725     BEGIN_BCS_BATCH(batch, 17);
 726     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2));
 727     OUT_BCS_BATCH(batch,
 728                   width_in_mbs * height_in_mbs);
 729     OUT_BCS_BATCH(batch,
 730                   ((height_in_mbs - 1) << 16) |
 731                   ((width_in_mbs - 1) << 0));
 732     OUT_BCS_BATCH(batch,
 733                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 734                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 735                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 736                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 737                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 738                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 739                   (img_struct << 8));
 740     OUT_BCS_BATCH(batch,
 741                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 742                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 743                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 744                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 745                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 746                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 747                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 748                   (mbaff_frame_flag << 1) |
 749                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 750     OUT_BCS_BATCH(batch, 0);
 751     OUT_BCS_BATCH(batch, 0);
 752     OUT_BCS_BATCH(batch, 0);
 753     OUT_BCS_BATCH(batch, 0);
 754     OUT_BCS_BATCH(batch, 0);
 755     OUT_BCS_BATCH(batch, 0);
 756     OUT_BCS_BATCH(batch, 0);
 757     OUT_BCS_BATCH(batch, 0);
 758     OUT_BCS_BATCH(batch, 0);
 759     OUT_BCS_BATCH(batch, 0);
 760     OUT_BCS_BATCH(batch, 0);
 761     OUT_BCS_BATCH(batch, 0);
 762     ADVANCE_BCS_BATCH(batch);
 763 }
 764
 765 static void
 766 gen75_mfd_avc_qm_state(VADriverContextP ctx,
 767                       struct decode_state *decode_state,
 768                       struct gen7_mfd_context *gen7_mfd_context)
 769 {
 770     VAIQMatrixBufferH264 *iq_matrix;
 771     VAPictureParameterBufferH264 *pic_param;
 772
 773     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 774         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 775     else
 776         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 777
 778     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 779     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 780
 781     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 782     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 783
 784     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 785         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 786         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 787     }
 788 }
 789
 790 static void
 791 gen75_mfd_avc_picid_state(VADriverContextP ctx,
 792                       struct decode_state *decode_state,
 793                       struct gen7_mfd_context *gen7_mfd_context)
 794 {
 795     struct i965_driver_data *i965 = i965_driver_data(ctx);
 796     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 797
 798     BEGIN_BCS_BATCH(batch, 10);
 799     OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2));
 800     OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping
 801     OUT_BCS_BATCH(batch, 0);
 802     OUT_BCS_BATCH(batch, 0);
 803     OUT_BCS_BATCH(batch, 0);
 804     OUT_BCS_BATCH(batch, 0);
 805     OUT_BCS_BATCH(batch, 0);
 806     OUT_BCS_BATCH(batch, 0);
 807     OUT_BCS_BATCH(batch, 0);
 808     OUT_BCS_BATCH(batch, 0);
 809     ADVANCE_BCS_BATCH(batch);
 810 }
 811
 812 static void
 813 gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx,
 814                               VAPictureParameterBufferH264 *pic_param,
 815                               VASliceParameterBufferH264 *slice_param,
 816                               struct gen7_mfd_context *gen7_mfd_context)
 817 {
 818     struct i965_driver_data *i965 = i965_driver_data(ctx);
 819     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 820     struct object_surface *obj_surface;
 821     struct gen7_avc_surface *gen7_avc_surface;
 822     VAPictureH264 *va_pic;
 823     int i, j;
 824
 825     BEGIN_BCS_BATCH(batch, 71);
 826     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
 827
 828     /* reference surfaces 0..15 */
 829     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 830         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 831             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 832             assert(obj_surface);
 833             gen7_avc_surface = obj_surface->private_data;
 834
 835             if (gen7_avc_surface == NULL) {
 836                 OUT_BCS_BATCH(batch, 0);
 837                 OUT_BCS_BATCH(batch, 0);
 838             } else {
 839                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 840                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 841                               0);
 842                 OUT_BCS_BATCH(batch, 0);
 843             }
 844         } else {
 845             OUT_BCS_BATCH(batch, 0);
 846             OUT_BCS_BATCH(batch, 0);
 847         }
 848     }
 849         OUT_BCS_BATCH(batch, 0);
 850
 851     /* the current decoding frame/field */
 852     va_pic = &pic_param->CurrPic;
 853     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 854     obj_surface = SURFACE(va_pic->picture_id);
 855     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 856     gen7_avc_surface = obj_surface->private_data;
 857
 858     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 859                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 860                   0);
 861
 862         OUT_BCS_BATCH(batch, 0);
 863         OUT_BCS_BATCH(batch, 0);
 864
 865     /* POC List */
 866     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 867         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 868             int found = 0;
 869             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 870                 va_pic = &pic_param->ReferenceFrames[j];
 871
 872                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 873                     continue;
 874
 875                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 876                     found = 1;
 877                     break;
 878                 }
 879             }
 880
 881             assert(found == 1);
 882             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 883
 884             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 885             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 886         } else {
 887             OUT_BCS_BATCH(batch, 0);
 888             OUT_BCS_BATCH(batch, 0);
 889         }
 890     }
 891
 892     va_pic = &pic_param->CurrPic;
 893     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 894     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 895
 896     ADVANCE_BCS_BATCH(batch);
 897 }
 898
 899 static void
 900 gen75_mfd_avc_directmode_state(VADriverContextP ctx,
 901                               VAPictureParameterBufferH264 *pic_param,
 902                               VASliceParameterBufferH264 *slice_param,
 903                               struct gen7_mfd_context *gen7_mfd_context)
 904 {
 905     struct i965_driver_data *i965 = i965_driver_data(ctx);
 906     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 907     struct object_surface *obj_surface;
 908     struct gen7_avc_surface *gen7_avc_surface;
 909     VAPictureH264 *va_pic;
 910     int i, j;
 911
 912         if (IS_STEPPING_BPLUS(i965)) {
 913                 gen75_mfd_avc_directmode_state_bplus(ctx, pic_param, slice_param,
 914                         gen7_mfd_context);
 915
 916                 return;
 917         }
 918
 919     BEGIN_BCS_BATCH(batch, 69);
 920     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 921
 922     /* reference surfaces 0..15 */
 923     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 924         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 925             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 926             assert(obj_surface);
 927             gen7_avc_surface = obj_surface->private_data;
 928
 929             if (gen7_avc_surface == NULL) {
 930                 OUT_BCS_BATCH(batch, 0);
 931                 OUT_BCS_BATCH(batch, 0);
 932             } else {
 933                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 934                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 935                               0);
 936
 937                 if (gen7_avc_surface->dmv_bottom_flag == 1)
 938                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 939                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 940                                   0);
 941                 else
 942                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 943                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 944                                   0);
 945             }
 946         } else {
 947             OUT_BCS_BATCH(batch, 0);
 948             OUT_BCS_BATCH(batch, 0);
 949         }
 950     }
 951
 952     /* the current decoding frame/field */
 953     va_pic = &pic_param->CurrPic;
 954     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 955     obj_surface = SURFACE(va_pic->picture_id);
 956     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 957     gen7_avc_surface = obj_surface->private_data;
 958
 959     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 960                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 961                   0);
 962
 963     if (gen7_avc_surface->dmv_bottom_flag == 1)
 964         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 965                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 966                       0);
 967     else
 968         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 969                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 970                       0);
 971
 972     /* POC List */
 973     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 974         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 975             int found = 0;
 976             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 977                 va_pic = &pic_param->ReferenceFrames[j];
 978
 979                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 980                     continue;
 981
 982                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 983                     found = 1;
 984                     break;
 985                 }
 986             }
 987
 988             assert(found == 1);
 989             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 990
 991             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 992             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 993         } else {
 994             OUT_BCS_BATCH(batch, 0);
 995             OUT_BCS_BATCH(batch, 0);
 996         }
 997     }
 998
 999     va_pic = &pic_param->CurrPic;
1000     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
1001     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
1002
1003     ADVANCE_BCS_BATCH(batch);
1004 }
1005
1006 static void
1007 gen75_mfd_avc_slice_state(VADriverContextP ctx,
1008                          VAPictureParameterBufferH264 *pic_param,
1009                          VASliceParameterBufferH264 *slice_param,
1010                          VASliceParameterBufferH264 *next_slice_param,
1011                          struct gen7_mfd_context *gen7_mfd_context)
1012 {
1013     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1014     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1015     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1016     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
1017     int num_ref_idx_l0, num_ref_idx_l1;
1018     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
1019                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
1020     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
1021     int slice_type;
1022
1023     if (slice_param->slice_type == SLICE_TYPE_I ||
1024         slice_param->slice_type == SLICE_TYPE_SI) {
1025         slice_type = SLICE_TYPE_I;
1026     } else if (slice_param->slice_type == SLICE_TYPE_P ||
1027                slice_param->slice_type == SLICE_TYPE_SP) {
1028         slice_type = SLICE_TYPE_P;
1029     } else {
1030         assert(slice_param->slice_type == SLICE_TYPE_B);
1031         slice_type = SLICE_TYPE_B;
1032     }
1033
1034     if (slice_type == SLICE_TYPE_I) {
1035         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
1036         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1037         num_ref_idx_l0 = 0;
1038         num_ref_idx_l1 = 0;
1039     } else if (slice_type == SLICE_TYPE_P) {
1040         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1041         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1042         num_ref_idx_l1 = 0;
1043     } else {
1044         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1045         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
1046     }
1047
1048     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
1049     slice_hor_pos = first_mb_in_slice % width_in_mbs;
1050     slice_ver_pos = first_mb_in_slice / width_in_mbs;
1051
1052     if (next_slice_param) {
1053         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
1054         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
1055         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
1056     } else {
1057         next_slice_hor_pos = 0;
1058         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
1059     }
1060
1061     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
1062     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
1063     OUT_BCS_BATCH(batch, slice_type);
1064     OUT_BCS_BATCH(batch,
1065                   (num_ref_idx_l1 << 24) |
1066                   (num_ref_idx_l0 << 16) |
1067                   (slice_param->chroma_log2_weight_denom << 8) |
1068                   (slice_param->luma_log2_weight_denom << 0));
1069     OUT_BCS_BATCH(batch,
1070                   (slice_param->direct_spatial_mv_pred_flag << 29) |
1071                   (slice_param->disable_deblocking_filter_idc << 27) |
1072                   (slice_param->cabac_init_idc << 24) |
1073                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
1074                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
1075                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
1076     OUT_BCS_BATCH(batch,
1077                   (slice_ver_pos << 24) |
1078                   (slice_hor_pos << 16) |
1079                   (first_mb_in_slice << 0));
1080     OUT_BCS_BATCH(batch,
1081                   (next_slice_ver_pos << 16) |
1082                   (next_slice_hor_pos << 0));
1083     OUT_BCS_BATCH(batch,
1084                   (next_slice_param == NULL) << 19); /* last slice flag */
1085     OUT_BCS_BATCH(batch, 0);
1086     OUT_BCS_BATCH(batch, 0);
1087     OUT_BCS_BATCH(batch, 0);
1088     OUT_BCS_BATCH(batch, 0);
1089     ADVANCE_BCS_BATCH(batch);
1090 }
1091
1092 static inline void
1093 gen75_mfd_avc_ref_idx_state(VADriverContextP ctx,
1094                            VAPictureParameterBufferH264 *pic_param,
1095                            VASliceParameterBufferH264 *slice_param,
1096                            struct gen7_mfd_context *gen7_mfd_context)
1097 {
1098     gen6_send_avc_ref_idx_state(
1099         gen7_mfd_context->base.batch,
1100         slice_param,
1101         gen7_mfd_context->reference_surface
1102     );
1103 }
1104
1105 static void
1106 gen75_mfd_avc_weightoffset_state(VADriverContextP ctx,
1107                                 VAPictureParameterBufferH264 *pic_param,
1108                                 VASliceParameterBufferH264 *slice_param,
1109                                 struct gen7_mfd_context *gen7_mfd_context)
1110 {
1111     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1112     int i, j, num_weight_offset_table = 0;
1113     short weightoffsets[32 * 6];
1114
1115     if ((slice_param->slice_type == SLICE_TYPE_P ||
1116          slice_param->slice_type == SLICE_TYPE_SP) &&
1117         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
1118         num_weight_offset_table = 1;
1119     }
1120
1121     if ((slice_param->slice_type == SLICE_TYPE_B) &&
1122         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
1123         num_weight_offset_table = 2;
1124     }
1125
1126     for (i = 0; i < num_weight_offset_table; i++) {
1127         BEGIN_BCS_BATCH(batch, 98);
1128         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
1129         OUT_BCS_BATCH(batch, i);
1130
1131         if (i == 0) {
1132             for (j = 0; j < 32; j++) {
1133                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
1134                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
1135                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
1136                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
1137                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
1138                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
1139             }
1140         } else {
1141             for (j = 0; j < 32; j++) {
1142                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
1143                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
1144                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
1145                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
1146                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
1147                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
1148             }
1149         }
1150
1151         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
1152         ADVANCE_BCS_BATCH(batch);
1153     }
1154 }
1155
1156 static int
1157 gen75_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
1158 {
1159     int out_slice_data_bit_offset;
1160     int slice_header_size = in_slice_data_bit_offset / 8;
1161     int i, j;
1162
1163     for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1164         if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
1165             i++, j += 2;
1166         }
1167     }
1168
1169     out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1170
1171     if (mode_flag == ENTROPY_CABAC)
1172         out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
1173
1174     return out_slice_data_bit_offset;
1175 }
1176
1177 static void
1178 gen75_mfd_avc_bsd_object(VADriverContextP ctx,
1179                         VAPictureParameterBufferH264 *pic_param,
1180                         VASliceParameterBufferH264 *slice_param,
1181                         dri_bo *slice_data_bo,
1182                         VASliceParameterBufferH264 *next_slice_param,
1183                         struct gen7_mfd_context *gen7_mfd_context)
1184 {
1185     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1186     int slice_data_bit_offset;
1187     uint8_t *slice_data = NULL;
1188
1189     dri_bo_map(slice_data_bo, 0);
1190     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1191     slice_data_bit_offset = gen75_mfd_avc_get_slice_bit_offset(slice_data,
1192                                                               pic_param->pic_fields.bits.entropy_coding_mode_flag,
1193                                                               slice_param->slice_data_bit_offset);
1194     dri_bo_unmap(slice_data_bo);
1195
1196     /* the input bitsteam format on GEN7 differs from GEN6 */
1197     BEGIN_BCS_BATCH(batch, 6);
1198     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
1199     OUT_BCS_BATCH(batch,
1200                   (slice_param->slice_data_size));
1201     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
1202     OUT_BCS_BATCH(batch,
1203                   (0 << 31) |
1204                   (0 << 14) |
1205                   (0 << 12) |
1206                   (0 << 10) |
1207                   (0 << 8));
1208     OUT_BCS_BATCH(batch,
1209                   ((slice_data_bit_offset >> 3) << 16) |
1210                   (0 << 5)  |
1211                   (0 << 4)  |
1212                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
1213                   (slice_data_bit_offset & 0x7));
1214     OUT_BCS_BATCH(batch, 0);
1215     ADVANCE_BCS_BATCH(batch);
1216 }
1217
1218 static inline void
1219 gen75_mfd_avc_context_init(
1220     VADriverContextP         ctx,
1221     struct gen7_mfd_context *gen7_mfd_context
1222 )
1223 {
1224     /* Initialize flat scaling lists */
1225     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
1226 }
1227
1228 static void
1229 gen75_mfd_avc_decode_init(VADriverContextP ctx,
1230                          struct decode_state *decode_state,
1231                          struct gen7_mfd_context *gen7_mfd_context)
1232 {
1233     VAPictureParameterBufferH264 *pic_param;
1234     VASliceParameterBufferH264 *slice_param;
1235     VAPictureH264 *va_pic;
1236     struct i965_driver_data *i965 = i965_driver_data(ctx);
1237     struct object_surface *obj_surface;
1238     dri_bo *bo;
1239     int i, j, enable_avc_ildb = 0;
1240     unsigned int width_in_mbs, height_in_mbs;
1241
1242     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
1243         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1244         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1245
1246         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1247             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1248             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1249                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1250                    (slice_param->slice_type == SLICE_TYPE_P) ||
1251                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1252                    (slice_param->slice_type == SLICE_TYPE_B));
1253
1254             if (slice_param->disable_deblocking_filter_idc != 1) {
1255                 enable_avc_ildb = 1;
1256                 break;
1257             }
1258
1259             slice_param++;
1260         }
1261     }
1262
1263     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1264     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1265     gen75_mfd_avc_frame_store_index(ctx, pic_param, gen7_mfd_context);
1266     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1267     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1268     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
1269     assert(height_in_mbs > 0 && height_in_mbs <= 256);
1270
1271     /* Current decoded picture */
1272     va_pic = &pic_param->CurrPic;
1273     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
1274     obj_surface = SURFACE(va_pic->picture_id);
1275     assert(obj_surface);
1276     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
1277     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
1278     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1279     gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface);
1280
1281     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1282     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1283     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1284     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
1285
1286     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1287     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1288     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1289     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
1290
1291     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1292     bo = dri_bo_alloc(i965->intel.bufmgr,
1293                       "intra row store",
1294                       width_in_mbs * 64,
1295                       0x1000);
1296     assert(bo);
1297     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1298     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1299
1300     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1301     bo = dri_bo_alloc(i965->intel.bufmgr,
1302                       "deblocking filter row store",
1303                       width_in_mbs * 64 * 4,
1304                       0x1000);
1305     assert(bo);
1306     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1307     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1308
1309     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1310     bo = dri_bo_alloc(i965->intel.bufmgr,
1311                       "bsd mpc row store",
1312                       width_in_mbs * 64 * 2,
1313                       0x1000);
1314     assert(bo);
1315     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1316     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1317
1318     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
1319     bo = dri_bo_alloc(i965->intel.bufmgr,
1320                       "mpr row store",
1321                       width_in_mbs * 64 * 2,
1322                       0x1000);
1323     assert(bo);
1324     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
1325     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1326
1327     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1328 }
1329
1330 static void
1331 gen75_mfd_avc_decode_picture(VADriverContextP ctx,
1332                             struct decode_state *decode_state,
1333                             struct gen7_mfd_context *gen7_mfd_context)
1334 {
1335     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1336     VAPictureParameterBufferH264 *pic_param;
1337     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1338     dri_bo *slice_data_bo;
1339     int i, j;
1340
1341     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1342     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1343     gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
1344
1345     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1346     intel_batchbuffer_emit_mi_flush(batch);
1347     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1348     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1349     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1350     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1351     gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
1352     gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1353     gen75_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context);
1354
1355     for (j = 0; j < decode_state->num_slice_params; j++) {
1356         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1357         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1358         slice_data_bo = decode_state->slice_datas[j]->bo;
1359         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1360
1361         if (j == decode_state->num_slice_params - 1)
1362             next_slice_group_param = NULL;
1363         else
1364             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1365
1366         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1367             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1368             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1369                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1370                    (slice_param->slice_type == SLICE_TYPE_P) ||
1371                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1372                    (slice_param->slice_type == SLICE_TYPE_B));
1373
1374             if (i < decode_state->slice_params[j]->num_elements - 1)
1375                 next_slice_param = slice_param + 1;
1376             else
1377                 next_slice_param = next_slice_group_param;
1378
1379             gen75_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen7_mfd_context);
1380             gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1381             gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1382             gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1383             gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1384             slice_param++;
1385         }
1386     }
1387
1388     intel_batchbuffer_end_atomic(batch);
1389     intel_batchbuffer_flush(batch);
1390 }
1391
1392 static void
1393 gen75_mfd_mpeg2_decode_init(VADriverContextP ctx,
1394                            struct decode_state *decode_state,
1395                            struct gen7_mfd_context *gen7_mfd_context)
1396 {
1397     VAPictureParameterBufferMPEG2 *pic_param;
1398     struct i965_driver_data *i965 = i965_driver_data(ctx);
1399     struct object_surface *obj_surface;
1400     dri_bo *bo;
1401     unsigned int width_in_mbs;
1402
1403     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1404     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1405     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1406
1407     mpeg2_set_reference_surfaces(
1408         ctx,
1409         gen7_mfd_context->reference_surface,
1410         decode_state,
1411         pic_param
1412     );
1413
1414     /* Current decoded picture */
1415     obj_surface = SURFACE(decode_state->current_render_target);
1416     assert(obj_surface);
1417     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1418
1419     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1420     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1421     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1422     gen7_mfd_context->pre_deblocking_output.valid = 1;
1423
1424     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1425     bo = dri_bo_alloc(i965->intel.bufmgr,
1426                       "bsd mpc row store",
1427                       width_in_mbs * 96,
1428                       0x1000);
1429     assert(bo);
1430     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1431     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1432
1433     gen7_mfd_context->post_deblocking_output.valid = 0;
1434     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1435     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1436     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1437     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1438 }
1439
1440 static void
1441 gen75_mfd_mpeg2_pic_state(VADriverContextP ctx,
1442                          struct decode_state *decode_state,
1443                          struct gen7_mfd_context *gen7_mfd_context)
1444 {
1445     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1446     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1447     VAPictureParameterBufferMPEG2 *pic_param;
1448     unsigned int slice_concealment_disable_bit = 0;
1449
1450     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1451     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1452
1453     slice_concealment_disable_bit = 1;
1454
1455     BEGIN_BCS_BATCH(batch, 13);
1456     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1457     OUT_BCS_BATCH(batch,
1458                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1459                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1460                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1461                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1462                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1463                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1464                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
1465                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1466                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1467                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1468                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1469                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1470     OUT_BCS_BATCH(batch,
1471                   pic_param->picture_coding_type << 9);
1472     OUT_BCS_BATCH(batch,
1473                   (slice_concealment_disable_bit << 31) |
1474                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1475                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1476     OUT_BCS_BATCH(batch, 0);
1477     OUT_BCS_BATCH(batch, 0);
1478     OUT_BCS_BATCH(batch, 0);
1479     OUT_BCS_BATCH(batch, 0);
1480     OUT_BCS_BATCH(batch, 0);
1481     OUT_BCS_BATCH(batch, 0);
1482     OUT_BCS_BATCH(batch, 0);
1483     OUT_BCS_BATCH(batch, 0);
1484     OUT_BCS_BATCH(batch, 0);
1485     ADVANCE_BCS_BATCH(batch);
1486 }
1487
1488 static void
1489 gen75_mfd_mpeg2_qm_state(VADriverContextP ctx,
1490                         struct decode_state *decode_state,
1491                         struct gen7_mfd_context *gen7_mfd_context)
1492 {
1493     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1494     int i, j;
1495
1496     /* Update internal QM state */
1497     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1498         VAIQMatrixBufferMPEG2 * const iq_matrix =
1499             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1500
1501         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1502             iq_matrix->load_intra_quantiser_matrix) {
1503             gen_iq_matrix->load_intra_quantiser_matrix =
1504                 iq_matrix->load_intra_quantiser_matrix;
1505             if (iq_matrix->load_intra_quantiser_matrix) {
1506                 for (j = 0; j < 64; j++)
1507                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1508                         iq_matrix->intra_quantiser_matrix[j];
1509             }
1510         }
1511
1512         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1513             iq_matrix->load_non_intra_quantiser_matrix) {
1514             gen_iq_matrix->load_non_intra_quantiser_matrix =
1515                 iq_matrix->load_non_intra_quantiser_matrix;
1516             if (iq_matrix->load_non_intra_quantiser_matrix) {
1517                 for (j = 0; j < 64; j++)
1518                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1519                         iq_matrix->non_intra_quantiser_matrix[j];
1520             }
1521         }
1522     }
1523
1524     /* Commit QM state to HW */
1525     for (i = 0; i < 2; i++) {
1526         unsigned char *qm = NULL;
1527         int qm_type;
1528
1529         if (i == 0) {
1530             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1531                 qm = gen_iq_matrix->intra_quantiser_matrix;
1532                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1533             }
1534         } else {
1535             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1536                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1537                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1538             }
1539         }
1540
1541         if (!qm)
1542             continue;
1543
1544         gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1545     }
1546 }
1547
1548 static void
1549 gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1550                           VAPictureParameterBufferMPEG2 *pic_param,
1551                           VASliceParameterBufferMPEG2 *slice_param,
1552                           VASliceParameterBufferMPEG2 *next_slice_param,
1553                           struct gen7_mfd_context *gen7_mfd_context)
1554 {
1555     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1556     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1557     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1558     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1559
1560     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1561         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1562         is_field_pic = 1;
1563     is_field_pic_wa = is_field_pic &&
1564         gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1565
1566     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1567     hpos0 = slice_param->slice_horizontal_position;
1568
1569     if (next_slice_param == NULL) {
1570         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1571         hpos1 = 0;
1572     } else {
1573         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1574         hpos1 = next_slice_param->slice_horizontal_position;
1575     }
1576
1577     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1578
1579     BEGIN_BCS_BATCH(batch, 5);
1580     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1581     OUT_BCS_BATCH(batch,
1582                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1583     OUT_BCS_BATCH(batch,
1584                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1585     OUT_BCS_BATCH(batch,
1586                   hpos0 << 24 |
1587                   vpos0 << 16 |
1588                   mb_count << 8 |
1589                   (next_slice_param == NULL) << 5 |
1590                   (next_slice_param == NULL) << 3 |
1591                   (slice_param->macroblock_offset & 0x7));
1592     OUT_BCS_BATCH(batch,
1593                   (slice_param->quantiser_scale_code << 24) |
1594                   (vpos1 << 8 | hpos1));
1595     ADVANCE_BCS_BATCH(batch);
1596 }
1597
1598 static void
1599 gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1600                               struct decode_state *decode_state,
1601                               struct gen7_mfd_context *gen7_mfd_context)
1602 {
1603     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1604     VAPictureParameterBufferMPEG2 *pic_param;
1605     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1606     dri_bo *slice_data_bo;
1607     int i, j;
1608
1609     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1610     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1611
1612     gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1613     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1614     intel_batchbuffer_emit_mi_flush(batch);
1615     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1616     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1617     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1618     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1619     gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1620     gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1621
1622     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1623         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1624             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1625
1626     for (j = 0; j < decode_state->num_slice_params; j++) {
1627         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1628         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1629         slice_data_bo = decode_state->slice_datas[j]->bo;
1630         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1631
1632         if (j == decode_state->num_slice_params - 1)
1633             next_slice_group_param = NULL;
1634         else
1635             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1636
1637         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1638             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1639
1640             if (i < decode_state->slice_params[j]->num_elements - 1)
1641                 next_slice_param = slice_param + 1;
1642             else
1643                 next_slice_param = next_slice_group_param;
1644
1645             gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1646             slice_param++;
1647         }
1648     }
1649
1650     intel_batchbuffer_end_atomic(batch);
1651     intel_batchbuffer_flush(batch);
1652 }
1653
1654 static const int va_to_gen7_vc1_pic_type[5] = {
1655     GEN7_VC1_I_PICTURE,
1656     GEN7_VC1_P_PICTURE,
1657     GEN7_VC1_B_PICTURE,
1658     GEN7_VC1_BI_PICTURE,
1659     GEN7_VC1_P_PICTURE,
1660 };
1661
1662 static const int va_to_gen7_vc1_mv[4] = {
1663     1, /* 1-MV */
1664     2, /* 1-MV half-pel */
1665     3, /* 1-MV half-pef bilinear */
1666     0, /* Mixed MV */
1667 };
1668
1669 static const int b_picture_scale_factor[21] = {
1670     128, 85,  170, 64,  192,
1671     51,  102, 153, 204, 43,
1672     215, 37,  74,  111, 148,
1673     185, 222, 32,  96,  160,
1674     224,
1675 };
1676
1677 static const int va_to_gen7_vc1_condover[3] = {
1678     0,
1679     2,
1680     3
1681 };
1682
1683 static const int va_to_gen7_vc1_profile[4] = {
1684     GEN7_VC1_SIMPLE_PROFILE,
1685     GEN7_VC1_MAIN_PROFILE,
1686     GEN7_VC1_RESERVED_PROFILE,
1687     GEN7_VC1_ADVANCED_PROFILE
1688 };
1689
1690 static void
1691 gen75_mfd_free_vc1_surface(void **data)
1692 {
1693     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1694
1695     if (!gen7_vc1_surface)
1696         return;
1697
1698     dri_bo_unreference(gen7_vc1_surface->dmv);
1699     free(gen7_vc1_surface);
1700     *data = NULL;
1701 }
1702
1703 static void
1704 gen75_mfd_init_vc1_surface(VADriverContextP ctx,
1705                           VAPictureParameterBufferVC1 *pic_param,
1706                           struct object_surface *obj_surface)
1707 {
1708     struct i965_driver_data *i965 = i965_driver_data(ctx);
1709     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1710     int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1711     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1712
1713     obj_surface->free_private_data = gen75_mfd_free_vc1_surface;
1714
1715     if (!gen7_vc1_surface) {
1716         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1717         assert((obj_surface->size & 0x3f) == 0);
1718         obj_surface->private_data = gen7_vc1_surface;
1719     }
1720
1721     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1722
1723     if (gen7_vc1_surface->dmv == NULL) {
1724         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1725                                              "direct mv w/r buffer",
1726                                              width_in_mbs * height_in_mbs * 64,
1727                                              0x1000);
1728     }
1729 }
1730
1731 static void
1732 gen75_mfd_vc1_decode_init(VADriverContextP ctx,
1733                          struct decode_state *decode_state,
1734                          struct gen7_mfd_context *gen7_mfd_context)
1735 {
1736     VAPictureParameterBufferVC1 *pic_param;
1737     struct i965_driver_data *i965 = i965_driver_data(ctx);
1738     struct object_surface *obj_surface;
1739     int i;
1740     dri_bo *bo;
1741     int width_in_mbs;
1742
1743     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1744     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1745     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1746
1747     /* reference picture */
1748     obj_surface = SURFACE(pic_param->forward_reference_picture);
1749
1750     if (obj_surface && obj_surface->bo)
1751         gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1752     else
1753         gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1754
1755     obj_surface = SURFACE(pic_param->backward_reference_picture);
1756
1757     if (obj_surface && obj_surface->bo)
1758         gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1759     else
1760         gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1761
1762     /* must do so !!! */
1763     for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1764         gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1765
1766     /* Current decoded picture */
1767     obj_surface = SURFACE(decode_state->current_render_target);
1768     assert(obj_surface);
1769     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1770     gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1771
1772     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1773     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1774     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1775     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1776
1777     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1778     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1779     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1780     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1781
1782     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1783     bo = dri_bo_alloc(i965->intel.bufmgr,
1784                       "intra row store",
1785                       width_in_mbs * 64,
1786                       0x1000);
1787     assert(bo);
1788     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1789     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1790
1791     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1792     bo = dri_bo_alloc(i965->intel.bufmgr,
1793                       "deblocking filter row store",
1794                       width_in_mbs * 6 * 64,
1795                       0x1000);
1796     assert(bo);
1797     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1798     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1799
1800     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1801     bo = dri_bo_alloc(i965->intel.bufmgr,
1802                       "bsd mpc row store",
1803                       width_in_mbs * 96,
1804                       0x1000);
1805     assert(bo);
1806     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1807     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1808
1809     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1810
1811     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1812     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1813
1814     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1815         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1816         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1817         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1818         int src_w, src_h;
1819         uint8_t *src = NULL, *dst = NULL;
1820
1821         assert(decode_state->bit_plane->buffer);
1822         src = decode_state->bit_plane->buffer;
1823
1824         bo = dri_bo_alloc(i965->intel.bufmgr,
1825                           "VC-1 Bitplane",
1826                           bitplane_width * bitplane_width,
1827                           0x1000);
1828         assert(bo);
1829         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1830
1831         dri_bo_map(bo, True);
1832         assert(bo->virtual);
1833         dst = bo->virtual;
1834
1835         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1836             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1837                 int src_index, dst_index;
1838                 int src_shift;
1839                 uint8_t src_value;
1840
1841                 src_index = (src_h * width_in_mbs + src_w) / 2;
1842                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1843                 src_value = ((src[src_index] >> src_shift) & 0xf);
1844
1845                 dst_index = src_w / 2;
1846                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1847             }
1848
1849             if (src_w & 1)
1850                 dst[src_w / 2] >>= 4;
1851
1852             dst += bitplane_width;
1853         }
1854
1855         dri_bo_unmap(bo);
1856     } else
1857         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1858 }
1859
1860 static void
1861 gen75_mfd_vc1_pic_state(VADriverContextP ctx,
1862                        struct decode_state *decode_state,
1863                        struct gen7_mfd_context *gen7_mfd_context)
1864 {
1865     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1866     VAPictureParameterBufferVC1 *pic_param;
1867     struct i965_driver_data *i965 = i965_driver_data(ctx);
1868     struct object_surface *obj_surface;
1869     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1870     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1871     int unified_mv_mode;
1872     int ref_field_pic_polarity = 0;
1873     int scale_factor = 0;
1874     int trans_ac_y = 0;
1875     int dmv_surface_valid = 0;
1876     int brfd = 0;
1877     int fcm = 0;
1878     int picture_type;
1879     int profile;
1880     int overlap;
1881     int interpolation_mode = 0;
1882
1883     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1884     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1885
1886     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1887     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1888     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1889     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1890     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1891     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1892     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1893     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1894
1895     if (dquant == 0) {
1896         alt_pquant_config = 0;
1897         alt_pquant_edge_mask = 0;
1898     } else if (dquant == 2) {
1899         alt_pquant_config = 1;
1900         alt_pquant_edge_mask = 0xf;
1901     } else {
1902         assert(dquant == 1);
1903         if (dquantfrm == 0) {
1904             alt_pquant_config = 0;
1905             alt_pquant_edge_mask = 0;
1906             alt_pq = 0;
1907         } else {
1908             assert(dquantfrm == 1);
1909             alt_pquant_config = 1;
1910
1911             switch (dqprofile) {
1912             case 3:
1913                 if (dqbilevel == 0) {
1914                     alt_pquant_config = 2;
1915                     alt_pquant_edge_mask = 0;
1916                 } else {
1917                     assert(dqbilevel == 1);
1918                     alt_pquant_config = 3;
1919                     alt_pquant_edge_mask = 0;
1920                 }
1921                 break;
1922
1923             case 0:
1924                 alt_pquant_edge_mask = 0xf;
1925                 break;
1926
1927             case 1:
1928                 if (dqdbedge == 3)
1929                     alt_pquant_edge_mask = 0x9;
1930                 else
1931                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1932
1933                 break;
1934
1935             case 2:
1936                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1937                 break;
1938
1939             default:
1940                 assert(0);
1941             }
1942         }
1943     }
1944
1945     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1946         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1947         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1948     } else {
1949         assert(pic_param->mv_fields.bits.mv_mode < 4);
1950         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1951     }
1952
1953     if (pic_param->sequence_fields.bits.interlace == 1 &&
1954         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1955         /* FIXME: calculate reference field picture polarity */
1956         assert(0);
1957         ref_field_pic_polarity = 0;
1958     }
1959
1960     if (pic_param->b_picture_fraction < 21)
1961         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1962
1963     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1964
1965     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1966         picture_type == GEN7_VC1_I_PICTURE)
1967         picture_type = GEN7_VC1_BI_PICTURE;
1968
1969     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1970         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1971     else
1972         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1973
1974
1975     if (picture_type == GEN7_VC1_B_PICTURE) {
1976         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1977
1978         obj_surface = SURFACE(pic_param->backward_reference_picture);
1979         assert(obj_surface);
1980         gen7_vc1_surface = obj_surface->private_data;
1981
1982         if (!gen7_vc1_surface ||
1983             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1984              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1985             dmv_surface_valid = 0;
1986         else
1987             dmv_surface_valid = 1;
1988     }
1989
1990     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1991
1992     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1993         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1994     else {
1995         if (pic_param->picture_fields.bits.top_field_first)
1996             fcm = 2;
1997         else
1998             fcm = 3;
1999     }
2000
2001     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
2002         brfd = pic_param->reference_fields.bits.reference_distance;
2003         brfd = (scale_factor * brfd) >> 8;
2004         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
2005
2006         if (brfd < 0)
2007             brfd = 0;
2008     }
2009
2010     overlap = pic_param->sequence_fields.bits.overlap;
2011     if (profile != GEN7_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
2012         overlap = 0;
2013
2014     assert(pic_param->conditional_overlap_flag < 3);
2015     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
2016
2017     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
2018         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2019          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
2020         interpolation_mode = 9; /* Half-pel bilinear */
2021     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
2022              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2023               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
2024         interpolation_mode = 1; /* Half-pel bicubic */
2025     else
2026         interpolation_mode = 0; /* Quarter-pel bicubic */
2027
2028     BEGIN_BCS_BATCH(batch, 6);
2029     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
2030     OUT_BCS_BATCH(batch,
2031                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
2032                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
2033     OUT_BCS_BATCH(batch,
2034                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
2035                   dmv_surface_valid << 15 |
2036                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
2037                   pic_param->rounding_control << 13 |
2038                   pic_param->sequence_fields.bits.syncmarker << 12 |
2039                   interpolation_mode << 8 |
2040                   0 << 7 | /* FIXME: scale up or down ??? */
2041                   pic_param->range_reduction_frame << 6 |
2042                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
2043                   overlap << 4 |
2044                   !pic_param->picture_fields.bits.is_first_field << 3 |
2045                   (pic_param->sequence_fields.bits.profile == 3) << 0);
2046     OUT_BCS_BATCH(batch,
2047                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
2048                   picture_type << 26 |
2049                   fcm << 24 |
2050                   alt_pq << 16 |
2051                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
2052                   scale_factor << 0);
2053     OUT_BCS_BATCH(batch,
2054                   unified_mv_mode << 28 |
2055                   pic_param->mv_fields.bits.four_mv_switch << 27 |
2056                   pic_param->fast_uvmc_flag << 26 |
2057                   ref_field_pic_polarity << 25 |
2058                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
2059                   pic_param->reference_fields.bits.reference_distance << 20 |
2060                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
2061                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
2062                   pic_param->mv_fields.bits.extended_mv_range << 8 |
2063                   alt_pquant_edge_mask << 4 |
2064                   alt_pquant_config << 2 |
2065                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
2066                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
2067     OUT_BCS_BATCH(batch,
2068                   !!pic_param->bitplane_present.value << 31 |
2069                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
2070                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
2071                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
2072                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
2073                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
2074                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
2075                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
2076                   pic_param->mv_fields.bits.mv_table << 20 |
2077                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
2078                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
2079                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
2080                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
2081                   pic_param->mb_mode_table << 8 |
2082                   trans_ac_y << 6 |
2083                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
2084                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
2085                   pic_param->cbp_table << 0);
2086     ADVANCE_BCS_BATCH(batch);
2087 }
2088
2089 static void
2090 gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
2091                              struct decode_state *decode_state,
2092                              struct gen7_mfd_context *gen7_mfd_context)
2093 {
2094     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2095     VAPictureParameterBufferVC1 *pic_param;
2096     int intensitycomp_single;
2097
2098     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2099     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2100
2101     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2102     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2103     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
2104
2105     BEGIN_BCS_BATCH(batch, 6);
2106     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
2107     OUT_BCS_BATCH(batch,
2108                   0 << 14 | /* FIXME: double ??? */
2109                   0 << 12 |
2110                   intensitycomp_single << 10 |
2111                   intensitycomp_single << 8 |
2112                   0 << 4 | /* FIXME: interlace mode */
2113                   0);
2114     OUT_BCS_BATCH(batch,
2115                   pic_param->luma_shift << 16 |
2116                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
2117     OUT_BCS_BATCH(batch, 0);
2118     OUT_BCS_BATCH(batch, 0);
2119     OUT_BCS_BATCH(batch, 0);
2120     ADVANCE_BCS_BATCH(batch);
2121 }
2122
2123 static void
2124 gen75_mfd_vc1_directmode_state_bplus(VADriverContextP ctx,
2125                               struct decode_state *decode_state,
2126                               struct gen7_mfd_context *gen7_mfd_context)
2127 {
2128     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2129     VAPictureParameterBufferVC1 *pic_param;
2130     struct i965_driver_data *i965 = i965_driver_data(ctx);
2131     struct object_surface *obj_surface;
2132     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2133
2134     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2135     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2136
2137     obj_surface = SURFACE(decode_state->current_render_target);
2138
2139     if (obj_surface && obj_surface->private_data) {
2140         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2141     }
2142
2143     obj_surface = SURFACE(pic_param->backward_reference_picture);
2144
2145     if (obj_surface && obj_surface->private_data) {
2146         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2147     }
2148
2149     BEGIN_BCS_BATCH(batch, 7);
2150     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2));
2151
2152     if (dmv_write_buffer)
2153         OUT_BCS_RELOC(batch, dmv_write_buffer,
2154                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2155                       0);
2156     else
2157         OUT_BCS_BATCH(batch, 0);
2158
2159         OUT_BCS_BATCH(batch, 0);
2160         OUT_BCS_BATCH(batch, 0);
2161
2162     if (dmv_read_buffer)
2163         OUT_BCS_RELOC(batch, dmv_read_buffer,
2164                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2165                       0);
2166     else
2167         OUT_BCS_BATCH(batch, 0);
2168         OUT_BCS_BATCH(batch, 0);
2169         OUT_BCS_BATCH(batch, 0);
2170
2171     ADVANCE_BCS_BATCH(batch);
2172 }
2173
2174 static void
2175 gen75_mfd_vc1_directmode_state(VADriverContextP ctx,
2176                               struct decode_state *decode_state,
2177                               struct gen7_mfd_context *gen7_mfd_context)
2178 {
2179     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2180     VAPictureParameterBufferVC1 *pic_param;
2181     struct i965_driver_data *i965 = i965_driver_data(ctx);
2182     struct object_surface *obj_surface;
2183     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2184
2185     if (IS_STEPPING_BPLUS(i965)) {
2186         gen75_mfd_vc1_directmode_state_bplus(ctx, decode_state, gen7_mfd_context);
2187         return;
2188     }
2189     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2190     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2191
2192     obj_surface = SURFACE(decode_state->current_render_target);
2193
2194     if (obj_surface && obj_surface->private_data) {
2195         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2196     }
2197
2198     obj_surface = SURFACE(pic_param->backward_reference_picture);
2199
2200     if (obj_surface && obj_surface->private_data) {
2201         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2202     }
2203
2204     BEGIN_BCS_BATCH(batch, 3);
2205     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
2206
2207     if (dmv_write_buffer)
2208         OUT_BCS_RELOC(batch, dmv_write_buffer,
2209                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2210                       0);
2211     else
2212         OUT_BCS_BATCH(batch, 0);
2213
2214     if (dmv_read_buffer)
2215         OUT_BCS_RELOC(batch, dmv_read_buffer,
2216                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2217                       0);
2218     else
2219         OUT_BCS_BATCH(batch, 0);
2220
2221     ADVANCE_BCS_BATCH(batch);
2222 }
2223
2224 static int
2225 gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
2226 {
2227     int out_slice_data_bit_offset;
2228     int slice_header_size = in_slice_data_bit_offset / 8;
2229     int i, j;
2230
2231     if (profile != 3)
2232         out_slice_data_bit_offset = in_slice_data_bit_offset;
2233     else {
2234         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
2235             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
2236                 i++, j += 2;
2237             }
2238         }
2239
2240         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
2241     }
2242
2243     return out_slice_data_bit_offset;
2244 }
2245
2246 static void
2247 gen75_mfd_vc1_bsd_object(VADriverContextP ctx,
2248                         VAPictureParameterBufferVC1 *pic_param,
2249                         VASliceParameterBufferVC1 *slice_param,
2250                         VASliceParameterBufferVC1 *next_slice_param,
2251                         dri_bo *slice_data_bo,
2252                         struct gen7_mfd_context *gen7_mfd_context)
2253 {
2254     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2255     int next_slice_start_vert_pos;
2256     int macroblock_offset;
2257     uint8_t *slice_data = NULL;
2258
2259     dri_bo_map(slice_data_bo, 0);
2260     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
2261     macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data,
2262                                                                slice_param->macroblock_offset,
2263                                                                pic_param->sequence_fields.bits.profile);
2264     dri_bo_unmap(slice_data_bo);
2265
2266     if (next_slice_param)
2267         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
2268     else
2269         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
2270
2271     BEGIN_BCS_BATCH(batch, 5);
2272     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
2273     OUT_BCS_BATCH(batch,
2274                   slice_param->slice_data_size - (macroblock_offset >> 3));
2275     OUT_BCS_BATCH(batch,
2276                   slice_param->slice_data_offset + (macroblock_offset >> 3));
2277     OUT_BCS_BATCH(batch,
2278                   slice_param->slice_vertical_position << 16 |
2279                   next_slice_start_vert_pos << 0);
2280     OUT_BCS_BATCH(batch,
2281                   (macroblock_offset & 0x7));
2282     ADVANCE_BCS_BATCH(batch);
2283 }
2284
2285 static void
2286 gen75_mfd_vc1_decode_picture(VADriverContextP ctx,
2287                             struct decode_state *decode_state,
2288                             struct gen7_mfd_context *gen7_mfd_context)
2289 {
2290     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2291     VAPictureParameterBufferVC1 *pic_param;
2292     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2293     dri_bo *slice_data_bo;
2294     int i, j;
2295
2296     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2297     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2298
2299     gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2300     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2301     intel_batchbuffer_emit_mi_flush(batch);
2302     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2303     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2304     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2305     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2306     gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2307     gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2308     gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2309
2310     for (j = 0; j < decode_state->num_slice_params; j++) {
2311         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2312         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2313         slice_data_bo = decode_state->slice_datas[j]->bo;
2314         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2315
2316         if (j == decode_state->num_slice_params - 1)
2317             next_slice_group_param = NULL;
2318         else
2319             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2320
2321         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2322             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2323
2324             if (i < decode_state->slice_params[j]->num_elements - 1)
2325                 next_slice_param = slice_param + 1;
2326             else
2327                 next_slice_param = next_slice_group_param;
2328
2329             gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2330             slice_param++;
2331         }
2332     }
2333
2334     intel_batchbuffer_end_atomic(batch);
2335     intel_batchbuffer_flush(batch);
2336 }
2337
2338 static void
2339 gen75_mfd_jpeg_decode_init(VADriverContextP ctx,
2340                           struct decode_state *decode_state,
2341                           struct gen7_mfd_context *gen7_mfd_context)
2342 {
2343     struct i965_driver_data *i965 = i965_driver_data(ctx);
2344     struct object_surface *obj_surface;
2345     VAPictureParameterBufferJPEGBaseline *pic_param;
2346     int subsampling = SUBSAMPLE_YUV420;
2347
2348     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2349
2350     if (pic_param->num_components == 1)
2351         subsampling = SUBSAMPLE_YUV400;
2352     else if (pic_param->num_components == 3) {
2353         int h1 = pic_param->components[0].h_sampling_factor;
2354         int h2 = pic_param->components[1].h_sampling_factor;
2355         int h3 = pic_param->components[2].h_sampling_factor;
2356         int v1 = pic_param->components[0].v_sampling_factor;
2357         int v2 = pic_param->components[1].v_sampling_factor;
2358         int v3 = pic_param->components[2].v_sampling_factor;
2359
2360         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2361             v1 == 2 && v2 == 1 && v3 == 1)
2362             subsampling = SUBSAMPLE_YUV420;
2363         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2364                  v1 == 1 && v2 == 1 && v3 == 1)
2365             subsampling = SUBSAMPLE_YUV422H;
2366         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2367                  v1 == 1 && v2 == 1 && v3 == 1)
2368             subsampling = SUBSAMPLE_YUV444;
2369         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2370                  v1 == 1 && v2 == 1 && v3 == 1)
2371             subsampling = SUBSAMPLE_YUV411;
2372         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2373                  v1 == 2 && v2 == 1 && v3 == 1)
2374             subsampling = SUBSAMPLE_YUV422V;
2375         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2376                  v1 == 2 && v2 == 2 && v3 == 2)
2377             subsampling = SUBSAMPLE_YUV422H;
2378         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2379                  v1 == 2 && v2 == 1 && v3 == 1)
2380             subsampling = SUBSAMPLE_YUV422V;
2381         else
2382             assert(0);
2383     } else {
2384         assert(0);
2385     }
2386
2387     /* Current decoded picture */
2388     obj_surface = SURFACE(decode_state->current_render_target);
2389     assert(obj_surface);
2390     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('I','M','C','1'), subsampling);
2391
2392     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2393     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2394     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2395     gen7_mfd_context->pre_deblocking_output.valid = 1;
2396
2397     gen7_mfd_context->post_deblocking_output.bo = NULL;
2398     gen7_mfd_context->post_deblocking_output.valid = 0;
2399
2400     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2401     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2402
2403     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2404     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2405
2406     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2407     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2408
2409     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2410     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2411
2412     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2413     gen7_mfd_context->bitplane_read_buffer.valid = 0;
2414 }
2415
2416 static const int va_to_gen7_jpeg_rotation[4] = {
2417     GEN7_JPEG_ROTATION_0,
2418     GEN7_JPEG_ROTATION_90,
2419     GEN7_JPEG_ROTATION_180,
2420     GEN7_JPEG_ROTATION_270
2421 };
2422
2423 static void
2424 gen75_mfd_jpeg_pic_state(VADriverContextP ctx,
2425                         struct decode_state *decode_state,
2426                         struct gen7_mfd_context *gen7_mfd_context)
2427 {
2428     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2429     VAPictureParameterBufferJPEGBaseline *pic_param;
2430     int chroma_type = GEN7_YUV420;
2431     int frame_width_in_blks;
2432     int frame_height_in_blks;
2433
2434     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2435     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2436
2437     if (pic_param->num_components == 1)
2438         chroma_type = GEN7_YUV400;
2439     else if (pic_param->num_components == 3) {
2440         int h1 = pic_param->components[0].h_sampling_factor;
2441         int h2 = pic_param->components[1].h_sampling_factor;
2442         int h3 = pic_param->components[2].h_sampling_factor;
2443         int v1 = pic_param->components[0].v_sampling_factor;
2444         int v2 = pic_param->components[1].v_sampling_factor;
2445         int v3 = pic_param->components[2].v_sampling_factor;
2446
2447         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2448             v1 == 2 && v2 == 1 && v3 == 1)
2449             chroma_type = GEN7_YUV420;
2450         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2451                  v1 == 1 && v2 == 1 && v3 == 1)
2452             chroma_type = GEN7_YUV422H_2Y;
2453         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2454                  v1 == 1 && v2 == 1 && v3 == 1)
2455             chroma_type = GEN7_YUV444;
2456         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2457                  v1 == 1 && v2 == 1 && v3 == 1)
2458             chroma_type = GEN7_YUV411;
2459         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2460                  v1 == 2 && v2 == 1 && v3 == 1)
2461             chroma_type = GEN7_YUV422V_2Y;
2462         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2463                  v1 == 2 && v2 == 2 && v3 == 2)
2464             chroma_type = GEN7_YUV422H_4Y;
2465         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2466                  v1 == 2 && v2 == 1 && v3 == 1)
2467             chroma_type = GEN7_YUV422V_4Y;
2468         else
2469             assert(0);
2470     }
2471
2472     if (chroma_type == GEN7_YUV400 ||
2473         chroma_type == GEN7_YUV444 ||
2474         chroma_type == GEN7_YUV422V_2Y) {
2475         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2476         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2477     } else if (chroma_type == GEN7_YUV411) {
2478         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2479         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2480     } else {
2481         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2482         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2483     }
2484
2485     BEGIN_BCS_BATCH(batch, 3);
2486     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2487     OUT_BCS_BATCH(batch,
2488                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2489                   (chroma_type << 0));
2490     OUT_BCS_BATCH(batch,
2491                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2492                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2493     ADVANCE_BCS_BATCH(batch);
2494 }
2495
2496 static const int va_to_gen7_jpeg_hufftable[2] = {
2497     MFX_HUFFTABLE_ID_Y,
2498     MFX_HUFFTABLE_ID_UV
2499 };
2500
2501 static void
2502 gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2503                                struct decode_state *decode_state,
2504                                struct gen7_mfd_context *gen7_mfd_context,
2505                                int num_tables)
2506 {
2507     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2508     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2509     int index;
2510
2511     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2512         return;
2513
2514     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2515
2516     for (index = 0; index < num_tables; index++) {
2517         int id = va_to_gen7_jpeg_hufftable[index];
2518         if (!huffman_table->load_huffman_table[index])
2519             continue;
2520         BEGIN_BCS_BATCH(batch, 53);
2521         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2522         OUT_BCS_BATCH(batch, id);
2523         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2524         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2525         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2526         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2527         ADVANCE_BCS_BATCH(batch);
2528     }
2529 }
2530
2531 static const int va_to_gen7_jpeg_qm[5] = {
2532     -1,
2533     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2534     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2535     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2536     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2537 };
2538
2539 static void
2540 gen75_mfd_jpeg_qm_state(VADriverContextP ctx,
2541                        struct decode_state *decode_state,
2542                        struct gen7_mfd_context *gen7_mfd_context)
2543 {
2544     VAPictureParameterBufferJPEGBaseline *pic_param;
2545     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2546     int index;
2547
2548     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2549         return;
2550
2551     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2552     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2553
2554     assert(pic_param->num_components <= 3);
2555
2556     for (index = 0; index < pic_param->num_components; index++) {
2557         int qm_type = va_to_gen7_jpeg_qm[pic_param->components[index].component_id - pic_param->components[0].component_id + 1];
2558         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2559         unsigned char raster_qm[64];
2560         int j;
2561
2562         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2563             continue;
2564
2565         for (j = 0; j < 64; j++)
2566             raster_qm[zigzag_direct[j]] = qm[j];
2567
2568         gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2569     }
2570 }
2571
2572 static void
2573 gen75_mfd_jpeg_bsd_object(VADriverContextP ctx,
2574                          VAPictureParameterBufferJPEGBaseline *pic_param,
2575                          VASliceParameterBufferJPEGBaseline *slice_param,
2576                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2577                          dri_bo *slice_data_bo,
2578                          struct gen7_mfd_context *gen7_mfd_context)
2579 {
2580     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2581     int scan_component_mask = 0;
2582     int i;
2583
2584     assert(slice_param->num_components > 0);
2585     assert(slice_param->num_components < 4);
2586     assert(slice_param->num_components <= pic_param->num_components);
2587
2588     for (i = 0; i < slice_param->num_components; i++) {
2589         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2590         case 1:
2591             scan_component_mask |= (1 << 0);
2592             break;
2593         case 2:
2594             scan_component_mask |= (1 << 1);
2595             break;
2596         case 3:
2597             scan_component_mask |= (1 << 2);
2598             break;
2599         default:
2600             assert(0);
2601             break;
2602         }
2603     }
2604
2605     BEGIN_BCS_BATCH(batch, 6);
2606     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2607     OUT_BCS_BATCH(batch,
2608                   slice_param->slice_data_size);
2609     OUT_BCS_BATCH(batch,
2610                   slice_param->slice_data_offset);
2611     OUT_BCS_BATCH(batch,
2612                   slice_param->slice_horizontal_position << 16 |
2613                   slice_param->slice_vertical_position << 0);
2614     OUT_BCS_BATCH(batch,
2615                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2616                   (scan_component_mask << 27) |                 /* scan components */
2617                   (0 << 26) |   /* disable interrupt allowed */
2618                   (slice_param->num_mcus << 0));                /* MCU count */
2619     OUT_BCS_BATCH(batch,
2620                   (slice_param->restart_interval << 0));    /* RestartInterval */
2621     ADVANCE_BCS_BATCH(batch);
2622 }
2623
2624 /* Workaround for JPEG decoding on Ivybridge */
2625
2626 VAStatus
2627 i965_DestroySurfaces(VADriverContextP ctx,
2628                      VASurfaceID *surface_list,
2629                      int num_surfaces);
2630 VAStatus
2631 i965_CreateSurfaces(VADriverContextP ctx,
2632                     int width,
2633                     int height,
2634                     int format,
2635                     int num_surfaces,
2636                     VASurfaceID *surfaces);
2637
2638 static struct {
2639     int width;
2640     int height;
2641     unsigned char data[32];
2642     int data_size;
2643     int data_bit_offset;
2644     int qp;
2645 } gen7_jpeg_wa_clip = {
2646     16,
2647     16,
2648     {
2649         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2650         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2651     },
2652     14,
2653     40,
2654     28,
2655 };
2656
2657 static void
2658 gen75_jpeg_wa_init(VADriverContextP ctx,
2659                   struct gen7_mfd_context *gen7_mfd_context)
2660 {
2661     struct i965_driver_data *i965 = i965_driver_data(ctx);
2662     VAStatus status;
2663     struct object_surface *obj_surface;
2664
2665     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2666         i965_DestroySurfaces(ctx,
2667                              &gen7_mfd_context->jpeg_wa_surface_id,
2668                              1);
2669
2670     status = i965_CreateSurfaces(ctx,
2671                                  gen7_jpeg_wa_clip.width,
2672                                  gen7_jpeg_wa_clip.height,
2673                                  VA_RT_FORMAT_YUV420,
2674                                  1,
2675                                  &gen7_mfd_context->jpeg_wa_surface_id);
2676     assert(status == VA_STATUS_SUCCESS);
2677
2678     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2679     assert(obj_surface);
2680     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
2681
2682     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2683         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2684                                                                "JPEG WA data",
2685                                                                0x1000,
2686                                                                0x1000);
2687         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2688                        0,
2689                        gen7_jpeg_wa_clip.data_size,
2690                        gen7_jpeg_wa_clip.data);
2691     }
2692 }
2693
2694 static void
2695 gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2696                               struct gen7_mfd_context *gen7_mfd_context)
2697 {
2698     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2699
2700     BEGIN_BCS_BATCH(batch, 5);
2701     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2702     OUT_BCS_BATCH(batch,
2703                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2704                   (MFD_MODE_VLD << 15) | /* VLD mode */
2705                   (0 << 10) | /* disable Stream-Out */
2706                   (0 << 9)  | /* Post Deblocking Output */
2707                   (1 << 8)  | /* Pre Deblocking Output */
2708                   (0 << 5)  | /* not in stitch mode */
2709                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2710                   (MFX_FORMAT_AVC << 0));
2711     OUT_BCS_BATCH(batch,
2712                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2713                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2714                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2715                   (0 << 1)  |
2716                   (0 << 0));
2717     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2718     OUT_BCS_BATCH(batch, 0); /* reserved */
2719     ADVANCE_BCS_BATCH(batch);
2720 }
2721
2722 static void
2723 gen75_jpeg_wa_surface_state(VADriverContextP ctx,
2724                            struct gen7_mfd_context *gen7_mfd_context)
2725 {
2726     struct i965_driver_data *i965 = i965_driver_data(ctx);
2727     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2728     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2729
2730     BEGIN_BCS_BATCH(batch, 6);
2731     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2732     OUT_BCS_BATCH(batch, 0);
2733     OUT_BCS_BATCH(batch,
2734                   ((obj_surface->orig_width - 1) << 18) |
2735                   ((obj_surface->orig_height - 1) << 4));
2736     OUT_BCS_BATCH(batch,
2737                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2738                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2739                   (0 << 22) | /* surface object control state, ignored */
2740                   ((obj_surface->width - 1) << 3) | /* pitch */
2741                   (0 << 2)  | /* must be 0 */
2742                   (1 << 1)  | /* must be tiled */
2743                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2744     OUT_BCS_BATCH(batch,
2745                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2746                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2747     OUT_BCS_BATCH(batch,
2748                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2749                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2750     ADVANCE_BCS_BATCH(batch);
2751 }
2752
2753 static void
2754 gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx,
2755                                  struct gen7_mfd_context *gen7_mfd_context)
2756 {
2757     struct i965_driver_data *i965 = i965_driver_data(ctx);
2758     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2759     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2760     dri_bo *intra_bo;
2761     int i;
2762
2763     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2764                             "intra row store",
2765                             128 * 64,
2766                             0x1000);
2767
2768     BEGIN_BCS_BATCH(batch, 61);
2769     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
2770     OUT_BCS_RELOC(batch,
2771                   obj_surface->bo,
2772                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2773                   0);
2774         OUT_BCS_BATCH(batch, 0);
2775         OUT_BCS_BATCH(batch, 0);
2776
2777
2778     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2779         OUT_BCS_BATCH(batch, 0);
2780         OUT_BCS_BATCH(batch, 0);
2781
2782         /* uncompressed-video & stream out 7-12 */
2783     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2784     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2785         OUT_BCS_BATCH(batch, 0);
2786         OUT_BCS_BATCH(batch, 0);
2787         OUT_BCS_BATCH(batch, 0);
2788         OUT_BCS_BATCH(batch, 0);
2789
2790         /* the DW 13-15 is for intra row store scratch */
2791     OUT_BCS_RELOC(batch,
2792                   intra_bo,
2793                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2794                   0);
2795         OUT_BCS_BATCH(batch, 0);
2796         OUT_BCS_BATCH(batch, 0);
2797
2798         /* the DW 16-18 is for deblocking filter */
2799     OUT_BCS_BATCH(batch, 0);
2800         OUT_BCS_BATCH(batch, 0);
2801         OUT_BCS_BATCH(batch, 0);
2802
2803     /* DW 19..50 */
2804     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2805         OUT_BCS_BATCH(batch, 0);
2806         OUT_BCS_BATCH(batch, 0);
2807     }
2808     OUT_BCS_BATCH(batch, 0);
2809
2810         /* the DW52-54 is for mb status address */
2811     OUT_BCS_BATCH(batch, 0);
2812         OUT_BCS_BATCH(batch, 0);
2813         OUT_BCS_BATCH(batch, 0);
2814         /* the DW56-60 is for ILDB & second ILDB address */
2815     OUT_BCS_BATCH(batch, 0);
2816         OUT_BCS_BATCH(batch, 0);
2817         OUT_BCS_BATCH(batch, 0);
2818     OUT_BCS_BATCH(batch, 0);
2819         OUT_BCS_BATCH(batch, 0);
2820         OUT_BCS_BATCH(batch, 0);
2821
2822     ADVANCE_BCS_BATCH(batch);
2823
2824     dri_bo_unreference(intra_bo);
2825 }
2826 static void
2827 gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2828                                  struct gen7_mfd_context *gen7_mfd_context)
2829 {
2830     struct i965_driver_data *i965 = i965_driver_data(ctx);
2831     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2832     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2833     dri_bo *intra_bo;
2834     int i;
2835
2836         if (IS_STEPPING_BPLUS(i965)) {
2837                 gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context);
2838                 return;
2839         }
2840     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2841                             "intra row store",
2842                             128 * 64,
2843                             0x1000);
2844
2845     BEGIN_BCS_BATCH(batch, 25);
2846     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
2847     OUT_BCS_RELOC(batch,
2848                   obj_surface->bo,
2849                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2850                   0);
2851
2852     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2853
2854     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2855     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2856
2857     OUT_BCS_RELOC(batch,
2858                   intra_bo,
2859                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2860                   0);
2861
2862     OUT_BCS_BATCH(batch, 0);
2863
2864     /* DW 7..22 */
2865     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2866         OUT_BCS_BATCH(batch, 0);
2867     }
2868
2869     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2870     OUT_BCS_BATCH(batch, 0);
2871     ADVANCE_BCS_BATCH(batch);
2872
2873     dri_bo_unreference(intra_bo);
2874 }
2875
2876 static void
2877 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
2878                                      struct gen7_mfd_context *gen7_mfd_context)
2879 {
2880     struct i965_driver_data *i965 = i965_driver_data(ctx);
2881     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2882     dri_bo *bsd_mpc_bo, *mpr_bo;
2883
2884     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2885                               "bsd mpc row store",
2886                               11520, /* 1.5 * 120 * 64 */
2887                               0x1000);
2888
2889     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2890                           "mpr row store",
2891                           7680, /* 1. 0 * 120 * 64 */
2892                           0x1000);
2893
2894     BEGIN_BCS_BATCH(batch, 10);
2895     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
2896
2897     OUT_BCS_RELOC(batch,
2898                   bsd_mpc_bo,
2899                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2900                   0);
2901
2902     OUT_BCS_BATCH(batch, 0);
2903     OUT_BCS_BATCH(batch, 0);
2904
2905     OUT_BCS_RELOC(batch,
2906                   mpr_bo,
2907                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2908                   0);
2909     OUT_BCS_BATCH(batch, 0);
2910     OUT_BCS_BATCH(batch, 0);
2911
2912     OUT_BCS_BATCH(batch, 0);
2913     OUT_BCS_BATCH(batch, 0);
2914     OUT_BCS_BATCH(batch, 0);
2915
2916     ADVANCE_BCS_BATCH(batch);
2917
2918     dri_bo_unreference(bsd_mpc_bo);
2919     dri_bo_unreference(mpr_bo);
2920 }
2921
2922 static void
2923 gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2924                                      struct gen7_mfd_context *gen7_mfd_context)
2925 {
2926     struct i965_driver_data *i965 = i965_driver_data(ctx);
2927     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2928     dri_bo *bsd_mpc_bo, *mpr_bo;
2929
2930     if (IS_STEPPING_BPLUS(i965)) {
2931         gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(ctx, gen7_mfd_context);
2932         return;
2933     }
2934
2935     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2936                               "bsd mpc row store",
2937                               11520, /* 1.5 * 120 * 64 */
2938                               0x1000);
2939
2940     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2941                           "mpr row store",
2942                           7680, /* 1. 0 * 120 * 64 */
2943                           0x1000);
2944
2945     BEGIN_BCS_BATCH(batch, 4);
2946     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2947
2948     OUT_BCS_RELOC(batch,
2949                   bsd_mpc_bo,
2950                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2951                   0);
2952
2953     OUT_BCS_RELOC(batch,
2954                   mpr_bo,
2955                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2956                   0);
2957     OUT_BCS_BATCH(batch, 0);
2958
2959     ADVANCE_BCS_BATCH(batch);
2960
2961     dri_bo_unreference(bsd_mpc_bo);
2962     dri_bo_unreference(mpr_bo);
2963 }
2964
2965 static void
2966 gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2967                           struct gen7_mfd_context *gen7_mfd_context)
2968 {
2969
2970 }
2971
2972 static void
2973 gen75_jpeg_wa_avc_img_state(VADriverContextP ctx,
2974                            struct gen7_mfd_context *gen7_mfd_context)
2975 {
2976     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2977     int img_struct = 0;
2978     int mbaff_frame_flag = 0;
2979     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2980
2981     BEGIN_BCS_BATCH(batch, 16);
2982     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2983     OUT_BCS_BATCH(batch,
2984                   width_in_mbs * height_in_mbs);
2985     OUT_BCS_BATCH(batch,
2986                   ((height_in_mbs - 1) << 16) |
2987                   ((width_in_mbs - 1) << 0));
2988     OUT_BCS_BATCH(batch,
2989                   (0 << 24) |
2990                   (0 << 16) |
2991                   (0 << 14) |
2992                   (0 << 13) |
2993                   (0 << 12) | /* differ from GEN6 */
2994                   (0 << 10) |
2995                   (img_struct << 8));
2996     OUT_BCS_BATCH(batch,
2997                   (1 << 10) | /* 4:2:0 */
2998                   (1 << 7) |  /* CABAC */
2999                   (0 << 6) |
3000                   (0 << 5) |
3001                   (0 << 4) |
3002                   (0 << 3) |
3003                   (1 << 2) |
3004                   (mbaff_frame_flag << 1) |
3005                   (0 << 0));
3006     OUT_BCS_BATCH(batch, 0);
3007     OUT_BCS_BATCH(batch, 0);
3008     OUT_BCS_BATCH(batch, 0);
3009     OUT_BCS_BATCH(batch, 0);
3010     OUT_BCS_BATCH(batch, 0);
3011     OUT_BCS_BATCH(batch, 0);
3012     OUT_BCS_BATCH(batch, 0);
3013     OUT_BCS_BATCH(batch, 0);
3014     OUT_BCS_BATCH(batch, 0);
3015     OUT_BCS_BATCH(batch, 0);
3016     OUT_BCS_BATCH(batch, 0);
3017     ADVANCE_BCS_BATCH(batch);
3018 }
3019
3020 static void
3021 gen75_jpeg_wa_avc_directmode_state_bplus(VADriverContextP ctx,
3022                                   struct gen7_mfd_context *gen7_mfd_context)
3023 {
3024     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3025     int i;
3026
3027     BEGIN_BCS_BATCH(batch, 71);
3028     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
3029
3030     /* reference surfaces 0..15 */
3031     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3032         OUT_BCS_BATCH(batch, 0); /* top */
3033         OUT_BCS_BATCH(batch, 0); /* bottom */
3034     }
3035
3036         OUT_BCS_BATCH(batch, 0);
3037
3038     /* the current decoding frame/field */
3039     OUT_BCS_BATCH(batch, 0); /* top */
3040     OUT_BCS_BATCH(batch, 0);
3041     OUT_BCS_BATCH(batch, 0);
3042
3043     /* POC List */
3044     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3045         OUT_BCS_BATCH(batch, 0);
3046         OUT_BCS_BATCH(batch, 0);
3047     }
3048
3049     OUT_BCS_BATCH(batch, 0);
3050     OUT_BCS_BATCH(batch, 0);
3051
3052     ADVANCE_BCS_BATCH(batch);
3053 }
3054
3055 static void
3056 gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
3057                                   struct gen7_mfd_context *gen7_mfd_context)
3058 {
3059     struct i965_driver_data *i965 = i965_driver_data(ctx);
3060     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3061     int i;
3062
3063     if (IS_STEPPING_BPLUS(i965)) {
3064         gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context);
3065         return;
3066     }
3067
3068     BEGIN_BCS_BATCH(batch, 69);
3069     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
3070
3071     /* reference surfaces 0..15 */
3072     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3073         OUT_BCS_BATCH(batch, 0); /* top */
3074         OUT_BCS_BATCH(batch, 0); /* bottom */
3075     }
3076
3077     /* the current decoding frame/field */
3078     OUT_BCS_BATCH(batch, 0); /* top */
3079     OUT_BCS_BATCH(batch, 0); /* bottom */
3080
3081     /* POC List */
3082     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3083         OUT_BCS_BATCH(batch, 0);
3084         OUT_BCS_BATCH(batch, 0);
3085     }
3086
3087     OUT_BCS_BATCH(batch, 0);
3088     OUT_BCS_BATCH(batch, 0);
3089
3090     ADVANCE_BCS_BATCH(batch);
3091 }
3092
3093 static void
3094 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
3095                                      struct gen7_mfd_context *gen7_mfd_context)
3096 {
3097     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3098
3099     BEGIN_BCS_BATCH(batch, 11);
3100     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3101     OUT_BCS_RELOC(batch,
3102                   gen7_mfd_context->jpeg_wa_slice_data_bo,
3103                   I915_GEM_DOMAIN_INSTRUCTION, 0,
3104                   0);
3105     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3106     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3107     OUT_BCS_BATCH(batch, 0);
3108     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3109     OUT_BCS_BATCH(batch, 0);
3110     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3111     OUT_BCS_BATCH(batch, 0);
3112     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3113     OUT_BCS_BATCH(batch, 0);
3114     ADVANCE_BCS_BATCH(batch);
3115 }
3116
3117 static void
3118 gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
3119                                      struct gen7_mfd_context *gen7_mfd_context)
3120 {
3121     struct i965_driver_data *i965 = i965_driver_data(ctx);
3122     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3123
3124     if (IS_STEPPING_BPLUS(i965)) {
3125         gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context);
3126         return;
3127     }
3128     BEGIN_BCS_BATCH(batch, 11);
3129     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3130     OUT_BCS_RELOC(batch,
3131                   gen7_mfd_context->jpeg_wa_slice_data_bo,
3132                   I915_GEM_DOMAIN_INSTRUCTION, 0,
3133                   0);
3134     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3135     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3136     OUT_BCS_BATCH(batch, 0);
3137     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3138     OUT_BCS_BATCH(batch, 0);
3139     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3140     OUT_BCS_BATCH(batch, 0);
3141     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3142     OUT_BCS_BATCH(batch, 0);
3143     ADVANCE_BCS_BATCH(batch);
3144 }
3145
3146 static void
3147 gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
3148                             struct gen7_mfd_context *gen7_mfd_context)
3149 {
3150     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3151
3152     /* the input bitsteam format on GEN7 differs from GEN6 */
3153     BEGIN_BCS_BATCH(batch, 6);
3154     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
3155     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
3156     OUT_BCS_BATCH(batch, 0);
3157     OUT_BCS_BATCH(batch,
3158                   (0 << 31) |
3159                   (0 << 14) |
3160                   (0 << 12) |
3161                   (0 << 10) |
3162                   (0 << 8));
3163     OUT_BCS_BATCH(batch,
3164                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
3165                   (0 << 5)  |
3166                   (0 << 4)  |
3167                   (1 << 3) | /* LastSlice Flag */
3168                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
3169     OUT_BCS_BATCH(batch, 0);
3170     ADVANCE_BCS_BATCH(batch);
3171 }
3172
3173 static void
3174 gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx,
3175                              struct gen7_mfd_context *gen7_mfd_context)
3176 {
3177     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3178     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
3179     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
3180     int first_mb_in_slice = 0;
3181     int slice_type = SLICE_TYPE_I;
3182
3183     BEGIN_BCS_BATCH(batch, 11);
3184     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
3185     OUT_BCS_BATCH(batch, slice_type);
3186     OUT_BCS_BATCH(batch,
3187                   (num_ref_idx_l1 << 24) |
3188                   (num_ref_idx_l0 << 16) |
3189                   (0 << 8) |
3190                   (0 << 0));
3191     OUT_BCS_BATCH(batch,
3192                   (0 << 29) |
3193                   (1 << 27) |   /* disable Deblocking */
3194                   (0 << 24) |
3195                   (gen7_jpeg_wa_clip.qp << 16) |
3196                   (0 << 8) |
3197                   (0 << 0));
3198     OUT_BCS_BATCH(batch,
3199                   (slice_ver_pos << 24) |
3200                   (slice_hor_pos << 16) |
3201                   (first_mb_in_slice << 0));
3202     OUT_BCS_BATCH(batch,
3203                   (next_slice_ver_pos << 16) |
3204                   (next_slice_hor_pos << 0));
3205     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
3206     OUT_BCS_BATCH(batch, 0);
3207     OUT_BCS_BATCH(batch, 0);
3208     OUT_BCS_BATCH(batch, 0);
3209     OUT_BCS_BATCH(batch, 0);
3210     ADVANCE_BCS_BATCH(batch);
3211 }
3212
3213 static void
3214 gen75_mfd_jpeg_wa(VADriverContextP ctx,
3215                  struct gen7_mfd_context *gen7_mfd_context)
3216 {
3217     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3218     gen75_jpeg_wa_init(ctx, gen7_mfd_context);
3219     intel_batchbuffer_emit_mi_flush(batch);
3220     gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
3221     gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context);
3222     gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
3223     gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
3224     gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
3225     gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
3226     gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
3227
3228     gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
3229     gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
3230     gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
3231 }
3232
3233 void
3234 gen75_mfd_jpeg_decode_picture(VADriverContextP ctx,
3235                              struct decode_state *decode_state,
3236                              struct gen7_mfd_context *gen7_mfd_context)
3237 {
3238     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3239     VAPictureParameterBufferJPEGBaseline *pic_param;
3240     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
3241     dri_bo *slice_data_bo;
3242     int i, j, max_selector = 0;
3243
3244     assert(decode_state->pic_param && decode_state->pic_param->buffer);
3245     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
3246
3247     /* Currently only support Baseline DCT */
3248     gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
3249     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
3250     gen75_mfd_jpeg_wa(ctx, gen7_mfd_context);
3251     intel_batchbuffer_emit_mi_flush(batch);
3252     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3253     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3254     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3255     gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
3256     gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
3257
3258     for (j = 0; j < decode_state->num_slice_params; j++) {
3259         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3260         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3261         slice_data_bo = decode_state->slice_datas[j]->bo;
3262         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3263
3264         if (j == decode_state->num_slice_params - 1)
3265             next_slice_group_param = NULL;
3266         else
3267             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3268
3269         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3270             int component;
3271
3272             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3273
3274             if (i < decode_state->slice_params[j]->num_elements - 1)
3275                 next_slice_param = slice_param + 1;
3276             else
3277                 next_slice_param = next_slice_group_param;
3278
3279             for (component = 0; component < slice_param->num_components; component++) {
3280                 if (max_selector < slice_param->components[component].dc_table_selector)
3281                     max_selector = slice_param->components[component].dc_table_selector;
3282
3283                 if (max_selector < slice_param->components[component].ac_table_selector)
3284                     max_selector = slice_param->components[component].ac_table_selector;
3285             }
3286
3287             slice_param++;
3288         }
3289     }
3290
3291     assert(max_selector < 2);
3292     gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
3293
3294     for (j = 0; j < decode_state->num_slice_params; j++) {
3295         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3296         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3297         slice_data_bo = decode_state->slice_datas[j]->bo;
3298         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3299
3300         if (j == decode_state->num_slice_params - 1)
3301             next_slice_group_param = NULL;
3302         else
3303             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3304
3305         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3306             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3307
3308             if (i < decode_state->slice_params[j]->num_elements - 1)
3309                 next_slice_param = slice_param + 1;
3310             else
3311                 next_slice_param = next_slice_group_param;
3312
3313             gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
3314             slice_param++;
3315         }
3316     }
3317
3318     intel_batchbuffer_end_atomic(batch);
3319     intel_batchbuffer_flush(batch);
3320 }
3321
3322 static void
3323 gen75_mfd_decode_picture(VADriverContextP ctx,
3324                         VAProfile profile,
3325                         union codec_state *codec_state,
3326                         struct hw_context *hw_context)
3327
3328 {
3329     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3330     struct decode_state *decode_state = &codec_state->decode;
3331
3332     assert(gen7_mfd_context);
3333
3334     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
3335
3336     switch (profile) {
3337     case VAProfileMPEG2Simple:
3338     case VAProfileMPEG2Main:
3339         gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
3340         break;
3341
3342     case VAProfileH264Baseline:
3343     case VAProfileH264Main:
3344     case VAProfileH264High:
3345         gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
3346         break;
3347
3348     case VAProfileVC1Simple:
3349     case VAProfileVC1Main:
3350     case VAProfileVC1Advanced:
3351         gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
3352         break;
3353
3354     case VAProfileJPEGBaseline:
3355         gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
3356         break;
3357
3358     default:
3359         assert(0);
3360         break;
3361     }
3362 }
3363
3364 static void
3365 gen75_mfd_context_destroy(void *hw_context)
3366 {
3367     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3368
3369     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
3370     gen7_mfd_context->post_deblocking_output.bo = NULL;
3371
3372     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
3373     gen7_mfd_context->pre_deblocking_output.bo = NULL;
3374
3375     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
3376     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
3377
3378     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
3379     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
3380
3381     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
3382     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
3383
3384     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
3385     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
3386
3387     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
3388     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
3389
3390     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
3391
3392     intel_batchbuffer_free(gen7_mfd_context->base.batch);
3393     free(gen7_mfd_context);
3394 }
3395
3396 static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx,
3397                                     struct gen7_mfd_context *gen7_mfd_context)
3398 {
3399     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
3400     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
3401     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
3402     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
3403 }
3404
3405 struct hw_context *
3406 gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
3407 {
3408     struct intel_driver_data *intel = intel_driver_data(ctx);
3409     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
3410     int i;
3411
3412     gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
3413     gen7_mfd_context->base.run = gen75_mfd_decode_picture;
3414     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
3415
3416     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
3417         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
3418         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
3419     }
3420
3421     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
3422
3423     switch (obj_config->profile) {
3424     case VAProfileMPEG2Simple:
3425     case VAProfileMPEG2Main:
3426         gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
3427         break;
3428
3429     case VAProfileH264Baseline:
3430     case VAProfileH264Main:
3431     case VAProfileH264High:
3432         gen75_mfd_avc_context_init(ctx, gen7_mfd_context);
3433         break;
3434     default:
3435         break;
3436     }
3437     return (struct hw_context *)gen7_mfd_context;
3438 }