src/gen75_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zhao  Yakui  <yakui.zhao@intel.com>
  27  *
  28  */
  29
  30 #ifndef HAVE_GEN_AVC_SURFACE
  31 #define HAVE_GEN_AVC_SURFACE 1
  32 #endif
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <assert.h>
  38 #include <va/va_dec_jpeg.h>
  39
  40 #include "intel_batchbuffer.h"
  41 #include "intel_driver.h"
  42
  43 #include "i965_defines.h"
  44 #include "i965_drv_video.h"
  45 #include "i965_decoder_utils.h"
  46
  47 #include "gen7_mfd.h"
  48
  49 #define B0_STEP_REV             2
  50 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
  51
  52 static const uint32_t zigzag_direct[64] = {
  53     0,   1,  8, 16,  9,  2,  3, 10,
  54     17, 24, 32, 25, 18, 11,  4,  5,
  55     12, 19, 26, 33, 40, 48, 41, 34,
  56     27, 20, 13,  6,  7, 14, 21, 28,
  57     35, 42, 49, 56, 57, 50, 43, 36,
  58     29, 22, 15, 23, 30, 37, 44, 51,
  59     58, 59, 52, 45, 38, 31, 39, 46,
  60     53, 60, 61, 54, 47, 55, 62, 63
  61 };
  62
  63 static void
  64 gen75_mfd_avc_frame_store_index(VADriverContextP ctx,
  65                                VAPictureParameterBufferH264 *pic_param,
  66                                struct gen7_mfd_context *gen7_mfd_context)
  67 {
  68     struct i965_driver_data *i965 = i965_driver_data(ctx);
  69     int i, j;
  70
  71     assert(ARRAY_ELEMS(gen7_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
  72
  73     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
  74         int found = 0;
  75
  76         if (gen7_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
  77             continue;
  78
  79         for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
  80             VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
  81             if (ref_pic->flags & VA_PICTURE_H264_INVALID)
  82                 continue;
  83
  84             if (gen7_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
  85                 found = 1;
  86                 break;
  87             }
  88         }
  89
  90         if (!found) {
  91             struct object_surface *obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
  92             obj_surface->flags &= ~SURFACE_REFERENCED;
  93
  94             if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
  95                 dri_bo_unreference(obj_surface->bo);
  96                 obj_surface->bo = NULL;
  97                 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
  98             }
  99
 100             if (obj_surface->free_private_data)
 101                 obj_surface->free_private_data(&obj_surface->private_data);
 102
 103             gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
 104             gen7_mfd_context->reference_surface[i].frame_store_id = -1;
 105         }
 106     }
 107
 108     for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
 109         VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
 110         int found = 0;
 111
 112         if (ref_pic->flags & VA_PICTURE_H264_INVALID)
 113             continue;
 114
 115         for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 116             if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 117                 continue;
 118
 119             if (gen7_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
 120                 found = 1;
 121                 break;
 122             }
 123         }
 124
 125         if (!found) {
 126             int frame_idx;
 127             struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
 128
 129             assert(obj_surface);
 130             i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 131
 132             for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface); frame_idx++) {
 133                 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 134                     if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 135                         continue;
 136
 137                     if (gen7_mfd_context->reference_surface[j].frame_store_id == frame_idx)
 138                         break;
 139                 }
 140
 141                 if (j == ARRAY_ELEMS(gen7_mfd_context->reference_surface))
 142                     break;
 143             }
 144
 145             assert(frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface));
 146
 147             for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 148                 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
 149                     gen7_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
 150                     gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 151                     break;
 152                 }
 153             }
 154         }
 155     }
 156
 157     /* sort */
 158     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface) - 1; i++) {
 159         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 160             gen7_mfd_context->reference_surface[i].frame_store_id == i)
 161             continue;
 162
 163         for (j = i + 1; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 164             if (gen7_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
 165                 gen7_mfd_context->reference_surface[j].frame_store_id == i) {
 166                 VASurfaceID id = gen7_mfd_context->reference_surface[i].surface_id;
 167                 int frame_idx = gen7_mfd_context->reference_surface[i].frame_store_id;
 168
 169                 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[j].surface_id;
 170                 gen7_mfd_context->reference_surface[i].frame_store_id = gen7_mfd_context->reference_surface[j].frame_store_id;
 171                 gen7_mfd_context->reference_surface[j].surface_id = id;
 172                 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 173                 break;
 174             }
 175         }
 176     }
 177 }
 178
 179 static void
 180 gen75_mfd_init_avc_surface(VADriverContextP ctx,
 181                           VAPictureParameterBufferH264 *pic_param,
 182                           struct object_surface *obj_surface)
 183 {
 184     struct i965_driver_data *i965 = i965_driver_data(ctx);
 185     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
 186     int width_in_mbs, height_in_mbs;
 187
 188     obj_surface->free_private_data = gen_free_avc_surface;
 189     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 190     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 191
 192     if (!gen7_avc_surface) {
 193         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
 194         assert((obj_surface->size & 0x3f) == 0);
 195         obj_surface->private_data = gen7_avc_surface;
 196     }
 197
 198     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
 199                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
 200
 201     if (gen7_avc_surface->dmv_top == NULL) {
 202         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
 203                                                  "direct mv w/r buffer",
 204                                                  width_in_mbs * height_in_mbs * 128,
 205                                                  0x1000);
 206         assert(gen7_avc_surface->dmv_top);
 207     }
 208
 209     if (gen7_avc_surface->dmv_bottom_flag &&
 210         gen7_avc_surface->dmv_bottom == NULL) {
 211         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
 212                                                     "direct mv w/r buffer",
 213                                                     width_in_mbs * height_in_mbs * 128,
 214                                                     0x1000);
 215         assert(gen7_avc_surface->dmv_bottom);
 216     }
 217 }
 218
 219 static void
 220 gen75_mfd_pipe_mode_select(VADriverContextP ctx,
 221                           struct decode_state *decode_state,
 222                           int standard_select,
 223                           struct gen7_mfd_context *gen7_mfd_context)
 224 {
 225     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 226
 227     assert(standard_select == MFX_FORMAT_MPEG2 ||
 228            standard_select == MFX_FORMAT_AVC ||
 229            standard_select == MFX_FORMAT_VC1 ||
 230            standard_select == MFX_FORMAT_JPEG);
 231
 232     BEGIN_BCS_BATCH(batch, 5);
 233     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 234     OUT_BCS_BATCH(batch,
 235                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 236                   (MFD_MODE_VLD << 15) | /* VLD mode */
 237                   (0 << 10) | /* disable Stream-Out */
 238                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 239                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 240                   (0 << 5)  | /* not in stitch mode */
 241                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 242                   (standard_select << 0));
 243     OUT_BCS_BATCH(batch,
 244                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 245                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 246                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 247                   (0 << 1)  |
 248                   (0 << 0));
 249     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 250     OUT_BCS_BATCH(batch, 0); /* reserved */
 251     ADVANCE_BCS_BATCH(batch);
 252 }
 253
 254 static void
 255 gen75_mfd_surface_state(VADriverContextP ctx,
 256                        struct decode_state *decode_state,
 257                        int standard_select,
 258                        struct gen7_mfd_context *gen7_mfd_context)
 259 {
 260     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 261     struct i965_driver_data *i965 = i965_driver_data(ctx);
 262     struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
 263     unsigned int y_cb_offset;
 264     unsigned int y_cr_offset;
 265
 266     assert(obj_surface);
 267
 268     y_cb_offset = obj_surface->y_cb_offset;
 269     y_cr_offset = obj_surface->y_cr_offset;
 270
 271     BEGIN_BCS_BATCH(batch, 6);
 272     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 273     OUT_BCS_BATCH(batch, 0);
 274     OUT_BCS_BATCH(batch,
 275                   ((obj_surface->orig_height - 1) << 18) |
 276                   ((obj_surface->orig_width - 1) << 4));
 277     OUT_BCS_BATCH(batch,
 278                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 279                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 280                   (0 << 22) | /* surface object control state, ignored */
 281                   ((obj_surface->width - 1) << 3) | /* pitch */
 282                   (0 << 2)  | /* must be 0 */
 283                   (1 << 1)  | /* must be tiled */
 284                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 285     OUT_BCS_BATCH(batch,
 286                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 287                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 288     OUT_BCS_BATCH(batch,
 289                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 290                   (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void
 295 gen75_mfd_pipe_buf_addr_state_bplus(VADriverContextP ctx,
 296                              struct decode_state *decode_state,
 297                              int standard_select,
 298                              struct gen7_mfd_context *gen7_mfd_context)
 299 {
 300     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 301     struct i965_driver_data *i965 = i965_driver_data(ctx);
 302     int i;
 303
 304     BEGIN_BCS_BATCH(batch, 61);
 305     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
 306         /* Pre-deblock 1-3 */
 307     if (gen7_mfd_context->pre_deblocking_output.valid)
 308         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 309                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 310                       0);
 311     else
 312         OUT_BCS_BATCH(batch, 0);
 313
 314         OUT_BCS_BATCH(batch, 0);
 315         OUT_BCS_BATCH(batch, 0);
 316         /* Post-debloing 4-6 */
 317     if (gen7_mfd_context->post_deblocking_output.valid)
 318         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 319                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 320                       0);
 321     else
 322         OUT_BCS_BATCH(batch, 0);
 323
 324         OUT_BCS_BATCH(batch, 0);
 325         OUT_BCS_BATCH(batch, 0);
 326
 327         /* uncompressed-video & stream out 7-12 */
 328     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 329     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 330         OUT_BCS_BATCH(batch, 0);
 331         OUT_BCS_BATCH(batch, 0);
 332         OUT_BCS_BATCH(batch, 0);
 333         OUT_BCS_BATCH(batch, 0);
 334
 335         /* intra row-store scratch 13-15 */
 336     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 337         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 338                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 339                       0);
 340     else
 341         OUT_BCS_BATCH(batch, 0);
 342
 343         OUT_BCS_BATCH(batch, 0);
 344         OUT_BCS_BATCH(batch, 0);
 345         /* deblocking-filter-row-store 16-18 */
 346     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 347         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 348                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 349                       0);
 350     else
 351         OUT_BCS_BATCH(batch, 0);
 352         OUT_BCS_BATCH(batch, 0);
 353         OUT_BCS_BATCH(batch, 0);
 354
 355     /* DW 19..50 */
 356     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 357         struct object_surface *obj_surface;
 358
 359         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 360             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 361             assert(obj_surface && obj_surface->bo);
 362
 363             OUT_BCS_RELOC(batch, obj_surface->bo,
 364                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 365                           0);
 366         } else {
 367             OUT_BCS_BATCH(batch, 0);
 368         }
 369             OUT_BCS_BATCH(batch, 0);
 370     }
 371         /* reference property 51 */
 372     OUT_BCS_BATCH(batch, 0);
 373
 374         /* Macroblock status & ILDB 52-57 */
 375         OUT_BCS_BATCH(batch, 0);
 376         OUT_BCS_BATCH(batch, 0);
 377         OUT_BCS_BATCH(batch, 0);
 378         OUT_BCS_BATCH(batch, 0);
 379         OUT_BCS_BATCH(batch, 0);
 380         OUT_BCS_BATCH(batch, 0);
 381
 382         /* the second Macroblock status 58-60 */
 383         OUT_BCS_BATCH(batch, 0);
 384         OUT_BCS_BATCH(batch, 0);
 385         OUT_BCS_BATCH(batch, 0);
 386     ADVANCE_BCS_BATCH(batch);
 387 }
 388
 389 static void
 390 gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 391                              struct decode_state *decode_state,
 392                              int standard_select,
 393                              struct gen7_mfd_context *gen7_mfd_context)
 394 {
 395     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 396     struct i965_driver_data *i965 = i965_driver_data(ctx);
 397     int i;
 398
 399         if (IS_STEPPING_BPLUS(i965)) {
 400                 gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state,
 401                                 standard_select, gen7_mfd_context);
 402                 return;
 403         }
 404     BEGIN_BCS_BATCH(batch, 25);
 405     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
 406     if (gen7_mfd_context->pre_deblocking_output.valid)
 407         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 408                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 409                       0);
 410     else
 411         OUT_BCS_BATCH(batch, 0);
 412
 413     if (gen7_mfd_context->post_deblocking_output.valid)
 414         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 415                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 416                       0);
 417     else
 418         OUT_BCS_BATCH(batch, 0);
 419
 420     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 421     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 422
 423     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 424         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 425                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 426                       0);
 427     else
 428         OUT_BCS_BATCH(batch, 0);
 429
 430     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 431         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 432                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 433                       0);
 434     else
 435         OUT_BCS_BATCH(batch, 0);
 436
 437     /* DW 7..22 */
 438     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 439         struct object_surface *obj_surface;
 440
 441         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 442             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 443             assert(obj_surface && obj_surface->bo);
 444
 445             OUT_BCS_RELOC(batch, obj_surface->bo,
 446                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 447                           0);
 448         } else {
 449             OUT_BCS_BATCH(batch, 0);
 450         }
 451     }
 452
 453     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 454     OUT_BCS_BATCH(batch, 0);   /* ignore DW24 for decoding */
 455     ADVANCE_BCS_BATCH(batch);
 456 }
 457
 458 static void
 459 gen75_mfd_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
 460                                  dri_bo *slice_data_bo,
 461                                  int standard_select,
 462                                  struct gen7_mfd_context *gen7_mfd_context)
 463 {
 464     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 465
 466     BEGIN_BCS_BATCH(batch, 26);
 467     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
 468         /* MFX In BS 1-5 */
 469     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 470     OUT_BCS_BATCH(batch, 0);
 471     OUT_BCS_BATCH(batch, 0);
 472         /* Upper bound 4-5 */
 473     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 474     OUT_BCS_BATCH(batch, 0);
 475
 476         /* MFX indirect MV 6-10 */
 477     OUT_BCS_BATCH(batch, 0);
 478     OUT_BCS_BATCH(batch, 0);
 479     OUT_BCS_BATCH(batch, 0);
 480     OUT_BCS_BATCH(batch, 0);
 481     OUT_BCS_BATCH(batch, 0);
 482
 483         /* MFX IT_COFF 11-15 */
 484     OUT_BCS_BATCH(batch, 0);
 485     OUT_BCS_BATCH(batch, 0);
 486     OUT_BCS_BATCH(batch, 0);
 487     OUT_BCS_BATCH(batch, 0);
 488     OUT_BCS_BATCH(batch, 0);
 489
 490         /* MFX IT_DBLK 16-20 */
 491     OUT_BCS_BATCH(batch, 0);
 492     OUT_BCS_BATCH(batch, 0);
 493     OUT_BCS_BATCH(batch, 0);
 494     OUT_BCS_BATCH(batch, 0);
 495     OUT_BCS_BATCH(batch, 0);
 496
 497         /* MFX PAK_BSE object for encoder 21-25 */
 498     OUT_BCS_BATCH(batch, 0);
 499     OUT_BCS_BATCH(batch, 0);
 500     OUT_BCS_BATCH(batch, 0);
 501     OUT_BCS_BATCH(batch, 0);
 502     OUT_BCS_BATCH(batch, 0);
 503
 504     ADVANCE_BCS_BATCH(batch);
 505 }
 506
 507 static void
 508 gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 509                                  dri_bo *slice_data_bo,
 510                                  int standard_select,
 511                                  struct gen7_mfd_context *gen7_mfd_context)
 512 {
 513     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 514
 515     struct i965_driver_data *i965 = i965_driver_data(ctx);
 516
 517         if (IS_STEPPING_BPLUS(i965)) {
 518                 gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo,
 519                                         standard_select, gen7_mfd_context);
 520                 return;
 521         }
 522     BEGIN_BCS_BATCH(batch, 11);
 523     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 524     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 525     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 526     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 527     OUT_BCS_BATCH(batch, 0);
 528     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 529     OUT_BCS_BATCH(batch, 0);
 530     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 531     OUT_BCS_BATCH(batch, 0);
 532     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 533     OUT_BCS_BATCH(batch, 0);
 534     ADVANCE_BCS_BATCH(batch);
 535 }
 536
 537 static void
 538 gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
 539                                  struct decode_state *decode_state,
 540                                  int standard_select,
 541                                  struct gen7_mfd_context *gen7_mfd_context)
 542 {
 543     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 544
 545     BEGIN_BCS_BATCH(batch, 10);
 546     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
 547
 548     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 549         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 550                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 551                       0);
 552         else
 553                 OUT_BCS_BATCH(batch, 0);
 554
 555     OUT_BCS_BATCH(batch, 0);
 556     OUT_BCS_BATCH(batch, 0);
 557         /* MPR Row Store Scratch buffer 4-6 */
 558     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 559         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 560                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 561                       0);
 562     else
 563             OUT_BCS_BATCH(batch, 0);
 564     OUT_BCS_BATCH(batch, 0);
 565     OUT_BCS_BATCH(batch, 0);
 566
 567         /* Bitplane 7-9 */
 568     if (gen7_mfd_context->bitplane_read_buffer.valid)
 569         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 570                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 571                       0);
 572     else
 573         OUT_BCS_BATCH(batch, 0);
 574     OUT_BCS_BATCH(batch, 0);
 575     OUT_BCS_BATCH(batch, 0);
 576     ADVANCE_BCS_BATCH(batch);
 577 }
 578
 579 static void
 580 gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 581                                  struct decode_state *decode_state,
 582                                  int standard_select,
 583                                  struct gen7_mfd_context *gen7_mfd_context)
 584 {
 585     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 586     struct i965_driver_data *i965 = i965_driver_data(ctx);
 587
 588         if (IS_STEPPING_BPLUS(i965)) {
 589                 gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state,
 590                                         standard_select, gen7_mfd_context);
 591                 return;
 592         }
 593
 594     BEGIN_BCS_BATCH(batch, 4);
 595     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 596
 597     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 598         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 599                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 600                       0);
 601     else
 602         OUT_BCS_BATCH(batch, 0);
 603
 604     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 605         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 606                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 607                       0);
 608     else
 609         OUT_BCS_BATCH(batch, 0);
 610
 611     if (gen7_mfd_context->bitplane_read_buffer.valid)
 612         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 613                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 614                       0);
 615     else
 616         OUT_BCS_BATCH(batch, 0);
 617
 618     ADVANCE_BCS_BATCH(batch);
 619 }
 620
 621 #if 0
 622 static void
 623 gen7_mfd_aes_state(VADriverContextP ctx,
 624                    struct decode_state *decode_state,
 625                    int standard_select)
 626 {
 627     /* FIXME */
 628 }
 629 #endif
 630
 631 static void
 632 gen75_mfd_qm_state(VADriverContextP ctx,
 633                   int qm_type,
 634                   unsigned char *qm,
 635                   int qm_length,
 636                   struct gen7_mfd_context *gen7_mfd_context)
 637 {
 638     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 639     unsigned int qm_buffer[16];
 640
 641     assert(qm_length <= 16 * 4);
 642     memcpy(qm_buffer, qm, qm_length);
 643
 644     BEGIN_BCS_BATCH(batch, 18);
 645     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 646     OUT_BCS_BATCH(batch, qm_type << 0);
 647     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 648     ADVANCE_BCS_BATCH(batch);
 649 }
 650
 651 #if 0
 652 static void
 653 gen7_mfd_wait(VADriverContextP ctx,
 654               struct decode_state *decode_state,
 655               int standard_select,
 656               struct gen7_mfd_context *gen7_mfd_context)
 657 {
 658     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 659
 660     BEGIN_BCS_BATCH(batch, 1);
 661     OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
 662     ADVANCE_BCS_BATCH(batch);
 663 }
 664 #endif
 665
 666 static void
 667 gen75_mfd_avc_img_state(VADriverContextP ctx,
 668                        struct decode_state *decode_state,
 669                        struct gen7_mfd_context *gen7_mfd_context)
 670 {
 671     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 672     int img_struct;
 673     int mbaff_frame_flag;
 674     unsigned int width_in_mbs, height_in_mbs;
 675     VAPictureParameterBufferH264 *pic_param;
 676
 677     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 678     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 679     assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
 680
 681     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 682         img_struct = 1;
 683     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 684         img_struct = 3;
 685     else
 686         img_struct = 0;
 687
 688     if ((img_struct & 0x1) == 0x1) {
 689         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 690     } else {
 691         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 692     }
 693
 694     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 695         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 696         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 697     } else {
 698         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 699     }
 700
 701     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 702                         !pic_param->pic_fields.bits.field_pic_flag);
 703
 704     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 705     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 706
 707     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 708     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 709            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 710     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 711
 712     BEGIN_BCS_BATCH(batch, 17);
 713     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2));
 714     OUT_BCS_BATCH(batch,
 715                   width_in_mbs * height_in_mbs);
 716     OUT_BCS_BATCH(batch,
 717                   ((height_in_mbs - 1) << 16) |
 718                   ((width_in_mbs - 1) << 0));
 719     OUT_BCS_BATCH(batch,
 720                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 721                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 722                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 723                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 724                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 725                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 726                   (img_struct << 8));
 727     OUT_BCS_BATCH(batch,
 728                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 729                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 730                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 731                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 732                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 733                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 734                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 735                   (mbaff_frame_flag << 1) |
 736                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 737     OUT_BCS_BATCH(batch, 0);
 738     OUT_BCS_BATCH(batch, 0);
 739     OUT_BCS_BATCH(batch, 0);
 740     OUT_BCS_BATCH(batch, 0);
 741     OUT_BCS_BATCH(batch, 0);
 742     OUT_BCS_BATCH(batch, 0);
 743     OUT_BCS_BATCH(batch, 0);
 744     OUT_BCS_BATCH(batch, 0);
 745     OUT_BCS_BATCH(batch, 0);
 746     OUT_BCS_BATCH(batch, 0);
 747     OUT_BCS_BATCH(batch, 0);
 748     OUT_BCS_BATCH(batch, 0);
 749     ADVANCE_BCS_BATCH(batch);
 750 }
 751
 752 static void
 753 gen75_mfd_avc_qm_state(VADriverContextP ctx,
 754                       struct decode_state *decode_state,
 755                       struct gen7_mfd_context *gen7_mfd_context)
 756 {
 757     VAIQMatrixBufferH264 *iq_matrix;
 758     VAPictureParameterBufferH264 *pic_param;
 759
 760     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 761         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 762     else
 763         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 764
 765     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 766     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 767
 768     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 769     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 770
 771     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 772         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 773         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 774     }
 775 }
 776
 777 static void
 778 gen75_mfd_avc_picid_state(VADriverContextP ctx,
 779                       struct decode_state *decode_state,
 780                       struct gen7_mfd_context *gen7_mfd_context)
 781 {
 782     struct i965_driver_data *i965 = i965_driver_data(ctx);
 783     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 784
 785     BEGIN_BCS_BATCH(batch, 10);
 786     OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2));
 787     OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping
 788     OUT_BCS_BATCH(batch, 0);
 789     OUT_BCS_BATCH(batch, 0);
 790     OUT_BCS_BATCH(batch, 0);
 791     OUT_BCS_BATCH(batch, 0);
 792     OUT_BCS_BATCH(batch, 0);
 793     OUT_BCS_BATCH(batch, 0);
 794     OUT_BCS_BATCH(batch, 0);
 795     OUT_BCS_BATCH(batch, 0);
 796     ADVANCE_BCS_BATCH(batch);
 797 }
 798
 799 static void
 800 gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx,
 801                               VAPictureParameterBufferH264 *pic_param,
 802                               VASliceParameterBufferH264 *slice_param,
 803                               struct gen7_mfd_context *gen7_mfd_context)
 804 {
 805     struct i965_driver_data *i965 = i965_driver_data(ctx);
 806     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 807     struct object_surface *obj_surface;
 808     GenAvcSurface *gen7_avc_surface;
 809     VAPictureH264 *va_pic;
 810     int i, j;
 811
 812     BEGIN_BCS_BATCH(batch, 71);
 813     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
 814
 815     /* reference surfaces 0..15 */
 816     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 817         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 818             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 819             assert(obj_surface);
 820             gen7_avc_surface = obj_surface->private_data;
 821
 822             if (gen7_avc_surface == NULL) {
 823                 OUT_BCS_BATCH(batch, 0);
 824                 OUT_BCS_BATCH(batch, 0);
 825             } else {
 826                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 827                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 828                               0);
 829                 OUT_BCS_BATCH(batch, 0);
 830             }
 831         } else {
 832             OUT_BCS_BATCH(batch, 0);
 833             OUT_BCS_BATCH(batch, 0);
 834         }
 835     }
 836         OUT_BCS_BATCH(batch, 0);
 837
 838     /* the current decoding frame/field */
 839     va_pic = &pic_param->CurrPic;
 840     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 841     obj_surface = SURFACE(va_pic->picture_id);
 842     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 843     gen7_avc_surface = obj_surface->private_data;
 844
 845     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 846                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 847                   0);
 848
 849         OUT_BCS_BATCH(batch, 0);
 850         OUT_BCS_BATCH(batch, 0);
 851
 852     /* POC List */
 853     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 854         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 855             int found = 0;
 856             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 857                 va_pic = &pic_param->ReferenceFrames[j];
 858
 859                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 860                     continue;
 861
 862                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 863                     found = 1;
 864                     break;
 865                 }
 866             }
 867
 868             assert(found == 1);
 869             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 870
 871             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 872             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 873         } else {
 874             OUT_BCS_BATCH(batch, 0);
 875             OUT_BCS_BATCH(batch, 0);
 876         }
 877     }
 878
 879     va_pic = &pic_param->CurrPic;
 880     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 881     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 882
 883     ADVANCE_BCS_BATCH(batch);
 884 }
 885
 886 static void
 887 gen75_mfd_avc_directmode_state(VADriverContextP ctx,
 888                               VAPictureParameterBufferH264 *pic_param,
 889                               VASliceParameterBufferH264 *slice_param,
 890                               struct gen7_mfd_context *gen7_mfd_context)
 891 {
 892     struct i965_driver_data *i965 = i965_driver_data(ctx);
 893     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 894     struct object_surface *obj_surface;
 895     GenAvcSurface *gen7_avc_surface;
 896     VAPictureH264 *va_pic;
 897     int i, j;
 898
 899         if (IS_STEPPING_BPLUS(i965)) {
 900                 gen75_mfd_avc_directmode_state_bplus(ctx, pic_param, slice_param,
 901                         gen7_mfd_context);
 902
 903                 return;
 904         }
 905
 906     BEGIN_BCS_BATCH(batch, 69);
 907     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 908
 909     /* reference surfaces 0..15 */
 910     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 911         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 912             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 913             assert(obj_surface);
 914             gen7_avc_surface = obj_surface->private_data;
 915
 916             if (gen7_avc_surface == NULL) {
 917                 OUT_BCS_BATCH(batch, 0);
 918                 OUT_BCS_BATCH(batch, 0);
 919             } else {
 920                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 921                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 922                               0);
 923
 924                 if (gen7_avc_surface->dmv_bottom_flag == 1)
 925                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 926                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 927                                   0);
 928                 else
 929                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 930                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 931                                   0);
 932             }
 933         } else {
 934             OUT_BCS_BATCH(batch, 0);
 935             OUT_BCS_BATCH(batch, 0);
 936         }
 937     }
 938
 939     /* the current decoding frame/field */
 940     va_pic = &pic_param->CurrPic;
 941     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 942     obj_surface = SURFACE(va_pic->picture_id);
 943     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 944     gen7_avc_surface = obj_surface->private_data;
 945
 946     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 947                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 948                   0);
 949
 950     if (gen7_avc_surface->dmv_bottom_flag == 1)
 951         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 952                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 953                       0);
 954     else
 955         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 956                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 957                       0);
 958
 959     /* POC List */
 960     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 961         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 962             int found = 0;
 963             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 964                 va_pic = &pic_param->ReferenceFrames[j];
 965
 966                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 967                     continue;
 968
 969                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 970                     found = 1;
 971                     break;
 972                 }
 973             }
 974
 975             assert(found == 1);
 976             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 977
 978             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 979             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 980         } else {
 981             OUT_BCS_BATCH(batch, 0);
 982             OUT_BCS_BATCH(batch, 0);
 983         }
 984     }
 985
 986     va_pic = &pic_param->CurrPic;
 987     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 988     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 989
 990     ADVANCE_BCS_BATCH(batch);
 991 }
 992
 993 static void
 994 gen75_mfd_avc_slice_state(VADriverContextP ctx,
 995                          VAPictureParameterBufferH264 *pic_param,
 996                          VASliceParameterBufferH264 *slice_param,
 997                          VASliceParameterBufferH264 *next_slice_param,
 998                          struct gen7_mfd_context *gen7_mfd_context)
 999 {
1000     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1001     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1002     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1003     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
1004     int num_ref_idx_l0, num_ref_idx_l1;
1005     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
1006                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
1007     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
1008     int slice_type;
1009
1010     if (slice_param->slice_type == SLICE_TYPE_I ||
1011         slice_param->slice_type == SLICE_TYPE_SI) {
1012         slice_type = SLICE_TYPE_I;
1013     } else if (slice_param->slice_type == SLICE_TYPE_P ||
1014                slice_param->slice_type == SLICE_TYPE_SP) {
1015         slice_type = SLICE_TYPE_P;
1016     } else {
1017         assert(slice_param->slice_type == SLICE_TYPE_B);
1018         slice_type = SLICE_TYPE_B;
1019     }
1020
1021     if (slice_type == SLICE_TYPE_I) {
1022         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
1023         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1024         num_ref_idx_l0 = 0;
1025         num_ref_idx_l1 = 0;
1026     } else if (slice_type == SLICE_TYPE_P) {
1027         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1028         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1029         num_ref_idx_l1 = 0;
1030     } else {
1031         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1032         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
1033     }
1034
1035     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
1036     slice_hor_pos = first_mb_in_slice % width_in_mbs;
1037     slice_ver_pos = first_mb_in_slice / width_in_mbs;
1038
1039     if (next_slice_param) {
1040         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
1041         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
1042         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
1043     } else {
1044         next_slice_hor_pos = 0;
1045         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
1046     }
1047
1048     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
1049     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
1050     OUT_BCS_BATCH(batch, slice_type);
1051     OUT_BCS_BATCH(batch,
1052                   (num_ref_idx_l1 << 24) |
1053                   (num_ref_idx_l0 << 16) |
1054                   (slice_param->chroma_log2_weight_denom << 8) |
1055                   (slice_param->luma_log2_weight_denom << 0));
1056     OUT_BCS_BATCH(batch,
1057                   (slice_param->direct_spatial_mv_pred_flag << 29) |
1058                   (slice_param->disable_deblocking_filter_idc << 27) |
1059                   (slice_param->cabac_init_idc << 24) |
1060                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
1061                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
1062                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
1063     OUT_BCS_BATCH(batch,
1064                   (slice_ver_pos << 24) |
1065                   (slice_hor_pos << 16) |
1066                   (first_mb_in_slice << 0));
1067     OUT_BCS_BATCH(batch,
1068                   (next_slice_ver_pos << 16) |
1069                   (next_slice_hor_pos << 0));
1070     OUT_BCS_BATCH(batch,
1071                   (next_slice_param == NULL) << 19); /* last slice flag */
1072     OUT_BCS_BATCH(batch, 0);
1073     OUT_BCS_BATCH(batch, 0);
1074     OUT_BCS_BATCH(batch, 0);
1075     OUT_BCS_BATCH(batch, 0);
1076     ADVANCE_BCS_BATCH(batch);
1077 }
1078
1079 static inline void
1080 gen75_mfd_avc_ref_idx_state(VADriverContextP ctx,
1081                            VAPictureParameterBufferH264 *pic_param,
1082                            VASliceParameterBufferH264 *slice_param,
1083                            struct gen7_mfd_context *gen7_mfd_context)
1084 {
1085     gen6_send_avc_ref_idx_state(
1086         gen7_mfd_context->base.batch,
1087         slice_param,
1088         gen7_mfd_context->reference_surface
1089     );
1090 }
1091
1092 static void
1093 gen75_mfd_avc_weightoffset_state(VADriverContextP ctx,
1094                                 VAPictureParameterBufferH264 *pic_param,
1095                                 VASliceParameterBufferH264 *slice_param,
1096                                 struct gen7_mfd_context *gen7_mfd_context)
1097 {
1098     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1099     int i, j, num_weight_offset_table = 0;
1100     short weightoffsets[32 * 6];
1101
1102     if ((slice_param->slice_type == SLICE_TYPE_P ||
1103          slice_param->slice_type == SLICE_TYPE_SP) &&
1104         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
1105         num_weight_offset_table = 1;
1106     }
1107
1108     if ((slice_param->slice_type == SLICE_TYPE_B) &&
1109         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
1110         num_weight_offset_table = 2;
1111     }
1112
1113     for (i = 0; i < num_weight_offset_table; i++) {
1114         BEGIN_BCS_BATCH(batch, 98);
1115         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
1116         OUT_BCS_BATCH(batch, i);
1117
1118         if (i == 0) {
1119             for (j = 0; j < 32; j++) {
1120                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
1121                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
1122                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
1123                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
1124                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
1125                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
1126             }
1127         } else {
1128             for (j = 0; j < 32; j++) {
1129                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
1130                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
1131                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
1132                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
1133                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
1134                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
1135             }
1136         }
1137
1138         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
1139         ADVANCE_BCS_BATCH(batch);
1140     }
1141 }
1142
1143 static int
1144 gen75_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
1145 {
1146     int out_slice_data_bit_offset;
1147     int slice_header_size = in_slice_data_bit_offset / 8;
1148     int i, j;
1149
1150     for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1151         if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
1152             i++, j += 2;
1153         }
1154     }
1155
1156     out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1157
1158     if (mode_flag == ENTROPY_CABAC)
1159         out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
1160
1161     return out_slice_data_bit_offset;
1162 }
1163
1164 static void
1165 gen75_mfd_avc_bsd_object(VADriverContextP ctx,
1166                         VAPictureParameterBufferH264 *pic_param,
1167                         VASliceParameterBufferH264 *slice_param,
1168                         dri_bo *slice_data_bo,
1169                         VASliceParameterBufferH264 *next_slice_param,
1170                         struct gen7_mfd_context *gen7_mfd_context)
1171 {
1172     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1173     int slice_data_bit_offset;
1174     uint8_t *slice_data = NULL;
1175
1176     dri_bo_map(slice_data_bo, 0);
1177     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1178     slice_data_bit_offset = gen75_mfd_avc_get_slice_bit_offset(slice_data,
1179                                                               pic_param->pic_fields.bits.entropy_coding_mode_flag,
1180                                                               slice_param->slice_data_bit_offset);
1181     dri_bo_unmap(slice_data_bo);
1182
1183     /* the input bitsteam format on GEN7 differs from GEN6 */
1184     BEGIN_BCS_BATCH(batch, 6);
1185     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
1186     OUT_BCS_BATCH(batch,
1187                   (slice_param->slice_data_size));
1188     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
1189     OUT_BCS_BATCH(batch,
1190                   (0 << 31) |
1191                   (0 << 14) |
1192                   (0 << 12) |
1193                   (0 << 10) |
1194                   (0 << 8));
1195     OUT_BCS_BATCH(batch,
1196                   ((slice_data_bit_offset >> 3) << 16) |
1197                   (0 << 5)  |
1198                   (0 << 4)  |
1199                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
1200                   (slice_data_bit_offset & 0x7));
1201     OUT_BCS_BATCH(batch, 0);
1202     ADVANCE_BCS_BATCH(batch);
1203 }
1204
1205 static inline void
1206 gen75_mfd_avc_context_init(
1207     VADriverContextP         ctx,
1208     struct gen7_mfd_context *gen7_mfd_context
1209 )
1210 {
1211     /* Initialize flat scaling lists */
1212     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
1213 }
1214
1215 static void
1216 gen75_mfd_avc_decode_init(VADriverContextP ctx,
1217                          struct decode_state *decode_state,
1218                          struct gen7_mfd_context *gen7_mfd_context)
1219 {
1220     VAPictureParameterBufferH264 *pic_param;
1221     VASliceParameterBufferH264 *slice_param;
1222     VAPictureH264 *va_pic;
1223     struct i965_driver_data *i965 = i965_driver_data(ctx);
1224     struct object_surface *obj_surface;
1225     dri_bo *bo;
1226     int i, j, enable_avc_ildb = 0;
1227     unsigned int width_in_mbs, height_in_mbs;
1228
1229     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
1230         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1231         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1232
1233         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1234             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1235             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1236                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1237                    (slice_param->slice_type == SLICE_TYPE_P) ||
1238                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1239                    (slice_param->slice_type == SLICE_TYPE_B));
1240
1241             if (slice_param->disable_deblocking_filter_idc != 1) {
1242                 enable_avc_ildb = 1;
1243                 break;
1244             }
1245
1246             slice_param++;
1247         }
1248     }
1249
1250     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1251     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1252     gen75_mfd_avc_frame_store_index(ctx, pic_param, gen7_mfd_context);
1253     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1254     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1255     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
1256     assert(height_in_mbs > 0 && height_in_mbs <= 256);
1257
1258     /* Current decoded picture */
1259     va_pic = &pic_param->CurrPic;
1260     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
1261     obj_surface = SURFACE(va_pic->picture_id);
1262     assert(obj_surface);
1263     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
1264     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
1265     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1266     gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface);
1267
1268     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1269     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1270     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1271     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
1272
1273     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1274     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1275     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1276     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
1277
1278     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1279     bo = dri_bo_alloc(i965->intel.bufmgr,
1280                       "intra row store",
1281                       width_in_mbs * 64,
1282                       0x1000);
1283     assert(bo);
1284     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1285     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1286
1287     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1288     bo = dri_bo_alloc(i965->intel.bufmgr,
1289                       "deblocking filter row store",
1290                       width_in_mbs * 64 * 4,
1291                       0x1000);
1292     assert(bo);
1293     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1294     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1295
1296     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1297     bo = dri_bo_alloc(i965->intel.bufmgr,
1298                       "bsd mpc row store",
1299                       width_in_mbs * 64 * 2,
1300                       0x1000);
1301     assert(bo);
1302     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1303     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1304
1305     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
1306     bo = dri_bo_alloc(i965->intel.bufmgr,
1307                       "mpr row store",
1308                       width_in_mbs * 64 * 2,
1309                       0x1000);
1310     assert(bo);
1311     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
1312     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1313
1314     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1315 }
1316
1317 static void
1318 gen75_mfd_avc_decode_picture(VADriverContextP ctx,
1319                             struct decode_state *decode_state,
1320                             struct gen7_mfd_context *gen7_mfd_context)
1321 {
1322     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1323     VAPictureParameterBufferH264 *pic_param;
1324     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1325     dri_bo *slice_data_bo;
1326     int i, j;
1327
1328     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1329     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1330     gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
1331
1332     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1333     intel_batchbuffer_emit_mi_flush(batch);
1334     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1335     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1336     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1337     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1338     gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
1339     gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1340     gen75_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context);
1341
1342     for (j = 0; j < decode_state->num_slice_params; j++) {
1343         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1344         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1345         slice_data_bo = decode_state->slice_datas[j]->bo;
1346         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1347
1348         if (j == decode_state->num_slice_params - 1)
1349             next_slice_group_param = NULL;
1350         else
1351             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1352
1353         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1354             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1355             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1356                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1357                    (slice_param->slice_type == SLICE_TYPE_P) ||
1358                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1359                    (slice_param->slice_type == SLICE_TYPE_B));
1360
1361             if (i < decode_state->slice_params[j]->num_elements - 1)
1362                 next_slice_param = slice_param + 1;
1363             else
1364                 next_slice_param = next_slice_group_param;
1365
1366             gen75_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen7_mfd_context);
1367             gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1368             gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1369             gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1370             gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1371             slice_param++;
1372         }
1373     }
1374
1375     intel_batchbuffer_end_atomic(batch);
1376     intel_batchbuffer_flush(batch);
1377 }
1378
1379 static void
1380 gen75_mfd_mpeg2_decode_init(VADriverContextP ctx,
1381                            struct decode_state *decode_state,
1382                            struct gen7_mfd_context *gen7_mfd_context)
1383 {
1384     VAPictureParameterBufferMPEG2 *pic_param;
1385     struct i965_driver_data *i965 = i965_driver_data(ctx);
1386     struct object_surface *obj_surface;
1387     dri_bo *bo;
1388     unsigned int width_in_mbs;
1389
1390     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1391     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1392     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1393
1394     mpeg2_set_reference_surfaces(
1395         ctx,
1396         gen7_mfd_context->reference_surface,
1397         decode_state,
1398         pic_param
1399     );
1400
1401     /* Current decoded picture */
1402     obj_surface = SURFACE(decode_state->current_render_target);
1403     assert(obj_surface);
1404     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1405
1406     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1407     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1408     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1409     gen7_mfd_context->pre_deblocking_output.valid = 1;
1410
1411     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1412     bo = dri_bo_alloc(i965->intel.bufmgr,
1413                       "bsd mpc row store",
1414                       width_in_mbs * 96,
1415                       0x1000);
1416     assert(bo);
1417     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1418     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1419
1420     gen7_mfd_context->post_deblocking_output.valid = 0;
1421     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1422     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1423     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1424     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1425 }
1426
1427 static void
1428 gen75_mfd_mpeg2_pic_state(VADriverContextP ctx,
1429                          struct decode_state *decode_state,
1430                          struct gen7_mfd_context *gen7_mfd_context)
1431 {
1432     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1433     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1434     VAPictureParameterBufferMPEG2 *pic_param;
1435     unsigned int slice_concealment_disable_bit = 0;
1436
1437     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1438     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1439
1440     slice_concealment_disable_bit = 1;
1441
1442     BEGIN_BCS_BATCH(batch, 13);
1443     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1444     OUT_BCS_BATCH(batch,
1445                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1446                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1447                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1448                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1449                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1450                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1451                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
1452                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1453                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1454                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1455                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1456                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1457     OUT_BCS_BATCH(batch,
1458                   pic_param->picture_coding_type << 9);
1459     OUT_BCS_BATCH(batch,
1460                   (slice_concealment_disable_bit << 31) |
1461                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1462                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1463     OUT_BCS_BATCH(batch, 0);
1464     OUT_BCS_BATCH(batch, 0);
1465     OUT_BCS_BATCH(batch, 0);
1466     OUT_BCS_BATCH(batch, 0);
1467     OUT_BCS_BATCH(batch, 0);
1468     OUT_BCS_BATCH(batch, 0);
1469     OUT_BCS_BATCH(batch, 0);
1470     OUT_BCS_BATCH(batch, 0);
1471     OUT_BCS_BATCH(batch, 0);
1472     ADVANCE_BCS_BATCH(batch);
1473 }
1474
1475 static void
1476 gen75_mfd_mpeg2_qm_state(VADriverContextP ctx,
1477                         struct decode_state *decode_state,
1478                         struct gen7_mfd_context *gen7_mfd_context)
1479 {
1480     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1481     int i, j;
1482
1483     /* Update internal QM state */
1484     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1485         VAIQMatrixBufferMPEG2 * const iq_matrix =
1486             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1487
1488         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1489             iq_matrix->load_intra_quantiser_matrix) {
1490             gen_iq_matrix->load_intra_quantiser_matrix =
1491                 iq_matrix->load_intra_quantiser_matrix;
1492             if (iq_matrix->load_intra_quantiser_matrix) {
1493                 for (j = 0; j < 64; j++)
1494                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1495                         iq_matrix->intra_quantiser_matrix[j];
1496             }
1497         }
1498
1499         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1500             iq_matrix->load_non_intra_quantiser_matrix) {
1501             gen_iq_matrix->load_non_intra_quantiser_matrix =
1502                 iq_matrix->load_non_intra_quantiser_matrix;
1503             if (iq_matrix->load_non_intra_quantiser_matrix) {
1504                 for (j = 0; j < 64; j++)
1505                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1506                         iq_matrix->non_intra_quantiser_matrix[j];
1507             }
1508         }
1509     }
1510
1511     /* Commit QM state to HW */
1512     for (i = 0; i < 2; i++) {
1513         unsigned char *qm = NULL;
1514         int qm_type;
1515
1516         if (i == 0) {
1517             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1518                 qm = gen_iq_matrix->intra_quantiser_matrix;
1519                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1520             }
1521         } else {
1522             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1523                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1524                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1525             }
1526         }
1527
1528         if (!qm)
1529             continue;
1530
1531         gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1532     }
1533 }
1534
1535 static void
1536 gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1537                           VAPictureParameterBufferMPEG2 *pic_param,
1538                           VASliceParameterBufferMPEG2 *slice_param,
1539                           VASliceParameterBufferMPEG2 *next_slice_param,
1540                           struct gen7_mfd_context *gen7_mfd_context)
1541 {
1542     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1543     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1544     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1545     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1546
1547     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1548         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1549         is_field_pic = 1;
1550     is_field_pic_wa = is_field_pic &&
1551         gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1552
1553     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1554     hpos0 = slice_param->slice_horizontal_position;
1555
1556     if (next_slice_param == NULL) {
1557         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1558         hpos1 = 0;
1559     } else {
1560         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1561         hpos1 = next_slice_param->slice_horizontal_position;
1562     }
1563
1564     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1565
1566     BEGIN_BCS_BATCH(batch, 5);
1567     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1568     OUT_BCS_BATCH(batch,
1569                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1570     OUT_BCS_BATCH(batch,
1571                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1572     OUT_BCS_BATCH(batch,
1573                   hpos0 << 24 |
1574                   vpos0 << 16 |
1575                   mb_count << 8 |
1576                   (next_slice_param == NULL) << 5 |
1577                   (next_slice_param == NULL) << 3 |
1578                   (slice_param->macroblock_offset & 0x7));
1579     OUT_BCS_BATCH(batch,
1580                   (slice_param->quantiser_scale_code << 24) |
1581                   (vpos1 << 8 | hpos1));
1582     ADVANCE_BCS_BATCH(batch);
1583 }
1584
1585 static void
1586 gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1587                               struct decode_state *decode_state,
1588                               struct gen7_mfd_context *gen7_mfd_context)
1589 {
1590     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1591     VAPictureParameterBufferMPEG2 *pic_param;
1592     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1593     dri_bo *slice_data_bo;
1594     int i, j;
1595
1596     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1597     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1598
1599     gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1600     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1601     intel_batchbuffer_emit_mi_flush(batch);
1602     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1603     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1604     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1605     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1606     gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1607     gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1608
1609     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1610         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1611             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1612
1613     for (j = 0; j < decode_state->num_slice_params; j++) {
1614         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1615         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1616         slice_data_bo = decode_state->slice_datas[j]->bo;
1617         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1618
1619         if (j == decode_state->num_slice_params - 1)
1620             next_slice_group_param = NULL;
1621         else
1622             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1623
1624         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1625             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1626
1627             if (i < decode_state->slice_params[j]->num_elements - 1)
1628                 next_slice_param = slice_param + 1;
1629             else
1630                 next_slice_param = next_slice_group_param;
1631
1632             gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1633             slice_param++;
1634         }
1635     }
1636
1637     intel_batchbuffer_end_atomic(batch);
1638     intel_batchbuffer_flush(batch);
1639 }
1640
1641 static const int va_to_gen7_vc1_pic_type[5] = {
1642     GEN7_VC1_I_PICTURE,
1643     GEN7_VC1_P_PICTURE,
1644     GEN7_VC1_B_PICTURE,
1645     GEN7_VC1_BI_PICTURE,
1646     GEN7_VC1_P_PICTURE,
1647 };
1648
1649 static const int va_to_gen7_vc1_mv[4] = {
1650     1, /* 1-MV */
1651     2, /* 1-MV half-pel */
1652     3, /* 1-MV half-pef bilinear */
1653     0, /* Mixed MV */
1654 };
1655
1656 static const int b_picture_scale_factor[21] = {
1657     128, 85,  170, 64,  192,
1658     51,  102, 153, 204, 43,
1659     215, 37,  74,  111, 148,
1660     185, 222, 32,  96,  160,
1661     224,
1662 };
1663
1664 static const int va_to_gen7_vc1_condover[3] = {
1665     0,
1666     2,
1667     3
1668 };
1669
1670 static const int va_to_gen7_vc1_profile[4] = {
1671     GEN7_VC1_SIMPLE_PROFILE,
1672     GEN7_VC1_MAIN_PROFILE,
1673     GEN7_VC1_RESERVED_PROFILE,
1674     GEN7_VC1_ADVANCED_PROFILE
1675 };
1676
1677 static void
1678 gen75_mfd_free_vc1_surface(void **data)
1679 {
1680     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1681
1682     if (!gen7_vc1_surface)
1683         return;
1684
1685     dri_bo_unreference(gen7_vc1_surface->dmv);
1686     free(gen7_vc1_surface);
1687     *data = NULL;
1688 }
1689
1690 static void
1691 gen75_mfd_init_vc1_surface(VADriverContextP ctx,
1692                           VAPictureParameterBufferVC1 *pic_param,
1693                           struct object_surface *obj_surface)
1694 {
1695     struct i965_driver_data *i965 = i965_driver_data(ctx);
1696     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1697     int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1698     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1699
1700     obj_surface->free_private_data = gen75_mfd_free_vc1_surface;
1701
1702     if (!gen7_vc1_surface) {
1703         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1704         assert((obj_surface->size & 0x3f) == 0);
1705         obj_surface->private_data = gen7_vc1_surface;
1706     }
1707
1708     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1709
1710     if (gen7_vc1_surface->dmv == NULL) {
1711         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1712                                              "direct mv w/r buffer",
1713                                              width_in_mbs * height_in_mbs * 64,
1714                                              0x1000);
1715     }
1716 }
1717
1718 static void
1719 gen75_mfd_vc1_decode_init(VADriverContextP ctx,
1720                          struct decode_state *decode_state,
1721                          struct gen7_mfd_context *gen7_mfd_context)
1722 {
1723     VAPictureParameterBufferVC1 *pic_param;
1724     struct i965_driver_data *i965 = i965_driver_data(ctx);
1725     struct object_surface *obj_surface;
1726     int i;
1727     dri_bo *bo;
1728     int width_in_mbs;
1729
1730     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1731     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1732     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1733
1734     /* reference picture */
1735     obj_surface = SURFACE(pic_param->forward_reference_picture);
1736
1737     if (obj_surface && obj_surface->bo)
1738         gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1739     else
1740         gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1741
1742     obj_surface = SURFACE(pic_param->backward_reference_picture);
1743
1744     if (obj_surface && obj_surface->bo)
1745         gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1746     else
1747         gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1748
1749     /* must do so !!! */
1750     for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1751         gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1752
1753     /* Current decoded picture */
1754     obj_surface = SURFACE(decode_state->current_render_target);
1755     assert(obj_surface);
1756     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1757     gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1758
1759     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1760     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1761     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1762     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1763
1764     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1765     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1766     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1767     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1768
1769     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1770     bo = dri_bo_alloc(i965->intel.bufmgr,
1771                       "intra row store",
1772                       width_in_mbs * 64,
1773                       0x1000);
1774     assert(bo);
1775     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1776     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1777
1778     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1779     bo = dri_bo_alloc(i965->intel.bufmgr,
1780                       "deblocking filter row store",
1781                       width_in_mbs * 6 * 64,
1782                       0x1000);
1783     assert(bo);
1784     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1785     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1786
1787     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1788     bo = dri_bo_alloc(i965->intel.bufmgr,
1789                       "bsd mpc row store",
1790                       width_in_mbs * 96,
1791                       0x1000);
1792     assert(bo);
1793     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1794     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1795
1796     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1797
1798     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1799     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1800
1801     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1802         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1803         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1804         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1805         int src_w, src_h;
1806         uint8_t *src = NULL, *dst = NULL;
1807
1808         assert(decode_state->bit_plane->buffer);
1809         src = decode_state->bit_plane->buffer;
1810
1811         bo = dri_bo_alloc(i965->intel.bufmgr,
1812                           "VC-1 Bitplane",
1813                           bitplane_width * bitplane_width,
1814                           0x1000);
1815         assert(bo);
1816         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1817
1818         dri_bo_map(bo, True);
1819         assert(bo->virtual);
1820         dst = bo->virtual;
1821
1822         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1823             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1824                 int src_index, dst_index;
1825                 int src_shift;
1826                 uint8_t src_value;
1827
1828                 src_index = (src_h * width_in_mbs + src_w) / 2;
1829                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1830                 src_value = ((src[src_index] >> src_shift) & 0xf);
1831
1832                 dst_index = src_w / 2;
1833                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1834             }
1835
1836             if (src_w & 1)
1837                 dst[src_w / 2] >>= 4;
1838
1839             dst += bitplane_width;
1840         }
1841
1842         dri_bo_unmap(bo);
1843     } else
1844         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1845 }
1846
1847 static void
1848 gen75_mfd_vc1_pic_state(VADriverContextP ctx,
1849                        struct decode_state *decode_state,
1850                        struct gen7_mfd_context *gen7_mfd_context)
1851 {
1852     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1853     VAPictureParameterBufferVC1 *pic_param;
1854     struct i965_driver_data *i965 = i965_driver_data(ctx);
1855     struct object_surface *obj_surface;
1856     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1857     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1858     int unified_mv_mode;
1859     int ref_field_pic_polarity = 0;
1860     int scale_factor = 0;
1861     int trans_ac_y = 0;
1862     int dmv_surface_valid = 0;
1863     int brfd = 0;
1864     int fcm = 0;
1865     int picture_type;
1866     int profile;
1867     int overlap;
1868     int interpolation_mode = 0;
1869
1870     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1871     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1872
1873     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1874     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1875     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1876     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1877     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1878     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1879     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1880     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1881
1882     if (dquant == 0) {
1883         alt_pquant_config = 0;
1884         alt_pquant_edge_mask = 0;
1885     } else if (dquant == 2) {
1886         alt_pquant_config = 1;
1887         alt_pquant_edge_mask = 0xf;
1888     } else {
1889         assert(dquant == 1);
1890         if (dquantfrm == 0) {
1891             alt_pquant_config = 0;
1892             alt_pquant_edge_mask = 0;
1893             alt_pq = 0;
1894         } else {
1895             assert(dquantfrm == 1);
1896             alt_pquant_config = 1;
1897
1898             switch (dqprofile) {
1899             case 3:
1900                 if (dqbilevel == 0) {
1901                     alt_pquant_config = 2;
1902                     alt_pquant_edge_mask = 0;
1903                 } else {
1904                     assert(dqbilevel == 1);
1905                     alt_pquant_config = 3;
1906                     alt_pquant_edge_mask = 0;
1907                 }
1908                 break;
1909
1910             case 0:
1911                 alt_pquant_edge_mask = 0xf;
1912                 break;
1913
1914             case 1:
1915                 if (dqdbedge == 3)
1916                     alt_pquant_edge_mask = 0x9;
1917                 else
1918                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1919
1920                 break;
1921
1922             case 2:
1923                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1924                 break;
1925
1926             default:
1927                 assert(0);
1928             }
1929         }
1930     }
1931
1932     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1933         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1934         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1935     } else {
1936         assert(pic_param->mv_fields.bits.mv_mode < 4);
1937         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1938     }
1939
1940     if (pic_param->sequence_fields.bits.interlace == 1 &&
1941         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1942         /* FIXME: calculate reference field picture polarity */
1943         assert(0);
1944         ref_field_pic_polarity = 0;
1945     }
1946
1947     if (pic_param->b_picture_fraction < 21)
1948         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1949
1950     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1951
1952     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1953         picture_type == GEN7_VC1_I_PICTURE)
1954         picture_type = GEN7_VC1_BI_PICTURE;
1955
1956     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1957         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1958     else
1959         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1960
1961
1962     if (picture_type == GEN7_VC1_B_PICTURE) {
1963         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1964
1965         obj_surface = SURFACE(pic_param->backward_reference_picture);
1966         assert(obj_surface);
1967         gen7_vc1_surface = obj_surface->private_data;
1968
1969         if (!gen7_vc1_surface ||
1970             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1971              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1972             dmv_surface_valid = 0;
1973         else
1974             dmv_surface_valid = 1;
1975     }
1976
1977     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1978
1979     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1980         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1981     else {
1982         if (pic_param->picture_fields.bits.top_field_first)
1983             fcm = 2;
1984         else
1985             fcm = 3;
1986     }
1987
1988     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1989         brfd = pic_param->reference_fields.bits.reference_distance;
1990         brfd = (scale_factor * brfd) >> 8;
1991         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1992
1993         if (brfd < 0)
1994             brfd = 0;
1995     }
1996
1997     overlap = pic_param->sequence_fields.bits.overlap;
1998     if (profile != GEN7_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
1999         overlap = 0;
2000
2001     assert(pic_param->conditional_overlap_flag < 3);
2002     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
2003
2004     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
2005         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2006          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
2007         interpolation_mode = 9; /* Half-pel bilinear */
2008     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
2009              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2010               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
2011         interpolation_mode = 1; /* Half-pel bicubic */
2012     else
2013         interpolation_mode = 0; /* Quarter-pel bicubic */
2014
2015     BEGIN_BCS_BATCH(batch, 6);
2016     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
2017     OUT_BCS_BATCH(batch,
2018                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
2019                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
2020     OUT_BCS_BATCH(batch,
2021                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
2022                   dmv_surface_valid << 15 |
2023                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
2024                   pic_param->rounding_control << 13 |
2025                   pic_param->sequence_fields.bits.syncmarker << 12 |
2026                   interpolation_mode << 8 |
2027                   0 << 7 | /* FIXME: scale up or down ??? */
2028                   pic_param->range_reduction_frame << 6 |
2029                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
2030                   overlap << 4 |
2031                   !pic_param->picture_fields.bits.is_first_field << 3 |
2032                   (pic_param->sequence_fields.bits.profile == 3) << 0);
2033     OUT_BCS_BATCH(batch,
2034                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
2035                   picture_type << 26 |
2036                   fcm << 24 |
2037                   alt_pq << 16 |
2038                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
2039                   scale_factor << 0);
2040     OUT_BCS_BATCH(batch,
2041                   unified_mv_mode << 28 |
2042                   pic_param->mv_fields.bits.four_mv_switch << 27 |
2043                   pic_param->fast_uvmc_flag << 26 |
2044                   ref_field_pic_polarity << 25 |
2045                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
2046                   pic_param->reference_fields.bits.reference_distance << 20 |
2047                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
2048                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
2049                   pic_param->mv_fields.bits.extended_mv_range << 8 |
2050                   alt_pquant_edge_mask << 4 |
2051                   alt_pquant_config << 2 |
2052                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
2053                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
2054     OUT_BCS_BATCH(batch,
2055                   !!pic_param->bitplane_present.value << 31 |
2056                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
2057                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
2058                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
2059                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
2060                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
2061                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
2062                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
2063                   pic_param->mv_fields.bits.mv_table << 20 |
2064                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
2065                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
2066                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
2067                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
2068                   pic_param->mb_mode_table << 8 |
2069                   trans_ac_y << 6 |
2070                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
2071                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
2072                   pic_param->cbp_table << 0);
2073     ADVANCE_BCS_BATCH(batch);
2074 }
2075
2076 static void
2077 gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
2078                              struct decode_state *decode_state,
2079                              struct gen7_mfd_context *gen7_mfd_context)
2080 {
2081     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2082     VAPictureParameterBufferVC1 *pic_param;
2083     int intensitycomp_single;
2084
2085     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2086     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2087
2088     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2089     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2090     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
2091
2092     BEGIN_BCS_BATCH(batch, 6);
2093     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
2094     OUT_BCS_BATCH(batch,
2095                   0 << 14 | /* FIXME: double ??? */
2096                   0 << 12 |
2097                   intensitycomp_single << 10 |
2098                   intensitycomp_single << 8 |
2099                   0 << 4 | /* FIXME: interlace mode */
2100                   0);
2101     OUT_BCS_BATCH(batch,
2102                   pic_param->luma_shift << 16 |
2103                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
2104     OUT_BCS_BATCH(batch, 0);
2105     OUT_BCS_BATCH(batch, 0);
2106     OUT_BCS_BATCH(batch, 0);
2107     ADVANCE_BCS_BATCH(batch);
2108 }
2109
2110 static void
2111 gen75_mfd_vc1_directmode_state_bplus(VADriverContextP ctx,
2112                               struct decode_state *decode_state,
2113                               struct gen7_mfd_context *gen7_mfd_context)
2114 {
2115     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2116     VAPictureParameterBufferVC1 *pic_param;
2117     struct i965_driver_data *i965 = i965_driver_data(ctx);
2118     struct object_surface *obj_surface;
2119     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2120
2121     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2122     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2123
2124     obj_surface = SURFACE(decode_state->current_render_target);
2125
2126     if (obj_surface && obj_surface->private_data) {
2127         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2128     }
2129
2130     obj_surface = SURFACE(pic_param->backward_reference_picture);
2131
2132     if (obj_surface && obj_surface->private_data) {
2133         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2134     }
2135
2136     BEGIN_BCS_BATCH(batch, 7);
2137     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2));
2138
2139     if (dmv_write_buffer)
2140         OUT_BCS_RELOC(batch, dmv_write_buffer,
2141                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2142                       0);
2143     else
2144         OUT_BCS_BATCH(batch, 0);
2145
2146         OUT_BCS_BATCH(batch, 0);
2147         OUT_BCS_BATCH(batch, 0);
2148
2149     if (dmv_read_buffer)
2150         OUT_BCS_RELOC(batch, dmv_read_buffer,
2151                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2152                       0);
2153     else
2154         OUT_BCS_BATCH(batch, 0);
2155         OUT_BCS_BATCH(batch, 0);
2156         OUT_BCS_BATCH(batch, 0);
2157
2158     ADVANCE_BCS_BATCH(batch);
2159 }
2160
2161 static void
2162 gen75_mfd_vc1_directmode_state(VADriverContextP ctx,
2163                               struct decode_state *decode_state,
2164                               struct gen7_mfd_context *gen7_mfd_context)
2165 {
2166     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2167     VAPictureParameterBufferVC1 *pic_param;
2168     struct i965_driver_data *i965 = i965_driver_data(ctx);
2169     struct object_surface *obj_surface;
2170     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2171
2172     if (IS_STEPPING_BPLUS(i965)) {
2173         gen75_mfd_vc1_directmode_state_bplus(ctx, decode_state, gen7_mfd_context);
2174         return;
2175     }
2176     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2177     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2178
2179     obj_surface = SURFACE(decode_state->current_render_target);
2180
2181     if (obj_surface && obj_surface->private_data) {
2182         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2183     }
2184
2185     obj_surface = SURFACE(pic_param->backward_reference_picture);
2186
2187     if (obj_surface && obj_surface->private_data) {
2188         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2189     }
2190
2191     BEGIN_BCS_BATCH(batch, 3);
2192     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
2193
2194     if (dmv_write_buffer)
2195         OUT_BCS_RELOC(batch, dmv_write_buffer,
2196                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2197                       0);
2198     else
2199         OUT_BCS_BATCH(batch, 0);
2200
2201     if (dmv_read_buffer)
2202         OUT_BCS_RELOC(batch, dmv_read_buffer,
2203                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2204                       0);
2205     else
2206         OUT_BCS_BATCH(batch, 0);
2207
2208     ADVANCE_BCS_BATCH(batch);
2209 }
2210
2211 static int
2212 gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
2213 {
2214     int out_slice_data_bit_offset;
2215     int slice_header_size = in_slice_data_bit_offset / 8;
2216     int i, j;
2217
2218     if (profile != 3)
2219         out_slice_data_bit_offset = in_slice_data_bit_offset;
2220     else {
2221         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
2222             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
2223                 i++, j += 2;
2224             }
2225         }
2226
2227         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
2228     }
2229
2230     return out_slice_data_bit_offset;
2231 }
2232
2233 static void
2234 gen75_mfd_vc1_bsd_object(VADriverContextP ctx,
2235                         VAPictureParameterBufferVC1 *pic_param,
2236                         VASliceParameterBufferVC1 *slice_param,
2237                         VASliceParameterBufferVC1 *next_slice_param,
2238                         dri_bo *slice_data_bo,
2239                         struct gen7_mfd_context *gen7_mfd_context)
2240 {
2241     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2242     int next_slice_start_vert_pos;
2243     int macroblock_offset;
2244     uint8_t *slice_data = NULL;
2245
2246     dri_bo_map(slice_data_bo, 0);
2247     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
2248     macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data,
2249                                                                slice_param->macroblock_offset,
2250                                                                pic_param->sequence_fields.bits.profile);
2251     dri_bo_unmap(slice_data_bo);
2252
2253     if (next_slice_param)
2254         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
2255     else
2256         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
2257
2258     BEGIN_BCS_BATCH(batch, 5);
2259     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
2260     OUT_BCS_BATCH(batch,
2261                   slice_param->slice_data_size - (macroblock_offset >> 3));
2262     OUT_BCS_BATCH(batch,
2263                   slice_param->slice_data_offset + (macroblock_offset >> 3));
2264     OUT_BCS_BATCH(batch,
2265                   slice_param->slice_vertical_position << 16 |
2266                   next_slice_start_vert_pos << 0);
2267     OUT_BCS_BATCH(batch,
2268                   (macroblock_offset & 0x7));
2269     ADVANCE_BCS_BATCH(batch);
2270 }
2271
2272 static void
2273 gen75_mfd_vc1_decode_picture(VADriverContextP ctx,
2274                             struct decode_state *decode_state,
2275                             struct gen7_mfd_context *gen7_mfd_context)
2276 {
2277     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2278     VAPictureParameterBufferVC1 *pic_param;
2279     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2280     dri_bo *slice_data_bo;
2281     int i, j;
2282
2283     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2284     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2285
2286     gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2287     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2288     intel_batchbuffer_emit_mi_flush(batch);
2289     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2290     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2291     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2292     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2293     gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2294     gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2295     gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2296
2297     for (j = 0; j < decode_state->num_slice_params; j++) {
2298         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2299         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2300         slice_data_bo = decode_state->slice_datas[j]->bo;
2301         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2302
2303         if (j == decode_state->num_slice_params - 1)
2304             next_slice_group_param = NULL;
2305         else
2306             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2307
2308         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2309             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2310
2311             if (i < decode_state->slice_params[j]->num_elements - 1)
2312                 next_slice_param = slice_param + 1;
2313             else
2314                 next_slice_param = next_slice_group_param;
2315
2316             gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2317             slice_param++;
2318         }
2319     }
2320
2321     intel_batchbuffer_end_atomic(batch);
2322     intel_batchbuffer_flush(batch);
2323 }
2324
2325 static void
2326 gen75_mfd_jpeg_decode_init(VADriverContextP ctx,
2327                           struct decode_state *decode_state,
2328                           struct gen7_mfd_context *gen7_mfd_context)
2329 {
2330     struct i965_driver_data *i965 = i965_driver_data(ctx);
2331     struct object_surface *obj_surface;
2332     VAPictureParameterBufferJPEGBaseline *pic_param;
2333     int subsampling = SUBSAMPLE_YUV420;
2334
2335     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2336
2337     if (pic_param->num_components == 1)
2338         subsampling = SUBSAMPLE_YUV400;
2339     else if (pic_param->num_components == 3) {
2340         int h1 = pic_param->components[0].h_sampling_factor;
2341         int h2 = pic_param->components[1].h_sampling_factor;
2342         int h3 = pic_param->components[2].h_sampling_factor;
2343         int v1 = pic_param->components[0].v_sampling_factor;
2344         int v2 = pic_param->components[1].v_sampling_factor;
2345         int v3 = pic_param->components[2].v_sampling_factor;
2346
2347         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2348             v1 == 2 && v2 == 1 && v3 == 1)
2349             subsampling = SUBSAMPLE_YUV420;
2350         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2351                  v1 == 1 && v2 == 1 && v3 == 1)
2352             subsampling = SUBSAMPLE_YUV422H;
2353         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2354                  v1 == 1 && v2 == 1 && v3 == 1)
2355             subsampling = SUBSAMPLE_YUV444;
2356         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2357                  v1 == 1 && v2 == 1 && v3 == 1)
2358             subsampling = SUBSAMPLE_YUV411;
2359         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2360                  v1 == 2 && v2 == 1 && v3 == 1)
2361             subsampling = SUBSAMPLE_YUV422V;
2362         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2363                  v1 == 2 && v2 == 2 && v3 == 2)
2364             subsampling = SUBSAMPLE_YUV422H;
2365         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2366                  v1 == 2 && v2 == 1 && v3 == 1)
2367             subsampling = SUBSAMPLE_YUV422V;
2368         else
2369             assert(0);
2370     } else {
2371         assert(0);
2372     }
2373
2374     /* Current decoded picture */
2375     obj_surface = SURFACE(decode_state->current_render_target);
2376     assert(obj_surface);
2377     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('I','M','C','1'), subsampling);
2378
2379     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2380     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2381     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2382     gen7_mfd_context->pre_deblocking_output.valid = 1;
2383
2384     gen7_mfd_context->post_deblocking_output.bo = NULL;
2385     gen7_mfd_context->post_deblocking_output.valid = 0;
2386
2387     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2388     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2389
2390     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2391     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2392
2393     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2394     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2395
2396     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2397     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2398
2399     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2400     gen7_mfd_context->bitplane_read_buffer.valid = 0;
2401 }
2402
2403 static const int va_to_gen7_jpeg_rotation[4] = {
2404     GEN7_JPEG_ROTATION_0,
2405     GEN7_JPEG_ROTATION_90,
2406     GEN7_JPEG_ROTATION_180,
2407     GEN7_JPEG_ROTATION_270
2408 };
2409
2410 static void
2411 gen75_mfd_jpeg_pic_state(VADriverContextP ctx,
2412                         struct decode_state *decode_state,
2413                         struct gen7_mfd_context *gen7_mfd_context)
2414 {
2415     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2416     VAPictureParameterBufferJPEGBaseline *pic_param;
2417     int chroma_type = GEN7_YUV420;
2418     int frame_width_in_blks;
2419     int frame_height_in_blks;
2420
2421     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2422     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2423
2424     if (pic_param->num_components == 1)
2425         chroma_type = GEN7_YUV400;
2426     else if (pic_param->num_components == 3) {
2427         int h1 = pic_param->components[0].h_sampling_factor;
2428         int h2 = pic_param->components[1].h_sampling_factor;
2429         int h3 = pic_param->components[2].h_sampling_factor;
2430         int v1 = pic_param->components[0].v_sampling_factor;
2431         int v2 = pic_param->components[1].v_sampling_factor;
2432         int v3 = pic_param->components[2].v_sampling_factor;
2433
2434         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2435             v1 == 2 && v2 == 1 && v3 == 1)
2436             chroma_type = GEN7_YUV420;
2437         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2438                  v1 == 1 && v2 == 1 && v3 == 1)
2439             chroma_type = GEN7_YUV422H_2Y;
2440         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2441                  v1 == 1 && v2 == 1 && v3 == 1)
2442             chroma_type = GEN7_YUV444;
2443         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2444                  v1 == 1 && v2 == 1 && v3 == 1)
2445             chroma_type = GEN7_YUV411;
2446         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2447                  v1 == 2 && v2 == 1 && v3 == 1)
2448             chroma_type = GEN7_YUV422V_2Y;
2449         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2450                  v1 == 2 && v2 == 2 && v3 == 2)
2451             chroma_type = GEN7_YUV422H_4Y;
2452         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2453                  v1 == 2 && v2 == 1 && v3 == 1)
2454             chroma_type = GEN7_YUV422V_4Y;
2455         else
2456             assert(0);
2457     }
2458
2459     if (chroma_type == GEN7_YUV400 ||
2460         chroma_type == GEN7_YUV444 ||
2461         chroma_type == GEN7_YUV422V_2Y) {
2462         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2463         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2464     } else if (chroma_type == GEN7_YUV411) {
2465         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2466         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2467     } else {
2468         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2469         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2470     }
2471
2472     BEGIN_BCS_BATCH(batch, 3);
2473     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2474     OUT_BCS_BATCH(batch,
2475                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2476                   (chroma_type << 0));
2477     OUT_BCS_BATCH(batch,
2478                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2479                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2480     ADVANCE_BCS_BATCH(batch);
2481 }
2482
2483 static const int va_to_gen7_jpeg_hufftable[2] = {
2484     MFX_HUFFTABLE_ID_Y,
2485     MFX_HUFFTABLE_ID_UV
2486 };
2487
2488 static void
2489 gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2490                                struct decode_state *decode_state,
2491                                struct gen7_mfd_context *gen7_mfd_context,
2492                                int num_tables)
2493 {
2494     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2495     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2496     int index;
2497
2498     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2499         return;
2500
2501     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2502
2503     for (index = 0; index < num_tables; index++) {
2504         int id = va_to_gen7_jpeg_hufftable[index];
2505         if (!huffman_table->load_huffman_table[index])
2506             continue;
2507         BEGIN_BCS_BATCH(batch, 53);
2508         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2509         OUT_BCS_BATCH(batch, id);
2510         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2511         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2512         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2513         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2514         ADVANCE_BCS_BATCH(batch);
2515     }
2516 }
2517
2518 static const int va_to_gen7_jpeg_qm[5] = {
2519     -1,
2520     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2521     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2522     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2523     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2524 };
2525
2526 static void
2527 gen75_mfd_jpeg_qm_state(VADriverContextP ctx,
2528                        struct decode_state *decode_state,
2529                        struct gen7_mfd_context *gen7_mfd_context)
2530 {
2531     VAPictureParameterBufferJPEGBaseline *pic_param;
2532     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2533     int index;
2534
2535     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2536         return;
2537
2538     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2539     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2540
2541     assert(pic_param->num_components <= 3);
2542
2543     for (index = 0; index < pic_param->num_components; index++) {
2544         int qm_type = va_to_gen7_jpeg_qm[pic_param->components[index].component_id - pic_param->components[0].component_id + 1];
2545         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2546         unsigned char raster_qm[64];
2547         int j;
2548
2549         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2550             continue;
2551
2552         for (j = 0; j < 64; j++)
2553             raster_qm[zigzag_direct[j]] = qm[j];
2554
2555         gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2556     }
2557 }
2558
2559 static void
2560 gen75_mfd_jpeg_bsd_object(VADriverContextP ctx,
2561                          VAPictureParameterBufferJPEGBaseline *pic_param,
2562                          VASliceParameterBufferJPEGBaseline *slice_param,
2563                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2564                          dri_bo *slice_data_bo,
2565                          struct gen7_mfd_context *gen7_mfd_context)
2566 {
2567     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2568     int scan_component_mask = 0;
2569     int i;
2570
2571     assert(slice_param->num_components > 0);
2572     assert(slice_param->num_components < 4);
2573     assert(slice_param->num_components <= pic_param->num_components);
2574
2575     for (i = 0; i < slice_param->num_components; i++) {
2576         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2577         case 1:
2578             scan_component_mask |= (1 << 0);
2579             break;
2580         case 2:
2581             scan_component_mask |= (1 << 1);
2582             break;
2583         case 3:
2584             scan_component_mask |= (1 << 2);
2585             break;
2586         default:
2587             assert(0);
2588             break;
2589         }
2590     }
2591
2592     BEGIN_BCS_BATCH(batch, 6);
2593     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2594     OUT_BCS_BATCH(batch,
2595                   slice_param->slice_data_size);
2596     OUT_BCS_BATCH(batch,
2597                   slice_param->slice_data_offset);
2598     OUT_BCS_BATCH(batch,
2599                   slice_param->slice_horizontal_position << 16 |
2600                   slice_param->slice_vertical_position << 0);
2601     OUT_BCS_BATCH(batch,
2602                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2603                   (scan_component_mask << 27) |                 /* scan components */
2604                   (0 << 26) |   /* disable interrupt allowed */
2605                   (slice_param->num_mcus << 0));                /* MCU count */
2606     OUT_BCS_BATCH(batch,
2607                   (slice_param->restart_interval << 0));    /* RestartInterval */
2608     ADVANCE_BCS_BATCH(batch);
2609 }
2610
2611 /* Workaround for JPEG decoding on Ivybridge */
2612
2613 VAStatus
2614 i965_DestroySurfaces(VADriverContextP ctx,
2615                      VASurfaceID *surface_list,
2616                      int num_surfaces);
2617 VAStatus
2618 i965_CreateSurfaces(VADriverContextP ctx,
2619                     int width,
2620                     int height,
2621                     int format,
2622                     int num_surfaces,
2623                     VASurfaceID *surfaces);
2624
2625 static struct {
2626     int width;
2627     int height;
2628     unsigned char data[32];
2629     int data_size;
2630     int data_bit_offset;
2631     int qp;
2632 } gen7_jpeg_wa_clip = {
2633     16,
2634     16,
2635     {
2636         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2637         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2638     },
2639     14,
2640     40,
2641     28,
2642 };
2643
2644 static void
2645 gen75_jpeg_wa_init(VADriverContextP ctx,
2646                   struct gen7_mfd_context *gen7_mfd_context)
2647 {
2648     struct i965_driver_data *i965 = i965_driver_data(ctx);
2649     VAStatus status;
2650     struct object_surface *obj_surface;
2651
2652     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2653         i965_DestroySurfaces(ctx,
2654                              &gen7_mfd_context->jpeg_wa_surface_id,
2655                              1);
2656
2657     status = i965_CreateSurfaces(ctx,
2658                                  gen7_jpeg_wa_clip.width,
2659                                  gen7_jpeg_wa_clip.height,
2660                                  VA_RT_FORMAT_YUV420,
2661                                  1,
2662                                  &gen7_mfd_context->jpeg_wa_surface_id);
2663     assert(status == VA_STATUS_SUCCESS);
2664
2665     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2666     assert(obj_surface);
2667     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
2668
2669     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2670         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2671                                                                "JPEG WA data",
2672                                                                0x1000,
2673                                                                0x1000);
2674         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2675                        0,
2676                        gen7_jpeg_wa_clip.data_size,
2677                        gen7_jpeg_wa_clip.data);
2678     }
2679 }
2680
2681 static void
2682 gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2683                               struct gen7_mfd_context *gen7_mfd_context)
2684 {
2685     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2686
2687     BEGIN_BCS_BATCH(batch, 5);
2688     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2689     OUT_BCS_BATCH(batch,
2690                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2691                   (MFD_MODE_VLD << 15) | /* VLD mode */
2692                   (0 << 10) | /* disable Stream-Out */
2693                   (0 << 9)  | /* Post Deblocking Output */
2694                   (1 << 8)  | /* Pre Deblocking Output */
2695                   (0 << 5)  | /* not in stitch mode */
2696                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2697                   (MFX_FORMAT_AVC << 0));
2698     OUT_BCS_BATCH(batch,
2699                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2700                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2701                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2702                   (0 << 1)  |
2703                   (0 << 0));
2704     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2705     OUT_BCS_BATCH(batch, 0); /* reserved */
2706     ADVANCE_BCS_BATCH(batch);
2707 }
2708
2709 static void
2710 gen75_jpeg_wa_surface_state(VADriverContextP ctx,
2711                            struct gen7_mfd_context *gen7_mfd_context)
2712 {
2713     struct i965_driver_data *i965 = i965_driver_data(ctx);
2714     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2715     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2716
2717     BEGIN_BCS_BATCH(batch, 6);
2718     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2719     OUT_BCS_BATCH(batch, 0);
2720     OUT_BCS_BATCH(batch,
2721                   ((obj_surface->orig_width - 1) << 18) |
2722                   ((obj_surface->orig_height - 1) << 4));
2723     OUT_BCS_BATCH(batch,
2724                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2725                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2726                   (0 << 22) | /* surface object control state, ignored */
2727                   ((obj_surface->width - 1) << 3) | /* pitch */
2728                   (0 << 2)  | /* must be 0 */
2729                   (1 << 1)  | /* must be tiled */
2730                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2731     OUT_BCS_BATCH(batch,
2732                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2733                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2734     OUT_BCS_BATCH(batch,
2735                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2736                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2737     ADVANCE_BCS_BATCH(batch);
2738 }
2739
2740 static void
2741 gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx,
2742                                  struct gen7_mfd_context *gen7_mfd_context)
2743 {
2744     struct i965_driver_data *i965 = i965_driver_data(ctx);
2745     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2746     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2747     dri_bo *intra_bo;
2748     int i;
2749
2750     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2751                             "intra row store",
2752                             128 * 64,
2753                             0x1000);
2754
2755     BEGIN_BCS_BATCH(batch, 61);
2756     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
2757     OUT_BCS_RELOC(batch,
2758                   obj_surface->bo,
2759                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2760                   0);
2761         OUT_BCS_BATCH(batch, 0);
2762         OUT_BCS_BATCH(batch, 0);
2763
2764
2765     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2766         OUT_BCS_BATCH(batch, 0);
2767         OUT_BCS_BATCH(batch, 0);
2768
2769         /* uncompressed-video & stream out 7-12 */
2770     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2771     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2772         OUT_BCS_BATCH(batch, 0);
2773         OUT_BCS_BATCH(batch, 0);
2774         OUT_BCS_BATCH(batch, 0);
2775         OUT_BCS_BATCH(batch, 0);
2776
2777         /* the DW 13-15 is for intra row store scratch */
2778     OUT_BCS_RELOC(batch,
2779                   intra_bo,
2780                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2781                   0);
2782         OUT_BCS_BATCH(batch, 0);
2783         OUT_BCS_BATCH(batch, 0);
2784
2785         /* the DW 16-18 is for deblocking filter */
2786     OUT_BCS_BATCH(batch, 0);
2787         OUT_BCS_BATCH(batch, 0);
2788         OUT_BCS_BATCH(batch, 0);
2789
2790     /* DW 19..50 */
2791     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2792         OUT_BCS_BATCH(batch, 0);
2793         OUT_BCS_BATCH(batch, 0);
2794     }
2795     OUT_BCS_BATCH(batch, 0);
2796
2797         /* the DW52-54 is for mb status address */
2798     OUT_BCS_BATCH(batch, 0);
2799         OUT_BCS_BATCH(batch, 0);
2800         OUT_BCS_BATCH(batch, 0);
2801         /* the DW56-60 is for ILDB & second ILDB address */
2802     OUT_BCS_BATCH(batch, 0);
2803         OUT_BCS_BATCH(batch, 0);
2804         OUT_BCS_BATCH(batch, 0);
2805     OUT_BCS_BATCH(batch, 0);
2806         OUT_BCS_BATCH(batch, 0);
2807         OUT_BCS_BATCH(batch, 0);
2808
2809     ADVANCE_BCS_BATCH(batch);
2810
2811     dri_bo_unreference(intra_bo);
2812 }
2813 static void
2814 gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2815                                  struct gen7_mfd_context *gen7_mfd_context)
2816 {
2817     struct i965_driver_data *i965 = i965_driver_data(ctx);
2818     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2819     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2820     dri_bo *intra_bo;
2821     int i;
2822
2823         if (IS_STEPPING_BPLUS(i965)) {
2824                 gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context);
2825                 return;
2826         }
2827     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2828                             "intra row store",
2829                             128 * 64,
2830                             0x1000);
2831
2832     BEGIN_BCS_BATCH(batch, 25);
2833     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
2834     OUT_BCS_RELOC(batch,
2835                   obj_surface->bo,
2836                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2837                   0);
2838
2839     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2840
2841     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2842     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2843
2844     OUT_BCS_RELOC(batch,
2845                   intra_bo,
2846                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2847                   0);
2848
2849     OUT_BCS_BATCH(batch, 0);
2850
2851     /* DW 7..22 */
2852     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2853         OUT_BCS_BATCH(batch, 0);
2854     }
2855
2856     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2857     OUT_BCS_BATCH(batch, 0);
2858     ADVANCE_BCS_BATCH(batch);
2859
2860     dri_bo_unreference(intra_bo);
2861 }
2862
2863 static void
2864 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
2865                                      struct gen7_mfd_context *gen7_mfd_context)
2866 {
2867     struct i965_driver_data *i965 = i965_driver_data(ctx);
2868     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2869     dri_bo *bsd_mpc_bo, *mpr_bo;
2870
2871     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2872                               "bsd mpc row store",
2873                               11520, /* 1.5 * 120 * 64 */
2874                               0x1000);
2875
2876     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2877                           "mpr row store",
2878                           7680, /* 1. 0 * 120 * 64 */
2879                           0x1000);
2880
2881     BEGIN_BCS_BATCH(batch, 10);
2882     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
2883
2884     OUT_BCS_RELOC(batch,
2885                   bsd_mpc_bo,
2886                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2887                   0);
2888
2889     OUT_BCS_BATCH(batch, 0);
2890     OUT_BCS_BATCH(batch, 0);
2891
2892     OUT_BCS_RELOC(batch,
2893                   mpr_bo,
2894                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2895                   0);
2896     OUT_BCS_BATCH(batch, 0);
2897     OUT_BCS_BATCH(batch, 0);
2898
2899     OUT_BCS_BATCH(batch, 0);
2900     OUT_BCS_BATCH(batch, 0);
2901     OUT_BCS_BATCH(batch, 0);
2902
2903     ADVANCE_BCS_BATCH(batch);
2904
2905     dri_bo_unreference(bsd_mpc_bo);
2906     dri_bo_unreference(mpr_bo);
2907 }
2908
2909 static void
2910 gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2911                                      struct gen7_mfd_context *gen7_mfd_context)
2912 {
2913     struct i965_driver_data *i965 = i965_driver_data(ctx);
2914     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2915     dri_bo *bsd_mpc_bo, *mpr_bo;
2916
2917     if (IS_STEPPING_BPLUS(i965)) {
2918         gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(ctx, gen7_mfd_context);
2919         return;
2920     }
2921
2922     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2923                               "bsd mpc row store",
2924                               11520, /* 1.5 * 120 * 64 */
2925                               0x1000);
2926
2927     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2928                           "mpr row store",
2929                           7680, /* 1. 0 * 120 * 64 */
2930                           0x1000);
2931
2932     BEGIN_BCS_BATCH(batch, 4);
2933     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2934
2935     OUT_BCS_RELOC(batch,
2936                   bsd_mpc_bo,
2937                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2938                   0);
2939
2940     OUT_BCS_RELOC(batch,
2941                   mpr_bo,
2942                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2943                   0);
2944     OUT_BCS_BATCH(batch, 0);
2945
2946     ADVANCE_BCS_BATCH(batch);
2947
2948     dri_bo_unreference(bsd_mpc_bo);
2949     dri_bo_unreference(mpr_bo);
2950 }
2951
2952 static void
2953 gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2954                           struct gen7_mfd_context *gen7_mfd_context)
2955 {
2956
2957 }
2958
2959 static void
2960 gen75_jpeg_wa_avc_img_state(VADriverContextP ctx,
2961                            struct gen7_mfd_context *gen7_mfd_context)
2962 {
2963     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2964     int img_struct = 0;
2965     int mbaff_frame_flag = 0;
2966     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2967
2968     BEGIN_BCS_BATCH(batch, 16);
2969     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2970     OUT_BCS_BATCH(batch,
2971                   width_in_mbs * height_in_mbs);
2972     OUT_BCS_BATCH(batch,
2973                   ((height_in_mbs - 1) << 16) |
2974                   ((width_in_mbs - 1) << 0));
2975     OUT_BCS_BATCH(batch,
2976                   (0 << 24) |
2977                   (0 << 16) |
2978                   (0 << 14) |
2979                   (0 << 13) |
2980                   (0 << 12) | /* differ from GEN6 */
2981                   (0 << 10) |
2982                   (img_struct << 8));
2983     OUT_BCS_BATCH(batch,
2984                   (1 << 10) | /* 4:2:0 */
2985                   (1 << 7) |  /* CABAC */
2986                   (0 << 6) |
2987                   (0 << 5) |
2988                   (0 << 4) |
2989                   (0 << 3) |
2990                   (1 << 2) |
2991                   (mbaff_frame_flag << 1) |
2992                   (0 << 0));
2993     OUT_BCS_BATCH(batch, 0);
2994     OUT_BCS_BATCH(batch, 0);
2995     OUT_BCS_BATCH(batch, 0);
2996     OUT_BCS_BATCH(batch, 0);
2997     OUT_BCS_BATCH(batch, 0);
2998     OUT_BCS_BATCH(batch, 0);
2999     OUT_BCS_BATCH(batch, 0);
3000     OUT_BCS_BATCH(batch, 0);
3001     OUT_BCS_BATCH(batch, 0);
3002     OUT_BCS_BATCH(batch, 0);
3003     OUT_BCS_BATCH(batch, 0);
3004     ADVANCE_BCS_BATCH(batch);
3005 }
3006
3007 static void
3008 gen75_jpeg_wa_avc_directmode_state_bplus(VADriverContextP ctx,
3009                                   struct gen7_mfd_context *gen7_mfd_context)
3010 {
3011     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3012     int i;
3013
3014     BEGIN_BCS_BATCH(batch, 71);
3015     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
3016
3017     /* reference surfaces 0..15 */
3018     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3019         OUT_BCS_BATCH(batch, 0); /* top */
3020         OUT_BCS_BATCH(batch, 0); /* bottom */
3021     }
3022
3023         OUT_BCS_BATCH(batch, 0);
3024
3025     /* the current decoding frame/field */
3026     OUT_BCS_BATCH(batch, 0); /* top */
3027     OUT_BCS_BATCH(batch, 0);
3028     OUT_BCS_BATCH(batch, 0);
3029
3030     /* POC List */
3031     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3032         OUT_BCS_BATCH(batch, 0);
3033         OUT_BCS_BATCH(batch, 0);
3034     }
3035
3036     OUT_BCS_BATCH(batch, 0);
3037     OUT_BCS_BATCH(batch, 0);
3038
3039     ADVANCE_BCS_BATCH(batch);
3040 }
3041
3042 static void
3043 gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
3044                                   struct gen7_mfd_context *gen7_mfd_context)
3045 {
3046     struct i965_driver_data *i965 = i965_driver_data(ctx);
3047     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3048     int i;
3049
3050     if (IS_STEPPING_BPLUS(i965)) {
3051         gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context);
3052         return;
3053     }
3054
3055     BEGIN_BCS_BATCH(batch, 69);
3056     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
3057
3058     /* reference surfaces 0..15 */
3059     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3060         OUT_BCS_BATCH(batch, 0); /* top */
3061         OUT_BCS_BATCH(batch, 0); /* bottom */
3062     }
3063
3064     /* the current decoding frame/field */
3065     OUT_BCS_BATCH(batch, 0); /* top */
3066     OUT_BCS_BATCH(batch, 0); /* bottom */
3067
3068     /* POC List */
3069     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3070         OUT_BCS_BATCH(batch, 0);
3071         OUT_BCS_BATCH(batch, 0);
3072     }
3073
3074     OUT_BCS_BATCH(batch, 0);
3075     OUT_BCS_BATCH(batch, 0);
3076
3077     ADVANCE_BCS_BATCH(batch);
3078 }
3079
3080 static void
3081 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
3082                                      struct gen7_mfd_context *gen7_mfd_context)
3083 {
3084     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3085
3086     BEGIN_BCS_BATCH(batch, 11);
3087     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3088     OUT_BCS_RELOC(batch,
3089                   gen7_mfd_context->jpeg_wa_slice_data_bo,
3090                   I915_GEM_DOMAIN_INSTRUCTION, 0,
3091                   0);
3092     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3093     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3094     OUT_BCS_BATCH(batch, 0);
3095     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3096     OUT_BCS_BATCH(batch, 0);
3097     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3098     OUT_BCS_BATCH(batch, 0);
3099     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3100     OUT_BCS_BATCH(batch, 0);
3101     ADVANCE_BCS_BATCH(batch);
3102 }
3103
3104 static void
3105 gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
3106                                      struct gen7_mfd_context *gen7_mfd_context)
3107 {
3108     struct i965_driver_data *i965 = i965_driver_data(ctx);
3109     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3110
3111     if (IS_STEPPING_BPLUS(i965)) {
3112         gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context);
3113         return;
3114     }
3115     BEGIN_BCS_BATCH(batch, 11);
3116     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3117     OUT_BCS_RELOC(batch,
3118                   gen7_mfd_context->jpeg_wa_slice_data_bo,
3119                   I915_GEM_DOMAIN_INSTRUCTION, 0,
3120                   0);
3121     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3122     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3123     OUT_BCS_BATCH(batch, 0);
3124     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3125     OUT_BCS_BATCH(batch, 0);
3126     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3127     OUT_BCS_BATCH(batch, 0);
3128     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3129     OUT_BCS_BATCH(batch, 0);
3130     ADVANCE_BCS_BATCH(batch);
3131 }
3132
3133 static void
3134 gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
3135                             struct gen7_mfd_context *gen7_mfd_context)
3136 {
3137     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3138
3139     /* the input bitsteam format on GEN7 differs from GEN6 */
3140     BEGIN_BCS_BATCH(batch, 6);
3141     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
3142     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
3143     OUT_BCS_BATCH(batch, 0);
3144     OUT_BCS_BATCH(batch,
3145                   (0 << 31) |
3146                   (0 << 14) |
3147                   (0 << 12) |
3148                   (0 << 10) |
3149                   (0 << 8));
3150     OUT_BCS_BATCH(batch,
3151                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
3152                   (0 << 5)  |
3153                   (0 << 4)  |
3154                   (1 << 3) | /* LastSlice Flag */
3155                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
3156     OUT_BCS_BATCH(batch, 0);
3157     ADVANCE_BCS_BATCH(batch);
3158 }
3159
3160 static void
3161 gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx,
3162                              struct gen7_mfd_context *gen7_mfd_context)
3163 {
3164     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3165     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
3166     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
3167     int first_mb_in_slice = 0;
3168     int slice_type = SLICE_TYPE_I;
3169
3170     BEGIN_BCS_BATCH(batch, 11);
3171     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
3172     OUT_BCS_BATCH(batch, slice_type);
3173     OUT_BCS_BATCH(batch,
3174                   (num_ref_idx_l1 << 24) |
3175                   (num_ref_idx_l0 << 16) |
3176                   (0 << 8) |
3177                   (0 << 0));
3178     OUT_BCS_BATCH(batch,
3179                   (0 << 29) |
3180                   (1 << 27) |   /* disable Deblocking */
3181                   (0 << 24) |
3182                   (gen7_jpeg_wa_clip.qp << 16) |
3183                   (0 << 8) |
3184                   (0 << 0));
3185     OUT_BCS_BATCH(batch,
3186                   (slice_ver_pos << 24) |
3187                   (slice_hor_pos << 16) |
3188                   (first_mb_in_slice << 0));
3189     OUT_BCS_BATCH(batch,
3190                   (next_slice_ver_pos << 16) |
3191                   (next_slice_hor_pos << 0));
3192     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
3193     OUT_BCS_BATCH(batch, 0);
3194     OUT_BCS_BATCH(batch, 0);
3195     OUT_BCS_BATCH(batch, 0);
3196     OUT_BCS_BATCH(batch, 0);
3197     ADVANCE_BCS_BATCH(batch);
3198 }
3199
3200 static void
3201 gen75_mfd_jpeg_wa(VADriverContextP ctx,
3202                  struct gen7_mfd_context *gen7_mfd_context)
3203 {
3204     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3205     gen75_jpeg_wa_init(ctx, gen7_mfd_context);
3206     intel_batchbuffer_emit_mi_flush(batch);
3207     gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
3208     gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context);
3209     gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
3210     gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
3211     gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
3212     gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
3213     gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
3214
3215     gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
3216     gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
3217     gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
3218 }
3219
3220 void
3221 gen75_mfd_jpeg_decode_picture(VADriverContextP ctx,
3222                              struct decode_state *decode_state,
3223                              struct gen7_mfd_context *gen7_mfd_context)
3224 {
3225     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3226     VAPictureParameterBufferJPEGBaseline *pic_param;
3227     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
3228     dri_bo *slice_data_bo;
3229     int i, j, max_selector = 0;
3230
3231     assert(decode_state->pic_param && decode_state->pic_param->buffer);
3232     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
3233
3234     /* Currently only support Baseline DCT */
3235     gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
3236     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
3237     gen75_mfd_jpeg_wa(ctx, gen7_mfd_context);
3238     intel_batchbuffer_emit_mi_flush(batch);
3239     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3240     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3241     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3242     gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
3243     gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
3244
3245     for (j = 0; j < decode_state->num_slice_params; j++) {
3246         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3247         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3248         slice_data_bo = decode_state->slice_datas[j]->bo;
3249         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3250
3251         if (j == decode_state->num_slice_params - 1)
3252             next_slice_group_param = NULL;
3253         else
3254             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3255
3256         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3257             int component;
3258
3259             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3260
3261             if (i < decode_state->slice_params[j]->num_elements - 1)
3262                 next_slice_param = slice_param + 1;
3263             else
3264                 next_slice_param = next_slice_group_param;
3265
3266             for (component = 0; component < slice_param->num_components; component++) {
3267                 if (max_selector < slice_param->components[component].dc_table_selector)
3268                     max_selector = slice_param->components[component].dc_table_selector;
3269
3270                 if (max_selector < slice_param->components[component].ac_table_selector)
3271                     max_selector = slice_param->components[component].ac_table_selector;
3272             }
3273
3274             slice_param++;
3275         }
3276     }
3277
3278     assert(max_selector < 2);
3279     gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
3280
3281     for (j = 0; j < decode_state->num_slice_params; j++) {
3282         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3283         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3284         slice_data_bo = decode_state->slice_datas[j]->bo;
3285         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3286
3287         if (j == decode_state->num_slice_params - 1)
3288             next_slice_group_param = NULL;
3289         else
3290             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3291
3292         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3293             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3294
3295             if (i < decode_state->slice_params[j]->num_elements - 1)
3296                 next_slice_param = slice_param + 1;
3297             else
3298                 next_slice_param = next_slice_group_param;
3299
3300             gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
3301             slice_param++;
3302         }
3303     }
3304
3305     intel_batchbuffer_end_atomic(batch);
3306     intel_batchbuffer_flush(batch);
3307 }
3308
3309 static void
3310 gen75_mfd_decode_picture(VADriverContextP ctx,
3311                         VAProfile profile,
3312                         union codec_state *codec_state,
3313                         struct hw_context *hw_context)
3314
3315 {
3316     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3317     struct decode_state *decode_state = &codec_state->decode;
3318
3319     assert(gen7_mfd_context);
3320
3321     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
3322
3323     switch (profile) {
3324     case VAProfileMPEG2Simple:
3325     case VAProfileMPEG2Main:
3326         gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
3327         break;
3328
3329     case VAProfileH264Baseline:
3330     case VAProfileH264Main:
3331     case VAProfileH264High:
3332         gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
3333         break;
3334
3335     case VAProfileVC1Simple:
3336     case VAProfileVC1Main:
3337     case VAProfileVC1Advanced:
3338         gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
3339         break;
3340
3341     case VAProfileJPEGBaseline:
3342         gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
3343         break;
3344
3345     default:
3346         assert(0);
3347         break;
3348     }
3349 }
3350
3351 static void
3352 gen75_mfd_context_destroy(void *hw_context)
3353 {
3354     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3355
3356     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
3357     gen7_mfd_context->post_deblocking_output.bo = NULL;
3358
3359     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
3360     gen7_mfd_context->pre_deblocking_output.bo = NULL;
3361
3362     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
3363     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
3364
3365     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
3366     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
3367
3368     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
3369     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
3370
3371     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
3372     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
3373
3374     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
3375     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
3376
3377     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
3378
3379     intel_batchbuffer_free(gen7_mfd_context->base.batch);
3380     free(gen7_mfd_context);
3381 }
3382
3383 static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx,
3384                                     struct gen7_mfd_context *gen7_mfd_context)
3385 {
3386     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
3387     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
3388     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
3389     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
3390 }
3391
3392 struct hw_context *
3393 gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
3394 {
3395     struct intel_driver_data *intel = intel_driver_data(ctx);
3396     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
3397     int i;
3398
3399     gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
3400     gen7_mfd_context->base.run = gen75_mfd_decode_picture;
3401     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
3402
3403     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
3404         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
3405         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
3406     }
3407
3408     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
3409
3410     switch (obj_config->profile) {
3411     case VAProfileMPEG2Simple:
3412     case VAProfileMPEG2Main:
3413         gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
3414         break;
3415
3416     case VAProfileH264Baseline:
3417     case VAProfileH264Main:
3418     case VAProfileH264High:
3419         gen75_mfd_avc_context_init(ctx, gen7_mfd_context);
3420         break;
3421     default:
3422         break;
3423     }
3424     return (struct hw_context *)gen7_mfd_context;
3425 }