src/gen75_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zhao  Yakui  <yakui.zhao@intel.com>
  27  *
  28  */
  29
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include <assert.h>
  34 #include <va/va_dec_jpeg.h>
  35
  36 #include "intel_batchbuffer.h"
  37 #include "intel_driver.h"
  38
  39 #include "i965_defines.h"
  40 #include "i965_drv_video.h"
  41 #include "i965_decoder_utils.h"
  42
  43 #include "gen7_mfd.h"
  44
  45 static const uint32_t zigzag_direct[64] = {
  46     0,   1,  8, 16,  9,  2,  3, 10,
  47     17, 24, 32, 25, 18, 11,  4,  5,
  48     12, 19, 26, 33, 40, 48, 41, 34,
  49     27, 20, 13,  6,  7, 14, 21, 28,
  50     35, 42, 49, 56, 57, 50, 43, 36,
  51     29, 22, 15, 23, 30, 37, 44, 51,
  52     58, 59, 52, 45, 38, 31, 39, 46,
  53     53, 60, 61, 54, 47, 55, 62, 63
  54 };
  55
  56 static void
  57 gen75_mfd_avc_frame_store_index(VADriverContextP ctx,
  58                                VAPictureParameterBufferH264 *pic_param,
  59                                struct gen7_mfd_context *gen7_mfd_context)
  60 {
  61     struct i965_driver_data *i965 = i965_driver_data(ctx);
  62     int i, j;
  63
  64     assert(ARRAY_ELEMS(gen7_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
  65
  66     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
  67         int found = 0;
  68
  69         if (gen7_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
  70             continue;
  71
  72         for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
  73             VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
  74             if (ref_pic->flags & VA_PICTURE_H264_INVALID)
  75                 continue;
  76
  77             if (gen7_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
  78                 found = 1;
  79                 break;
  80             }
  81         }
  82
  83         if (!found) {
  84             struct object_surface *obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
  85             obj_surface->flags &= ~SURFACE_REFERENCED;
  86
  87             if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
  88                 dri_bo_unreference(obj_surface->bo);
  89                 obj_surface->bo = NULL;
  90                 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
  91             }
  92
  93             if (obj_surface->free_private_data)
  94                 obj_surface->free_private_data(&obj_surface->private_data);
  95
  96             gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
  97             gen7_mfd_context->reference_surface[i].frame_store_id = -1;
  98         }
  99     }
 100
 101     for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
 102         VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
 103         int found = 0;
 104
 105         if (ref_pic->flags & VA_PICTURE_H264_INVALID)
 106             continue;
 107
 108         for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 109             if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 110                 continue;
 111
 112             if (gen7_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
 113                 found = 1;
 114                 break;
 115             }
 116         }
 117
 118         if (!found) {
 119             int frame_idx;
 120             struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
 121
 122             assert(obj_surface);
 123             i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 124
 125             for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface); frame_idx++) {
 126                 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 127                     if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 128                         continue;
 129
 130                     if (gen7_mfd_context->reference_surface[j].frame_store_id == frame_idx)
 131                         break;
 132                 }
 133
 134                 if (j == ARRAY_ELEMS(gen7_mfd_context->reference_surface))
 135                     break;
 136             }
 137
 138             assert(frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface));
 139
 140             for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 141                 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
 142                     gen7_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
 143                     gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 144                     break;
 145                 }
 146             }
 147         }
 148     }
 149
 150     /* sort */
 151     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface) - 1; i++) {
 152         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 153             gen7_mfd_context->reference_surface[i].frame_store_id == i)
 154             continue;
 155
 156         for (j = i + 1; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 157             if (gen7_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
 158                 gen7_mfd_context->reference_surface[j].frame_store_id == i) {
 159                 VASurfaceID id = gen7_mfd_context->reference_surface[i].surface_id;
 160                 int frame_idx = gen7_mfd_context->reference_surface[i].frame_store_id;
 161
 162                 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[j].surface_id;
 163                 gen7_mfd_context->reference_surface[i].frame_store_id = gen7_mfd_context->reference_surface[j].frame_store_id;
 164                 gen7_mfd_context->reference_surface[j].surface_id = id;
 165                 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 166                 break;
 167             }
 168         }
 169     }
 170 }
 171
 172 static void
 173 gen75_mfd_free_avc_surface(void **data)
 174 {
 175     struct gen7_avc_surface *gen7_avc_surface = *data;
 176
 177     if (!gen7_avc_surface)
 178         return;
 179
 180     dri_bo_unreference(gen7_avc_surface->dmv_top);
 181     gen7_avc_surface->dmv_top = NULL;
 182     dri_bo_unreference(gen7_avc_surface->dmv_bottom);
 183     gen7_avc_surface->dmv_bottom = NULL;
 184
 185     free(gen7_avc_surface);
 186     *data = NULL;
 187 }
 188
 189 static void
 190 gen75_mfd_init_avc_surface(VADriverContextP ctx,
 191                           VAPictureParameterBufferH264 *pic_param,
 192                           struct object_surface *obj_surface)
 193 {
 194     struct i965_driver_data *i965 = i965_driver_data(ctx);
 195     struct gen7_avc_surface *gen7_avc_surface = obj_surface->private_data;
 196     int width_in_mbs, height_in_mbs;
 197
 198     obj_surface->free_private_data = gen75_mfd_free_avc_surface;
 199     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 200     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 201
 202     if (!gen7_avc_surface) {
 203         gen7_avc_surface = calloc(sizeof(struct gen7_avc_surface), 1);
 204         assert((obj_surface->size & 0x3f) == 0);
 205         obj_surface->private_data = gen7_avc_surface;
 206     }
 207
 208     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
 209                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
 210
 211     if (gen7_avc_surface->dmv_top == NULL) {
 212         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
 213                                                  "direct mv w/r buffer",
 214                                                  width_in_mbs * height_in_mbs * 64,
 215                                                  0x1000);
 216         assert(gen7_avc_surface->dmv_top);
 217     }
 218
 219     if (gen7_avc_surface->dmv_bottom_flag &&
 220         gen7_avc_surface->dmv_bottom == NULL) {
 221         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
 222                                                     "direct mv w/r buffer",
 223                                                     width_in_mbs * height_in_mbs * 64,
 224                                                     0x1000);
 225         assert(gen7_avc_surface->dmv_bottom);
 226     }
 227 }
 228
 229 static void
 230 gen75_mfd_pipe_mode_select(VADriverContextP ctx,
 231                           struct decode_state *decode_state,
 232                           int standard_select,
 233                           struct gen7_mfd_context *gen7_mfd_context)
 234 {
 235     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 236
 237     assert(standard_select == MFX_FORMAT_MPEG2 ||
 238            standard_select == MFX_FORMAT_AVC ||
 239            standard_select == MFX_FORMAT_VC1 ||
 240            standard_select == MFX_FORMAT_JPEG);
 241
 242     BEGIN_BCS_BATCH(batch, 5);
 243     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 244     OUT_BCS_BATCH(batch,
 245                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 246                   (MFD_MODE_VLD << 15) | /* VLD mode */
 247                   (0 << 10) | /* disable Stream-Out */
 248                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 249                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 250                   (0 << 5)  | /* not in stitch mode */
 251                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 252                   (standard_select << 0));
 253     OUT_BCS_BATCH(batch,
 254                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 255                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 256                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 257                   (0 << 1)  |
 258                   (0 << 0));
 259     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 260     OUT_BCS_BATCH(batch, 0); /* reserved */
 261     ADVANCE_BCS_BATCH(batch);
 262 }
 263
 264 static void
 265 gen75_mfd_surface_state(VADriverContextP ctx,
 266                        struct decode_state *decode_state,
 267                        int standard_select,
 268                        struct gen7_mfd_context *gen7_mfd_context)
 269 {
 270     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 271     struct i965_driver_data *i965 = i965_driver_data(ctx);
 272     struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
 273     unsigned int y_cb_offset;
 274     unsigned int y_cr_offset;
 275
 276     assert(obj_surface);
 277
 278     y_cb_offset = obj_surface->y_cb_offset;
 279     y_cr_offset = obj_surface->y_cr_offset;
 280
 281     BEGIN_BCS_BATCH(batch, 6);
 282     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 283     OUT_BCS_BATCH(batch, 0);
 284     OUT_BCS_BATCH(batch,
 285                   ((obj_surface->orig_height - 1) << 18) |
 286                   ((obj_surface->orig_width - 1) << 4));
 287     OUT_BCS_BATCH(batch,
 288                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 289                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 290                   (0 << 22) | /* surface object control state, ignored */
 291                   ((obj_surface->width - 1) << 3) | /* pitch */
 292                   (0 << 2)  | /* must be 0 */
 293                   (1 << 1)  | /* must be tiled */
 294                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 295     OUT_BCS_BATCH(batch,
 296                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 297                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 298     OUT_BCS_BATCH(batch,
 299                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 300                   (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 301     ADVANCE_BCS_BATCH(batch);
 302 }
 303
 304 static void
 305 gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 306                              struct decode_state *decode_state,
 307                              int standard_select,
 308                              struct gen7_mfd_context *gen7_mfd_context)
 309 {
 310     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 311     struct i965_driver_data *i965 = i965_driver_data(ctx);
 312     int i;
 313
 314     BEGIN_BCS_BATCH(batch, 24);
 315     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 316     if (gen7_mfd_context->pre_deblocking_output.valid)
 317         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 318                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 319                       0);
 320     else
 321         OUT_BCS_BATCH(batch, 0);
 322
 323     if (gen7_mfd_context->post_deblocking_output.valid)
 324         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 325                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 326                       0);
 327     else
 328         OUT_BCS_BATCH(batch, 0);
 329
 330     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 331     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 332
 333     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 334         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 335                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 336                       0);
 337     else
 338         OUT_BCS_BATCH(batch, 0);
 339
 340     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 341         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 342                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 343                       0);
 344     else
 345         OUT_BCS_BATCH(batch, 0);
 346
 347     /* DW 7..22 */
 348     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 349         struct object_surface *obj_surface;
 350
 351         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 352             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 353             assert(obj_surface && obj_surface->bo);
 354
 355             OUT_BCS_RELOC(batch, obj_surface->bo,
 356                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 357                           0);
 358         } else {
 359             OUT_BCS_BATCH(batch, 0);
 360         }
 361     }
 362
 363     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 364     ADVANCE_BCS_BATCH(batch);
 365 }
 366
 367 static void
 368 gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 369                                  dri_bo *slice_data_bo,
 370                                  int standard_select,
 371                                  struct gen7_mfd_context *gen7_mfd_context)
 372 {
 373     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 374
 375     BEGIN_BCS_BATCH(batch, 11);
 376     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 377     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 378     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 379     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 380     OUT_BCS_BATCH(batch, 0);
 381     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 382     OUT_BCS_BATCH(batch, 0);
 383     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 384     OUT_BCS_BATCH(batch, 0);
 385     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 386     OUT_BCS_BATCH(batch, 0);
 387     ADVANCE_BCS_BATCH(batch);
 388 }
 389
 390 static void
 391 gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 392                                  struct decode_state *decode_state,
 393                                  int standard_select,
 394                                  struct gen7_mfd_context *gen7_mfd_context)
 395 {
 396     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 397
 398     BEGIN_BCS_BATCH(batch, 4);
 399     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 400
 401     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 402         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 403                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 404                       0);
 405     else
 406         OUT_BCS_BATCH(batch, 0);
 407
 408     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 409         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 410                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 411                       0);
 412     else
 413         OUT_BCS_BATCH(batch, 0);
 414
 415     if (gen7_mfd_context->bitplane_read_buffer.valid)
 416         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 417                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 418                       0);
 419     else
 420         OUT_BCS_BATCH(batch, 0);
 421
 422     ADVANCE_BCS_BATCH(batch);
 423 }
 424
 425 #if 0
 426 static void
 427 gen7_mfd_aes_state(VADriverContextP ctx,
 428                    struct decode_state *decode_state,
 429                    int standard_select)
 430 {
 431     /* FIXME */
 432 }
 433 #endif
 434
 435 static void
 436 gen75_mfd_qm_state(VADriverContextP ctx,
 437                   int qm_type,
 438                   unsigned char *qm,
 439                   int qm_length,
 440                   struct gen7_mfd_context *gen7_mfd_context)
 441 {
 442     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 443     unsigned int qm_buffer[16];
 444
 445     assert(qm_length <= 16 * 4);
 446     memcpy(qm_buffer, qm, qm_length);
 447
 448     BEGIN_BCS_BATCH(batch, 18);
 449     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 450     OUT_BCS_BATCH(batch, qm_type << 0);
 451     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 452     ADVANCE_BCS_BATCH(batch);
 453 }
 454
 455 #if 0
 456 static void
 457 gen7_mfd_wait(VADriverContextP ctx,
 458               struct decode_state *decode_state,
 459               int standard_select,
 460               struct gen7_mfd_context *gen7_mfd_context)
 461 {
 462     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 463
 464     BEGIN_BCS_BATCH(batch, 1);
 465     OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
 466     ADVANCE_BCS_BATCH(batch);
 467 }
 468 #endif
 469
 470 static void
 471 gen75_mfd_avc_img_state(VADriverContextP ctx,
 472                        struct decode_state *decode_state,
 473                        struct gen7_mfd_context *gen7_mfd_context)
 474 {
 475     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 476     int img_struct;
 477     int mbaff_frame_flag;
 478     unsigned int width_in_mbs, height_in_mbs;
 479     VAPictureParameterBufferH264 *pic_param;
 480
 481     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 482     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 483     assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
 484
 485     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 486         img_struct = 1;
 487     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 488         img_struct = 3;
 489     else
 490         img_struct = 0;
 491
 492     if ((img_struct & 0x1) == 0x1) {
 493         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 494     } else {
 495         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 496     }
 497
 498     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 499         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 500         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 501     } else {
 502         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 503     }
 504
 505     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 506                         !pic_param->pic_fields.bits.field_pic_flag);
 507
 508     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 509     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 510
 511     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 512     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 513            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 514     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 515
 516     BEGIN_BCS_BATCH(batch, 16);
 517     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 518     OUT_BCS_BATCH(batch,
 519                   width_in_mbs * height_in_mbs);
 520     OUT_BCS_BATCH(batch,
 521                   ((height_in_mbs - 1) << 16) |
 522                   ((width_in_mbs - 1) << 0));
 523     OUT_BCS_BATCH(batch,
 524                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 525                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 526                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 527                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 528                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 529                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 530                   (img_struct << 8));
 531     OUT_BCS_BATCH(batch,
 532                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 533                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 534                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 535                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 536                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 537                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 538                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 539                   (mbaff_frame_flag << 1) |
 540                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 541     OUT_BCS_BATCH(batch, 0);
 542     OUT_BCS_BATCH(batch, 0);
 543     OUT_BCS_BATCH(batch, 0);
 544     OUT_BCS_BATCH(batch, 0);
 545     OUT_BCS_BATCH(batch, 0);
 546     OUT_BCS_BATCH(batch, 0);
 547     OUT_BCS_BATCH(batch, 0);
 548     OUT_BCS_BATCH(batch, 0);
 549     OUT_BCS_BATCH(batch, 0);
 550     OUT_BCS_BATCH(batch, 0);
 551     OUT_BCS_BATCH(batch, 0);
 552     ADVANCE_BCS_BATCH(batch);
 553 }
 554
 555 static void
 556 gen75_mfd_avc_qm_state(VADriverContextP ctx,
 557                       struct decode_state *decode_state,
 558                       struct gen7_mfd_context *gen7_mfd_context)
 559 {
 560     VAIQMatrixBufferH264 *iq_matrix;
 561     VAPictureParameterBufferH264 *pic_param;
 562
 563     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 564         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 565     else
 566         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 567
 568     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 569     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 570
 571     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 572     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 573
 574     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 575         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 576         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 577     }
 578 }
 579
 580 static void
 581 gen75_mfd_avc_directmode_state(VADriverContextP ctx,
 582                               VAPictureParameterBufferH264 *pic_param,
 583                               VASliceParameterBufferH264 *slice_param,
 584                               struct gen7_mfd_context *gen7_mfd_context)
 585 {
 586     struct i965_driver_data *i965 = i965_driver_data(ctx);
 587     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 588     struct object_surface *obj_surface;
 589     struct gen7_avc_surface *gen7_avc_surface;
 590     VAPictureH264 *va_pic;
 591     int i, j;
 592
 593     BEGIN_BCS_BATCH(batch, 69);
 594     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 595
 596     /* reference surfaces 0..15 */
 597     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 598         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 599             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 600             assert(obj_surface);
 601             gen7_avc_surface = obj_surface->private_data;
 602
 603             if (gen7_avc_surface == NULL) {
 604                 OUT_BCS_BATCH(batch, 0);
 605                 OUT_BCS_BATCH(batch, 0);
 606             } else {
 607                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 608                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 609                               0);
 610
 611                 if (gen7_avc_surface->dmv_bottom_flag == 1)
 612                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 613                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 614                                   0);
 615                 else
 616                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 617                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 618                                   0);
 619             }
 620         } else {
 621             OUT_BCS_BATCH(batch, 0);
 622             OUT_BCS_BATCH(batch, 0);
 623         }
 624     }
 625
 626     /* the current decoding frame/field */
 627     va_pic = &pic_param->CurrPic;
 628     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 629     obj_surface = SURFACE(va_pic->picture_id);
 630     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 631     gen7_avc_surface = obj_surface->private_data;
 632
 633     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 634                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 635                   0);
 636
 637     if (gen7_avc_surface->dmv_bottom_flag == 1)
 638         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 639                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 640                       0);
 641     else
 642         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 643                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 644                       0);
 645
 646     /* POC List */
 647     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 648         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 649             int found = 0;
 650             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 651                 va_pic = &pic_param->ReferenceFrames[j];
 652
 653                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 654                     continue;
 655
 656                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 657                     found = 1;
 658                     break;
 659                 }
 660             }
 661
 662             assert(found == 1);
 663             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 664
 665             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 666             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 667         } else {
 668             OUT_BCS_BATCH(batch, 0);
 669             OUT_BCS_BATCH(batch, 0);
 670         }
 671     }
 672
 673     va_pic = &pic_param->CurrPic;
 674     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 675     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 676
 677     ADVANCE_BCS_BATCH(batch);
 678 }
 679
 680 static void
 681 gen75_mfd_avc_slice_state(VADriverContextP ctx,
 682                          VAPictureParameterBufferH264 *pic_param,
 683                          VASliceParameterBufferH264 *slice_param,
 684                          VASliceParameterBufferH264 *next_slice_param,
 685                          struct gen7_mfd_context *gen7_mfd_context)
 686 {
 687     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 688     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 689     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 690     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 691     int num_ref_idx_l0, num_ref_idx_l1;
 692     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 693                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 694     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 695     int slice_type;
 696
 697     if (slice_param->slice_type == SLICE_TYPE_I ||
 698         slice_param->slice_type == SLICE_TYPE_SI) {
 699         slice_type = SLICE_TYPE_I;
 700     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 701                slice_param->slice_type == SLICE_TYPE_SP) {
 702         slice_type = SLICE_TYPE_P;
 703     } else {
 704         assert(slice_param->slice_type == SLICE_TYPE_B);
 705         slice_type = SLICE_TYPE_B;
 706     }
 707
 708     if (slice_type == SLICE_TYPE_I) {
 709         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 710         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 711         num_ref_idx_l0 = 0;
 712         num_ref_idx_l1 = 0;
 713     } else if (slice_type == SLICE_TYPE_P) {
 714         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 715         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 716         num_ref_idx_l1 = 0;
 717     } else {
 718         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 719         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 720     }
 721
 722     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 723     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 724     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 725
 726     if (next_slice_param) {
 727         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 728         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 729         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 730     } else {
 731         next_slice_hor_pos = 0;
 732         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 733     }
 734
 735     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 736     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 737     OUT_BCS_BATCH(batch, slice_type);
 738     OUT_BCS_BATCH(batch,
 739                   (num_ref_idx_l1 << 24) |
 740                   (num_ref_idx_l0 << 16) |
 741                   (slice_param->chroma_log2_weight_denom << 8) |
 742                   (slice_param->luma_log2_weight_denom << 0));
 743     OUT_BCS_BATCH(batch,
 744                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 745                   (slice_param->disable_deblocking_filter_idc << 27) |
 746                   (slice_param->cabac_init_idc << 24) |
 747                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 748                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 749                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 750     OUT_BCS_BATCH(batch,
 751                   (slice_ver_pos << 24) |
 752                   (slice_hor_pos << 16) |
 753                   (first_mb_in_slice << 0));
 754     OUT_BCS_BATCH(batch,
 755                   (next_slice_ver_pos << 16) |
 756                   (next_slice_hor_pos << 0));
 757     OUT_BCS_BATCH(batch,
 758                   (next_slice_param == NULL) << 19); /* last slice flag */
 759     OUT_BCS_BATCH(batch, 0);
 760     OUT_BCS_BATCH(batch, 0);
 761     OUT_BCS_BATCH(batch, 0);
 762     OUT_BCS_BATCH(batch, 0);
 763     ADVANCE_BCS_BATCH(batch);
 764 }
 765
 766 static inline void
 767 gen75_mfd_avc_ref_idx_state(VADriverContextP ctx,
 768                            VAPictureParameterBufferH264 *pic_param,
 769                            VASliceParameterBufferH264 *slice_param,
 770                            struct gen7_mfd_context *gen7_mfd_context)
 771 {
 772     gen6_send_avc_ref_idx_state(
 773         gen7_mfd_context->base.batch,
 774         slice_param,
 775         gen7_mfd_context->reference_surface
 776     );
 777 }
 778
 779 static void
 780 gen75_mfd_avc_weightoffset_state(VADriverContextP ctx,
 781                                 VAPictureParameterBufferH264 *pic_param,
 782                                 VASliceParameterBufferH264 *slice_param,
 783                                 struct gen7_mfd_context *gen7_mfd_context)
 784 {
 785     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 786     int i, j, num_weight_offset_table = 0;
 787     short weightoffsets[32 * 6];
 788
 789     if ((slice_param->slice_type == SLICE_TYPE_P ||
 790          slice_param->slice_type == SLICE_TYPE_SP) &&
 791         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 792         num_weight_offset_table = 1;
 793     }
 794
 795     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 796         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 797         num_weight_offset_table = 2;
 798     }
 799
 800     for (i = 0; i < num_weight_offset_table; i++) {
 801         BEGIN_BCS_BATCH(batch, 98);
 802         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 803         OUT_BCS_BATCH(batch, i);
 804
 805         if (i == 0) {
 806             for (j = 0; j < 32; j++) {
 807                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 808                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 809                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 810                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 811                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 812                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 813             }
 814         } else {
 815             for (j = 0; j < 32; j++) {
 816                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 817                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 818                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 819                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 820                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 821                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 822             }
 823         }
 824
 825         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 826         ADVANCE_BCS_BATCH(batch);
 827     }
 828 }
 829
 830 static int
 831 gen75_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
 832 {
 833     int out_slice_data_bit_offset;
 834     int slice_header_size = in_slice_data_bit_offset / 8;
 835     int i, j;
 836
 837     for (i = 0, j = 0; i < slice_header_size; i++, j++) {
 838         if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
 839             i++, j += 2;
 840         }
 841     }
 842
 843     out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
 844
 845     if (mode_flag == ENTROPY_CABAC)
 846         out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
 847
 848     return out_slice_data_bit_offset;
 849 }
 850
 851 static void
 852 gen75_mfd_avc_bsd_object(VADriverContextP ctx,
 853                         VAPictureParameterBufferH264 *pic_param,
 854                         VASliceParameterBufferH264 *slice_param,
 855                         dri_bo *slice_data_bo,
 856                         VASliceParameterBufferH264 *next_slice_param,
 857                         struct gen7_mfd_context *gen7_mfd_context)
 858 {
 859     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 860     int slice_data_bit_offset;
 861     uint8_t *slice_data = NULL;
 862
 863     dri_bo_map(slice_data_bo, 0);
 864     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
 865     slice_data_bit_offset = gen75_mfd_avc_get_slice_bit_offset(slice_data,
 866                                                               pic_param->pic_fields.bits.entropy_coding_mode_flag,
 867                                                               slice_param->slice_data_bit_offset);
 868     dri_bo_unmap(slice_data_bo);
 869
 870     /* the input bitsteam format on GEN7 differs from GEN6 */
 871     BEGIN_BCS_BATCH(batch, 6);
 872     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 873     OUT_BCS_BATCH(batch,
 874                   (slice_param->slice_data_size));
 875     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 876     OUT_BCS_BATCH(batch,
 877                   (0 << 31) |
 878                   (0 << 14) |
 879                   (0 << 12) |
 880                   (0 << 10) |
 881                   (0 << 8));
 882     OUT_BCS_BATCH(batch,
 883                   ((slice_data_bit_offset >> 3) << 16) |
 884                   (0 << 5)  |
 885                   (0 << 4)  |
 886                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
 887                   (slice_data_bit_offset & 0x7));
 888     OUT_BCS_BATCH(batch, 0);
 889     ADVANCE_BCS_BATCH(batch);
 890 }
 891
 892 static inline void
 893 gen75_mfd_avc_context_init(
 894     VADriverContextP         ctx,
 895     struct gen7_mfd_context *gen7_mfd_context
 896 )
 897 {
 898     /* Initialize flat scaling lists */
 899     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
 900 }
 901
 902 static void
 903 gen75_mfd_avc_decode_init(VADriverContextP ctx,
 904                          struct decode_state *decode_state,
 905                          struct gen7_mfd_context *gen7_mfd_context)
 906 {
 907     VAPictureParameterBufferH264 *pic_param;
 908     VASliceParameterBufferH264 *slice_param;
 909     VAPictureH264 *va_pic;
 910     struct i965_driver_data *i965 = i965_driver_data(ctx);
 911     struct object_surface *obj_surface;
 912     dri_bo *bo;
 913     int i, j, enable_avc_ildb = 0;
 914     unsigned int width_in_mbs, height_in_mbs;
 915
 916     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 917         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 918         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 919
 920         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 921             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 922             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 923                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 924                    (slice_param->slice_type == SLICE_TYPE_P) ||
 925                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 926                    (slice_param->slice_type == SLICE_TYPE_B));
 927
 928             if (slice_param->disable_deblocking_filter_idc != 1) {
 929                 enable_avc_ildb = 1;
 930                 break;
 931             }
 932
 933             slice_param++;
 934         }
 935     }
 936
 937     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 938     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 939     gen75_mfd_avc_frame_store_index(ctx, pic_param, gen7_mfd_context);
 940     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 941     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 942     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
 943     assert(height_in_mbs > 0 && height_in_mbs <= 256);
 944
 945     /* Current decoded picture */
 946     va_pic = &pic_param->CurrPic;
 947     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 948     obj_surface = SURFACE(va_pic->picture_id);
 949     assert(obj_surface);
 950     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
 951     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
 952     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 953     gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 954
 955     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
 956     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 957     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
 958     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 959
 960     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
 961     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 962     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
 963     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 964
 965     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
 966     bo = dri_bo_alloc(i965->intel.bufmgr,
 967                       "intra row store",
 968                       width_in_mbs * 64,
 969                       0x1000);
 970     assert(bo);
 971     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 972     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 973
 974     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 975     bo = dri_bo_alloc(i965->intel.bufmgr,
 976                       "deblocking filter row store",
 977                       width_in_mbs * 64 * 4,
 978                       0x1000);
 979     assert(bo);
 980     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 981     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 982
 983     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 984     bo = dri_bo_alloc(i965->intel.bufmgr,
 985                       "bsd mpc row store",
 986                       width_in_mbs * 64 * 2,
 987                       0x1000);
 988     assert(bo);
 989     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 990     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 991
 992     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
 993     bo = dri_bo_alloc(i965->intel.bufmgr,
 994                       "mpr row store",
 995                       width_in_mbs * 64 * 2,
 996                       0x1000);
 997     assert(bo);
 998     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 999     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1000
1001     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1002 }
1003
1004 static void
1005 gen75_mfd_avc_decode_picture(VADriverContextP ctx,
1006                             struct decode_state *decode_state,
1007                             struct gen7_mfd_context *gen7_mfd_context)
1008 {
1009     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1010     VAPictureParameterBufferH264 *pic_param;
1011     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1012     dri_bo *slice_data_bo;
1013     int i, j;
1014
1015     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1016     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1017     gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
1018
1019     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1020     intel_batchbuffer_emit_mi_flush(batch);
1021     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1022     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1023     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1024     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1025     gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
1026     gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1027
1028     for (j = 0; j < decode_state->num_slice_params; j++) {
1029         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1030         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1031         slice_data_bo = decode_state->slice_datas[j]->bo;
1032         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1033
1034         if (j == decode_state->num_slice_params - 1)
1035             next_slice_group_param = NULL;
1036         else
1037             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1038
1039         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1040             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1041             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1042                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1043                    (slice_param->slice_type == SLICE_TYPE_P) ||
1044                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1045                    (slice_param->slice_type == SLICE_TYPE_B));
1046
1047             if (i < decode_state->slice_params[j]->num_elements - 1)
1048                 next_slice_param = slice_param + 1;
1049             else
1050                 next_slice_param = next_slice_group_param;
1051
1052             gen75_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen7_mfd_context);
1053             gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1054             gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1055             gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1056             gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1057             slice_param++;
1058         }
1059     }
1060
1061     intel_batchbuffer_end_atomic(batch);
1062     intel_batchbuffer_flush(batch);
1063 }
1064
1065 static void
1066 gen75_mfd_mpeg2_decode_init(VADriverContextP ctx,
1067                            struct decode_state *decode_state,
1068                            struct gen7_mfd_context *gen7_mfd_context)
1069 {
1070     VAPictureParameterBufferMPEG2 *pic_param;
1071     struct i965_driver_data *i965 = i965_driver_data(ctx);
1072     struct object_surface *obj_surface;
1073     dri_bo *bo;
1074     unsigned int width_in_mbs;
1075
1076     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1077     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1078     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1079
1080     mpeg2_set_reference_surfaces(
1081         ctx,
1082         gen7_mfd_context->reference_surface,
1083         decode_state,
1084         pic_param
1085     );
1086
1087     /* Current decoded picture */
1088     obj_surface = SURFACE(decode_state->current_render_target);
1089     assert(obj_surface);
1090     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1091
1092     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1093     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1094     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1095     gen7_mfd_context->pre_deblocking_output.valid = 1;
1096
1097     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1098     bo = dri_bo_alloc(i965->intel.bufmgr,
1099                       "bsd mpc row store",
1100                       width_in_mbs * 96,
1101                       0x1000);
1102     assert(bo);
1103     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1104     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1105
1106     gen7_mfd_context->post_deblocking_output.valid = 0;
1107     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1108     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1109     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1110     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1111 }
1112
1113 static void
1114 gen75_mfd_mpeg2_pic_state(VADriverContextP ctx,
1115                          struct decode_state *decode_state,
1116                          struct gen7_mfd_context *gen7_mfd_context)
1117 {
1118     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1119     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1120     VAPictureParameterBufferMPEG2 *pic_param;
1121     unsigned int slice_concealment_disable_bit = 0;
1122
1123     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1124     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1125
1126     slice_concealment_disable_bit = 1;
1127
1128     BEGIN_BCS_BATCH(batch, 13);
1129     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1130     OUT_BCS_BATCH(batch,
1131                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1132                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1133                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1134                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1135                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1136                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1137                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
1138                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1139                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1140                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1141                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1142                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1143     OUT_BCS_BATCH(batch,
1144                   pic_param->picture_coding_type << 9);
1145     OUT_BCS_BATCH(batch,
1146                   (slice_concealment_disable_bit << 31) |
1147                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1148                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1149     OUT_BCS_BATCH(batch, 0);
1150     OUT_BCS_BATCH(batch, 0);
1151     OUT_BCS_BATCH(batch, 0);
1152     OUT_BCS_BATCH(batch, 0);
1153     OUT_BCS_BATCH(batch, 0);
1154     OUT_BCS_BATCH(batch, 0);
1155     OUT_BCS_BATCH(batch, 0);
1156     OUT_BCS_BATCH(batch, 0);
1157     OUT_BCS_BATCH(batch, 0);
1158     ADVANCE_BCS_BATCH(batch);
1159 }
1160
1161 static void
1162 gen75_mfd_mpeg2_qm_state(VADriverContextP ctx,
1163                         struct decode_state *decode_state,
1164                         struct gen7_mfd_context *gen7_mfd_context)
1165 {
1166     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1167     int i, j;
1168
1169     /* Update internal QM state */
1170     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1171         VAIQMatrixBufferMPEG2 * const iq_matrix =
1172             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1173
1174         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1175             iq_matrix->load_intra_quantiser_matrix) {
1176             gen_iq_matrix->load_intra_quantiser_matrix =
1177                 iq_matrix->load_intra_quantiser_matrix;
1178             if (iq_matrix->load_intra_quantiser_matrix) {
1179                 for (j = 0; j < 64; j++)
1180                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1181                         iq_matrix->intra_quantiser_matrix[j];
1182             }
1183         }
1184
1185         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1186             iq_matrix->load_non_intra_quantiser_matrix) {
1187             gen_iq_matrix->load_non_intra_quantiser_matrix =
1188                 iq_matrix->load_non_intra_quantiser_matrix;
1189             if (iq_matrix->load_non_intra_quantiser_matrix) {
1190                 for (j = 0; j < 64; j++)
1191                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1192                         iq_matrix->non_intra_quantiser_matrix[j];
1193             }
1194         }
1195     }
1196
1197     /* Commit QM state to HW */
1198     for (i = 0; i < 2; i++) {
1199         unsigned char *qm = NULL;
1200         int qm_type;
1201
1202         if (i == 0) {
1203             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1204                 qm = gen_iq_matrix->intra_quantiser_matrix;
1205                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1206             }
1207         } else {
1208             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1209                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1210                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1211             }
1212         }
1213
1214         if (!qm)
1215             continue;
1216
1217         gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1218     }
1219 }
1220
1221 static void
1222 gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1223                           VAPictureParameterBufferMPEG2 *pic_param,
1224                           VASliceParameterBufferMPEG2 *slice_param,
1225                           VASliceParameterBufferMPEG2 *next_slice_param,
1226                           struct gen7_mfd_context *gen7_mfd_context)
1227 {
1228     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1229     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1230     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1231     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1232
1233     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1234         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1235         is_field_pic = 1;
1236     is_field_pic_wa = is_field_pic &&
1237         gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1238
1239     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1240     hpos0 = slice_param->slice_horizontal_position;
1241
1242     if (next_slice_param == NULL) {
1243         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1244         hpos1 = 0;
1245     } else {
1246         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1247         hpos1 = next_slice_param->slice_horizontal_position;
1248     }
1249
1250     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1251
1252     BEGIN_BCS_BATCH(batch, 5);
1253     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1254     OUT_BCS_BATCH(batch,
1255                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1256     OUT_BCS_BATCH(batch,
1257                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1258     OUT_BCS_BATCH(batch,
1259                   hpos0 << 24 |
1260                   vpos0 << 16 |
1261                   mb_count << 8 |
1262                   (next_slice_param == NULL) << 5 |
1263                   (next_slice_param == NULL) << 3 |
1264                   (slice_param->macroblock_offset & 0x7));
1265     OUT_BCS_BATCH(batch,
1266                   (slice_param->quantiser_scale_code << 24) |
1267                   (vpos1 << 8 | hpos1));
1268     ADVANCE_BCS_BATCH(batch);
1269 }
1270
1271 static void
1272 gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1273                               struct decode_state *decode_state,
1274                               struct gen7_mfd_context *gen7_mfd_context)
1275 {
1276     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1277     VAPictureParameterBufferMPEG2 *pic_param;
1278     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1279     dri_bo *slice_data_bo;
1280     int i, j;
1281
1282     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1283     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1284
1285     gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1286     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1287     intel_batchbuffer_emit_mi_flush(batch);
1288     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1289     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1290     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1291     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1292     gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1293     gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1294
1295     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1296         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1297             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1298
1299     for (j = 0; j < decode_state->num_slice_params; j++) {
1300         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1301         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1302         slice_data_bo = decode_state->slice_datas[j]->bo;
1303         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1304
1305         if (j == decode_state->num_slice_params - 1)
1306             next_slice_group_param = NULL;
1307         else
1308             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1309
1310         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1311             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1312
1313             if (i < decode_state->slice_params[j]->num_elements - 1)
1314                 next_slice_param = slice_param + 1;
1315             else
1316                 next_slice_param = next_slice_group_param;
1317
1318             gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1319             slice_param++;
1320         }
1321     }
1322
1323     intel_batchbuffer_end_atomic(batch);
1324     intel_batchbuffer_flush(batch);
1325 }
1326
1327 static const int va_to_gen7_vc1_pic_type[5] = {
1328     GEN7_VC1_I_PICTURE,
1329     GEN7_VC1_P_PICTURE,
1330     GEN7_VC1_B_PICTURE,
1331     GEN7_VC1_BI_PICTURE,
1332     GEN7_VC1_P_PICTURE,
1333 };
1334
1335 static const int va_to_gen7_vc1_mv[4] = {
1336     1, /* 1-MV */
1337     2, /* 1-MV half-pel */
1338     3, /* 1-MV half-pef bilinear */
1339     0, /* Mixed MV */
1340 };
1341
1342 static const int b_picture_scale_factor[21] = {
1343     128, 85,  170, 64,  192,
1344     51,  102, 153, 204, 43,
1345     215, 37,  74,  111, 148,
1346     185, 222, 32,  96,  160,
1347     224,
1348 };
1349
1350 static const int va_to_gen7_vc1_condover[3] = {
1351     0,
1352     2,
1353     3
1354 };
1355
1356 static const int va_to_gen7_vc1_profile[4] = {
1357     GEN7_VC1_SIMPLE_PROFILE,
1358     GEN7_VC1_MAIN_PROFILE,
1359     GEN7_VC1_RESERVED_PROFILE,
1360     GEN7_VC1_ADVANCED_PROFILE
1361 };
1362
1363 static void
1364 gen75_mfd_free_vc1_surface(void **data)
1365 {
1366     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1367
1368     if (!gen7_vc1_surface)
1369         return;
1370
1371     dri_bo_unreference(gen7_vc1_surface->dmv);
1372     free(gen7_vc1_surface);
1373     *data = NULL;
1374 }
1375
1376 static void
1377 gen75_mfd_init_vc1_surface(VADriverContextP ctx,
1378                           VAPictureParameterBufferVC1 *pic_param,
1379                           struct object_surface *obj_surface)
1380 {
1381     struct i965_driver_data *i965 = i965_driver_data(ctx);
1382     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1383     int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1384     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1385
1386     obj_surface->free_private_data = gen75_mfd_free_vc1_surface;
1387
1388     if (!gen7_vc1_surface) {
1389         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1390         assert((obj_surface->size & 0x3f) == 0);
1391         obj_surface->private_data = gen7_vc1_surface;
1392     }
1393
1394     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1395
1396     if (gen7_vc1_surface->dmv == NULL) {
1397         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1398                                              "direct mv w/r buffer",
1399                                              width_in_mbs * height_in_mbs * 64,
1400                                              0x1000);
1401     }
1402 }
1403
1404 static void
1405 gen75_mfd_vc1_decode_init(VADriverContextP ctx,
1406                          struct decode_state *decode_state,
1407                          struct gen7_mfd_context *gen7_mfd_context)
1408 {
1409     VAPictureParameterBufferVC1 *pic_param;
1410     struct i965_driver_data *i965 = i965_driver_data(ctx);
1411     struct object_surface *obj_surface;
1412     int i;
1413     dri_bo *bo;
1414     int width_in_mbs;
1415
1416     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1417     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1418     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1419
1420     /* reference picture */
1421     obj_surface = SURFACE(pic_param->forward_reference_picture);
1422
1423     if (obj_surface && obj_surface->bo)
1424         gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1425     else
1426         gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1427
1428     obj_surface = SURFACE(pic_param->backward_reference_picture);
1429
1430     if (obj_surface && obj_surface->bo)
1431         gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1432     else
1433         gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1434
1435     /* must do so !!! */
1436     for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1437         gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1438
1439     /* Current decoded picture */
1440     obj_surface = SURFACE(decode_state->current_render_target);
1441     assert(obj_surface);
1442     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1443     gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1444
1445     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1446     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1447     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1448     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1449
1450     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1451     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1452     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1453     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1454
1455     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1456     bo = dri_bo_alloc(i965->intel.bufmgr,
1457                       "intra row store",
1458                       width_in_mbs * 64,
1459                       0x1000);
1460     assert(bo);
1461     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1462     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1463
1464     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1465     bo = dri_bo_alloc(i965->intel.bufmgr,
1466                       "deblocking filter row store",
1467                       width_in_mbs * 6 * 64,
1468                       0x1000);
1469     assert(bo);
1470     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1471     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1472
1473     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1474     bo = dri_bo_alloc(i965->intel.bufmgr,
1475                       "bsd mpc row store",
1476                       width_in_mbs * 96,
1477                       0x1000);
1478     assert(bo);
1479     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1480     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1481
1482     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1483
1484     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1485     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1486
1487     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1488         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1489         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1490         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1491         int src_w, src_h;
1492         uint8_t *src = NULL, *dst = NULL;
1493
1494         assert(decode_state->bit_plane->buffer);
1495         src = decode_state->bit_plane->buffer;
1496
1497         bo = dri_bo_alloc(i965->intel.bufmgr,
1498                           "VC-1 Bitplane",
1499                           bitplane_width * bitplane_width,
1500                           0x1000);
1501         assert(bo);
1502         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1503
1504         dri_bo_map(bo, True);
1505         assert(bo->virtual);
1506         dst = bo->virtual;
1507
1508         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1509             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1510                 int src_index, dst_index;
1511                 int src_shift;
1512                 uint8_t src_value;
1513
1514                 src_index = (src_h * width_in_mbs + src_w) / 2;
1515                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1516                 src_value = ((src[src_index] >> src_shift) & 0xf);
1517
1518                 dst_index = src_w / 2;
1519                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1520             }
1521
1522             if (src_w & 1)
1523                 dst[src_w / 2] >>= 4;
1524
1525             dst += bitplane_width;
1526         }
1527
1528         dri_bo_unmap(bo);
1529     } else
1530         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1531 }
1532
1533 static void
1534 gen75_mfd_vc1_pic_state(VADriverContextP ctx,
1535                        struct decode_state *decode_state,
1536                        struct gen7_mfd_context *gen7_mfd_context)
1537 {
1538     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1539     VAPictureParameterBufferVC1 *pic_param;
1540     struct i965_driver_data *i965 = i965_driver_data(ctx);
1541     struct object_surface *obj_surface;
1542     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1543     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1544     int unified_mv_mode;
1545     int ref_field_pic_polarity = 0;
1546     int scale_factor = 0;
1547     int trans_ac_y = 0;
1548     int dmv_surface_valid = 0;
1549     int brfd = 0;
1550     int fcm = 0;
1551     int picture_type;
1552     int profile;
1553     int overlap;
1554     int interpolation_mode = 0;
1555
1556     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1557     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1558
1559     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1560     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1561     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1562     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1563     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1564     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1565     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1566     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1567
1568     if (dquant == 0) {
1569         alt_pquant_config = 0;
1570         alt_pquant_edge_mask = 0;
1571     } else if (dquant == 2) {
1572         alt_pquant_config = 1;
1573         alt_pquant_edge_mask = 0xf;
1574     } else {
1575         assert(dquant == 1);
1576         if (dquantfrm == 0) {
1577             alt_pquant_config = 0;
1578             alt_pquant_edge_mask = 0;
1579             alt_pq = 0;
1580         } else {
1581             assert(dquantfrm == 1);
1582             alt_pquant_config = 1;
1583
1584             switch (dqprofile) {
1585             case 3:
1586                 if (dqbilevel == 0) {
1587                     alt_pquant_config = 2;
1588                     alt_pquant_edge_mask = 0;
1589                 } else {
1590                     assert(dqbilevel == 1);
1591                     alt_pquant_config = 3;
1592                     alt_pquant_edge_mask = 0;
1593                 }
1594                 break;
1595
1596             case 0:
1597                 alt_pquant_edge_mask = 0xf;
1598                 break;
1599
1600             case 1:
1601                 if (dqdbedge == 3)
1602                     alt_pquant_edge_mask = 0x9;
1603                 else
1604                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1605
1606                 break;
1607
1608             case 2:
1609                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1610                 break;
1611
1612             default:
1613                 assert(0);
1614             }
1615         }
1616     }
1617
1618     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1619         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1620         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1621     } else {
1622         assert(pic_param->mv_fields.bits.mv_mode < 4);
1623         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1624     }
1625
1626     if (pic_param->sequence_fields.bits.interlace == 1 &&
1627         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1628         /* FIXME: calculate reference field picture polarity */
1629         assert(0);
1630         ref_field_pic_polarity = 0;
1631     }
1632
1633     if (pic_param->b_picture_fraction < 21)
1634         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1635
1636     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1637
1638     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1639         picture_type == GEN7_VC1_I_PICTURE)
1640         picture_type = GEN7_VC1_BI_PICTURE;
1641
1642     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1643         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1644     else
1645         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1646
1647
1648     if (picture_type == GEN7_VC1_B_PICTURE) {
1649         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1650
1651         obj_surface = SURFACE(pic_param->backward_reference_picture);
1652         assert(obj_surface);
1653         gen7_vc1_surface = obj_surface->private_data;
1654
1655         if (!gen7_vc1_surface ||
1656             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1657              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1658             dmv_surface_valid = 0;
1659         else
1660             dmv_surface_valid = 1;
1661     }
1662
1663     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1664
1665     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1666         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1667     else {
1668         if (pic_param->picture_fields.bits.top_field_first)
1669             fcm = 2;
1670         else
1671             fcm = 3;
1672     }
1673
1674     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1675         brfd = pic_param->reference_fields.bits.reference_distance;
1676         brfd = (scale_factor * brfd) >> 8;
1677         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1678
1679         if (brfd < 0)
1680             brfd = 0;
1681     }
1682
1683     overlap = pic_param->sequence_fields.bits.overlap;
1684     if (profile != GEN7_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
1685         overlap = 0;
1686
1687     assert(pic_param->conditional_overlap_flag < 3);
1688     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1689
1690     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1691         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1692          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1693         interpolation_mode = 9; /* Half-pel bilinear */
1694     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1695              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1696               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1697         interpolation_mode = 1; /* Half-pel bicubic */
1698     else
1699         interpolation_mode = 0; /* Quarter-pel bicubic */
1700
1701     BEGIN_BCS_BATCH(batch, 6);
1702     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1703     OUT_BCS_BATCH(batch,
1704                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1705                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1706     OUT_BCS_BATCH(batch,
1707                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1708                   dmv_surface_valid << 15 |
1709                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1710                   pic_param->rounding_control << 13 |
1711                   pic_param->sequence_fields.bits.syncmarker << 12 |
1712                   interpolation_mode << 8 |
1713                   0 << 7 | /* FIXME: scale up or down ??? */
1714                   pic_param->range_reduction_frame << 6 |
1715                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
1716                   overlap << 4 |
1717                   !pic_param->picture_fields.bits.is_first_field << 3 |
1718                   (pic_param->sequence_fields.bits.profile == 3) << 0);
1719     OUT_BCS_BATCH(batch,
1720                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1721                   picture_type << 26 |
1722                   fcm << 24 |
1723                   alt_pq << 16 |
1724                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1725                   scale_factor << 0);
1726     OUT_BCS_BATCH(batch,
1727                   unified_mv_mode << 28 |
1728                   pic_param->mv_fields.bits.four_mv_switch << 27 |
1729                   pic_param->fast_uvmc_flag << 26 |
1730                   ref_field_pic_polarity << 25 |
1731                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
1732                   pic_param->reference_fields.bits.reference_distance << 20 |
1733                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1734                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
1735                   pic_param->mv_fields.bits.extended_mv_range << 8 |
1736                   alt_pquant_edge_mask << 4 |
1737                   alt_pquant_config << 2 |
1738                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1739                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1740     OUT_BCS_BATCH(batch,
1741                   !!pic_param->bitplane_present.value << 31 |
1742                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
1743                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
1744                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
1745                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
1746                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
1747                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
1748                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
1749                   pic_param->mv_fields.bits.mv_table << 20 |
1750                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1751                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1752                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1753                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1754                   pic_param->mb_mode_table << 8 |
1755                   trans_ac_y << 6 |
1756                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1757                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1758                   pic_param->cbp_table << 0);
1759     ADVANCE_BCS_BATCH(batch);
1760 }
1761
1762 static void
1763 gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1764                              struct decode_state *decode_state,
1765                              struct gen7_mfd_context *gen7_mfd_context)
1766 {
1767     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1768     VAPictureParameterBufferVC1 *pic_param;
1769     int intensitycomp_single;
1770
1771     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1772     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1773
1774     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1775     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1776     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1777
1778     BEGIN_BCS_BATCH(batch, 6);
1779     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1780     OUT_BCS_BATCH(batch,
1781                   0 << 14 | /* FIXME: double ??? */
1782                   0 << 12 |
1783                   intensitycomp_single << 10 |
1784                   intensitycomp_single << 8 |
1785                   0 << 4 | /* FIXME: interlace mode */
1786                   0);
1787     OUT_BCS_BATCH(batch,
1788                   pic_param->luma_shift << 16 |
1789                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1790     OUT_BCS_BATCH(batch, 0);
1791     OUT_BCS_BATCH(batch, 0);
1792     OUT_BCS_BATCH(batch, 0);
1793     ADVANCE_BCS_BATCH(batch);
1794 }
1795
1796
1797 static void
1798 gen75_mfd_vc1_directmode_state(VADriverContextP ctx,
1799                               struct decode_state *decode_state,
1800                               struct gen7_mfd_context *gen7_mfd_context)
1801 {
1802     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1803     VAPictureParameterBufferVC1 *pic_param;
1804     struct i965_driver_data *i965 = i965_driver_data(ctx);
1805     struct object_surface *obj_surface;
1806     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1807
1808     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1809     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1810
1811     obj_surface = SURFACE(decode_state->current_render_target);
1812
1813     if (obj_surface && obj_surface->private_data) {
1814         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1815     }
1816
1817     obj_surface = SURFACE(pic_param->backward_reference_picture);
1818
1819     if (obj_surface && obj_surface->private_data) {
1820         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1821     }
1822
1823     BEGIN_BCS_BATCH(batch, 3);
1824     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1825
1826     if (dmv_write_buffer)
1827         OUT_BCS_RELOC(batch, dmv_write_buffer,
1828                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1829                       0);
1830     else
1831         OUT_BCS_BATCH(batch, 0);
1832
1833     if (dmv_read_buffer)
1834         OUT_BCS_RELOC(batch, dmv_read_buffer,
1835                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1836                       0);
1837     else
1838         OUT_BCS_BATCH(batch, 0);
1839
1840     ADVANCE_BCS_BATCH(batch);
1841 }
1842
1843 static int
1844 gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1845 {
1846     int out_slice_data_bit_offset;
1847     int slice_header_size = in_slice_data_bit_offset / 8;
1848     int i, j;
1849
1850     if (profile != 3)
1851         out_slice_data_bit_offset = in_slice_data_bit_offset;
1852     else {
1853         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1854             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1855                 i++, j += 2;
1856             }
1857         }
1858
1859         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1860     }
1861
1862     return out_slice_data_bit_offset;
1863 }
1864
1865 static void
1866 gen75_mfd_vc1_bsd_object(VADriverContextP ctx,
1867                         VAPictureParameterBufferVC1 *pic_param,
1868                         VASliceParameterBufferVC1 *slice_param,
1869                         VASliceParameterBufferVC1 *next_slice_param,
1870                         dri_bo *slice_data_bo,
1871                         struct gen7_mfd_context *gen7_mfd_context)
1872 {
1873     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1874     int next_slice_start_vert_pos;
1875     int macroblock_offset;
1876     uint8_t *slice_data = NULL;
1877
1878     dri_bo_map(slice_data_bo, 0);
1879     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1880     macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data,
1881                                                                slice_param->macroblock_offset,
1882                                                                pic_param->sequence_fields.bits.profile);
1883     dri_bo_unmap(slice_data_bo);
1884
1885     if (next_slice_param)
1886         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1887     else
1888         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1889
1890     BEGIN_BCS_BATCH(batch, 5);
1891     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
1892     OUT_BCS_BATCH(batch,
1893                   slice_param->slice_data_size - (macroblock_offset >> 3));
1894     OUT_BCS_BATCH(batch,
1895                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1896     OUT_BCS_BATCH(batch,
1897                   slice_param->slice_vertical_position << 16 |
1898                   next_slice_start_vert_pos << 0);
1899     OUT_BCS_BATCH(batch,
1900                   (macroblock_offset & 0x7));
1901     ADVANCE_BCS_BATCH(batch);
1902 }
1903
1904 static void
1905 gen75_mfd_vc1_decode_picture(VADriverContextP ctx,
1906                             struct decode_state *decode_state,
1907                             struct gen7_mfd_context *gen7_mfd_context)
1908 {
1909     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1910     VAPictureParameterBufferVC1 *pic_param;
1911     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1912     dri_bo *slice_data_bo;
1913     int i, j;
1914
1915     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1916     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1917
1918     gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
1919     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1920     intel_batchbuffer_emit_mi_flush(batch);
1921     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1922     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1923     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1924     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
1925     gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
1926     gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
1927     gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
1928
1929     for (j = 0; j < decode_state->num_slice_params; j++) {
1930         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1931         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1932         slice_data_bo = decode_state->slice_datas[j]->bo;
1933         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
1934
1935         if (j == decode_state->num_slice_params - 1)
1936             next_slice_group_param = NULL;
1937         else
1938             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1939
1940         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1941             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1942
1943             if (i < decode_state->slice_params[j]->num_elements - 1)
1944                 next_slice_param = slice_param + 1;
1945             else
1946                 next_slice_param = next_slice_group_param;
1947
1948             gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
1949             slice_param++;
1950         }
1951     }
1952
1953     intel_batchbuffer_end_atomic(batch);
1954     intel_batchbuffer_flush(batch);
1955 }
1956
1957 static void
1958 gen75_mfd_jpeg_decode_init(VADriverContextP ctx,
1959                           struct decode_state *decode_state,
1960                           struct gen7_mfd_context *gen7_mfd_context)
1961 {
1962     struct i965_driver_data *i965 = i965_driver_data(ctx);
1963     struct object_surface *obj_surface;
1964     VAPictureParameterBufferJPEGBaseline *pic_param;
1965     int subsampling = SUBSAMPLE_YUV420;
1966
1967     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
1968
1969     if (pic_param->num_components == 1)
1970         subsampling = SUBSAMPLE_YUV400;
1971     else if (pic_param->num_components == 3) {
1972         int h1 = pic_param->components[0].h_sampling_factor;
1973         int h2 = pic_param->components[1].h_sampling_factor;
1974         int h3 = pic_param->components[2].h_sampling_factor;
1975         int v1 = pic_param->components[0].v_sampling_factor;
1976         int v2 = pic_param->components[1].v_sampling_factor;
1977         int v3 = pic_param->components[2].v_sampling_factor;
1978
1979         if (h1 == 2 && h2 == 1 && h3 == 1 &&
1980             v1 == 2 && v2 == 1 && v3 == 1)
1981             subsampling = SUBSAMPLE_YUV420;
1982         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1983                  v1 == 1 && v2 == 1 && v3 == 1)
1984             subsampling = SUBSAMPLE_YUV422H;
1985         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1986                  v1 == 1 && v2 == 1 && v3 == 1)
1987             subsampling = SUBSAMPLE_YUV444;
1988         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
1989                  v1 == 1 && v2 == 1 && v3 == 1)
1990             subsampling = SUBSAMPLE_YUV411;
1991         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
1992                  v1 == 2 && v2 == 1 && v3 == 1)
1993             subsampling = SUBSAMPLE_YUV422V;
1994         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
1995                  v1 == 2 && v2 == 2 && v3 == 2)
1996             subsampling = SUBSAMPLE_YUV422H;
1997         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
1998                  v1 == 2 && v2 == 1 && v3 == 1)
1999             subsampling = SUBSAMPLE_YUV422V;
2000         else
2001             assert(0);
2002     } else {
2003         assert(0);
2004     }
2005
2006     /* Current decoded picture */
2007     obj_surface = SURFACE(decode_state->current_render_target);
2008     assert(obj_surface);
2009     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('I','M','C','1'), subsampling);
2010
2011     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2012     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2013     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2014     gen7_mfd_context->pre_deblocking_output.valid = 1;
2015
2016     gen7_mfd_context->post_deblocking_output.bo = NULL;
2017     gen7_mfd_context->post_deblocking_output.valid = 0;
2018
2019     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2020     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2021
2022     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2023     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2024
2025     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2026     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2027
2028     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2029     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2030
2031     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2032     gen7_mfd_context->bitplane_read_buffer.valid = 0;
2033 }
2034
2035 static const int va_to_gen7_jpeg_rotation[4] = {
2036     GEN7_JPEG_ROTATION_0,
2037     GEN7_JPEG_ROTATION_90,
2038     GEN7_JPEG_ROTATION_180,
2039     GEN7_JPEG_ROTATION_270
2040 };
2041
2042 static void
2043 gen75_mfd_jpeg_pic_state(VADriverContextP ctx,
2044                         struct decode_state *decode_state,
2045                         struct gen7_mfd_context *gen7_mfd_context)
2046 {
2047     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2048     VAPictureParameterBufferJPEGBaseline *pic_param;
2049     int chroma_type = GEN7_YUV420;
2050     int frame_width_in_blks;
2051     int frame_height_in_blks;
2052
2053     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2054     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2055
2056     if (pic_param->num_components == 1)
2057         chroma_type = GEN7_YUV400;
2058     else if (pic_param->num_components == 3) {
2059         int h1 = pic_param->components[0].h_sampling_factor;
2060         int h2 = pic_param->components[1].h_sampling_factor;
2061         int h3 = pic_param->components[2].h_sampling_factor;
2062         int v1 = pic_param->components[0].v_sampling_factor;
2063         int v2 = pic_param->components[1].v_sampling_factor;
2064         int v3 = pic_param->components[2].v_sampling_factor;
2065
2066         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2067             v1 == 2 && v2 == 1 && v3 == 1)
2068             chroma_type = GEN7_YUV420;
2069         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2070                  v1 == 1 && v2 == 1 && v3 == 1)
2071             chroma_type = GEN7_YUV422H_2Y;
2072         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2073                  v1 == 1 && v2 == 1 && v3 == 1)
2074             chroma_type = GEN7_YUV444;
2075         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2076                  v1 == 1 && v2 == 1 && v3 == 1)
2077             chroma_type = GEN7_YUV411;
2078         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2079                  v1 == 2 && v2 == 1 && v3 == 1)
2080             chroma_type = GEN7_YUV422V_2Y;
2081         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2082                  v1 == 2 && v2 == 2 && v3 == 2)
2083             chroma_type = GEN7_YUV422H_4Y;
2084         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2085                  v1 == 2 && v2 == 1 && v3 == 1)
2086             chroma_type = GEN7_YUV422V_4Y;
2087         else
2088             assert(0);
2089     }
2090
2091     if (chroma_type == GEN7_YUV400 ||
2092         chroma_type == GEN7_YUV444 ||
2093         chroma_type == GEN7_YUV422V_2Y) {
2094         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2095         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2096     } else if (chroma_type == GEN7_YUV411) {
2097         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2098         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2099     } else {
2100         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2101         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2102     }
2103
2104     BEGIN_BCS_BATCH(batch, 3);
2105     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2106     OUT_BCS_BATCH(batch,
2107                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2108                   (chroma_type << 0));
2109     OUT_BCS_BATCH(batch,
2110                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2111                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2112     ADVANCE_BCS_BATCH(batch);
2113 }
2114
2115 static const int va_to_gen7_jpeg_hufftable[2] = {
2116     MFX_HUFFTABLE_ID_Y,
2117     MFX_HUFFTABLE_ID_UV
2118 };
2119
2120 static void
2121 gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2122                                struct decode_state *decode_state,
2123                                struct gen7_mfd_context *gen7_mfd_context,
2124                                int num_tables)
2125 {
2126     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2127     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2128     int index;
2129
2130     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2131         return;
2132
2133     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2134
2135     for (index = 0; index < num_tables; index++) {
2136         int id = va_to_gen7_jpeg_hufftable[index];
2137         if (!huffman_table->load_huffman_table[index])
2138             continue;
2139         BEGIN_BCS_BATCH(batch, 53);
2140         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2141         OUT_BCS_BATCH(batch, id);
2142         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2143         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2144         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2145         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2146         ADVANCE_BCS_BATCH(batch);
2147     }
2148 }
2149
2150 static const int va_to_gen7_jpeg_qm[5] = {
2151     -1,
2152     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2153     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2154     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2155     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2156 };
2157
2158 static void
2159 gen75_mfd_jpeg_qm_state(VADriverContextP ctx,
2160                        struct decode_state *decode_state,
2161                        struct gen7_mfd_context *gen7_mfd_context)
2162 {
2163     VAPictureParameterBufferJPEGBaseline *pic_param;
2164     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2165     int index;
2166
2167     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2168         return;
2169
2170     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2171     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2172
2173     assert(pic_param->num_components <= 3);
2174
2175     for (index = 0; index < pic_param->num_components; index++) {
2176         int qm_type = va_to_gen7_jpeg_qm[pic_param->components[index].component_id - pic_param->components[0].component_id + 1];
2177         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2178         unsigned char raster_qm[64];
2179         int j;
2180
2181         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2182             continue;
2183
2184         for (j = 0; j < 64; j++)
2185             raster_qm[zigzag_direct[j]] = qm[j];
2186
2187         gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2188     }
2189 }
2190
2191 static void
2192 gen75_mfd_jpeg_bsd_object(VADriverContextP ctx,
2193                          VAPictureParameterBufferJPEGBaseline *pic_param,
2194                          VASliceParameterBufferJPEGBaseline *slice_param,
2195                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2196                          dri_bo *slice_data_bo,
2197                          struct gen7_mfd_context *gen7_mfd_context)
2198 {
2199     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2200     int scan_component_mask = 0;
2201     int i;
2202
2203     assert(slice_param->num_components > 0);
2204     assert(slice_param->num_components < 4);
2205     assert(slice_param->num_components <= pic_param->num_components);
2206
2207     for (i = 0; i < slice_param->num_components; i++) {
2208         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2209         case 1:
2210             scan_component_mask |= (1 << 0);
2211             break;
2212         case 2:
2213             scan_component_mask |= (1 << 1);
2214             break;
2215         case 3:
2216             scan_component_mask |= (1 << 2);
2217             break;
2218         default:
2219             assert(0);
2220             break;
2221         }
2222     }
2223
2224     BEGIN_BCS_BATCH(batch, 6);
2225     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2226     OUT_BCS_BATCH(batch,
2227                   slice_param->slice_data_size);
2228     OUT_BCS_BATCH(batch,
2229                   slice_param->slice_data_offset);
2230     OUT_BCS_BATCH(batch,
2231                   slice_param->slice_horizontal_position << 16 |
2232                   slice_param->slice_vertical_position << 0);
2233     OUT_BCS_BATCH(batch,
2234                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2235                   (scan_component_mask << 27) |                 /* scan components */
2236                   (0 << 26) |   /* disable interrupt allowed */
2237                   (slice_param->num_mcus << 0));                /* MCU count */
2238     OUT_BCS_BATCH(batch,
2239                   (slice_param->restart_interval << 0));    /* RestartInterval */
2240     ADVANCE_BCS_BATCH(batch);
2241 }
2242
2243 /* Workaround for JPEG decoding on Ivybridge */
2244
2245 VAStatus
2246 i965_DestroySurfaces(VADriverContextP ctx,
2247                      VASurfaceID *surface_list,
2248                      int num_surfaces);
2249 VAStatus
2250 i965_CreateSurfaces(VADriverContextP ctx,
2251                     int width,
2252                     int height,
2253                     int format,
2254                     int num_surfaces,
2255                     VASurfaceID *surfaces);
2256
2257 static struct {
2258     int width;
2259     int height;
2260     unsigned char data[32];
2261     int data_size;
2262     int data_bit_offset;
2263     int qp;
2264 } gen7_jpeg_wa_clip = {
2265     16,
2266     16,
2267     {
2268         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2269         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2270     },
2271     14,
2272     40,
2273     28,
2274 };
2275
2276 static void
2277 gen75_jpeg_wa_init(VADriverContextP ctx,
2278                   struct gen7_mfd_context *gen7_mfd_context)
2279 {
2280     struct i965_driver_data *i965 = i965_driver_data(ctx);
2281     VAStatus status;
2282     struct object_surface *obj_surface;
2283
2284     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2285         i965_DestroySurfaces(ctx,
2286                              &gen7_mfd_context->jpeg_wa_surface_id,
2287                              1);
2288
2289     status = i965_CreateSurfaces(ctx,
2290                                  gen7_jpeg_wa_clip.width,
2291                                  gen7_jpeg_wa_clip.height,
2292                                  VA_RT_FORMAT_YUV420,
2293                                  1,
2294                                  &gen7_mfd_context->jpeg_wa_surface_id);
2295     assert(status == VA_STATUS_SUCCESS);
2296
2297     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2298     assert(obj_surface);
2299     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
2300
2301     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2302         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2303                                                                "JPEG WA data",
2304                                                                0x1000,
2305                                                                0x1000);
2306         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2307                        0,
2308                        gen7_jpeg_wa_clip.data_size,
2309                        gen7_jpeg_wa_clip.data);
2310     }
2311 }
2312
2313 static void
2314 gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2315                               struct gen7_mfd_context *gen7_mfd_context)
2316 {
2317     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2318
2319     BEGIN_BCS_BATCH(batch, 5);
2320     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2321     OUT_BCS_BATCH(batch,
2322                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2323                   (MFD_MODE_VLD << 15) | /* VLD mode */
2324                   (0 << 10) | /* disable Stream-Out */
2325                   (0 << 9)  | /* Post Deblocking Output */
2326                   (1 << 8)  | /* Pre Deblocking Output */
2327                   (0 << 5)  | /* not in stitch mode */
2328                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2329                   (MFX_FORMAT_AVC << 0));
2330     OUT_BCS_BATCH(batch,
2331                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2332                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2333                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2334                   (0 << 1)  |
2335                   (0 << 0));
2336     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2337     OUT_BCS_BATCH(batch, 0); /* reserved */
2338     ADVANCE_BCS_BATCH(batch);
2339 }
2340
2341 static void
2342 gen75_jpeg_wa_surface_state(VADriverContextP ctx,
2343                            struct gen7_mfd_context *gen7_mfd_context)
2344 {
2345     struct i965_driver_data *i965 = i965_driver_data(ctx);
2346     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2347     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2348
2349     BEGIN_BCS_BATCH(batch, 6);
2350     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2351     OUT_BCS_BATCH(batch, 0);
2352     OUT_BCS_BATCH(batch,
2353                   ((obj_surface->orig_width - 1) << 18) |
2354                   ((obj_surface->orig_height - 1) << 4));
2355     OUT_BCS_BATCH(batch,
2356                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2357                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2358                   (0 << 22) | /* surface object control state, ignored */
2359                   ((obj_surface->width - 1) << 3) | /* pitch */
2360                   (0 << 2)  | /* must be 0 */
2361                   (1 << 1)  | /* must be tiled */
2362                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2363     OUT_BCS_BATCH(batch,
2364                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2365                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2366     OUT_BCS_BATCH(batch,
2367                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2368                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2369     ADVANCE_BCS_BATCH(batch);
2370 }
2371
2372 static void
2373 gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2374                                  struct gen7_mfd_context *gen7_mfd_context)
2375 {
2376     struct i965_driver_data *i965 = i965_driver_data(ctx);
2377     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2378     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2379     dri_bo *intra_bo;
2380     int i;
2381
2382     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2383                             "intra row store",
2384                             128 * 64,
2385                             0x1000);
2386
2387     BEGIN_BCS_BATCH(batch, 24);
2388     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
2389     OUT_BCS_RELOC(batch,
2390                   obj_surface->bo,
2391                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2392                   0);
2393
2394     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2395
2396     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2397     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2398
2399     OUT_BCS_RELOC(batch,
2400                   intra_bo,
2401                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2402                   0);
2403
2404     OUT_BCS_BATCH(batch, 0);
2405
2406     /* DW 7..22 */
2407     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2408         OUT_BCS_BATCH(batch, 0);
2409     }
2410
2411     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2412     ADVANCE_BCS_BATCH(batch);
2413
2414     dri_bo_unreference(intra_bo);
2415 }
2416
2417 static void
2418 gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2419                                      struct gen7_mfd_context *gen7_mfd_context)
2420 {
2421     struct i965_driver_data *i965 = i965_driver_data(ctx);
2422     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2423     dri_bo *bsd_mpc_bo, *mpr_bo;
2424
2425     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2426                               "bsd mpc row store",
2427                               11520, /* 1.5 * 120 * 64 */
2428                               0x1000);
2429
2430     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2431                           "mpr row store",
2432                           7680, /* 1. 0 * 120 * 64 */
2433                           0x1000);
2434
2435     BEGIN_BCS_BATCH(batch, 4);
2436     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2437
2438     OUT_BCS_RELOC(batch,
2439                   bsd_mpc_bo,
2440                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2441                   0);
2442
2443     OUT_BCS_RELOC(batch,
2444                   mpr_bo,
2445                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2446                   0);
2447     OUT_BCS_BATCH(batch, 0);
2448
2449     ADVANCE_BCS_BATCH(batch);
2450
2451     dri_bo_unreference(bsd_mpc_bo);
2452     dri_bo_unreference(mpr_bo);
2453 }
2454
2455 static void
2456 gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2457                           struct gen7_mfd_context *gen7_mfd_context)
2458 {
2459
2460 }
2461
2462 static void
2463 gen75_jpeg_wa_avc_img_state(VADriverContextP ctx,
2464                            struct gen7_mfd_context *gen7_mfd_context)
2465 {
2466     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2467     int img_struct = 0;
2468     int mbaff_frame_flag = 0;
2469     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2470
2471     BEGIN_BCS_BATCH(batch, 16);
2472     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2473     OUT_BCS_BATCH(batch,
2474                   width_in_mbs * height_in_mbs);
2475     OUT_BCS_BATCH(batch,
2476                   ((height_in_mbs - 1) << 16) |
2477                   ((width_in_mbs - 1) << 0));
2478     OUT_BCS_BATCH(batch,
2479                   (0 << 24) |
2480                   (0 << 16) |
2481                   (0 << 14) |
2482                   (0 << 13) |
2483                   (0 << 12) | /* differ from GEN6 */
2484                   (0 << 10) |
2485                   (img_struct << 8));
2486     OUT_BCS_BATCH(batch,
2487                   (1 << 10) | /* 4:2:0 */
2488                   (1 << 7) |  /* CABAC */
2489                   (0 << 6) |
2490                   (0 << 5) |
2491                   (0 << 4) |
2492                   (0 << 3) |
2493                   (1 << 2) |
2494                   (mbaff_frame_flag << 1) |
2495                   (0 << 0));
2496     OUT_BCS_BATCH(batch, 0);
2497     OUT_BCS_BATCH(batch, 0);
2498     OUT_BCS_BATCH(batch, 0);
2499     OUT_BCS_BATCH(batch, 0);
2500     OUT_BCS_BATCH(batch, 0);
2501     OUT_BCS_BATCH(batch, 0);
2502     OUT_BCS_BATCH(batch, 0);
2503     OUT_BCS_BATCH(batch, 0);
2504     OUT_BCS_BATCH(batch, 0);
2505     OUT_BCS_BATCH(batch, 0);
2506     OUT_BCS_BATCH(batch, 0);
2507     ADVANCE_BCS_BATCH(batch);
2508 }
2509
2510 static void
2511 gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2512                                   struct gen7_mfd_context *gen7_mfd_context)
2513 {
2514     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2515     int i;
2516
2517     BEGIN_BCS_BATCH(batch, 69);
2518     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2519
2520     /* reference surfaces 0..15 */
2521     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2522         OUT_BCS_BATCH(batch, 0); /* top */
2523         OUT_BCS_BATCH(batch, 0); /* bottom */
2524     }
2525
2526     /* the current decoding frame/field */
2527     OUT_BCS_BATCH(batch, 0); /* top */
2528     OUT_BCS_BATCH(batch, 0); /* bottom */
2529
2530     /* POC List */
2531     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2532         OUT_BCS_BATCH(batch, 0);
2533         OUT_BCS_BATCH(batch, 0);
2534     }
2535
2536     OUT_BCS_BATCH(batch, 0);
2537     OUT_BCS_BATCH(batch, 0);
2538
2539     ADVANCE_BCS_BATCH(batch);
2540 }
2541
2542 static void
2543 gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2544                                      struct gen7_mfd_context *gen7_mfd_context)
2545 {
2546     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2547
2548     BEGIN_BCS_BATCH(batch, 11);
2549     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2550     OUT_BCS_RELOC(batch,
2551                   gen7_mfd_context->jpeg_wa_slice_data_bo,
2552                   I915_GEM_DOMAIN_INSTRUCTION, 0,
2553                   0);
2554     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2555     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2556     OUT_BCS_BATCH(batch, 0);
2557     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2558     OUT_BCS_BATCH(batch, 0);
2559     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2560     OUT_BCS_BATCH(batch, 0);
2561     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2562     OUT_BCS_BATCH(batch, 0);
2563     ADVANCE_BCS_BATCH(batch);
2564 }
2565
2566 static void
2567 gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2568                             struct gen7_mfd_context *gen7_mfd_context)
2569 {
2570     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2571
2572     /* the input bitsteam format on GEN7 differs from GEN6 */
2573     BEGIN_BCS_BATCH(batch, 6);
2574     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2575     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2576     OUT_BCS_BATCH(batch, 0);
2577     OUT_BCS_BATCH(batch,
2578                   (0 << 31) |
2579                   (0 << 14) |
2580                   (0 << 12) |
2581                   (0 << 10) |
2582                   (0 << 8));
2583     OUT_BCS_BATCH(batch,
2584                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
2585                   (0 << 5)  |
2586                   (0 << 4)  |
2587                   (1 << 3) | /* LastSlice Flag */
2588                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
2589     OUT_BCS_BATCH(batch, 0);
2590     ADVANCE_BCS_BATCH(batch);
2591 }
2592
2593 static void
2594 gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx,
2595                              struct gen7_mfd_context *gen7_mfd_context)
2596 {
2597     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2598     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
2599     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
2600     int first_mb_in_slice = 0;
2601     int slice_type = SLICE_TYPE_I;
2602
2603     BEGIN_BCS_BATCH(batch, 11);
2604     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
2605     OUT_BCS_BATCH(batch, slice_type);
2606     OUT_BCS_BATCH(batch,
2607                   (num_ref_idx_l1 << 24) |
2608                   (num_ref_idx_l0 << 16) |
2609                   (0 << 8) |
2610                   (0 << 0));
2611     OUT_BCS_BATCH(batch,
2612                   (0 << 29) |
2613                   (1 << 27) |   /* disable Deblocking */
2614                   (0 << 24) |
2615                   (gen7_jpeg_wa_clip.qp << 16) |
2616                   (0 << 8) |
2617                   (0 << 0));
2618     OUT_BCS_BATCH(batch,
2619                   (slice_ver_pos << 24) |
2620                   (slice_hor_pos << 16) |
2621                   (first_mb_in_slice << 0));
2622     OUT_BCS_BATCH(batch,
2623                   (next_slice_ver_pos << 16) |
2624                   (next_slice_hor_pos << 0));
2625     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
2626     OUT_BCS_BATCH(batch, 0);
2627     OUT_BCS_BATCH(batch, 0);
2628     OUT_BCS_BATCH(batch, 0);
2629     OUT_BCS_BATCH(batch, 0);
2630     ADVANCE_BCS_BATCH(batch);
2631 }
2632
2633 static void
2634 gen75_mfd_jpeg_wa(VADriverContextP ctx,
2635                  struct gen7_mfd_context *gen7_mfd_context)
2636 {
2637     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2638     gen75_jpeg_wa_init(ctx, gen7_mfd_context);
2639     intel_batchbuffer_emit_mi_flush(batch);
2640     gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
2641     gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context);
2642     gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
2643     gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
2644     gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
2645     gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
2646     gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
2647
2648     gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
2649     gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
2650     gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
2651 }
2652
2653 void
2654 gen75_mfd_jpeg_decode_picture(VADriverContextP ctx,
2655                              struct decode_state *decode_state,
2656                              struct gen7_mfd_context *gen7_mfd_context)
2657 {
2658     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2659     VAPictureParameterBufferJPEGBaseline *pic_param;
2660     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
2661     dri_bo *slice_data_bo;
2662     int i, j, max_selector = 0;
2663
2664     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2665     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2666
2667     /* Currently only support Baseline DCT */
2668     gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
2669     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2670     gen75_mfd_jpeg_wa(ctx, gen7_mfd_context);
2671     intel_batchbuffer_emit_mi_flush(batch);
2672     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2673     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2674     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
2675     gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
2676     gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
2677
2678     for (j = 0; j < decode_state->num_slice_params; j++) {
2679         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2680         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2681         slice_data_bo = decode_state->slice_datas[j]->bo;
2682         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2683
2684         if (j == decode_state->num_slice_params - 1)
2685             next_slice_group_param = NULL;
2686         else
2687             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2688
2689         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2690             int component;
2691
2692             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2693
2694             if (i < decode_state->slice_params[j]->num_elements - 1)
2695                 next_slice_param = slice_param + 1;
2696             else
2697                 next_slice_param = next_slice_group_param;
2698
2699             for (component = 0; component < slice_param->num_components; component++) {
2700                 if (max_selector < slice_param->components[component].dc_table_selector)
2701                     max_selector = slice_param->components[component].dc_table_selector;
2702
2703                 if (max_selector < slice_param->components[component].ac_table_selector)
2704                     max_selector = slice_param->components[component].ac_table_selector;
2705             }
2706
2707             slice_param++;
2708         }
2709     }
2710
2711     assert(max_selector < 2);
2712     gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
2713
2714     for (j = 0; j < decode_state->num_slice_params; j++) {
2715         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2716         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
2717         slice_data_bo = decode_state->slice_datas[j]->bo;
2718         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
2719
2720         if (j == decode_state->num_slice_params - 1)
2721             next_slice_group_param = NULL;
2722         else
2723             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
2724
2725         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2726             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2727
2728             if (i < decode_state->slice_params[j]->num_elements - 1)
2729                 next_slice_param = slice_param + 1;
2730             else
2731                 next_slice_param = next_slice_group_param;
2732
2733             gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2734             slice_param++;
2735         }
2736     }
2737
2738     intel_batchbuffer_end_atomic(batch);
2739     intel_batchbuffer_flush(batch);
2740 }
2741
2742 static void
2743 gen75_mfd_decode_picture(VADriverContextP ctx,
2744                         VAProfile profile,
2745                         union codec_state *codec_state,
2746                         struct hw_context *hw_context)
2747
2748 {
2749     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2750     struct decode_state *decode_state = &codec_state->decode;
2751
2752     assert(gen7_mfd_context);
2753
2754     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2755
2756     switch (profile) {
2757     case VAProfileMPEG2Simple:
2758     case VAProfileMPEG2Main:
2759         gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
2760         break;
2761
2762     case VAProfileH264Baseline:
2763     case VAProfileH264Main:
2764     case VAProfileH264High:
2765         gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
2766         break;
2767
2768     case VAProfileVC1Simple:
2769     case VAProfileVC1Main:
2770     case VAProfileVC1Advanced:
2771         gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
2772         break;
2773
2774     case VAProfileJPEGBaseline:
2775         gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
2776         break;
2777
2778     default:
2779         assert(0);
2780         break;
2781     }
2782 }
2783
2784 static void
2785 gen75_mfd_context_destroy(void *hw_context)
2786 {
2787     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
2788
2789     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
2790     gen7_mfd_context->post_deblocking_output.bo = NULL;
2791
2792     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2793     gen7_mfd_context->pre_deblocking_output.bo = NULL;
2794
2795     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
2796     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2797
2798     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2799     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2800
2801     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2802     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2803
2804     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
2805     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2806
2807     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
2808     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2809
2810     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
2811
2812     intel_batchbuffer_free(gen7_mfd_context->base.batch);
2813     free(gen7_mfd_context);
2814 }
2815
2816 static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx,
2817                                     struct gen7_mfd_context *gen7_mfd_context)
2818 {
2819     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
2820     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
2821     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
2822     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
2823 }
2824
2825 struct hw_context *
2826 gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2827 {
2828     struct intel_driver_data *intel = intel_driver_data(ctx);
2829     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
2830     int i;
2831
2832     gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
2833     gen7_mfd_context->base.run = gen75_mfd_decode_picture;
2834     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER);
2835
2836     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
2837         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2838         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
2839     }
2840
2841     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
2842
2843     switch (obj_config->profile) {
2844     case VAProfileMPEG2Simple:
2845     case VAProfileMPEG2Main:
2846         gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
2847         break;
2848
2849     case VAProfileH264Baseline:
2850     case VAProfileH264Main:
2851     case VAProfileH264High:
2852         gen75_mfd_avc_context_init(ctx, gen7_mfd_context);
2853         break;
2854     default:
2855         break;
2856     }
2857     return (struct hw_context *)gen7_mfd_context;
2858 }