2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
26 * Zhao Yakui <yakui.zhao@intel.com>
31 #include <va/va_dec_jpeg.h>
33 #include "intel_batchbuffer.h"
34 #include "intel_driver.h"
35 #include "i965_defines.h"
36 #include "i965_drv_video.h"
37 #include "i965_decoder_utils.h"
39 #include "intel_media.h"
42 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
44 static const uint32_t zigzag_direct[64] = {
45 0, 1, 8, 16, 9, 2, 3, 10,
46 17, 24, 32, 25, 18, 11, 4, 5,
47 12, 19, 26, 33, 40, 48, 41, 34,
48 27, 20, 13, 6, 7, 14, 21, 28,
49 35, 42, 49, 56, 57, 50, 43, 36,
50 29, 22, 15, 23, 30, 37, 44, 51,
51 58, 59, 52, 45, 38, 31, 39, 46,
52 53, 60, 61, 54, 47, 55, 62, 63
56 gen75_mfd_init_avc_surface(VADriverContextP ctx,
57 VAPictureParameterBufferH264 *pic_param,
58 struct object_surface *obj_surface)
60 struct i965_driver_data *i965 = i965_driver_data(ctx);
61 GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
62 int width_in_mbs, height_in_mbs;
64 obj_surface->free_private_data = gen_free_avc_surface;
65 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
66 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
68 if (!gen7_avc_surface) {
69 gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
70 assert((obj_surface->size & 0x3f) == 0);
71 obj_surface->private_data = gen7_avc_surface;
74 gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
75 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
77 if (gen7_avc_surface->dmv_top == NULL) {
78 gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
79 "direct mv w/r buffer",
80 width_in_mbs * height_in_mbs * 128,
82 assert(gen7_avc_surface->dmv_top);
85 if (gen7_avc_surface->dmv_bottom_flag &&
86 gen7_avc_surface->dmv_bottom == NULL) {
87 gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
88 "direct mv w/r buffer",
89 width_in_mbs * height_in_mbs * 128,
91 assert(gen7_avc_surface->dmv_bottom);
96 gen75_mfd_pipe_mode_select(VADriverContextP ctx,
97 struct decode_state *decode_state,
99 struct gen7_mfd_context *gen7_mfd_context)
101 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
103 assert(standard_select == MFX_FORMAT_MPEG2 ||
104 standard_select == MFX_FORMAT_AVC ||
105 standard_select == MFX_FORMAT_VC1 ||
106 standard_select == MFX_FORMAT_JPEG);
108 BEGIN_BCS_BATCH(batch, 5);
109 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
111 (MFX_LONG_MODE << 17) | /* Currently only support long format */
112 (MFD_MODE_VLD << 15) | /* VLD mode */
113 (0 << 10) | /* disable Stream-Out */
114 (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
115 (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
116 (0 << 5) | /* not in stitch mode */
117 (MFX_CODEC_DECODE << 4) | /* decoding mode */
118 (standard_select << 0));
120 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
121 (0 << 3) | /* terminate if AVC mbdata error occurs */
122 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
125 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
126 OUT_BCS_BATCH(batch, 0); /* reserved */
127 ADVANCE_BCS_BATCH(batch);
131 gen75_mfd_surface_state(VADriverContextP ctx,
132 struct decode_state *decode_state,
134 struct gen7_mfd_context *gen7_mfd_context)
136 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
137 struct object_surface *obj_surface = decode_state->render_object;
138 unsigned int y_cb_offset;
139 unsigned int y_cr_offset;
143 y_cb_offset = obj_surface->y_cb_offset;
144 y_cr_offset = obj_surface->y_cr_offset;
146 BEGIN_BCS_BATCH(batch, 6);
147 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
148 OUT_BCS_BATCH(batch, 0);
150 ((obj_surface->orig_height - 1) << 18) |
151 ((obj_surface->orig_width - 1) << 4));
153 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
154 ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
155 (0 << 22) | /* surface object control state, ignored */
156 ((obj_surface->width - 1) << 3) | /* pitch */
157 (0 << 2) | /* must be 0 */
158 (1 << 1) | /* must be tiled */
159 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
161 (0 << 16) | /* X offset for U(Cb), must be 0 */
162 (y_cb_offset << 0)); /* Y offset for U(Cb) */
164 (0 << 16) | /* X offset for V(Cr), must be 0 */
165 (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
166 ADVANCE_BCS_BATCH(batch);
170 gen75_mfd_pipe_buf_addr_state_bplus(VADriverContextP ctx,
171 struct decode_state *decode_state,
173 struct gen7_mfd_context *gen7_mfd_context)
175 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
178 BEGIN_BCS_BATCH(batch, 61);
179 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
180 /* Pre-deblock 1-3 */
181 if (gen7_mfd_context->pre_deblocking_output.valid)
182 OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
183 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
186 OUT_BCS_BATCH(batch, 0);
188 OUT_BCS_BATCH(batch, 0);
189 OUT_BCS_BATCH(batch, 0);
190 /* Post-debloing 4-6 */
191 if (gen7_mfd_context->post_deblocking_output.valid)
192 OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
193 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
196 OUT_BCS_BATCH(batch, 0);
198 OUT_BCS_BATCH(batch, 0);
199 OUT_BCS_BATCH(batch, 0);
201 /* uncompressed-video & stream out 7-12 */
202 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
203 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
204 OUT_BCS_BATCH(batch, 0);
205 OUT_BCS_BATCH(batch, 0);
206 OUT_BCS_BATCH(batch, 0);
207 OUT_BCS_BATCH(batch, 0);
209 /* intra row-store scratch 13-15 */
210 if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
211 OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
212 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
215 OUT_BCS_BATCH(batch, 0);
217 OUT_BCS_BATCH(batch, 0);
218 OUT_BCS_BATCH(batch, 0);
219 /* deblocking-filter-row-store 16-18 */
220 if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
221 OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
222 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
225 OUT_BCS_BATCH(batch, 0);
226 OUT_BCS_BATCH(batch, 0);
227 OUT_BCS_BATCH(batch, 0);
230 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
231 struct object_surface *obj_surface;
233 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
234 gen7_mfd_context->reference_surface[i].obj_surface &&
235 gen7_mfd_context->reference_surface[i].obj_surface->bo) {
236 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
238 OUT_BCS_RELOC(batch, obj_surface->bo,
239 I915_GEM_DOMAIN_INSTRUCTION, 0,
242 OUT_BCS_BATCH(batch, 0);
244 OUT_BCS_BATCH(batch, 0);
246 /* reference property 51 */
247 OUT_BCS_BATCH(batch, 0);
249 /* Macroblock status & ILDB 52-57 */
250 OUT_BCS_BATCH(batch, 0);
251 OUT_BCS_BATCH(batch, 0);
252 OUT_BCS_BATCH(batch, 0);
253 OUT_BCS_BATCH(batch, 0);
254 OUT_BCS_BATCH(batch, 0);
255 OUT_BCS_BATCH(batch, 0);
257 /* the second Macroblock status 58-60 */
258 OUT_BCS_BATCH(batch, 0);
259 OUT_BCS_BATCH(batch, 0);
260 OUT_BCS_BATCH(batch, 0);
261 ADVANCE_BCS_BATCH(batch);
265 gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx,
266 struct decode_state *decode_state,
268 struct gen7_mfd_context *gen7_mfd_context)
270 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
271 struct i965_driver_data *i965 = i965_driver_data(ctx);
274 if (IS_STEPPING_BPLUS(i965)) {
275 gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state,
276 standard_select, gen7_mfd_context);
280 BEGIN_BCS_BATCH(batch, 25);
281 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
282 if (gen7_mfd_context->pre_deblocking_output.valid)
283 OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
284 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
287 OUT_BCS_BATCH(batch, 0);
289 if (gen7_mfd_context->post_deblocking_output.valid)
290 OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
291 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
294 OUT_BCS_BATCH(batch, 0);
296 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
297 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
299 if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
300 OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
301 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
304 OUT_BCS_BATCH(batch, 0);
306 if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
307 OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
308 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
311 OUT_BCS_BATCH(batch, 0);
314 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
315 struct object_surface *obj_surface;
317 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
318 gen7_mfd_context->reference_surface[i].obj_surface &&
319 gen7_mfd_context->reference_surface[i].obj_surface->bo) {
320 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
322 OUT_BCS_RELOC(batch, obj_surface->bo,
323 I915_GEM_DOMAIN_INSTRUCTION, 0,
326 OUT_BCS_BATCH(batch, 0);
330 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
331 OUT_BCS_BATCH(batch, 0); /* ignore DW24 for decoding */
332 ADVANCE_BCS_BATCH(batch);
336 gen75_mfd_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
337 dri_bo *slice_data_bo,
339 struct gen7_mfd_context *gen7_mfd_context)
341 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
343 BEGIN_BCS_BATCH(batch, 26);
344 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
346 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
347 OUT_BCS_BATCH(batch, 0);
348 OUT_BCS_BATCH(batch, 0);
349 /* Upper bound 4-5 */
350 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
351 OUT_BCS_BATCH(batch, 0);
353 /* MFX indirect MV 6-10 */
354 OUT_BCS_BATCH(batch, 0);
355 OUT_BCS_BATCH(batch, 0);
356 OUT_BCS_BATCH(batch, 0);
357 OUT_BCS_BATCH(batch, 0);
358 OUT_BCS_BATCH(batch, 0);
360 /* MFX IT_COFF 11-15 */
361 OUT_BCS_BATCH(batch, 0);
362 OUT_BCS_BATCH(batch, 0);
363 OUT_BCS_BATCH(batch, 0);
364 OUT_BCS_BATCH(batch, 0);
365 OUT_BCS_BATCH(batch, 0);
367 /* MFX IT_DBLK 16-20 */
368 OUT_BCS_BATCH(batch, 0);
369 OUT_BCS_BATCH(batch, 0);
370 OUT_BCS_BATCH(batch, 0);
371 OUT_BCS_BATCH(batch, 0);
372 OUT_BCS_BATCH(batch, 0);
374 /* MFX PAK_BSE object for encoder 21-25 */
375 OUT_BCS_BATCH(batch, 0);
376 OUT_BCS_BATCH(batch, 0);
377 OUT_BCS_BATCH(batch, 0);
378 OUT_BCS_BATCH(batch, 0);
379 OUT_BCS_BATCH(batch, 0);
381 ADVANCE_BCS_BATCH(batch);
385 gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
386 dri_bo *slice_data_bo,
388 struct gen7_mfd_context *gen7_mfd_context)
390 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
391 struct i965_driver_data *i965 = i965_driver_data(ctx);
393 if (IS_STEPPING_BPLUS(i965)) {
394 gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo,
395 standard_select, gen7_mfd_context);
399 BEGIN_BCS_BATCH(batch, 11);
400 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
401 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
402 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
403 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
404 OUT_BCS_BATCH(batch, 0);
405 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
406 OUT_BCS_BATCH(batch, 0);
407 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
408 OUT_BCS_BATCH(batch, 0);
409 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
410 OUT_BCS_BATCH(batch, 0);
411 ADVANCE_BCS_BATCH(batch);
415 gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
416 struct decode_state *decode_state,
418 struct gen7_mfd_context *gen7_mfd_context)
420 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
422 BEGIN_BCS_BATCH(batch, 10);
423 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
425 if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
426 OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
427 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
430 OUT_BCS_BATCH(batch, 0);
432 OUT_BCS_BATCH(batch, 0);
433 OUT_BCS_BATCH(batch, 0);
434 /* MPR Row Store Scratch buffer 4-6 */
435 if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
436 OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
437 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
440 OUT_BCS_BATCH(batch, 0);
441 OUT_BCS_BATCH(batch, 0);
442 OUT_BCS_BATCH(batch, 0);
445 if (gen7_mfd_context->bitplane_read_buffer.valid)
446 OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
447 I915_GEM_DOMAIN_INSTRUCTION, 0,
450 OUT_BCS_BATCH(batch, 0);
451 OUT_BCS_BATCH(batch, 0);
452 OUT_BCS_BATCH(batch, 0);
454 ADVANCE_BCS_BATCH(batch);
458 gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
459 struct decode_state *decode_state,
461 struct gen7_mfd_context *gen7_mfd_context)
463 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
464 struct i965_driver_data *i965 = i965_driver_data(ctx);
466 if (IS_STEPPING_BPLUS(i965)) {
467 gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state,
468 standard_select, gen7_mfd_context);
472 BEGIN_BCS_BATCH(batch, 4);
473 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
475 if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
476 OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
477 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
480 OUT_BCS_BATCH(batch, 0);
482 if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
483 OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
484 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
487 OUT_BCS_BATCH(batch, 0);
489 if (gen7_mfd_context->bitplane_read_buffer.valid)
490 OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
491 I915_GEM_DOMAIN_INSTRUCTION, 0,
494 OUT_BCS_BATCH(batch, 0);
496 ADVANCE_BCS_BATCH(batch);
500 gen75_mfd_qm_state(VADriverContextP ctx,
504 struct gen7_mfd_context *gen7_mfd_context)
506 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
507 unsigned int qm_buffer[16];
509 assert(qm_length <= 16 * 4);
510 memcpy(qm_buffer, qm, qm_length);
512 BEGIN_BCS_BATCH(batch, 18);
513 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
514 OUT_BCS_BATCH(batch, qm_type << 0);
515 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
516 ADVANCE_BCS_BATCH(batch);
520 gen75_mfd_avc_img_state(VADriverContextP ctx,
521 struct decode_state *decode_state,
522 struct gen7_mfd_context *gen7_mfd_context)
524 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
526 int mbaff_frame_flag;
527 unsigned int width_in_mbs, height_in_mbs;
528 VAPictureParameterBufferH264 *pic_param;
530 assert(decode_state->pic_param && decode_state->pic_param->buffer);
531 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
533 assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
535 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
537 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
542 if ((img_struct & 0x1) == 0x1) {
543 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
545 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
548 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
549 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
550 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
552 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
555 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
556 !pic_param->pic_fields.bits.field_pic_flag);
558 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
559 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
561 /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
562 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
563 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
564 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
566 BEGIN_BCS_BATCH(batch, 17);
567 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2));
569 (width_in_mbs * height_in_mbs - 1));
571 ((height_in_mbs - 1) << 16) |
572 ((width_in_mbs - 1) << 0));
574 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
575 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
576 (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
577 (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
578 (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
579 (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
582 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
583 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
584 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
585 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
586 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
587 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
588 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
589 (mbaff_frame_flag << 1) |
590 (pic_param->pic_fields.bits.field_pic_flag << 0));
591 OUT_BCS_BATCH(batch, 0);
592 OUT_BCS_BATCH(batch, 0);
593 OUT_BCS_BATCH(batch, 0);
594 OUT_BCS_BATCH(batch, 0);
595 OUT_BCS_BATCH(batch, 0);
596 OUT_BCS_BATCH(batch, 0);
597 OUT_BCS_BATCH(batch, 0);
598 OUT_BCS_BATCH(batch, 0);
599 OUT_BCS_BATCH(batch, 0);
600 OUT_BCS_BATCH(batch, 0);
601 OUT_BCS_BATCH(batch, 0);
602 OUT_BCS_BATCH(batch, 0);
603 ADVANCE_BCS_BATCH(batch);
607 gen75_mfd_avc_qm_state(VADriverContextP ctx,
608 struct decode_state *decode_state,
609 struct gen7_mfd_context *gen7_mfd_context)
611 VAIQMatrixBufferH264 *iq_matrix;
612 VAPictureParameterBufferH264 *pic_param;
614 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
615 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
617 iq_matrix = &gen7_mfd_context->iq_matrix.h264;
619 assert(decode_state->pic_param && decode_state->pic_param->buffer);
620 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
622 gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
623 gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
625 if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
626 gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
627 gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
632 gen75_mfd_avc_picid_state(VADriverContextP ctx,
633 struct decode_state *decode_state,
634 struct gen7_mfd_context *gen7_mfd_context)
636 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
638 BEGIN_BCS_BATCH(batch, 10);
639 OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2));
640 OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping
641 OUT_BCS_BATCH(batch, 0);
642 OUT_BCS_BATCH(batch, 0);
643 OUT_BCS_BATCH(batch, 0);
644 OUT_BCS_BATCH(batch, 0);
645 OUT_BCS_BATCH(batch, 0);
646 OUT_BCS_BATCH(batch, 0);
647 OUT_BCS_BATCH(batch, 0);
648 OUT_BCS_BATCH(batch, 0);
649 ADVANCE_BCS_BATCH(batch);
653 gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx,
654 struct decode_state *decode_state,
655 VAPictureParameterBufferH264 *pic_param,
656 VASliceParameterBufferH264 *slice_param,
657 struct gen7_mfd_context *gen7_mfd_context)
659 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
660 struct object_surface *obj_surface;
661 GenAvcSurface *gen7_avc_surface;
662 VAPictureH264 *va_pic;
665 BEGIN_BCS_BATCH(batch, 71);
666 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
668 /* reference surfaces 0..15 */
669 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
670 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
671 gen7_mfd_context->reference_surface[i].obj_surface &&
672 gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
674 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
675 gen7_avc_surface = obj_surface->private_data;
676 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
677 I915_GEM_DOMAIN_INSTRUCTION, 0,
679 OUT_BCS_BATCH(batch, 0);
681 OUT_BCS_BATCH(batch, 0);
682 OUT_BCS_BATCH(batch, 0);
686 OUT_BCS_BATCH(batch, 0);
688 /* the current decoding frame/field */
689 va_pic = &pic_param->CurrPic;
690 obj_surface = decode_state->render_object;
691 assert(obj_surface->bo && obj_surface->private_data);
692 gen7_avc_surface = obj_surface->private_data;
694 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
695 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
698 OUT_BCS_BATCH(batch, 0);
699 OUT_BCS_BATCH(batch, 0);
702 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
703 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
706 assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL);
708 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
709 va_pic = &pic_param->ReferenceFrames[j];
711 if (va_pic->flags & VA_PICTURE_H264_INVALID)
714 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
721 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
723 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
724 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
726 OUT_BCS_BATCH(batch, 0);
727 OUT_BCS_BATCH(batch, 0);
731 va_pic = &pic_param->CurrPic;
732 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
733 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
735 ADVANCE_BCS_BATCH(batch);
739 gen75_mfd_avc_directmode_state(VADriverContextP ctx,
740 struct decode_state *decode_state,
741 VAPictureParameterBufferH264 *pic_param,
742 VASliceParameterBufferH264 *slice_param,
743 struct gen7_mfd_context *gen7_mfd_context)
745 struct i965_driver_data *i965 = i965_driver_data(ctx);
746 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
747 struct object_surface *obj_surface;
748 GenAvcSurface *gen7_avc_surface;
749 VAPictureH264 *va_pic;
752 if (IS_STEPPING_BPLUS(i965)) {
753 gen75_mfd_avc_directmode_state_bplus(ctx, decode_state, pic_param, slice_param,
759 BEGIN_BCS_BATCH(batch, 69);
760 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
762 /* reference surfaces 0..15 */
763 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
764 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
765 gen7_mfd_context->reference_surface[i].obj_surface &&
766 gen7_mfd_context->reference_surface[i].obj_surface->private_data) {
768 obj_surface = gen7_mfd_context->reference_surface[i].obj_surface;
769 gen7_avc_surface = obj_surface->private_data;
771 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
772 I915_GEM_DOMAIN_INSTRUCTION, 0,
775 if (gen7_avc_surface->dmv_bottom_flag == 1)
776 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
777 I915_GEM_DOMAIN_INSTRUCTION, 0,
780 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
781 I915_GEM_DOMAIN_INSTRUCTION, 0,
784 OUT_BCS_BATCH(batch, 0);
785 OUT_BCS_BATCH(batch, 0);
789 /* the current decoding frame/field */
790 va_pic = &pic_param->CurrPic;
791 obj_surface = decode_state->render_object;
792 assert(obj_surface->bo && obj_surface->private_data);
793 gen7_avc_surface = obj_surface->private_data;
795 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
796 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
799 if (gen7_avc_surface->dmv_bottom_flag == 1)
800 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
801 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
804 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
805 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
809 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
810 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
813 assert(gen7_mfd_context->reference_surface[i].obj_surface != NULL);
815 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
816 va_pic = &pic_param->ReferenceFrames[j];
818 if (va_pic->flags & VA_PICTURE_H264_INVALID)
821 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
828 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
830 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
831 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
833 OUT_BCS_BATCH(batch, 0);
834 OUT_BCS_BATCH(batch, 0);
838 va_pic = &pic_param->CurrPic;
839 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
840 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
842 ADVANCE_BCS_BATCH(batch);
846 gen75_mfd_avc_slice_state(VADriverContextP ctx,
847 VAPictureParameterBufferH264 *pic_param,
848 VASliceParameterBufferH264 *slice_param,
849 VASliceParameterBufferH264 *next_slice_param,
850 struct gen7_mfd_context *gen7_mfd_context)
852 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
853 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
854 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
855 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
856 int num_ref_idx_l0, num_ref_idx_l1;
857 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
858 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
859 int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
862 if (slice_param->slice_type == SLICE_TYPE_I ||
863 slice_param->slice_type == SLICE_TYPE_SI) {
864 slice_type = SLICE_TYPE_I;
865 } else if (slice_param->slice_type == SLICE_TYPE_P ||
866 slice_param->slice_type == SLICE_TYPE_SP) {
867 slice_type = SLICE_TYPE_P;
869 assert(slice_param->slice_type == SLICE_TYPE_B);
870 slice_type = SLICE_TYPE_B;
873 if (slice_type == SLICE_TYPE_I) {
874 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
875 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
878 } else if (slice_type == SLICE_TYPE_P) {
879 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
880 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
883 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
884 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
887 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
888 slice_hor_pos = first_mb_in_slice % width_in_mbs;
889 slice_ver_pos = first_mb_in_slice / width_in_mbs;
891 if (next_slice_param) {
892 first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
893 next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
894 next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
896 next_slice_hor_pos = 0;
897 next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
900 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
901 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
902 OUT_BCS_BATCH(batch, slice_type);
904 (num_ref_idx_l1 << 24) |
905 (num_ref_idx_l0 << 16) |
906 (slice_param->chroma_log2_weight_denom << 8) |
907 (slice_param->luma_log2_weight_denom << 0));
909 (slice_param->direct_spatial_mv_pred_flag << 29) |
910 (slice_param->disable_deblocking_filter_idc << 27) |
911 (slice_param->cabac_init_idc << 24) |
912 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
913 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
914 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
916 (slice_ver_pos << 24) |
917 (slice_hor_pos << 16) |
918 (first_mb_in_slice << 0));
920 (next_slice_ver_pos << 16) |
921 (next_slice_hor_pos << 0));
923 (next_slice_param == NULL) << 19); /* last slice flag */
924 OUT_BCS_BATCH(batch, 0);
925 OUT_BCS_BATCH(batch, 0);
926 OUT_BCS_BATCH(batch, 0);
927 OUT_BCS_BATCH(batch, 0);
928 ADVANCE_BCS_BATCH(batch);
932 gen75_mfd_avc_ref_idx_state(VADriverContextP ctx,
933 VAPictureParameterBufferH264 *pic_param,
934 VASliceParameterBufferH264 *slice_param,
935 struct gen7_mfd_context *gen7_mfd_context)
937 gen6_send_avc_ref_idx_state(
938 gen7_mfd_context->base.batch,
940 gen7_mfd_context->reference_surface
945 gen75_mfd_avc_weightoffset_state(VADriverContextP ctx,
946 VAPictureParameterBufferH264 *pic_param,
947 VASliceParameterBufferH264 *slice_param,
948 struct gen7_mfd_context *gen7_mfd_context)
950 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
951 int i, j, num_weight_offset_table = 0;
952 short weightoffsets[32 * 6];
954 if ((slice_param->slice_type == SLICE_TYPE_P ||
955 slice_param->slice_type == SLICE_TYPE_SP) &&
956 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
957 num_weight_offset_table = 1;
960 if ((slice_param->slice_type == SLICE_TYPE_B) &&
961 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
962 num_weight_offset_table = 2;
965 for (i = 0; i < num_weight_offset_table; i++) {
966 BEGIN_BCS_BATCH(batch, 98);
967 OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
968 OUT_BCS_BATCH(batch, i);
971 for (j = 0; j < 32; j++) {
972 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
973 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
974 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
975 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
976 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
977 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
980 for (j = 0; j < 32; j++) {
981 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
982 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
983 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
984 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
985 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
986 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
990 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
991 ADVANCE_BCS_BATCH(batch);
996 gen75_mfd_avc_bsd_object(VADriverContextP ctx,
997 VAPictureParameterBufferH264 *pic_param,
998 VASliceParameterBufferH264 *slice_param,
999 dri_bo *slice_data_bo,
1000 VASliceParameterBufferH264 *next_slice_param,
1001 struct gen7_mfd_context *gen7_mfd_context)
1003 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1004 int slice_data_bit_offset = avc_get_first_mb_bit_offset(slice_data_bo,
1006 pic_param->pic_fields.bits.entropy_coding_mode_flag);
1008 /* the input bitsteam format on GEN7 differs from GEN6 */
1009 BEGIN_BCS_BATCH(batch, 6);
1010 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
1011 OUT_BCS_BATCH(batch,
1012 (slice_param->slice_data_size - slice_param->slice_data_offset));
1013 OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
1014 OUT_BCS_BATCH(batch,
1020 OUT_BCS_BATCH(batch,
1021 ((slice_data_bit_offset >> 3) << 16) |
1025 ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
1026 (slice_data_bit_offset & 0x7));
1027 OUT_BCS_BATCH(batch, 0);
1028 ADVANCE_BCS_BATCH(batch);
1032 gen75_mfd_avc_context_init(
1033 VADriverContextP ctx,
1034 struct gen7_mfd_context *gen7_mfd_context
1037 /* Initialize flat scaling lists */
1038 avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
1042 gen75_mfd_avc_decode_init(VADriverContextP ctx,
1043 struct decode_state *decode_state,
1044 struct gen7_mfd_context *gen7_mfd_context)
1046 VAPictureParameterBufferH264 *pic_param;
1047 VASliceParameterBufferH264 *slice_param;
1048 struct i965_driver_data *i965 = i965_driver_data(ctx);
1049 struct object_surface *obj_surface;
1051 int i, j, enable_avc_ildb = 0;
1052 unsigned int width_in_mbs, height_in_mbs;
1054 for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
1055 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1056 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1058 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1059 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1060 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1061 (slice_param->slice_type == SLICE_TYPE_SI) ||
1062 (slice_param->slice_type == SLICE_TYPE_P) ||
1063 (slice_param->slice_type == SLICE_TYPE_SP) ||
1064 (slice_param->slice_type == SLICE_TYPE_B));
1066 if (slice_param->disable_deblocking_filter_idc != 1) {
1067 enable_avc_ildb = 1;
1075 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1076 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1077 intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen7_mfd_context->reference_surface);
1078 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1079 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1080 assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
1081 assert(height_in_mbs > 0 && height_in_mbs <= 256);
1083 /* Current decoded picture */
1084 obj_surface = decode_state->render_object;
1085 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
1086 obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
1087 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1089 /* initial uv component for YUV400 case */
1090 if (pic_param->seq_fields.bits.chroma_format_idc == 0) {
1091 unsigned int uv_offset = obj_surface->width * obj_surface->height;
1092 unsigned int uv_size = obj_surface->width * obj_surface->height / 2;
1094 drm_intel_gem_bo_map_gtt(obj_surface->bo);
1095 memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size);
1096 drm_intel_gem_bo_unmap_gtt(obj_surface->bo);
1099 gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface);
1101 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1102 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1103 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1104 gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
1106 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1107 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1108 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1109 gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
1111 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1112 bo = dri_bo_alloc(i965->intel.bufmgr,
1117 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1118 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1120 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1121 bo = dri_bo_alloc(i965->intel.bufmgr,
1122 "deblocking filter row store",
1123 width_in_mbs * 64 * 4,
1126 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1127 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1129 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1130 bo = dri_bo_alloc(i965->intel.bufmgr,
1131 "bsd mpc row store",
1132 width_in_mbs * 64 * 2,
1135 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1136 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1138 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
1139 bo = dri_bo_alloc(i965->intel.bufmgr,
1141 width_in_mbs * 64 * 2,
1144 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
1145 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1147 gen7_mfd_context->bitplane_read_buffer.valid = 0;
1151 gen75_mfd_avc_decode_picture(VADriverContextP ctx,
1152 struct decode_state *decode_state,
1153 struct gen7_mfd_context *gen7_mfd_context)
1155 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1156 VAPictureParameterBufferH264 *pic_param;
1157 VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1158 dri_bo *slice_data_bo;
1161 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1162 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1163 gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
1165 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1166 intel_batchbuffer_emit_mi_flush(batch);
1167 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1168 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1169 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1170 gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1171 gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
1172 gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1173 gen75_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context);
1175 for (j = 0; j < decode_state->num_slice_params; j++) {
1176 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1177 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1178 slice_data_bo = decode_state->slice_datas[j]->bo;
1179 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1181 if (j == decode_state->num_slice_params - 1)
1182 next_slice_group_param = NULL;
1184 next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1186 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1187 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1188 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1189 (slice_param->slice_type == SLICE_TYPE_SI) ||
1190 (slice_param->slice_type == SLICE_TYPE_P) ||
1191 (slice_param->slice_type == SLICE_TYPE_SP) ||
1192 (slice_param->slice_type == SLICE_TYPE_B));
1194 if (i < decode_state->slice_params[j]->num_elements - 1)
1195 next_slice_param = slice_param + 1;
1197 next_slice_param = next_slice_group_param;
1199 gen75_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen7_mfd_context);
1200 gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1201 gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1202 gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1203 gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1208 intel_batchbuffer_end_atomic(batch);
1209 intel_batchbuffer_flush(batch);
1213 gen75_mfd_mpeg2_decode_init(VADriverContextP ctx,
1214 struct decode_state *decode_state,
1215 struct gen7_mfd_context *gen7_mfd_context)
1217 VAPictureParameterBufferMPEG2 *pic_param;
1218 struct i965_driver_data *i965 = i965_driver_data(ctx);
1219 struct object_surface *obj_surface;
1221 unsigned int width_in_mbs;
1223 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1224 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1225 width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1227 mpeg2_set_reference_surfaces(
1229 gen7_mfd_context->reference_surface,
1234 /* Current decoded picture */
1235 obj_surface = decode_state->render_object;
1236 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1238 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1239 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1240 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1241 gen7_mfd_context->pre_deblocking_output.valid = 1;
1243 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1244 bo = dri_bo_alloc(i965->intel.bufmgr,
1245 "bsd mpc row store",
1249 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1250 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1252 gen7_mfd_context->post_deblocking_output.valid = 0;
1253 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1254 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1255 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1256 gen7_mfd_context->bitplane_read_buffer.valid = 0;
1260 gen75_mfd_mpeg2_pic_state(VADriverContextP ctx,
1261 struct decode_state *decode_state,
1262 struct gen7_mfd_context *gen7_mfd_context)
1264 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1265 VAPictureParameterBufferMPEG2 *pic_param;
1266 unsigned int slice_concealment_disable_bit = 0;
1268 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1269 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1271 slice_concealment_disable_bit = 1;
1273 BEGIN_BCS_BATCH(batch, 13);
1274 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1275 OUT_BCS_BATCH(batch,
1276 (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1277 ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1278 ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1279 ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1280 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1281 pic_param->picture_coding_extension.bits.picture_structure << 12 |
1282 pic_param->picture_coding_extension.bits.top_field_first << 11 |
1283 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1284 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1285 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1286 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1287 pic_param->picture_coding_extension.bits.alternate_scan << 6);
1288 OUT_BCS_BATCH(batch,
1289 pic_param->picture_coding_type << 9);
1290 OUT_BCS_BATCH(batch,
1291 (slice_concealment_disable_bit << 31) |
1292 ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1293 ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1294 OUT_BCS_BATCH(batch, 0);
1295 OUT_BCS_BATCH(batch, 0);
1296 OUT_BCS_BATCH(batch, 0);
1297 OUT_BCS_BATCH(batch, 0);
1298 OUT_BCS_BATCH(batch, 0);
1299 OUT_BCS_BATCH(batch, 0);
1300 OUT_BCS_BATCH(batch, 0);
1301 OUT_BCS_BATCH(batch, 0);
1302 OUT_BCS_BATCH(batch, 0);
1303 ADVANCE_BCS_BATCH(batch);
1307 gen75_mfd_mpeg2_qm_state(VADriverContextP ctx,
1308 struct decode_state *decode_state,
1309 struct gen7_mfd_context *gen7_mfd_context)
1311 VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1314 /* Update internal QM state */
1315 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1316 VAIQMatrixBufferMPEG2 * const iq_matrix =
1317 (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1319 if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1320 iq_matrix->load_intra_quantiser_matrix) {
1321 gen_iq_matrix->load_intra_quantiser_matrix =
1322 iq_matrix->load_intra_quantiser_matrix;
1323 if (iq_matrix->load_intra_quantiser_matrix) {
1324 for (j = 0; j < 64; j++)
1325 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1326 iq_matrix->intra_quantiser_matrix[j];
1330 if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1331 iq_matrix->load_non_intra_quantiser_matrix) {
1332 gen_iq_matrix->load_non_intra_quantiser_matrix =
1333 iq_matrix->load_non_intra_quantiser_matrix;
1334 if (iq_matrix->load_non_intra_quantiser_matrix) {
1335 for (j = 0; j < 64; j++)
1336 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1337 iq_matrix->non_intra_quantiser_matrix[j];
1342 /* Commit QM state to HW */
1343 for (i = 0; i < 2; i++) {
1344 unsigned char *qm = NULL;
1348 if (gen_iq_matrix->load_intra_quantiser_matrix) {
1349 qm = gen_iq_matrix->intra_quantiser_matrix;
1350 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1353 if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1354 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1355 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1362 gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1367 gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1368 VAPictureParameterBufferMPEG2 *pic_param,
1369 VASliceParameterBufferMPEG2 *slice_param,
1370 VASliceParameterBufferMPEG2 *next_slice_param,
1371 struct gen7_mfd_context *gen7_mfd_context)
1373 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1374 unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1375 int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1377 if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1378 pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1380 is_field_pic_wa = is_field_pic &&
1381 gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1383 vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1384 hpos0 = slice_param->slice_horizontal_position;
1386 if (next_slice_param == NULL) {
1387 vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1390 vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1391 hpos1 = next_slice_param->slice_horizontal_position;
1394 mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1396 BEGIN_BCS_BATCH(batch, 5);
1397 OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1398 OUT_BCS_BATCH(batch,
1399 slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1400 OUT_BCS_BATCH(batch,
1401 slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1402 OUT_BCS_BATCH(batch,
1406 (next_slice_param == NULL) << 5 |
1407 (next_slice_param == NULL) << 3 |
1408 (slice_param->macroblock_offset & 0x7));
1409 OUT_BCS_BATCH(batch,
1410 (slice_param->quantiser_scale_code << 24) |
1411 (vpos1 << 8 | hpos1));
1412 ADVANCE_BCS_BATCH(batch);
1416 gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1417 struct decode_state *decode_state,
1418 struct gen7_mfd_context *gen7_mfd_context)
1420 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1421 VAPictureParameterBufferMPEG2 *pic_param;
1422 VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1423 dri_bo *slice_data_bo;
1426 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1427 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1429 gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1430 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1431 intel_batchbuffer_emit_mi_flush(batch);
1432 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1433 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1434 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1435 gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1436 gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1437 gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1439 if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1440 gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1441 mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1443 for (j = 0; j < decode_state->num_slice_params; j++) {
1444 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1445 slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1446 slice_data_bo = decode_state->slice_datas[j]->bo;
1447 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1449 if (j == decode_state->num_slice_params - 1)
1450 next_slice_group_param = NULL;
1452 next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1454 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1455 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1457 if (i < decode_state->slice_params[j]->num_elements - 1)
1458 next_slice_param = slice_param + 1;
1460 next_slice_param = next_slice_group_param;
1462 gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1467 intel_batchbuffer_end_atomic(batch);
1468 intel_batchbuffer_flush(batch);
1471 static const int va_to_gen7_vc1_pic_type[5] = {
1475 GEN7_VC1_BI_PICTURE,
1479 static const int va_to_gen7_vc1_mv[4] = {
1481 2, /* 1-MV half-pel */
1482 3, /* 1-MV half-pef bilinear */
1486 static const int b_picture_scale_factor[21] = {
1487 128, 85, 170, 64, 192,
1488 51, 102, 153, 204, 43,
1489 215, 37, 74, 111, 148,
1490 185, 222, 32, 96, 160,
1494 static const int va_to_gen7_vc1_condover[3] = {
1500 static const int va_to_gen7_vc1_profile[4] = {
1501 GEN7_VC1_SIMPLE_PROFILE,
1502 GEN7_VC1_MAIN_PROFILE,
1503 GEN7_VC1_RESERVED_PROFILE,
1504 GEN7_VC1_ADVANCED_PROFILE
1508 gen75_mfd_free_vc1_surface(void **data)
1510 struct gen7_vc1_surface *gen7_vc1_surface = *data;
1512 if (!gen7_vc1_surface)
1515 dri_bo_unreference(gen7_vc1_surface->dmv);
1516 free(gen7_vc1_surface);
1521 gen75_mfd_init_vc1_surface(VADriverContextP ctx,
1522 VAPictureParameterBufferVC1 *pic_param,
1523 struct object_surface *obj_surface)
1525 struct i965_driver_data *i965 = i965_driver_data(ctx);
1526 struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1527 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1528 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1530 obj_surface->free_private_data = gen75_mfd_free_vc1_surface;
1532 if (!gen7_vc1_surface) {
1533 gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1534 assert((obj_surface->size & 0x3f) == 0);
1535 obj_surface->private_data = gen7_vc1_surface;
1538 gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1540 if (gen7_vc1_surface->dmv == NULL) {
1541 gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1542 "direct mv w/r buffer",
1543 width_in_mbs * height_in_mbs * 64,
1549 gen75_mfd_vc1_decode_init(VADriverContextP ctx,
1550 struct decode_state *decode_state,
1551 struct gen7_mfd_context *gen7_mfd_context)
1553 VAPictureParameterBufferVC1 *pic_param;
1554 struct i965_driver_data *i965 = i965_driver_data(ctx);
1555 struct object_surface *obj_surface;
1560 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1561 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1562 width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1563 picture_type = pic_param->picture_fields.bits.picture_type;
1565 intel_update_vc1_frame_store_index(ctx,
1568 gen7_mfd_context->reference_surface);
1570 /* Current decoded picture */
1571 obj_surface = decode_state->render_object;
1572 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
1573 gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1575 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1576 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1577 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1578 gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1580 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1581 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1582 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1583 gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1585 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1586 bo = dri_bo_alloc(i965->intel.bufmgr,
1591 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1592 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1594 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1595 bo = dri_bo_alloc(i965->intel.bufmgr,
1596 "deblocking filter row store",
1597 width_in_mbs * 7 * 64,
1600 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1601 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1603 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1604 bo = dri_bo_alloc(i965->intel.bufmgr,
1605 "bsd mpc row store",
1609 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1610 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1612 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1614 gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1615 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1617 if (gen7_mfd_context->bitplane_read_buffer.valid) {
1618 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1619 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1620 int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1622 uint8_t *src = NULL, *dst = NULL;
1624 assert(decode_state->bit_plane->buffer);
1625 src = decode_state->bit_plane->buffer;
1627 bo = dri_bo_alloc(i965->intel.bufmgr,
1629 bitplane_width * height_in_mbs,
1632 gen7_mfd_context->bitplane_read_buffer.bo = bo;
1634 dri_bo_map(bo, True);
1635 assert(bo->virtual);
1638 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1639 for(src_w = 0; src_w < width_in_mbs; src_w++) {
1640 int src_index, dst_index;
1644 src_index = (src_h * width_in_mbs + src_w) / 2;
1645 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1646 src_value = ((src[src_index] >> src_shift) & 0xf);
1648 if (picture_type == GEN7_VC1_SKIPPED_PICTURE){
1652 dst_index = src_w / 2;
1653 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1657 dst[src_w / 2] >>= 4;
1659 dst += bitplane_width;
1664 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1668 gen75_mfd_vc1_pic_state(VADriverContextP ctx,
1669 struct decode_state *decode_state,
1670 struct gen7_mfd_context *gen7_mfd_context)
1672 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1673 VAPictureParameterBufferVC1 *pic_param;
1674 struct object_surface *obj_surface;
1675 int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1676 int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1677 int unified_mv_mode;
1678 int ref_field_pic_polarity = 0;
1679 int scale_factor = 0;
1681 int dmv_surface_valid = 0;
1687 int interpolation_mode = 0;
1689 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1690 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1692 profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1693 dquant = pic_param->pic_quantizer_fields.bits.dquant;
1694 dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1695 dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1696 dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1697 dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1698 dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1699 alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1702 alt_pquant_config = 0;
1703 alt_pquant_edge_mask = 0;
1704 } else if (dquant == 2) {
1705 alt_pquant_config = 1;
1706 alt_pquant_edge_mask = 0xf;
1708 assert(dquant == 1);
1709 if (dquantfrm == 0) {
1710 alt_pquant_config = 0;
1711 alt_pquant_edge_mask = 0;
1714 assert(dquantfrm == 1);
1715 alt_pquant_config = 1;
1717 switch (dqprofile) {
1719 if (dqbilevel == 0) {
1720 alt_pquant_config = 2;
1721 alt_pquant_edge_mask = 0;
1723 assert(dqbilevel == 1);
1724 alt_pquant_config = 3;
1725 alt_pquant_edge_mask = 0;
1730 alt_pquant_edge_mask = 0xf;
1735 alt_pquant_edge_mask = 0x9;
1737 alt_pquant_edge_mask = (0x3 << dqdbedge);
1742 alt_pquant_edge_mask = (0x1 << dqsbedge);
1751 if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1752 assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1753 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1755 assert(pic_param->mv_fields.bits.mv_mode < 4);
1756 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1759 if (pic_param->sequence_fields.bits.interlace == 1 &&
1760 pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1761 /* FIXME: calculate reference field picture polarity */
1763 ref_field_pic_polarity = 0;
1766 if (pic_param->b_picture_fraction < 21)
1767 scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1769 picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1771 if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1772 picture_type == GEN7_VC1_I_PICTURE)
1773 picture_type = GEN7_VC1_BI_PICTURE;
1775 if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1776 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1778 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1781 * 8.3.6.2.1 Transform Type Selection
1782 * If variable-sized transform coding is not enabled,
1783 * then the 8x8 transform shall be used for all blocks.
1784 * it is also MFX_VC1_PIC_STATE requirement.
1786 if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1787 pic_param->transform_fields.bits.mb_level_transform_type_flag = 1;
1788 pic_param->transform_fields.bits.frame_level_transform_type = 0;
1792 if (picture_type == GEN7_VC1_B_PICTURE) {
1793 struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1795 obj_surface = decode_state->reference_objects[1];
1798 gen7_vc1_surface = obj_surface->private_data;
1800 if (!gen7_vc1_surface ||
1801 (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1802 va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1803 dmv_surface_valid = 0;
1805 dmv_surface_valid = 1;
1808 assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1810 if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1811 fcm = pic_param->picture_fields.bits.frame_coding_mode;
1813 if (pic_param->picture_fields.bits.top_field_first)
1819 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1820 brfd = pic_param->reference_fields.bits.reference_distance;
1821 brfd = (scale_factor * brfd) >> 8;
1822 brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1829 if (profile != GEN7_VC1_ADVANCED_PROFILE){
1830 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1831 pic_param->picture_fields.bits.picture_type != GEN7_VC1_B_PICTURE) {
1835 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_P_PICTURE &&
1836 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1839 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_I_PICTURE ||
1840 pic_param->picture_fields.bits.picture_type == GEN7_VC1_BI_PICTURE){
1841 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1843 } else if (va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1844 va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1850 assert(pic_param->conditional_overlap_flag < 3);
1851 assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1853 if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1854 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1855 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1856 interpolation_mode = 9; /* Half-pel bilinear */
1857 else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1858 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1859 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1860 interpolation_mode = 1; /* Half-pel bicubic */
1862 interpolation_mode = 0; /* Quarter-pel bicubic */
1864 BEGIN_BCS_BATCH(batch, 6);
1865 OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
1866 OUT_BCS_BATCH(batch,
1867 (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
1868 ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
1869 OUT_BCS_BATCH(batch,
1870 ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
1871 dmv_surface_valid << 15 |
1872 (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
1873 pic_param->rounding_control << 13 |
1874 pic_param->sequence_fields.bits.syncmarker << 12 |
1875 interpolation_mode << 8 |
1876 0 << 7 | /* FIXME: scale up or down ??? */
1877 pic_param->range_reduction_frame << 6 |
1878 pic_param->entrypoint_fields.bits.loopfilter << 5 |
1880 !pic_param->picture_fields.bits.is_first_field << 3 |
1881 (pic_param->sequence_fields.bits.profile == 3) << 0);
1882 OUT_BCS_BATCH(batch,
1883 va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
1884 picture_type << 26 |
1887 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
1889 OUT_BCS_BATCH(batch,
1890 unified_mv_mode << 28 |
1891 pic_param->mv_fields.bits.four_mv_switch << 27 |
1892 pic_param->fast_uvmc_flag << 26 |
1893 ref_field_pic_polarity << 25 |
1894 pic_param->reference_fields.bits.num_reference_pictures << 24 |
1895 pic_param->reference_fields.bits.reference_distance << 20 |
1896 pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
1897 pic_param->mv_fields.bits.extended_dmv_range << 10 |
1898 pic_param->mv_fields.bits.extended_mv_range << 8 |
1899 alt_pquant_edge_mask << 4 |
1900 alt_pquant_config << 2 |
1901 pic_param->pic_quantizer_fields.bits.half_qp << 1 |
1902 pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
1903 OUT_BCS_BATCH(batch,
1904 !!pic_param->bitplane_present.value << 31 |
1905 !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
1906 !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
1907 !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
1908 !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
1909 !pic_param->bitplane_present.flags.bp_overflags << 26 |
1910 !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
1911 !pic_param->bitplane_present.flags.bp_field_tx << 24 |
1912 pic_param->mv_fields.bits.mv_table << 20 |
1913 pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1914 pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1915 pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1916 pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1917 pic_param->mb_mode_table << 8 |
1919 pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1920 pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1921 pic_param->cbp_table << 0);
1922 ADVANCE_BCS_BATCH(batch);
1926 gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1927 struct decode_state *decode_state,
1928 struct gen7_mfd_context *gen7_mfd_context)
1930 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1931 VAPictureParameterBufferVC1 *pic_param;
1932 int intensitycomp_single;
1934 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1935 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1937 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1938 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1939 intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1941 BEGIN_BCS_BATCH(batch, 6);
1942 OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
1943 OUT_BCS_BATCH(batch,
1944 0 << 14 | /* FIXME: double ??? */
1946 intensitycomp_single << 10 |
1947 intensitycomp_single << 8 |
1948 0 << 4 | /* FIXME: interlace mode */
1950 OUT_BCS_BATCH(batch,
1951 pic_param->luma_shift << 16 |
1952 pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1953 OUT_BCS_BATCH(batch, 0);
1954 OUT_BCS_BATCH(batch, 0);
1955 OUT_BCS_BATCH(batch, 0);
1956 ADVANCE_BCS_BATCH(batch);
1960 gen75_mfd_vc1_directmode_state_bplus(VADriverContextP ctx,
1961 struct decode_state *decode_state,
1962 struct gen7_mfd_context *gen7_mfd_context)
1964 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1965 struct object_surface *obj_surface;
1966 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1968 obj_surface = decode_state->render_object;
1970 if (obj_surface && obj_surface->private_data) {
1971 dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1974 obj_surface = decode_state->reference_objects[1];
1976 if (obj_surface && obj_surface->private_data) {
1977 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
1980 BEGIN_BCS_BATCH(batch, 7);
1981 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2));
1983 if (dmv_write_buffer)
1984 OUT_BCS_RELOC(batch, dmv_write_buffer,
1985 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1988 OUT_BCS_BATCH(batch, 0);
1990 OUT_BCS_BATCH(batch, 0);
1991 OUT_BCS_BATCH(batch, 0);
1993 if (dmv_read_buffer)
1994 OUT_BCS_RELOC(batch, dmv_read_buffer,
1995 I915_GEM_DOMAIN_INSTRUCTION, 0,
1998 OUT_BCS_BATCH(batch, 0);
1999 OUT_BCS_BATCH(batch, 0);
2000 OUT_BCS_BATCH(batch, 0);
2002 ADVANCE_BCS_BATCH(batch);
2006 gen75_mfd_vc1_directmode_state(VADriverContextP ctx,
2007 struct decode_state *decode_state,
2008 struct gen7_mfd_context *gen7_mfd_context)
2010 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2011 struct i965_driver_data *i965 = i965_driver_data(ctx);
2012 struct object_surface *obj_surface;
2013 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2015 if (IS_STEPPING_BPLUS(i965)) {
2016 gen75_mfd_vc1_directmode_state_bplus(ctx, decode_state, gen7_mfd_context);
2020 obj_surface = decode_state->render_object;
2022 if (obj_surface && obj_surface->private_data) {
2023 dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2026 obj_surface = decode_state->reference_objects[1];
2028 if (obj_surface && obj_surface->private_data) {
2029 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2032 BEGIN_BCS_BATCH(batch, 3);
2033 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
2035 if (dmv_write_buffer)
2036 OUT_BCS_RELOC(batch, dmv_write_buffer,
2037 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2040 OUT_BCS_BATCH(batch, 0);
2042 if (dmv_read_buffer)
2043 OUT_BCS_RELOC(batch, dmv_read_buffer,
2044 I915_GEM_DOMAIN_INSTRUCTION, 0,
2047 OUT_BCS_BATCH(batch, 0);
2049 ADVANCE_BCS_BATCH(batch);
2053 gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
2055 int out_slice_data_bit_offset;
2056 int slice_header_size = in_slice_data_bit_offset / 8;
2060 out_slice_data_bit_offset = in_slice_data_bit_offset;
2062 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
2063 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
2068 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
2071 return out_slice_data_bit_offset;
2075 gen75_mfd_vc1_bsd_object(VADriverContextP ctx,
2076 VAPictureParameterBufferVC1 *pic_param,
2077 VASliceParameterBufferVC1 *slice_param,
2078 VASliceParameterBufferVC1 *next_slice_param,
2079 dri_bo *slice_data_bo,
2080 struct gen7_mfd_context *gen7_mfd_context)
2082 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2083 int next_slice_start_vert_pos;
2084 int macroblock_offset;
2085 uint8_t *slice_data = NULL;
2087 dri_bo_map(slice_data_bo, 0);
2088 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
2089 macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data,
2090 slice_param->macroblock_offset,
2091 pic_param->sequence_fields.bits.profile);
2092 dri_bo_unmap(slice_data_bo);
2094 if (next_slice_param)
2095 next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
2097 next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
2099 BEGIN_BCS_BATCH(batch, 5);
2100 OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
2101 OUT_BCS_BATCH(batch,
2102 slice_param->slice_data_size - (macroblock_offset >> 3));
2103 OUT_BCS_BATCH(batch,
2104 slice_param->slice_data_offset + (macroblock_offset >> 3));
2105 OUT_BCS_BATCH(batch,
2106 slice_param->slice_vertical_position << 16 |
2107 next_slice_start_vert_pos << 0);
2108 OUT_BCS_BATCH(batch,
2109 (macroblock_offset & 0x7));
2110 ADVANCE_BCS_BATCH(batch);
2114 gen75_mfd_vc1_decode_picture(VADriverContextP ctx,
2115 struct decode_state *decode_state,
2116 struct gen7_mfd_context *gen7_mfd_context)
2118 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2119 VAPictureParameterBufferVC1 *pic_param;
2120 VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2121 dri_bo *slice_data_bo;
2124 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2125 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2127 gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2128 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2129 intel_batchbuffer_emit_mi_flush(batch);
2130 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2131 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2132 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2133 gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2134 gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2135 gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2136 gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2138 for (j = 0; j < decode_state->num_slice_params; j++) {
2139 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2140 slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2141 slice_data_bo = decode_state->slice_datas[j]->bo;
2142 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2144 if (j == decode_state->num_slice_params - 1)
2145 next_slice_group_param = NULL;
2147 next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2149 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2150 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2152 if (i < decode_state->slice_params[j]->num_elements - 1)
2153 next_slice_param = slice_param + 1;
2155 next_slice_param = next_slice_group_param;
2157 gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2162 intel_batchbuffer_end_atomic(batch);
2163 intel_batchbuffer_flush(batch);
2167 gen75_mfd_jpeg_decode_init(VADriverContextP ctx,
2168 struct decode_state *decode_state,
2169 struct gen7_mfd_context *gen7_mfd_context)
2171 struct object_surface *obj_surface;
2172 VAPictureParameterBufferJPEGBaseline *pic_param;
2173 int subsampling = SUBSAMPLE_YUV420;
2174 int fourcc = VA_FOURCC_IMC3;
2176 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2178 if (pic_param->num_components == 1) {
2179 subsampling = SUBSAMPLE_YUV400;
2180 fourcc = VA_FOURCC_Y800;
2181 } else if (pic_param->num_components == 3) {
2182 int h1 = pic_param->components[0].h_sampling_factor;
2183 int h2 = pic_param->components[1].h_sampling_factor;
2184 int h3 = pic_param->components[2].h_sampling_factor;
2185 int v1 = pic_param->components[0].v_sampling_factor;
2186 int v2 = pic_param->components[1].v_sampling_factor;
2187 int v3 = pic_param->components[2].v_sampling_factor;
2189 if (h1 == 2 && h2 == 1 && h3 == 1 &&
2190 v1 == 2 && v2 == 1 && v3 == 1) {
2191 subsampling = SUBSAMPLE_YUV420;
2192 fourcc = VA_FOURCC_IMC3;
2193 } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2194 v1 == 1 && v2 == 1 && v3 == 1) {
2195 subsampling = SUBSAMPLE_YUV422H;
2196 fourcc = VA_FOURCC_422H;
2197 } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2198 v1 == 1 && v2 == 1 && v3 == 1) {
2199 subsampling = SUBSAMPLE_YUV444;
2200 fourcc = VA_FOURCC_444P;
2201 } else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2202 v1 == 1 && v2 == 1 && v3 == 1) {
2203 subsampling = SUBSAMPLE_YUV411;
2204 fourcc = VA_FOURCC_411P;
2205 } else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2206 v1 == 2 && v2 == 1 && v3 == 1) {
2207 subsampling = SUBSAMPLE_YUV422V;
2208 fourcc = VA_FOURCC_422V;
2209 } else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2210 v1 == 2 && v2 == 2 && v3 == 2) {
2211 subsampling = SUBSAMPLE_YUV422H;
2212 fourcc = VA_FOURCC_422H;
2213 } else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2214 v1 == 2 && v2 == 1 && v3 == 1) {
2215 subsampling = SUBSAMPLE_YUV422V;
2216 fourcc = VA_FOURCC_422V;
2223 /* Current decoded picture */
2224 obj_surface = decode_state->render_object;
2225 i965_check_alloc_surface_bo(ctx, obj_surface, 1, fourcc, subsampling);
2227 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2228 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2229 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2230 gen7_mfd_context->pre_deblocking_output.valid = 1;
2232 gen7_mfd_context->post_deblocking_output.bo = NULL;
2233 gen7_mfd_context->post_deblocking_output.valid = 0;
2235 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2236 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2238 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2239 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2241 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2242 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2244 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2245 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2247 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2248 gen7_mfd_context->bitplane_read_buffer.valid = 0;
2251 static const int va_to_gen7_jpeg_rotation[4] = {
2252 GEN7_JPEG_ROTATION_0,
2253 GEN7_JPEG_ROTATION_90,
2254 GEN7_JPEG_ROTATION_180,
2255 GEN7_JPEG_ROTATION_270
2259 gen75_mfd_jpeg_pic_state(VADriverContextP ctx,
2260 struct decode_state *decode_state,
2261 struct gen7_mfd_context *gen7_mfd_context)
2263 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2264 VAPictureParameterBufferJPEGBaseline *pic_param;
2265 int chroma_type = GEN7_YUV420;
2266 int frame_width_in_blks;
2267 int frame_height_in_blks;
2269 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2270 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2272 if (pic_param->num_components == 1)
2273 chroma_type = GEN7_YUV400;
2274 else if (pic_param->num_components == 3) {
2275 int h1 = pic_param->components[0].h_sampling_factor;
2276 int h2 = pic_param->components[1].h_sampling_factor;
2277 int h3 = pic_param->components[2].h_sampling_factor;
2278 int v1 = pic_param->components[0].v_sampling_factor;
2279 int v2 = pic_param->components[1].v_sampling_factor;
2280 int v3 = pic_param->components[2].v_sampling_factor;
2282 if (h1 == 2 && h2 == 1 && h3 == 1 &&
2283 v1 == 2 && v2 == 1 && v3 == 1)
2284 chroma_type = GEN7_YUV420;
2285 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2286 v1 == 1 && v2 == 1 && v3 == 1)
2287 chroma_type = GEN7_YUV422H_2Y;
2288 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2289 v1 == 1 && v2 == 1 && v3 == 1)
2290 chroma_type = GEN7_YUV444;
2291 else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2292 v1 == 1 && v2 == 1 && v3 == 1)
2293 chroma_type = GEN7_YUV411;
2294 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2295 v1 == 2 && v2 == 1 && v3 == 1)
2296 chroma_type = GEN7_YUV422V_2Y;
2297 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2298 v1 == 2 && v2 == 2 && v3 == 2)
2299 chroma_type = GEN7_YUV422H_4Y;
2300 else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2301 v1 == 2 && v2 == 1 && v3 == 1)
2302 chroma_type = GEN7_YUV422V_4Y;
2307 if (chroma_type == GEN7_YUV400 ||
2308 chroma_type == GEN7_YUV444 ||
2309 chroma_type == GEN7_YUV422V_2Y) {
2310 frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2311 frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2312 } else if (chroma_type == GEN7_YUV411) {
2313 frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2314 frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2316 frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2317 frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2320 BEGIN_BCS_BATCH(batch, 3);
2321 OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2322 OUT_BCS_BATCH(batch,
2323 (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */
2324 (chroma_type << 0));
2325 OUT_BCS_BATCH(batch,
2326 ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */
2327 ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */
2328 ADVANCE_BCS_BATCH(batch);
2331 static const int va_to_gen7_jpeg_hufftable[2] = {
2337 gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2338 struct decode_state *decode_state,
2339 struct gen7_mfd_context *gen7_mfd_context,
2342 VAHuffmanTableBufferJPEGBaseline *huffman_table;
2343 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2346 if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2349 huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2351 for (index = 0; index < num_tables; index++) {
2352 int id = va_to_gen7_jpeg_hufftable[index];
2354 if (!huffman_table->load_huffman_table[index])
2357 BEGIN_BCS_BATCH(batch, 53);
2358 OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2359 OUT_BCS_BATCH(batch, id);
2360 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2361 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2362 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2363 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2364 ADVANCE_BCS_BATCH(batch);
2368 static const int va_to_gen7_jpeg_qm[5] = {
2370 MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2371 MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2372 MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2373 MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2377 gen75_mfd_jpeg_qm_state(VADriverContextP ctx,
2378 struct decode_state *decode_state,
2379 struct gen7_mfd_context *gen7_mfd_context)
2381 VAPictureParameterBufferJPEGBaseline *pic_param;
2382 VAIQMatrixBufferJPEGBaseline *iq_matrix;
2385 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2388 iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2389 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2391 assert(pic_param->num_components <= 3);
2393 for (index = 0; index < pic_param->num_components; index++) {
2394 int id = pic_param->components[index].component_id - pic_param->components[0].component_id + 1;
2396 unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2397 unsigned char raster_qm[64];
2400 if (id > 4 || id < 1)
2403 if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2406 qm_type = va_to_gen7_jpeg_qm[id];
2408 for (j = 0; j < 64; j++)
2409 raster_qm[zigzag_direct[j]] = qm[j];
2411 gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2416 gen75_mfd_jpeg_bsd_object(VADriverContextP ctx,
2417 VAPictureParameterBufferJPEGBaseline *pic_param,
2418 VASliceParameterBufferJPEGBaseline *slice_param,
2419 VASliceParameterBufferJPEGBaseline *next_slice_param,
2420 dri_bo *slice_data_bo,
2421 struct gen7_mfd_context *gen7_mfd_context)
2423 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2424 int scan_component_mask = 0;
2427 assert(slice_param->num_components > 0);
2428 assert(slice_param->num_components < 4);
2429 assert(slice_param->num_components <= pic_param->num_components);
2431 for (i = 0; i < slice_param->num_components; i++) {
2432 switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2434 scan_component_mask |= (1 << 0);
2437 scan_component_mask |= (1 << 1);
2440 scan_component_mask |= (1 << 2);
2448 BEGIN_BCS_BATCH(batch, 6);
2449 OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2450 OUT_BCS_BATCH(batch,
2451 slice_param->slice_data_size);
2452 OUT_BCS_BATCH(batch,
2453 slice_param->slice_data_offset);
2454 OUT_BCS_BATCH(batch,
2455 slice_param->slice_horizontal_position << 16 |
2456 slice_param->slice_vertical_position << 0);
2457 OUT_BCS_BATCH(batch,
2458 ((slice_param->num_components != 1) << 30) | /* interleaved */
2459 (scan_component_mask << 27) | /* scan components */
2460 (0 << 26) | /* disable interrupt allowed */
2461 (slice_param->num_mcus << 0)); /* MCU count */
2462 OUT_BCS_BATCH(batch,
2463 (slice_param->restart_interval << 0)); /* RestartInterval */
2464 ADVANCE_BCS_BATCH(batch);
2467 /* Workaround for JPEG decoding on Ivybridge */
2470 i965_CreateSurfaces(VADriverContextP ctx,
2475 VASurfaceID *surfaces);
2480 unsigned char data[32];
2482 int data_bit_offset;
2484 } gen7_jpeg_wa_clip = {
2488 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2489 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2497 gen75_jpeg_wa_init(VADriverContextP ctx,
2498 struct gen7_mfd_context *gen7_mfd_context)
2500 struct i965_driver_data *i965 = i965_driver_data(ctx);
2502 struct object_surface *obj_surface;
2504 if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2505 i965_DestroySurfaces(ctx,
2506 &gen7_mfd_context->jpeg_wa_surface_id,
2509 status = i965_CreateSurfaces(ctx,
2510 gen7_jpeg_wa_clip.width,
2511 gen7_jpeg_wa_clip.height,
2512 VA_RT_FORMAT_YUV420,
2514 &gen7_mfd_context->jpeg_wa_surface_id);
2515 assert(status == VA_STATUS_SUCCESS);
2517 obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2518 assert(obj_surface);
2519 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
2520 gen7_mfd_context->jpeg_wa_surface_object = obj_surface;
2522 if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2523 gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2527 dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2529 gen7_jpeg_wa_clip.data_size,
2530 gen7_jpeg_wa_clip.data);
2535 gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2536 struct gen7_mfd_context *gen7_mfd_context)
2538 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2540 BEGIN_BCS_BATCH(batch, 5);
2541 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2542 OUT_BCS_BATCH(batch,
2543 (MFX_LONG_MODE << 17) | /* Currently only support long format */
2544 (MFD_MODE_VLD << 15) | /* VLD mode */
2545 (0 << 10) | /* disable Stream-Out */
2546 (0 << 9) | /* Post Deblocking Output */
2547 (1 << 8) | /* Pre Deblocking Output */
2548 (0 << 5) | /* not in stitch mode */
2549 (MFX_CODEC_DECODE << 4) | /* decoding mode */
2550 (MFX_FORMAT_AVC << 0));
2551 OUT_BCS_BATCH(batch,
2552 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
2553 (0 << 3) | /* terminate if AVC mbdata error occurs */
2554 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
2557 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2558 OUT_BCS_BATCH(batch, 0); /* reserved */
2559 ADVANCE_BCS_BATCH(batch);
2563 gen75_jpeg_wa_surface_state(VADriverContextP ctx,
2564 struct gen7_mfd_context *gen7_mfd_context)
2566 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2567 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2569 BEGIN_BCS_BATCH(batch, 6);
2570 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2571 OUT_BCS_BATCH(batch, 0);
2572 OUT_BCS_BATCH(batch,
2573 ((obj_surface->orig_width - 1) << 18) |
2574 ((obj_surface->orig_height - 1) << 4));
2575 OUT_BCS_BATCH(batch,
2576 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2577 (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2578 (0 << 22) | /* surface object control state, ignored */
2579 ((obj_surface->width - 1) << 3) | /* pitch */
2580 (0 << 2) | /* must be 0 */
2581 (1 << 1) | /* must be tiled */
2582 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
2583 OUT_BCS_BATCH(batch,
2584 (0 << 16) | /* X offset for U(Cb), must be 0 */
2585 (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2586 OUT_BCS_BATCH(batch,
2587 (0 << 16) | /* X offset for V(Cr), must be 0 */
2588 (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2589 ADVANCE_BCS_BATCH(batch);
2593 gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx,
2594 struct gen7_mfd_context *gen7_mfd_context)
2596 struct i965_driver_data *i965 = i965_driver_data(ctx);
2597 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2598 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2602 intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2607 BEGIN_BCS_BATCH(batch, 61);
2608 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
2609 OUT_BCS_RELOC(batch,
2611 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2613 OUT_BCS_BATCH(batch, 0);
2614 OUT_BCS_BATCH(batch, 0);
2617 OUT_BCS_BATCH(batch, 0); /* post deblocking */
2618 OUT_BCS_BATCH(batch, 0);
2619 OUT_BCS_BATCH(batch, 0);
2621 /* uncompressed-video & stream out 7-12 */
2622 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2623 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2624 OUT_BCS_BATCH(batch, 0);
2625 OUT_BCS_BATCH(batch, 0);
2626 OUT_BCS_BATCH(batch, 0);
2627 OUT_BCS_BATCH(batch, 0);
2629 /* the DW 13-15 is for intra row store scratch */
2630 OUT_BCS_RELOC(batch,
2632 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2634 OUT_BCS_BATCH(batch, 0);
2635 OUT_BCS_BATCH(batch, 0);
2637 /* the DW 16-18 is for deblocking filter */
2638 OUT_BCS_BATCH(batch, 0);
2639 OUT_BCS_BATCH(batch, 0);
2640 OUT_BCS_BATCH(batch, 0);
2643 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2644 OUT_BCS_BATCH(batch, 0);
2645 OUT_BCS_BATCH(batch, 0);
2647 OUT_BCS_BATCH(batch, 0);
2649 /* the DW52-54 is for mb status address */
2650 OUT_BCS_BATCH(batch, 0);
2651 OUT_BCS_BATCH(batch, 0);
2652 OUT_BCS_BATCH(batch, 0);
2653 /* the DW56-60 is for ILDB & second ILDB address */
2654 OUT_BCS_BATCH(batch, 0);
2655 OUT_BCS_BATCH(batch, 0);
2656 OUT_BCS_BATCH(batch, 0);
2657 OUT_BCS_BATCH(batch, 0);
2658 OUT_BCS_BATCH(batch, 0);
2659 OUT_BCS_BATCH(batch, 0);
2661 ADVANCE_BCS_BATCH(batch);
2663 dri_bo_unreference(intra_bo);
2667 gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2668 struct gen7_mfd_context *gen7_mfd_context)
2670 struct i965_driver_data *i965 = i965_driver_data(ctx);
2671 struct object_surface *obj_surface = gen7_mfd_context->jpeg_wa_surface_object;
2672 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2676 if (IS_STEPPING_BPLUS(i965)) {
2677 gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context);
2681 intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2686 BEGIN_BCS_BATCH(batch, 25);
2687 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
2688 OUT_BCS_RELOC(batch,
2690 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2693 OUT_BCS_BATCH(batch, 0); /* post deblocking */
2695 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2696 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2698 OUT_BCS_RELOC(batch,
2700 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2703 OUT_BCS_BATCH(batch, 0);
2706 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2707 OUT_BCS_BATCH(batch, 0);
2710 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
2711 OUT_BCS_BATCH(batch, 0);
2712 ADVANCE_BCS_BATCH(batch);
2714 dri_bo_unreference(intra_bo);
2718 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
2719 struct gen7_mfd_context *gen7_mfd_context)
2721 struct i965_driver_data *i965 = i965_driver_data(ctx);
2722 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2723 dri_bo *bsd_mpc_bo, *mpr_bo;
2725 bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2726 "bsd mpc row store",
2727 11520, /* 1.5 * 120 * 64 */
2730 mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2732 7680, /* 1. 0 * 120 * 64 */
2735 BEGIN_BCS_BATCH(batch, 10);
2736 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
2738 OUT_BCS_RELOC(batch,
2740 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2743 OUT_BCS_BATCH(batch, 0);
2744 OUT_BCS_BATCH(batch, 0);
2746 OUT_BCS_RELOC(batch,
2748 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2750 OUT_BCS_BATCH(batch, 0);
2751 OUT_BCS_BATCH(batch, 0);
2753 OUT_BCS_BATCH(batch, 0);
2754 OUT_BCS_BATCH(batch, 0);
2755 OUT_BCS_BATCH(batch, 0);
2757 ADVANCE_BCS_BATCH(batch);
2759 dri_bo_unreference(bsd_mpc_bo);
2760 dri_bo_unreference(mpr_bo);
2764 gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2765 struct gen7_mfd_context *gen7_mfd_context)
2767 struct i965_driver_data *i965 = i965_driver_data(ctx);
2768 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2769 dri_bo *bsd_mpc_bo, *mpr_bo;
2771 if (IS_STEPPING_BPLUS(i965)) {
2772 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(ctx, gen7_mfd_context);
2776 bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2777 "bsd mpc row store",
2778 11520, /* 1.5 * 120 * 64 */
2781 mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2783 7680, /* 1. 0 * 120 * 64 */
2786 BEGIN_BCS_BATCH(batch, 4);
2787 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2789 OUT_BCS_RELOC(batch,
2791 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2794 OUT_BCS_RELOC(batch,
2796 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2798 OUT_BCS_BATCH(batch, 0);
2800 ADVANCE_BCS_BATCH(batch);
2802 dri_bo_unreference(bsd_mpc_bo);
2803 dri_bo_unreference(mpr_bo);
2807 gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2808 struct gen7_mfd_context *gen7_mfd_context)
2814 gen75_jpeg_wa_avc_img_state(VADriverContextP ctx,
2815 struct gen7_mfd_context *gen7_mfd_context)
2817 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2819 int mbaff_frame_flag = 0;
2820 unsigned int width_in_mbs = 1, height_in_mbs = 1;
2822 BEGIN_BCS_BATCH(batch, 16);
2823 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2824 OUT_BCS_BATCH(batch,
2825 (width_in_mbs * height_in_mbs - 1));
2826 OUT_BCS_BATCH(batch,
2827 ((height_in_mbs - 1) << 16) |
2828 ((width_in_mbs - 1) << 0));
2829 OUT_BCS_BATCH(batch,
2834 (0 << 12) | /* differ from GEN6 */
2837 OUT_BCS_BATCH(batch,
2838 (1 << 10) | /* 4:2:0 */
2839 (1 << 7) | /* CABAC */
2845 (mbaff_frame_flag << 1) |
2847 OUT_BCS_BATCH(batch, 0);
2848 OUT_BCS_BATCH(batch, 0);
2849 OUT_BCS_BATCH(batch, 0);
2850 OUT_BCS_BATCH(batch, 0);
2851 OUT_BCS_BATCH(batch, 0);
2852 OUT_BCS_BATCH(batch, 0);
2853 OUT_BCS_BATCH(batch, 0);
2854 OUT_BCS_BATCH(batch, 0);
2855 OUT_BCS_BATCH(batch, 0);
2856 OUT_BCS_BATCH(batch, 0);
2857 OUT_BCS_BATCH(batch, 0);
2858 ADVANCE_BCS_BATCH(batch);
2862 gen75_jpeg_wa_avc_directmode_state_bplus(VADriverContextP ctx,
2863 struct gen7_mfd_context *gen7_mfd_context)
2865 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2868 BEGIN_BCS_BATCH(batch, 71);
2869 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
2871 /* reference surfaces 0..15 */
2872 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2873 OUT_BCS_BATCH(batch, 0); /* top */
2874 OUT_BCS_BATCH(batch, 0); /* bottom */
2877 OUT_BCS_BATCH(batch, 0);
2879 /* the current decoding frame/field */
2880 OUT_BCS_BATCH(batch, 0); /* top */
2881 OUT_BCS_BATCH(batch, 0);
2882 OUT_BCS_BATCH(batch, 0);
2885 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2886 OUT_BCS_BATCH(batch, 0);
2887 OUT_BCS_BATCH(batch, 0);
2890 OUT_BCS_BATCH(batch, 0);
2891 OUT_BCS_BATCH(batch, 0);
2893 ADVANCE_BCS_BATCH(batch);
2897 gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
2898 struct gen7_mfd_context *gen7_mfd_context)
2900 struct i965_driver_data *i965 = i965_driver_data(ctx);
2901 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2904 if (IS_STEPPING_BPLUS(i965)) {
2905 gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context);
2909 BEGIN_BCS_BATCH(batch, 69);
2910 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
2912 /* reference surfaces 0..15 */
2913 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2914 OUT_BCS_BATCH(batch, 0); /* top */
2915 OUT_BCS_BATCH(batch, 0); /* bottom */
2918 /* the current decoding frame/field */
2919 OUT_BCS_BATCH(batch, 0); /* top */
2920 OUT_BCS_BATCH(batch, 0); /* bottom */
2923 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2924 OUT_BCS_BATCH(batch, 0);
2925 OUT_BCS_BATCH(batch, 0);
2928 OUT_BCS_BATCH(batch, 0);
2929 OUT_BCS_BATCH(batch, 0);
2931 ADVANCE_BCS_BATCH(batch);
2935 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
2936 struct gen7_mfd_context *gen7_mfd_context)
2938 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2940 BEGIN_BCS_BATCH(batch, 11);
2941 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2942 OUT_BCS_RELOC(batch,
2943 gen7_mfd_context->jpeg_wa_slice_data_bo,
2944 I915_GEM_DOMAIN_INSTRUCTION, 0,
2946 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2947 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2948 OUT_BCS_BATCH(batch, 0);
2949 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2950 OUT_BCS_BATCH(batch, 0);
2951 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2952 OUT_BCS_BATCH(batch, 0);
2953 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2954 OUT_BCS_BATCH(batch, 0);
2955 ADVANCE_BCS_BATCH(batch);
2959 gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
2960 struct gen7_mfd_context *gen7_mfd_context)
2962 struct i965_driver_data *i965 = i965_driver_data(ctx);
2963 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2965 if (IS_STEPPING_BPLUS(i965)) {
2966 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context);
2970 BEGIN_BCS_BATCH(batch, 11);
2971 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
2972 OUT_BCS_RELOC(batch,
2973 gen7_mfd_context->jpeg_wa_slice_data_bo,
2974 I915_GEM_DOMAIN_INSTRUCTION, 0,
2976 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
2977 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2978 OUT_BCS_BATCH(batch, 0);
2979 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2980 OUT_BCS_BATCH(batch, 0);
2981 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2982 OUT_BCS_BATCH(batch, 0);
2983 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
2984 OUT_BCS_BATCH(batch, 0);
2985 ADVANCE_BCS_BATCH(batch);
2989 gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
2990 struct gen7_mfd_context *gen7_mfd_context)
2992 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2994 /* the input bitsteam format on GEN7 differs from GEN6 */
2995 BEGIN_BCS_BATCH(batch, 6);
2996 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
2997 OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
2998 OUT_BCS_BATCH(batch, 0);
2999 OUT_BCS_BATCH(batch,
3005 OUT_BCS_BATCH(batch,
3006 ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
3009 (1 << 3) | /* LastSlice Flag */
3010 (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
3011 OUT_BCS_BATCH(batch, 0);
3012 ADVANCE_BCS_BATCH(batch);
3016 gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx,
3017 struct gen7_mfd_context *gen7_mfd_context)
3019 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3020 int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
3021 int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
3022 int first_mb_in_slice = 0;
3023 int slice_type = SLICE_TYPE_I;
3025 BEGIN_BCS_BATCH(batch, 11);
3026 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
3027 OUT_BCS_BATCH(batch, slice_type);
3028 OUT_BCS_BATCH(batch,
3029 (num_ref_idx_l1 << 24) |
3030 (num_ref_idx_l0 << 16) |
3033 OUT_BCS_BATCH(batch,
3035 (1 << 27) | /* disable Deblocking */
3037 (gen7_jpeg_wa_clip.qp << 16) |
3040 OUT_BCS_BATCH(batch,
3041 (slice_ver_pos << 24) |
3042 (slice_hor_pos << 16) |
3043 (first_mb_in_slice << 0));
3044 OUT_BCS_BATCH(batch,
3045 (next_slice_ver_pos << 16) |
3046 (next_slice_hor_pos << 0));
3047 OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
3048 OUT_BCS_BATCH(batch, 0);
3049 OUT_BCS_BATCH(batch, 0);
3050 OUT_BCS_BATCH(batch, 0);
3051 OUT_BCS_BATCH(batch, 0);
3052 ADVANCE_BCS_BATCH(batch);
3056 gen75_mfd_jpeg_wa(VADriverContextP ctx,
3057 struct gen7_mfd_context *gen7_mfd_context)
3059 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3060 gen75_jpeg_wa_init(ctx, gen7_mfd_context);
3061 intel_batchbuffer_emit_mi_flush(batch);
3062 gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
3063 gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context);
3064 gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
3065 gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
3066 gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
3067 gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
3068 gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
3070 gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
3071 gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
3072 gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
3076 gen75_mfd_jpeg_decode_picture(VADriverContextP ctx,
3077 struct decode_state *decode_state,
3078 struct gen7_mfd_context *gen7_mfd_context)
3080 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3081 VAPictureParameterBufferJPEGBaseline *pic_param;
3082 VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
3083 dri_bo *slice_data_bo;
3084 int i, j, max_selector = 0;
3086 assert(decode_state->pic_param && decode_state->pic_param->buffer);
3087 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
3089 /* Currently only support Baseline DCT */
3090 gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
3091 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
3092 gen75_mfd_jpeg_wa(ctx, gen7_mfd_context);
3093 intel_batchbuffer_emit_mi_flush(batch);
3094 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3095 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3096 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3097 gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
3098 gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
3100 for (j = 0; j < decode_state->num_slice_params; j++) {
3101 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3102 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3103 slice_data_bo = decode_state->slice_datas[j]->bo;
3104 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3106 if (j == decode_state->num_slice_params - 1)
3107 next_slice_group_param = NULL;
3109 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3111 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3114 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3116 if (i < decode_state->slice_params[j]->num_elements - 1)
3117 next_slice_param = slice_param + 1;
3119 next_slice_param = next_slice_group_param;
3121 for (component = 0; component < slice_param->num_components; component++) {
3122 if (max_selector < slice_param->components[component].dc_table_selector)
3123 max_selector = slice_param->components[component].dc_table_selector;
3125 if (max_selector < slice_param->components[component].ac_table_selector)
3126 max_selector = slice_param->components[component].ac_table_selector;
3133 assert(max_selector < 2);
3134 gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
3136 for (j = 0; j < decode_state->num_slice_params; j++) {
3137 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3138 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3139 slice_data_bo = decode_state->slice_datas[j]->bo;
3140 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3142 if (j == decode_state->num_slice_params - 1)
3143 next_slice_group_param = NULL;
3145 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3147 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3148 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3150 if (i < decode_state->slice_params[j]->num_elements - 1)
3151 next_slice_param = slice_param + 1;
3153 next_slice_param = next_slice_group_param;
3155 gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
3160 intel_batchbuffer_end_atomic(batch);
3161 intel_batchbuffer_flush(batch);
3165 gen75_mfd_decode_picture(VADriverContextP ctx,
3167 union codec_state *codec_state,
3168 struct hw_context *hw_context)
3171 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3172 struct decode_state *decode_state = &codec_state->decode;
3175 assert(gen7_mfd_context);
3177 vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
3179 if (vaStatus != VA_STATUS_SUCCESS)
3182 gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
3185 case VAProfileMPEG2Simple:
3186 case VAProfileMPEG2Main:
3187 gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
3190 case VAProfileH264ConstrainedBaseline:
3191 case VAProfileH264Main:
3192 case VAProfileH264High:
3193 gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
3196 case VAProfileVC1Simple:
3197 case VAProfileVC1Main:
3198 case VAProfileVC1Advanced:
3199 gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
3202 case VAProfileJPEGBaseline:
3203 gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
3211 vaStatus = VA_STATUS_SUCCESS;
3218 gen75_mfd_context_destroy(void *hw_context)
3220 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3222 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
3223 gen7_mfd_context->post_deblocking_output.bo = NULL;
3225 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
3226 gen7_mfd_context->pre_deblocking_output.bo = NULL;
3228 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
3229 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
3231 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
3232 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
3234 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
3235 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
3237 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
3238 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
3240 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
3241 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
3243 dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
3245 intel_batchbuffer_free(gen7_mfd_context->base.batch);
3246 free(gen7_mfd_context);
3249 static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx,
3250 struct gen7_mfd_context *gen7_mfd_context)
3252 gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
3253 gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
3254 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
3255 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
3259 gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
3261 struct intel_driver_data *intel = intel_driver_data(ctx);
3262 struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
3265 gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
3266 gen7_mfd_context->base.run = gen75_mfd_decode_picture;
3267 gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
3269 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
3270 gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
3271 gen7_mfd_context->reference_surface[i].frame_store_id = -1;
3272 gen7_mfd_context->reference_surface[i].obj_surface = NULL;
3275 gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
3276 gen7_mfd_context->jpeg_wa_surface_object = NULL;
3278 switch (obj_config->profile) {
3279 case VAProfileMPEG2Simple:
3280 case VAProfileMPEG2Main:
3281 gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
3284 case VAProfileH264ConstrainedBaseline:
3285 case VAProfileH264Main:
3286 case VAProfileH264High:
3287 gen75_mfd_avc_context_init(ctx, gen7_mfd_context);
3292 return (struct hw_context *)gen7_mfd_context;