src/gen75_mfd.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *    Zhao  Yakui  <yakui.zhao@intel.com>
  27  *
  28  */
  29
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include <assert.h>
  34 #include <va/va_dec_jpeg.h>
  35
  36 #include "intel_batchbuffer.h"
  37 #include "intel_driver.h"
  38
  39 #include "i965_defines.h"
  40 #include "i965_drv_video.h"
  41 #include "i965_decoder_utils.h"
  42
  43 #include "gen7_mfd.h"
  44 #include "intel_media.h"
  45
  46 #define B0_STEP_REV             2
  47 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
  48
  49 static const uint32_t zigzag_direct[64] = {
  50     0,   1,  8, 16,  9,  2,  3, 10,
  51     17, 24, 32, 25, 18, 11,  4,  5,
  52     12, 19, 26, 33, 40, 48, 41, 34,
  53     27, 20, 13,  6,  7, 14, 21, 28,
  54     35, 42, 49, 56, 57, 50, 43, 36,
  55     29, 22, 15, 23, 30, 37, 44, 51,
  56     58, 59, 52, 45, 38, 31, 39, 46,
  57     53, 60, 61, 54, 47, 55, 62, 63
  58 };
  59
  60 static void
  61 gen75_mfd_avc_frame_store_index(VADriverContextP ctx,
  62                                VAPictureParameterBufferH264 *pic_param,
  63                                struct gen7_mfd_context *gen7_mfd_context)
  64 {
  65     struct i965_driver_data *i965 = i965_driver_data(ctx);
  66     int i, j;
  67
  68     assert(ARRAY_ELEMS(gen7_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
  69
  70     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
  71         int found = 0;
  72
  73         if (gen7_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
  74             continue;
  75
  76         for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
  77             VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
  78             if (ref_pic->flags & VA_PICTURE_H264_INVALID)
  79                 continue;
  80
  81             if (gen7_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
  82                 found = 1;
  83                 break;
  84             }
  85         }
  86
  87         if (!found) {
  88             struct object_surface *obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
  89             obj_surface->flags &= ~SURFACE_REFERENCED;
  90
  91             if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
  92                 dri_bo_unreference(obj_surface->bo);
  93                 obj_surface->bo = NULL;
  94                 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
  95             }
  96
  97             if (obj_surface->free_private_data)
  98                 obj_surface->free_private_data(&obj_surface->private_data);
  99
 100             gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
 101             gen7_mfd_context->reference_surface[i].frame_store_id = -1;
 102         }
 103     }
 104
 105     for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
 106         VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
 107         int found = 0;
 108
 109         if (ref_pic->flags & VA_PICTURE_H264_INVALID)
 110             continue;
 111
 112         for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 113             if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 114                 continue;
 115
 116             if (gen7_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
 117                 found = 1;
 118                 break;
 119             }
 120         }
 121
 122         if (!found) {
 123             int frame_idx;
 124             struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
 125
 126             assert(obj_surface);
 127             i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 128
 129             for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface); frame_idx++) {
 130                 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 131                     if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 132                         continue;
 133
 134                     if (gen7_mfd_context->reference_surface[j].frame_store_id == frame_idx)
 135                         break;
 136                 }
 137
 138                 if (j == ARRAY_ELEMS(gen7_mfd_context->reference_surface))
 139                     break;
 140             }
 141
 142             assert(frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface));
 143
 144             for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 145                 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
 146                     gen7_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
 147                     gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 148                     break;
 149                 }
 150             }
 151         }
 152     }
 153
 154     /* sort */
 155     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface) - 1; i++) {
 156         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 157             gen7_mfd_context->reference_surface[i].frame_store_id == i)
 158             continue;
 159
 160         for (j = i + 1; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
 161             if (gen7_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
 162                 gen7_mfd_context->reference_surface[j].frame_store_id == i) {
 163                 VASurfaceID id = gen7_mfd_context->reference_surface[i].surface_id;
 164                 int frame_idx = gen7_mfd_context->reference_surface[i].frame_store_id;
 165
 166                 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[j].surface_id;
 167                 gen7_mfd_context->reference_surface[i].frame_store_id = gen7_mfd_context->reference_surface[j].frame_store_id;
 168                 gen7_mfd_context->reference_surface[j].surface_id = id;
 169                 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 170                 break;
 171             }
 172         }
 173     }
 174 }
 175
 176 static void
 177 gen75_mfd_init_avc_surface(VADriverContextP ctx,
 178                           VAPictureParameterBufferH264 *pic_param,
 179                           struct object_surface *obj_surface)
 180 {
 181     struct i965_driver_data *i965 = i965_driver_data(ctx);
 182     GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
 183     int width_in_mbs, height_in_mbs;
 184
 185     obj_surface->free_private_data = gen_free_avc_surface;
 186     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 187     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 188
 189     if (!gen7_avc_surface) {
 190         gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
 191         assert((obj_surface->size & 0x3f) == 0);
 192         obj_surface->private_data = gen7_avc_surface;
 193     }
 194
 195     gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
 196                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
 197
 198     if (gen7_avc_surface->dmv_top == NULL) {
 199         gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
 200                                                  "direct mv w/r buffer",
 201                                                  width_in_mbs * height_in_mbs * 128,
 202                                                  0x1000);
 203         assert(gen7_avc_surface->dmv_top);
 204     }
 205
 206     if (gen7_avc_surface->dmv_bottom_flag &&
 207         gen7_avc_surface->dmv_bottom == NULL) {
 208         gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
 209                                                     "direct mv w/r buffer",
 210                                                     width_in_mbs * height_in_mbs * 128,
 211                                                     0x1000);
 212         assert(gen7_avc_surface->dmv_bottom);
 213     }
 214 }
 215
 216 static void
 217 gen75_mfd_pipe_mode_select(VADriverContextP ctx,
 218                           struct decode_state *decode_state,
 219                           int standard_select,
 220                           struct gen7_mfd_context *gen7_mfd_context)
 221 {
 222     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 223
 224     assert(standard_select == MFX_FORMAT_MPEG2 ||
 225            standard_select == MFX_FORMAT_AVC ||
 226            standard_select == MFX_FORMAT_VC1 ||
 227            standard_select == MFX_FORMAT_JPEG);
 228
 229     BEGIN_BCS_BATCH(batch, 5);
 230     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
 231     OUT_BCS_BATCH(batch,
 232                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
 233                   (MFD_MODE_VLD << 15) | /* VLD mode */
 234                   (0 << 10) | /* disable Stream-Out */
 235                   (gen7_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 236                   (gen7_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 237                   (0 << 5)  | /* not in stitch mode */
 238                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 239                   (standard_select << 0));
 240     OUT_BCS_BATCH(batch,
 241                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 242                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 243                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 244                   (0 << 1)  |
 245                   (0 << 0));
 246     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
 247     OUT_BCS_BATCH(batch, 0); /* reserved */
 248     ADVANCE_BCS_BATCH(batch);
 249 }
 250
 251 static void
 252 gen75_mfd_surface_state(VADriverContextP ctx,
 253                        struct decode_state *decode_state,
 254                        int standard_select,
 255                        struct gen7_mfd_context *gen7_mfd_context)
 256 {
 257     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 258     struct i965_driver_data *i965 = i965_driver_data(ctx);
 259     struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
 260     unsigned int y_cb_offset;
 261     unsigned int y_cr_offset;
 262
 263     assert(obj_surface);
 264
 265     y_cb_offset = obj_surface->y_cb_offset;
 266     y_cr_offset = obj_surface->y_cr_offset;
 267
 268     BEGIN_BCS_BATCH(batch, 6);
 269     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 270     OUT_BCS_BATCH(batch, 0);
 271     OUT_BCS_BATCH(batch,
 272                   ((obj_surface->orig_height - 1) << 18) |
 273                   ((obj_surface->orig_width - 1) << 4));
 274     OUT_BCS_BATCH(batch,
 275                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 276                   ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
 277                   (0 << 22) | /* surface object control state, ignored */
 278                   ((obj_surface->width - 1) << 3) | /* pitch */
 279                   (0 << 2)  | /* must be 0 */
 280                   (1 << 1)  | /* must be tiled */
 281                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
 282     OUT_BCS_BATCH(batch,
 283                   (0 << 16) | /* X offset for U(Cb), must be 0 */
 284                   (y_cb_offset << 0)); /* Y offset for U(Cb) */
 285     OUT_BCS_BATCH(batch,
 286                   (0 << 16) | /* X offset for V(Cr), must be 0 */
 287                   (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
 288     ADVANCE_BCS_BATCH(batch);
 289 }
 290
 291 static void
 292 gen75_mfd_pipe_buf_addr_state_bplus(VADriverContextP ctx,
 293                              struct decode_state *decode_state,
 294                              int standard_select,
 295                              struct gen7_mfd_context *gen7_mfd_context)
 296 {
 297     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 298     struct i965_driver_data *i965 = i965_driver_data(ctx);
 299     int i;
 300
 301     BEGIN_BCS_BATCH(batch, 61);
 302     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
 303         /* Pre-deblock 1-3 */
 304     if (gen7_mfd_context->pre_deblocking_output.valid)
 305         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 306                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 307                       0);
 308     else
 309         OUT_BCS_BATCH(batch, 0);
 310
 311         OUT_BCS_BATCH(batch, 0);
 312         OUT_BCS_BATCH(batch, 0);
 313         /* Post-debloing 4-6 */
 314     if (gen7_mfd_context->post_deblocking_output.valid)
 315         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 316                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 317                       0);
 318     else
 319         OUT_BCS_BATCH(batch, 0);
 320
 321         OUT_BCS_BATCH(batch, 0);
 322         OUT_BCS_BATCH(batch, 0);
 323
 324         /* uncompressed-video & stream out 7-12 */
 325     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 326     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 327         OUT_BCS_BATCH(batch, 0);
 328         OUT_BCS_BATCH(batch, 0);
 329         OUT_BCS_BATCH(batch, 0);
 330         OUT_BCS_BATCH(batch, 0);
 331
 332         /* intra row-store scratch 13-15 */
 333     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 334         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 335                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 336                       0);
 337     else
 338         OUT_BCS_BATCH(batch, 0);
 339
 340         OUT_BCS_BATCH(batch, 0);
 341         OUT_BCS_BATCH(batch, 0);
 342         /* deblocking-filter-row-store 16-18 */
 343     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 344         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 345                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 346                       0);
 347     else
 348         OUT_BCS_BATCH(batch, 0);
 349         OUT_BCS_BATCH(batch, 0);
 350         OUT_BCS_BATCH(batch, 0);
 351
 352     /* DW 19..50 */
 353     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 354         struct object_surface *obj_surface;
 355
 356         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 357             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 358             assert(obj_surface && obj_surface->bo);
 359
 360             OUT_BCS_RELOC(batch, obj_surface->bo,
 361                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 362                           0);
 363         } else {
 364             OUT_BCS_BATCH(batch, 0);
 365         }
 366             OUT_BCS_BATCH(batch, 0);
 367     }
 368         /* reference property 51 */
 369     OUT_BCS_BATCH(batch, 0);
 370
 371         /* Macroblock status & ILDB 52-57 */
 372         OUT_BCS_BATCH(batch, 0);
 373         OUT_BCS_BATCH(batch, 0);
 374         OUT_BCS_BATCH(batch, 0);
 375         OUT_BCS_BATCH(batch, 0);
 376         OUT_BCS_BATCH(batch, 0);
 377         OUT_BCS_BATCH(batch, 0);
 378
 379         /* the second Macroblock status 58-60 */
 380         OUT_BCS_BATCH(batch, 0);
 381         OUT_BCS_BATCH(batch, 0);
 382         OUT_BCS_BATCH(batch, 0);
 383     ADVANCE_BCS_BATCH(batch);
 384 }
 385
 386 static void
 387 gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 388                              struct decode_state *decode_state,
 389                              int standard_select,
 390                              struct gen7_mfd_context *gen7_mfd_context)
 391 {
 392     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 393     struct i965_driver_data *i965 = i965_driver_data(ctx);
 394     int i;
 395
 396         if (IS_STEPPING_BPLUS(i965)) {
 397                 gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state,
 398                                 standard_select, gen7_mfd_context);
 399                 return;
 400         }
 401     BEGIN_BCS_BATCH(batch, 25);
 402     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
 403     if (gen7_mfd_context->pre_deblocking_output.valid)
 404         OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
 405                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 406                       0);
 407     else
 408         OUT_BCS_BATCH(batch, 0);
 409
 410     if (gen7_mfd_context->post_deblocking_output.valid)
 411         OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
 412                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 413                       0);
 414     else
 415         OUT_BCS_BATCH(batch, 0);
 416
 417     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 418     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 419
 420     if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
 421         OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
 422                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 423                       0);
 424     else
 425         OUT_BCS_BATCH(batch, 0);
 426
 427     if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 428         OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 429                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 430                       0);
 431     else
 432         OUT_BCS_BATCH(batch, 0);
 433
 434     /* DW 7..22 */
 435     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 436         struct object_surface *obj_surface;
 437
 438         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 439             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 440             assert(obj_surface && obj_surface->bo);
 441
 442             OUT_BCS_RELOC(batch, obj_surface->bo,
 443                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 444                           0);
 445         } else {
 446             OUT_BCS_BATCH(batch, 0);
 447         }
 448     }
 449
 450     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 451     OUT_BCS_BATCH(batch, 0);   /* ignore DW24 for decoding */
 452     ADVANCE_BCS_BATCH(batch);
 453 }
 454
 455 static void
 456 gen75_mfd_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
 457                                  dri_bo *slice_data_bo,
 458                                  int standard_select,
 459                                  struct gen7_mfd_context *gen7_mfd_context)
 460 {
 461     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 462
 463     BEGIN_BCS_BATCH(batch, 26);
 464     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
 465         /* MFX In BS 1-5 */
 466     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 467     OUT_BCS_BATCH(batch, 0);
 468     OUT_BCS_BATCH(batch, 0);
 469         /* Upper bound 4-5 */
 470     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 471     OUT_BCS_BATCH(batch, 0);
 472
 473         /* MFX indirect MV 6-10 */
 474     OUT_BCS_BATCH(batch, 0);
 475     OUT_BCS_BATCH(batch, 0);
 476     OUT_BCS_BATCH(batch, 0);
 477     OUT_BCS_BATCH(batch, 0);
 478     OUT_BCS_BATCH(batch, 0);
 479
 480         /* MFX IT_COFF 11-15 */
 481     OUT_BCS_BATCH(batch, 0);
 482     OUT_BCS_BATCH(batch, 0);
 483     OUT_BCS_BATCH(batch, 0);
 484     OUT_BCS_BATCH(batch, 0);
 485     OUT_BCS_BATCH(batch, 0);
 486
 487         /* MFX IT_DBLK 16-20 */
 488     OUT_BCS_BATCH(batch, 0);
 489     OUT_BCS_BATCH(batch, 0);
 490     OUT_BCS_BATCH(batch, 0);
 491     OUT_BCS_BATCH(batch, 0);
 492     OUT_BCS_BATCH(batch, 0);
 493
 494         /* MFX PAK_BSE object for encoder 21-25 */
 495     OUT_BCS_BATCH(batch, 0);
 496     OUT_BCS_BATCH(batch, 0);
 497     OUT_BCS_BATCH(batch, 0);
 498     OUT_BCS_BATCH(batch, 0);
 499     OUT_BCS_BATCH(batch, 0);
 500
 501     ADVANCE_BCS_BATCH(batch);
 502 }
 503
 504 static void
 505 gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 506                                  dri_bo *slice_data_bo,
 507                                  int standard_select,
 508                                  struct gen7_mfd_context *gen7_mfd_context)
 509 {
 510     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 511
 512     struct i965_driver_data *i965 = i965_driver_data(ctx);
 513
 514         if (IS_STEPPING_BPLUS(i965)) {
 515                 gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo,
 516                                         standard_select, gen7_mfd_context);
 517                 return;
 518         }
 519     BEGIN_BCS_BATCH(batch, 11);
 520     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 521     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 522     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 523     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 524     OUT_BCS_BATCH(batch, 0);
 525     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 526     OUT_BCS_BATCH(batch, 0);
 527     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 528     OUT_BCS_BATCH(batch, 0);
 529     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 530     OUT_BCS_BATCH(batch, 0);
 531     ADVANCE_BCS_BATCH(batch);
 532 }
 533
 534 static void
 535 gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
 536                                  struct decode_state *decode_state,
 537                                  int standard_select,
 538                                  struct gen7_mfd_context *gen7_mfd_context)
 539 {
 540     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 541
 542     BEGIN_BCS_BATCH(batch, 10);
 543     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
 544
 545     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 546         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 547                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 548                       0);
 549         else
 550                 OUT_BCS_BATCH(batch, 0);
 551
 552     OUT_BCS_BATCH(batch, 0);
 553     OUT_BCS_BATCH(batch, 0);
 554         /* MPR Row Store Scratch buffer 4-6 */
 555     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 556         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 557                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 558                       0);
 559     else
 560             OUT_BCS_BATCH(batch, 0);
 561     OUT_BCS_BATCH(batch, 0);
 562     OUT_BCS_BATCH(batch, 0);
 563
 564         /* Bitplane 7-9 */
 565     if (gen7_mfd_context->bitplane_read_buffer.valid)
 566         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 567                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 568                       0);
 569     else
 570         OUT_BCS_BATCH(batch, 0);
 571     OUT_BCS_BATCH(batch, 0);
 572     OUT_BCS_BATCH(batch, 0);
 573     ADVANCE_BCS_BATCH(batch);
 574 }
 575
 576 static void
 577 gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 578                                  struct decode_state *decode_state,
 579                                  int standard_select,
 580                                  struct gen7_mfd_context *gen7_mfd_context)
 581 {
 582     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 583     struct i965_driver_data *i965 = i965_driver_data(ctx);
 584
 585         if (IS_STEPPING_BPLUS(i965)) {
 586                 gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state,
 587                                         standard_select, gen7_mfd_context);
 588                 return;
 589         }
 590
 591     BEGIN_BCS_BATCH(batch, 4);
 592     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 593
 594     if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 595         OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 596                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 597                       0);
 598     else
 599         OUT_BCS_BATCH(batch, 0);
 600
 601     if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
 602         OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
 603                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 604                       0);
 605     else
 606         OUT_BCS_BATCH(batch, 0);
 607
 608     if (gen7_mfd_context->bitplane_read_buffer.valid)
 609         OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
 610                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 611                       0);
 612     else
 613         OUT_BCS_BATCH(batch, 0);
 614
 615     ADVANCE_BCS_BATCH(batch);
 616 }
 617
 618 #if 0
 619 static void
 620 gen7_mfd_aes_state(VADriverContextP ctx,
 621                    struct decode_state *decode_state,
 622                    int standard_select)
 623 {
 624     /* FIXME */
 625 }
 626 #endif
 627
 628 static void
 629 gen75_mfd_qm_state(VADriverContextP ctx,
 630                   int qm_type,
 631                   unsigned char *qm,
 632                   int qm_length,
 633                   struct gen7_mfd_context *gen7_mfd_context)
 634 {
 635     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 636     unsigned int qm_buffer[16];
 637
 638     assert(qm_length <= 16 * 4);
 639     memcpy(qm_buffer, qm, qm_length);
 640
 641     BEGIN_BCS_BATCH(batch, 18);
 642     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 643     OUT_BCS_BATCH(batch, qm_type << 0);
 644     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 645     ADVANCE_BCS_BATCH(batch);
 646 }
 647
 648 #if 0
 649 static void
 650 gen7_mfd_wait(VADriverContextP ctx,
 651               struct decode_state *decode_state,
 652               int standard_select,
 653               struct gen7_mfd_context *gen7_mfd_context)
 654 {
 655     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 656
 657     BEGIN_BCS_BATCH(batch, 1);
 658     OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
 659     ADVANCE_BCS_BATCH(batch);
 660 }
 661 #endif
 662
 663 static void
 664 gen75_mfd_avc_img_state(VADriverContextP ctx,
 665                        struct decode_state *decode_state,
 666                        struct gen7_mfd_context *gen7_mfd_context)
 667 {
 668     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 669     int img_struct;
 670     int mbaff_frame_flag;
 671     unsigned int width_in_mbs, height_in_mbs;
 672     VAPictureParameterBufferH264 *pic_param;
 673
 674     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 675     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 676     assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
 677
 678     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 679         img_struct = 1;
 680     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 681         img_struct = 3;
 682     else
 683         img_struct = 0;
 684
 685     if ((img_struct & 0x1) == 0x1) {
 686         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 687     } else {
 688         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 689     }
 690
 691     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 692         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 693         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 694     } else {
 695         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 696     }
 697
 698     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 699                         !pic_param->pic_fields.bits.field_pic_flag);
 700
 701     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 702     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 703
 704     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 705     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 706            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 707     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 708
 709     BEGIN_BCS_BATCH(batch, 17);
 710     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2));
 711     OUT_BCS_BATCH(batch,
 712                   width_in_mbs * height_in_mbs);
 713     OUT_BCS_BATCH(batch,
 714                   ((height_in_mbs - 1) << 16) |
 715                   ((width_in_mbs - 1) << 0));
 716     OUT_BCS_BATCH(batch,
 717                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 718                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 719                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 720                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 721                   (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
 722                   (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
 723                   (img_struct << 8));
 724     OUT_BCS_BATCH(batch,
 725                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 726                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 727                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 728                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 729                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 730                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 731                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 732                   (mbaff_frame_flag << 1) |
 733                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 734     OUT_BCS_BATCH(batch, 0);
 735     OUT_BCS_BATCH(batch, 0);
 736     OUT_BCS_BATCH(batch, 0);
 737     OUT_BCS_BATCH(batch, 0);
 738     OUT_BCS_BATCH(batch, 0);
 739     OUT_BCS_BATCH(batch, 0);
 740     OUT_BCS_BATCH(batch, 0);
 741     OUT_BCS_BATCH(batch, 0);
 742     OUT_BCS_BATCH(batch, 0);
 743     OUT_BCS_BATCH(batch, 0);
 744     OUT_BCS_BATCH(batch, 0);
 745     OUT_BCS_BATCH(batch, 0);
 746     ADVANCE_BCS_BATCH(batch);
 747 }
 748
 749 static void
 750 gen75_mfd_avc_qm_state(VADriverContextP ctx,
 751                       struct decode_state *decode_state,
 752                       struct gen7_mfd_context *gen7_mfd_context)
 753 {
 754     VAIQMatrixBufferH264 *iq_matrix;
 755     VAPictureParameterBufferH264 *pic_param;
 756
 757     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 758         iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 759     else
 760         iq_matrix = &gen7_mfd_context->iq_matrix.h264;
 761
 762     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 763     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 764
 765     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
 766     gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
 767
 768     if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
 769         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
 770         gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
 771     }
 772 }
 773
 774 static void
 775 gen75_mfd_avc_picid_state(VADriverContextP ctx,
 776                       struct decode_state *decode_state,
 777                       struct gen7_mfd_context *gen7_mfd_context)
 778 {
 779     struct i965_driver_data *i965 = i965_driver_data(ctx);
 780     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 781
 782     BEGIN_BCS_BATCH(batch, 10);
 783     OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2));
 784     OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping
 785     OUT_BCS_BATCH(batch, 0);
 786     OUT_BCS_BATCH(batch, 0);
 787     OUT_BCS_BATCH(batch, 0);
 788     OUT_BCS_BATCH(batch, 0);
 789     OUT_BCS_BATCH(batch, 0);
 790     OUT_BCS_BATCH(batch, 0);
 791     OUT_BCS_BATCH(batch, 0);
 792     OUT_BCS_BATCH(batch, 0);
 793     ADVANCE_BCS_BATCH(batch);
 794 }
 795
 796 static void
 797 gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx,
 798                               VAPictureParameterBufferH264 *pic_param,
 799                               VASliceParameterBufferH264 *slice_param,
 800                               struct gen7_mfd_context *gen7_mfd_context)
 801 {
 802     struct i965_driver_data *i965 = i965_driver_data(ctx);
 803     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 804     struct object_surface *obj_surface;
 805     GenAvcSurface *gen7_avc_surface;
 806     VAPictureH264 *va_pic;
 807     int i, j;
 808
 809     BEGIN_BCS_BATCH(batch, 71);
 810     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
 811
 812     /* reference surfaces 0..15 */
 813     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 814         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 815             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 816             assert(obj_surface);
 817             gen7_avc_surface = obj_surface->private_data;
 818
 819             if (gen7_avc_surface == NULL) {
 820                 OUT_BCS_BATCH(batch, 0);
 821                 OUT_BCS_BATCH(batch, 0);
 822             } else {
 823                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 824                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 825                               0);
 826                 OUT_BCS_BATCH(batch, 0);
 827             }
 828         } else {
 829             OUT_BCS_BATCH(batch, 0);
 830             OUT_BCS_BATCH(batch, 0);
 831         }
 832     }
 833         OUT_BCS_BATCH(batch, 0);
 834
 835     /* the current decoding frame/field */
 836     va_pic = &pic_param->CurrPic;
 837     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 838     obj_surface = SURFACE(va_pic->picture_id);
 839     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 840     gen7_avc_surface = obj_surface->private_data;
 841
 842     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 843                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 844                   0);
 845
 846         OUT_BCS_BATCH(batch, 0);
 847         OUT_BCS_BATCH(batch, 0);
 848
 849     /* POC List */
 850     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 851         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 852             int found = 0;
 853             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 854                 va_pic = &pic_param->ReferenceFrames[j];
 855
 856                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 857                     continue;
 858
 859                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 860                     found = 1;
 861                     break;
 862                 }
 863             }
 864
 865             assert(found == 1);
 866             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 867
 868             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 869             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 870         } else {
 871             OUT_BCS_BATCH(batch, 0);
 872             OUT_BCS_BATCH(batch, 0);
 873         }
 874     }
 875
 876     va_pic = &pic_param->CurrPic;
 877     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 878     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 879
 880     ADVANCE_BCS_BATCH(batch);
 881 }
 882
 883 static void
 884 gen75_mfd_avc_directmode_state(VADriverContextP ctx,
 885                               VAPictureParameterBufferH264 *pic_param,
 886                               VASliceParameterBufferH264 *slice_param,
 887                               struct gen7_mfd_context *gen7_mfd_context)
 888 {
 889     struct i965_driver_data *i965 = i965_driver_data(ctx);
 890     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 891     struct object_surface *obj_surface;
 892     GenAvcSurface *gen7_avc_surface;
 893     VAPictureH264 *va_pic;
 894     int i, j;
 895
 896         if (IS_STEPPING_BPLUS(i965)) {
 897                 gen75_mfd_avc_directmode_state_bplus(ctx, pic_param, slice_param,
 898                         gen7_mfd_context);
 899
 900                 return;
 901         }
 902
 903     BEGIN_BCS_BATCH(batch, 69);
 904     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 905
 906     /* reference surfaces 0..15 */
 907     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 908         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 909             obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
 910             assert(obj_surface);
 911             gen7_avc_surface = obj_surface->private_data;
 912
 913             if (gen7_avc_surface == NULL) {
 914                 OUT_BCS_BATCH(batch, 0);
 915                 OUT_BCS_BATCH(batch, 0);
 916             } else {
 917                 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 918                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 919                               0);
 920
 921                 if (gen7_avc_surface->dmv_bottom_flag == 1)
 922                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 923                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 924                                   0);
 925                 else
 926                     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 927                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 928                                   0);
 929             }
 930         } else {
 931             OUT_BCS_BATCH(batch, 0);
 932             OUT_BCS_BATCH(batch, 0);
 933         }
 934     }
 935
 936     /* the current decoding frame/field */
 937     va_pic = &pic_param->CurrPic;
 938     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 939     obj_surface = SURFACE(va_pic->picture_id);
 940     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 941     gen7_avc_surface = obj_surface->private_data;
 942
 943     OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 944                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 945                   0);
 946
 947     if (gen7_avc_surface->dmv_bottom_flag == 1)
 948         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
 949                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 950                       0);
 951     else
 952         OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
 953                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 954                       0);
 955
 956     /* POC List */
 957     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
 958         if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 959             int found = 0;
 960             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 961                 va_pic = &pic_param->ReferenceFrames[j];
 962
 963                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 964                     continue;
 965
 966                 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
 967                     found = 1;
 968                     break;
 969                 }
 970             }
 971
 972             assert(found == 1);
 973             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 974
 975             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 976             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 977         } else {
 978             OUT_BCS_BATCH(batch, 0);
 979             OUT_BCS_BATCH(batch, 0);
 980         }
 981     }
 982
 983     va_pic = &pic_param->CurrPic;
 984     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 985     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 986
 987     ADVANCE_BCS_BATCH(batch);
 988 }
 989
 990 static void
 991 gen75_mfd_avc_slice_state(VADriverContextP ctx,
 992                          VAPictureParameterBufferH264 *pic_param,
 993                          VASliceParameterBufferH264 *slice_param,
 994                          VASliceParameterBufferH264 *next_slice_param,
 995                          struct gen7_mfd_context *gen7_mfd_context)
 996 {
 997     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
 998     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 999     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1000     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
1001     int num_ref_idx_l0, num_ref_idx_l1;
1002     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
1003                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
1004     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
1005     int slice_type;
1006
1007     if (slice_param->slice_type == SLICE_TYPE_I ||
1008         slice_param->slice_type == SLICE_TYPE_SI) {
1009         slice_type = SLICE_TYPE_I;
1010     } else if (slice_param->slice_type == SLICE_TYPE_P ||
1011                slice_param->slice_type == SLICE_TYPE_SP) {
1012         slice_type = SLICE_TYPE_P;
1013     } else {
1014         assert(slice_param->slice_type == SLICE_TYPE_B);
1015         slice_type = SLICE_TYPE_B;
1016     }
1017
1018     if (slice_type == SLICE_TYPE_I) {
1019         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
1020         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1021         num_ref_idx_l0 = 0;
1022         num_ref_idx_l1 = 0;
1023     } else if (slice_type == SLICE_TYPE_P) {
1024         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1025         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1026         num_ref_idx_l1 = 0;
1027     } else {
1028         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1029         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
1030     }
1031
1032     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
1033     slice_hor_pos = first_mb_in_slice % width_in_mbs;
1034     slice_ver_pos = first_mb_in_slice / width_in_mbs;
1035
1036     if (next_slice_param) {
1037         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
1038         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
1039         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
1040     } else {
1041         next_slice_hor_pos = 0;
1042         next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
1043     }
1044
1045     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
1046     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
1047     OUT_BCS_BATCH(batch, slice_type);
1048     OUT_BCS_BATCH(batch,
1049                   (num_ref_idx_l1 << 24) |
1050                   (num_ref_idx_l0 << 16) |
1051                   (slice_param->chroma_log2_weight_denom << 8) |
1052                   (slice_param->luma_log2_weight_denom << 0));
1053     OUT_BCS_BATCH(batch,
1054                   (slice_param->direct_spatial_mv_pred_flag << 29) |
1055                   (slice_param->disable_deblocking_filter_idc << 27) |
1056                   (slice_param->cabac_init_idc << 24) |
1057                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
1058                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
1059                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
1060     OUT_BCS_BATCH(batch,
1061                   (slice_ver_pos << 24) |
1062                   (slice_hor_pos << 16) |
1063                   (first_mb_in_slice << 0));
1064     OUT_BCS_BATCH(batch,
1065                   (next_slice_ver_pos << 16) |
1066                   (next_slice_hor_pos << 0));
1067     OUT_BCS_BATCH(batch,
1068                   (next_slice_param == NULL) << 19); /* last slice flag */
1069     OUT_BCS_BATCH(batch, 0);
1070     OUT_BCS_BATCH(batch, 0);
1071     OUT_BCS_BATCH(batch, 0);
1072     OUT_BCS_BATCH(batch, 0);
1073     ADVANCE_BCS_BATCH(batch);
1074 }
1075
1076 static inline void
1077 gen75_mfd_avc_ref_idx_state(VADriverContextP ctx,
1078                            VAPictureParameterBufferH264 *pic_param,
1079                            VASliceParameterBufferH264 *slice_param,
1080                            struct gen7_mfd_context *gen7_mfd_context)
1081 {
1082     gen6_send_avc_ref_idx_state(
1083         gen7_mfd_context->base.batch,
1084         slice_param,
1085         gen7_mfd_context->reference_surface
1086     );
1087 }
1088
1089 static void
1090 gen75_mfd_avc_weightoffset_state(VADriverContextP ctx,
1091                                 VAPictureParameterBufferH264 *pic_param,
1092                                 VASliceParameterBufferH264 *slice_param,
1093                                 struct gen7_mfd_context *gen7_mfd_context)
1094 {
1095     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1096     int i, j, num_weight_offset_table = 0;
1097     short weightoffsets[32 * 6];
1098
1099     if ((slice_param->slice_type == SLICE_TYPE_P ||
1100          slice_param->slice_type == SLICE_TYPE_SP) &&
1101         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
1102         num_weight_offset_table = 1;
1103     }
1104
1105     if ((slice_param->slice_type == SLICE_TYPE_B) &&
1106         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
1107         num_weight_offset_table = 2;
1108     }
1109
1110     for (i = 0; i < num_weight_offset_table; i++) {
1111         BEGIN_BCS_BATCH(batch, 98);
1112         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
1113         OUT_BCS_BATCH(batch, i);
1114
1115         if (i == 0) {
1116             for (j = 0; j < 32; j++) {
1117                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
1118                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
1119                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
1120                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
1121                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
1122                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
1123             }
1124         } else {
1125             for (j = 0; j < 32; j++) {
1126                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
1127                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
1128                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
1129                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
1130                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
1131                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
1132             }
1133         }
1134
1135         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
1136         ADVANCE_BCS_BATCH(batch);
1137     }
1138 }
1139
1140 static int
1141 gen75_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
1142 {
1143     int out_slice_data_bit_offset;
1144     int slice_header_size = in_slice_data_bit_offset / 8;
1145     int i, j;
1146
1147     for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1148         if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
1149             i++, j += 2;
1150         }
1151     }
1152
1153     out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1154
1155     if (mode_flag == ENTROPY_CABAC)
1156         out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
1157
1158     return out_slice_data_bit_offset;
1159 }
1160
1161 static void
1162 gen75_mfd_avc_bsd_object(VADriverContextP ctx,
1163                         VAPictureParameterBufferH264 *pic_param,
1164                         VASliceParameterBufferH264 *slice_param,
1165                         dri_bo *slice_data_bo,
1166                         VASliceParameterBufferH264 *next_slice_param,
1167                         struct gen7_mfd_context *gen7_mfd_context)
1168 {
1169     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1170     int slice_data_bit_offset;
1171     uint8_t *slice_data = NULL;
1172
1173     dri_bo_map(slice_data_bo, 0);
1174     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1175     slice_data_bit_offset = gen75_mfd_avc_get_slice_bit_offset(slice_data,
1176                                                               pic_param->pic_fields.bits.entropy_coding_mode_flag,
1177                                                               slice_param->slice_data_bit_offset);
1178     dri_bo_unmap(slice_data_bo);
1179
1180     /* the input bitsteam format on GEN7 differs from GEN6 */
1181     BEGIN_BCS_BATCH(batch, 6);
1182     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
1183     OUT_BCS_BATCH(batch,
1184                   (slice_param->slice_data_size));
1185     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
1186     OUT_BCS_BATCH(batch,
1187                   (0 << 31) |
1188                   (0 << 14) |
1189                   (0 << 12) |
1190                   (0 << 10) |
1191                   (0 << 8));
1192     OUT_BCS_BATCH(batch,
1193                   ((slice_data_bit_offset >> 3) << 16) |
1194                   (0 << 5)  |
1195                   (0 << 4)  |
1196                   ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
1197                   (slice_data_bit_offset & 0x7));
1198     OUT_BCS_BATCH(batch, 0);
1199     ADVANCE_BCS_BATCH(batch);
1200 }
1201
1202 static inline void
1203 gen75_mfd_avc_context_init(
1204     VADriverContextP         ctx,
1205     struct gen7_mfd_context *gen7_mfd_context
1206 )
1207 {
1208     /* Initialize flat scaling lists */
1209     avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
1210 }
1211
1212 static void
1213 gen75_mfd_avc_decode_init(VADriverContextP ctx,
1214                          struct decode_state *decode_state,
1215                          struct gen7_mfd_context *gen7_mfd_context)
1216 {
1217     VAPictureParameterBufferH264 *pic_param;
1218     VASliceParameterBufferH264 *slice_param;
1219     VAPictureH264 *va_pic;
1220     struct i965_driver_data *i965 = i965_driver_data(ctx);
1221     struct object_surface *obj_surface;
1222     dri_bo *bo;
1223     int i, j, enable_avc_ildb = 0;
1224     unsigned int width_in_mbs, height_in_mbs;
1225
1226     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
1227         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1228         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1229
1230         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1231             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1232             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1233                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1234                    (slice_param->slice_type == SLICE_TYPE_P) ||
1235                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1236                    (slice_param->slice_type == SLICE_TYPE_B));
1237
1238             if (slice_param->disable_deblocking_filter_idc != 1) {
1239                 enable_avc_ildb = 1;
1240                 break;
1241             }
1242
1243             slice_param++;
1244         }
1245     }
1246
1247     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1248     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1249     gen75_mfd_avc_frame_store_index(ctx, pic_param, gen7_mfd_context);
1250     width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1251     height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1252     assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
1253     assert(height_in_mbs > 0 && height_in_mbs <= 256);
1254
1255     /* Current decoded picture */
1256     va_pic = &pic_param->CurrPic;
1257     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
1258     obj_surface = SURFACE(va_pic->picture_id);
1259     assert(obj_surface);
1260     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
1261     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
1262     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1263     gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface);
1264
1265     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1266     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1267     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1268     gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
1269
1270     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1271     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1272     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1273     gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
1274
1275     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1276     bo = dri_bo_alloc(i965->intel.bufmgr,
1277                       "intra row store",
1278                       width_in_mbs * 64,
1279                       0x1000);
1280     assert(bo);
1281     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1282     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1283
1284     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1285     bo = dri_bo_alloc(i965->intel.bufmgr,
1286                       "deblocking filter row store",
1287                       width_in_mbs * 64 * 4,
1288                       0x1000);
1289     assert(bo);
1290     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1291     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1292
1293     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1294     bo = dri_bo_alloc(i965->intel.bufmgr,
1295                       "bsd mpc row store",
1296                       width_in_mbs * 64 * 2,
1297                       0x1000);
1298     assert(bo);
1299     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1300     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1301
1302     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
1303     bo = dri_bo_alloc(i965->intel.bufmgr,
1304                       "mpr row store",
1305                       width_in_mbs * 64 * 2,
1306                       0x1000);
1307     assert(bo);
1308     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
1309     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1310
1311     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1312 }
1313
1314 static void
1315 gen75_mfd_avc_decode_picture(VADriverContextP ctx,
1316                             struct decode_state *decode_state,
1317                             struct gen7_mfd_context *gen7_mfd_context)
1318 {
1319     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1320     VAPictureParameterBufferH264 *pic_param;
1321     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1322     dri_bo *slice_data_bo;
1323     int i, j;
1324
1325     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1326     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1327     gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
1328
1329     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1330     intel_batchbuffer_emit_mi_flush(batch);
1331     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1332     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1333     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1334     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1335     gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
1336     gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1337     gen75_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context);
1338
1339     for (j = 0; j < decode_state->num_slice_params; j++) {
1340         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1341         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1342         slice_data_bo = decode_state->slice_datas[j]->bo;
1343         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1344
1345         if (j == decode_state->num_slice_params - 1)
1346             next_slice_group_param = NULL;
1347         else
1348             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1349
1350         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1351             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1352             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1353                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1354                    (slice_param->slice_type == SLICE_TYPE_P) ||
1355                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1356                    (slice_param->slice_type == SLICE_TYPE_B));
1357
1358             if (i < decode_state->slice_params[j]->num_elements - 1)
1359                 next_slice_param = slice_param + 1;
1360             else
1361                 next_slice_param = next_slice_group_param;
1362
1363             gen75_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen7_mfd_context);
1364             gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1365             gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1366             gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1367             gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1368             slice_param++;
1369         }
1370     }
1371
1372     intel_batchbuffer_end_atomic(batch);
1373     intel_batchbuffer_flush(batch);
1374 }
1375
1376 static void
1377 gen75_mfd_mpeg2_decode_init(VADriverContextP ctx,
1378                            struct decode_state *decode_state,
1379                            struct gen7_mfd_context *gen7_mfd_context)
1380 {
1381     VAPictureParameterBufferMPEG2 *pic_param;
1382     struct i965_driver_data *i965 = i965_driver_data(ctx);
1383     struct object_surface *obj_surface;
1384     dri_bo *bo;
1385     unsigned int width_in_mbs;
1386
1387     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1388     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1389     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1390
1391     mpeg2_set_reference_surfaces(
1392         ctx,
1393         gen7_mfd_context->reference_surface,
1394         decode_state,
1395         pic_param
1396     );
1397
1398     /* Current decoded picture */
1399     obj_surface = SURFACE(decode_state->current_render_target);
1400     assert(obj_surface);
1401     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1402
1403     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1404     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1405     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1406     gen7_mfd_context->pre_deblocking_output.valid = 1;
1407
1408     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1409     bo = dri_bo_alloc(i965->intel.bufmgr,
1410                       "bsd mpc row store",
1411                       width_in_mbs * 96,
1412                       0x1000);
1413     assert(bo);
1414     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1415     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1416
1417     gen7_mfd_context->post_deblocking_output.valid = 0;
1418     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1419     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1420     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1421     gen7_mfd_context->bitplane_read_buffer.valid = 0;
1422 }
1423
1424 static void
1425 gen75_mfd_mpeg2_pic_state(VADriverContextP ctx,
1426                          struct decode_state *decode_state,
1427                          struct gen7_mfd_context *gen7_mfd_context)
1428 {
1429     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1430     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1431     VAPictureParameterBufferMPEG2 *pic_param;
1432     unsigned int slice_concealment_disable_bit = 0;
1433
1434     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1435     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1436
1437     slice_concealment_disable_bit = 1;
1438
1439     BEGIN_BCS_BATCH(batch, 13);
1440     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1441     OUT_BCS_BATCH(batch,
1442                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1443                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1444                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1445                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1446                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1447                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1448                   pic_param->picture_coding_extension.bits.top_field_first << 11 |
1449                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1450                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1451                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1452                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1453                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1454     OUT_BCS_BATCH(batch,
1455                   pic_param->picture_coding_type << 9);
1456     OUT_BCS_BATCH(batch,
1457                   (slice_concealment_disable_bit << 31) |
1458                   ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1459                   ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1460     OUT_BCS_BATCH(batch, 0);
1461     OUT_BCS_BATCH(batch, 0);
1462     OUT_BCS_BATCH(batch, 0);
1463     OUT_BCS_BATCH(batch, 0);
1464     OUT_BCS_BATCH(batch, 0);
1465     OUT_BCS_BATCH(batch, 0);
1466     OUT_BCS_BATCH(batch, 0);
1467     OUT_BCS_BATCH(batch, 0);
1468     OUT_BCS_BATCH(batch, 0);
1469     ADVANCE_BCS_BATCH(batch);
1470 }
1471
1472 static void
1473 gen75_mfd_mpeg2_qm_state(VADriverContextP ctx,
1474                         struct decode_state *decode_state,
1475                         struct gen7_mfd_context *gen7_mfd_context)
1476 {
1477     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1478     int i, j;
1479
1480     /* Update internal QM state */
1481     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1482         VAIQMatrixBufferMPEG2 * const iq_matrix =
1483             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1484
1485         if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1486             iq_matrix->load_intra_quantiser_matrix) {
1487             gen_iq_matrix->load_intra_quantiser_matrix =
1488                 iq_matrix->load_intra_quantiser_matrix;
1489             if (iq_matrix->load_intra_quantiser_matrix) {
1490                 for (j = 0; j < 64; j++)
1491                     gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1492                         iq_matrix->intra_quantiser_matrix[j];
1493             }
1494         }
1495
1496         if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1497             iq_matrix->load_non_intra_quantiser_matrix) {
1498             gen_iq_matrix->load_non_intra_quantiser_matrix =
1499                 iq_matrix->load_non_intra_quantiser_matrix;
1500             if (iq_matrix->load_non_intra_quantiser_matrix) {
1501                 for (j = 0; j < 64; j++)
1502                     gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1503                         iq_matrix->non_intra_quantiser_matrix[j];
1504             }
1505         }
1506     }
1507
1508     /* Commit QM state to HW */
1509     for (i = 0; i < 2; i++) {
1510         unsigned char *qm = NULL;
1511         int qm_type;
1512
1513         if (i == 0) {
1514             if (gen_iq_matrix->load_intra_quantiser_matrix) {
1515                 qm = gen_iq_matrix->intra_quantiser_matrix;
1516                 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1517             }
1518         } else {
1519             if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1520                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1521                 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1522             }
1523         }
1524
1525         if (!qm)
1526             continue;
1527
1528         gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1529     }
1530 }
1531
1532 static void
1533 gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1534                           VAPictureParameterBufferMPEG2 *pic_param,
1535                           VASliceParameterBufferMPEG2 *slice_param,
1536                           VASliceParameterBufferMPEG2 *next_slice_param,
1537                           struct gen7_mfd_context *gen7_mfd_context)
1538 {
1539     struct i965_driver_data * const i965 = i965_driver_data(ctx);
1540     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1541     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1542     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1543
1544     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1545         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1546         is_field_pic = 1;
1547     is_field_pic_wa = is_field_pic &&
1548         gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1549
1550     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1551     hpos0 = slice_param->slice_horizontal_position;
1552
1553     if (next_slice_param == NULL) {
1554         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1555         hpos1 = 0;
1556     } else {
1557         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1558         hpos1 = next_slice_param->slice_horizontal_position;
1559     }
1560
1561     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1562
1563     BEGIN_BCS_BATCH(batch, 5);
1564     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1565     OUT_BCS_BATCH(batch,
1566                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1567     OUT_BCS_BATCH(batch,
1568                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1569     OUT_BCS_BATCH(batch,
1570                   hpos0 << 24 |
1571                   vpos0 << 16 |
1572                   mb_count << 8 |
1573                   (next_slice_param == NULL) << 5 |
1574                   (next_slice_param == NULL) << 3 |
1575                   (slice_param->macroblock_offset & 0x7));
1576     OUT_BCS_BATCH(batch,
1577                   (slice_param->quantiser_scale_code << 24) |
1578                   (vpos1 << 8 | hpos1));
1579     ADVANCE_BCS_BATCH(batch);
1580 }
1581
1582 static void
1583 gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1584                               struct decode_state *decode_state,
1585                               struct gen7_mfd_context *gen7_mfd_context)
1586 {
1587     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1588     VAPictureParameterBufferMPEG2 *pic_param;
1589     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1590     dri_bo *slice_data_bo;
1591     int i, j;
1592
1593     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1594     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1595
1596     gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1597     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1598     intel_batchbuffer_emit_mi_flush(batch);
1599     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1600     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1601     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1602     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1603     gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1604     gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1605
1606     if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1607         gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1608             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1609
1610     for (j = 0; j < decode_state->num_slice_params; j++) {
1611         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1612         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1613         slice_data_bo = decode_state->slice_datas[j]->bo;
1614         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1615
1616         if (j == decode_state->num_slice_params - 1)
1617             next_slice_group_param = NULL;
1618         else
1619             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1620
1621         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1622             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1623
1624             if (i < decode_state->slice_params[j]->num_elements - 1)
1625                 next_slice_param = slice_param + 1;
1626             else
1627                 next_slice_param = next_slice_group_param;
1628
1629             gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1630             slice_param++;
1631         }
1632     }
1633
1634     intel_batchbuffer_end_atomic(batch);
1635     intel_batchbuffer_flush(batch);
1636 }
1637
1638 static const int va_to_gen7_vc1_pic_type[5] = {
1639     GEN7_VC1_I_PICTURE,
1640     GEN7_VC1_P_PICTURE,
1641     GEN7_VC1_B_PICTURE,
1642     GEN7_VC1_BI_PICTURE,
1643     GEN7_VC1_P_PICTURE,
1644 };
1645
1646 static const int va_to_gen7_vc1_mv[4] = {
1647     1, /* 1-MV */
1648     2, /* 1-MV half-pel */
1649     3, /* 1-MV half-pef bilinear */
1650     0, /* Mixed MV */
1651 };
1652
1653 static const int b_picture_scale_factor[21] = {
1654     128, 85,  170, 64,  192,
1655     51,  102, 153, 204, 43,
1656     215, 37,  74,  111, 148,
1657     185, 222, 32,  96,  160,
1658     224,
1659 };
1660
1661 static const int va_to_gen7_vc1_condover[3] = {
1662     0,
1663     2,
1664     3
1665 };
1666
1667 static const int va_to_gen7_vc1_profile[4] = {
1668     GEN7_VC1_SIMPLE_PROFILE,
1669     GEN7_VC1_MAIN_PROFILE,
1670     GEN7_VC1_RESERVED_PROFILE,
1671     GEN7_VC1_ADVANCED_PROFILE
1672 };
1673
1674 static void
1675 gen75_mfd_free_vc1_surface(void **data)
1676 {
1677     struct gen7_vc1_surface *gen7_vc1_surface = *data;
1678
1679     if (!gen7_vc1_surface)
1680         return;
1681
1682     dri_bo_unreference(gen7_vc1_surface->dmv);
1683     free(gen7_vc1_surface);
1684     *data = NULL;
1685 }
1686
1687 static void
1688 gen75_mfd_init_vc1_surface(VADriverContextP ctx,
1689                           VAPictureParameterBufferVC1 *pic_param,
1690                           struct object_surface *obj_surface)
1691 {
1692     struct i965_driver_data *i965 = i965_driver_data(ctx);
1693     struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1694     int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1695     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1696
1697     obj_surface->free_private_data = gen75_mfd_free_vc1_surface;
1698
1699     if (!gen7_vc1_surface) {
1700         gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1701         assert((obj_surface->size & 0x3f) == 0);
1702         obj_surface->private_data = gen7_vc1_surface;
1703     }
1704
1705     gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1706
1707     if (gen7_vc1_surface->dmv == NULL) {
1708         gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1709                                              "direct mv w/r buffer",
1710                                              width_in_mbs * height_in_mbs * 64,
1711                                              0x1000);
1712     }
1713 }
1714
1715 static void
1716 gen75_mfd_vc1_decode_init(VADriverContextP ctx,
1717                          struct decode_state *decode_state,
1718                          struct gen7_mfd_context *gen7_mfd_context)
1719 {
1720     VAPictureParameterBufferVC1 *pic_param;
1721     struct i965_driver_data *i965 = i965_driver_data(ctx);
1722     struct object_surface *obj_surface;
1723     int i;
1724     dri_bo *bo;
1725     int width_in_mbs;
1726
1727     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1728     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1729     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1730
1731     /* reference picture */
1732     obj_surface = SURFACE(pic_param->forward_reference_picture);
1733
1734     if (obj_surface && obj_surface->bo)
1735         gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1736     else
1737         gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1738
1739     obj_surface = SURFACE(pic_param->backward_reference_picture);
1740
1741     if (obj_surface && obj_surface->bo)
1742         gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1743     else
1744         gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1745
1746     /* must do so !!! */
1747     for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1748         gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1749
1750     /* Current decoded picture */
1751     obj_surface = SURFACE(decode_state->current_render_target);
1752     assert(obj_surface);
1753     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1754     gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1755
1756     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1757     gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1758     dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1759     gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1760
1761     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1762     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1763     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1764     gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1765
1766     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1767     bo = dri_bo_alloc(i965->intel.bufmgr,
1768                       "intra row store",
1769                       width_in_mbs * 64,
1770                       0x1000);
1771     assert(bo);
1772     gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1773     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1774
1775     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1776     bo = dri_bo_alloc(i965->intel.bufmgr,
1777                       "deblocking filter row store",
1778                       width_in_mbs * 6 * 64,
1779                       0x1000);
1780     assert(bo);
1781     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1782     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1783
1784     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1785     bo = dri_bo_alloc(i965->intel.bufmgr,
1786                       "bsd mpc row store",
1787                       width_in_mbs * 96,
1788                       0x1000);
1789     assert(bo);
1790     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1791     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1792
1793     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1794
1795     gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1796     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1797
1798     if (gen7_mfd_context->bitplane_read_buffer.valid) {
1799         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1800         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1801         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1802         int src_w, src_h;
1803         uint8_t *src = NULL, *dst = NULL;
1804
1805         assert(decode_state->bit_plane->buffer);
1806         src = decode_state->bit_plane->buffer;
1807
1808         bo = dri_bo_alloc(i965->intel.bufmgr,
1809                           "VC-1 Bitplane",
1810                           bitplane_width * height_in_mbs,
1811                           0x1000);
1812         assert(bo);
1813         gen7_mfd_context->bitplane_read_buffer.bo = bo;
1814
1815         dri_bo_map(bo, True);
1816         assert(bo->virtual);
1817         dst = bo->virtual;
1818
1819         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1820             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1821                 int src_index, dst_index;
1822                 int src_shift;
1823                 uint8_t src_value;
1824
1825                 src_index = (src_h * width_in_mbs + src_w) / 2;
1826                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1827                 src_value = ((src[src_index] >> src_shift) & 0xf);
1828
1829                 dst_index = src_w / 2;
1830                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1831             }
1832
1833             if (src_w & 1)
1834                 dst[src_w / 2] >>= 4;
1835
1836             dst += bitplane_width;
1837         }
1838
1839         dri_bo_unmap(bo);
1840     } else
1841         gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1842 }
1843
1844 static void
1845 gen75_mfd_vc1_pic_state(VADriverContextP ctx,
1846                        struct decode_state *decode_state,
1847                        struct gen7_mfd_context *gen7_mfd_context)
1848 {
1849     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1850     VAPictureParameterBufferVC1 *pic_param;
1851     struct i965_driver_data *i965 = i965_driver_data(ctx);
1852     struct object_surface *obj_surface;
1853     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1854     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1855     int unified_mv_mode;
1856     int ref_field_pic_polarity = 0;
1857     int scale_factor = 0;
1858     int trans_ac_y = 0;
1859     int dmv_surface_valid = 0;
1860     int brfd = 0;
1861     int fcm = 0;
1862     int picture_type;
1863     int profile;
1864     int overlap;
1865     int interpolation_mode = 0;
1866
1867     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1868     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1869
1870     profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1871     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1872     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1873     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1874     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1875     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1876     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1877     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1878
1879     if (dquant == 0) {
1880         alt_pquant_config = 0;
1881         alt_pquant_edge_mask = 0;
1882     } else if (dquant == 2) {
1883         alt_pquant_config = 1;
1884         alt_pquant_edge_mask = 0xf;
1885     } else {
1886         assert(dquant == 1);
1887         if (dquantfrm == 0) {
1888             alt_pquant_config = 0;
1889             alt_pquant_edge_mask = 0;
1890             alt_pq = 0;
1891         } else {
1892             assert(dquantfrm == 1);
1893             alt_pquant_config = 1;
1894
1895             switch (dqprofile) {
1896             case 3:
1897                 if (dqbilevel == 0) {
1898                     alt_pquant_config = 2;
1899                     alt_pquant_edge_mask = 0;
1900                 } else {
1901                     assert(dqbilevel == 1);
1902                     alt_pquant_config = 3;
1903                     alt_pquant_edge_mask = 0;
1904                 }
1905                 break;
1906
1907             case 0:
1908                 alt_pquant_edge_mask = 0xf;
1909                 break;
1910
1911             case 1:
1912                 if (dqdbedge == 3)
1913                     alt_pquant_edge_mask = 0x9;
1914                 else
1915                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1916
1917                 break;
1918
1919             case 2:
1920                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1921                 break;
1922
1923             default:
1924                 assert(0);
1925             }
1926         }
1927     }
1928
1929     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1930         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1931         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1932     } else {
1933         assert(pic_param->mv_fields.bits.mv_mode < 4);
1934         unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1935     }
1936
1937     if (pic_param->sequence_fields.bits.interlace == 1 &&
1938         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1939         /* FIXME: calculate reference field picture polarity */
1940         assert(0);
1941         ref_field_pic_polarity = 0;
1942     }
1943
1944     if (pic_param->b_picture_fraction < 21)
1945         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1946
1947     picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1948
1949     if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1950         picture_type == GEN7_VC1_I_PICTURE)
1951         picture_type = GEN7_VC1_BI_PICTURE;
1952
1953     if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1954         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1955     else
1956         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1957
1958
1959     if (picture_type == GEN7_VC1_B_PICTURE) {
1960         struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1961
1962         obj_surface = SURFACE(pic_param->backward_reference_picture);
1963         assert(obj_surface);
1964         gen7_vc1_surface = obj_surface->private_data;
1965
1966         if (!gen7_vc1_surface ||
1967             (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1968              va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1969             dmv_surface_valid = 0;
1970         else
1971             dmv_surface_valid = 1;
1972     }
1973
1974     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1975
1976     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1977         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1978     else {
1979         if (pic_param->picture_fields.bits.top_field_first)
1980             fcm = 2;
1981         else
1982             fcm = 3;
1983     }
1984
1985     if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1986         brfd = pic_param->reference_fields.bits.reference_distance;
1987         brfd = (scale_factor * brfd) >> 8;
1988         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1989
1990         if (brfd < 0)
1991             brfd = 0;
1992     }
1993
1994     overlap = pic_param->sequence_fields.bits.overlap;
1995     if (profile != GEN7_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
1996         overlap = 0;
1997
1998     assert(pic_param->conditional_overlap_flag < 3);
1999     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
2000
2001     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
2002         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2003          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
2004         interpolation_mode = 9; /* Half-pel bilinear */
2005     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
2006              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2007               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
2008         interpolation_mode = 1; /* Half-pel bicubic */
2009     else
2010         interpolation_mode = 0; /* Quarter-pel bicubic */
2011
2012     BEGIN_BCS_BATCH(batch, 6);
2013     OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
2014     OUT_BCS_BATCH(batch,
2015                   (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
2016                   ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
2017     OUT_BCS_BATCH(batch,
2018                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
2019                   dmv_surface_valid << 15 |
2020                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
2021                   pic_param->rounding_control << 13 |
2022                   pic_param->sequence_fields.bits.syncmarker << 12 |
2023                   interpolation_mode << 8 |
2024                   0 << 7 | /* FIXME: scale up or down ??? */
2025                   pic_param->range_reduction_frame << 6 |
2026                   pic_param->entrypoint_fields.bits.loopfilter << 5 |
2027                   overlap << 4 |
2028                   !pic_param->picture_fields.bits.is_first_field << 3 |
2029                   (pic_param->sequence_fields.bits.profile == 3) << 0);
2030     OUT_BCS_BATCH(batch,
2031                   va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
2032                   picture_type << 26 |
2033                   fcm << 24 |
2034                   alt_pq << 16 |
2035                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
2036                   scale_factor << 0);
2037     OUT_BCS_BATCH(batch,
2038                   unified_mv_mode << 28 |
2039                   pic_param->mv_fields.bits.four_mv_switch << 27 |
2040                   pic_param->fast_uvmc_flag << 26 |
2041                   ref_field_pic_polarity << 25 |
2042                   pic_param->reference_fields.bits.num_reference_pictures << 24 |
2043                   pic_param->reference_fields.bits.reference_distance << 20 |
2044                   pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
2045                   pic_param->mv_fields.bits.extended_dmv_range << 10 |
2046                   pic_param->mv_fields.bits.extended_mv_range << 8 |
2047                   alt_pquant_edge_mask << 4 |
2048                   alt_pquant_config << 2 |
2049                   pic_param->pic_quantizer_fields.bits.half_qp << 1 |
2050                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
2051     OUT_BCS_BATCH(batch,
2052                   !!pic_param->bitplane_present.value << 31 |
2053                   !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
2054                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
2055                   !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
2056                   !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
2057                   !pic_param->bitplane_present.flags.bp_overflags << 26 |
2058                   !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
2059                   !pic_param->bitplane_present.flags.bp_field_tx << 24 |
2060                   pic_param->mv_fields.bits.mv_table << 20 |
2061                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
2062                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
2063                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
2064                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
2065                   pic_param->mb_mode_table << 8 |
2066                   trans_ac_y << 6 |
2067                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
2068                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
2069                   pic_param->cbp_table << 0);
2070     ADVANCE_BCS_BATCH(batch);
2071 }
2072
2073 static void
2074 gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
2075                              struct decode_state *decode_state,
2076                              struct gen7_mfd_context *gen7_mfd_context)
2077 {
2078     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2079     VAPictureParameterBufferVC1 *pic_param;
2080     int intensitycomp_single;
2081
2082     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2083     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2084
2085     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2086     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2087     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
2088
2089     BEGIN_BCS_BATCH(batch, 6);
2090     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
2091     OUT_BCS_BATCH(batch,
2092                   0 << 14 | /* FIXME: double ??? */
2093                   0 << 12 |
2094                   intensitycomp_single << 10 |
2095                   intensitycomp_single << 8 |
2096                   0 << 4 | /* FIXME: interlace mode */
2097                   0);
2098     OUT_BCS_BATCH(batch,
2099                   pic_param->luma_shift << 16 |
2100                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
2101     OUT_BCS_BATCH(batch, 0);
2102     OUT_BCS_BATCH(batch, 0);
2103     OUT_BCS_BATCH(batch, 0);
2104     ADVANCE_BCS_BATCH(batch);
2105 }
2106
2107 static void
2108 gen75_mfd_vc1_directmode_state_bplus(VADriverContextP ctx,
2109                               struct decode_state *decode_state,
2110                               struct gen7_mfd_context *gen7_mfd_context)
2111 {
2112     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2113     VAPictureParameterBufferVC1 *pic_param;
2114     struct i965_driver_data *i965 = i965_driver_data(ctx);
2115     struct object_surface *obj_surface;
2116     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2117
2118     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2119     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2120
2121     obj_surface = SURFACE(decode_state->current_render_target);
2122
2123     if (obj_surface && obj_surface->private_data) {
2124         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2125     }
2126
2127     obj_surface = SURFACE(pic_param->backward_reference_picture);
2128
2129     if (obj_surface && obj_surface->private_data) {
2130         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2131     }
2132
2133     BEGIN_BCS_BATCH(batch, 7);
2134     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2));
2135
2136     if (dmv_write_buffer)
2137         OUT_BCS_RELOC(batch, dmv_write_buffer,
2138                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2139                       0);
2140     else
2141         OUT_BCS_BATCH(batch, 0);
2142
2143         OUT_BCS_BATCH(batch, 0);
2144         OUT_BCS_BATCH(batch, 0);
2145
2146     if (dmv_read_buffer)
2147         OUT_BCS_RELOC(batch, dmv_read_buffer,
2148                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2149                       0);
2150     else
2151         OUT_BCS_BATCH(batch, 0);
2152         OUT_BCS_BATCH(batch, 0);
2153         OUT_BCS_BATCH(batch, 0);
2154
2155     ADVANCE_BCS_BATCH(batch);
2156 }
2157
2158 static void
2159 gen75_mfd_vc1_directmode_state(VADriverContextP ctx,
2160                               struct decode_state *decode_state,
2161                               struct gen7_mfd_context *gen7_mfd_context)
2162 {
2163     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2164     VAPictureParameterBufferVC1 *pic_param;
2165     struct i965_driver_data *i965 = i965_driver_data(ctx);
2166     struct object_surface *obj_surface;
2167     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2168
2169     if (IS_STEPPING_BPLUS(i965)) {
2170         gen75_mfd_vc1_directmode_state_bplus(ctx, decode_state, gen7_mfd_context);
2171         return;
2172     }
2173     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2174     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2175
2176     obj_surface = SURFACE(decode_state->current_render_target);
2177
2178     if (obj_surface && obj_surface->private_data) {
2179         dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2180     }
2181
2182     obj_surface = SURFACE(pic_param->backward_reference_picture);
2183
2184     if (obj_surface && obj_surface->private_data) {
2185         dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2186     }
2187
2188     BEGIN_BCS_BATCH(batch, 3);
2189     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
2190
2191     if (dmv_write_buffer)
2192         OUT_BCS_RELOC(batch, dmv_write_buffer,
2193                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2194                       0);
2195     else
2196         OUT_BCS_BATCH(batch, 0);
2197
2198     if (dmv_read_buffer)
2199         OUT_BCS_RELOC(batch, dmv_read_buffer,
2200                       I915_GEM_DOMAIN_INSTRUCTION, 0,
2201                       0);
2202     else
2203         OUT_BCS_BATCH(batch, 0);
2204
2205     ADVANCE_BCS_BATCH(batch);
2206 }
2207
2208 static int
2209 gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
2210 {
2211     int out_slice_data_bit_offset;
2212     int slice_header_size = in_slice_data_bit_offset / 8;
2213     int i, j;
2214
2215     if (profile != 3)
2216         out_slice_data_bit_offset = in_slice_data_bit_offset;
2217     else {
2218         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
2219             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
2220                 i++, j += 2;
2221             }
2222         }
2223
2224         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
2225     }
2226
2227     return out_slice_data_bit_offset;
2228 }
2229
2230 static void
2231 gen75_mfd_vc1_bsd_object(VADriverContextP ctx,
2232                         VAPictureParameterBufferVC1 *pic_param,
2233                         VASliceParameterBufferVC1 *slice_param,
2234                         VASliceParameterBufferVC1 *next_slice_param,
2235                         dri_bo *slice_data_bo,
2236                         struct gen7_mfd_context *gen7_mfd_context)
2237 {
2238     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2239     int next_slice_start_vert_pos;
2240     int macroblock_offset;
2241     uint8_t *slice_data = NULL;
2242
2243     dri_bo_map(slice_data_bo, 0);
2244     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
2245     macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data,
2246                                                                slice_param->macroblock_offset,
2247                                                                pic_param->sequence_fields.bits.profile);
2248     dri_bo_unmap(slice_data_bo);
2249
2250     if (next_slice_param)
2251         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
2252     else
2253         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
2254
2255     BEGIN_BCS_BATCH(batch, 5);
2256     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
2257     OUT_BCS_BATCH(batch,
2258                   slice_param->slice_data_size - (macroblock_offset >> 3));
2259     OUT_BCS_BATCH(batch,
2260                   slice_param->slice_data_offset + (macroblock_offset >> 3));
2261     OUT_BCS_BATCH(batch,
2262                   slice_param->slice_vertical_position << 16 |
2263                   next_slice_start_vert_pos << 0);
2264     OUT_BCS_BATCH(batch,
2265                   (macroblock_offset & 0x7));
2266     ADVANCE_BCS_BATCH(batch);
2267 }
2268
2269 static void
2270 gen75_mfd_vc1_decode_picture(VADriverContextP ctx,
2271                             struct decode_state *decode_state,
2272                             struct gen7_mfd_context *gen7_mfd_context)
2273 {
2274     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2275     VAPictureParameterBufferVC1 *pic_param;
2276     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2277     dri_bo *slice_data_bo;
2278     int i, j;
2279
2280     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2281     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2282
2283     gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2284     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2285     intel_batchbuffer_emit_mi_flush(batch);
2286     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2287     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2288     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2289     gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2290     gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2291     gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2292     gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2293
2294     for (j = 0; j < decode_state->num_slice_params; j++) {
2295         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2296         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2297         slice_data_bo = decode_state->slice_datas[j]->bo;
2298         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2299
2300         if (j == decode_state->num_slice_params - 1)
2301             next_slice_group_param = NULL;
2302         else
2303             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2304
2305         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2306             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2307
2308             if (i < decode_state->slice_params[j]->num_elements - 1)
2309                 next_slice_param = slice_param + 1;
2310             else
2311                 next_slice_param = next_slice_group_param;
2312
2313             gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2314             slice_param++;
2315         }
2316     }
2317
2318     intel_batchbuffer_end_atomic(batch);
2319     intel_batchbuffer_flush(batch);
2320 }
2321
2322 static void
2323 gen75_mfd_jpeg_decode_init(VADriverContextP ctx,
2324                           struct decode_state *decode_state,
2325                           struct gen7_mfd_context *gen7_mfd_context)
2326 {
2327     struct i965_driver_data *i965 = i965_driver_data(ctx);
2328     struct object_surface *obj_surface;
2329     VAPictureParameterBufferJPEGBaseline *pic_param;
2330     int subsampling = SUBSAMPLE_YUV420;
2331
2332     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2333
2334     if (pic_param->num_components == 1)
2335         subsampling = SUBSAMPLE_YUV400;
2336     else if (pic_param->num_components == 3) {
2337         int h1 = pic_param->components[0].h_sampling_factor;
2338         int h2 = pic_param->components[1].h_sampling_factor;
2339         int h3 = pic_param->components[2].h_sampling_factor;
2340         int v1 = pic_param->components[0].v_sampling_factor;
2341         int v2 = pic_param->components[1].v_sampling_factor;
2342         int v3 = pic_param->components[2].v_sampling_factor;
2343
2344         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2345             v1 == 2 && v2 == 1 && v3 == 1)
2346             subsampling = SUBSAMPLE_YUV420;
2347         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2348                  v1 == 1 && v2 == 1 && v3 == 1)
2349             subsampling = SUBSAMPLE_YUV422H;
2350         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2351                  v1 == 1 && v2 == 1 && v3 == 1)
2352             subsampling = SUBSAMPLE_YUV444;
2353         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2354                  v1 == 1 && v2 == 1 && v3 == 1)
2355             subsampling = SUBSAMPLE_YUV411;
2356         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2357                  v1 == 2 && v2 == 1 && v3 == 1)
2358             subsampling = SUBSAMPLE_YUV422V;
2359         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2360                  v1 == 2 && v2 == 2 && v3 == 2)
2361             subsampling = SUBSAMPLE_YUV422H;
2362         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2363                  v1 == 2 && v2 == 1 && v3 == 1)
2364             subsampling = SUBSAMPLE_YUV422V;
2365         else
2366             assert(0);
2367     } else {
2368         assert(0);
2369     }
2370
2371     /* Current decoded picture */
2372     obj_surface = SURFACE(decode_state->current_render_target);
2373     assert(obj_surface);
2374     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('I','M','C','1'), subsampling);
2375
2376     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2377     gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2378     dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2379     gen7_mfd_context->pre_deblocking_output.valid = 1;
2380
2381     gen7_mfd_context->post_deblocking_output.bo = NULL;
2382     gen7_mfd_context->post_deblocking_output.valid = 0;
2383
2384     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2385     gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2386
2387     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2388     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2389
2390     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2391     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2392
2393     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2394     gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2395
2396     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2397     gen7_mfd_context->bitplane_read_buffer.valid = 0;
2398 }
2399
2400 static const int va_to_gen7_jpeg_rotation[4] = {
2401     GEN7_JPEG_ROTATION_0,
2402     GEN7_JPEG_ROTATION_90,
2403     GEN7_JPEG_ROTATION_180,
2404     GEN7_JPEG_ROTATION_270
2405 };
2406
2407 static void
2408 gen75_mfd_jpeg_pic_state(VADriverContextP ctx,
2409                         struct decode_state *decode_state,
2410                         struct gen7_mfd_context *gen7_mfd_context)
2411 {
2412     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2413     VAPictureParameterBufferJPEGBaseline *pic_param;
2414     int chroma_type = GEN7_YUV420;
2415     int frame_width_in_blks;
2416     int frame_height_in_blks;
2417
2418     assert(decode_state->pic_param && decode_state->pic_param->buffer);
2419     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2420
2421     if (pic_param->num_components == 1)
2422         chroma_type = GEN7_YUV400;
2423     else if (pic_param->num_components == 3) {
2424         int h1 = pic_param->components[0].h_sampling_factor;
2425         int h2 = pic_param->components[1].h_sampling_factor;
2426         int h3 = pic_param->components[2].h_sampling_factor;
2427         int v1 = pic_param->components[0].v_sampling_factor;
2428         int v2 = pic_param->components[1].v_sampling_factor;
2429         int v3 = pic_param->components[2].v_sampling_factor;
2430
2431         if (h1 == 2 && h2 == 1 && h3 == 1 &&
2432             v1 == 2 && v2 == 1 && v3 == 1)
2433             chroma_type = GEN7_YUV420;
2434         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2435                  v1 == 1 && v2 == 1 && v3 == 1)
2436             chroma_type = GEN7_YUV422H_2Y;
2437         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2438                  v1 == 1 && v2 == 1 && v3 == 1)
2439             chroma_type = GEN7_YUV444;
2440         else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2441                  v1 == 1 && v2 == 1 && v3 == 1)
2442             chroma_type = GEN7_YUV411;
2443         else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2444                  v1 == 2 && v2 == 1 && v3 == 1)
2445             chroma_type = GEN7_YUV422V_2Y;
2446         else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2447                  v1 == 2 && v2 == 2 && v3 == 2)
2448             chroma_type = GEN7_YUV422H_4Y;
2449         else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2450                  v1 == 2 && v2 == 1 && v3 == 1)
2451             chroma_type = GEN7_YUV422V_4Y;
2452         else
2453             assert(0);
2454     }
2455
2456     if (chroma_type == GEN7_YUV400 ||
2457         chroma_type == GEN7_YUV444 ||
2458         chroma_type == GEN7_YUV422V_2Y) {
2459         frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2460         frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2461     } else if (chroma_type == GEN7_YUV411) {
2462         frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2463         frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2464     } else {
2465         frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2466         frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2467     }
2468
2469     BEGIN_BCS_BATCH(batch, 3);
2470     OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2471     OUT_BCS_BATCH(batch,
2472                   (va_to_gen7_jpeg_rotation[0] << 4) |    /* without rotation */
2473                   (chroma_type << 0));
2474     OUT_BCS_BATCH(batch,
2475                   ((frame_height_in_blks - 1) << 16) |   /* FrameHeightInBlks */
2476                   ((frame_width_in_blks - 1) << 0));    /* FrameWidthInBlks */
2477     ADVANCE_BCS_BATCH(batch);
2478 }
2479
2480 static const int va_to_gen7_jpeg_hufftable[2] = {
2481     MFX_HUFFTABLE_ID_Y,
2482     MFX_HUFFTABLE_ID_UV
2483 };
2484
2485 static void
2486 gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2487                                struct decode_state *decode_state,
2488                                struct gen7_mfd_context *gen7_mfd_context,
2489                                int num_tables)
2490 {
2491     VAHuffmanTableBufferJPEGBaseline *huffman_table;
2492     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2493     int index;
2494
2495     if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2496         return;
2497
2498     huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2499
2500     for (index = 0; index < num_tables; index++) {
2501         int id = va_to_gen7_jpeg_hufftable[index];
2502         if (!huffman_table->load_huffman_table[index])
2503             continue;
2504         BEGIN_BCS_BATCH(batch, 53);
2505         OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2506         OUT_BCS_BATCH(batch, id);
2507         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2508         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2509         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2510         intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2511         ADVANCE_BCS_BATCH(batch);
2512     }
2513 }
2514
2515 static const int va_to_gen7_jpeg_qm[5] = {
2516     -1,
2517     MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2518     MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2519     MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2520     MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2521 };
2522
2523 static void
2524 gen75_mfd_jpeg_qm_state(VADriverContextP ctx,
2525                        struct decode_state *decode_state,
2526                        struct gen7_mfd_context *gen7_mfd_context)
2527 {
2528     VAPictureParameterBufferJPEGBaseline *pic_param;
2529     VAIQMatrixBufferJPEGBaseline *iq_matrix;
2530     int index;
2531
2532     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2533         return;
2534
2535     iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2536     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2537
2538     assert(pic_param->num_components <= 3);
2539
2540     for (index = 0; index < pic_param->num_components; index++) {
2541         int qm_type = va_to_gen7_jpeg_qm[pic_param->components[index].component_id - pic_param->components[0].component_id + 1];
2542         unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2543         unsigned char raster_qm[64];
2544         int j;
2545
2546         if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2547             continue;
2548
2549         for (j = 0; j < 64; j++)
2550             raster_qm[zigzag_direct[j]] = qm[j];
2551
2552         gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2553     }
2554 }
2555
2556 static void
2557 gen75_mfd_jpeg_bsd_object(VADriverContextP ctx,
2558                          VAPictureParameterBufferJPEGBaseline *pic_param,
2559                          VASliceParameterBufferJPEGBaseline *slice_param,
2560                          VASliceParameterBufferJPEGBaseline *next_slice_param,
2561                          dri_bo *slice_data_bo,
2562                          struct gen7_mfd_context *gen7_mfd_context)
2563 {
2564     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2565     int scan_component_mask = 0;
2566     int i;
2567
2568     assert(slice_param->num_components > 0);
2569     assert(slice_param->num_components < 4);
2570     assert(slice_param->num_components <= pic_param->num_components);
2571
2572     for (i = 0; i < slice_param->num_components; i++) {
2573         switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2574         case 1:
2575             scan_component_mask |= (1 << 0);
2576             break;
2577         case 2:
2578             scan_component_mask |= (1 << 1);
2579             break;
2580         case 3:
2581             scan_component_mask |= (1 << 2);
2582             break;
2583         default:
2584             assert(0);
2585             break;
2586         }
2587     }
2588
2589     BEGIN_BCS_BATCH(batch, 6);
2590     OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2591     OUT_BCS_BATCH(batch,
2592                   slice_param->slice_data_size);
2593     OUT_BCS_BATCH(batch,
2594                   slice_param->slice_data_offset);
2595     OUT_BCS_BATCH(batch,
2596                   slice_param->slice_horizontal_position << 16 |
2597                   slice_param->slice_vertical_position << 0);
2598     OUT_BCS_BATCH(batch,
2599                   ((slice_param->num_components != 1) << 30) |  /* interleaved */
2600                   (scan_component_mask << 27) |                 /* scan components */
2601                   (0 << 26) |   /* disable interrupt allowed */
2602                   (slice_param->num_mcus << 0));                /* MCU count */
2603     OUT_BCS_BATCH(batch,
2604                   (slice_param->restart_interval << 0));    /* RestartInterval */
2605     ADVANCE_BCS_BATCH(batch);
2606 }
2607
2608 /* Workaround for JPEG decoding on Ivybridge */
2609
2610 VAStatus
2611 i965_DestroySurfaces(VADriverContextP ctx,
2612                      VASurfaceID *surface_list,
2613                      int num_surfaces);
2614 VAStatus
2615 i965_CreateSurfaces(VADriverContextP ctx,
2616                     int width,
2617                     int height,
2618                     int format,
2619                     int num_surfaces,
2620                     VASurfaceID *surfaces);
2621
2622 static struct {
2623     int width;
2624     int height;
2625     unsigned char data[32];
2626     int data_size;
2627     int data_bit_offset;
2628     int qp;
2629 } gen7_jpeg_wa_clip = {
2630     16,
2631     16,
2632     {
2633         0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2634         0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2635     },
2636     14,
2637     40,
2638     28,
2639 };
2640
2641 static void
2642 gen75_jpeg_wa_init(VADriverContextP ctx,
2643                   struct gen7_mfd_context *gen7_mfd_context)
2644 {
2645     struct i965_driver_data *i965 = i965_driver_data(ctx);
2646     VAStatus status;
2647     struct object_surface *obj_surface;
2648
2649     if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2650         i965_DestroySurfaces(ctx,
2651                              &gen7_mfd_context->jpeg_wa_surface_id,
2652                              1);
2653
2654     status = i965_CreateSurfaces(ctx,
2655                                  gen7_jpeg_wa_clip.width,
2656                                  gen7_jpeg_wa_clip.height,
2657                                  VA_RT_FORMAT_YUV420,
2658                                  1,
2659                                  &gen7_mfd_context->jpeg_wa_surface_id);
2660     assert(status == VA_STATUS_SUCCESS);
2661
2662     obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2663     assert(obj_surface);
2664     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
2665
2666     if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2667         gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2668                                                                "JPEG WA data",
2669                                                                0x1000,
2670                                                                0x1000);
2671         dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2672                        0,
2673                        gen7_jpeg_wa_clip.data_size,
2674                        gen7_jpeg_wa_clip.data);
2675     }
2676 }
2677
2678 static void
2679 gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2680                               struct gen7_mfd_context *gen7_mfd_context)
2681 {
2682     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2683
2684     BEGIN_BCS_BATCH(batch, 5);
2685     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2686     OUT_BCS_BATCH(batch,
2687                   (MFX_LONG_MODE << 17) | /* Currently only support long format */
2688                   (MFD_MODE_VLD << 15) | /* VLD mode */
2689                   (0 << 10) | /* disable Stream-Out */
2690                   (0 << 9)  | /* Post Deblocking Output */
2691                   (1 << 8)  | /* Pre Deblocking Output */
2692                   (0 << 5)  | /* not in stitch mode */
2693                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
2694                   (MFX_FORMAT_AVC << 0));
2695     OUT_BCS_BATCH(batch,
2696                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
2697                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
2698                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
2699                   (0 << 1)  |
2700                   (0 << 0));
2701     OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2702     OUT_BCS_BATCH(batch, 0); /* reserved */
2703     ADVANCE_BCS_BATCH(batch);
2704 }
2705
2706 static void
2707 gen75_jpeg_wa_surface_state(VADriverContextP ctx,
2708                            struct gen7_mfd_context *gen7_mfd_context)
2709 {
2710     struct i965_driver_data *i965 = i965_driver_data(ctx);
2711     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2712     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2713
2714     BEGIN_BCS_BATCH(batch, 6);
2715     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2716     OUT_BCS_BATCH(batch, 0);
2717     OUT_BCS_BATCH(batch,
2718                   ((obj_surface->orig_width - 1) << 18) |
2719                   ((obj_surface->orig_height - 1) << 4));
2720     OUT_BCS_BATCH(batch,
2721                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2722                   (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2723                   (0 << 22) | /* surface object control state, ignored */
2724                   ((obj_surface->width - 1) << 3) | /* pitch */
2725                   (0 << 2)  | /* must be 0 */
2726                   (1 << 1)  | /* must be tiled */
2727                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, must be 1 */
2728     OUT_BCS_BATCH(batch,
2729                   (0 << 16) | /* X offset for U(Cb), must be 0 */
2730                   (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2731     OUT_BCS_BATCH(batch,
2732                   (0 << 16) | /* X offset for V(Cr), must be 0 */
2733                   (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2734     ADVANCE_BCS_BATCH(batch);
2735 }
2736
2737 static void
2738 gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx,
2739                                  struct gen7_mfd_context *gen7_mfd_context)
2740 {
2741     struct i965_driver_data *i965 = i965_driver_data(ctx);
2742     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2743     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2744     dri_bo *intra_bo;
2745     int i;
2746
2747     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2748                             "intra row store",
2749                             128 * 64,
2750                             0x1000);
2751
2752     BEGIN_BCS_BATCH(batch, 61);
2753     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
2754     OUT_BCS_RELOC(batch,
2755                   obj_surface->bo,
2756                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2757                   0);
2758         OUT_BCS_BATCH(batch, 0);
2759         OUT_BCS_BATCH(batch, 0);
2760
2761
2762     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2763         OUT_BCS_BATCH(batch, 0);
2764         OUT_BCS_BATCH(batch, 0);
2765
2766         /* uncompressed-video & stream out 7-12 */
2767     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2768     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2769         OUT_BCS_BATCH(batch, 0);
2770         OUT_BCS_BATCH(batch, 0);
2771         OUT_BCS_BATCH(batch, 0);
2772         OUT_BCS_BATCH(batch, 0);
2773
2774         /* the DW 13-15 is for intra row store scratch */
2775     OUT_BCS_RELOC(batch,
2776                   intra_bo,
2777                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2778                   0);
2779         OUT_BCS_BATCH(batch, 0);
2780         OUT_BCS_BATCH(batch, 0);
2781
2782         /* the DW 16-18 is for deblocking filter */
2783     OUT_BCS_BATCH(batch, 0);
2784         OUT_BCS_BATCH(batch, 0);
2785         OUT_BCS_BATCH(batch, 0);
2786
2787     /* DW 19..50 */
2788     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2789         OUT_BCS_BATCH(batch, 0);
2790         OUT_BCS_BATCH(batch, 0);
2791     }
2792     OUT_BCS_BATCH(batch, 0);
2793
2794         /* the DW52-54 is for mb status address */
2795     OUT_BCS_BATCH(batch, 0);
2796         OUT_BCS_BATCH(batch, 0);
2797         OUT_BCS_BATCH(batch, 0);
2798         /* the DW56-60 is for ILDB & second ILDB address */
2799     OUT_BCS_BATCH(batch, 0);
2800         OUT_BCS_BATCH(batch, 0);
2801         OUT_BCS_BATCH(batch, 0);
2802     OUT_BCS_BATCH(batch, 0);
2803         OUT_BCS_BATCH(batch, 0);
2804         OUT_BCS_BATCH(batch, 0);
2805
2806     ADVANCE_BCS_BATCH(batch);
2807
2808     dri_bo_unreference(intra_bo);
2809 }
2810 static void
2811 gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2812                                  struct gen7_mfd_context *gen7_mfd_context)
2813 {
2814     struct i965_driver_data *i965 = i965_driver_data(ctx);
2815     struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2816     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2817     dri_bo *intra_bo;
2818     int i;
2819
2820         if (IS_STEPPING_BPLUS(i965)) {
2821                 gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context);
2822                 return;
2823         }
2824     intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2825                             "intra row store",
2826                             128 * 64,
2827                             0x1000);
2828
2829     BEGIN_BCS_BATCH(batch, 25);
2830     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
2831     OUT_BCS_RELOC(batch,
2832                   obj_surface->bo,
2833                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2834                   0);
2835
2836     OUT_BCS_BATCH(batch, 0); /* post deblocking */
2837
2838     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2839     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2840
2841     OUT_BCS_RELOC(batch,
2842                   intra_bo,
2843                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2844                   0);
2845
2846     OUT_BCS_BATCH(batch, 0);
2847
2848     /* DW 7..22 */
2849     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2850         OUT_BCS_BATCH(batch, 0);
2851     }
2852
2853     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
2854     OUT_BCS_BATCH(batch, 0);
2855     ADVANCE_BCS_BATCH(batch);
2856
2857     dri_bo_unreference(intra_bo);
2858 }
2859
2860 static void
2861 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
2862                                      struct gen7_mfd_context *gen7_mfd_context)
2863 {
2864     struct i965_driver_data *i965 = i965_driver_data(ctx);
2865     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2866     dri_bo *bsd_mpc_bo, *mpr_bo;
2867
2868     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2869                               "bsd mpc row store",
2870                               11520, /* 1.5 * 120 * 64 */
2871                               0x1000);
2872
2873     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2874                           "mpr row store",
2875                           7680, /* 1. 0 * 120 * 64 */
2876                           0x1000);
2877
2878     BEGIN_BCS_BATCH(batch, 10);
2879     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
2880
2881     OUT_BCS_RELOC(batch,
2882                   bsd_mpc_bo,
2883                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2884                   0);
2885
2886     OUT_BCS_BATCH(batch, 0);
2887     OUT_BCS_BATCH(batch, 0);
2888
2889     OUT_BCS_RELOC(batch,
2890                   mpr_bo,
2891                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2892                   0);
2893     OUT_BCS_BATCH(batch, 0);
2894     OUT_BCS_BATCH(batch, 0);
2895
2896     OUT_BCS_BATCH(batch, 0);
2897     OUT_BCS_BATCH(batch, 0);
2898     OUT_BCS_BATCH(batch, 0);
2899
2900     ADVANCE_BCS_BATCH(batch);
2901
2902     dri_bo_unreference(bsd_mpc_bo);
2903     dri_bo_unreference(mpr_bo);
2904 }
2905
2906 static void
2907 gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2908                                      struct gen7_mfd_context *gen7_mfd_context)
2909 {
2910     struct i965_driver_data *i965 = i965_driver_data(ctx);
2911     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2912     dri_bo *bsd_mpc_bo, *mpr_bo;
2913
2914     if (IS_STEPPING_BPLUS(i965)) {
2915         gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(ctx, gen7_mfd_context);
2916         return;
2917     }
2918
2919     bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2920                               "bsd mpc row store",
2921                               11520, /* 1.5 * 120 * 64 */
2922                               0x1000);
2923
2924     mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2925                           "mpr row store",
2926                           7680, /* 1. 0 * 120 * 64 */
2927                           0x1000);
2928
2929     BEGIN_BCS_BATCH(batch, 4);
2930     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2931
2932     OUT_BCS_RELOC(batch,
2933                   bsd_mpc_bo,
2934                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2935                   0);
2936
2937     OUT_BCS_RELOC(batch,
2938                   mpr_bo,
2939                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2940                   0);
2941     OUT_BCS_BATCH(batch, 0);
2942
2943     ADVANCE_BCS_BATCH(batch);
2944
2945     dri_bo_unreference(bsd_mpc_bo);
2946     dri_bo_unreference(mpr_bo);
2947 }
2948
2949 static void
2950 gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2951                           struct gen7_mfd_context *gen7_mfd_context)
2952 {
2953
2954 }
2955
2956 static void
2957 gen75_jpeg_wa_avc_img_state(VADriverContextP ctx,
2958                            struct gen7_mfd_context *gen7_mfd_context)
2959 {
2960     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2961     int img_struct = 0;
2962     int mbaff_frame_flag = 0;
2963     unsigned int width_in_mbs = 1, height_in_mbs = 1;
2964
2965     BEGIN_BCS_BATCH(batch, 16);
2966     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2967     OUT_BCS_BATCH(batch,
2968                   width_in_mbs * height_in_mbs);
2969     OUT_BCS_BATCH(batch,
2970                   ((height_in_mbs - 1) << 16) |
2971                   ((width_in_mbs - 1) << 0));
2972     OUT_BCS_BATCH(batch,
2973                   (0 << 24) |
2974                   (0 << 16) |
2975                   (0 << 14) |
2976                   (0 << 13) |
2977                   (0 << 12) | /* differ from GEN6 */
2978                   (0 << 10) |
2979                   (img_struct << 8));
2980     OUT_BCS_BATCH(batch,
2981                   (1 << 10) | /* 4:2:0 */
2982                   (1 << 7) |  /* CABAC */
2983                   (0 << 6) |
2984                   (0 << 5) |
2985                   (0 << 4) |
2986                   (0 << 3) |
2987                   (1 << 2) |
2988                   (mbaff_frame_flag << 1) |
2989                   (0 << 0));
2990     OUT_BCS_BATCH(batch, 0);
2991     OUT_BCS_BATCH(batch, 0);
2992     OUT_BCS_BATCH(batch, 0);
2993     OUT_BCS_BATCH(batch, 0);
2994     OUT_BCS_BATCH(batch, 0);
2995     OUT_BCS_BATCH(batch, 0);
2996     OUT_BCS_BATCH(batch, 0);
2997     OUT_BCS_BATCH(batch, 0);
2998     OUT_BCS_BATCH(batch, 0);
2999     OUT_BCS_BATCH(batch, 0);
3000     OUT_BCS_BATCH(batch, 0);
3001     ADVANCE_BCS_BATCH(batch);
3002 }
3003
3004 static void
3005 gen75_jpeg_wa_avc_directmode_state_bplus(VADriverContextP ctx,
3006                                   struct gen7_mfd_context *gen7_mfd_context)
3007 {
3008     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3009     int i;
3010
3011     BEGIN_BCS_BATCH(batch, 71);
3012     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
3013
3014     /* reference surfaces 0..15 */
3015     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3016         OUT_BCS_BATCH(batch, 0); /* top */
3017         OUT_BCS_BATCH(batch, 0); /* bottom */
3018     }
3019
3020         OUT_BCS_BATCH(batch, 0);
3021
3022     /* the current decoding frame/field */
3023     OUT_BCS_BATCH(batch, 0); /* top */
3024     OUT_BCS_BATCH(batch, 0);
3025     OUT_BCS_BATCH(batch, 0);
3026
3027     /* POC List */
3028     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3029         OUT_BCS_BATCH(batch, 0);
3030         OUT_BCS_BATCH(batch, 0);
3031     }
3032
3033     OUT_BCS_BATCH(batch, 0);
3034     OUT_BCS_BATCH(batch, 0);
3035
3036     ADVANCE_BCS_BATCH(batch);
3037 }
3038
3039 static void
3040 gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
3041                                   struct gen7_mfd_context *gen7_mfd_context)
3042 {
3043     struct i965_driver_data *i965 = i965_driver_data(ctx);
3044     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3045     int i;
3046
3047     if (IS_STEPPING_BPLUS(i965)) {
3048         gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context);
3049         return;
3050     }
3051
3052     BEGIN_BCS_BATCH(batch, 69);
3053     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
3054
3055     /* reference surfaces 0..15 */
3056     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3057         OUT_BCS_BATCH(batch, 0); /* top */
3058         OUT_BCS_BATCH(batch, 0); /* bottom */
3059     }
3060
3061     /* the current decoding frame/field */
3062     OUT_BCS_BATCH(batch, 0); /* top */
3063     OUT_BCS_BATCH(batch, 0); /* bottom */
3064
3065     /* POC List */
3066     for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3067         OUT_BCS_BATCH(batch, 0);
3068         OUT_BCS_BATCH(batch, 0);
3069     }
3070
3071     OUT_BCS_BATCH(batch, 0);
3072     OUT_BCS_BATCH(batch, 0);
3073
3074     ADVANCE_BCS_BATCH(batch);
3075 }
3076
3077 static void
3078 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
3079                                      struct gen7_mfd_context *gen7_mfd_context)
3080 {
3081     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3082
3083     BEGIN_BCS_BATCH(batch, 11);
3084     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3085     OUT_BCS_RELOC(batch,
3086                   gen7_mfd_context->jpeg_wa_slice_data_bo,
3087                   I915_GEM_DOMAIN_INSTRUCTION, 0,
3088                   0);
3089     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3090     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3091     OUT_BCS_BATCH(batch, 0);
3092     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3093     OUT_BCS_BATCH(batch, 0);
3094     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3095     OUT_BCS_BATCH(batch, 0);
3096     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3097     OUT_BCS_BATCH(batch, 0);
3098     ADVANCE_BCS_BATCH(batch);
3099 }
3100
3101 static void
3102 gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
3103                                      struct gen7_mfd_context *gen7_mfd_context)
3104 {
3105     struct i965_driver_data *i965 = i965_driver_data(ctx);
3106     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3107
3108     if (IS_STEPPING_BPLUS(i965)) {
3109         gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context);
3110         return;
3111     }
3112     BEGIN_BCS_BATCH(batch, 11);
3113     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3114     OUT_BCS_RELOC(batch,
3115                   gen7_mfd_context->jpeg_wa_slice_data_bo,
3116                   I915_GEM_DOMAIN_INSTRUCTION, 0,
3117                   0);
3118     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3119     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3120     OUT_BCS_BATCH(batch, 0);
3121     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3122     OUT_BCS_BATCH(batch, 0);
3123     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3124     OUT_BCS_BATCH(batch, 0);
3125     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3126     OUT_BCS_BATCH(batch, 0);
3127     ADVANCE_BCS_BATCH(batch);
3128 }
3129
3130 static void
3131 gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
3132                             struct gen7_mfd_context *gen7_mfd_context)
3133 {
3134     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3135
3136     /* the input bitsteam format on GEN7 differs from GEN6 */
3137     BEGIN_BCS_BATCH(batch, 6);
3138     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
3139     OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
3140     OUT_BCS_BATCH(batch, 0);
3141     OUT_BCS_BATCH(batch,
3142                   (0 << 31) |
3143                   (0 << 14) |
3144                   (0 << 12) |
3145                   (0 << 10) |
3146                   (0 << 8));
3147     OUT_BCS_BATCH(batch,
3148                   ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
3149                   (0 << 5)  |
3150                   (0 << 4)  |
3151                   (1 << 3) | /* LastSlice Flag */
3152                   (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
3153     OUT_BCS_BATCH(batch, 0);
3154     ADVANCE_BCS_BATCH(batch);
3155 }
3156
3157 static void
3158 gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx,
3159                              struct gen7_mfd_context *gen7_mfd_context)
3160 {
3161     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3162     int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
3163     int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
3164     int first_mb_in_slice = 0;
3165     int slice_type = SLICE_TYPE_I;
3166
3167     BEGIN_BCS_BATCH(batch, 11);
3168     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
3169     OUT_BCS_BATCH(batch, slice_type);
3170     OUT_BCS_BATCH(batch,
3171                   (num_ref_idx_l1 << 24) |
3172                   (num_ref_idx_l0 << 16) |
3173                   (0 << 8) |
3174                   (0 << 0));
3175     OUT_BCS_BATCH(batch,
3176                   (0 << 29) |
3177                   (1 << 27) |   /* disable Deblocking */
3178                   (0 << 24) |
3179                   (gen7_jpeg_wa_clip.qp << 16) |
3180                   (0 << 8) |
3181                   (0 << 0));
3182     OUT_BCS_BATCH(batch,
3183                   (slice_ver_pos << 24) |
3184                   (slice_hor_pos << 16) |
3185                   (first_mb_in_slice << 0));
3186     OUT_BCS_BATCH(batch,
3187                   (next_slice_ver_pos << 16) |
3188                   (next_slice_hor_pos << 0));
3189     OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
3190     OUT_BCS_BATCH(batch, 0);
3191     OUT_BCS_BATCH(batch, 0);
3192     OUT_BCS_BATCH(batch, 0);
3193     OUT_BCS_BATCH(batch, 0);
3194     ADVANCE_BCS_BATCH(batch);
3195 }
3196
3197 static void
3198 gen75_mfd_jpeg_wa(VADriverContextP ctx,
3199                  struct gen7_mfd_context *gen7_mfd_context)
3200 {
3201     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3202     gen75_jpeg_wa_init(ctx, gen7_mfd_context);
3203     intel_batchbuffer_emit_mi_flush(batch);
3204     gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
3205     gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context);
3206     gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
3207     gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
3208     gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
3209     gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
3210     gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
3211
3212     gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
3213     gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
3214     gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
3215 }
3216
3217 void
3218 gen75_mfd_jpeg_decode_picture(VADriverContextP ctx,
3219                              struct decode_state *decode_state,
3220                              struct gen7_mfd_context *gen7_mfd_context)
3221 {
3222     struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3223     VAPictureParameterBufferJPEGBaseline *pic_param;
3224     VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
3225     dri_bo *slice_data_bo;
3226     int i, j, max_selector = 0;
3227
3228     assert(decode_state->pic_param && decode_state->pic_param->buffer);
3229     pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
3230
3231     /* Currently only support Baseline DCT */
3232     gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
3233     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
3234     gen75_mfd_jpeg_wa(ctx, gen7_mfd_context);
3235     intel_batchbuffer_emit_mi_flush(batch);
3236     gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3237     gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3238     gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3239     gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
3240     gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
3241
3242     for (j = 0; j < decode_state->num_slice_params; j++) {
3243         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3244         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3245         slice_data_bo = decode_state->slice_datas[j]->bo;
3246         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3247
3248         if (j == decode_state->num_slice_params - 1)
3249             next_slice_group_param = NULL;
3250         else
3251             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3252
3253         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3254             int component;
3255
3256             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3257
3258             if (i < decode_state->slice_params[j]->num_elements - 1)
3259                 next_slice_param = slice_param + 1;
3260             else
3261                 next_slice_param = next_slice_group_param;
3262
3263             for (component = 0; component < slice_param->num_components; component++) {
3264                 if (max_selector < slice_param->components[component].dc_table_selector)
3265                     max_selector = slice_param->components[component].dc_table_selector;
3266
3267                 if (max_selector < slice_param->components[component].ac_table_selector)
3268                     max_selector = slice_param->components[component].ac_table_selector;
3269             }
3270
3271             slice_param++;
3272         }
3273     }
3274
3275     assert(max_selector < 2);
3276     gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
3277
3278     for (j = 0; j < decode_state->num_slice_params; j++) {
3279         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3280         slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3281         slice_data_bo = decode_state->slice_datas[j]->bo;
3282         gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3283
3284         if (j == decode_state->num_slice_params - 1)
3285             next_slice_group_param = NULL;
3286         else
3287             next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3288
3289         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3290             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3291
3292             if (i < decode_state->slice_params[j]->num_elements - 1)
3293                 next_slice_param = slice_param + 1;
3294             else
3295                 next_slice_param = next_slice_group_param;
3296
3297             gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
3298             slice_param++;
3299         }
3300     }
3301
3302     intel_batchbuffer_end_atomic(batch);
3303     intel_batchbuffer_flush(batch);
3304 }
3305
3306 static void
3307 gen75_mfd_decode_picture(VADriverContextP ctx,
3308                         VAProfile profile,
3309                         union codec_state *codec_state,
3310                         struct hw_context *hw_context)
3311
3312 {
3313     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3314     struct decode_state *decode_state = &codec_state->decode;
3315
3316     assert(gen7_mfd_context);
3317
3318     gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
3319
3320     switch (profile) {
3321     case VAProfileMPEG2Simple:
3322     case VAProfileMPEG2Main:
3323         gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
3324         break;
3325
3326     case VAProfileH264Baseline:
3327     case VAProfileH264Main:
3328     case VAProfileH264High:
3329         gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
3330         break;
3331
3332     case VAProfileVC1Simple:
3333     case VAProfileVC1Main:
3334     case VAProfileVC1Advanced:
3335         gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
3336         break;
3337
3338     case VAProfileJPEGBaseline:
3339         gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
3340         break;
3341
3342     default:
3343         assert(0);
3344         break;
3345     }
3346 }
3347
3348 static void
3349 gen75_mfd_context_destroy(void *hw_context)
3350 {
3351     struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3352
3353     dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
3354     gen7_mfd_context->post_deblocking_output.bo = NULL;
3355
3356     dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
3357     gen7_mfd_context->pre_deblocking_output.bo = NULL;
3358
3359     dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
3360     gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
3361
3362     dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
3363     gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
3364
3365     dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
3366     gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
3367
3368     dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
3369     gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
3370
3371     dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
3372     gen7_mfd_context->bitplane_read_buffer.bo = NULL;
3373
3374     dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
3375
3376     intel_batchbuffer_free(gen7_mfd_context->base.batch);
3377     free(gen7_mfd_context);
3378 }
3379
3380 static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx,
3381                                     struct gen7_mfd_context *gen7_mfd_context)
3382 {
3383     gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
3384     gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
3385     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
3386     gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
3387 }
3388
3389 struct hw_context *
3390 gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
3391 {
3392     struct intel_driver_data *intel = intel_driver_data(ctx);
3393     struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
3394     int i;
3395
3396     gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
3397     gen7_mfd_context->base.run = gen75_mfd_decode_picture;
3398     gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
3399
3400     for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
3401         gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
3402         gen7_mfd_context->reference_surface[i].frame_store_id = -1;
3403     }
3404
3405     gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
3406
3407     switch (obj_config->profile) {
3408     case VAProfileMPEG2Simple:
3409     case VAProfileMPEG2Main:
3410         gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
3411         break;
3412
3413     case VAProfileH264Baseline:
3414     case VAProfileH264Main:
3415     case VAProfileH264High:
3416         gen75_mfd_avc_context_init(ctx, gen7_mfd_context);
3417         break;
3418     default:
3419         break;
3420     }
3421     return (struct hw_context *)gen7_mfd_context;
3422 }