2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
26 * Zhao Yakui <yakui.zhao@intel.com>
34 #include <va/va_dec_jpeg.h>
36 #include "intel_batchbuffer.h"
37 #include "intel_driver.h"
39 #include "i965_defines.h"
40 #include "i965_drv_video.h"
41 #include "i965_decoder_utils.h"
44 #include "intel_media.h"
47 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
49 static const uint32_t zigzag_direct[64] = {
50 0, 1, 8, 16, 9, 2, 3, 10,
51 17, 24, 32, 25, 18, 11, 4, 5,
52 12, 19, 26, 33, 40, 48, 41, 34,
53 27, 20, 13, 6, 7, 14, 21, 28,
54 35, 42, 49, 56, 57, 50, 43, 36,
55 29, 22, 15, 23, 30, 37, 44, 51,
56 58, 59, 52, 45, 38, 31, 39, 46,
57 53, 60, 61, 54, 47, 55, 62, 63
61 gen75_mfd_avc_frame_store_index(VADriverContextP ctx,
62 VAPictureParameterBufferH264 *pic_param,
63 struct gen7_mfd_context *gen7_mfd_context)
65 struct i965_driver_data *i965 = i965_driver_data(ctx);
68 assert(ARRAY_ELEMS(gen7_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
70 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
73 if (gen7_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
76 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
77 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
78 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
81 if (gen7_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
88 struct object_surface *obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
89 obj_surface->flags &= ~SURFACE_REFERENCED;
91 if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
92 dri_bo_unreference(obj_surface->bo);
93 obj_surface->bo = NULL;
94 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
97 if (obj_surface->free_private_data)
98 obj_surface->free_private_data(&obj_surface->private_data);
100 gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
101 gen7_mfd_context->reference_surface[i].frame_store_id = -1;
105 for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
106 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
109 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
112 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
113 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
116 if (gen7_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
124 struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
127 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
129 for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface); frame_idx++) {
130 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
131 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
134 if (gen7_mfd_context->reference_surface[j].frame_store_id == frame_idx)
138 if (j == ARRAY_ELEMS(gen7_mfd_context->reference_surface))
142 assert(frame_idx < ARRAY_ELEMS(gen7_mfd_context->reference_surface));
144 for (j = 0; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
145 if (gen7_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
146 gen7_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
147 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
155 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface) - 1; i++) {
156 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
157 gen7_mfd_context->reference_surface[i].frame_store_id == i)
160 for (j = i + 1; j < ARRAY_ELEMS(gen7_mfd_context->reference_surface); j++) {
161 if (gen7_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
162 gen7_mfd_context->reference_surface[j].frame_store_id == i) {
163 VASurfaceID id = gen7_mfd_context->reference_surface[i].surface_id;
164 int frame_idx = gen7_mfd_context->reference_surface[i].frame_store_id;
166 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[j].surface_id;
167 gen7_mfd_context->reference_surface[i].frame_store_id = gen7_mfd_context->reference_surface[j].frame_store_id;
168 gen7_mfd_context->reference_surface[j].surface_id = id;
169 gen7_mfd_context->reference_surface[j].frame_store_id = frame_idx;
177 gen75_mfd_init_avc_surface(VADriverContextP ctx,
178 VAPictureParameterBufferH264 *pic_param,
179 struct object_surface *obj_surface)
181 struct i965_driver_data *i965 = i965_driver_data(ctx);
182 GenAvcSurface *gen7_avc_surface = obj_surface->private_data;
183 int width_in_mbs, height_in_mbs;
185 obj_surface->free_private_data = gen_free_avc_surface;
186 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
187 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
189 if (!gen7_avc_surface) {
190 gen7_avc_surface = calloc(sizeof(GenAvcSurface), 1);
191 assert((obj_surface->size & 0x3f) == 0);
192 obj_surface->private_data = gen7_avc_surface;
195 gen7_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
196 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
198 if (gen7_avc_surface->dmv_top == NULL) {
199 gen7_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
200 "direct mv w/r buffer",
201 width_in_mbs * height_in_mbs * 128,
203 assert(gen7_avc_surface->dmv_top);
206 if (gen7_avc_surface->dmv_bottom_flag &&
207 gen7_avc_surface->dmv_bottom == NULL) {
208 gen7_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
209 "direct mv w/r buffer",
210 width_in_mbs * height_in_mbs * 128,
212 assert(gen7_avc_surface->dmv_bottom);
217 gen75_mfd_pipe_mode_select(VADriverContextP ctx,
218 struct decode_state *decode_state,
220 struct gen7_mfd_context *gen7_mfd_context)
222 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
224 assert(standard_select == MFX_FORMAT_MPEG2 ||
225 standard_select == MFX_FORMAT_AVC ||
226 standard_select == MFX_FORMAT_VC1 ||
227 standard_select == MFX_FORMAT_JPEG);
229 BEGIN_BCS_BATCH(batch, 5);
230 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
232 (MFX_LONG_MODE << 17) | /* Currently only support long format */
233 (MFD_MODE_VLD << 15) | /* VLD mode */
234 (0 << 10) | /* disable Stream-Out */
235 (gen7_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
236 (gen7_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
237 (0 << 5) | /* not in stitch mode */
238 (MFX_CODEC_DECODE << 4) | /* decoding mode */
239 (standard_select << 0));
241 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
242 (0 << 3) | /* terminate if AVC mbdata error occurs */
243 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
246 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
247 OUT_BCS_BATCH(batch, 0); /* reserved */
248 ADVANCE_BCS_BATCH(batch);
252 gen75_mfd_surface_state(VADriverContextP ctx,
253 struct decode_state *decode_state,
255 struct gen7_mfd_context *gen7_mfd_context)
257 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
258 struct i965_driver_data *i965 = i965_driver_data(ctx);
259 struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
260 unsigned int y_cb_offset;
261 unsigned int y_cr_offset;
265 y_cb_offset = obj_surface->y_cb_offset;
266 y_cr_offset = obj_surface->y_cr_offset;
268 BEGIN_BCS_BATCH(batch, 6);
269 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
270 OUT_BCS_BATCH(batch, 0);
272 ((obj_surface->orig_height - 1) << 18) |
273 ((obj_surface->orig_width - 1) << 4));
275 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
276 ((standard_select != MFX_FORMAT_JPEG) << 27) | /* interleave chroma, set to 0 for JPEG */
277 (0 << 22) | /* surface object control state, ignored */
278 ((obj_surface->width - 1) << 3) | /* pitch */
279 (0 << 2) | /* must be 0 */
280 (1 << 1) | /* must be tiled */
281 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
283 (0 << 16) | /* X offset for U(Cb), must be 0 */
284 (y_cb_offset << 0)); /* Y offset for U(Cb) */
286 (0 << 16) | /* X offset for V(Cr), must be 0 */
287 (y_cr_offset << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
288 ADVANCE_BCS_BATCH(batch);
292 gen75_mfd_pipe_buf_addr_state_bplus(VADriverContextP ctx,
293 struct decode_state *decode_state,
295 struct gen7_mfd_context *gen7_mfd_context)
297 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
298 struct i965_driver_data *i965 = i965_driver_data(ctx);
301 BEGIN_BCS_BATCH(batch, 61);
302 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
303 /* Pre-deblock 1-3 */
304 if (gen7_mfd_context->pre_deblocking_output.valid)
305 OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
306 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
309 OUT_BCS_BATCH(batch, 0);
311 OUT_BCS_BATCH(batch, 0);
312 OUT_BCS_BATCH(batch, 0);
313 /* Post-debloing 4-6 */
314 if (gen7_mfd_context->post_deblocking_output.valid)
315 OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
316 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
319 OUT_BCS_BATCH(batch, 0);
321 OUT_BCS_BATCH(batch, 0);
322 OUT_BCS_BATCH(batch, 0);
324 /* uncompressed-video & stream out 7-12 */
325 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
326 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
327 OUT_BCS_BATCH(batch, 0);
328 OUT_BCS_BATCH(batch, 0);
329 OUT_BCS_BATCH(batch, 0);
330 OUT_BCS_BATCH(batch, 0);
332 /* intra row-store scratch 13-15 */
333 if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
334 OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
335 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
338 OUT_BCS_BATCH(batch, 0);
340 OUT_BCS_BATCH(batch, 0);
341 OUT_BCS_BATCH(batch, 0);
342 /* deblocking-filter-row-store 16-18 */
343 if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
344 OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
345 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
348 OUT_BCS_BATCH(batch, 0);
349 OUT_BCS_BATCH(batch, 0);
350 OUT_BCS_BATCH(batch, 0);
353 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
354 struct object_surface *obj_surface;
356 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
357 obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
358 assert(obj_surface && obj_surface->bo);
360 OUT_BCS_RELOC(batch, obj_surface->bo,
361 I915_GEM_DOMAIN_INSTRUCTION, 0,
364 OUT_BCS_BATCH(batch, 0);
366 OUT_BCS_BATCH(batch, 0);
368 /* reference property 51 */
369 OUT_BCS_BATCH(batch, 0);
371 /* Macroblock status & ILDB 52-57 */
372 OUT_BCS_BATCH(batch, 0);
373 OUT_BCS_BATCH(batch, 0);
374 OUT_BCS_BATCH(batch, 0);
375 OUT_BCS_BATCH(batch, 0);
376 OUT_BCS_BATCH(batch, 0);
377 OUT_BCS_BATCH(batch, 0);
379 /* the second Macroblock status 58-60 */
380 OUT_BCS_BATCH(batch, 0);
381 OUT_BCS_BATCH(batch, 0);
382 OUT_BCS_BATCH(batch, 0);
383 ADVANCE_BCS_BATCH(batch);
387 gen75_mfd_pipe_buf_addr_state(VADriverContextP ctx,
388 struct decode_state *decode_state,
390 struct gen7_mfd_context *gen7_mfd_context)
392 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
393 struct i965_driver_data *i965 = i965_driver_data(ctx);
396 if (IS_STEPPING_BPLUS(i965)) {
397 gen75_mfd_pipe_buf_addr_state_bplus(ctx, decode_state,
398 standard_select, gen7_mfd_context);
401 BEGIN_BCS_BATCH(batch, 25);
402 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
403 if (gen7_mfd_context->pre_deblocking_output.valid)
404 OUT_BCS_RELOC(batch, gen7_mfd_context->pre_deblocking_output.bo,
405 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
408 OUT_BCS_BATCH(batch, 0);
410 if (gen7_mfd_context->post_deblocking_output.valid)
411 OUT_BCS_RELOC(batch, gen7_mfd_context->post_deblocking_output.bo,
412 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
415 OUT_BCS_BATCH(batch, 0);
417 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
418 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
420 if (gen7_mfd_context->intra_row_store_scratch_buffer.valid)
421 OUT_BCS_RELOC(batch, gen7_mfd_context->intra_row_store_scratch_buffer.bo,
422 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
425 OUT_BCS_BATCH(batch, 0);
427 if (gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
428 OUT_BCS_RELOC(batch, gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
429 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
432 OUT_BCS_BATCH(batch, 0);
435 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
436 struct object_surface *obj_surface;
438 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
439 obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
440 assert(obj_surface && obj_surface->bo);
442 OUT_BCS_RELOC(batch, obj_surface->bo,
443 I915_GEM_DOMAIN_INSTRUCTION, 0,
446 OUT_BCS_BATCH(batch, 0);
450 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
451 OUT_BCS_BATCH(batch, 0); /* ignore DW24 for decoding */
452 ADVANCE_BCS_BATCH(batch);
456 gen75_mfd_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
457 dri_bo *slice_data_bo,
459 struct gen7_mfd_context *gen7_mfd_context)
461 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
463 BEGIN_BCS_BATCH(batch, 26);
464 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
466 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
467 OUT_BCS_BATCH(batch, 0);
468 OUT_BCS_BATCH(batch, 0);
469 /* Upper bound 4-5 */
470 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
471 OUT_BCS_BATCH(batch, 0);
473 /* MFX indirect MV 6-10 */
474 OUT_BCS_BATCH(batch, 0);
475 OUT_BCS_BATCH(batch, 0);
476 OUT_BCS_BATCH(batch, 0);
477 OUT_BCS_BATCH(batch, 0);
478 OUT_BCS_BATCH(batch, 0);
480 /* MFX IT_COFF 11-15 */
481 OUT_BCS_BATCH(batch, 0);
482 OUT_BCS_BATCH(batch, 0);
483 OUT_BCS_BATCH(batch, 0);
484 OUT_BCS_BATCH(batch, 0);
485 OUT_BCS_BATCH(batch, 0);
487 /* MFX IT_DBLK 16-20 */
488 OUT_BCS_BATCH(batch, 0);
489 OUT_BCS_BATCH(batch, 0);
490 OUT_BCS_BATCH(batch, 0);
491 OUT_BCS_BATCH(batch, 0);
492 OUT_BCS_BATCH(batch, 0);
494 /* MFX PAK_BSE object for encoder 21-25 */
495 OUT_BCS_BATCH(batch, 0);
496 OUT_BCS_BATCH(batch, 0);
497 OUT_BCS_BATCH(batch, 0);
498 OUT_BCS_BATCH(batch, 0);
499 OUT_BCS_BATCH(batch, 0);
501 ADVANCE_BCS_BATCH(batch);
505 gen75_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
506 dri_bo *slice_data_bo,
508 struct gen7_mfd_context *gen7_mfd_context)
510 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
512 struct i965_driver_data *i965 = i965_driver_data(ctx);
514 if (IS_STEPPING_BPLUS(i965)) {
515 gen75_mfd_ind_obj_base_addr_state_bplus(ctx, slice_data_bo,
516 standard_select, gen7_mfd_context);
519 BEGIN_BCS_BATCH(batch, 11);
520 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
521 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
522 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
523 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
524 OUT_BCS_BATCH(batch, 0);
525 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
526 OUT_BCS_BATCH(batch, 0);
527 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
528 OUT_BCS_BATCH(batch, 0);
529 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
530 OUT_BCS_BATCH(batch, 0);
531 ADVANCE_BCS_BATCH(batch);
535 gen75_mfd_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
536 struct decode_state *decode_state,
538 struct gen7_mfd_context *gen7_mfd_context)
540 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
542 BEGIN_BCS_BATCH(batch, 10);
543 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
545 if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
546 OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
547 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
550 OUT_BCS_BATCH(batch, 0);
552 OUT_BCS_BATCH(batch, 0);
553 OUT_BCS_BATCH(batch, 0);
554 /* MPR Row Store Scratch buffer 4-6 */
555 if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
556 OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
557 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
560 OUT_BCS_BATCH(batch, 0);
561 OUT_BCS_BATCH(batch, 0);
562 OUT_BCS_BATCH(batch, 0);
565 if (gen7_mfd_context->bitplane_read_buffer.valid)
566 OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
567 I915_GEM_DOMAIN_INSTRUCTION, 0,
570 OUT_BCS_BATCH(batch, 0);
571 OUT_BCS_BATCH(batch, 0);
572 OUT_BCS_BATCH(batch, 0);
573 ADVANCE_BCS_BATCH(batch);
577 gen75_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
578 struct decode_state *decode_state,
580 struct gen7_mfd_context *gen7_mfd_context)
582 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
583 struct i965_driver_data *i965 = i965_driver_data(ctx);
585 if (IS_STEPPING_BPLUS(i965)) {
586 gen75_mfd_bsp_buf_base_addr_state_bplus(ctx, decode_state,
587 standard_select, gen7_mfd_context);
591 BEGIN_BCS_BATCH(batch, 4);
592 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
594 if (gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
595 OUT_BCS_RELOC(batch, gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
596 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
599 OUT_BCS_BATCH(batch, 0);
601 if (gen7_mfd_context->mpr_row_store_scratch_buffer.valid)
602 OUT_BCS_RELOC(batch, gen7_mfd_context->mpr_row_store_scratch_buffer.bo,
603 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
606 OUT_BCS_BATCH(batch, 0);
608 if (gen7_mfd_context->bitplane_read_buffer.valid)
609 OUT_BCS_RELOC(batch, gen7_mfd_context->bitplane_read_buffer.bo,
610 I915_GEM_DOMAIN_INSTRUCTION, 0,
613 OUT_BCS_BATCH(batch, 0);
615 ADVANCE_BCS_BATCH(batch);
620 gen7_mfd_aes_state(VADriverContextP ctx,
621 struct decode_state *decode_state,
629 gen75_mfd_qm_state(VADriverContextP ctx,
633 struct gen7_mfd_context *gen7_mfd_context)
635 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
636 unsigned int qm_buffer[16];
638 assert(qm_length <= 16 * 4);
639 memcpy(qm_buffer, qm, qm_length);
641 BEGIN_BCS_BATCH(batch, 18);
642 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
643 OUT_BCS_BATCH(batch, qm_type << 0);
644 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
645 ADVANCE_BCS_BATCH(batch);
650 gen7_mfd_wait(VADriverContextP ctx,
651 struct decode_state *decode_state,
653 struct gen7_mfd_context *gen7_mfd_context)
655 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
657 BEGIN_BCS_BATCH(batch, 1);
658 OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
659 ADVANCE_BCS_BATCH(batch);
664 gen75_mfd_avc_img_state(VADriverContextP ctx,
665 struct decode_state *decode_state,
666 struct gen7_mfd_context *gen7_mfd_context)
668 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
670 int mbaff_frame_flag;
671 unsigned int width_in_mbs, height_in_mbs;
672 VAPictureParameterBufferH264 *pic_param;
674 assert(decode_state->pic_param && decode_state->pic_param->buffer);
675 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
676 assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
678 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
680 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
685 if ((img_struct & 0x1) == 0x1) {
686 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
688 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
691 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
692 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
693 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
695 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
698 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
699 !pic_param->pic_fields.bits.field_pic_flag);
701 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
702 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
704 /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
705 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
706 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
707 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
709 BEGIN_BCS_BATCH(batch, 17);
710 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (17 - 2));
712 width_in_mbs * height_in_mbs);
714 ((height_in_mbs - 1) << 16) |
715 ((width_in_mbs - 1) << 0));
717 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
718 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
719 (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
720 (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
721 (pic_param->pic_fields.bits.weighted_pred_flag << 12) | /* differ from GEN6 */
722 (pic_param->pic_fields.bits.weighted_bipred_idc << 10) |
725 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
726 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
727 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
728 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
729 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
730 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
731 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
732 (mbaff_frame_flag << 1) |
733 (pic_param->pic_fields.bits.field_pic_flag << 0));
734 OUT_BCS_BATCH(batch, 0);
735 OUT_BCS_BATCH(batch, 0);
736 OUT_BCS_BATCH(batch, 0);
737 OUT_BCS_BATCH(batch, 0);
738 OUT_BCS_BATCH(batch, 0);
739 OUT_BCS_BATCH(batch, 0);
740 OUT_BCS_BATCH(batch, 0);
741 OUT_BCS_BATCH(batch, 0);
742 OUT_BCS_BATCH(batch, 0);
743 OUT_BCS_BATCH(batch, 0);
744 OUT_BCS_BATCH(batch, 0);
745 OUT_BCS_BATCH(batch, 0);
746 ADVANCE_BCS_BATCH(batch);
750 gen75_mfd_avc_qm_state(VADriverContextP ctx,
751 struct decode_state *decode_state,
752 struct gen7_mfd_context *gen7_mfd_context)
754 VAIQMatrixBufferH264 *iq_matrix;
755 VAPictureParameterBufferH264 *pic_param;
757 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
758 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
760 iq_matrix = &gen7_mfd_context->iq_matrix.h264;
762 assert(decode_state->pic_param && decode_state->pic_param->buffer);
763 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
765 gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, &iq_matrix->ScalingList4x4[0][0], 3 * 16, gen7_mfd_context);
766 gen75_mfd_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, &iq_matrix->ScalingList4x4[3][0], 3 * 16, gen7_mfd_context);
768 if (pic_param->pic_fields.bits.transform_8x8_mode_flag) {
769 gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, &iq_matrix->ScalingList8x8[0][0], 64, gen7_mfd_context);
770 gen75_mfd_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, &iq_matrix->ScalingList8x8[1][0], 64, gen7_mfd_context);
775 gen75_mfd_avc_picid_state(VADriverContextP ctx,
776 struct decode_state *decode_state,
777 struct gen7_mfd_context *gen7_mfd_context)
779 struct i965_driver_data *i965 = i965_driver_data(ctx);
780 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
782 BEGIN_BCS_BATCH(batch, 10);
783 OUT_BCS_BATCH(batch, MFD_AVC_PICID_STATE | (10 - 2));
784 OUT_BCS_BATCH(batch, 1); // disable Picture ID Remapping
785 OUT_BCS_BATCH(batch, 0);
786 OUT_BCS_BATCH(batch, 0);
787 OUT_BCS_BATCH(batch, 0);
788 OUT_BCS_BATCH(batch, 0);
789 OUT_BCS_BATCH(batch, 0);
790 OUT_BCS_BATCH(batch, 0);
791 OUT_BCS_BATCH(batch, 0);
792 OUT_BCS_BATCH(batch, 0);
793 ADVANCE_BCS_BATCH(batch);
797 gen75_mfd_avc_directmode_state_bplus(VADriverContextP ctx,
798 VAPictureParameterBufferH264 *pic_param,
799 VASliceParameterBufferH264 *slice_param,
800 struct gen7_mfd_context *gen7_mfd_context)
802 struct i965_driver_data *i965 = i965_driver_data(ctx);
803 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
804 struct object_surface *obj_surface;
805 GenAvcSurface *gen7_avc_surface;
806 VAPictureH264 *va_pic;
809 BEGIN_BCS_BATCH(batch, 71);
810 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
812 /* reference surfaces 0..15 */
813 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
814 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
815 obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
817 gen7_avc_surface = obj_surface->private_data;
819 if (gen7_avc_surface == NULL) {
820 OUT_BCS_BATCH(batch, 0);
821 OUT_BCS_BATCH(batch, 0);
823 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
824 I915_GEM_DOMAIN_INSTRUCTION, 0,
826 OUT_BCS_BATCH(batch, 0);
829 OUT_BCS_BATCH(batch, 0);
830 OUT_BCS_BATCH(batch, 0);
833 OUT_BCS_BATCH(batch, 0);
835 /* the current decoding frame/field */
836 va_pic = &pic_param->CurrPic;
837 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
838 obj_surface = SURFACE(va_pic->picture_id);
839 assert(obj_surface && obj_surface->bo && obj_surface->private_data);
840 gen7_avc_surface = obj_surface->private_data;
842 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
843 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
846 OUT_BCS_BATCH(batch, 0);
847 OUT_BCS_BATCH(batch, 0);
850 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
851 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
853 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
854 va_pic = &pic_param->ReferenceFrames[j];
856 if (va_pic->flags & VA_PICTURE_H264_INVALID)
859 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
866 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
868 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
869 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
871 OUT_BCS_BATCH(batch, 0);
872 OUT_BCS_BATCH(batch, 0);
876 va_pic = &pic_param->CurrPic;
877 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
878 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
880 ADVANCE_BCS_BATCH(batch);
884 gen75_mfd_avc_directmode_state(VADriverContextP ctx,
885 VAPictureParameterBufferH264 *pic_param,
886 VASliceParameterBufferH264 *slice_param,
887 struct gen7_mfd_context *gen7_mfd_context)
889 struct i965_driver_data *i965 = i965_driver_data(ctx);
890 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
891 struct object_surface *obj_surface;
892 GenAvcSurface *gen7_avc_surface;
893 VAPictureH264 *va_pic;
896 if (IS_STEPPING_BPLUS(i965)) {
897 gen75_mfd_avc_directmode_state_bplus(ctx, pic_param, slice_param,
903 BEGIN_BCS_BATCH(batch, 69);
904 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
906 /* reference surfaces 0..15 */
907 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
908 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
909 obj_surface = SURFACE(gen7_mfd_context->reference_surface[i].surface_id);
911 gen7_avc_surface = obj_surface->private_data;
913 if (gen7_avc_surface == NULL) {
914 OUT_BCS_BATCH(batch, 0);
915 OUT_BCS_BATCH(batch, 0);
917 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
918 I915_GEM_DOMAIN_INSTRUCTION, 0,
921 if (gen7_avc_surface->dmv_bottom_flag == 1)
922 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
923 I915_GEM_DOMAIN_INSTRUCTION, 0,
926 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
927 I915_GEM_DOMAIN_INSTRUCTION, 0,
931 OUT_BCS_BATCH(batch, 0);
932 OUT_BCS_BATCH(batch, 0);
936 /* the current decoding frame/field */
937 va_pic = &pic_param->CurrPic;
938 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
939 obj_surface = SURFACE(va_pic->picture_id);
940 assert(obj_surface && obj_surface->bo && obj_surface->private_data);
941 gen7_avc_surface = obj_surface->private_data;
943 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
944 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
947 if (gen7_avc_surface->dmv_bottom_flag == 1)
948 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_bottom,
949 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
952 OUT_BCS_RELOC(batch, gen7_avc_surface->dmv_top,
953 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
957 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
958 if (gen7_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
960 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
961 va_pic = &pic_param->ReferenceFrames[j];
963 if (va_pic->flags & VA_PICTURE_H264_INVALID)
966 if (va_pic->picture_id == gen7_mfd_context->reference_surface[i].surface_id) {
973 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
975 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
976 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
978 OUT_BCS_BATCH(batch, 0);
979 OUT_BCS_BATCH(batch, 0);
983 va_pic = &pic_param->CurrPic;
984 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
985 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
987 ADVANCE_BCS_BATCH(batch);
991 gen75_mfd_avc_slice_state(VADriverContextP ctx,
992 VAPictureParameterBufferH264 *pic_param,
993 VASliceParameterBufferH264 *slice_param,
994 VASliceParameterBufferH264 *next_slice_param,
995 struct gen7_mfd_context *gen7_mfd_context)
997 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
998 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
999 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1000 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
1001 int num_ref_idx_l0, num_ref_idx_l1;
1002 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
1003 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
1004 int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
1007 if (slice_param->slice_type == SLICE_TYPE_I ||
1008 slice_param->slice_type == SLICE_TYPE_SI) {
1009 slice_type = SLICE_TYPE_I;
1010 } else if (slice_param->slice_type == SLICE_TYPE_P ||
1011 slice_param->slice_type == SLICE_TYPE_SP) {
1012 slice_type = SLICE_TYPE_P;
1014 assert(slice_param->slice_type == SLICE_TYPE_B);
1015 slice_type = SLICE_TYPE_B;
1018 if (slice_type == SLICE_TYPE_I) {
1019 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
1020 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1023 } else if (slice_type == SLICE_TYPE_P) {
1024 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
1025 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1028 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
1029 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
1032 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
1033 slice_hor_pos = first_mb_in_slice % width_in_mbs;
1034 slice_ver_pos = first_mb_in_slice / width_in_mbs;
1036 if (next_slice_param) {
1037 first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
1038 next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
1039 next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
1041 next_slice_hor_pos = 0;
1042 next_slice_ver_pos = height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
1045 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
1046 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
1047 OUT_BCS_BATCH(batch, slice_type);
1048 OUT_BCS_BATCH(batch,
1049 (num_ref_idx_l1 << 24) |
1050 (num_ref_idx_l0 << 16) |
1051 (slice_param->chroma_log2_weight_denom << 8) |
1052 (slice_param->luma_log2_weight_denom << 0));
1053 OUT_BCS_BATCH(batch,
1054 (slice_param->direct_spatial_mv_pred_flag << 29) |
1055 (slice_param->disable_deblocking_filter_idc << 27) |
1056 (slice_param->cabac_init_idc << 24) |
1057 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
1058 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
1059 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
1060 OUT_BCS_BATCH(batch,
1061 (slice_ver_pos << 24) |
1062 (slice_hor_pos << 16) |
1063 (first_mb_in_slice << 0));
1064 OUT_BCS_BATCH(batch,
1065 (next_slice_ver_pos << 16) |
1066 (next_slice_hor_pos << 0));
1067 OUT_BCS_BATCH(batch,
1068 (next_slice_param == NULL) << 19); /* last slice flag */
1069 OUT_BCS_BATCH(batch, 0);
1070 OUT_BCS_BATCH(batch, 0);
1071 OUT_BCS_BATCH(batch, 0);
1072 OUT_BCS_BATCH(batch, 0);
1073 ADVANCE_BCS_BATCH(batch);
1077 gen75_mfd_avc_ref_idx_state(VADriverContextP ctx,
1078 VAPictureParameterBufferH264 *pic_param,
1079 VASliceParameterBufferH264 *slice_param,
1080 struct gen7_mfd_context *gen7_mfd_context)
1082 gen6_send_avc_ref_idx_state(
1083 gen7_mfd_context->base.batch,
1085 gen7_mfd_context->reference_surface
1090 gen75_mfd_avc_weightoffset_state(VADriverContextP ctx,
1091 VAPictureParameterBufferH264 *pic_param,
1092 VASliceParameterBufferH264 *slice_param,
1093 struct gen7_mfd_context *gen7_mfd_context)
1095 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1096 int i, j, num_weight_offset_table = 0;
1097 short weightoffsets[32 * 6];
1099 if ((slice_param->slice_type == SLICE_TYPE_P ||
1100 slice_param->slice_type == SLICE_TYPE_SP) &&
1101 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
1102 num_weight_offset_table = 1;
1105 if ((slice_param->slice_type == SLICE_TYPE_B) &&
1106 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
1107 num_weight_offset_table = 2;
1110 for (i = 0; i < num_weight_offset_table; i++) {
1111 BEGIN_BCS_BATCH(batch, 98);
1112 OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
1113 OUT_BCS_BATCH(batch, i);
1116 for (j = 0; j < 32; j++) {
1117 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
1118 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
1119 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
1120 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
1121 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
1122 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
1125 for (j = 0; j < 32; j++) {
1126 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
1127 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
1128 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
1129 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
1130 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
1131 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
1135 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
1136 ADVANCE_BCS_BATCH(batch);
1141 gen75_mfd_avc_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
1143 int out_slice_data_bit_offset;
1144 int slice_header_size = in_slice_data_bit_offset / 8;
1147 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1148 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
1153 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1155 if (mode_flag == ENTROPY_CABAC)
1156 out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
1158 return out_slice_data_bit_offset;
1162 gen75_mfd_avc_bsd_object(VADriverContextP ctx,
1163 VAPictureParameterBufferH264 *pic_param,
1164 VASliceParameterBufferH264 *slice_param,
1165 dri_bo *slice_data_bo,
1166 VASliceParameterBufferH264 *next_slice_param,
1167 struct gen7_mfd_context *gen7_mfd_context)
1169 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1170 int slice_data_bit_offset;
1171 uint8_t *slice_data = NULL;
1173 dri_bo_map(slice_data_bo, 0);
1174 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1175 slice_data_bit_offset = gen75_mfd_avc_get_slice_bit_offset(slice_data,
1176 pic_param->pic_fields.bits.entropy_coding_mode_flag,
1177 slice_param->slice_data_bit_offset);
1178 dri_bo_unmap(slice_data_bo);
1180 /* the input bitsteam format on GEN7 differs from GEN6 */
1181 BEGIN_BCS_BATCH(batch, 6);
1182 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
1183 OUT_BCS_BATCH(batch,
1184 (slice_param->slice_data_size));
1185 OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
1186 OUT_BCS_BATCH(batch,
1192 OUT_BCS_BATCH(batch,
1193 ((slice_data_bit_offset >> 3) << 16) |
1196 ((next_slice_param == NULL) << 3) | /* LastSlice Flag */
1197 (slice_data_bit_offset & 0x7));
1198 OUT_BCS_BATCH(batch, 0);
1199 ADVANCE_BCS_BATCH(batch);
1203 gen75_mfd_avc_context_init(
1204 VADriverContextP ctx,
1205 struct gen7_mfd_context *gen7_mfd_context
1208 /* Initialize flat scaling lists */
1209 avc_gen_default_iq_matrix(&gen7_mfd_context->iq_matrix.h264);
1213 gen75_mfd_avc_decode_init(VADriverContextP ctx,
1214 struct decode_state *decode_state,
1215 struct gen7_mfd_context *gen7_mfd_context)
1217 VAPictureParameterBufferH264 *pic_param;
1218 VASliceParameterBufferH264 *slice_param;
1219 VAPictureH264 *va_pic;
1220 struct i965_driver_data *i965 = i965_driver_data(ctx);
1221 struct object_surface *obj_surface;
1223 int i, j, enable_avc_ildb = 0;
1224 unsigned int width_in_mbs, height_in_mbs;
1226 for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
1227 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1228 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1230 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1231 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1232 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1233 (slice_param->slice_type == SLICE_TYPE_SI) ||
1234 (slice_param->slice_type == SLICE_TYPE_P) ||
1235 (slice_param->slice_type == SLICE_TYPE_SP) ||
1236 (slice_param->slice_type == SLICE_TYPE_B));
1238 if (slice_param->disable_deblocking_filter_idc != 1) {
1239 enable_avc_ildb = 1;
1247 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1248 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1249 gen75_mfd_avc_frame_store_index(ctx, pic_param, gen7_mfd_context);
1250 width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
1251 height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
1252 assert(width_in_mbs > 0 && width_in_mbs <= 256); /* 4K */
1253 assert(height_in_mbs > 0 && height_in_mbs <= 256);
1255 /* Current decoded picture */
1256 va_pic = &pic_param->CurrPic;
1257 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
1258 obj_surface = SURFACE(va_pic->picture_id);
1259 assert(obj_surface);
1260 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
1261 obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
1262 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1264 /* initial uv component for YUV400 case */
1265 if (pic_param->seq_fields.bits.chroma_format_idc == 0) {
1266 unsigned int uv_offset = obj_surface->width * obj_surface->height;
1267 unsigned int uv_size = obj_surface->width * obj_surface->height / 2;
1269 drm_intel_gem_bo_map_gtt(obj_surface->bo);
1270 memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size);
1271 drm_intel_gem_bo_unmap_gtt(obj_surface->bo);
1274 gen75_mfd_init_avc_surface(ctx, pic_param, obj_surface);
1276 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1277 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1278 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1279 gen7_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
1281 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1282 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1283 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1284 gen7_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
1286 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1287 bo = dri_bo_alloc(i965->intel.bufmgr,
1292 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1293 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1295 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1296 bo = dri_bo_alloc(i965->intel.bufmgr,
1297 "deblocking filter row store",
1298 width_in_mbs * 64 * 4,
1301 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1302 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1304 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1305 bo = dri_bo_alloc(i965->intel.bufmgr,
1306 "bsd mpc row store",
1307 width_in_mbs * 64 * 2,
1310 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1311 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1313 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
1314 bo = dri_bo_alloc(i965->intel.bufmgr,
1316 width_in_mbs * 64 * 2,
1319 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
1320 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1322 gen7_mfd_context->bitplane_read_buffer.valid = 0;
1326 gen75_mfd_avc_decode_picture(VADriverContextP ctx,
1327 struct decode_state *decode_state,
1328 struct gen7_mfd_context *gen7_mfd_context)
1330 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1331 VAPictureParameterBufferH264 *pic_param;
1332 VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1333 dri_bo *slice_data_bo;
1336 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1337 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1338 gen75_mfd_avc_decode_init(ctx, decode_state, gen7_mfd_context);
1340 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1341 intel_batchbuffer_emit_mi_flush(batch);
1342 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1343 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1344 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1345 gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen7_mfd_context);
1346 gen75_mfd_avc_qm_state(ctx, decode_state, gen7_mfd_context);
1347 gen75_mfd_avc_img_state(ctx, decode_state, gen7_mfd_context);
1348 gen75_mfd_avc_picid_state(ctx, decode_state, gen7_mfd_context);
1350 for (j = 0; j < decode_state->num_slice_params; j++) {
1351 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1352 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1353 slice_data_bo = decode_state->slice_datas[j]->bo;
1354 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen7_mfd_context);
1356 if (j == decode_state->num_slice_params - 1)
1357 next_slice_group_param = NULL;
1359 next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1361 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1362 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1363 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1364 (slice_param->slice_type == SLICE_TYPE_SI) ||
1365 (slice_param->slice_type == SLICE_TYPE_P) ||
1366 (slice_param->slice_type == SLICE_TYPE_SP) ||
1367 (slice_param->slice_type == SLICE_TYPE_B));
1369 if (i < decode_state->slice_params[j]->num_elements - 1)
1370 next_slice_param = slice_param + 1;
1372 next_slice_param = next_slice_group_param;
1374 gen75_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen7_mfd_context);
1375 gen75_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen7_mfd_context);
1376 gen75_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen7_mfd_context);
1377 gen75_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1378 gen75_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, next_slice_param, gen7_mfd_context);
1383 intel_batchbuffer_end_atomic(batch);
1384 intel_batchbuffer_flush(batch);
1388 gen75_mfd_mpeg2_decode_init(VADriverContextP ctx,
1389 struct decode_state *decode_state,
1390 struct gen7_mfd_context *gen7_mfd_context)
1392 VAPictureParameterBufferMPEG2 *pic_param;
1393 struct i965_driver_data *i965 = i965_driver_data(ctx);
1394 struct object_surface *obj_surface;
1396 unsigned int width_in_mbs;
1398 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1399 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1400 width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1402 mpeg2_set_reference_surfaces(
1404 gen7_mfd_context->reference_surface,
1409 /* Current decoded picture */
1410 obj_surface = SURFACE(decode_state->current_render_target);
1411 assert(obj_surface);
1412 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1414 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1415 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1416 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1417 gen7_mfd_context->pre_deblocking_output.valid = 1;
1419 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1420 bo = dri_bo_alloc(i965->intel.bufmgr,
1421 "bsd mpc row store",
1425 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1426 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1428 gen7_mfd_context->post_deblocking_output.valid = 0;
1429 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1430 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1431 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1432 gen7_mfd_context->bitplane_read_buffer.valid = 0;
1436 gen75_mfd_mpeg2_pic_state(VADriverContextP ctx,
1437 struct decode_state *decode_state,
1438 struct gen7_mfd_context *gen7_mfd_context)
1440 struct i965_driver_data * const i965 = i965_driver_data(ctx);
1441 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1442 VAPictureParameterBufferMPEG2 *pic_param;
1443 unsigned int slice_concealment_disable_bit = 0;
1445 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1446 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1448 slice_concealment_disable_bit = 1;
1450 BEGIN_BCS_BATCH(batch, 13);
1451 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1452 OUT_BCS_BATCH(batch,
1453 (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1454 ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1455 ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1456 ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1457 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1458 pic_param->picture_coding_extension.bits.picture_structure << 12 |
1459 pic_param->picture_coding_extension.bits.top_field_first << 11 |
1460 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1461 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1462 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1463 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1464 pic_param->picture_coding_extension.bits.alternate_scan << 6);
1465 OUT_BCS_BATCH(batch,
1466 pic_param->picture_coding_type << 9);
1467 OUT_BCS_BATCH(batch,
1468 (slice_concealment_disable_bit << 31) |
1469 ((ALIGN(pic_param->vertical_size, 16) / 16) - 1) << 16 |
1470 ((ALIGN(pic_param->horizontal_size, 16) / 16) - 1));
1471 OUT_BCS_BATCH(batch, 0);
1472 OUT_BCS_BATCH(batch, 0);
1473 OUT_BCS_BATCH(batch, 0);
1474 OUT_BCS_BATCH(batch, 0);
1475 OUT_BCS_BATCH(batch, 0);
1476 OUT_BCS_BATCH(batch, 0);
1477 OUT_BCS_BATCH(batch, 0);
1478 OUT_BCS_BATCH(batch, 0);
1479 OUT_BCS_BATCH(batch, 0);
1480 ADVANCE_BCS_BATCH(batch);
1484 gen75_mfd_mpeg2_qm_state(VADriverContextP ctx,
1485 struct decode_state *decode_state,
1486 struct gen7_mfd_context *gen7_mfd_context)
1488 VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen7_mfd_context->iq_matrix.mpeg2;
1491 /* Update internal QM state */
1492 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1493 VAIQMatrixBufferMPEG2 * const iq_matrix =
1494 (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1496 if (gen_iq_matrix->load_intra_quantiser_matrix == -1 ||
1497 iq_matrix->load_intra_quantiser_matrix) {
1498 gen_iq_matrix->load_intra_quantiser_matrix =
1499 iq_matrix->load_intra_quantiser_matrix;
1500 if (iq_matrix->load_intra_quantiser_matrix) {
1501 for (j = 0; j < 64; j++)
1502 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1503 iq_matrix->intra_quantiser_matrix[j];
1507 if (gen_iq_matrix->load_non_intra_quantiser_matrix == -1 ||
1508 iq_matrix->load_non_intra_quantiser_matrix) {
1509 gen_iq_matrix->load_non_intra_quantiser_matrix =
1510 iq_matrix->load_non_intra_quantiser_matrix;
1511 if (iq_matrix->load_non_intra_quantiser_matrix) {
1512 for (j = 0; j < 64; j++)
1513 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1514 iq_matrix->non_intra_quantiser_matrix[j];
1519 /* Commit QM state to HW */
1520 for (i = 0; i < 2; i++) {
1521 unsigned char *qm = NULL;
1525 if (gen_iq_matrix->load_intra_quantiser_matrix) {
1526 qm = gen_iq_matrix->intra_quantiser_matrix;
1527 qm_type = MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX;
1530 if (gen_iq_matrix->load_non_intra_quantiser_matrix) {
1531 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1532 qm_type = MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX;
1539 gen75_mfd_qm_state(ctx, qm_type, qm, 64, gen7_mfd_context);
1544 gen75_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1545 VAPictureParameterBufferMPEG2 *pic_param,
1546 VASliceParameterBufferMPEG2 *slice_param,
1547 VASliceParameterBufferMPEG2 *next_slice_param,
1548 struct gen7_mfd_context *gen7_mfd_context)
1550 struct i965_driver_data * const i965 = i965_driver_data(ctx);
1551 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1552 unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1553 int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1555 if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1556 pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1558 is_field_pic_wa = is_field_pic &&
1559 gen7_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1561 vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1562 hpos0 = slice_param->slice_horizontal_position;
1564 if (next_slice_param == NULL) {
1565 vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1568 vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1569 hpos1 = next_slice_param->slice_horizontal_position;
1572 mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1574 BEGIN_BCS_BATCH(batch, 5);
1575 OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1576 OUT_BCS_BATCH(batch,
1577 slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1578 OUT_BCS_BATCH(batch,
1579 slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1580 OUT_BCS_BATCH(batch,
1584 (next_slice_param == NULL) << 5 |
1585 (next_slice_param == NULL) << 3 |
1586 (slice_param->macroblock_offset & 0x7));
1587 OUT_BCS_BATCH(batch,
1588 (slice_param->quantiser_scale_code << 24) |
1589 (vpos1 << 8 | hpos1));
1590 ADVANCE_BCS_BATCH(batch);
1594 gen75_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1595 struct decode_state *decode_state,
1596 struct gen7_mfd_context *gen7_mfd_context)
1598 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1599 VAPictureParameterBufferMPEG2 *pic_param;
1600 VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1601 dri_bo *slice_data_bo;
1604 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1605 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1607 gen75_mfd_mpeg2_decode_init(ctx, decode_state, gen7_mfd_context);
1608 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1609 intel_batchbuffer_emit_mi_flush(batch);
1610 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1611 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1612 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1613 gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen7_mfd_context);
1614 gen75_mfd_mpeg2_pic_state(ctx, decode_state, gen7_mfd_context);
1615 gen75_mfd_mpeg2_qm_state(ctx, decode_state, gen7_mfd_context);
1617 if (gen7_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1618 gen7_mfd_context->wa_mpeg2_slice_vertical_position =
1619 mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1621 for (j = 0; j < decode_state->num_slice_params; j++) {
1622 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1623 slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1624 slice_data_bo = decode_state->slice_datas[j]->bo;
1625 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen7_mfd_context);
1627 if (j == decode_state->num_slice_params - 1)
1628 next_slice_group_param = NULL;
1630 next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1632 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1633 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1635 if (i < decode_state->slice_params[j]->num_elements - 1)
1636 next_slice_param = slice_param + 1;
1638 next_slice_param = next_slice_group_param;
1640 gen75_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen7_mfd_context);
1645 intel_batchbuffer_end_atomic(batch);
1646 intel_batchbuffer_flush(batch);
1649 static const int va_to_gen7_vc1_pic_type[5] = {
1653 GEN7_VC1_BI_PICTURE,
1657 static const int va_to_gen7_vc1_mv[4] = {
1659 2, /* 1-MV half-pel */
1660 3, /* 1-MV half-pef bilinear */
1664 static const int b_picture_scale_factor[21] = {
1665 128, 85, 170, 64, 192,
1666 51, 102, 153, 204, 43,
1667 215, 37, 74, 111, 148,
1668 185, 222, 32, 96, 160,
1672 static const int va_to_gen7_vc1_condover[3] = {
1678 static const int va_to_gen7_vc1_profile[4] = {
1679 GEN7_VC1_SIMPLE_PROFILE,
1680 GEN7_VC1_MAIN_PROFILE,
1681 GEN7_VC1_RESERVED_PROFILE,
1682 GEN7_VC1_ADVANCED_PROFILE
1686 gen75_mfd_free_vc1_surface(void **data)
1688 struct gen7_vc1_surface *gen7_vc1_surface = *data;
1690 if (!gen7_vc1_surface)
1693 dri_bo_unreference(gen7_vc1_surface->dmv);
1694 free(gen7_vc1_surface);
1699 gen75_mfd_init_vc1_surface(VADriverContextP ctx,
1700 VAPictureParameterBufferVC1 *pic_param,
1701 struct object_surface *obj_surface)
1703 struct i965_driver_data *i965 = i965_driver_data(ctx);
1704 struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data;
1705 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1706 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1708 obj_surface->free_private_data = gen75_mfd_free_vc1_surface;
1710 if (!gen7_vc1_surface) {
1711 gen7_vc1_surface = calloc(sizeof(struct gen7_vc1_surface), 1);
1712 assert((obj_surface->size & 0x3f) == 0);
1713 obj_surface->private_data = gen7_vc1_surface;
1716 gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1718 if (gen7_vc1_surface->dmv == NULL) {
1719 gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1720 "direct mv w/r buffer",
1721 width_in_mbs * height_in_mbs * 64,
1727 gen75_mfd_vc1_decode_init(VADriverContextP ctx,
1728 struct decode_state *decode_state,
1729 struct gen7_mfd_context *gen7_mfd_context)
1731 VAPictureParameterBufferVC1 *pic_param;
1732 struct i965_driver_data *i965 = i965_driver_data(ctx);
1733 struct object_surface *obj_surface;
1738 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1739 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1740 width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1742 /* reference picture */
1743 obj_surface = SURFACE(pic_param->forward_reference_picture);
1745 if (obj_surface && obj_surface->bo)
1746 gen7_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1748 gen7_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1750 obj_surface = SURFACE(pic_param->backward_reference_picture);
1752 if (obj_surface && obj_surface->bo)
1753 gen7_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1755 gen7_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1757 /* must do so !!! */
1758 for (i = 2; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++)
1759 gen7_mfd_context->reference_surface[i].surface_id = gen7_mfd_context->reference_surface[i % 2].surface_id;
1761 /* Current decoded picture */
1762 obj_surface = SURFACE(decode_state->current_render_target);
1763 assert(obj_surface);
1764 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1765 gen75_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1767 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
1768 gen7_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1769 dri_bo_reference(gen7_mfd_context->post_deblocking_output.bo);
1770 gen7_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1772 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
1773 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1774 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
1775 gen7_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1777 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
1778 bo = dri_bo_alloc(i965->intel.bufmgr,
1783 gen7_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1784 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1786 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1787 bo = dri_bo_alloc(i965->intel.bufmgr,
1788 "deblocking filter row store",
1789 width_in_mbs * 6 * 64,
1792 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1793 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1795 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1796 bo = dri_bo_alloc(i965->intel.bufmgr,
1797 "bsd mpc row store",
1801 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1802 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1804 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1806 gen7_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1807 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
1809 if (gen7_mfd_context->bitplane_read_buffer.valid) {
1810 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1811 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1812 int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1814 uint8_t *src = NULL, *dst = NULL;
1816 assert(decode_state->bit_plane->buffer);
1817 src = decode_state->bit_plane->buffer;
1819 bo = dri_bo_alloc(i965->intel.bufmgr,
1821 bitplane_width * height_in_mbs,
1824 gen7_mfd_context->bitplane_read_buffer.bo = bo;
1826 dri_bo_map(bo, True);
1827 assert(bo->virtual);
1830 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1831 for(src_w = 0; src_w < width_in_mbs; src_w++) {
1832 int src_index, dst_index;
1836 src_index = (src_h * width_in_mbs + src_w) / 2;
1837 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1838 src_value = ((src[src_index] >> src_shift) & 0xf);
1840 dst_index = src_w / 2;
1841 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1845 dst[src_w / 2] >>= 4;
1847 dst += bitplane_width;
1852 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
1856 gen75_mfd_vc1_pic_state(VADriverContextP ctx,
1857 struct decode_state *decode_state,
1858 struct gen7_mfd_context *gen7_mfd_context)
1860 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
1861 VAPictureParameterBufferVC1 *pic_param;
1862 struct i965_driver_data *i965 = i965_driver_data(ctx);
1863 struct object_surface *obj_surface;
1864 int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1865 int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1866 int unified_mv_mode;
1867 int ref_field_pic_polarity = 0;
1868 int scale_factor = 0;
1870 int dmv_surface_valid = 0;
1876 int interpolation_mode = 0;
1878 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1879 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1881 profile = va_to_gen7_vc1_profile[pic_param->sequence_fields.bits.profile];
1882 dquant = pic_param->pic_quantizer_fields.bits.dquant;
1883 dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1884 dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1885 dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1886 dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1887 dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1888 alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1891 alt_pquant_config = 0;
1892 alt_pquant_edge_mask = 0;
1893 } else if (dquant == 2) {
1894 alt_pquant_config = 1;
1895 alt_pquant_edge_mask = 0xf;
1897 assert(dquant == 1);
1898 if (dquantfrm == 0) {
1899 alt_pquant_config = 0;
1900 alt_pquant_edge_mask = 0;
1903 assert(dquantfrm == 1);
1904 alt_pquant_config = 1;
1906 switch (dqprofile) {
1908 if (dqbilevel == 0) {
1909 alt_pquant_config = 2;
1910 alt_pquant_edge_mask = 0;
1912 assert(dqbilevel == 1);
1913 alt_pquant_config = 3;
1914 alt_pquant_edge_mask = 0;
1919 alt_pquant_edge_mask = 0xf;
1924 alt_pquant_edge_mask = 0x9;
1926 alt_pquant_edge_mask = (0x3 << dqdbedge);
1931 alt_pquant_edge_mask = (0x1 << dqsbedge);
1940 if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1941 assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1942 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1944 assert(pic_param->mv_fields.bits.mv_mode < 4);
1945 unified_mv_mode = va_to_gen7_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1948 if (pic_param->sequence_fields.bits.interlace == 1 &&
1949 pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1950 /* FIXME: calculate reference field picture polarity */
1952 ref_field_pic_polarity = 0;
1955 if (pic_param->b_picture_fraction < 21)
1956 scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1958 picture_type = va_to_gen7_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1960 if (profile == GEN7_VC1_ADVANCED_PROFILE &&
1961 picture_type == GEN7_VC1_I_PICTURE)
1962 picture_type = GEN7_VC1_BI_PICTURE;
1964 if (picture_type == GEN7_VC1_I_PICTURE || picture_type == GEN7_VC1_BI_PICTURE) /* I picture */
1965 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1967 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1970 if (picture_type == GEN7_VC1_B_PICTURE) {
1971 struct gen7_vc1_surface *gen7_vc1_surface = NULL;
1973 obj_surface = SURFACE(pic_param->backward_reference_picture);
1974 assert(obj_surface);
1975 gen7_vc1_surface = obj_surface->private_data;
1977 if (!gen7_vc1_surface ||
1978 (va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_I_PICTURE ||
1979 va_to_gen7_vc1_pic_type[gen7_vc1_surface->picture_type] == GEN7_VC1_BI_PICTURE))
1980 dmv_surface_valid = 0;
1982 dmv_surface_valid = 1;
1985 assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1987 if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1988 fcm = pic_param->picture_fields.bits.frame_coding_mode;
1990 if (pic_param->picture_fields.bits.top_field_first)
1996 if (pic_param->picture_fields.bits.picture_type == GEN7_VC1_B_PICTURE) { /* B picture */
1997 brfd = pic_param->reference_fields.bits.reference_distance;
1998 brfd = (scale_factor * brfd) >> 8;
1999 brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
2005 overlap = pic_param->sequence_fields.bits.overlap;
2006 if (profile != GEN7_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
2009 assert(pic_param->conditional_overlap_flag < 3);
2010 assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
2012 if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
2013 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2014 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
2015 interpolation_mode = 9; /* Half-pel bilinear */
2016 else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
2017 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
2018 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
2019 interpolation_mode = 1; /* Half-pel bicubic */
2021 interpolation_mode = 0; /* Quarter-pel bicubic */
2023 BEGIN_BCS_BATCH(batch, 6);
2024 OUT_BCS_BATCH(batch, MFD_VC1_LONG_PIC_STATE | (6 - 2));
2025 OUT_BCS_BATCH(batch,
2026 (((ALIGN(pic_param->coded_height, 16) / 16) - 1) << 16) |
2027 ((ALIGN(pic_param->coded_width, 16) / 16) - 1));
2028 OUT_BCS_BATCH(batch,
2029 ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1) << 24 |
2030 dmv_surface_valid << 15 |
2031 (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 14 | /* implicit quantizer */
2032 pic_param->rounding_control << 13 |
2033 pic_param->sequence_fields.bits.syncmarker << 12 |
2034 interpolation_mode << 8 |
2035 0 << 7 | /* FIXME: scale up or down ??? */
2036 pic_param->range_reduction_frame << 6 |
2037 pic_param->entrypoint_fields.bits.loopfilter << 5 |
2039 !pic_param->picture_fields.bits.is_first_field << 3 |
2040 (pic_param->sequence_fields.bits.profile == 3) << 0);
2041 OUT_BCS_BATCH(batch,
2042 va_to_gen7_vc1_condover[pic_param->conditional_overlap_flag] << 29 |
2043 picture_type << 26 |
2046 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 8 |
2048 OUT_BCS_BATCH(batch,
2049 unified_mv_mode << 28 |
2050 pic_param->mv_fields.bits.four_mv_switch << 27 |
2051 pic_param->fast_uvmc_flag << 26 |
2052 ref_field_pic_polarity << 25 |
2053 pic_param->reference_fields.bits.num_reference_pictures << 24 |
2054 pic_param->reference_fields.bits.reference_distance << 20 |
2055 pic_param->reference_fields.bits.reference_distance << 16 | /* FIXME: ??? */
2056 pic_param->mv_fields.bits.extended_dmv_range << 10 |
2057 pic_param->mv_fields.bits.extended_mv_range << 8 |
2058 alt_pquant_edge_mask << 4 |
2059 alt_pquant_config << 2 |
2060 pic_param->pic_quantizer_fields.bits.half_qp << 1 |
2061 pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 0);
2062 OUT_BCS_BATCH(batch,
2063 !!pic_param->bitplane_present.value << 31 |
2064 !pic_param->bitplane_present.flags.bp_forward_mb << 30 |
2065 !pic_param->bitplane_present.flags.bp_mv_type_mb << 29 |
2066 !pic_param->bitplane_present.flags.bp_skip_mb << 28 |
2067 !pic_param->bitplane_present.flags.bp_direct_mb << 27 |
2068 !pic_param->bitplane_present.flags.bp_overflags << 26 |
2069 !pic_param->bitplane_present.flags.bp_ac_pred << 25 |
2070 !pic_param->bitplane_present.flags.bp_field_tx << 24 |
2071 pic_param->mv_fields.bits.mv_table << 20 |
2072 pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
2073 pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
2074 pic_param->transform_fields.bits.frame_level_transform_type << 12 |
2075 pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
2076 pic_param->mb_mode_table << 8 |
2078 pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
2079 pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
2080 pic_param->cbp_table << 0);
2081 ADVANCE_BCS_BATCH(batch);
2085 gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
2086 struct decode_state *decode_state,
2087 struct gen7_mfd_context *gen7_mfd_context)
2089 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2090 VAPictureParameterBufferVC1 *pic_param;
2091 int intensitycomp_single;
2093 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2094 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2096 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2097 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2098 intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
2100 BEGIN_BCS_BATCH(batch, 6);
2101 OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2));
2102 OUT_BCS_BATCH(batch,
2103 0 << 14 | /* FIXME: double ??? */
2105 intensitycomp_single << 10 |
2106 intensitycomp_single << 8 |
2107 0 << 4 | /* FIXME: interlace mode */
2109 OUT_BCS_BATCH(batch,
2110 pic_param->luma_shift << 16 |
2111 pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
2112 OUT_BCS_BATCH(batch, 0);
2113 OUT_BCS_BATCH(batch, 0);
2114 OUT_BCS_BATCH(batch, 0);
2115 ADVANCE_BCS_BATCH(batch);
2119 gen75_mfd_vc1_directmode_state_bplus(VADriverContextP ctx,
2120 struct decode_state *decode_state,
2121 struct gen7_mfd_context *gen7_mfd_context)
2123 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2124 VAPictureParameterBufferVC1 *pic_param;
2125 struct i965_driver_data *i965 = i965_driver_data(ctx);
2126 struct object_surface *obj_surface;
2127 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2129 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2130 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2132 obj_surface = SURFACE(decode_state->current_render_target);
2134 if (obj_surface && obj_surface->private_data) {
2135 dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2138 obj_surface = SURFACE(pic_param->backward_reference_picture);
2140 if (obj_surface && obj_surface->private_data) {
2141 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2144 BEGIN_BCS_BATCH(batch, 7);
2145 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (7 - 2));
2147 if (dmv_write_buffer)
2148 OUT_BCS_RELOC(batch, dmv_write_buffer,
2149 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2152 OUT_BCS_BATCH(batch, 0);
2154 OUT_BCS_BATCH(batch, 0);
2155 OUT_BCS_BATCH(batch, 0);
2157 if (dmv_read_buffer)
2158 OUT_BCS_RELOC(batch, dmv_read_buffer,
2159 I915_GEM_DOMAIN_INSTRUCTION, 0,
2162 OUT_BCS_BATCH(batch, 0);
2163 OUT_BCS_BATCH(batch, 0);
2164 OUT_BCS_BATCH(batch, 0);
2166 ADVANCE_BCS_BATCH(batch);
2170 gen75_mfd_vc1_directmode_state(VADriverContextP ctx,
2171 struct decode_state *decode_state,
2172 struct gen7_mfd_context *gen7_mfd_context)
2174 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2175 VAPictureParameterBufferVC1 *pic_param;
2176 struct i965_driver_data *i965 = i965_driver_data(ctx);
2177 struct object_surface *obj_surface;
2178 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
2180 if (IS_STEPPING_BPLUS(i965)) {
2181 gen75_mfd_vc1_directmode_state_bplus(ctx, decode_state, gen7_mfd_context);
2184 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2185 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2187 obj_surface = SURFACE(decode_state->current_render_target);
2189 if (obj_surface && obj_surface->private_data) {
2190 dmv_write_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2193 obj_surface = SURFACE(pic_param->backward_reference_picture);
2195 if (obj_surface && obj_surface->private_data) {
2196 dmv_read_buffer = ((struct gen7_vc1_surface *)(obj_surface->private_data))->dmv;
2199 BEGIN_BCS_BATCH(batch, 3);
2200 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
2202 if (dmv_write_buffer)
2203 OUT_BCS_RELOC(batch, dmv_write_buffer,
2204 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2207 OUT_BCS_BATCH(batch, 0);
2209 if (dmv_read_buffer)
2210 OUT_BCS_RELOC(batch, dmv_read_buffer,
2211 I915_GEM_DOMAIN_INSTRUCTION, 0,
2214 OUT_BCS_BATCH(batch, 0);
2216 ADVANCE_BCS_BATCH(batch);
2220 gen75_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
2222 int out_slice_data_bit_offset;
2223 int slice_header_size = in_slice_data_bit_offset / 8;
2227 out_slice_data_bit_offset = in_slice_data_bit_offset;
2229 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
2230 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
2235 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
2238 return out_slice_data_bit_offset;
2242 gen75_mfd_vc1_bsd_object(VADriverContextP ctx,
2243 VAPictureParameterBufferVC1 *pic_param,
2244 VASliceParameterBufferVC1 *slice_param,
2245 VASliceParameterBufferVC1 *next_slice_param,
2246 dri_bo *slice_data_bo,
2247 struct gen7_mfd_context *gen7_mfd_context)
2249 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2250 int next_slice_start_vert_pos;
2251 int macroblock_offset;
2252 uint8_t *slice_data = NULL;
2254 dri_bo_map(slice_data_bo, 0);
2255 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
2256 macroblock_offset = gen75_mfd_vc1_get_macroblock_bit_offset(slice_data,
2257 slice_param->macroblock_offset,
2258 pic_param->sequence_fields.bits.profile);
2259 dri_bo_unmap(slice_data_bo);
2261 if (next_slice_param)
2262 next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
2264 next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
2266 BEGIN_BCS_BATCH(batch, 5);
2267 OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (5 - 2));
2268 OUT_BCS_BATCH(batch,
2269 slice_param->slice_data_size - (macroblock_offset >> 3));
2270 OUT_BCS_BATCH(batch,
2271 slice_param->slice_data_offset + (macroblock_offset >> 3));
2272 OUT_BCS_BATCH(batch,
2273 slice_param->slice_vertical_position << 16 |
2274 next_slice_start_vert_pos << 0);
2275 OUT_BCS_BATCH(batch,
2276 (macroblock_offset & 0x7));
2277 ADVANCE_BCS_BATCH(batch);
2281 gen75_mfd_vc1_decode_picture(VADriverContextP ctx,
2282 struct decode_state *decode_state,
2283 struct gen7_mfd_context *gen7_mfd_context)
2285 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2286 VAPictureParameterBufferVC1 *pic_param;
2287 VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
2288 dri_bo *slice_data_bo;
2291 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2292 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
2294 gen75_mfd_vc1_decode_init(ctx, decode_state, gen7_mfd_context);
2295 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
2296 intel_batchbuffer_emit_mi_flush(batch);
2297 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2298 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2299 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2300 gen75_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen7_mfd_context);
2301 gen75_mfd_vc1_pic_state(ctx, decode_state, gen7_mfd_context);
2302 gen75_mfd_vc1_pred_pipe_state(ctx, decode_state, gen7_mfd_context);
2303 gen75_mfd_vc1_directmode_state(ctx, decode_state, gen7_mfd_context);
2305 for (j = 0; j < decode_state->num_slice_params; j++) {
2306 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
2307 slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
2308 slice_data_bo = decode_state->slice_datas[j]->bo;
2309 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen7_mfd_context);
2311 if (j == decode_state->num_slice_params - 1)
2312 next_slice_group_param = NULL;
2314 next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
2316 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
2317 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
2319 if (i < decode_state->slice_params[j]->num_elements - 1)
2320 next_slice_param = slice_param + 1;
2322 next_slice_param = next_slice_group_param;
2324 gen75_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
2329 intel_batchbuffer_end_atomic(batch);
2330 intel_batchbuffer_flush(batch);
2334 gen75_mfd_jpeg_decode_init(VADriverContextP ctx,
2335 struct decode_state *decode_state,
2336 struct gen7_mfd_context *gen7_mfd_context)
2338 struct i965_driver_data *i965 = i965_driver_data(ctx);
2339 struct object_surface *obj_surface;
2340 VAPictureParameterBufferJPEGBaseline *pic_param;
2341 int subsampling = SUBSAMPLE_YUV420;
2343 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2345 if (pic_param->num_components == 1)
2346 subsampling = SUBSAMPLE_YUV400;
2347 else if (pic_param->num_components == 3) {
2348 int h1 = pic_param->components[0].h_sampling_factor;
2349 int h2 = pic_param->components[1].h_sampling_factor;
2350 int h3 = pic_param->components[2].h_sampling_factor;
2351 int v1 = pic_param->components[0].v_sampling_factor;
2352 int v2 = pic_param->components[1].v_sampling_factor;
2353 int v3 = pic_param->components[2].v_sampling_factor;
2355 if (h1 == 2 && h2 == 1 && h3 == 1 &&
2356 v1 == 2 && v2 == 1 && v3 == 1)
2357 subsampling = SUBSAMPLE_YUV420;
2358 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2359 v1 == 1 && v2 == 1 && v3 == 1)
2360 subsampling = SUBSAMPLE_YUV422H;
2361 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2362 v1 == 1 && v2 == 1 && v3 == 1)
2363 subsampling = SUBSAMPLE_YUV444;
2364 else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2365 v1 == 1 && v2 == 1 && v3 == 1)
2366 subsampling = SUBSAMPLE_YUV411;
2367 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2368 v1 == 2 && v2 == 1 && v3 == 1)
2369 subsampling = SUBSAMPLE_YUV422V;
2370 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2371 v1 == 2 && v2 == 2 && v3 == 2)
2372 subsampling = SUBSAMPLE_YUV422H;
2373 else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2374 v1 == 2 && v2 == 1 && v3 == 1)
2375 subsampling = SUBSAMPLE_YUV422V;
2382 /* Current decoded picture */
2383 obj_surface = SURFACE(decode_state->current_render_target);
2384 assert(obj_surface);
2385 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('I','M','C','1'), subsampling);
2387 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
2388 gen7_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
2389 dri_bo_reference(gen7_mfd_context->pre_deblocking_output.bo);
2390 gen7_mfd_context->pre_deblocking_output.valid = 1;
2392 gen7_mfd_context->post_deblocking_output.bo = NULL;
2393 gen7_mfd_context->post_deblocking_output.valid = 0;
2395 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2396 gen7_mfd_context->intra_row_store_scratch_buffer.valid = 0;
2398 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2399 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
2401 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2402 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 0;
2404 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2405 gen7_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
2407 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
2408 gen7_mfd_context->bitplane_read_buffer.valid = 0;
2411 static const int va_to_gen7_jpeg_rotation[4] = {
2412 GEN7_JPEG_ROTATION_0,
2413 GEN7_JPEG_ROTATION_90,
2414 GEN7_JPEG_ROTATION_180,
2415 GEN7_JPEG_ROTATION_270
2419 gen75_mfd_jpeg_pic_state(VADriverContextP ctx,
2420 struct decode_state *decode_state,
2421 struct gen7_mfd_context *gen7_mfd_context)
2423 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2424 VAPictureParameterBufferJPEGBaseline *pic_param;
2425 int chroma_type = GEN7_YUV420;
2426 int frame_width_in_blks;
2427 int frame_height_in_blks;
2429 assert(decode_state->pic_param && decode_state->pic_param->buffer);
2430 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2432 if (pic_param->num_components == 1)
2433 chroma_type = GEN7_YUV400;
2434 else if (pic_param->num_components == 3) {
2435 int h1 = pic_param->components[0].h_sampling_factor;
2436 int h2 = pic_param->components[1].h_sampling_factor;
2437 int h3 = pic_param->components[2].h_sampling_factor;
2438 int v1 = pic_param->components[0].v_sampling_factor;
2439 int v2 = pic_param->components[1].v_sampling_factor;
2440 int v3 = pic_param->components[2].v_sampling_factor;
2442 if (h1 == 2 && h2 == 1 && h3 == 1 &&
2443 v1 == 2 && v2 == 1 && v3 == 1)
2444 chroma_type = GEN7_YUV420;
2445 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2446 v1 == 1 && v2 == 1 && v3 == 1)
2447 chroma_type = GEN7_YUV422H_2Y;
2448 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2449 v1 == 1 && v2 == 1 && v3 == 1)
2450 chroma_type = GEN7_YUV444;
2451 else if (h1 == 4 && h2 == 1 && h3 == 1 &&
2452 v1 == 1 && v2 == 1 && v3 == 1)
2453 chroma_type = GEN7_YUV411;
2454 else if (h1 == 1 && h2 == 1 && h3 == 1 &&
2455 v1 == 2 && v2 == 1 && v3 == 1)
2456 chroma_type = GEN7_YUV422V_2Y;
2457 else if (h1 == 2 && h2 == 1 && h3 == 1 &&
2458 v1 == 2 && v2 == 2 && v3 == 2)
2459 chroma_type = GEN7_YUV422H_4Y;
2460 else if (h2 == 2 && h2 == 2 && h3 == 2 &&
2461 v1 == 2 && v2 == 1 && v3 == 1)
2462 chroma_type = GEN7_YUV422V_4Y;
2467 if (chroma_type == GEN7_YUV400 ||
2468 chroma_type == GEN7_YUV444 ||
2469 chroma_type == GEN7_YUV422V_2Y) {
2470 frame_width_in_blks = ((pic_param->picture_width + 7) / 8);
2471 frame_height_in_blks = ((pic_param->picture_height + 7) / 8);
2472 } else if (chroma_type == GEN7_YUV411) {
2473 frame_width_in_blks = ((pic_param->picture_width + 31) / 32) * 4;
2474 frame_height_in_blks = ((pic_param->picture_height + 31) / 32) * 4;
2476 frame_width_in_blks = ((pic_param->picture_width + 15) / 16) * 2;
2477 frame_height_in_blks = ((pic_param->picture_height + 15) / 16) * 2;
2480 BEGIN_BCS_BATCH(batch, 3);
2481 OUT_BCS_BATCH(batch, MFX_JPEG_PIC_STATE | (3 - 2));
2482 OUT_BCS_BATCH(batch,
2483 (va_to_gen7_jpeg_rotation[0] << 4) | /* without rotation */
2484 (chroma_type << 0));
2485 OUT_BCS_BATCH(batch,
2486 ((frame_height_in_blks - 1) << 16) | /* FrameHeightInBlks */
2487 ((frame_width_in_blks - 1) << 0)); /* FrameWidthInBlks */
2488 ADVANCE_BCS_BATCH(batch);
2491 static const int va_to_gen7_jpeg_hufftable[2] = {
2497 gen75_mfd_jpeg_huff_table_state(VADriverContextP ctx,
2498 struct decode_state *decode_state,
2499 struct gen7_mfd_context *gen7_mfd_context,
2502 VAHuffmanTableBufferJPEGBaseline *huffman_table;
2503 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2506 if (!decode_state->huffman_table || !decode_state->huffman_table->buffer)
2509 huffman_table = (VAHuffmanTableBufferJPEGBaseline *)decode_state->huffman_table->buffer;
2511 for (index = 0; index < num_tables; index++) {
2512 int id = va_to_gen7_jpeg_hufftable[index];
2513 if (!huffman_table->load_huffman_table[index])
2515 BEGIN_BCS_BATCH(batch, 53);
2516 OUT_BCS_BATCH(batch, MFX_JPEG_HUFF_TABLE_STATE | (53 - 2));
2517 OUT_BCS_BATCH(batch, id);
2518 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_dc_codes, 12);
2519 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].dc_values, 12);
2520 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].num_ac_codes, 16);
2521 intel_batchbuffer_data(batch, huffman_table->huffman_table[index].ac_values, 164);
2522 ADVANCE_BCS_BATCH(batch);
2526 static const int va_to_gen7_jpeg_qm[5] = {
2528 MFX_QM_JPEG_LUMA_Y_QUANTIZER_MATRIX,
2529 MFX_QM_JPEG_CHROMA_CB_QUANTIZER_MATRIX,
2530 MFX_QM_JPEG_CHROMA_CR_QUANTIZER_MATRIX,
2531 MFX_QM_JPEG_ALPHA_QUANTIZER_MATRIX
2535 gen75_mfd_jpeg_qm_state(VADriverContextP ctx,
2536 struct decode_state *decode_state,
2537 struct gen7_mfd_context *gen7_mfd_context)
2539 VAPictureParameterBufferJPEGBaseline *pic_param;
2540 VAIQMatrixBufferJPEGBaseline *iq_matrix;
2543 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
2546 iq_matrix = (VAIQMatrixBufferJPEGBaseline *)decode_state->iq_matrix->buffer;
2547 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
2549 assert(pic_param->num_components <= 3);
2551 for (index = 0; index < pic_param->num_components; index++) {
2552 int qm_type = va_to_gen7_jpeg_qm[pic_param->components[index].component_id - pic_param->components[0].component_id + 1];
2553 unsigned char *qm = iq_matrix->quantiser_table[pic_param->components[index].quantiser_table_selector];
2554 unsigned char raster_qm[64];
2557 if (!iq_matrix->load_quantiser_table[pic_param->components[index].quantiser_table_selector])
2560 for (j = 0; j < 64; j++)
2561 raster_qm[zigzag_direct[j]] = qm[j];
2563 gen75_mfd_qm_state(ctx, qm_type, raster_qm, 64, gen7_mfd_context);
2568 gen75_mfd_jpeg_bsd_object(VADriverContextP ctx,
2569 VAPictureParameterBufferJPEGBaseline *pic_param,
2570 VASliceParameterBufferJPEGBaseline *slice_param,
2571 VASliceParameterBufferJPEGBaseline *next_slice_param,
2572 dri_bo *slice_data_bo,
2573 struct gen7_mfd_context *gen7_mfd_context)
2575 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2576 int scan_component_mask = 0;
2579 assert(slice_param->num_components > 0);
2580 assert(slice_param->num_components < 4);
2581 assert(slice_param->num_components <= pic_param->num_components);
2583 for (i = 0; i < slice_param->num_components; i++) {
2584 switch (slice_param->components[i].component_selector - pic_param->components[0].component_id + 1) {
2586 scan_component_mask |= (1 << 0);
2589 scan_component_mask |= (1 << 1);
2592 scan_component_mask |= (1 << 2);
2600 BEGIN_BCS_BATCH(batch, 6);
2601 OUT_BCS_BATCH(batch, MFD_JPEG_BSD_OBJECT | (6 - 2));
2602 OUT_BCS_BATCH(batch,
2603 slice_param->slice_data_size);
2604 OUT_BCS_BATCH(batch,
2605 slice_param->slice_data_offset);
2606 OUT_BCS_BATCH(batch,
2607 slice_param->slice_horizontal_position << 16 |
2608 slice_param->slice_vertical_position << 0);
2609 OUT_BCS_BATCH(batch,
2610 ((slice_param->num_components != 1) << 30) | /* interleaved */
2611 (scan_component_mask << 27) | /* scan components */
2612 (0 << 26) | /* disable interrupt allowed */
2613 (slice_param->num_mcus << 0)); /* MCU count */
2614 OUT_BCS_BATCH(batch,
2615 (slice_param->restart_interval << 0)); /* RestartInterval */
2616 ADVANCE_BCS_BATCH(batch);
2619 /* Workaround for JPEG decoding on Ivybridge */
2622 i965_DestroySurfaces(VADriverContextP ctx,
2623 VASurfaceID *surface_list,
2626 i965_CreateSurfaces(VADriverContextP ctx,
2631 VASurfaceID *surfaces);
2636 unsigned char data[32];
2638 int data_bit_offset;
2640 } gen7_jpeg_wa_clip = {
2644 0x65, 0xb8, 0x40, 0x32, 0x13, 0xfd, 0x06, 0x6c,
2645 0xfc, 0x0a, 0x50, 0x71, 0x5c, 0x00
2653 gen75_jpeg_wa_init(VADriverContextP ctx,
2654 struct gen7_mfd_context *gen7_mfd_context)
2656 struct i965_driver_data *i965 = i965_driver_data(ctx);
2658 struct object_surface *obj_surface;
2660 if (gen7_mfd_context->jpeg_wa_surface_id != VA_INVALID_SURFACE)
2661 i965_DestroySurfaces(ctx,
2662 &gen7_mfd_context->jpeg_wa_surface_id,
2665 status = i965_CreateSurfaces(ctx,
2666 gen7_jpeg_wa_clip.width,
2667 gen7_jpeg_wa_clip.height,
2668 VA_RT_FORMAT_YUV420,
2670 &gen7_mfd_context->jpeg_wa_surface_id);
2671 assert(status == VA_STATUS_SUCCESS);
2673 obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2674 assert(obj_surface);
2675 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
2677 if (!gen7_mfd_context->jpeg_wa_slice_data_bo) {
2678 gen7_mfd_context->jpeg_wa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
2682 dri_bo_subdata(gen7_mfd_context->jpeg_wa_slice_data_bo,
2684 gen7_jpeg_wa_clip.data_size,
2685 gen7_jpeg_wa_clip.data);
2690 gen75_jpeg_wa_pipe_mode_select(VADriverContextP ctx,
2691 struct gen7_mfd_context *gen7_mfd_context)
2693 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2695 BEGIN_BCS_BATCH(batch, 5);
2696 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
2697 OUT_BCS_BATCH(batch,
2698 (MFX_LONG_MODE << 17) | /* Currently only support long format */
2699 (MFD_MODE_VLD << 15) | /* VLD mode */
2700 (0 << 10) | /* disable Stream-Out */
2701 (0 << 9) | /* Post Deblocking Output */
2702 (1 << 8) | /* Pre Deblocking Output */
2703 (0 << 5) | /* not in stitch mode */
2704 (MFX_CODEC_DECODE << 4) | /* decoding mode */
2705 (MFX_FORMAT_AVC << 0));
2706 OUT_BCS_BATCH(batch,
2707 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
2708 (0 << 3) | /* terminate if AVC mbdata error occurs */
2709 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
2712 OUT_BCS_BATCH(batch, 0); /* pic status/error report id */
2713 OUT_BCS_BATCH(batch, 0); /* reserved */
2714 ADVANCE_BCS_BATCH(batch);
2718 gen75_jpeg_wa_surface_state(VADriverContextP ctx,
2719 struct gen7_mfd_context *gen7_mfd_context)
2721 struct i965_driver_data *i965 = i965_driver_data(ctx);
2722 struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2723 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2725 BEGIN_BCS_BATCH(batch, 6);
2726 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
2727 OUT_BCS_BATCH(batch, 0);
2728 OUT_BCS_BATCH(batch,
2729 ((obj_surface->orig_width - 1) << 18) |
2730 ((obj_surface->orig_height - 1) << 4));
2731 OUT_BCS_BATCH(batch,
2732 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
2733 (1 << 27) | /* interleave chroma, set to 0 for JPEG */
2734 (0 << 22) | /* surface object control state, ignored */
2735 ((obj_surface->width - 1) << 3) | /* pitch */
2736 (0 << 2) | /* must be 0 */
2737 (1 << 1) | /* must be tiled */
2738 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
2739 OUT_BCS_BATCH(batch,
2740 (0 << 16) | /* X offset for U(Cb), must be 0 */
2741 (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
2742 OUT_BCS_BATCH(batch,
2743 (0 << 16) | /* X offset for V(Cr), must be 0 */
2744 (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec, non-zoro for JPEG */
2745 ADVANCE_BCS_BATCH(batch);
2749 gen75_jpeg_wa_pipe_buf_addr_state_bplus(VADriverContextP ctx,
2750 struct gen7_mfd_context *gen7_mfd_context)
2752 struct i965_driver_data *i965 = i965_driver_data(ctx);
2753 struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2754 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2758 intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2763 BEGIN_BCS_BATCH(batch, 61);
2764 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
2765 OUT_BCS_RELOC(batch,
2767 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2769 OUT_BCS_BATCH(batch, 0);
2770 OUT_BCS_BATCH(batch, 0);
2773 OUT_BCS_BATCH(batch, 0); /* post deblocking */
2774 OUT_BCS_BATCH(batch, 0);
2775 OUT_BCS_BATCH(batch, 0);
2777 /* uncompressed-video & stream out 7-12 */
2778 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2779 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2780 OUT_BCS_BATCH(batch, 0);
2781 OUT_BCS_BATCH(batch, 0);
2782 OUT_BCS_BATCH(batch, 0);
2783 OUT_BCS_BATCH(batch, 0);
2785 /* the DW 13-15 is for intra row store scratch */
2786 OUT_BCS_RELOC(batch,
2788 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2790 OUT_BCS_BATCH(batch, 0);
2791 OUT_BCS_BATCH(batch, 0);
2793 /* the DW 16-18 is for deblocking filter */
2794 OUT_BCS_BATCH(batch, 0);
2795 OUT_BCS_BATCH(batch, 0);
2796 OUT_BCS_BATCH(batch, 0);
2799 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2800 OUT_BCS_BATCH(batch, 0);
2801 OUT_BCS_BATCH(batch, 0);
2803 OUT_BCS_BATCH(batch, 0);
2805 /* the DW52-54 is for mb status address */
2806 OUT_BCS_BATCH(batch, 0);
2807 OUT_BCS_BATCH(batch, 0);
2808 OUT_BCS_BATCH(batch, 0);
2809 /* the DW56-60 is for ILDB & second ILDB address */
2810 OUT_BCS_BATCH(batch, 0);
2811 OUT_BCS_BATCH(batch, 0);
2812 OUT_BCS_BATCH(batch, 0);
2813 OUT_BCS_BATCH(batch, 0);
2814 OUT_BCS_BATCH(batch, 0);
2815 OUT_BCS_BATCH(batch, 0);
2817 ADVANCE_BCS_BATCH(batch);
2819 dri_bo_unreference(intra_bo);
2822 gen75_jpeg_wa_pipe_buf_addr_state(VADriverContextP ctx,
2823 struct gen7_mfd_context *gen7_mfd_context)
2825 struct i965_driver_data *i965 = i965_driver_data(ctx);
2826 struct object_surface *obj_surface = SURFACE(gen7_mfd_context->jpeg_wa_surface_id);
2827 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2831 if (IS_STEPPING_BPLUS(i965)) {
2832 gen75_jpeg_wa_pipe_buf_addr_state_bplus(ctx, gen7_mfd_context);
2835 intra_bo = dri_bo_alloc(i965->intel.bufmgr,
2840 BEGIN_BCS_BATCH(batch, 25);
2841 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
2842 OUT_BCS_RELOC(batch,
2844 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2847 OUT_BCS_BATCH(batch, 0); /* post deblocking */
2849 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2850 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
2852 OUT_BCS_RELOC(batch,
2854 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2857 OUT_BCS_BATCH(batch, 0);
2860 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
2861 OUT_BCS_BATCH(batch, 0);
2864 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
2865 OUT_BCS_BATCH(batch, 0);
2866 ADVANCE_BCS_BATCH(batch);
2868 dri_bo_unreference(intra_bo);
2872 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
2873 struct gen7_mfd_context *gen7_mfd_context)
2875 struct i965_driver_data *i965 = i965_driver_data(ctx);
2876 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2877 dri_bo *bsd_mpc_bo, *mpr_bo;
2879 bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2880 "bsd mpc row store",
2881 11520, /* 1.5 * 120 * 64 */
2884 mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2886 7680, /* 1. 0 * 120 * 64 */
2889 BEGIN_BCS_BATCH(batch, 10);
2890 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
2892 OUT_BCS_RELOC(batch,
2894 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2897 OUT_BCS_BATCH(batch, 0);
2898 OUT_BCS_BATCH(batch, 0);
2900 OUT_BCS_RELOC(batch,
2902 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2904 OUT_BCS_BATCH(batch, 0);
2905 OUT_BCS_BATCH(batch, 0);
2907 OUT_BCS_BATCH(batch, 0);
2908 OUT_BCS_BATCH(batch, 0);
2909 OUT_BCS_BATCH(batch, 0);
2911 ADVANCE_BCS_BATCH(batch);
2913 dri_bo_unreference(bsd_mpc_bo);
2914 dri_bo_unreference(mpr_bo);
2918 gen75_jpeg_wa_bsp_buf_base_addr_state(VADriverContextP ctx,
2919 struct gen7_mfd_context *gen7_mfd_context)
2921 struct i965_driver_data *i965 = i965_driver_data(ctx);
2922 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2923 dri_bo *bsd_mpc_bo, *mpr_bo;
2925 if (IS_STEPPING_BPLUS(i965)) {
2926 gen75_jpeg_wa_bsp_buf_base_addr_state_bplus(ctx, gen7_mfd_context);
2930 bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
2931 "bsd mpc row store",
2932 11520, /* 1.5 * 120 * 64 */
2935 mpr_bo = dri_bo_alloc(i965->intel.bufmgr,
2937 7680, /* 1. 0 * 120 * 64 */
2940 BEGIN_BCS_BATCH(batch, 4);
2941 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
2943 OUT_BCS_RELOC(batch,
2945 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2948 OUT_BCS_RELOC(batch,
2950 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
2952 OUT_BCS_BATCH(batch, 0);
2954 ADVANCE_BCS_BATCH(batch);
2956 dri_bo_unreference(bsd_mpc_bo);
2957 dri_bo_unreference(mpr_bo);
2961 gen75_jpeg_wa_avc_qm_state(VADriverContextP ctx,
2962 struct gen7_mfd_context *gen7_mfd_context)
2968 gen75_jpeg_wa_avc_img_state(VADriverContextP ctx,
2969 struct gen7_mfd_context *gen7_mfd_context)
2971 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
2973 int mbaff_frame_flag = 0;
2974 unsigned int width_in_mbs = 1, height_in_mbs = 1;
2976 BEGIN_BCS_BATCH(batch, 16);
2977 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
2978 OUT_BCS_BATCH(batch,
2979 width_in_mbs * height_in_mbs);
2980 OUT_BCS_BATCH(batch,
2981 ((height_in_mbs - 1) << 16) |
2982 ((width_in_mbs - 1) << 0));
2983 OUT_BCS_BATCH(batch,
2988 (0 << 12) | /* differ from GEN6 */
2991 OUT_BCS_BATCH(batch,
2992 (1 << 10) | /* 4:2:0 */
2993 (1 << 7) | /* CABAC */
2999 (mbaff_frame_flag << 1) |
3001 OUT_BCS_BATCH(batch, 0);
3002 OUT_BCS_BATCH(batch, 0);
3003 OUT_BCS_BATCH(batch, 0);
3004 OUT_BCS_BATCH(batch, 0);
3005 OUT_BCS_BATCH(batch, 0);
3006 OUT_BCS_BATCH(batch, 0);
3007 OUT_BCS_BATCH(batch, 0);
3008 OUT_BCS_BATCH(batch, 0);
3009 OUT_BCS_BATCH(batch, 0);
3010 OUT_BCS_BATCH(batch, 0);
3011 OUT_BCS_BATCH(batch, 0);
3012 ADVANCE_BCS_BATCH(batch);
3016 gen75_jpeg_wa_avc_directmode_state_bplus(VADriverContextP ctx,
3017 struct gen7_mfd_context *gen7_mfd_context)
3019 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3022 BEGIN_BCS_BATCH(batch, 71);
3023 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
3025 /* reference surfaces 0..15 */
3026 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3027 OUT_BCS_BATCH(batch, 0); /* top */
3028 OUT_BCS_BATCH(batch, 0); /* bottom */
3031 OUT_BCS_BATCH(batch, 0);
3033 /* the current decoding frame/field */
3034 OUT_BCS_BATCH(batch, 0); /* top */
3035 OUT_BCS_BATCH(batch, 0);
3036 OUT_BCS_BATCH(batch, 0);
3039 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3040 OUT_BCS_BATCH(batch, 0);
3041 OUT_BCS_BATCH(batch, 0);
3044 OUT_BCS_BATCH(batch, 0);
3045 OUT_BCS_BATCH(batch, 0);
3047 ADVANCE_BCS_BATCH(batch);
3051 gen75_jpeg_wa_avc_directmode_state(VADriverContextP ctx,
3052 struct gen7_mfd_context *gen7_mfd_context)
3054 struct i965_driver_data *i965 = i965_driver_data(ctx);
3055 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3058 if (IS_STEPPING_BPLUS(i965)) {
3059 gen75_jpeg_wa_avc_directmode_state_bplus(ctx, gen7_mfd_context);
3063 BEGIN_BCS_BATCH(batch, 69);
3064 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
3066 /* reference surfaces 0..15 */
3067 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3068 OUT_BCS_BATCH(batch, 0); /* top */
3069 OUT_BCS_BATCH(batch, 0); /* bottom */
3072 /* the current decoding frame/field */
3073 OUT_BCS_BATCH(batch, 0); /* top */
3074 OUT_BCS_BATCH(batch, 0); /* bottom */
3077 for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
3078 OUT_BCS_BATCH(batch, 0);
3079 OUT_BCS_BATCH(batch, 0);
3082 OUT_BCS_BATCH(batch, 0);
3083 OUT_BCS_BATCH(batch, 0);
3085 ADVANCE_BCS_BATCH(batch);
3089 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
3090 struct gen7_mfd_context *gen7_mfd_context)
3092 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3094 BEGIN_BCS_BATCH(batch, 11);
3095 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3096 OUT_BCS_RELOC(batch,
3097 gen7_mfd_context->jpeg_wa_slice_data_bo,
3098 I915_GEM_DOMAIN_INSTRUCTION, 0,
3100 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3101 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3102 OUT_BCS_BATCH(batch, 0);
3103 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3104 OUT_BCS_BATCH(batch, 0);
3105 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3106 OUT_BCS_BATCH(batch, 0);
3107 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3108 OUT_BCS_BATCH(batch, 0);
3109 ADVANCE_BCS_BATCH(batch);
3113 gen75_jpeg_wa_ind_obj_base_addr_state(VADriverContextP ctx,
3114 struct gen7_mfd_context *gen7_mfd_context)
3116 struct i965_driver_data *i965 = i965_driver_data(ctx);
3117 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3119 if (IS_STEPPING_BPLUS(i965)) {
3120 gen75_jpeg_wa_ind_obj_base_addr_state_bplus(ctx, gen7_mfd_context);
3123 BEGIN_BCS_BATCH(batch, 11);
3124 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
3125 OUT_BCS_RELOC(batch,
3126 gen7_mfd_context->jpeg_wa_slice_data_bo,
3127 I915_GEM_DOMAIN_INSTRUCTION, 0,
3129 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
3130 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3131 OUT_BCS_BATCH(batch, 0);
3132 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3133 OUT_BCS_BATCH(batch, 0);
3134 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3135 OUT_BCS_BATCH(batch, 0);
3136 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
3137 OUT_BCS_BATCH(batch, 0);
3138 ADVANCE_BCS_BATCH(batch);
3142 gen75_jpeg_wa_avc_bsd_object(VADriverContextP ctx,
3143 struct gen7_mfd_context *gen7_mfd_context)
3145 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3147 /* the input bitsteam format on GEN7 differs from GEN6 */
3148 BEGIN_BCS_BATCH(batch, 6);
3149 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
3150 OUT_BCS_BATCH(batch, gen7_jpeg_wa_clip.data_size);
3151 OUT_BCS_BATCH(batch, 0);
3152 OUT_BCS_BATCH(batch,
3158 OUT_BCS_BATCH(batch,
3159 ((gen7_jpeg_wa_clip.data_bit_offset >> 3) << 16) |
3162 (1 << 3) | /* LastSlice Flag */
3163 (gen7_jpeg_wa_clip.data_bit_offset & 0x7));
3164 OUT_BCS_BATCH(batch, 0);
3165 ADVANCE_BCS_BATCH(batch);
3169 gen75_jpeg_wa_avc_slice_state(VADriverContextP ctx,
3170 struct gen7_mfd_context *gen7_mfd_context)
3172 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3173 int slice_hor_pos = 0, slice_ver_pos = 0, next_slice_hor_pos = 0, next_slice_ver_pos = 1;
3174 int num_ref_idx_l0 = 0, num_ref_idx_l1 = 0;
3175 int first_mb_in_slice = 0;
3176 int slice_type = SLICE_TYPE_I;
3178 BEGIN_BCS_BATCH(batch, 11);
3179 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
3180 OUT_BCS_BATCH(batch, slice_type);
3181 OUT_BCS_BATCH(batch,
3182 (num_ref_idx_l1 << 24) |
3183 (num_ref_idx_l0 << 16) |
3186 OUT_BCS_BATCH(batch,
3188 (1 << 27) | /* disable Deblocking */
3190 (gen7_jpeg_wa_clip.qp << 16) |
3193 OUT_BCS_BATCH(batch,
3194 (slice_ver_pos << 24) |
3195 (slice_hor_pos << 16) |
3196 (first_mb_in_slice << 0));
3197 OUT_BCS_BATCH(batch,
3198 (next_slice_ver_pos << 16) |
3199 (next_slice_hor_pos << 0));
3200 OUT_BCS_BATCH(batch, (1 << 19)); /* last slice flag */
3201 OUT_BCS_BATCH(batch, 0);
3202 OUT_BCS_BATCH(batch, 0);
3203 OUT_BCS_BATCH(batch, 0);
3204 OUT_BCS_BATCH(batch, 0);
3205 ADVANCE_BCS_BATCH(batch);
3209 gen75_mfd_jpeg_wa(VADriverContextP ctx,
3210 struct gen7_mfd_context *gen7_mfd_context)
3212 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3213 gen75_jpeg_wa_init(ctx, gen7_mfd_context);
3214 intel_batchbuffer_emit_mi_flush(batch);
3215 gen75_jpeg_wa_pipe_mode_select(ctx, gen7_mfd_context);
3216 gen75_jpeg_wa_surface_state(ctx, gen7_mfd_context);
3217 gen75_jpeg_wa_pipe_buf_addr_state(ctx, gen7_mfd_context);
3218 gen75_jpeg_wa_bsp_buf_base_addr_state(ctx, gen7_mfd_context);
3219 gen75_jpeg_wa_avc_qm_state(ctx, gen7_mfd_context);
3220 gen75_jpeg_wa_avc_img_state(ctx, gen7_mfd_context);
3221 gen75_jpeg_wa_ind_obj_base_addr_state(ctx, gen7_mfd_context);
3223 gen75_jpeg_wa_avc_directmode_state(ctx, gen7_mfd_context);
3224 gen75_jpeg_wa_avc_slice_state(ctx, gen7_mfd_context);
3225 gen75_jpeg_wa_avc_bsd_object(ctx, gen7_mfd_context);
3229 gen75_mfd_jpeg_decode_picture(VADriverContextP ctx,
3230 struct decode_state *decode_state,
3231 struct gen7_mfd_context *gen7_mfd_context)
3233 struct intel_batchbuffer *batch = gen7_mfd_context->base.batch;
3234 VAPictureParameterBufferJPEGBaseline *pic_param;
3235 VASliceParameterBufferJPEGBaseline *slice_param, *next_slice_param, *next_slice_group_param;
3236 dri_bo *slice_data_bo;
3237 int i, j, max_selector = 0;
3239 assert(decode_state->pic_param && decode_state->pic_param->buffer);
3240 pic_param = (VAPictureParameterBufferJPEGBaseline *)decode_state->pic_param->buffer;
3242 /* Currently only support Baseline DCT */
3243 gen75_mfd_jpeg_decode_init(ctx, decode_state, gen7_mfd_context);
3244 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
3245 gen75_mfd_jpeg_wa(ctx, gen7_mfd_context);
3246 intel_batchbuffer_emit_mi_flush(batch);
3247 gen75_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3248 gen75_mfd_surface_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3249 gen75_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_JPEG, gen7_mfd_context);
3250 gen75_mfd_jpeg_pic_state(ctx, decode_state, gen7_mfd_context);
3251 gen75_mfd_jpeg_qm_state(ctx, decode_state, gen7_mfd_context);
3253 for (j = 0; j < decode_state->num_slice_params; j++) {
3254 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3255 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3256 slice_data_bo = decode_state->slice_datas[j]->bo;
3257 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3259 if (j == decode_state->num_slice_params - 1)
3260 next_slice_group_param = NULL;
3262 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3264 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3267 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3269 if (i < decode_state->slice_params[j]->num_elements - 1)
3270 next_slice_param = slice_param + 1;
3272 next_slice_param = next_slice_group_param;
3274 for (component = 0; component < slice_param->num_components; component++) {
3275 if (max_selector < slice_param->components[component].dc_table_selector)
3276 max_selector = slice_param->components[component].dc_table_selector;
3278 if (max_selector < slice_param->components[component].ac_table_selector)
3279 max_selector = slice_param->components[component].ac_table_selector;
3286 assert(max_selector < 2);
3287 gen75_mfd_jpeg_huff_table_state(ctx, decode_state, gen7_mfd_context, max_selector + 1);
3289 for (j = 0; j < decode_state->num_slice_params; j++) {
3290 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
3291 slice_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j]->buffer;
3292 slice_data_bo = decode_state->slice_datas[j]->bo;
3293 gen75_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_JPEG, gen7_mfd_context);
3295 if (j == decode_state->num_slice_params - 1)
3296 next_slice_group_param = NULL;
3298 next_slice_group_param = (VASliceParameterBufferJPEGBaseline *)decode_state->slice_params[j + 1]->buffer;
3300 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
3301 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
3303 if (i < decode_state->slice_params[j]->num_elements - 1)
3304 next_slice_param = slice_param + 1;
3306 next_slice_param = next_slice_group_param;
3308 gen75_mfd_jpeg_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen7_mfd_context);
3313 intel_batchbuffer_end_atomic(batch);
3314 intel_batchbuffer_flush(batch);
3318 gen75_mfd_decode_picture(VADriverContextP ctx,
3320 union codec_state *codec_state,
3321 struct hw_context *hw_context)
3324 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3325 struct decode_state *decode_state = &codec_state->decode;
3327 assert(gen7_mfd_context);
3329 gen7_mfd_context->wa_mpeg2_slice_vertical_position = -1;
3332 case VAProfileMPEG2Simple:
3333 case VAProfileMPEG2Main:
3334 gen75_mfd_mpeg2_decode_picture(ctx, decode_state, gen7_mfd_context);
3337 case VAProfileH264Baseline:
3338 case VAProfileH264Main:
3339 case VAProfileH264High:
3340 gen75_mfd_avc_decode_picture(ctx, decode_state, gen7_mfd_context);
3343 case VAProfileVC1Simple:
3344 case VAProfileVC1Main:
3345 case VAProfileVC1Advanced:
3346 gen75_mfd_vc1_decode_picture(ctx, decode_state, gen7_mfd_context);
3349 case VAProfileJPEGBaseline:
3350 gen75_mfd_jpeg_decode_picture(ctx, decode_state, gen7_mfd_context);
3360 gen75_mfd_context_destroy(void *hw_context)
3362 struct gen7_mfd_context *gen7_mfd_context = (struct gen7_mfd_context *)hw_context;
3364 dri_bo_unreference(gen7_mfd_context->post_deblocking_output.bo);
3365 gen7_mfd_context->post_deblocking_output.bo = NULL;
3367 dri_bo_unreference(gen7_mfd_context->pre_deblocking_output.bo);
3368 gen7_mfd_context->pre_deblocking_output.bo = NULL;
3370 dri_bo_unreference(gen7_mfd_context->intra_row_store_scratch_buffer.bo);
3371 gen7_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
3373 dri_bo_unreference(gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
3374 gen7_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
3376 dri_bo_unreference(gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
3377 gen7_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
3379 dri_bo_unreference(gen7_mfd_context->mpr_row_store_scratch_buffer.bo);
3380 gen7_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
3382 dri_bo_unreference(gen7_mfd_context->bitplane_read_buffer.bo);
3383 gen7_mfd_context->bitplane_read_buffer.bo = NULL;
3385 dri_bo_unreference(gen7_mfd_context->jpeg_wa_slice_data_bo);
3387 intel_batchbuffer_free(gen7_mfd_context->base.batch);
3388 free(gen7_mfd_context);
3391 static void gen75_mfd_mpeg2_context_init(VADriverContextP ctx,
3392 struct gen7_mfd_context *gen7_mfd_context)
3394 gen7_mfd_context->iq_matrix.mpeg2.load_intra_quantiser_matrix = -1;
3395 gen7_mfd_context->iq_matrix.mpeg2.load_non_intra_quantiser_matrix = -1;
3396 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_intra_quantiser_matrix = -1;
3397 gen7_mfd_context->iq_matrix.mpeg2.load_chroma_non_intra_quantiser_matrix = -1;
3401 gen75_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
3403 struct intel_driver_data *intel = intel_driver_data(ctx);
3404 struct gen7_mfd_context *gen7_mfd_context = calloc(1, sizeof(struct gen7_mfd_context));
3407 gen7_mfd_context->base.destroy = gen75_mfd_context_destroy;
3408 gen7_mfd_context->base.run = gen75_mfd_decode_picture;
3409 gen7_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
3411 for (i = 0; i < ARRAY_ELEMS(gen7_mfd_context->reference_surface); i++) {
3412 gen7_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
3413 gen7_mfd_context->reference_surface[i].frame_store_id = -1;
3416 gen7_mfd_context->jpeg_wa_surface_id = VA_INVALID_SURFACE;
3418 switch (obj_config->profile) {
3419 case VAProfileMPEG2Simple:
3420 case VAProfileMPEG2Main:
3421 gen75_mfd_mpeg2_context_init(ctx, gen7_mfd_context);
3424 case VAProfileH264Baseline:
3425 case VAProfileH264Main:
3426 case VAProfileH264High:
3427 gen75_mfd_avc_context_init(ctx, gen7_mfd_context);
3432 return (struct hw_context *)gen7_mfd_context;