2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhao Yakui <yakui.zhao@intel.com>
26 * Xiang Haihao <haihao.xiang@intel.com>
36 #include "intel_batchbuffer.h"
37 #include "i965_defines.h"
38 #include "i965_structs.h"
39 #include "i965_drv_video.h"
40 #include "i965_encoder.h"
41 #include "i965_encoder_utils.h"
44 #include "intel_media.h"
46 #define MFC_SOFTWARE_HASWELL 1
49 #define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
51 static const uint32_t gen75_mfc_batchbuffer_avc_intra[][4] = {
52 #include "shaders/utils/mfc_batchbuffer_avc_intra.g7b"
55 static const uint32_t gen75_mfc_batchbuffer_avc_inter[][4] = {
56 #include "shaders/utils/mfc_batchbuffer_avc_inter.g7b"
59 static struct i965_kernel gen75_mfc_kernels[] = {
61 "MFC AVC INTRA BATCHBUFFER ",
62 MFC_BATCHBUFFER_AVC_INTRA,
63 gen75_mfc_batchbuffer_avc_intra,
64 sizeof(gen75_mfc_batchbuffer_avc_intra),
69 "MFC AVC INTER BATCHBUFFER ",
70 MFC_BATCHBUFFER_AVC_INTER,
71 gen75_mfc_batchbuffer_avc_inter,
72 sizeof(gen75_mfc_batchbuffer_avc_inter),
77 #define INTER_MODE_MASK 0x03
78 #define INTER_8X8 0x03
79 #define INTER_16X8 0x01
80 #define INTER_8X16 0x02
81 #define SUBMB_SHAPE_MASK 0x00FF00
83 #define INTER_MV8 (4 << 20)
84 #define INTER_MV32 (6 << 20)
88 gen75_mfc_pipe_mode_select(VADriverContextP ctx,
90 struct intel_encoder_context *encoder_context)
92 struct intel_batchbuffer *batch = encoder_context->base.batch;
93 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
95 assert(standard_select == MFX_FORMAT_MPEG2 ||
96 standard_select == MFX_FORMAT_AVC);
98 BEGIN_BCS_BATCH(batch, 5);
100 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
102 (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
103 (MFD_MODE_VLD << 15) | /* VLD mode */
104 (0 << 10) | /* Stream-Out Enable */
105 ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
106 ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
107 (0 << 5) | /* not in stitch mode */
108 (1 << 4) | /* encoding mode */
109 (standard_select << 0)); /* standard select: avc or mpeg2 */
111 (0 << 7) | /* expand NOA bus flag */
112 (0 << 6) | /* disable slice-level clock gating */
113 (0 << 5) | /* disable clock gating for NOA */
114 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
115 (0 << 3) | /* terminate if AVC mbdata error occurs */
116 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
119 OUT_BCS_BATCH(batch, 0);
120 OUT_BCS_BATCH(batch, 0);
122 ADVANCE_BCS_BATCH(batch);
126 gen75_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
128 struct intel_batchbuffer *batch = encoder_context->base.batch;
129 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
131 BEGIN_BCS_BATCH(batch, 6);
133 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
134 OUT_BCS_BATCH(batch, 0);
136 ((mfc_context->surface_state.height - 1) << 18) |
137 ((mfc_context->surface_state.width - 1) << 4));
139 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
140 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
141 (0 << 22) | /* surface object control state, FIXME??? */
142 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
143 (0 << 2) | /* must be 0 for interleave U/V */
144 (1 << 1) | /* must be tiled */
145 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
147 (0 << 16) | /* must be 0 for interleave U/V */
148 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
149 OUT_BCS_BATCH(batch, 0);
151 ADVANCE_BCS_BATCH(batch);
155 gen75_mfc_ind_obj_base_addr_state_bplus(VADriverContextP ctx,
156 struct intel_encoder_context *encoder_context)
158 struct intel_batchbuffer *batch = encoder_context->base.batch;
159 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
160 struct gen6_vme_context *vme_context = encoder_context->vme_context;
162 BEGIN_BCS_BATCH(batch, 26);
164 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (26 - 2));
165 /* the DW1-3 is for the MFX indirect bistream offset */
166 OUT_BCS_BATCH(batch, 0);
167 OUT_BCS_BATCH(batch, 0);
168 OUT_BCS_BATCH(batch, 0);
169 /* the DW4-5 is the MFX upper bound */
170 OUT_BCS_BATCH(batch, 0);
171 OUT_BCS_BATCH(batch, 0);
173 /* the DW6-10 is for MFX Indirect MV Object Base Address */
174 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
175 OUT_BCS_BATCH(batch, 0);
176 OUT_BCS_BATCH(batch, 0);
177 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
178 OUT_BCS_BATCH(batch, 0);
180 /* the DW11-15 is for MFX IT-COFF. Not used on encoder */
181 OUT_BCS_BATCH(batch, 0);
182 OUT_BCS_BATCH(batch, 0);
183 OUT_BCS_BATCH(batch, 0);
184 OUT_BCS_BATCH(batch, 0);
185 OUT_BCS_BATCH(batch, 0);
187 /* the DW16-20 is for MFX indirect DBLK. Not used on encoder */
188 OUT_BCS_BATCH(batch, 0);
189 OUT_BCS_BATCH(batch, 0);
190 OUT_BCS_BATCH(batch, 0);
191 OUT_BCS_BATCH(batch, 0);
192 OUT_BCS_BATCH(batch, 0);
194 /* the DW21-25 is for MFC Indirect PAK-BSE Object Base Address for Encoder*/
196 mfc_context->mfc_indirect_pak_bse_object.bo,
197 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
199 OUT_BCS_BATCH(batch, 0);
200 OUT_BCS_BATCH(batch, 0);
203 mfc_context->mfc_indirect_pak_bse_object.bo,
204 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
205 mfc_context->mfc_indirect_pak_bse_object.end_offset);
206 OUT_BCS_BATCH(batch, 0);
208 ADVANCE_BCS_BATCH(batch);
212 gen75_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
214 struct intel_batchbuffer *batch = encoder_context->base.batch;
215 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
216 struct gen6_vme_context *vme_context = encoder_context->vme_context;
217 struct i965_driver_data *i965 = i965_driver_data(ctx);
219 if (IS_STEPPING_BPLUS(i965)) {
220 gen75_mfc_ind_obj_base_addr_state_bplus(ctx, encoder_context);
223 BEGIN_BCS_BATCH(batch, 11);
225 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
226 OUT_BCS_BATCH(batch, 0);
227 OUT_BCS_BATCH(batch, 0);
228 /* MFX Indirect MV Object Base Address */
229 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
230 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
231 OUT_BCS_BATCH(batch, 0);
232 OUT_BCS_BATCH(batch, 0);
233 OUT_BCS_BATCH(batch, 0);
234 OUT_BCS_BATCH(batch, 0);
235 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
237 mfc_context->mfc_indirect_pak_bse_object.bo,
238 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
241 mfc_context->mfc_indirect_pak_bse_object.bo,
242 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
243 mfc_context->mfc_indirect_pak_bse_object.end_offset);
245 ADVANCE_BCS_BATCH(batch);
249 gen75_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
250 struct intel_encoder_context *encoder_context)
252 struct intel_batchbuffer *batch = encoder_context->base.batch;
253 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
254 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
256 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
257 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
259 BEGIN_BCS_BATCH(batch, 16);
261 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
263 ((width_in_mbs * height_in_mbs) & 0xFFFF));
265 ((height_in_mbs - 1) << 16) |
266 ((width_in_mbs - 1) << 0));
268 (0 << 24) | /* Second Chroma QP Offset */
269 (0 << 16) | /* Chroma QP Offset */
270 (0 << 14) | /* Max-bit conformance Intra flag */
271 (0 << 13) | /* Max Macroblock size conformance Inter flag */
272 (pPicParameter->pic_fields.bits.weighted_pred_flag << 12) | /*Weighted_Pred_Flag */
273 (pPicParameter->pic_fields.bits.weighted_bipred_idc << 10) | /* Weighted_BiPred_Idc */
274 (0 << 8) | /* FIXME: Image Structure */
275 (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */
277 (0 << 16) | /* Mininum Frame size */
278 (0 << 15) | /* Disable reading of Macroblock Status Buffer */
279 (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */
280 (0 << 13) | /* CABAC 0 word insertion test enable */
281 (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
282 (1 << 10) | /* Chroma Format IDC, 4:2:0 */
283 (0 << 8) | /* FIXME: MbMvFormatFlag */
284 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
285 (0 << 6) | /* Only valid for VLD decoding mode */
286 (0 << 5) | /* Constrained Intra Predition Flag, from PPS */
287 (0 << 4) | /* Direct 8x8 inference flag */
288 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
289 (1 << 2) | /* Frame MB only flag */
290 (0 << 1) | /* MBAFF mode is in active */
291 (0 << 0)); /* Field picture flag */
292 OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */
293 OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */
294 (0xBB8 << 16) | /* InterMbMaxSz */
295 (0xEE8) ); /* IntraMbMaxSz */
296 OUT_BCS_BATCH(batch, 0); /* Reserved */
297 OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
298 OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
299 OUT_BCS_BATCH(batch, 0x8C000000);
300 OUT_BCS_BATCH(batch, 0x00010000);
301 OUT_BCS_BATCH(batch, 0);
302 OUT_BCS_BATCH(batch, 0);
303 OUT_BCS_BATCH(batch, 0);
304 OUT_BCS_BATCH(batch, 0);
306 ADVANCE_BCS_BATCH(batch);
310 gen75_mfc_qm_state(VADriverContextP ctx,
314 struct intel_encoder_context *encoder_context)
316 struct intel_batchbuffer *batch = encoder_context->base.batch;
317 unsigned int qm_buffer[16];
319 assert(qm_length <= 16);
320 assert(sizeof(*qm) == 4);
321 memcpy(qm_buffer, qm, qm_length * 4);
323 BEGIN_BCS_BATCH(batch, 18);
324 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
325 OUT_BCS_BATCH(batch, qm_type << 0);
326 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
327 ADVANCE_BCS_BATCH(batch);
331 gen75_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
333 unsigned int qm[16] = {
334 0x10101010, 0x10101010, 0x10101010, 0x10101010,
335 0x10101010, 0x10101010, 0x10101010, 0x10101010,
336 0x10101010, 0x10101010, 0x10101010, 0x10101010,
337 0x10101010, 0x10101010, 0x10101010, 0x10101010
340 gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
341 gen75_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
342 gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
343 gen75_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
347 gen75_mfc_fqm_state(VADriverContextP ctx,
351 struct intel_encoder_context *encoder_context)
353 struct intel_batchbuffer *batch = encoder_context->base.batch;
354 unsigned int fqm_buffer[32];
356 assert(fqm_length <= 32);
357 assert(sizeof(*fqm) == 4);
358 memcpy(fqm_buffer, fqm, fqm_length * 4);
360 BEGIN_BCS_BATCH(batch, 34);
361 OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
362 OUT_BCS_BATCH(batch, fqm_type << 0);
363 intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
364 ADVANCE_BCS_BATCH(batch);
368 gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
370 unsigned int qm[32] = {
371 0x10001000, 0x10001000, 0x10001000, 0x10001000,
372 0x10001000, 0x10001000, 0x10001000, 0x10001000,
373 0x10001000, 0x10001000, 0x10001000, 0x10001000,
374 0x10001000, 0x10001000, 0x10001000, 0x10001000,
375 0x10001000, 0x10001000, 0x10001000, 0x10001000,
376 0x10001000, 0x10001000, 0x10001000, 0x10001000,
377 0x10001000, 0x10001000, 0x10001000, 0x10001000,
378 0x10001000, 0x10001000, 0x10001000, 0x10001000
381 gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
382 gen75_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
383 gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
384 gen75_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
388 gen75_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
389 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
390 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
391 struct intel_batchbuffer *batch)
394 batch = encoder_context->base.batch;
396 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
398 OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
400 (0 << 16) | /* always start at offset 0 */
401 (data_bits_in_last_dw << 8) |
402 (skip_emul_byte_count << 4) |
403 (!!emulation_flag << 3) |
404 ((!!is_last_header) << 2) |
405 ((!!is_end_of_slice) << 1) |
406 (0 << 0)); /* FIXME: ??? */
407 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
409 ADVANCE_BCS_BATCH(batch);
413 static void gen75_mfc_init(VADriverContextP ctx,
414 struct encode_state *encode_state,
415 struct intel_encoder_context *encoder_context)
417 struct i965_driver_data *i965 = i965_driver_data(ctx);
418 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
421 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
422 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
423 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
425 /*Encode common setup for MFC*/
426 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
427 mfc_context->post_deblocking_output.bo = NULL;
429 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
430 mfc_context->pre_deblocking_output.bo = NULL;
432 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
433 mfc_context->uncompressed_picture_source.bo = NULL;
435 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
436 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
438 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
439 if ( mfc_context->direct_mv_buffers[i].bo != NULL);
440 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
441 mfc_context->direct_mv_buffers[i].bo = NULL;
444 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
445 if (mfc_context->reference_surfaces[i].bo != NULL)
446 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
447 mfc_context->reference_surfaces[i].bo = NULL;
450 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
451 bo = dri_bo_alloc(i965->intel.bufmgr,
456 mfc_context->intra_row_store_scratch_buffer.bo = bo;
458 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
459 bo = dri_bo_alloc(i965->intel.bufmgr,
461 width_in_mbs * height_in_mbs * 16,
464 mfc_context->macroblock_status_buffer.bo = bo;
466 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
467 bo = dri_bo_alloc(i965->intel.bufmgr,
469 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
472 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
474 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
475 bo = dri_bo_alloc(i965->intel.bufmgr,
477 2 * width_in_mbs * 64, /* 2 * width_in_mbs * 64 */
480 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
482 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
483 mfc_context->mfc_batchbuffer_surface.bo = NULL;
485 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
486 mfc_context->aux_batchbuffer_surface.bo = NULL;
488 if (mfc_context->aux_batchbuffer)
489 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
491 mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
492 mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
493 dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
494 mfc_context->aux_batchbuffer_surface.pitch = 16;
495 mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
496 mfc_context->aux_batchbuffer_surface.size_block = 16;
498 i965_gpe_context_init(ctx, &mfc_context->gpe_context);
502 gen75_mfc_pipe_buf_addr_state_bplus(VADriverContextP ctx,
503 struct intel_encoder_context *encoder_context)
505 struct intel_batchbuffer *batch = encoder_context->base.batch;
506 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
509 BEGIN_BCS_BATCH(batch, 61);
511 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (61 - 2));
513 /* the DW1-3 is for pre_deblocking */
514 if (mfc_context->pre_deblocking_output.bo)
515 OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
516 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
519 OUT_BCS_BATCH(batch, 0); /* pre output addr */
521 OUT_BCS_BATCH(batch, 0);
522 OUT_BCS_BATCH(batch, 0);
523 /* the DW4-6 is for the post_deblocking */
525 if (mfc_context->post_deblocking_output.bo)
526 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
527 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
528 0); /* post output addr */
530 OUT_BCS_BATCH(batch, 0);
531 OUT_BCS_BATCH(batch, 0);
532 OUT_BCS_BATCH(batch, 0);
534 /* the DW7-9 is for the uncompressed_picture */
535 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
536 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
537 0); /* uncompressed data */
539 OUT_BCS_BATCH(batch, 0);
540 OUT_BCS_BATCH(batch, 0);
542 /* the DW10-12 is for the mb status */
543 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
544 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
545 0); /* StreamOut data*/
546 OUT_BCS_BATCH(batch, 0);
547 OUT_BCS_BATCH(batch, 0);
549 /* the DW13-15 is for the intra_row_store_scratch */
550 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
551 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
553 OUT_BCS_BATCH(batch, 0);
554 OUT_BCS_BATCH(batch, 0);
556 /* the DW16-18 is for the deblocking filter */
557 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
558 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
560 OUT_BCS_BATCH(batch, 0);
561 OUT_BCS_BATCH(batch, 0);
563 /* the DW 19-50 is for Reference pictures*/
564 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
565 if ( mfc_context->reference_surfaces[i].bo != NULL) {
566 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
567 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
570 OUT_BCS_BATCH(batch, 0);
572 OUT_BCS_BATCH(batch, 0);
574 OUT_BCS_BATCH(batch, 0);
576 /* The DW 52-54 is for the MB status buffer */
577 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
578 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
579 0); /* Macroblock status buffer*/
581 OUT_BCS_BATCH(batch, 0);
582 OUT_BCS_BATCH(batch, 0);
584 /* the DW 55-57 is the ILDB buffer */
585 OUT_BCS_BATCH(batch, 0);
586 OUT_BCS_BATCH(batch, 0);
587 OUT_BCS_BATCH(batch, 0);
589 /* the DW 58-60 is the second ILDB buffer */
590 OUT_BCS_BATCH(batch, 0);
591 OUT_BCS_BATCH(batch, 0);
592 OUT_BCS_BATCH(batch, 0);
593 ADVANCE_BCS_BATCH(batch);
597 gen75_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
599 struct intel_batchbuffer *batch = encoder_context->base.batch;
600 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
601 struct i965_driver_data *i965 = i965_driver_data(ctx);
604 if (IS_STEPPING_BPLUS(i965)) {
605 gen75_mfc_pipe_buf_addr_state_bplus(ctx, encoder_context);
609 BEGIN_BCS_BATCH(batch, 25);
611 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (25 - 2));
613 if (mfc_context->pre_deblocking_output.bo)
614 OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
615 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
618 OUT_BCS_BATCH(batch, 0); /* pre output addr */
620 if (mfc_context->post_deblocking_output.bo)
621 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
622 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
623 0); /* post output addr */
625 OUT_BCS_BATCH(batch, 0);
627 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
628 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
629 0); /* uncompressed data */
630 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
631 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
632 0); /* StreamOut data*/
633 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
634 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
636 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
637 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
639 /* 7..22 Reference pictures*/
640 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
641 if ( mfc_context->reference_surfaces[i].bo != NULL) {
642 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
643 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
646 OUT_BCS_BATCH(batch, 0);
649 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
650 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
651 0); /* Macroblock status buffer*/
653 OUT_BCS_BATCH(batch, 0);
655 ADVANCE_BCS_BATCH(batch);
659 gen75_mfc_avc_directmode_state_bplus(VADriverContextP ctx,
660 struct intel_encoder_context *encoder_context)
662 struct intel_batchbuffer *batch = encoder_context->base.batch;
663 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
667 BEGIN_BCS_BATCH(batch, 71);
669 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (71 - 2));
671 /* Reference frames and Current frames */
672 /* the DW1-32 is for the direct MV for reference */
673 for(i = 0; i < NUM_MFC_DMV_BUFFERS - 2; i += 2) {
674 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
675 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
676 I915_GEM_DOMAIN_INSTRUCTION, 0,
678 OUT_BCS_BATCH(batch, 0);
680 OUT_BCS_BATCH(batch, 0);
681 OUT_BCS_BATCH(batch, 0);
684 OUT_BCS_BATCH(batch, 0);
686 /* the DW34-36 is the MV for the current reference */
687 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo,
688 I915_GEM_DOMAIN_INSTRUCTION, 0,
691 OUT_BCS_BATCH(batch, 0);
692 OUT_BCS_BATCH(batch, 0);
695 for(i = 0; i < 32; i++) {
696 OUT_BCS_BATCH(batch, i/2);
698 OUT_BCS_BATCH(batch, 0);
699 OUT_BCS_BATCH(batch, 0);
701 ADVANCE_BCS_BATCH(batch);
705 gen75_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
707 struct intel_batchbuffer *batch = encoder_context->base.batch;
708 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
709 struct i965_driver_data *i965 = i965_driver_data(ctx);
712 if (IS_STEPPING_BPLUS(i965)) {
713 gen75_mfc_avc_directmode_state_bplus(ctx, encoder_context);
717 BEGIN_BCS_BATCH(batch, 69);
719 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
721 /* Reference frames and Current frames */
722 for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
723 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
724 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
725 I915_GEM_DOMAIN_INSTRUCTION, 0,
728 OUT_BCS_BATCH(batch, 0);
733 for(i = 0; i < 32; i++) {
734 OUT_BCS_BATCH(batch, i/2);
736 OUT_BCS_BATCH(batch, 0);
737 OUT_BCS_BATCH(batch, 0);
739 ADVANCE_BCS_BATCH(batch);
743 gen75_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
745 struct intel_batchbuffer *batch = encoder_context->base.batch;
748 BEGIN_BCS_BATCH(batch, 10);
749 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
750 OUT_BCS_BATCH(batch, 0); //Select L0
751 OUT_BCS_BATCH(batch, 0x80808020); //Only 1 reference
752 for(i = 0; i < 7; i++) {
753 OUT_BCS_BATCH(batch, 0x80808080);
755 ADVANCE_BCS_BATCH(batch);
757 BEGIN_BCS_BATCH(batch, 10);
758 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
759 OUT_BCS_BATCH(batch, 1); //Select L1
760 OUT_BCS_BATCH(batch, 0x80808022); //Only 1 reference
761 for(i = 0; i < 7; i++) {
762 OUT_BCS_BATCH(batch, 0x80808080);
764 ADVANCE_BCS_BATCH(batch);
769 gen75_mfc_bsp_buf_base_addr_state_bplus(VADriverContextP ctx,
770 struct intel_encoder_context *encoder_context)
772 struct intel_batchbuffer *batch = encoder_context->base.batch;
773 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
775 BEGIN_BCS_BATCH(batch, 10);
777 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (10 - 2));
778 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
779 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
781 OUT_BCS_BATCH(batch, 0);
782 OUT_BCS_BATCH(batch, 0);
784 /* the DW4-6 is for MPR Row Store Scratch Buffer Base Address */
785 OUT_BCS_BATCH(batch, 0);
786 OUT_BCS_BATCH(batch, 0);
787 OUT_BCS_BATCH(batch, 0);
789 /* the DW7-9 is for Bitplane Read Buffer Base Address */
790 OUT_BCS_BATCH(batch, 0);
791 OUT_BCS_BATCH(batch, 0);
792 OUT_BCS_BATCH(batch, 0);
794 ADVANCE_BCS_BATCH(batch);
798 gen75_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
800 struct intel_batchbuffer *batch = encoder_context->base.batch;
801 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
802 struct i965_driver_data *i965 = i965_driver_data(ctx);
804 if (IS_STEPPING_BPLUS(i965)) {
805 gen75_mfc_bsp_buf_base_addr_state_bplus(ctx, encoder_context);
809 BEGIN_BCS_BATCH(batch, 4);
811 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
812 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
813 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
815 OUT_BCS_BATCH(batch, 0);
816 OUT_BCS_BATCH(batch, 0);
818 ADVANCE_BCS_BATCH(batch);
822 static void gen75_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
823 struct encode_state *encode_state,
824 struct intel_encoder_context *encoder_context)
826 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
828 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
829 mfc_context->set_surface_state(ctx, encoder_context);
830 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
831 gen75_mfc_pipe_buf_addr_state(ctx, encoder_context);
832 gen75_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
833 mfc_context->avc_img_state(ctx, encode_state, encoder_context);
834 mfc_context->avc_qm_state(ctx, encoder_context);
835 mfc_context->avc_fqm_state(ctx, encoder_context);
836 gen75_mfc_avc_directmode_state(ctx, encoder_context);
837 gen75_mfc_avc_ref_idx_state(ctx, encoder_context);
841 static VAStatus gen75_mfc_run(VADriverContextP ctx,
842 struct encode_state *encode_state,
843 struct intel_encoder_context *encoder_context)
845 struct intel_batchbuffer *batch = encoder_context->base.batch;
847 intel_batchbuffer_flush(batch); //run the pipeline
849 return VA_STATUS_SUCCESS;
854 gen75_mfc_stop(VADriverContextP ctx,
855 struct encode_state *encode_state,
856 struct intel_encoder_context *encoder_context,
857 int *encoded_bits_size)
859 VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
860 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
861 VACodedBufferSegment *coded_buffer_segment;
863 vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
864 assert(vaStatus == VA_STATUS_SUCCESS);
865 *encoded_bits_size = coded_buffer_segment->size * 8;
866 i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
868 return VA_STATUS_SUCCESS;
873 gen75_mfc_avc_slice_state(VADriverContextP ctx,
874 VAEncPictureParameterBufferH264 *pic_param,
875 VAEncSliceParameterBufferH264 *slice_param,
876 struct encode_state *encode_state,
877 struct intel_encoder_context *encoder_context,
878 int rate_control_enable,
880 struct intel_batchbuffer *batch)
882 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
883 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
884 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
885 int beginmb = slice_param->macroblock_address;
886 int endmb = beginmb + slice_param->num_macroblocks;
887 int beginx = beginmb % width_in_mbs;
888 int beginy = beginmb / width_in_mbs;
889 int nextx = endmb % width_in_mbs;
890 int nexty = endmb / width_in_mbs;
891 int slice_type = slice_param->slice_type;
892 int last_slice = (endmb == (width_in_mbs * height_in_mbs));
893 int bit_rate_control_target, maxQpN, maxQpP;
894 unsigned char correct[6], grow, shrink;
896 int weighted_pred_idc = 0;
897 unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
898 unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
901 batch = encoder_context->base.batch;
903 bit_rate_control_target = slice_type;
904 if (slice_type == SLICE_TYPE_SP)
905 bit_rate_control_target = SLICE_TYPE_P;
906 else if (slice_type == SLICE_TYPE_SI)
907 bit_rate_control_target = SLICE_TYPE_I;
909 if (slice_type == SLICE_TYPE_P) {
910 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
911 } else if (slice_type == SLICE_TYPE_B) {
912 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
914 if (weighted_pred_idc == 2) {
915 /* 8.4.3 - Derivation process for prediction weights (8-279) */
916 luma_log2_weight_denom = 5;
917 chroma_log2_weight_denom = 5;
921 maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
922 maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
924 for (i = 0; i < 6; i++)
925 correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
927 grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
928 (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
929 shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
930 (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
932 BEGIN_BCS_BATCH(batch, 11);;
934 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
935 OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
937 if (slice_type == SLICE_TYPE_I) {
938 OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
941 (1 << 16) | /*1 reference frame*/
942 (chroma_log2_weight_denom << 8) |
943 (luma_log2_weight_denom << 0));
947 (weighted_pred_idc << 30) |
948 (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
949 (slice_param->disable_deblocking_filter_idc << 27) |
950 (slice_param->cabac_init_idc << 24) |
951 (qp<<16) | /*Slice Quantization Parameter*/
952 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
953 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
955 (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
957 slice_param->macroblock_address );
958 OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
960 (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/
961 (1 << 30) | /*ResetRateControlCounter*/
962 (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
963 (4 << 24) | /*RC Stable Tolerance, middle level*/
964 (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/
965 (0 << 22) | /*QP mode, don't modfiy CBP*/
966 (0 << 21) | /*MB Type Direct Conversion Enabled*/
967 (0 << 20) | /*MB Type Skip Conversion Enabled*/
968 (last_slice << 19) | /*IsLastSlice*/
969 (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
970 (1 << 17) | /*HeaderPresentFlag*/
971 (1 << 16) | /*SliceData PresentFlag*/
972 (1 << 15) | /*TailPresentFlag*/
973 (1 << 13) | /*RBSP NAL TYPE*/
974 (0 << 12) ); /*CabacZeroWordInsertionEnable*/
975 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
977 (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
978 (maxQpP << 16) | /*Target QP + 20 is highest QP*/
988 OUT_BCS_BATCH(batch, 0);
990 ADVANCE_BCS_BATCH(batch);
994 #ifdef MFC_SOFTWARE_HASWELL
997 gen75_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
998 int qp,unsigned int *msg,
999 struct intel_encoder_context *encoder_context,
1000 unsigned char target_mb_size, unsigned char max_mb_size,
1001 struct intel_batchbuffer *batch)
1003 int len_in_dwords = 12;
1004 unsigned int intra_msg;
1005 #define INTRA_MSG_FLAG (1 << 13)
1006 #define INTRA_MBTYPE_MASK (0x1F0000)
1008 batch = encoder_context->base.batch;
1010 BEGIN_BCS_BATCH(batch, len_in_dwords);
1012 intra_msg = msg[0] & 0xC0FF;
1013 intra_msg |= INTRA_MSG_FLAG;
1014 intra_msg |= ((msg[0] & INTRA_MBTYPE_MASK) >> 8);
1015 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
1016 OUT_BCS_BATCH(batch, 0);
1017 OUT_BCS_BATCH(batch, 0);
1018 OUT_BCS_BATCH(batch,
1019 (0 << 24) | /* PackedMvNum, Debug*/
1020 (0 << 20) | /* No motion vector */
1021 (1 << 19) | /* CbpDcY */
1022 (1 << 18) | /* CbpDcU */
1023 (1 << 17) | /* CbpDcV */
1026 OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
1027 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
1028 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
1030 /*Stuff for Intra MB*/
1031 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
1032 OUT_BCS_BATCH(batch, msg[2]);
1033 OUT_BCS_BATCH(batch, msg[3]&0xFF);
1035 /*MaxSizeInWord and TargetSzieInWord*/
1036 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
1037 (target_mb_size << 16) );
1039 OUT_BCS_BATCH(batch, 0);
1041 ADVANCE_BCS_BATCH(batch);
1043 return len_in_dwords;
1047 gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
1048 unsigned int *msg, unsigned int offset,
1049 struct intel_encoder_context *encoder_context,
1050 unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
1051 struct intel_batchbuffer *batch)
1053 int len_in_dwords = 12;
1054 unsigned int inter_msg = 0;
1056 batch = encoder_context->base.batch;
1058 #define MSG_MV_OFFSET 4
1059 unsigned int *mv_ptr;
1060 mv_ptr = msg + MSG_MV_OFFSET;
1061 /* MV of VME output is based on 16 sub-blocks. So it is necessary
1062 * to convert them to be compatible with the format of AVC_PAK
1065 if ((msg[0] & INTER_MODE_MASK) == INTER_8X16) {
1066 /* MV[0] and MV[2] are replicated */
1067 mv_ptr[4] = mv_ptr[0];
1068 mv_ptr[5] = mv_ptr[1];
1069 mv_ptr[2] = mv_ptr[8];
1070 mv_ptr[3] = mv_ptr[9];
1071 mv_ptr[6] = mv_ptr[8];
1072 mv_ptr[7] = mv_ptr[9];
1073 } else if ((msg[0] & INTER_MODE_MASK) == INTER_16X8) {
1074 /* MV[0] and MV[1] are replicated */
1075 mv_ptr[2] = mv_ptr[0];
1076 mv_ptr[3] = mv_ptr[1];
1077 mv_ptr[4] = mv_ptr[16];
1078 mv_ptr[5] = mv_ptr[17];
1079 mv_ptr[6] = mv_ptr[24];
1080 mv_ptr[7] = mv_ptr[25];
1081 } else if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
1082 !(msg[1] & SUBMB_SHAPE_MASK)) {
1083 /* Don't touch MV[0] or MV[1] */
1084 mv_ptr[2] = mv_ptr[8];
1085 mv_ptr[3] = mv_ptr[9];
1086 mv_ptr[4] = mv_ptr[16];
1087 mv_ptr[5] = mv_ptr[17];
1088 mv_ptr[6] = mv_ptr[24];
1089 mv_ptr[7] = mv_ptr[25];
1093 BEGIN_BCS_BATCH(batch, len_in_dwords);
1095 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
1099 if ((msg[0] & INTER_MODE_MASK) == INTER_8X8) {
1100 if (msg[1] & SUBMB_SHAPE_MASK)
1103 OUT_BCS_BATCH(batch, inter_msg); /* 32 MV*/
1104 OUT_BCS_BATCH(batch, offset);
1105 inter_msg = msg[0] & (0x1F00FFFF);
1106 inter_msg |= INTER_MV8;
1107 inter_msg |= ((1 << 19) | (1 << 18) | (1 << 17));
1108 if (((msg[0] & INTER_MODE_MASK) == INTER_8X8) &&
1109 (msg[1] & SUBMB_SHAPE_MASK)) {
1110 inter_msg |= INTER_MV32;
1113 OUT_BCS_BATCH(batch, inter_msg);
1115 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
1116 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
1118 if ( slice_type == SLICE_TYPE_B) {
1119 OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
1121 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
1124 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
1127 inter_msg = msg[1] >> 8;
1128 /*Stuff for Inter MB*/
1129 OUT_BCS_BATCH(batch, inter_msg);
1130 OUT_BCS_BATCH(batch, 0x0);
1131 OUT_BCS_BATCH(batch, 0x0);
1133 /*MaxSizeInWord and TargetSzieInWord*/
1134 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
1135 (target_mb_size << 16) );
1137 OUT_BCS_BATCH(batch, 0x0);
1139 ADVANCE_BCS_BATCH(batch);
1141 return len_in_dwords;
1144 #define INTRA_RDO_OFFSET 4
1145 #define INTER_RDO_OFFSET 54
1146 #define INTER_MSG_OFFSET 52
1147 #define INTER_MV_OFFSET 224
1148 #define RDO_MASK 0xFFFF
1151 gen75_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
1152 struct encode_state *encode_state,
1153 struct intel_encoder_context *encoder_context,
1155 struct intel_batchbuffer *slice_batch)
1157 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1158 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1159 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1160 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1161 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1162 unsigned int *msg = NULL, offset = 0;
1163 unsigned char *msg_ptr = NULL;
1164 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
1165 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1166 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1167 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1169 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1170 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1171 unsigned char *slice_header = NULL;
1172 int slice_header_length_in_bits = 0;
1173 unsigned int tail_data[] = { 0x0, 0x0 };
1174 int slice_type = pSliceParameter->slice_type;
1177 if (rate_control_mode == VA_RC_CBR) {
1178 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1179 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1182 /* only support for 8-bit pixel bit-depth */
1183 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1184 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1185 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1186 assert(qp >= 0 && qp < 52);
1188 gen75_mfc_avc_slice_state(ctx,
1191 encode_state, encoder_context,
1192 (rate_control_mode == VA_RC_CBR), qp, slice_batch);
1194 if ( slice_index == 0)
1195 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1197 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1200 mfc_context->insert_object(ctx, encoder_context,
1201 (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
1202 5, /* first 5 bytes are start code + nal unit type */
1203 1, 0, 1, slice_batch);
1205 dri_bo_map(vme_context->vme_output.bo , 1);
1206 msg_ptr = (unsigned char *)vme_context->vme_output.bo->virtual;
1209 msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
1211 msg = (unsigned int *) (msg_ptr + pSliceParameter->macroblock_address * vme_context->vme_output.size_block);
1214 for (i = pSliceParameter->macroblock_address;
1215 i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
1216 int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
1217 x = i % width_in_mbs;
1218 y = i / width_in_mbs;
1219 msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
1223 gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
1225 int inter_rdo, intra_rdo;
1226 inter_rdo = msg[INTER_RDO_OFFSET] & RDO_MASK;
1227 intra_rdo = msg[INTRA_RDO_OFFSET] & RDO_MASK;
1228 offset = i * vme_context->vme_output.size_block + INTER_MV_OFFSET;
1229 if (intra_rdo < inter_rdo) {
1230 gen75_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
1232 msg += INTER_MSG_OFFSET;
1233 gen75_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
1238 dri_bo_unmap(vme_context->vme_output.bo);
1241 mfc_context->insert_object(ctx, encoder_context,
1243 2, 1, 1, 0, slice_batch);
1245 mfc_context->insert_object(ctx, encoder_context,
1247 1, 1, 1, 0, slice_batch);
1255 gen75_mfc_avc_software_batchbuffer(VADriverContextP ctx,
1256 struct encode_state *encode_state,
1257 struct intel_encoder_context *encoder_context)
1259 struct i965_driver_data *i965 = i965_driver_data(ctx);
1260 struct intel_batchbuffer *batch;
1264 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1265 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
1266 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
1268 buffer_size = width_in_mbs * height_in_mbs * 64;
1269 batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, buffer_size);
1270 batch_bo = batch->buffer;
1271 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1272 gen75_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
1275 intel_batchbuffer_align(batch, 8);
1277 BEGIN_BCS_BATCH(batch, 2);
1278 OUT_BCS_BATCH(batch, 0);
1279 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
1280 ADVANCE_BCS_BATCH(batch);
1282 dri_bo_reference(batch_bo);
1283 intel_batchbuffer_free(batch);
1291 gen75_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
1292 struct encode_state *encode_state,
1293 struct intel_encoder_context *encoder_context)
1296 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1297 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1299 assert(vme_context->vme_output.bo);
1300 mfc_context->buffer_suface_setup(ctx,
1301 &mfc_context->gpe_context,
1302 &vme_context->vme_output,
1303 BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
1304 SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
1305 assert(mfc_context->aux_batchbuffer_surface.bo);
1306 mfc_context->buffer_suface_setup(ctx,
1307 &mfc_context->gpe_context,
1308 &mfc_context->aux_batchbuffer_surface,
1309 BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
1310 SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
1314 gen75_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
1315 struct encode_state *encode_state,
1316 struct intel_encoder_context *encoder_context)
1319 struct i965_driver_data *i965 = i965_driver_data(ctx);
1320 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1321 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1322 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
1323 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
1324 mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
1325 mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
1326 mfc_context->mfc_batchbuffer_surface.pitch = 16;
1327 mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
1329 mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
1331 mfc_context->buffer_suface_setup(ctx,
1332 &mfc_context->gpe_context,
1333 &mfc_context->mfc_batchbuffer_surface,
1334 BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
1335 SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
1339 gen75_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
1340 struct encode_state *encode_state,
1341 struct intel_encoder_context *encoder_context)
1343 gen75_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
1344 gen75_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
1348 gen75_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
1349 struct encode_state *encode_state,
1350 struct intel_encoder_context *encoder_context)
1352 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1353 struct gen6_interface_descriptor_data *desc;
1357 bo = mfc_context->gpe_context.idrt.bo;
1359 assert(bo->virtual);
1362 for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
1363 struct i965_kernel *kernel;
1365 kernel = &mfc_context->gpe_context.kernels[i];
1366 assert(sizeof(*desc) == 32);
1368 /*Setup the descritor table*/
1369 memset(desc, 0, sizeof(*desc));
1370 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
1371 desc->desc2.sampler_count = 0;
1372 desc->desc2.sampler_state_pointer = 0;
1373 desc->desc3.binding_table_entry_count = 2;
1374 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
1375 desc->desc4.constant_urb_entry_read_offset = 0;
1376 desc->desc4.constant_urb_entry_read_length = 4;
1379 dri_bo_emit_reloc(bo,
1380 I915_GEM_DOMAIN_INSTRUCTION, 0,
1382 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
1391 gen75_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1392 struct encode_state *encode_state,
1393 struct intel_encoder_context *encoder_context)
1395 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1401 gen75_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1404 int batchbuffer_offset,
1416 BEGIN_BATCH(batch, 12);
1418 OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1419 OUT_BATCH(batch, index);
1420 OUT_BATCH(batch, 0);
1421 OUT_BATCH(batch, 0);
1422 OUT_BATCH(batch, 0);
1423 OUT_BATCH(batch, 0);
1426 OUT_BATCH(batch, head_offset);
1427 OUT_BATCH(batch, batchbuffer_offset);
1432 number_mb_cmds << 16 |
1443 ADVANCE_BATCH(batch);
1447 gen75_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1448 struct intel_encoder_context *encoder_context,
1449 VAEncSliceParameterBufferH264 *slice_param,
1451 unsigned short head_size,
1452 unsigned short tail_size,
1453 int batchbuffer_offset,
1457 struct intel_batchbuffer *batch = encoder_context->base.batch;
1458 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1459 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1460 int total_mbs = slice_param->num_macroblocks;
1461 int number_mb_cmds = 128;
1462 int starting_mb = 0;
1463 int last_object = 0;
1464 int first_object = 1;
1467 int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1469 for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1470 last_object = (total_mbs - starting_mb) == number_mb_cmds;
1471 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1472 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1473 assert(mb_x <= 255 && mb_y <= 255);
1475 starting_mb += number_mb_cmds;
1477 gen75_mfc_batchbuffer_emit_object_command(batch,
1493 head_offset += head_size;
1494 batchbuffer_offset += head_size;
1498 head_offset += tail_size;
1499 batchbuffer_offset += tail_size;
1502 batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1509 number_mb_cmds = total_mbs % number_mb_cmds;
1510 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1511 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1512 assert(mb_x <= 255 && mb_y <= 255);
1513 starting_mb += number_mb_cmds;
1515 gen75_mfc_batchbuffer_emit_object_command(batch,
1533 * return size in Owords (16bytes)
1536 gen75_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1537 struct encode_state *encode_state,
1538 struct intel_encoder_context *encoder_context,
1540 int batchbuffer_offset)
1542 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1543 struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1544 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1545 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1546 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1547 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1548 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1549 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1550 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1551 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1552 unsigned char *slice_header = NULL;
1553 int slice_header_length_in_bits = 0;
1554 unsigned int tail_data[] = { 0x0, 0x0 };
1556 int old_used = intel_batchbuffer_used_size(slice_batch), used;
1557 unsigned short head_size, tail_size;
1558 int slice_type = pSliceParameter->slice_type;
1560 if (rate_control_mode == VA_RC_CBR) {
1561 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1562 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1565 /* only support for 8-bit pixel bit-depth */
1566 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1567 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1568 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1569 assert(qp >= 0 && qp < 52);
1571 head_offset = old_used / 16;
1572 gen75_mfc_avc_slice_state(ctx,
1577 (rate_control_mode == VA_RC_CBR),
1581 if (slice_index == 0)
1582 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1584 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1587 mfc_context->insert_object(ctx,
1589 (unsigned int *)slice_header,
1590 ALIGN(slice_header_length_in_bits, 32) >> 5,
1591 slice_header_length_in_bits & 0x1f,
1592 5, /* first 5 bytes are start code + nal unit type */
1599 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1600 used = intel_batchbuffer_used_size(slice_batch);
1601 head_size = (used - old_used) / 16;
1606 mfc_context->insert_object(ctx,
1617 mfc_context->insert_object(ctx,
1629 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1630 used = intel_batchbuffer_used_size(slice_batch);
1631 tail_size = (used - old_used) / 16;
1634 gen75_mfc_avc_batchbuffer_slice_command(ctx,
1644 return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1648 gen75_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1649 struct encode_state *encode_state,
1650 struct intel_encoder_context *encoder_context)
1652 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1653 struct intel_batchbuffer *batch = encoder_context->base.batch;
1654 int i, size, offset = 0;
1655 intel_batchbuffer_start_atomic(batch, 0x4000);
1656 gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1658 for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1659 size = gen75_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1663 intel_batchbuffer_end_atomic(batch);
1664 intel_batchbuffer_flush(batch);
1668 gen75_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1669 struct encode_state *encode_state,
1670 struct intel_encoder_context *encoder_context)
1672 gen75_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1673 gen75_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1674 gen75_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1675 gen75_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1679 gen75_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1680 struct encode_state *encode_state,
1681 struct intel_encoder_context *encoder_context)
1683 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1685 gen75_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1686 dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1688 return mfc_context->mfc_batchbuffer_surface.bo;
1694 gen75_mfc_avc_pipeline_programing(VADriverContextP ctx,
1695 struct encode_state *encode_state,
1696 struct intel_encoder_context *encoder_context)
1698 struct intel_batchbuffer *batch = encoder_context->base.batch;
1699 dri_bo *slice_batch_bo;
1701 if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1702 fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1707 #ifdef MFC_SOFTWARE_HASWELL
1708 slice_batch_bo = gen75_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1710 slice_batch_bo = gen75_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1714 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1715 intel_batchbuffer_emit_mi_flush(batch);
1717 // picture level programing
1718 gen75_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1720 BEGIN_BCS_BATCH(batch, 2);
1721 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1722 OUT_BCS_RELOC(batch,
1724 I915_GEM_DOMAIN_COMMAND, 0,
1726 ADVANCE_BCS_BATCH(batch);
1729 intel_batchbuffer_end_atomic(batch);
1731 dri_bo_unreference(slice_batch_bo);
1736 gen75_mfc_avc_encode_picture(VADriverContextP ctx,
1737 struct encode_state *encode_state,
1738 struct intel_encoder_context *encoder_context)
1740 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1741 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1742 int current_frame_bits_size;
1746 gen75_mfc_init(ctx, encode_state, encoder_context);
1747 intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1748 /*Programing bcs pipeline*/
1749 gen75_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
1750 gen75_mfc_run(ctx, encode_state, encoder_context);
1751 if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1752 gen75_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
1753 sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1754 if (sts == BRC_NO_HRD_VIOLATION) {
1755 intel_mfc_hrd_context_update(encode_state, mfc_context);
1758 else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1759 if (!mfc_context->hrd.violation_noted) {
1760 fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1761 mfc_context->hrd.violation_noted = 1;
1763 return VA_STATUS_SUCCESS;
1770 return VA_STATUS_SUCCESS;
1778 va_to_gen75_mpeg2_picture_type[3] = {
1785 gen75_mfc_mpeg2_pic_state(VADriverContextP ctx,
1786 struct intel_encoder_context *encoder_context,
1787 struct encode_state *encode_state)
1789 struct intel_batchbuffer *batch = encoder_context->base.batch;
1790 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1791 VAEncPictureParameterBufferMPEG2 *pic_param;
1792 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1793 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1795 assert(encode_state->pic_param_ext && encode_state->pic_param_ext->buffer);
1796 pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
1798 BEGIN_BCS_BATCH(batch, 13);
1799 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (13 - 2));
1800 OUT_BCS_BATCH(batch,
1801 (pic_param->f_code[1][1] & 0xf) << 28 | /* f_code[1][1] */
1802 (pic_param->f_code[1][0] & 0xf) << 24 | /* f_code[1][0] */
1803 (pic_param->f_code[0][1] & 0xf) << 20 | /* f_code[0][1] */
1804 (pic_param->f_code[0][0] & 0xf) << 16 | /* f_code[0][0] */
1805 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1806 pic_param->picture_coding_extension.bits.picture_structure << 12 |
1807 pic_param->picture_coding_extension.bits.top_field_first << 11 |
1808 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1809 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1810 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1811 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1812 pic_param->picture_coding_extension.bits.alternate_scan << 6);
1813 OUT_BCS_BATCH(batch,
1814 0 << 14 | /* LoadSlicePointerFlag, 0 means only loading bitstream pointer once */
1815 va_to_gen75_mpeg2_picture_type[pic_param->picture_type] << 9 |
1817 OUT_BCS_BATCH(batch,
1818 1 << 31 | /* slice concealment */
1819 (height_in_mbs - 1) << 16 |
1820 (width_in_mbs - 1));
1821 OUT_BCS_BATCH(batch, 0);
1822 OUT_BCS_BATCH(batch, 0);
1823 OUT_BCS_BATCH(batch,
1824 0xFFF << 16 | /* InterMBMaxSize */
1825 0xFFF << 0 | /* IntraMBMaxSize */
1827 OUT_BCS_BATCH(batch, 0);
1828 OUT_BCS_BATCH(batch, 0);
1829 OUT_BCS_BATCH(batch, 0);
1830 OUT_BCS_BATCH(batch, 0);
1831 OUT_BCS_BATCH(batch, 0);
1832 OUT_BCS_BATCH(batch, 0);
1833 ADVANCE_BCS_BATCH(batch);
1837 gen75_mfc_mpeg2_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1839 unsigned int qm[16] = {
1840 0x10101010, 0x10101010, 0x10101010, 0x10101010,
1841 0x10101010, 0x10101010, 0x10101010, 0x10101010,
1842 0x10101010, 0x10101010, 0x10101010, 0x10101010,
1843 0x10101010, 0x10101010, 0x10101010, 0x10101010
1846 gen75_mfc_qm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, qm, 16, encoder_context);
1847 gen75_mfc_qm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, qm, 16,encoder_context);
1851 gen75_mfc_mpeg2_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1853 unsigned int qm[32] = {
1854 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1855 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1856 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1857 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1858 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1859 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1860 0x10001000, 0x10001000, 0x10001000, 0x10001000,
1861 0x10001000, 0x10001000, 0x10001000, 0x10001000
1864 gen75_mfc_fqm_state(ctx, MFX_QM_MPEG_INTRA_QUANTIZER_MATRIX, qm, 32, encoder_context);
1865 gen75_mfc_fqm_state(ctx, MFX_QM_MPEG_NON_INTRA_QUANTIZER_MATRIX, qm, 32, encoder_context);
1869 gen75_mfc_mpeg2_slicegroup_state(VADriverContextP ctx,
1870 struct intel_encoder_context *encoder_context,
1872 int next_x, int next_y,
1873 int is_fisrt_slice_group,
1874 int is_last_slice_group,
1877 struct intel_batchbuffer *batch)
1879 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1882 batch = encoder_context->base.batch;
1884 BEGIN_BCS_BATCH(batch, 8);
1886 OUT_BCS_BATCH(batch, MFC_MPEG2_SLICEGROUP_STATE | (8 - 2));
1887 OUT_BCS_BATCH(batch,
1888 0 << 31 | /* MbRateCtrlFlag */
1889 !!is_last_slice_group << 19 | /* IsLastSliceGrp */
1890 !!is_fisrt_slice_group << 17 | /* Insert Header before the first slice group data */
1891 1 << 16 | /* SliceData PresentFlag: always 1 */
1892 1 << 15 | /* TailPresentFlag: always 1 */
1893 0 << 14 | /* FirstSliceHdrDisabled: slice header for each slice */
1894 !!intra_slice << 13 | /* IntraSlice */
1895 !!intra_slice << 12 | /* IntraSliceFlag */
1897 OUT_BCS_BATCH(batch,
1903 OUT_BCS_BATCH(batch, qp); /* FIXME: SliceGroupQp */
1904 /* bitstream pointer is only loaded once for the first slice of a frame when
1905 * LoadSlicePointerFlag is 0
1907 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
1908 OUT_BCS_BATCH(batch, 0); /* FIXME: */
1909 OUT_BCS_BATCH(batch, 0); /* FIXME: CorrectPoints */
1910 OUT_BCS_BATCH(batch, 0); /* FIXME: CVxxx */
1912 ADVANCE_BCS_BATCH(batch);
1916 gen75_mfc_mpeg2_pak_object_intra(VADriverContextP ctx,
1917 struct intel_encoder_context *encoder_context,
1919 int first_mb_in_slice,
1920 int last_mb_in_slice,
1921 int first_mb_in_slice_group,
1922 int last_mb_in_slice_group,
1925 int coded_block_pattern,
1926 unsigned char target_size_in_word,
1927 unsigned char max_size_in_word,
1928 struct intel_batchbuffer *batch)
1930 int len_in_dwords = 9;
1933 batch = encoder_context->base.batch;
1935 BEGIN_BCS_BATCH(batch, len_in_dwords);
1937 OUT_BCS_BATCH(batch, MFC_MPEG2_PAK_OBJECT | (len_in_dwords - 2));
1938 OUT_BCS_BATCH(batch,
1939 0 << 24 | /* PackedMvNum */
1940 0 << 20 | /* MvFormat */
1941 7 << 17 | /* CbpDcY/CbpDcU/CbpDcV */
1942 0 << 15 | /* TransformFlag: frame DCT */
1943 0 << 14 | /* FieldMbFlag */
1944 1 << 13 | /* IntraMbFlag */
1945 mb_type << 8 | /* MbType: Intra */
1946 0 << 2 | /* SkipMbFlag */
1947 0 << 0 | /* InterMbMode */
1949 OUT_BCS_BATCH(batch, y << 16 | x);
1950 OUT_BCS_BATCH(batch,
1951 max_size_in_word << 24 |
1952 target_size_in_word << 16 |
1953 coded_block_pattern << 0 | /* CBP */
1955 OUT_BCS_BATCH(batch,
1956 last_mb_in_slice << 31 |
1957 first_mb_in_slice << 30 |
1958 0 << 27 | /* EnableCoeffClamp */
1959 last_mb_in_slice_group << 26 |
1960 0 << 25 | /* MbSkipConvDisable */
1961 first_mb_in_slice_group << 24 |
1962 0 << 16 | /* MvFieldSelect */
1963 qp_scale_code << 0 |
1965 OUT_BCS_BATCH(batch, 0); /* MV[0][0] */
1966 OUT_BCS_BATCH(batch, 0); /* MV[1][0] */
1967 OUT_BCS_BATCH(batch, 0); /* MV[0][1] */
1968 OUT_BCS_BATCH(batch, 0); /* MV[1][1] */
1970 ADVANCE_BCS_BATCH(batch);
1972 return len_in_dwords;
1975 #define INTRA_RDO_OFFSET 4
1976 #define INTER_RDO_OFFSET 54
1977 #define INTER_MSG_OFFSET 52
1978 #define INTER_MV_OFFSET 224
1979 #define RDO_MASK 0xFFFF
1982 intel_mfc_mpeg2_pipeline_header_programing(VADriverContextP ctx,
1983 struct encode_state *encode_state,
1984 struct intel_encoder_context *encoder_context,
1985 struct intel_batchbuffer *slice_batch)
1987 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1988 int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_SPS);
1990 if (encode_state->packed_header_data[idx]) {
1991 VAEncPackedHeaderParameterBuffer *param = NULL;
1992 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
1993 unsigned int length_in_bits;
1995 assert(encode_state->packed_header_param[idx]);
1996 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
1997 length_in_bits = param->bit_length;
1999 mfc_context->insert_object(ctx,
2002 ALIGN(length_in_bits, 32) >> 5,
2003 length_in_bits & 0x1f,
2004 5, /* FIXME: check it */
2007 !param->has_emulation_bytes,
2011 idx = va_enc_packed_type_to_idx(VAEncPackedHeaderMPEG2_PPS);
2013 if (encode_state->packed_header_data[idx]) {
2014 VAEncPackedHeaderParameterBuffer *param = NULL;
2015 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
2016 unsigned int length_in_bits;
2018 assert(encode_state->packed_header_param[idx]);
2019 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
2020 length_in_bits = param->bit_length;
2022 mfc_context->insert_object(ctx,
2025 ALIGN(length_in_bits, 32) >> 5,
2026 length_in_bits & 0x1f,
2027 5, /* FIXME: check it */
2030 !param->has_emulation_bytes,
2036 gen75_mfc_mpeg2_pipeline_slice_group(VADriverContextP ctx,
2037 struct encode_state *encode_state,
2038 struct intel_encoder_context *encoder_context,
2040 VAEncSliceParameterBufferMPEG2 *next_slice_group_param,
2041 struct intel_batchbuffer *slice_batch)
2043 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
2044 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
2045 VAEncSliceParameterBufferMPEG2 *slice_param = NULL;
2046 unsigned int tail_data[] = {0x0, 0x0, 0x0, 0x0};
2047 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
2048 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
2050 int h_start_pos, v_start_pos, h_next_start_pos, v_next_start_pos;
2052 slice_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[slice_index]->buffer;
2053 h_start_pos = slice_param->macroblock_address % width_in_mbs;
2054 v_start_pos = slice_param->macroblock_address / width_in_mbs;
2055 assert(h_start_pos + slice_param->num_macroblocks <= width_in_mbs);
2057 if (next_slice_group_param) {
2058 h_next_start_pos = next_slice_group_param->macroblock_address % width_in_mbs;
2059 v_next_start_pos = next_slice_group_param->macroblock_address / width_in_mbs;
2061 h_next_start_pos = 0;
2062 v_next_start_pos = height_in_mbs;
2065 gen75_mfc_mpeg2_slicegroup_state(ctx,
2072 next_slice_group_param == NULL,
2073 slice_param->is_intra_slice,
2074 slice_param->quantiser_scale_code,
2077 if (slice_index == 0)
2078 intel_mfc_mpeg2_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
2080 for (i = 0; i < encode_state->slice_params_ext[slice_index]->num_elements; i++) {
2081 /* PAK for each macroblocks */
2082 for (j = 0; j < slice_param->num_macroblocks; j++) {
2083 int h_pos = (slice_param->macroblock_address + j) % width_in_mbs;
2084 int v_pos = (slice_param->macroblock_address + j) / width_in_mbs;
2085 int first_mb_in_slice = (j == 0);
2086 int last_mb_in_slice = (j == slice_param->num_macroblocks - 1);
2087 int first_mb_in_slice_group = (i == 0 && j == 0);
2088 int last_mb_in_slice_group = (i == encode_state->slice_params_ext[slice_index]->num_elements - 1 &&
2089 j == slice_param->num_macroblocks - 1);
2091 if (slice_param->is_intra_slice) {
2092 gen75_mfc_mpeg2_pak_object_intra(ctx,
2097 first_mb_in_slice_group,
2098 last_mb_in_slice_group,
2100 slice_param->quantiser_scale_code,
2111 if (next_slice_group_param == NULL &&
2112 i == encode_state->slice_params_ext[slice_index]->num_elements - 1) { /* end of a picture */
2113 mfc_context->insert_object(ctx,
2123 } else { /* end of a lsice */
2124 mfc_context->insert_object(ctx,
2141 * A batch buffer for all slices, including slice state,
2142 * slice insert object and slice pak object commands
2146 gen75_mfc_mpeg2_software_slice_batchbuffer(VADriverContextP ctx,
2147 struct encode_state *encode_state,
2148 struct intel_encoder_context *encoder_context)
2150 struct i965_driver_data *i965 = i965_driver_data(ctx);
2151 struct intel_batchbuffer *batch;
2152 VAEncSequenceParameterBufferMPEG2 *seq_param = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
2153 VAEncSliceParameterBufferMPEG2 *next_slice_group_param = NULL;
2157 int width_in_mbs = ALIGN(seq_param->picture_width, 16) / 16;
2158 int height_in_mbs = ALIGN(seq_param->picture_height, 16) / 16;
2160 buffer_size = width_in_mbs * height_in_mbs * 64;
2161 batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, buffer_size);
2162 batch_bo = batch->buffer;
2164 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
2165 if (i == encode_state->num_slice_params_ext - 1)
2166 next_slice_group_param = NULL;
2168 next_slice_group_param = (VAEncSliceParameterBufferMPEG2 *)encode_state->slice_params_ext[i + 1]->buffer;
2170 gen75_mfc_mpeg2_pipeline_slice_group(ctx, encode_state, encoder_context, i, next_slice_group_param, batch);
2173 intel_batchbuffer_align(batch, 8);
2175 BEGIN_BCS_BATCH(batch, 2);
2176 OUT_BCS_BATCH(batch, 0);
2177 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
2178 ADVANCE_BCS_BATCH(batch);
2180 dri_bo_reference(batch_bo);
2181 intel_batchbuffer_free(batch);
2187 gen75_mfc_mpeg2_pipeline_picture_programing(VADriverContextP ctx,
2188 struct encode_state *encode_state,
2189 struct intel_encoder_context *encoder_context)
2191 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
2193 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_MPEG2, encoder_context);
2194 mfc_context->set_surface_state(ctx, encoder_context);
2195 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
2196 gen75_mfc_pipe_buf_addr_state(ctx, encoder_context);
2197 gen75_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
2198 gen75_mfc_mpeg2_pic_state(ctx, encoder_context, encode_state);
2199 gen75_mfc_mpeg2_qm_state(ctx, encoder_context);
2200 gen75_mfc_mpeg2_fqm_state(ctx, encoder_context);
2204 gen75_mfc_mpeg2_pipeline_programing(VADriverContextP ctx,
2205 struct encode_state *encode_state,
2206 struct intel_encoder_context *encoder_context)
2208 struct intel_batchbuffer *batch = encoder_context->base.batch;
2209 dri_bo *slice_batch_bo;
2211 slice_batch_bo = gen75_mfc_mpeg2_software_slice_batchbuffer(ctx, encode_state, encoder_context);
2214 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
2215 intel_batchbuffer_emit_mi_flush(batch);
2217 // picture level programing
2218 gen75_mfc_mpeg2_pipeline_picture_programing(ctx, encode_state, encoder_context);
2220 BEGIN_BCS_BATCH(batch, 2);
2221 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
2222 OUT_BCS_RELOC(batch,
2224 I915_GEM_DOMAIN_COMMAND, 0,
2226 ADVANCE_BCS_BATCH(batch);
2229 intel_batchbuffer_end_atomic(batch);
2231 dri_bo_unreference(slice_batch_bo);
2235 intel_mfc_mpeg2_prepare(VADriverContextP ctx,
2236 struct encode_state *encode_state,
2237 struct intel_encoder_context *encoder_context)
2239 struct i965_driver_data *i965 = i965_driver_data(ctx);
2240 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
2241 struct object_surface *obj_surface;
2242 struct object_buffer *obj_buffer;
2243 VAEncPictureParameterBufferMPEG2 *pic_param = (VAEncPictureParameterBufferMPEG2 *)encode_state->pic_param_ext->buffer;
2244 VACodedBufferSegment *coded_buffer_segment;
2245 unsigned char *flag = NULL;
2246 VAStatus vaStatus = VA_STATUS_SUCCESS;
2250 /* reconstructed surface */
2251 obj_surface = SURFACE(pic_param->reconstructed_picture);
2252 assert(obj_surface);
2253 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
2254 mfc_context->post_deblocking_output.bo = obj_surface->bo;
2255 dri_bo_reference(mfc_context->post_deblocking_output.bo);
2256 mfc_context->surface_state.width = obj_surface->orig_width;
2257 mfc_context->surface_state.height = obj_surface->orig_height;
2258 mfc_context->surface_state.w_pitch = obj_surface->width;
2259 mfc_context->surface_state.h_pitch = obj_surface->height;
2261 /* forward reference */
2262 obj_surface = SURFACE(pic_param->forward_reference_picture);
2264 if (obj_surface && obj_surface->bo) {
2265 mfc_context->reference_surfaces[0].bo = obj_surface->bo;
2266 dri_bo_reference(mfc_context->reference_surfaces[0].bo);
2268 mfc_context->reference_surfaces[0].bo = NULL;
2270 /* backward reference */
2271 obj_surface = SURFACE(pic_param->backward_reference_picture);
2273 if (obj_surface && obj_surface->bo) {
2274 mfc_context->reference_surfaces[1].bo = obj_surface->bo;
2275 dri_bo_reference(mfc_context->reference_surfaces[1].bo);
2277 mfc_context->reference_surfaces[1].bo = mfc_context->reference_surfaces[0].bo;
2279 if (mfc_context->reference_surfaces[1].bo)
2280 dri_bo_reference(mfc_context->reference_surfaces[1].bo);
2283 for (i = 2; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
2284 mfc_context->reference_surfaces[i].bo = mfc_context->reference_surfaces[i & 1].bo;
2286 if (mfc_context->reference_surfaces[i].bo)
2287 dri_bo_reference(mfc_context->reference_surfaces[i].bo);
2290 /* input YUV surface */
2291 obj_surface = SURFACE(encoder_context->input_yuv_surface);
2292 assert(obj_surface && obj_surface->bo);
2293 mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
2294 dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
2297 obj_buffer = BUFFER(pic_param->coded_buf);
2298 bo = obj_buffer->buffer_store->bo;
2300 mfc_context->mfc_indirect_pak_bse_object.bo = bo;
2301 mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_SIZE;
2302 mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000);
2303 dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
2305 /* set the internal flag to 0 to indicate the coded size is unknown */
2307 coded_buffer_segment = (VACodedBufferSegment *)bo->virtual;
2308 flag = (unsigned char *)(coded_buffer_segment + 1);
2316 gen75_mfc_mpeg2_encode_picture(VADriverContextP ctx,
2317 struct encode_state *encode_state,
2318 struct intel_encoder_context *encoder_context)
2320 gen75_mfc_init(ctx, encode_state, encoder_context);
2321 intel_mfc_mpeg2_prepare(ctx, encode_state, encoder_context);
2322 /*Programing bcs pipeline*/
2323 gen75_mfc_mpeg2_pipeline_programing(ctx, encode_state, encoder_context);
2324 gen75_mfc_run(ctx, encode_state, encoder_context);
2326 return VA_STATUS_SUCCESS;
2330 gen75_mfc_context_destroy(void *context)
2332 struct gen6_mfc_context *mfc_context = context;
2335 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
2336 mfc_context->post_deblocking_output.bo = NULL;
2338 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
2339 mfc_context->pre_deblocking_output.bo = NULL;
2341 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
2342 mfc_context->uncompressed_picture_source.bo = NULL;
2344 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
2345 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
2347 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
2348 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
2349 mfc_context->direct_mv_buffers[i].bo = NULL;
2352 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
2353 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
2355 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
2356 mfc_context->macroblock_status_buffer.bo = NULL;
2358 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
2359 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2361 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
2362 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2365 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
2366 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
2367 mfc_context->reference_surfaces[i].bo = NULL;
2370 i965_gpe_context_destroy(&mfc_context->gpe_context);
2372 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
2373 mfc_context->mfc_batchbuffer_surface.bo = NULL;
2375 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
2376 mfc_context->aux_batchbuffer_surface.bo = NULL;
2378 if (mfc_context->aux_batchbuffer)
2379 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
2381 mfc_context->aux_batchbuffer = NULL;
2386 static VAStatus gen75_mfc_pipeline(VADriverContextP ctx,
2388 struct encode_state *encode_state,
2389 struct intel_encoder_context *encoder_context)
2394 case VAProfileH264Baseline:
2395 case VAProfileH264Main:
2396 case VAProfileH264High:
2397 vaStatus = gen75_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
2400 /* FIXME: add for other profile */
2401 case VAProfileMPEG2Simple:
2402 case VAProfileMPEG2Main:
2403 vaStatus = gen75_mfc_mpeg2_encode_picture(ctx, encode_state, encoder_context);
2407 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
2414 Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
2416 struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
2418 mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
2420 mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
2421 mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
2423 mfc_context->gpe_context.curbe.length = 32 * 4;
2425 mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
2426 mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
2427 mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
2428 mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
2429 mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
2431 i965_gpe_load_kernels(ctx,
2432 &mfc_context->gpe_context,
2436 mfc_context->pipe_mode_select = gen75_mfc_pipe_mode_select;
2437 mfc_context->set_surface_state = gen75_mfc_surface_state;
2438 mfc_context->ind_obj_base_addr_state = gen75_mfc_ind_obj_base_addr_state;
2439 mfc_context->avc_img_state = gen75_mfc_avc_img_state;
2440 mfc_context->avc_qm_state = gen75_mfc_avc_qm_state;
2441 mfc_context->avc_fqm_state = gen75_mfc_avc_fqm_state;
2442 mfc_context->insert_object = gen75_mfc_avc_insert_object;
2443 mfc_context->buffer_suface_setup = gen7_gpe_buffer_suface_setup;
2445 encoder_context->mfc_context = mfc_context;
2446 encoder_context->mfc_context_destroy = gen75_mfc_context_destroy;
2447 encoder_context->mfc_pipeline = gen75_mfc_pipeline;
2448 encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;