2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
37 #include "i965_defines.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32)
44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32)
45 #define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32)
48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32)
49 #define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
51 #define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
52 #define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
53 #define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
55 #define CURBE_ALLOCATION_SIZE 37 /* in 256-bit */
56 #define CURBE_TOTAL_DATA_LENGTH (4 * 32) /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
57 #define CURBE_URB_ENTRY_LENGTH 4 /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
59 enum VIDEO_CODING_TYPE{
64 enum AVC_VME_KERNEL_TYPE{
65 AVC_VME_INTRA_SHADER = 0,
71 static const uint32_t gen6_vme_intra_frame[][4] = {
72 #include "shaders/vme/intra_frame.g6b"
75 static const uint32_t gen6_vme_inter_frame[][4] = {
76 #include "shaders/vme/inter_frame.g6b"
79 static const uint32_t gen6_vme_batchbuffer[][4] = {
80 #include "shaders/vme/batchbuffer.g6b"
83 static struct i965_kernel gen6_vme_kernels[] = {
85 "AVC VME Intra Frame",
86 AVC_VME_INTRA_SHADER, /*index*/
88 sizeof(gen6_vme_intra_frame),
92 "AVC VME inter Frame",
95 sizeof(gen6_vme_inter_frame),
99 "AVC VME BATCHBUFFER",
101 gen6_vme_batchbuffer,
102 sizeof(gen6_vme_batchbuffer),
107 /* only used for VME source surface state */
109 gen6_vme_source_surface_state(VADriverContextP ctx,
111 struct object_surface *obj_surface,
112 struct intel_encoder_context *encoder_context)
114 struct gen6_vme_context *vme_context = encoder_context->vme_context;
116 vme_context->vme_surface2_setup(ctx,
117 &vme_context->gpe_context,
119 BINDING_TABLE_OFFSET(index),
120 SURFACE_STATE_OFFSET(index));
124 gen6_vme_media_source_surface_state(VADriverContextP ctx,
126 struct object_surface *obj_surface,
127 struct intel_encoder_context *encoder_context)
129 struct gen6_vme_context *vme_context = encoder_context->vme_context;
131 vme_context->vme_media_rw_surface_setup(ctx,
132 &vme_context->gpe_context,
134 BINDING_TABLE_OFFSET(index),
135 SURFACE_STATE_OFFSET(index));
139 gen6_vme_output_buffer_setup(VADriverContextP ctx,
140 struct encode_state *encode_state,
142 struct intel_encoder_context *encoder_context)
145 struct i965_driver_data *i965 = i965_driver_data(ctx);
146 struct gen6_vme_context *vme_context = encoder_context->vme_context;
147 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
148 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
149 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
150 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
151 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
153 vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
154 vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
157 vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
159 vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
161 vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
163 vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
165 assert(vme_context->vme_output.bo);
166 vme_context->vme_buffer_suface_setup(ctx,
167 &vme_context->gpe_context,
168 &vme_context->vme_output,
169 BINDING_TABLE_OFFSET(index),
170 SURFACE_STATE_OFFSET(index));
174 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
175 struct encode_state *encode_state,
177 struct intel_encoder_context *encoder_context)
180 struct i965_driver_data *i965 = i965_driver_data(ctx);
181 struct gen6_vme_context *vme_context = encoder_context->vme_context;
182 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
183 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
184 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
186 vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
187 vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
188 vme_context->vme_batchbuffer.pitch = 16;
189 vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
191 vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
193 vme_context->vme_buffer_suface_setup(ctx,
194 &vme_context->gpe_context,
195 &vme_context->vme_batchbuffer,
196 BINDING_TABLE_OFFSET(index),
197 SURFACE_STATE_OFFSET(index));
201 gen6_vme_surface_setup(VADriverContextP ctx,
202 struct encode_state *encode_state,
204 struct intel_encoder_context *encoder_context)
206 struct object_surface *obj_surface;
208 /*Setup surfaces state*/
209 /* current picture for encoding */
210 obj_surface = encode_state->input_yuv_object;
211 gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
212 gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
216 obj_surface = encode_state->reference_objects[0];
218 if (obj_surface && obj_surface->bo)
219 gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
222 obj_surface = encode_state->reference_objects[1];
224 if (obj_surface && obj_surface->bo)
225 gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
229 gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
230 gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
232 return VA_STATUS_SUCCESS;
235 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
236 struct encode_state *encode_state,
237 struct intel_encoder_context *encoder_context)
239 struct gen6_vme_context *vme_context = encoder_context->vme_context;
240 struct gen6_interface_descriptor_data *desc;
244 bo = vme_context->gpe_context.idrt.bo;
249 for (i = 0; i < vme_context->vme_kernel_sum; i++) {
250 struct i965_kernel *kernel;
251 kernel = &vme_context->gpe_context.kernels[i];
252 assert(sizeof(*desc) == 32);
253 /*Setup the descritor table*/
254 memset(desc, 0, sizeof(*desc));
255 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
256 desc->desc2.sampler_count = 1; /* FIXME: */
257 desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
258 desc->desc3.binding_table_entry_count = 1; /* FIXME: */
259 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
260 desc->desc4.constant_urb_entry_read_offset = 0;
261 desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
264 dri_bo_emit_reloc(bo,
265 I915_GEM_DOMAIN_INSTRUCTION, 0,
267 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
269 /*Sampler State(VME state pointer)*/
270 dri_bo_emit_reloc(bo,
271 I915_GEM_DOMAIN_INSTRUCTION, 0,
273 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
274 vme_context->vme_state.bo);
279 return VA_STATUS_SUCCESS;
282 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
283 struct encode_state *encode_state,
284 struct intel_encoder_context *encoder_context)
286 struct gen6_vme_context *vme_context = encoder_context->vme_context;
287 // unsigned char *constant_buffer;
288 unsigned int *vme_state_message;
290 if (vme_context->h264_level >= 30) {
292 if (vme_context->h264_level >= 31)
296 dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
297 assert(vme_context->gpe_context.curbe.bo->virtual);
298 // constant_buffer = vme_context->curbe.bo->virtual;
299 vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual;
300 vme_state_message[31] = mv_num;
302 /*TODO copy buffer into CURB*/
304 dri_bo_unmap( vme_context->gpe_context.curbe.bo);
306 return VA_STATUS_SUCCESS;
309 static const unsigned int intra_mb_mode_cost_table[] = {
310 0x31110001, // for qp0
311 0x09110001, // for qp1
312 0x15030001, // for qp2
313 0x0b030001, // for qp3
314 0x0d030011, // for qp4
315 0x17210011, // for qp5
316 0x41210011, // for qp6
317 0x19210011, // for qp7
318 0x25050003, // for qp8
319 0x1b130003, // for qp9
320 0x1d130003, // for qp10
321 0x27070021, // for qp11
322 0x51310021, // for qp12
323 0x29090021, // for qp13
324 0x35150005, // for qp14
325 0x2b0b0013, // for qp15
326 0x2d0d0013, // for qp16
327 0x37170007, // for qp17
328 0x61410031, // for qp18
329 0x39190009, // for qp19
330 0x45250015, // for qp20
331 0x3b1b000b, // for qp21
332 0x3d1d000d, // for qp22
333 0x47270017, // for qp23
334 0x71510041, // for qp24 ! center for qp=0..30
335 0x49290019, // for qp25
336 0x55350025, // for qp26
337 0x4b2b001b, // for qp27
338 0x4d2d001d, // for qp28
339 0x57370027, // for qp29
340 0x81610051, // for qp30
341 0x57270017, // for qp31
342 0x81510041, // for qp32 ! center for qp=31..51
343 0x59290019, // for qp33
344 0x65350025, // for qp34
345 0x5b2b001b, // for qp35
346 0x5d2d001d, // for qp36
347 0x67370027, // for qp37
348 0x91610051, // for qp38
349 0x69390029, // for qp39
350 0x75450035, // for qp40
351 0x6b3b002b, // for qp41
352 0x6d3d002d, // for qp42
353 0x77470037, // for qp43
354 0xa1710061, // for qp44
355 0x79490039, // for qp45
356 0x85550045, // for qp46
357 0x7b4b003b, // for qp47
358 0x7d4d003d, // for qp48
359 0x87570047, // for qp49
360 0xb1810071, // for qp50
361 0x89590049 // for qp51
364 static void gen6_vme_state_setup_fixup(VADriverContextP ctx,
365 struct encode_state *encode_state,
366 struct intel_encoder_context *encoder_context,
367 unsigned int *vme_state_message)
369 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
370 VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
371 VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
373 if (slice_param->slice_type != SLICE_TYPE_I &&
374 slice_param->slice_type != SLICE_TYPE_SI)
377 if (encoder_context->rate_control_mode == VA_RC_CQP)
378 vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
380 vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY];
383 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
384 struct encode_state *encode_state,
386 struct intel_encoder_context *encoder_context)
388 struct gen6_vme_context *vme_context = encoder_context->vme_context;
389 unsigned int *vme_state_message;
392 //building VME state message
393 dri_bo_map(vme_context->vme_state.bo, 1);
394 assert(vme_context->vme_state.bo->virtual);
395 vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
397 vme_state_message[0] = 0x01010101;
398 vme_state_message[1] = 0x10010101;
399 vme_state_message[2] = 0x0F0F0F0F;
400 vme_state_message[3] = 0x100F0F0F;
401 vme_state_message[4] = 0x01010101;
402 vme_state_message[5] = 0x10010101;
403 vme_state_message[6] = 0x0F0F0F0F;
404 vme_state_message[7] = 0x100F0F0F;
405 vme_state_message[8] = 0x01010101;
406 vme_state_message[9] = 0x10010101;
407 vme_state_message[10] = 0x0F0F0F0F;
408 vme_state_message[11] = 0x000F0F0F;
409 vme_state_message[12] = 0x00;
410 vme_state_message[13] = 0x00;
412 vme_state_message[14] = 0x4a4a;
413 vme_state_message[15] = 0x0;
414 vme_state_message[16] = 0x4a4a4a4a;
415 vme_state_message[17] = 0x4a4a4a4a;
416 vme_state_message[18] = 0x21110100;
417 vme_state_message[19] = 0x61514131;
419 for(i = 20; i < 32; i++) {
420 vme_state_message[i] = 0;
422 //vme_state_message[16] = 0x42424242; //cost function LUT set 0 for Intra
424 gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
426 dri_bo_unmap( vme_context->vme_state.bo);
427 return VA_STATUS_SUCCESS;
431 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
432 struct encode_state *encode_state,
433 int mb_width, int mb_height,
435 int transform_8x8_mode_flag,
436 struct intel_encoder_context *encoder_context)
438 struct gen6_vme_context *vme_context = encoder_context->vme_context;
440 int mb_x = 0, mb_y = 0;
442 unsigned int *command_ptr;
444 dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
445 command_ptr = vme_context->vme_batchbuffer.bo->virtual;
447 for (s = 0; s < encode_state->num_slice_params_ext; s++) {
448 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
449 int slice_mb_begin = pSliceParameter->macroblock_address;
450 int slice_mb_number = pSliceParameter->num_macroblocks;
452 for (i = 0; i < slice_mb_number; ) {
453 int mb_count = i + slice_mb_begin;
454 mb_x = mb_count % mb_width;
455 mb_y = mb_count / mb_width;
457 number_mb_cmds = mb_width; // we must mark the slice edge.
458 } else if ( (i + 128 ) <= slice_mb_number) {
459 number_mb_cmds = 128;
461 number_mb_cmds = slice_mb_number - i;
464 *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
465 *command_ptr++ = kernel;
472 *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
473 *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
480 *command_ptr++ = MI_BATCH_BUFFER_END;
482 dri_bo_unmap(vme_context->vme_batchbuffer.bo);
485 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
487 struct i965_driver_data *i965 = i965_driver_data(ctx);
488 struct gen6_vme_context *vme_context = encoder_context->vme_context;
491 i965_gpe_context_init(ctx, &vme_context->gpe_context);
493 /* VME output buffer */
494 dri_bo_unreference(vme_context->vme_output.bo);
495 vme_context->vme_output.bo = NULL;
497 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
498 vme_context->vme_batchbuffer.bo = NULL;
501 dri_bo_unreference(vme_context->vme_state.bo);
502 bo = dri_bo_alloc(i965->intel.bufmgr,
506 vme_context->vme_state.bo = bo;
509 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
510 struct encode_state *encode_state,
511 struct intel_encoder_context *encoder_context)
513 struct gen6_vme_context *vme_context = encoder_context->vme_context;
514 struct intel_batchbuffer *batch = encoder_context->base.batch;
515 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
516 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
517 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
518 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
519 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
520 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
522 gen6_vme_fill_vme_batchbuffer(ctx,
524 width_in_mbs, height_in_mbs,
525 is_intra ? AVC_VME_INTRA_SHADER : AVC_VME_INTER_SHADER,
526 pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
529 intel_batchbuffer_start_atomic(batch, 0x1000);
530 gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
531 BEGIN_BATCH(batch, 2);
532 OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
534 vme_context->vme_batchbuffer.bo,
535 I915_GEM_DOMAIN_COMMAND, 0,
537 ADVANCE_BATCH(batch);
539 intel_batchbuffer_end_atomic(batch);
542 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
543 struct encode_state *encode_state,
544 struct intel_encoder_context *encoder_context)
546 VAStatus vaStatus = VA_STATUS_SUCCESS;
547 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
548 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
549 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
550 struct gen6_vme_context *vme_context = encoder_context->vme_context;
552 if (!vme_context->h264_level ||
553 (vme_context->h264_level != pSequenceParameter->level_idc)) {
554 vme_context->h264_level = pSequenceParameter->level_idc;
556 /*Setup all the memory object*/
557 gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
558 gen6_vme_interface_setup(ctx, encode_state, encoder_context);
559 gen6_vme_constant_setup(ctx, encode_state, encoder_context);
560 gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
562 /*Programing media pipeline*/
563 gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
568 static VAStatus gen6_vme_run(VADriverContextP ctx,
569 struct encode_state *encode_state,
570 struct intel_encoder_context *encoder_context)
572 struct intel_batchbuffer *batch = encoder_context->base.batch;
574 intel_batchbuffer_flush(batch);
576 return VA_STATUS_SUCCESS;
579 static VAStatus gen6_vme_stop(VADriverContextP ctx,
580 struct encode_state *encode_state,
581 struct intel_encoder_context *encoder_context)
583 return VA_STATUS_SUCCESS;
587 gen6_vme_pipeline(VADriverContextP ctx,
589 struct encode_state *encode_state,
590 struct intel_encoder_context *encoder_context)
592 gen6_vme_media_init(ctx, encoder_context);
593 gen6_vme_prepare(ctx, encode_state, encoder_context);
594 gen6_vme_run(ctx, encode_state, encoder_context);
595 gen6_vme_stop(ctx, encode_state, encoder_context);
597 return VA_STATUS_SUCCESS;
601 gen6_vme_context_destroy(void *context)
603 struct gen6_vme_context *vme_context = context;
605 i965_gpe_context_destroy(&vme_context->gpe_context);
607 dri_bo_unreference(vme_context->vme_output.bo);
608 vme_context->vme_output.bo = NULL;
610 dri_bo_unreference(vme_context->vme_state.bo);
611 vme_context->vme_state.bo = NULL;
613 dri_bo_unreference(vme_context->vme_batchbuffer.bo);
614 vme_context->vme_batchbuffer.bo = NULL;
619 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
621 struct gen6_vme_context *vme_context = NULL;
623 if (encoder_context->profile != VAProfileH264Baseline &&
624 encoder_context->profile != VAProfileH264Main &&
625 encoder_context->profile != VAProfileH264High) {
631 vme_context = calloc(1, sizeof(struct gen6_vme_context));
632 vme_context->gpe_context.surface_state_binding_table.length =
633 (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
635 vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
636 vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
637 vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
639 vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
640 vme_context->gpe_context.vfe_state.num_urb_entries = 16;
641 vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
642 vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
643 vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
645 vme_context->video_coding_type = VIDEO_CODING_AVC;
646 vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM;
647 i965_gpe_load_kernels(ctx,
648 &vme_context->gpe_context,
650 vme_context->vme_kernel_sum);
652 encoder_context->vme_pipeline = gen6_vme_pipeline;
653 vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
654 vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
655 vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
657 encoder_context->vme_context = vme_context;
658 encoder_context->vme_context_destroy = gen6_vme_context_destroy;